1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
97 { .vendor_id = 0, /* sentinel */ },
100 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
101 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
102 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
103 #define BNXT_DEVARG_REPRESENTOR "representor"
104 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
105 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
106 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
107 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
108 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
109 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
111 static const char *const bnxt_dev_args[] = {
112 BNXT_DEVARG_REPRESENTOR,
114 BNXT_DEVARG_FLOW_XSTAT,
115 BNXT_DEVARG_MAX_NUM_KFLOWS,
116 BNXT_DEVARG_REP_BASED_PF,
117 BNXT_DEVARG_REP_IS_PF,
118 BNXT_DEVARG_REP_Q_R2F,
119 BNXT_DEVARG_REP_Q_F2R,
120 BNXT_DEVARG_REP_FC_R2F,
121 BNXT_DEVARG_REP_FC_F2R,
126 * truflow == false to disable the feature
127 * truflow == true to enable the feature
129 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
132 * flow_xstat == false to disable the feature
133 * flow_xstat == true to enable the feature
135 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
138 * rep_is_pf == false to indicate VF representor
139 * rep_is_pf == true to indicate PF representor
141 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
144 * rep_based_pf == Physical index of the PF
146 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
148 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
150 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
153 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
155 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
158 * rep_fc_r2f == Flow control for the representor to endpoint direction
160 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
163 * rep_fc_f2r == Flow control for the endpoint to representor direction
165 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
167 int bnxt_cfa_code_dynfield_offset = -1;
170 * max_num_kflows must be >= 32
171 * and must be a power-of-2 supported value
172 * return: 1 -> invalid
175 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
177 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
182 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
183 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
184 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
185 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
186 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
187 static int bnxt_restore_vlan_filters(struct bnxt *bp);
188 static void bnxt_dev_recover(void *arg);
189 static void bnxt_free_error_recovery_info(struct bnxt *bp);
190 static void bnxt_free_rep_info(struct bnxt *bp);
192 int is_bnxt_in_error(struct bnxt *bp)
194 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
196 if (bp->flags & BNXT_FLAG_FW_RESET)
202 /***********************/
205 * High level utility functions
208 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
210 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
211 BNXT_RSS_TBL_SIZE_P5);
213 if (!BNXT_CHIP_P5(bp))
216 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
217 BNXT_RSS_ENTRIES_PER_CTX_P5) /
218 BNXT_RSS_ENTRIES_PER_CTX_P5;
221 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
223 if (!BNXT_CHIP_P5(bp))
224 return HW_HASH_INDEX_SIZE;
226 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
229 static void bnxt_free_parent_info(struct bnxt *bp)
231 rte_free(bp->parent);
234 static void bnxt_free_pf_info(struct bnxt *bp)
239 static void bnxt_free_link_info(struct bnxt *bp)
241 rte_free(bp->link_info);
244 static void bnxt_free_leds_info(struct bnxt *bp)
253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
255 rte_free(bp->flow_stat);
256 bp->flow_stat = NULL;
259 static void bnxt_free_cos_queues(struct bnxt *bp)
261 rte_free(bp->rx_cos_queue);
262 rte_free(bp->tx_cos_queue);
265 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
267 bnxt_free_filter_mem(bp);
268 bnxt_free_vnic_attributes(bp);
269 bnxt_free_vnic_mem(bp);
271 /* tx/rx rings are configured as part of *_queue_setup callbacks.
272 * If the number of rings change across fw update,
273 * we don't have much choice except to warn the user.
277 bnxt_free_tx_rings(bp);
278 bnxt_free_rx_rings(bp);
280 bnxt_free_async_cp_ring(bp);
281 bnxt_free_rxtx_nq_ring(bp);
283 rte_free(bp->grp_info);
287 static int bnxt_alloc_parent_info(struct bnxt *bp)
289 bp->parent = rte_zmalloc("bnxt_parent_info",
290 sizeof(struct bnxt_parent_info), 0);
291 if (bp->parent == NULL)
297 static int bnxt_alloc_pf_info(struct bnxt *bp)
299 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
306 static int bnxt_alloc_link_info(struct bnxt *bp)
309 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
310 if (bp->link_info == NULL)
316 static int bnxt_alloc_leds_info(struct bnxt *bp)
321 bp->leds = rte_zmalloc("bnxt_leds",
322 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
324 if (bp->leds == NULL)
330 static int bnxt_alloc_cos_queues(struct bnxt *bp)
333 rte_zmalloc("bnxt_rx_cosq",
334 BNXT_COS_QUEUE_COUNT *
335 sizeof(struct bnxt_cos_queue_info),
337 if (bp->rx_cos_queue == NULL)
341 rte_zmalloc("bnxt_tx_cosq",
342 BNXT_COS_QUEUE_COUNT *
343 sizeof(struct bnxt_cos_queue_info),
345 if (bp->tx_cos_queue == NULL)
351 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
353 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
354 sizeof(struct bnxt_flow_stat_info), 0);
355 if (bp->flow_stat == NULL)
361 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
365 rc = bnxt_alloc_ring_grps(bp);
369 rc = bnxt_alloc_async_ring_struct(bp);
373 rc = bnxt_alloc_vnic_mem(bp);
377 rc = bnxt_alloc_vnic_attributes(bp);
381 rc = bnxt_alloc_filter_mem(bp);
385 rc = bnxt_alloc_async_cp_ring(bp);
389 rc = bnxt_alloc_rxtx_nq_ring(bp);
393 if (BNXT_FLOW_XSTATS_EN(bp)) {
394 rc = bnxt_alloc_flow_stats_info(bp);
402 bnxt_free_mem(bp, reconfig);
406 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
408 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
409 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
410 uint64_t rx_offloads = dev_conf->rxmode.offloads;
411 struct bnxt_rx_queue *rxq;
415 rc = bnxt_vnic_grp_alloc(bp, vnic);
419 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
420 vnic_id, vnic, vnic->fw_grp_ids);
422 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
426 /* Alloc RSS context only if RSS mode is enabled */
427 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
428 int j, nr_ctxs = bnxt_rss_ctxts(bp);
430 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
431 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
432 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
434 "Only queues 0-%d will be in RSS table\n",
435 BNXT_RSS_TBL_SIZE_P5 - 1);
439 for (j = 0; j < nr_ctxs; j++) {
440 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
446 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
450 vnic->num_lb_ctxts = nr_ctxs;
454 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
455 * setting is not available at this time, it will not be
456 * configured correctly in the CFA.
458 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
459 vnic->vlan_strip = true;
461 vnic->vlan_strip = false;
463 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
467 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
471 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
472 rxq = bp->eth_dev->data->rx_queues[j];
475 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
476 j, rxq->vnic, rxq->vnic->fw_grp_ids);
478 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
479 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
481 vnic->rx_queue_cnt++;
484 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
486 rc = bnxt_vnic_rss_configure(bp, vnic);
490 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
492 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
493 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
495 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
499 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
504 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
508 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
509 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
514 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
515 " rx_fc_in_tbl.ctx_id = %d\n",
516 bp->flow_stat->rx_fc_in_tbl.va,
517 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
518 bp->flow_stat->rx_fc_in_tbl.ctx_id);
520 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
521 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
526 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
527 " rx_fc_out_tbl.ctx_id = %d\n",
528 bp->flow_stat->rx_fc_out_tbl.va,
529 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
530 bp->flow_stat->rx_fc_out_tbl.ctx_id);
532 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
533 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
538 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
539 " tx_fc_in_tbl.ctx_id = %d\n",
540 bp->flow_stat->tx_fc_in_tbl.va,
541 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
542 bp->flow_stat->tx_fc_in_tbl.ctx_id);
544 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
545 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
550 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
551 " tx_fc_out_tbl.ctx_id = %d\n",
552 bp->flow_stat->tx_fc_out_tbl.va,
553 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
554 bp->flow_stat->tx_fc_out_tbl.ctx_id);
556 memset(bp->flow_stat->rx_fc_out_tbl.va,
558 bp->flow_stat->rx_fc_out_tbl.size);
559 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
560 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
561 bp->flow_stat->rx_fc_out_tbl.ctx_id,
562 bp->flow_stat->max_fc,
567 memset(bp->flow_stat->tx_fc_out_tbl.va,
569 bp->flow_stat->tx_fc_out_tbl.size);
570 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
571 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
572 bp->flow_stat->tx_fc_out_tbl.ctx_id,
573 bp->flow_stat->max_fc,
579 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
580 struct bnxt_ctx_mem_buf_info *ctx)
585 ctx->va = rte_zmalloc(type, size, 0);
588 rte_mem_lock_page(ctx->va);
590 ctx->dma = rte_mem_virt2iova(ctx->va);
591 if (ctx->dma == RTE_BAD_IOVA)
597 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
599 struct rte_pci_device *pdev = bp->pdev;
600 char type[RTE_MEMZONE_NAMESIZE];
604 max_fc = bp->flow_stat->max_fc;
606 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
607 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
608 /* 4 bytes for each counter-id */
609 rc = bnxt_alloc_ctx_mem_buf(type,
611 &bp->flow_stat->rx_fc_in_tbl);
615 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
616 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
617 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
618 rc = bnxt_alloc_ctx_mem_buf(type,
620 &bp->flow_stat->rx_fc_out_tbl);
624 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
625 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
626 /* 4 bytes for each counter-id */
627 rc = bnxt_alloc_ctx_mem_buf(type,
629 &bp->flow_stat->tx_fc_in_tbl);
633 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
634 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
635 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
636 rc = bnxt_alloc_ctx_mem_buf(type,
638 &bp->flow_stat->tx_fc_out_tbl);
642 rc = bnxt_register_fc_ctx_mem(bp);
647 static int bnxt_init_ctx_mem(struct bnxt *bp)
651 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
652 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
653 !BNXT_FLOW_XSTATS_EN(bp))
656 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
660 rc = bnxt_init_fc_ctx_mem(bp);
665 static int bnxt_update_phy_setting(struct bnxt *bp)
667 struct rte_eth_link new;
670 rc = bnxt_get_hwrm_link_config(bp, &new);
672 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
677 * On BCM957508-N2100 adapters, FW will not allow any user other
678 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
679 * always returns link up. Force phy update always in that case.
681 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
682 rc = bnxt_set_hwrm_link_config(bp, true);
684 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
692 static int bnxt_init_chip(struct bnxt *bp)
694 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
695 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
696 uint32_t intr_vector = 0;
697 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
698 uint32_t vec = BNXT_MISC_VEC_ID;
702 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
703 bp->eth_dev->data->dev_conf.rxmode.offloads |=
704 DEV_RX_OFFLOAD_JUMBO_FRAME;
705 bp->flags |= BNXT_FLAG_JUMBO;
707 bp->eth_dev->data->dev_conf.rxmode.offloads &=
708 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
709 bp->flags &= ~BNXT_FLAG_JUMBO;
712 /* THOR does not support ring groups.
713 * But we will use the array to save RSS context IDs.
715 if (BNXT_CHIP_P5(bp))
716 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
718 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
720 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
724 rc = bnxt_alloc_hwrm_rings(bp);
726 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
730 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
732 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
736 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
739 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
740 if (bp->rx_cos_queue[i].id != 0xff) {
741 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
745 "Num pools more than FW profile\n");
749 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
755 rc = bnxt_mq_rx_configure(bp);
757 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
761 /* VNIC configuration */
762 for (i = 0; i < bp->nr_vnics; i++) {
763 rc = bnxt_setup_one_vnic(bp, i);
768 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
771 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
775 /* check and configure queue intr-vector mapping */
776 if ((rte_intr_cap_multiple(intr_handle) ||
777 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
778 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
779 intr_vector = bp->eth_dev->data->nb_rx_queues;
780 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
781 if (intr_vector > bp->rx_cp_nr_rings) {
782 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
786 rc = rte_intr_efd_enable(intr_handle, intr_vector);
791 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
792 intr_handle->intr_vec =
793 rte_zmalloc("intr_vec",
794 bp->eth_dev->data->nb_rx_queues *
796 if (intr_handle->intr_vec == NULL) {
797 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
798 " intr_vec", bp->eth_dev->data->nb_rx_queues);
802 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
803 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
804 intr_handle->intr_vec, intr_handle->nb_efd,
805 intr_handle->max_intr);
806 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
808 intr_handle->intr_vec[queue_id] =
809 vec + BNXT_RX_VEC_START;
810 if (vec < base + intr_handle->nb_efd - 1)
815 /* enable uio/vfio intr/eventfd mapping */
816 rc = rte_intr_enable(intr_handle);
817 #ifndef RTE_EXEC_ENV_FREEBSD
818 /* In FreeBSD OS, nic_uio driver does not support interrupts */
823 rc = bnxt_update_phy_setting(bp);
827 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
829 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
834 rte_free(intr_handle->intr_vec);
836 rte_intr_efd_disable(intr_handle);
838 /* Some of the error status returned by FW may not be from errno.h */
845 static int bnxt_shutdown_nic(struct bnxt *bp)
847 bnxt_free_all_hwrm_resources(bp);
848 bnxt_free_all_filters(bp);
849 bnxt_free_all_vnics(bp);
854 * Device configuration and status function
857 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
859 uint32_t link_speed = bp->link_info->support_speeds;
860 uint32_t speed_capa = 0;
862 /* If PAM4 is configured, use PAM4 supported speed */
863 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
864 link_speed = bp->link_info->support_pam4_speeds;
866 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
867 speed_capa |= ETH_LINK_SPEED_100M;
868 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
869 speed_capa |= ETH_LINK_SPEED_100M_HD;
870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
871 speed_capa |= ETH_LINK_SPEED_1G;
872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
873 speed_capa |= ETH_LINK_SPEED_2_5G;
874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
875 speed_capa |= ETH_LINK_SPEED_10G;
876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
877 speed_capa |= ETH_LINK_SPEED_20G;
878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
879 speed_capa |= ETH_LINK_SPEED_25G;
880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
881 speed_capa |= ETH_LINK_SPEED_40G;
882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
883 speed_capa |= ETH_LINK_SPEED_50G;
884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
885 speed_capa |= ETH_LINK_SPEED_100G;
886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
887 speed_capa |= ETH_LINK_SPEED_50G;
888 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
889 speed_capa |= ETH_LINK_SPEED_100G;
890 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
891 speed_capa |= ETH_LINK_SPEED_200G;
893 if (bp->link_info->auto_mode ==
894 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
895 speed_capa |= ETH_LINK_SPEED_FIXED;
897 speed_capa |= ETH_LINK_SPEED_AUTONEG;
902 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
903 struct rte_eth_dev_info *dev_info)
905 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
906 struct bnxt *bp = eth_dev->data->dev_private;
907 uint16_t max_vnics, i, j, vpool, vrxq;
908 unsigned int max_rx_rings;
911 rc = is_bnxt_in_error(bp);
916 dev_info->max_mac_addrs = bp->max_l2_ctx;
917 dev_info->max_hash_mac_addrs = 0;
919 /* PF/VF specifics */
921 dev_info->max_vfs = pdev->max_vfs;
923 max_rx_rings = bnxt_max_rings(bp);
924 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
925 dev_info->max_rx_queues = max_rx_rings;
926 dev_info->max_tx_queues = max_rx_rings;
927 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
928 dev_info->hash_key_size = 40;
929 max_vnics = bp->max_vnics;
932 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
933 dev_info->max_mtu = BNXT_MAX_MTU;
935 /* Fast path specifics */
936 dev_info->min_rx_bufsize = 1;
937 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
939 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
940 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
941 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
942 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
943 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
944 dev_info->tx_queue_offload_capa;
945 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
947 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
950 dev_info->default_rxconf = (struct rte_eth_rxconf) {
956 .rx_free_thresh = 32,
957 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
960 dev_info->default_txconf = (struct rte_eth_txconf) {
966 .tx_free_thresh = 32,
969 eth_dev->data->dev_conf.intr_conf.lsc = 1;
971 eth_dev->data->dev_conf.intr_conf.rxq = 1;
972 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
973 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
974 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
975 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
977 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
978 dev_info->switch_info.name = eth_dev->device->name;
979 dev_info->switch_info.domain_id = bp->switch_domain_id;
980 dev_info->switch_info.port_id =
981 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
982 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
988 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
989 * need further investigation.
993 vpool = 64; /* ETH_64_POOLS */
994 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
995 for (i = 0; i < 4; vpool >>= 1, i++) {
996 if (max_vnics > vpool) {
997 for (j = 0; j < 5; vrxq >>= 1, j++) {
998 if (dev_info->max_rx_queues > vrxq) {
1004 /* Not enough resources to support VMDq */
1008 /* Not enough resources to support VMDq */
1012 dev_info->max_vmdq_pools = vpool;
1013 dev_info->vmdq_queue_num = vrxq;
1015 dev_info->vmdq_pool_base = 0;
1016 dev_info->vmdq_queue_base = 0;
1021 /* Configure the device based on the configuration provided */
1022 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1024 struct bnxt *bp = eth_dev->data->dev_private;
1025 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1028 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1029 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1030 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1031 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1033 rc = is_bnxt_in_error(bp);
1037 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1038 rc = bnxt_hwrm_check_vf_rings(bp);
1040 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1044 /* If a resource has already been allocated - in this case
1045 * it is the async completion ring, free it. Reallocate it after
1046 * resource reservation. This will ensure the resource counts
1047 * are calculated correctly.
1050 pthread_mutex_lock(&bp->def_cp_lock);
1052 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1053 bnxt_disable_int(bp);
1054 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1057 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1059 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1060 pthread_mutex_unlock(&bp->def_cp_lock);
1064 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1065 rc = bnxt_alloc_async_cp_ring(bp);
1067 pthread_mutex_unlock(&bp->def_cp_lock);
1070 bnxt_enable_int(bp);
1073 pthread_mutex_unlock(&bp->def_cp_lock);
1076 /* Inherit new configurations */
1077 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1078 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1079 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1080 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1081 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1083 goto resource_error;
1085 if (BNXT_HAS_RING_GRPS(bp) &&
1086 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1087 goto resource_error;
1089 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1090 bp->max_vnics < eth_dev->data->nb_rx_queues)
1091 goto resource_error;
1093 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1094 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1096 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1097 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1098 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1100 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1101 eth_dev->data->mtu =
1102 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1103 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1105 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1111 "Insufficient resources to support requested config\n");
1113 "Num Queues Requested: Tx %d, Rx %d\n",
1114 eth_dev->data->nb_tx_queues,
1115 eth_dev->data->nb_rx_queues);
1117 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1118 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1119 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1123 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1125 struct rte_eth_link *link = ð_dev->data->dev_link;
1127 if (link->link_status)
1128 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1129 eth_dev->data->port_id,
1130 (uint32_t)link->link_speed,
1131 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1132 ("full-duplex") : ("half-duplex\n"));
1134 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1135 eth_dev->data->port_id);
1139 * Determine whether the current configuration requires support for scattered
1140 * receive; return 1 if scattered receive is required and 0 if not.
1142 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1147 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1150 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1151 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1153 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1154 RTE_PKTMBUF_HEADROOM);
1155 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1161 static eth_rx_burst_t
1162 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1164 struct bnxt *bp = eth_dev->data->dev_private;
1166 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1167 #ifndef RTE_LIBRTE_IEEE1588
1169 * Vector mode receive can be enabled only if scatter rx is not
1170 * in use and rx offloads are limited to VLAN stripping and
1173 if (!eth_dev->data->scattered_rx &&
1174 !(eth_dev->data->dev_conf.rxmode.offloads &
1175 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1176 DEV_RX_OFFLOAD_KEEP_CRC |
1177 DEV_RX_OFFLOAD_JUMBO_FRAME |
1178 DEV_RX_OFFLOAD_IPV4_CKSUM |
1179 DEV_RX_OFFLOAD_UDP_CKSUM |
1180 DEV_RX_OFFLOAD_TCP_CKSUM |
1181 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1182 DEV_RX_OFFLOAD_RSS_HASH |
1183 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1184 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1185 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1186 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1187 eth_dev->data->port_id);
1188 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1189 return bnxt_recv_pkts_vec;
1191 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1192 eth_dev->data->port_id);
1194 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1195 eth_dev->data->port_id,
1196 eth_dev->data->scattered_rx,
1197 eth_dev->data->dev_conf.rxmode.offloads);
1200 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1201 return bnxt_recv_pkts;
1204 static eth_tx_burst_t
1205 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1207 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1208 #ifndef RTE_LIBRTE_IEEE1588
1209 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1210 struct bnxt *bp = eth_dev->data->dev_private;
1213 * Vector mode transmit can be enabled only if not using scatter rx
1216 if (!eth_dev->data->scattered_rx &&
1217 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1218 !BNXT_TRUFLOW_EN(bp) &&
1219 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1220 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1221 eth_dev->data->port_id);
1222 return bnxt_xmit_pkts_vec;
1224 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1225 eth_dev->data->port_id);
1227 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1228 eth_dev->data->port_id,
1229 eth_dev->data->scattered_rx,
1233 return bnxt_xmit_pkts;
1236 static int bnxt_handle_if_change_status(struct bnxt *bp)
1240 /* Since fw has undergone a reset and lost all contexts,
1241 * set fatal flag to not issue hwrm during cleanup
1243 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1244 bnxt_uninit_resources(bp, true);
1246 /* clear fatal flag so that re-init happens */
1247 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1248 rc = bnxt_init_resources(bp, true);
1250 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1255 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1257 struct bnxt *bp = eth_dev->data->dev_private;
1258 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1260 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1262 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1263 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1267 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1269 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1270 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1273 rc = bnxt_hwrm_if_change(bp, true);
1274 if (rc == 0 || rc != -EAGAIN)
1277 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1278 } while (retry_cnt--);
1283 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1284 rc = bnxt_handle_if_change_status(bp);
1289 bnxt_enable_int(bp);
1291 rc = bnxt_init_chip(bp);
1295 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1296 eth_dev->data->dev_started = 1;
1298 bnxt_link_update_op(eth_dev, 1);
1300 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1301 vlan_mask |= ETH_VLAN_FILTER_MASK;
1302 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1303 vlan_mask |= ETH_VLAN_STRIP_MASK;
1304 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1308 /* Initialize bnxt ULP port details */
1309 rc = bnxt_ulp_port_init(bp);
1313 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1314 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1316 bnxt_schedule_fw_health_check(bp);
1321 bnxt_shutdown_nic(bp);
1322 bnxt_free_tx_mbufs(bp);
1323 bnxt_free_rx_mbufs(bp);
1324 bnxt_hwrm_if_change(bp, false);
1325 eth_dev->data->dev_started = 0;
1329 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1331 struct bnxt *bp = eth_dev->data->dev_private;
1334 if (!bp->link_info->link_up)
1335 rc = bnxt_set_hwrm_link_config(bp, true);
1337 eth_dev->data->dev_link.link_status = 1;
1339 bnxt_print_link_info(eth_dev);
1343 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1345 struct bnxt *bp = eth_dev->data->dev_private;
1347 eth_dev->data->dev_link.link_status = 0;
1348 bnxt_set_hwrm_link_config(bp, false);
1349 bp->link_info->link_up = 0;
1354 static void bnxt_free_switch_domain(struct bnxt *bp)
1358 if (bp->switch_domain_id) {
1359 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1361 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1362 bp->switch_domain_id, rc);
1366 /* Unload the driver, release resources */
1367 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1369 struct bnxt *bp = eth_dev->data->dev_private;
1370 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1371 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1372 struct rte_eth_link link;
1375 eth_dev->data->dev_started = 0;
1376 eth_dev->data->scattered_rx = 0;
1378 /* Prevent crashes when queues are still in use */
1379 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1380 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1382 bnxt_disable_int(bp);
1384 /* disable uio/vfio intr/eventfd mapping */
1385 rte_intr_disable(intr_handle);
1387 /* Stop the child representors for this device */
1388 ret = bnxt_rep_stop_all(bp);
1392 /* delete the bnxt ULP port details */
1393 bnxt_ulp_port_deinit(bp);
1395 bnxt_cancel_fw_health_check(bp);
1397 /* Do not bring link down during reset recovery */
1398 if (!is_bnxt_in_error(bp)) {
1399 bnxt_dev_set_link_down_op(eth_dev);
1400 /* Wait for link to be reset */
1401 if (BNXT_SINGLE_PF(bp))
1403 /* clear the recorded link status */
1404 memset(&link, 0, sizeof(link));
1405 rte_eth_linkstatus_set(eth_dev, &link);
1408 /* Clean queue intr-vector mapping */
1409 rte_intr_efd_disable(intr_handle);
1410 if (intr_handle->intr_vec != NULL) {
1411 rte_free(intr_handle->intr_vec);
1412 intr_handle->intr_vec = NULL;
1415 bnxt_hwrm_port_clr_stats(bp);
1416 bnxt_free_tx_mbufs(bp);
1417 bnxt_free_rx_mbufs(bp);
1418 /* Process any remaining notifications in default completion queue */
1419 bnxt_int_handler(eth_dev);
1420 bnxt_shutdown_nic(bp);
1421 bnxt_hwrm_if_change(bp, false);
1423 rte_free(bp->mark_table);
1424 bp->mark_table = NULL;
1426 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1427 bp->rx_cosq_cnt = 0;
1428 /* All filters are deleted on a port stop. */
1429 if (BNXT_FLOW_XSTATS_EN(bp))
1430 bp->flow_stat->flow_count = 0;
1435 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1437 struct bnxt *bp = eth_dev->data->dev_private;
1440 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1443 /* cancel the recovery handler before remove dev */
1444 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1445 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1446 bnxt_cancel_fc_thread(bp);
1448 if (eth_dev->data->dev_started)
1449 ret = bnxt_dev_stop_op(eth_dev);
1451 bnxt_free_switch_domain(bp);
1453 bnxt_uninit_resources(bp, false);
1455 bnxt_free_leds_info(bp);
1456 bnxt_free_cos_queues(bp);
1457 bnxt_free_link_info(bp);
1458 bnxt_free_pf_info(bp);
1459 bnxt_free_parent_info(bp);
1461 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1462 bp->tx_mem_zone = NULL;
1463 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1464 bp->rx_mem_zone = NULL;
1466 bnxt_hwrm_free_vf_info(bp);
1468 rte_free(bp->grp_info);
1469 bp->grp_info = NULL;
1474 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1477 struct bnxt *bp = eth_dev->data->dev_private;
1478 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1479 struct bnxt_vnic_info *vnic;
1480 struct bnxt_filter_info *filter, *temp_filter;
1483 if (is_bnxt_in_error(bp))
1487 * Loop through all VNICs from the specified filter flow pools to
1488 * remove the corresponding MAC addr filter
1490 for (i = 0; i < bp->nr_vnics; i++) {
1491 if (!(pool_mask & (1ULL << i)))
1494 vnic = &bp->vnic_info[i];
1495 filter = STAILQ_FIRST(&vnic->filter);
1497 temp_filter = STAILQ_NEXT(filter, next);
1498 if (filter->mac_index == index) {
1499 STAILQ_REMOVE(&vnic->filter, filter,
1500 bnxt_filter_info, next);
1501 bnxt_hwrm_clear_l2_filter(bp, filter);
1502 bnxt_free_filter(bp, filter);
1504 filter = temp_filter;
1509 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1510 struct rte_ether_addr *mac_addr, uint32_t index,
1513 struct bnxt_filter_info *filter;
1516 /* Attach requested MAC address to the new l2_filter */
1517 STAILQ_FOREACH(filter, &vnic->filter, next) {
1518 if (filter->mac_index == index) {
1520 "MAC addr already existed for pool %d\n",
1526 filter = bnxt_alloc_filter(bp);
1528 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1532 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1533 * if the MAC that's been programmed now is a different one, then,
1534 * copy that addr to filter->l2_addr
1537 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1538 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1540 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1542 filter->mac_index = index;
1543 if (filter->mac_index == 0)
1544 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1546 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1548 bnxt_free_filter(bp, filter);
1554 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1555 struct rte_ether_addr *mac_addr,
1556 uint32_t index, uint32_t pool)
1558 struct bnxt *bp = eth_dev->data->dev_private;
1559 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1562 rc = is_bnxt_in_error(bp);
1566 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1567 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1572 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1576 /* Filter settings will get applied when port is started */
1577 if (!eth_dev->data->dev_started)
1580 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1585 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1588 struct bnxt *bp = eth_dev->data->dev_private;
1589 struct rte_eth_link new;
1590 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1591 BNXT_MIN_LINK_WAIT_CNT;
1593 rc = is_bnxt_in_error(bp);
1597 memset(&new, 0, sizeof(new));
1599 /* Retrieve link info from hardware */
1600 rc = bnxt_get_hwrm_link_config(bp, &new);
1602 new.link_speed = ETH_LINK_SPEED_100M;
1603 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1605 "Failed to retrieve link rc = 0x%x!\n", rc);
1609 if (!wait_to_complete || new.link_status)
1612 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1615 /* Only single function PF can bring phy down.
1616 * When port is stopped, report link down for VF/MH/NPAR functions.
1618 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1619 memset(&new, 0, sizeof(new));
1622 /* Timed out or success */
1623 if (new.link_status != eth_dev->data->dev_link.link_status ||
1624 new.link_speed != eth_dev->data->dev_link.link_speed) {
1625 rte_eth_linkstatus_set(eth_dev, &new);
1627 rte_eth_dev_callback_process(eth_dev,
1628 RTE_ETH_EVENT_INTR_LSC,
1631 bnxt_print_link_info(eth_dev);
1637 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1639 struct bnxt *bp = eth_dev->data->dev_private;
1640 struct bnxt_vnic_info *vnic;
1644 rc = is_bnxt_in_error(bp);
1648 /* Filter settings will get applied when port is started */
1649 if (!eth_dev->data->dev_started)
1652 if (bp->vnic_info == NULL)
1655 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1657 old_flags = vnic->flags;
1658 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1659 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1661 vnic->flags = old_flags;
1666 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1668 struct bnxt *bp = eth_dev->data->dev_private;
1669 struct bnxt_vnic_info *vnic;
1673 rc = is_bnxt_in_error(bp);
1677 /* Filter settings will get applied when port is started */
1678 if (!eth_dev->data->dev_started)
1681 if (bp->vnic_info == NULL)
1684 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1686 old_flags = vnic->flags;
1687 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1688 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1690 vnic->flags = old_flags;
1695 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1697 struct bnxt *bp = eth_dev->data->dev_private;
1698 struct bnxt_vnic_info *vnic;
1702 rc = is_bnxt_in_error(bp);
1706 /* Filter settings will get applied when port is started */
1707 if (!eth_dev->data->dev_started)
1710 if (bp->vnic_info == NULL)
1713 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1715 old_flags = vnic->flags;
1716 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1717 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1719 vnic->flags = old_flags;
1724 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1726 struct bnxt *bp = eth_dev->data->dev_private;
1727 struct bnxt_vnic_info *vnic;
1731 rc = is_bnxt_in_error(bp);
1735 /* Filter settings will get applied when port is started */
1736 if (!eth_dev->data->dev_started)
1739 if (bp->vnic_info == NULL)
1742 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1744 old_flags = vnic->flags;
1745 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1746 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1748 vnic->flags = old_flags;
1753 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1754 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1756 if (qid >= bp->rx_nr_rings)
1759 return bp->eth_dev->data->rx_queues[qid];
1762 /* Return rxq corresponding to a given rss table ring/group ID. */
1763 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1765 struct bnxt_rx_queue *rxq;
1768 if (!BNXT_HAS_RING_GRPS(bp)) {
1769 for (i = 0; i < bp->rx_nr_rings; i++) {
1770 rxq = bp->eth_dev->data->rx_queues[i];
1771 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1775 for (i = 0; i < bp->rx_nr_rings; i++) {
1776 if (bp->grp_info[i].fw_grp_id == fwr)
1781 return INVALID_HW_RING_ID;
1784 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1785 struct rte_eth_rss_reta_entry64 *reta_conf,
1788 struct bnxt *bp = eth_dev->data->dev_private;
1789 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1790 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1791 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1795 rc = is_bnxt_in_error(bp);
1799 if (!vnic->rss_table)
1802 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1805 if (reta_size != tbl_size) {
1806 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1807 "(%d) must equal the size supported by the hardware "
1808 "(%d)\n", reta_size, tbl_size);
1812 for (i = 0; i < reta_size; i++) {
1813 struct bnxt_rx_queue *rxq;
1815 idx = i / RTE_RETA_GROUP_SIZE;
1816 sft = i % RTE_RETA_GROUP_SIZE;
1818 if (!(reta_conf[idx].mask & (1ULL << sft)))
1821 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1823 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1827 if (BNXT_CHIP_P5(bp)) {
1828 vnic->rss_table[i * 2] =
1829 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1830 vnic->rss_table[i * 2 + 1] =
1831 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1833 vnic->rss_table[i] =
1834 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1838 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1842 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1843 struct rte_eth_rss_reta_entry64 *reta_conf,
1846 struct bnxt *bp = eth_dev->data->dev_private;
1847 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1848 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1849 uint16_t idx, sft, i;
1852 rc = is_bnxt_in_error(bp);
1856 /* Retrieve from the default VNIC */
1859 if (!vnic->rss_table)
1862 if (reta_size != tbl_size) {
1863 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1864 "(%d) must equal the size supported by the hardware "
1865 "(%d)\n", reta_size, tbl_size);
1869 for (idx = 0, i = 0; i < reta_size; i++) {
1870 idx = i / RTE_RETA_GROUP_SIZE;
1871 sft = i % RTE_RETA_GROUP_SIZE;
1873 if (reta_conf[idx].mask & (1ULL << sft)) {
1876 if (BNXT_CHIP_P5(bp))
1877 qid = bnxt_rss_to_qid(bp,
1878 vnic->rss_table[i * 2]);
1880 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1882 if (qid == INVALID_HW_RING_ID) {
1883 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1886 reta_conf[idx].reta[sft] = qid;
1893 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1894 struct rte_eth_rss_conf *rss_conf)
1896 struct bnxt *bp = eth_dev->data->dev_private;
1897 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1898 struct bnxt_vnic_info *vnic;
1901 rc = is_bnxt_in_error(bp);
1906 * If RSS enablement were different than dev_configure,
1907 * then return -EINVAL
1909 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1910 if (!rss_conf->rss_hf)
1911 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1913 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1917 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1918 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1922 /* Update the default RSS VNIC(s) */
1923 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1924 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1926 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1927 ETH_RSS_LEVEL(rss_conf->rss_hf));
1930 * If hashkey is not specified, use the previously configured
1933 if (!rss_conf->rss_key)
1936 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1938 "Invalid hashkey length, should be 16 bytes\n");
1941 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1944 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1948 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1949 struct rte_eth_rss_conf *rss_conf)
1951 struct bnxt *bp = eth_dev->data->dev_private;
1952 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1954 uint32_t hash_types;
1956 rc = is_bnxt_in_error(bp);
1960 /* RSS configuration is the same for all VNICs */
1961 if (vnic && vnic->rss_hash_key) {
1962 if (rss_conf->rss_key) {
1963 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1964 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1965 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1968 hash_types = vnic->hash_type;
1969 rss_conf->rss_hf = 0;
1970 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1971 rss_conf->rss_hf |= ETH_RSS_IPV4;
1972 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1974 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1975 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1977 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1979 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1980 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1982 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1984 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1985 rss_conf->rss_hf |= ETH_RSS_IPV6;
1986 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1988 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1989 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1991 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1993 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1994 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1996 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2000 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2004 "Unknown RSS config from firmware (%08x), RSS disabled",
2009 rss_conf->rss_hf = 0;
2014 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2015 struct rte_eth_fc_conf *fc_conf)
2017 struct bnxt *bp = dev->data->dev_private;
2018 struct rte_eth_link link_info;
2021 rc = is_bnxt_in_error(bp);
2025 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2029 memset(fc_conf, 0, sizeof(*fc_conf));
2030 if (bp->link_info->auto_pause)
2031 fc_conf->autoneg = 1;
2032 switch (bp->link_info->pause) {
2034 fc_conf->mode = RTE_FC_NONE;
2036 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2037 fc_conf->mode = RTE_FC_TX_PAUSE;
2039 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2040 fc_conf->mode = RTE_FC_RX_PAUSE;
2042 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2043 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2044 fc_conf->mode = RTE_FC_FULL;
2050 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2051 struct rte_eth_fc_conf *fc_conf)
2053 struct bnxt *bp = dev->data->dev_private;
2056 rc = is_bnxt_in_error(bp);
2060 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2061 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2065 switch (fc_conf->mode) {
2067 bp->link_info->auto_pause = 0;
2068 bp->link_info->force_pause = 0;
2070 case RTE_FC_RX_PAUSE:
2071 if (fc_conf->autoneg) {
2072 bp->link_info->auto_pause =
2073 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2074 bp->link_info->force_pause = 0;
2076 bp->link_info->auto_pause = 0;
2077 bp->link_info->force_pause =
2078 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2081 case RTE_FC_TX_PAUSE:
2082 if (fc_conf->autoneg) {
2083 bp->link_info->auto_pause =
2084 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2085 bp->link_info->force_pause = 0;
2087 bp->link_info->auto_pause = 0;
2088 bp->link_info->force_pause =
2089 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2093 if (fc_conf->autoneg) {
2094 bp->link_info->auto_pause =
2095 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2096 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2097 bp->link_info->force_pause = 0;
2099 bp->link_info->auto_pause = 0;
2100 bp->link_info->force_pause =
2101 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2102 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2106 return bnxt_set_hwrm_link_config(bp, true);
2109 /* Add UDP tunneling port */
2111 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2112 struct rte_eth_udp_tunnel *udp_tunnel)
2114 struct bnxt *bp = eth_dev->data->dev_private;
2115 uint16_t tunnel_type = 0;
2118 rc = is_bnxt_in_error(bp);
2122 switch (udp_tunnel->prot_type) {
2123 case RTE_TUNNEL_TYPE_VXLAN:
2124 if (bp->vxlan_port_cnt) {
2125 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2126 udp_tunnel->udp_port);
2127 if (bp->vxlan_port != udp_tunnel->udp_port) {
2128 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2131 bp->vxlan_port_cnt++;
2135 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2136 bp->vxlan_port_cnt++;
2138 case RTE_TUNNEL_TYPE_GENEVE:
2139 if (bp->geneve_port_cnt) {
2140 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2141 udp_tunnel->udp_port);
2142 if (bp->geneve_port != udp_tunnel->udp_port) {
2143 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2146 bp->geneve_port_cnt++;
2150 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2151 bp->geneve_port_cnt++;
2154 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2157 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2163 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2164 struct rte_eth_udp_tunnel *udp_tunnel)
2166 struct bnxt *bp = eth_dev->data->dev_private;
2167 uint16_t tunnel_type = 0;
2171 rc = is_bnxt_in_error(bp);
2175 switch (udp_tunnel->prot_type) {
2176 case RTE_TUNNEL_TYPE_VXLAN:
2177 if (!bp->vxlan_port_cnt) {
2178 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2181 if (bp->vxlan_port != udp_tunnel->udp_port) {
2182 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2183 udp_tunnel->udp_port, bp->vxlan_port);
2186 if (--bp->vxlan_port_cnt)
2190 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2191 port = bp->vxlan_fw_dst_port_id;
2193 case RTE_TUNNEL_TYPE_GENEVE:
2194 if (!bp->geneve_port_cnt) {
2195 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2198 if (bp->geneve_port != udp_tunnel->udp_port) {
2199 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2200 udp_tunnel->udp_port, bp->geneve_port);
2203 if (--bp->geneve_port_cnt)
2207 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2208 port = bp->geneve_fw_dst_port_id;
2211 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2215 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2219 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2221 struct bnxt_filter_info *filter;
2222 struct bnxt_vnic_info *vnic;
2224 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2226 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2227 filter = STAILQ_FIRST(&vnic->filter);
2229 /* Search for this matching MAC+VLAN filter */
2230 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2231 /* Delete the filter */
2232 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2235 STAILQ_REMOVE(&vnic->filter, filter,
2236 bnxt_filter_info, next);
2237 bnxt_free_filter(bp, filter);
2239 "Deleted vlan filter for %d\n",
2243 filter = STAILQ_NEXT(filter, next);
2248 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2250 struct bnxt_filter_info *filter;
2251 struct bnxt_vnic_info *vnic;
2253 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2254 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2255 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2257 /* Implementation notes on the use of VNIC in this command:
2259 * By default, these filters belong to default vnic for the function.
2260 * Once these filters are set up, only destination VNIC can be modified.
2261 * If the destination VNIC is not specified in this command,
2262 * then the HWRM shall only create an l2 context id.
2265 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2266 filter = STAILQ_FIRST(&vnic->filter);
2267 /* Check if the VLAN has already been added */
2269 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2272 filter = STAILQ_NEXT(filter, next);
2275 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2276 * command to create MAC+VLAN filter with the right flags, enables set.
2278 filter = bnxt_alloc_filter(bp);
2281 "MAC/VLAN filter alloc failed\n");
2284 /* MAC + VLAN ID filter */
2285 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2286 * untagged packets are received
2288 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2289 * packets and only the programmed vlan's packets are received
2291 filter->l2_ivlan = vlan_id;
2292 filter->l2_ivlan_mask = 0x0FFF;
2293 filter->enables |= en;
2294 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2296 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2298 /* Free the newly allocated filter as we were
2299 * not able to create the filter in hardware.
2301 bnxt_free_filter(bp, filter);
2305 filter->mac_index = 0;
2306 /* Add this new filter to the list */
2308 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2310 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2313 "Added Vlan filter for %d\n", vlan_id);
2317 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2318 uint16_t vlan_id, int on)
2320 struct bnxt *bp = eth_dev->data->dev_private;
2323 rc = is_bnxt_in_error(bp);
2327 if (!eth_dev->data->dev_started) {
2328 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2332 /* These operations apply to ALL existing MAC/VLAN filters */
2334 return bnxt_add_vlan_filter(bp, vlan_id);
2336 return bnxt_del_vlan_filter(bp, vlan_id);
2339 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2340 struct bnxt_vnic_info *vnic)
2342 struct bnxt_filter_info *filter;
2345 filter = STAILQ_FIRST(&vnic->filter);
2347 if (filter->mac_index == 0 &&
2348 !memcmp(filter->l2_addr, bp->mac_addr,
2349 RTE_ETHER_ADDR_LEN)) {
2350 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2352 STAILQ_REMOVE(&vnic->filter, filter,
2353 bnxt_filter_info, next);
2354 bnxt_free_filter(bp, filter);
2358 filter = STAILQ_NEXT(filter, next);
2364 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2366 struct bnxt_vnic_info *vnic;
2370 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2371 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2372 /* Remove any VLAN filters programmed */
2373 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2374 bnxt_del_vlan_filter(bp, i);
2376 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2380 /* Default filter will allow packets that match the
2381 * dest mac. So, it has to be deleted, otherwise, we
2382 * will endup receiving vlan packets for which the
2383 * filter is not programmed, when hw-vlan-filter
2384 * configuration is ON
2386 bnxt_del_dflt_mac_filter(bp, vnic);
2387 /* This filter will allow only untagged packets */
2388 bnxt_add_vlan_filter(bp, 0);
2390 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2391 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2396 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2398 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2402 /* Destroy vnic filters and vnic */
2403 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2404 DEV_RX_OFFLOAD_VLAN_FILTER) {
2405 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2406 bnxt_del_vlan_filter(bp, i);
2408 bnxt_del_dflt_mac_filter(bp, vnic);
2410 rc = bnxt_hwrm_vnic_free(bp, vnic);
2414 rte_free(vnic->fw_grp_ids);
2415 vnic->fw_grp_ids = NULL;
2417 vnic->rx_queue_cnt = 0;
2423 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2425 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2428 /* Destroy, recreate and reconfigure the default vnic */
2429 rc = bnxt_free_one_vnic(bp, 0);
2433 /* default vnic 0 */
2434 rc = bnxt_setup_one_vnic(bp, 0);
2438 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2439 DEV_RX_OFFLOAD_VLAN_FILTER) {
2440 rc = bnxt_add_vlan_filter(bp, 0);
2443 rc = bnxt_restore_vlan_filters(bp);
2447 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2452 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2456 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2457 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2463 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2465 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2466 struct bnxt *bp = dev->data->dev_private;
2469 rc = is_bnxt_in_error(bp);
2473 /* Filter settings will get applied when port is started */
2474 if (!dev->data->dev_started)
2477 if (mask & ETH_VLAN_FILTER_MASK) {
2478 /* Enable or disable VLAN filtering */
2479 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2484 if (mask & ETH_VLAN_STRIP_MASK) {
2485 /* Enable or disable VLAN stripping */
2486 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2491 if (mask & ETH_VLAN_EXTEND_MASK) {
2492 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2493 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2495 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2502 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2505 struct bnxt *bp = dev->data->dev_private;
2506 int qinq = dev->data->dev_conf.rxmode.offloads &
2507 DEV_RX_OFFLOAD_VLAN_EXTEND;
2509 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2510 vlan_type != ETH_VLAN_TYPE_OUTER) {
2512 "Unsupported vlan type.");
2517 "QinQ not enabled. Needs to be ON as we can "
2518 "accelerate only outer vlan\n");
2522 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2524 case RTE_ETHER_TYPE_QINQ:
2526 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2528 case RTE_ETHER_TYPE_VLAN:
2530 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2532 case RTE_ETHER_TYPE_QINQ1:
2534 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2536 case RTE_ETHER_TYPE_QINQ2:
2538 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2540 case RTE_ETHER_TYPE_QINQ3:
2542 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2545 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2548 bp->outer_tpid_bd |= tpid;
2549 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2550 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2552 "Can accelerate only outer vlan in QinQ\n");
2560 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2561 struct rte_ether_addr *addr)
2563 struct bnxt *bp = dev->data->dev_private;
2564 /* Default Filter is tied to VNIC 0 */
2565 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2568 rc = is_bnxt_in_error(bp);
2572 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2575 if (rte_is_zero_ether_addr(addr))
2578 /* Filter settings will get applied when port is started */
2579 if (!dev->data->dev_started)
2582 /* Check if the requested MAC is already added */
2583 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2586 /* Destroy filter and re-create it */
2587 bnxt_del_dflt_mac_filter(bp, vnic);
2589 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2590 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2591 /* This filter will allow only untagged packets */
2592 rc = bnxt_add_vlan_filter(bp, 0);
2594 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2597 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2602 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2603 struct rte_ether_addr *mc_addr_set,
2604 uint32_t nb_mc_addr)
2606 struct bnxt *bp = eth_dev->data->dev_private;
2607 char *mc_addr_list = (char *)mc_addr_set;
2608 struct bnxt_vnic_info *vnic;
2609 uint32_t off = 0, i = 0;
2612 rc = is_bnxt_in_error(bp);
2616 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2618 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2619 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2623 /* TODO Check for Duplicate mcast addresses */
2624 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2625 for (i = 0; i < nb_mc_addr; i++) {
2626 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2627 RTE_ETHER_ADDR_LEN);
2628 off += RTE_ETHER_ADDR_LEN;
2631 vnic->mc_addr_cnt = i;
2632 if (vnic->mc_addr_cnt)
2633 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2635 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2638 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2642 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2644 struct bnxt *bp = dev->data->dev_private;
2645 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2646 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2647 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2648 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2651 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2652 fw_major, fw_minor, fw_updt, fw_rsvd);
2654 ret += 1; /* add the size of '\0' */
2655 if (fw_size < (uint32_t)ret)
2662 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2663 struct rte_eth_rxq_info *qinfo)
2665 struct bnxt *bp = dev->data->dev_private;
2666 struct bnxt_rx_queue *rxq;
2668 if (is_bnxt_in_error(bp))
2671 rxq = dev->data->rx_queues[queue_id];
2673 qinfo->mp = rxq->mb_pool;
2674 qinfo->scattered_rx = dev->data->scattered_rx;
2675 qinfo->nb_desc = rxq->nb_rx_desc;
2677 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2678 qinfo->conf.rx_drop_en = rxq->drop_en;
2679 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2680 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2684 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2685 struct rte_eth_txq_info *qinfo)
2687 struct bnxt *bp = dev->data->dev_private;
2688 struct bnxt_tx_queue *txq;
2690 if (is_bnxt_in_error(bp))
2693 txq = dev->data->tx_queues[queue_id];
2695 qinfo->nb_desc = txq->nb_tx_desc;
2697 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2698 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2699 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2701 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2702 qinfo->conf.tx_rs_thresh = 0;
2703 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2704 qinfo->conf.offloads = txq->offloads;
2707 static const struct {
2708 eth_rx_burst_t pkt_burst;
2710 } bnxt_rx_burst_info[] = {
2711 {bnxt_recv_pkts, "Scalar"},
2712 #if defined(RTE_ARCH_X86)
2713 {bnxt_recv_pkts_vec, "Vector SSE"},
2714 #elif defined(RTE_ARCH_ARM64)
2715 {bnxt_recv_pkts_vec, "Vector Neon"},
2720 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2721 struct rte_eth_burst_mode *mode)
2723 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2726 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2727 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2728 snprintf(mode->info, sizeof(mode->info), "%s",
2729 bnxt_rx_burst_info[i].info);
2737 static const struct {
2738 eth_tx_burst_t pkt_burst;
2740 } bnxt_tx_burst_info[] = {
2741 {bnxt_xmit_pkts, "Scalar"},
2742 #if defined(RTE_ARCH_X86)
2743 {bnxt_xmit_pkts_vec, "Vector SSE"},
2744 #elif defined(RTE_ARCH_ARM64)
2745 {bnxt_xmit_pkts_vec, "Vector Neon"},
2750 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2751 struct rte_eth_burst_mode *mode)
2753 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2756 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2757 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2758 snprintf(mode->info, sizeof(mode->info), "%s",
2759 bnxt_tx_burst_info[i].info);
2767 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2769 struct bnxt *bp = eth_dev->data->dev_private;
2770 uint32_t new_pkt_size;
2774 rc = is_bnxt_in_error(bp);
2778 /* Exit if receive queues are not configured yet */
2779 if (!eth_dev->data->nb_rx_queues)
2782 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2783 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2786 * Disallow any MTU change that would require scattered receive support
2787 * if it is not already enabled.
2789 if (eth_dev->data->dev_started &&
2790 !eth_dev->data->scattered_rx &&
2792 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2794 "MTU change would require scattered rx support. ");
2795 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2799 if (new_mtu > RTE_ETHER_MTU) {
2800 bp->flags |= BNXT_FLAG_JUMBO;
2801 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2802 DEV_RX_OFFLOAD_JUMBO_FRAME;
2804 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2805 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2806 bp->flags &= ~BNXT_FLAG_JUMBO;
2809 /* Is there a change in mtu setting? */
2810 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2813 for (i = 0; i < bp->nr_vnics; i++) {
2814 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2817 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2818 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2822 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2823 size -= RTE_PKTMBUF_HEADROOM;
2825 if (size < new_mtu) {
2826 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2833 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2835 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2841 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2843 struct bnxt *bp = dev->data->dev_private;
2844 uint16_t vlan = bp->vlan;
2847 rc = is_bnxt_in_error(bp);
2851 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2853 "PVID cannot be modified for this function\n");
2856 bp->vlan = on ? pvid : 0;
2858 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2865 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2867 struct bnxt *bp = dev->data->dev_private;
2870 rc = is_bnxt_in_error(bp);
2874 return bnxt_hwrm_port_led_cfg(bp, true);
2878 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2880 struct bnxt *bp = dev->data->dev_private;
2883 rc = is_bnxt_in_error(bp);
2887 return bnxt_hwrm_port_led_cfg(bp, false);
2891 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2893 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2894 uint32_t desc = 0, raw_cons = 0, cons;
2895 struct bnxt_cp_ring_info *cpr;
2896 struct bnxt_rx_queue *rxq;
2897 struct rx_pkt_cmpl *rxcmp;
2900 rc = is_bnxt_in_error(bp);
2904 rxq = dev->data->rx_queues[rx_queue_id];
2906 raw_cons = cpr->cp_raw_cons;
2909 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2910 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2911 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2913 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2925 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2927 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2928 struct bnxt_rx_ring_info *rxr;
2929 struct bnxt_cp_ring_info *cpr;
2930 struct rte_mbuf *rx_buf;
2931 struct rx_pkt_cmpl *rxcmp;
2932 uint32_t cons, cp_cons;
2938 rc = is_bnxt_in_error(rxq->bp);
2945 if (offset >= rxq->nb_rx_desc)
2948 cons = RING_CMP(cpr->cp_ring_struct, offset);
2949 cp_cons = cpr->cp_raw_cons;
2950 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2952 if (cons > cp_cons) {
2953 if (CMPL_VALID(rxcmp, cpr->valid))
2954 return RTE_ETH_RX_DESC_DONE;
2956 if (CMPL_VALID(rxcmp, !cpr->valid))
2957 return RTE_ETH_RX_DESC_DONE;
2959 rx_buf = rxr->rx_buf_ring[cons];
2960 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2961 return RTE_ETH_RX_DESC_UNAVAIL;
2964 return RTE_ETH_RX_DESC_AVAIL;
2968 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2970 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2971 struct bnxt_tx_ring_info *txr;
2972 struct bnxt_cp_ring_info *cpr;
2973 struct bnxt_sw_tx_bd *tx_buf;
2974 struct tx_pkt_cmpl *txcmp;
2975 uint32_t cons, cp_cons;
2981 rc = is_bnxt_in_error(txq->bp);
2988 if (offset >= txq->nb_tx_desc)
2991 cons = RING_CMP(cpr->cp_ring_struct, offset);
2992 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2993 cp_cons = cpr->cp_raw_cons;
2995 if (cons > cp_cons) {
2996 if (CMPL_VALID(txcmp, cpr->valid))
2997 return RTE_ETH_TX_DESC_UNAVAIL;
2999 if (CMPL_VALID(txcmp, !cpr->valid))
3000 return RTE_ETH_TX_DESC_UNAVAIL;
3002 tx_buf = &txr->tx_buf_ring[cons];
3003 if (tx_buf->mbuf == NULL)
3004 return RTE_ETH_TX_DESC_DONE;
3006 return RTE_ETH_TX_DESC_FULL;
3010 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3011 enum rte_filter_type filter_type,
3012 enum rte_filter_op filter_op, void *arg)
3014 struct bnxt *bp = dev->data->dev_private;
3020 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3021 struct bnxt_representor *vfr = dev->data->dev_private;
3022 bp = vfr->parent_dev->data->dev_private;
3023 /* parent is deleted while children are still valid */
3025 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3033 ret = is_bnxt_in_error(bp);
3037 switch (filter_type) {
3038 case RTE_ETH_FILTER_GENERIC:
3039 if (filter_op != RTE_ETH_FILTER_GET)
3042 /* PMD supports thread-safe flow operations. rte_flow API
3043 * functions can avoid mutex for multi-thread safety.
3045 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3047 if (BNXT_TRUFLOW_EN(bp))
3048 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3050 *(const void **)arg = &bnxt_flow_ops;
3054 "Filter type (%d) not supported", filter_type);
3061 static const uint32_t *
3062 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3064 static const uint32_t ptypes[] = {
3065 RTE_PTYPE_L2_ETHER_VLAN,
3066 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3067 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3071 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3072 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3073 RTE_PTYPE_INNER_L4_ICMP,
3074 RTE_PTYPE_INNER_L4_TCP,
3075 RTE_PTYPE_INNER_L4_UDP,
3079 if (!dev->rx_pkt_burst)
3085 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3088 uint32_t reg_base = *reg_arr & 0xfffff000;
3092 for (i = 0; i < count; i++) {
3093 if ((reg_arr[i] & 0xfffff000) != reg_base)
3096 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3097 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3101 static int bnxt_map_ptp_regs(struct bnxt *bp)
3103 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3107 reg_arr = ptp->rx_regs;
3108 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3112 reg_arr = ptp->tx_regs;
3113 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3117 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3118 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3120 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3121 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3126 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3128 rte_write32(0, (uint8_t *)bp->bar0 +
3129 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3130 rte_write32(0, (uint8_t *)bp->bar0 +
3131 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3134 static uint64_t bnxt_cc_read(struct bnxt *bp)
3138 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3139 BNXT_GRCPF_REG_SYNC_TIME));
3140 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3141 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3145 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3147 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3150 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3151 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3152 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3155 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3156 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3157 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3158 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3159 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3160 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3165 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3167 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3168 struct bnxt_pf_info *pf = bp->pf;
3175 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3176 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3177 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3180 port_id = pf->port_id;
3181 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3182 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3184 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3185 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3186 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3187 /* bnxt_clr_rx_ts(bp); TBD */
3191 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3192 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3193 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3194 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3200 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3203 struct bnxt *bp = dev->data->dev_private;
3204 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3209 ns = rte_timespec_to_ns(ts);
3210 /* Set the timecounters to a new value. */
3217 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3219 struct bnxt *bp = dev->data->dev_private;
3220 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3221 uint64_t ns, systime_cycles = 0;
3227 if (BNXT_CHIP_P5(bp))
3228 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3231 systime_cycles = bnxt_cc_read(bp);
3233 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3234 *ts = rte_ns_to_timespec(ns);
3239 bnxt_timesync_enable(struct rte_eth_dev *dev)
3241 struct bnxt *bp = dev->data->dev_private;
3242 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3250 ptp->tx_tstamp_en = 1;
3251 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3253 rc = bnxt_hwrm_ptp_cfg(bp);
3257 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3258 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3259 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3261 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3262 ptp->tc.cc_shift = shift;
3263 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3265 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3266 ptp->rx_tstamp_tc.cc_shift = shift;
3267 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3269 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3270 ptp->tx_tstamp_tc.cc_shift = shift;
3271 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3273 if (!BNXT_CHIP_P5(bp))
3274 bnxt_map_ptp_regs(bp);
3280 bnxt_timesync_disable(struct rte_eth_dev *dev)
3282 struct bnxt *bp = dev->data->dev_private;
3283 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3289 ptp->tx_tstamp_en = 0;
3292 bnxt_hwrm_ptp_cfg(bp);
3294 if (!BNXT_CHIP_P5(bp))
3295 bnxt_unmap_ptp_regs(bp);
3301 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3302 struct timespec *timestamp,
3303 uint32_t flags __rte_unused)
3305 struct bnxt *bp = dev->data->dev_private;
3306 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3307 uint64_t rx_tstamp_cycles = 0;
3313 if (BNXT_CHIP_P5(bp))
3314 rx_tstamp_cycles = ptp->rx_timestamp;
3316 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3318 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3319 *timestamp = rte_ns_to_timespec(ns);
3324 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3325 struct timespec *timestamp)
3327 struct bnxt *bp = dev->data->dev_private;
3328 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3329 uint64_t tx_tstamp_cycles = 0;
3336 if (BNXT_CHIP_P5(bp))
3337 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3340 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3342 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3343 *timestamp = rte_ns_to_timespec(ns);
3349 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3351 struct bnxt *bp = dev->data->dev_private;
3352 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3357 ptp->tc.nsec += delta;
3363 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3365 struct bnxt *bp = dev->data->dev_private;
3367 uint32_t dir_entries;
3368 uint32_t entry_length;
3370 rc = is_bnxt_in_error(bp);
3374 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3375 bp->pdev->addr.domain, bp->pdev->addr.bus,
3376 bp->pdev->addr.devid, bp->pdev->addr.function);
3378 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3382 return dir_entries * entry_length;
3386 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3387 struct rte_dev_eeprom_info *in_eeprom)
3389 struct bnxt *bp = dev->data->dev_private;
3394 rc = is_bnxt_in_error(bp);
3398 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3399 bp->pdev->addr.domain, bp->pdev->addr.bus,
3400 bp->pdev->addr.devid, bp->pdev->addr.function,
3401 in_eeprom->offset, in_eeprom->length);
3403 if (in_eeprom->offset == 0) /* special offset value to get directory */
3404 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3407 index = in_eeprom->offset >> 24;
3408 offset = in_eeprom->offset & 0xffffff;
3411 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3412 in_eeprom->length, in_eeprom->data);
3417 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3420 case BNX_DIR_TYPE_CHIMP_PATCH:
3421 case BNX_DIR_TYPE_BOOTCODE:
3422 case BNX_DIR_TYPE_BOOTCODE_2:
3423 case BNX_DIR_TYPE_APE_FW:
3424 case BNX_DIR_TYPE_APE_PATCH:
3425 case BNX_DIR_TYPE_KONG_FW:
3426 case BNX_DIR_TYPE_KONG_PATCH:
3427 case BNX_DIR_TYPE_BONO_FW:
3428 case BNX_DIR_TYPE_BONO_PATCH:
3436 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3439 case BNX_DIR_TYPE_AVS:
3440 case BNX_DIR_TYPE_EXP_ROM_MBA:
3441 case BNX_DIR_TYPE_PCIE:
3442 case BNX_DIR_TYPE_TSCF_UCODE:
3443 case BNX_DIR_TYPE_EXT_PHY:
3444 case BNX_DIR_TYPE_CCM:
3445 case BNX_DIR_TYPE_ISCSI_BOOT:
3446 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3447 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3455 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3457 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3458 bnxt_dir_type_is_other_exec_format(dir_type);
3462 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3463 struct rte_dev_eeprom_info *in_eeprom)
3465 struct bnxt *bp = dev->data->dev_private;
3466 uint8_t index, dir_op;
3467 uint16_t type, ext, ordinal, attr;
3470 rc = is_bnxt_in_error(bp);
3474 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3475 bp->pdev->addr.domain, bp->pdev->addr.bus,
3476 bp->pdev->addr.devid, bp->pdev->addr.function,
3477 in_eeprom->offset, in_eeprom->length);
3480 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3484 type = in_eeprom->magic >> 16;
3486 if (type == 0xffff) { /* special value for directory operations */
3487 index = in_eeprom->magic & 0xff;
3488 dir_op = in_eeprom->magic >> 8;
3492 case 0x0e: /* erase */
3493 if (in_eeprom->offset != ~in_eeprom->magic)
3495 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3501 /* Create or re-write an NVM item: */
3502 if (bnxt_dir_type_is_executable(type) == true)
3504 ext = in_eeprom->magic & 0xffff;
3505 ordinal = in_eeprom->offset >> 16;
3506 attr = in_eeprom->offset & 0xffff;
3508 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3509 in_eeprom->data, in_eeprom->length);
3516 static const struct eth_dev_ops bnxt_dev_ops = {
3517 .dev_infos_get = bnxt_dev_info_get_op,
3518 .dev_close = bnxt_dev_close_op,
3519 .dev_configure = bnxt_dev_configure_op,
3520 .dev_start = bnxt_dev_start_op,
3521 .dev_stop = bnxt_dev_stop_op,
3522 .dev_set_link_up = bnxt_dev_set_link_up_op,
3523 .dev_set_link_down = bnxt_dev_set_link_down_op,
3524 .stats_get = bnxt_stats_get_op,
3525 .stats_reset = bnxt_stats_reset_op,
3526 .rx_queue_setup = bnxt_rx_queue_setup_op,
3527 .rx_queue_release = bnxt_rx_queue_release_op,
3528 .tx_queue_setup = bnxt_tx_queue_setup_op,
3529 .tx_queue_release = bnxt_tx_queue_release_op,
3530 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3531 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3532 .reta_update = bnxt_reta_update_op,
3533 .reta_query = bnxt_reta_query_op,
3534 .rss_hash_update = bnxt_rss_hash_update_op,
3535 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3536 .link_update = bnxt_link_update_op,
3537 .promiscuous_enable = bnxt_promiscuous_enable_op,
3538 .promiscuous_disable = bnxt_promiscuous_disable_op,
3539 .allmulticast_enable = bnxt_allmulticast_enable_op,
3540 .allmulticast_disable = bnxt_allmulticast_disable_op,
3541 .mac_addr_add = bnxt_mac_addr_add_op,
3542 .mac_addr_remove = bnxt_mac_addr_remove_op,
3543 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3544 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3545 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3546 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3547 .vlan_filter_set = bnxt_vlan_filter_set_op,
3548 .vlan_offload_set = bnxt_vlan_offload_set_op,
3549 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3550 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3551 .mtu_set = bnxt_mtu_set_op,
3552 .mac_addr_set = bnxt_set_default_mac_addr_op,
3553 .xstats_get = bnxt_dev_xstats_get_op,
3554 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3555 .xstats_reset = bnxt_dev_xstats_reset_op,
3556 .fw_version_get = bnxt_fw_version_get,
3557 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3558 .rxq_info_get = bnxt_rxq_info_get_op,
3559 .txq_info_get = bnxt_txq_info_get_op,
3560 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3561 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3562 .dev_led_on = bnxt_dev_led_on_op,
3563 .dev_led_off = bnxt_dev_led_off_op,
3564 .rx_queue_start = bnxt_rx_queue_start,
3565 .rx_queue_stop = bnxt_rx_queue_stop,
3566 .tx_queue_start = bnxt_tx_queue_start,
3567 .tx_queue_stop = bnxt_tx_queue_stop,
3568 .filter_ctrl = bnxt_filter_ctrl_op,
3569 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3570 .get_eeprom_length = bnxt_get_eeprom_length_op,
3571 .get_eeprom = bnxt_get_eeprom_op,
3572 .set_eeprom = bnxt_set_eeprom_op,
3573 .timesync_enable = bnxt_timesync_enable,
3574 .timesync_disable = bnxt_timesync_disable,
3575 .timesync_read_time = bnxt_timesync_read_time,
3576 .timesync_write_time = bnxt_timesync_write_time,
3577 .timesync_adjust_time = bnxt_timesync_adjust_time,
3578 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3579 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3582 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3586 /* Only pre-map the reset GRC registers using window 3 */
3587 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3588 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3590 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3595 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3597 struct bnxt_error_recovery_info *info = bp->recovery_info;
3598 uint32_t reg_base = 0xffffffff;
3601 /* Only pre-map the monitoring GRC registers using window 2 */
3602 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3603 uint32_t reg = info->status_regs[i];
3605 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3608 if (reg_base == 0xffffffff)
3609 reg_base = reg & 0xfffff000;
3610 if ((reg & 0xfffff000) != reg_base)
3613 /* Use mask 0xffc as the Lower 2 bits indicates
3614 * address space location
3616 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3620 if (reg_base == 0xffffffff)
3623 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3624 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3629 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3631 struct bnxt_error_recovery_info *info = bp->recovery_info;
3632 uint32_t delay = info->delay_after_reset[index];
3633 uint32_t val = info->reset_reg_val[index];
3634 uint32_t reg = info->reset_reg[index];
3635 uint32_t type, offset;
3637 type = BNXT_FW_STATUS_REG_TYPE(reg);
3638 offset = BNXT_FW_STATUS_REG_OFF(reg);
3641 case BNXT_FW_STATUS_REG_TYPE_CFG:
3642 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3644 case BNXT_FW_STATUS_REG_TYPE_GRC:
3645 offset = bnxt_map_reset_regs(bp, offset);
3646 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3648 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3649 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3652 /* wait on a specific interval of time until core reset is complete */
3654 rte_delay_ms(delay);
3657 static void bnxt_dev_cleanup(struct bnxt *bp)
3659 bp->eth_dev->data->dev_link.link_status = 0;
3660 bp->link_info->link_up = 0;
3661 if (bp->eth_dev->data->dev_started)
3662 bnxt_dev_stop_op(bp->eth_dev);
3664 bnxt_uninit_resources(bp, true);
3667 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3669 struct rte_eth_dev *dev = bp->eth_dev;
3670 struct rte_vlan_filter_conf *vfc;
3674 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3675 vfc = &dev->data->vlan_filter_conf;
3676 vidx = vlan_id / 64;
3677 vbit = vlan_id % 64;
3679 /* Each bit corresponds to a VLAN id */
3680 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3681 rc = bnxt_add_vlan_filter(bp, vlan_id);
3690 static int bnxt_restore_mac_filters(struct bnxt *bp)
3692 struct rte_eth_dev *dev = bp->eth_dev;
3693 struct rte_eth_dev_info dev_info;
3694 struct rte_ether_addr *addr;
3700 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3703 rc = bnxt_dev_info_get_op(dev, &dev_info);
3707 /* replay MAC address configuration */
3708 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3709 addr = &dev->data->mac_addrs[i];
3711 /* skip zero address */
3712 if (rte_is_zero_ether_addr(addr))
3716 pool_mask = dev->data->mac_pool_sel[i];
3719 if (pool_mask & 1ULL) {
3720 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3726 } while (pool_mask);
3732 static int bnxt_restore_filters(struct bnxt *bp)
3734 struct rte_eth_dev *dev = bp->eth_dev;
3737 if (dev->data->all_multicast) {
3738 ret = bnxt_allmulticast_enable_op(dev);
3742 if (dev->data->promiscuous) {
3743 ret = bnxt_promiscuous_enable_op(dev);
3748 ret = bnxt_restore_mac_filters(bp);
3752 ret = bnxt_restore_vlan_filters(bp);
3753 /* TODO restore other filters as well */
3757 static void bnxt_dev_recover(void *arg)
3759 struct bnxt *bp = arg;
3760 int timeout = bp->fw_reset_max_msecs;
3763 /* Clear Error flag so that device re-init should happen */
3764 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3767 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3770 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3771 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3772 } while (rc && timeout);
3775 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3779 rc = bnxt_init_resources(bp, true);
3782 "Failed to initialize resources after reset\n");
3785 /* clear reset flag as the device is initialized now */
3786 bp->flags &= ~BNXT_FLAG_FW_RESET;
3788 rc = bnxt_dev_start_op(bp->eth_dev);
3790 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3794 rc = bnxt_restore_filters(bp);
3798 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3801 bnxt_dev_stop_op(bp->eth_dev);
3803 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3804 bnxt_uninit_resources(bp, false);
3805 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3808 void bnxt_dev_reset_and_resume(void *arg)
3810 struct bnxt *bp = arg;
3813 bnxt_dev_cleanup(bp);
3815 bnxt_wait_for_device_shutdown(bp);
3817 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3818 bnxt_dev_recover, (void *)bp);
3820 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3823 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3825 struct bnxt_error_recovery_info *info = bp->recovery_info;
3826 uint32_t reg = info->status_regs[index];
3827 uint32_t type, offset, val = 0;
3829 type = BNXT_FW_STATUS_REG_TYPE(reg);
3830 offset = BNXT_FW_STATUS_REG_OFF(reg);
3833 case BNXT_FW_STATUS_REG_TYPE_CFG:
3834 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3836 case BNXT_FW_STATUS_REG_TYPE_GRC:
3837 offset = info->mapped_status_regs[index];
3839 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3840 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3848 static int bnxt_fw_reset_all(struct bnxt *bp)
3850 struct bnxt_error_recovery_info *info = bp->recovery_info;
3854 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3855 /* Reset through master function driver */
3856 for (i = 0; i < info->reg_array_cnt; i++)
3857 bnxt_write_fw_reset_reg(bp, i);
3858 /* Wait for time specified by FW after triggering reset */
3859 rte_delay_ms(info->master_func_wait_period_after_reset);
3860 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3861 /* Reset with the help of Kong processor */
3862 rc = bnxt_hwrm_fw_reset(bp);
3864 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3870 static void bnxt_fw_reset_cb(void *arg)
3872 struct bnxt *bp = arg;
3873 struct bnxt_error_recovery_info *info = bp->recovery_info;
3876 /* Only Master function can do FW reset */
3877 if (bnxt_is_master_func(bp) &&
3878 bnxt_is_recovery_enabled(bp)) {
3879 rc = bnxt_fw_reset_all(bp);
3881 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3886 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3887 * EXCEPTION_FATAL_ASYNC event to all the functions
3888 * (including MASTER FUNC). After receiving this Async, all the active
3889 * drivers should treat this case as FW initiated recovery
3891 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3892 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3893 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3895 /* To recover from error */
3896 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3901 /* Driver should poll FW heartbeat, reset_counter with the frequency
3902 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3903 * When the driver detects heartbeat stop or change in reset_counter,
3904 * it has to trigger a reset to recover from the error condition.
3905 * A “master PF” is the function who will have the privilege to
3906 * initiate the chimp reset. The master PF will be elected by the
3907 * firmware and will be notified through async message.
3909 static void bnxt_check_fw_health(void *arg)
3911 struct bnxt *bp = arg;
3912 struct bnxt_error_recovery_info *info = bp->recovery_info;
3913 uint32_t val = 0, wait_msec;
3915 if (!info || !bnxt_is_recovery_enabled(bp) ||
3916 is_bnxt_in_error(bp))
3919 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3920 if (val == info->last_heart_beat)
3923 info->last_heart_beat = val;
3925 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3926 if (val != info->last_reset_counter)
3929 info->last_reset_counter = val;
3931 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3932 bnxt_check_fw_health, (void *)bp);
3936 /* Stop DMA to/from device */
3937 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3938 bp->flags |= BNXT_FLAG_FW_RESET;
3940 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3942 if (bnxt_is_master_func(bp))
3943 wait_msec = info->master_func_wait_period;
3945 wait_msec = info->normal_func_wait_period;
3947 rte_eal_alarm_set(US_PER_MS * wait_msec,
3948 bnxt_fw_reset_cb, (void *)bp);
3951 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3953 uint32_t polling_freq;
3955 pthread_mutex_lock(&bp->health_check_lock);
3957 if (!bnxt_is_recovery_enabled(bp))
3960 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3963 polling_freq = bp->recovery_info->driver_polling_freq;
3965 rte_eal_alarm_set(US_PER_MS * polling_freq,
3966 bnxt_check_fw_health, (void *)bp);
3967 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3970 pthread_mutex_unlock(&bp->health_check_lock);
3973 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3975 if (!bnxt_is_recovery_enabled(bp))
3978 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3979 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3982 static bool bnxt_vf_pciid(uint16_t device_id)
3984 switch (device_id) {
3985 case BROADCOM_DEV_ID_57304_VF:
3986 case BROADCOM_DEV_ID_57406_VF:
3987 case BROADCOM_DEV_ID_5731X_VF:
3988 case BROADCOM_DEV_ID_5741X_VF:
3989 case BROADCOM_DEV_ID_57414_VF:
3990 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
3991 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
3992 case BROADCOM_DEV_ID_58802_VF:
3993 case BROADCOM_DEV_ID_57500_VF1:
3994 case BROADCOM_DEV_ID_57500_VF2:
4002 /* Phase 5 device */
4003 static bool bnxt_p5_device(uint16_t device_id)
4005 switch (device_id) {
4006 case BROADCOM_DEV_ID_57508:
4007 case BROADCOM_DEV_ID_57504:
4008 case BROADCOM_DEV_ID_57502:
4009 case BROADCOM_DEV_ID_57508_MF1:
4010 case BROADCOM_DEV_ID_57504_MF1:
4011 case BROADCOM_DEV_ID_57502_MF1:
4012 case BROADCOM_DEV_ID_57508_MF2:
4013 case BROADCOM_DEV_ID_57504_MF2:
4014 case BROADCOM_DEV_ID_57502_MF2:
4015 case BROADCOM_DEV_ID_57500_VF1:
4016 case BROADCOM_DEV_ID_57500_VF2:
4024 bool bnxt_stratus_device(struct bnxt *bp)
4026 uint16_t device_id = bp->pdev->id.device_id;
4028 switch (device_id) {
4029 case BROADCOM_DEV_ID_STRATUS_NIC:
4030 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4031 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4039 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4041 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4042 struct bnxt *bp = eth_dev->data->dev_private;
4044 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4045 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4046 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4047 if (!bp->bar0 || !bp->doorbell_base) {
4048 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4052 bp->eth_dev = eth_dev;
4058 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4059 struct bnxt_ctx_pg_info *ctx_pg,
4064 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4065 const struct rte_memzone *mz = NULL;
4066 char mz_name[RTE_MEMZONE_NAMESIZE];
4067 rte_iova_t mz_phys_addr;
4068 uint64_t valid_bits = 0;
4075 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4077 rmem->page_size = BNXT_PAGE_SIZE;
4078 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4079 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4080 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4082 valid_bits = PTU_PTE_VALID;
4084 if (rmem->nr_pages > 1) {
4085 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4086 "bnxt_ctx_pg_tbl%s_%x_%d",
4087 suffix, idx, bp->eth_dev->data->port_id);
4088 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4089 mz = rte_memzone_lookup(mz_name);
4091 mz = rte_memzone_reserve_aligned(mz_name,
4095 RTE_MEMZONE_SIZE_HINT_ONLY |
4096 RTE_MEMZONE_IOVA_CONTIG,
4102 memset(mz->addr, 0, mz->len);
4103 mz_phys_addr = mz->iova;
4105 rmem->pg_tbl = mz->addr;
4106 rmem->pg_tbl_map = mz_phys_addr;
4107 rmem->pg_tbl_mz = mz;
4110 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4111 suffix, idx, bp->eth_dev->data->port_id);
4112 mz = rte_memzone_lookup(mz_name);
4114 mz = rte_memzone_reserve_aligned(mz_name,
4118 RTE_MEMZONE_SIZE_HINT_ONLY |
4119 RTE_MEMZONE_IOVA_CONTIG,
4125 memset(mz->addr, 0, mz->len);
4126 mz_phys_addr = mz->iova;
4128 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4129 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4130 rmem->dma_arr[i] = mz_phys_addr + sz;
4132 if (rmem->nr_pages > 1) {
4133 if (i == rmem->nr_pages - 2 &&
4134 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4135 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4136 else if (i == rmem->nr_pages - 1 &&
4137 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4138 valid_bits |= PTU_PTE_LAST;
4140 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4146 if (rmem->vmem_size)
4147 rmem->vmem = (void **)mz->addr;
4148 rmem->dma_arr[0] = mz_phys_addr;
4152 static void bnxt_free_ctx_mem(struct bnxt *bp)
4156 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4159 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4160 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4161 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4162 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4163 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4164 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4165 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4166 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4167 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4168 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4169 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4171 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4172 if (bp->ctx->tqm_mem[i])
4173 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4180 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4182 #define min_t(type, x, y) ({ \
4183 type __min1 = (x); \
4184 type __min2 = (y); \
4185 __min1 < __min2 ? __min1 : __min2; })
4187 #define max_t(type, x, y) ({ \
4188 type __max1 = (x); \
4189 type __max2 = (y); \
4190 __max1 > __max2 ? __max1 : __max2; })
4192 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4194 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4196 struct bnxt_ctx_pg_info *ctx_pg;
4197 struct bnxt_ctx_mem_info *ctx;
4198 uint32_t mem_size, ena, entries;
4199 uint32_t entries_sp, min;
4202 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4204 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4208 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4211 ctx_pg = &ctx->qp_mem;
4212 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4213 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4214 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4218 ctx_pg = &ctx->srq_mem;
4219 ctx_pg->entries = ctx->srq_max_l2_entries;
4220 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4221 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4225 ctx_pg = &ctx->cq_mem;
4226 ctx_pg->entries = ctx->cq_max_l2_entries;
4227 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4228 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4232 ctx_pg = &ctx->vnic_mem;
4233 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4234 ctx->vnic_max_ring_table_entries;
4235 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4236 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4240 ctx_pg = &ctx->stat_mem;
4241 ctx_pg->entries = ctx->stat_max_entries;
4242 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4243 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4247 min = ctx->tqm_min_entries_per_ring;
4249 entries_sp = ctx->qp_max_l2_entries +
4250 ctx->vnic_max_vnic_entries +
4251 2 * ctx->qp_min_qp1_entries + min;
4252 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4254 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4255 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4256 entries = clamp_t(uint32_t, entries, min,
4257 ctx->tqm_max_entries_per_ring);
4258 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4259 ctx_pg = ctx->tqm_mem[i];
4260 ctx_pg->entries = i ? entries : entries_sp;
4261 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4262 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4265 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4268 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4269 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4272 "Failed to configure context mem: rc = %d\n", rc);
4274 ctx->flags |= BNXT_CTX_FLAG_INITED;
4279 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4281 struct rte_pci_device *pci_dev = bp->pdev;
4282 char mz_name[RTE_MEMZONE_NAMESIZE];
4283 const struct rte_memzone *mz = NULL;
4284 uint32_t total_alloc_len;
4285 rte_iova_t mz_phys_addr;
4287 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4290 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4291 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4292 pci_dev->addr.bus, pci_dev->addr.devid,
4293 pci_dev->addr.function, "rx_port_stats");
4294 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4295 mz = rte_memzone_lookup(mz_name);
4297 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4298 sizeof(struct rx_port_stats_ext) + 512);
4300 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4303 RTE_MEMZONE_SIZE_HINT_ONLY |
4304 RTE_MEMZONE_IOVA_CONTIG);
4308 memset(mz->addr, 0, mz->len);
4309 mz_phys_addr = mz->iova;
4311 bp->rx_mem_zone = (const void *)mz;
4312 bp->hw_rx_port_stats = mz->addr;
4313 bp->hw_rx_port_stats_map = mz_phys_addr;
4315 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4316 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4317 pci_dev->addr.bus, pci_dev->addr.devid,
4318 pci_dev->addr.function, "tx_port_stats");
4319 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4320 mz = rte_memzone_lookup(mz_name);
4322 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4323 sizeof(struct tx_port_stats_ext) + 512);
4325 mz = rte_memzone_reserve(mz_name,
4329 RTE_MEMZONE_SIZE_HINT_ONLY |
4330 RTE_MEMZONE_IOVA_CONTIG);
4334 memset(mz->addr, 0, mz->len);
4335 mz_phys_addr = mz->iova;
4337 bp->tx_mem_zone = (const void *)mz;
4338 bp->hw_tx_port_stats = mz->addr;
4339 bp->hw_tx_port_stats_map = mz_phys_addr;
4340 bp->flags |= BNXT_FLAG_PORT_STATS;
4342 /* Display extended statistics if FW supports it */
4343 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4344 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4345 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4348 bp->hw_rx_port_stats_ext = (void *)
4349 ((uint8_t *)bp->hw_rx_port_stats +
4350 sizeof(struct rx_port_stats));
4351 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4352 sizeof(struct rx_port_stats);
4353 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4355 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4356 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4357 bp->hw_tx_port_stats_ext = (void *)
4358 ((uint8_t *)bp->hw_tx_port_stats +
4359 sizeof(struct tx_port_stats));
4360 bp->hw_tx_port_stats_ext_map =
4361 bp->hw_tx_port_stats_map +
4362 sizeof(struct tx_port_stats);
4363 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4369 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4371 struct bnxt *bp = eth_dev->data->dev_private;
4374 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4375 RTE_ETHER_ADDR_LEN *
4378 if (eth_dev->data->mac_addrs == NULL) {
4379 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4383 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4387 /* Generate a random MAC address, if none was assigned by PF */
4388 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4389 bnxt_eth_hw_addr_random(bp->mac_addr);
4391 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4392 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4393 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4395 rc = bnxt_hwrm_set_mac(bp);
4400 /* Copy the permanent MAC from the FUNC_QCAPS response */
4401 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4406 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4410 /* MAC is already configured in FW */
4411 if (BNXT_HAS_DFLT_MAC_SET(bp))
4414 /* Restore the old MAC configured */
4415 rc = bnxt_hwrm_set_mac(bp);
4417 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4422 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4427 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4429 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4430 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4431 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4432 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4433 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4434 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4438 bnxt_get_svif(uint16_t port_id, bool func_svif,
4439 enum bnxt_ulp_intf_type type)
4441 struct rte_eth_dev *eth_dev;
4444 eth_dev = &rte_eth_devices[port_id];
4445 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4446 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4450 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4453 eth_dev = vfr->parent_dev;
4456 bp = eth_dev->data->dev_private;
4458 return func_svif ? bp->func_svif : bp->port_svif;
4462 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4464 struct rte_eth_dev *eth_dev;
4465 struct bnxt_vnic_info *vnic;
4468 eth_dev = &rte_eth_devices[port];
4469 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4470 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4474 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4475 return vfr->dflt_vnic_id;
4477 eth_dev = vfr->parent_dev;
4480 bp = eth_dev->data->dev_private;
4482 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4484 return vnic->fw_vnic_id;
4488 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4490 struct rte_eth_dev *eth_dev;
4493 eth_dev = &rte_eth_devices[port];
4494 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4495 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4499 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4502 eth_dev = vfr->parent_dev;
4505 bp = eth_dev->data->dev_private;
4510 enum bnxt_ulp_intf_type
4511 bnxt_get_interface_type(uint16_t port)
4513 struct rte_eth_dev *eth_dev;
4516 eth_dev = &rte_eth_devices[port];
4517 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4518 return BNXT_ULP_INTF_TYPE_VF_REP;
4520 bp = eth_dev->data->dev_private;
4522 return BNXT_ULP_INTF_TYPE_PF;
4523 else if (BNXT_VF_IS_TRUSTED(bp))
4524 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4525 else if (BNXT_VF(bp))
4526 return BNXT_ULP_INTF_TYPE_VF;
4528 return BNXT_ULP_INTF_TYPE_INVALID;
4532 bnxt_get_phy_port_id(uint16_t port_id)
4534 struct bnxt_representor *vfr;
4535 struct rte_eth_dev *eth_dev;
4538 eth_dev = &rte_eth_devices[port_id];
4539 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4540 vfr = eth_dev->data->dev_private;
4544 eth_dev = vfr->parent_dev;
4547 bp = eth_dev->data->dev_private;
4549 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4553 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4555 struct rte_eth_dev *eth_dev;
4558 eth_dev = &rte_eth_devices[port_id];
4559 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4560 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4564 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4565 return vfr->fw_fid - 1;
4567 eth_dev = vfr->parent_dev;
4570 bp = eth_dev->data->dev_private;
4572 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4576 bnxt_get_vport(uint16_t port_id)
4578 return (1 << bnxt_get_phy_port_id(port_id));
4581 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4583 struct bnxt_error_recovery_info *info = bp->recovery_info;
4586 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4587 memset(info, 0, sizeof(*info));
4591 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4594 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4597 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4599 bp->recovery_info = info;
4602 static void bnxt_check_fw_status(struct bnxt *bp)
4606 if (!(bp->recovery_info &&
4607 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4610 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4611 if (fw_status != BNXT_FW_STATUS_HEALTHY)
4612 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4616 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4618 struct bnxt_error_recovery_info *info = bp->recovery_info;
4619 uint32_t status_loc;
4622 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4623 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4624 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4625 BNXT_GRCP_WINDOW_2_BASE +
4626 offsetof(struct hcomm_status,
4628 /* If the signature is absent, then FW does not support this feature */
4629 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4630 HCOMM_STATUS_SIGNATURE_VAL)
4634 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4638 bp->recovery_info = info;
4640 memset(info, 0, sizeof(*info));
4643 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4644 BNXT_GRCP_WINDOW_2_BASE +
4645 offsetof(struct hcomm_status,
4648 /* Only pre-map the FW health status GRC register */
4649 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4652 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4653 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4654 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4656 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4657 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4659 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4664 static int bnxt_init_fw(struct bnxt *bp)
4671 rc = bnxt_map_hcomm_fw_status_reg(bp);
4675 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4677 bnxt_check_fw_status(bp);
4681 rc = bnxt_hwrm_func_reset(bp);
4685 rc = bnxt_hwrm_vnic_qcaps(bp);
4689 rc = bnxt_hwrm_queue_qportcfg(bp);
4693 /* Get the MAX capabilities for this function.
4694 * This function also allocates context memory for TQM rings and
4695 * informs the firmware about this allocated backing store memory.
4697 rc = bnxt_hwrm_func_qcaps(bp);
4701 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4705 bnxt_hwrm_port_mac_qcfg(bp);
4707 bnxt_hwrm_parent_pf_qcfg(bp);
4709 bnxt_hwrm_port_phy_qcaps(bp);
4711 bnxt_alloc_error_recovery_info(bp);
4712 /* Get the adapter error recovery support info */
4713 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4715 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4717 bnxt_hwrm_port_led_qcaps(bp);
4723 bnxt_init_locks(struct bnxt *bp)
4727 err = pthread_mutex_init(&bp->flow_lock, NULL);
4729 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4733 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4735 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4739 err = pthread_mutex_init(&bp->health_check_lock, NULL);
4741 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4745 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4749 rc = bnxt_init_fw(bp);
4753 if (!reconfig_dev) {
4754 rc = bnxt_setup_mac_addr(bp->eth_dev);
4758 rc = bnxt_restore_dflt_mac(bp);
4763 bnxt_config_vf_req_fwd(bp);
4765 rc = bnxt_hwrm_func_driver_register(bp);
4767 PMD_DRV_LOG(ERR, "Failed to register driver");
4772 if (bp->pdev->max_vfs) {
4773 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4775 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4779 rc = bnxt_hwrm_allocate_pf_only(bp);
4782 "Failed to allocate PF resources");
4788 rc = bnxt_alloc_mem(bp, reconfig_dev);
4792 rc = bnxt_setup_int(bp);
4796 rc = bnxt_request_int(bp);
4800 rc = bnxt_init_ctx_mem(bp);
4802 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4806 rc = bnxt_init_locks(bp);
4814 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4815 const char *value, void *opaque_arg)
4817 struct bnxt *bp = opaque_arg;
4818 unsigned long truflow;
4821 if (!value || !opaque_arg) {
4823 "Invalid parameter passed to truflow devargs.\n");
4827 truflow = strtoul(value, &end, 10);
4828 if (end == NULL || *end != '\0' ||
4829 (truflow == ULONG_MAX && errno == ERANGE)) {
4831 "Invalid parameter passed to truflow devargs.\n");
4835 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4837 "Invalid value passed to truflow devargs.\n");
4842 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4843 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4845 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4846 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4853 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4854 const char *value, void *opaque_arg)
4856 struct bnxt *bp = opaque_arg;
4857 unsigned long flow_xstat;
4860 if (!value || !opaque_arg) {
4862 "Invalid parameter passed to flow_xstat devarg.\n");
4866 flow_xstat = strtoul(value, &end, 10);
4867 if (end == NULL || *end != '\0' ||
4868 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4870 "Invalid parameter passed to flow_xstat devarg.\n");
4874 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4876 "Invalid value passed to flow_xstat devarg.\n");
4880 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4881 if (BNXT_FLOW_XSTATS_EN(bp))
4882 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4888 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4889 const char *value, void *opaque_arg)
4891 struct bnxt *bp = opaque_arg;
4892 unsigned long max_num_kflows;
4895 if (!value || !opaque_arg) {
4897 "Invalid parameter passed to max_num_kflows devarg.\n");
4901 max_num_kflows = strtoul(value, &end, 10);
4902 if (end == NULL || *end != '\0' ||
4903 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4905 "Invalid parameter passed to max_num_kflows devarg.\n");
4909 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4911 "Invalid value passed to max_num_kflows devarg.\n");
4915 bp->max_num_kflows = max_num_kflows;
4916 if (bp->max_num_kflows)
4917 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
4924 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
4925 const char *value, void *opaque_arg)
4927 struct bnxt_representor *vfr_bp = opaque_arg;
4928 unsigned long rep_is_pf;
4931 if (!value || !opaque_arg) {
4933 "Invalid parameter passed to rep_is_pf devargs.\n");
4937 rep_is_pf = strtoul(value, &end, 10);
4938 if (end == NULL || *end != '\0' ||
4939 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
4941 "Invalid parameter passed to rep_is_pf devargs.\n");
4945 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
4947 "Invalid value passed to rep_is_pf devargs.\n");
4951 vfr_bp->flags |= rep_is_pf;
4952 if (BNXT_REP_PF(vfr_bp))
4953 PMD_DRV_LOG(INFO, "PF representor\n");
4955 PMD_DRV_LOG(INFO, "VF representor\n");
4961 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
4962 const char *value, void *opaque_arg)
4964 struct bnxt_representor *vfr_bp = opaque_arg;
4965 unsigned long rep_based_pf;
4968 if (!value || !opaque_arg) {
4970 "Invalid parameter passed to rep_based_pf "
4975 rep_based_pf = strtoul(value, &end, 10);
4976 if (end == NULL || *end != '\0' ||
4977 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
4979 "Invalid parameter passed to rep_based_pf "
4984 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
4986 "Invalid value passed to rep_based_pf devargs.\n");
4990 vfr_bp->rep_based_pf = rep_based_pf;
4991 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
4993 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
4999 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5000 const char *value, void *opaque_arg)
5002 struct bnxt_representor *vfr_bp = opaque_arg;
5003 unsigned long rep_q_r2f;
5006 if (!value || !opaque_arg) {
5008 "Invalid parameter passed to rep_q_r2f "
5013 rep_q_r2f = strtoul(value, &end, 10);
5014 if (end == NULL || *end != '\0' ||
5015 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5017 "Invalid parameter passed to rep_q_r2f "
5022 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5024 "Invalid value passed to rep_q_r2f devargs.\n");
5028 vfr_bp->rep_q_r2f = rep_q_r2f;
5029 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5030 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5036 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5037 const char *value, void *opaque_arg)
5039 struct bnxt_representor *vfr_bp = opaque_arg;
5040 unsigned long rep_q_f2r;
5043 if (!value || !opaque_arg) {
5045 "Invalid parameter passed to rep_q_f2r "
5050 rep_q_f2r = strtoul(value, &end, 10);
5051 if (end == NULL || *end != '\0' ||
5052 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5054 "Invalid parameter passed to rep_q_f2r "
5059 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5061 "Invalid value passed to rep_q_f2r devargs.\n");
5065 vfr_bp->rep_q_f2r = rep_q_f2r;
5066 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5067 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5073 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5074 const char *value, void *opaque_arg)
5076 struct bnxt_representor *vfr_bp = opaque_arg;
5077 unsigned long rep_fc_r2f;
5080 if (!value || !opaque_arg) {
5082 "Invalid parameter passed to rep_fc_r2f "
5087 rep_fc_r2f = strtoul(value, &end, 10);
5088 if (end == NULL || *end != '\0' ||
5089 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5091 "Invalid parameter passed to rep_fc_r2f "
5096 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5098 "Invalid value passed to rep_fc_r2f devargs.\n");
5102 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5103 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5104 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5110 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5111 const char *value, void *opaque_arg)
5113 struct bnxt_representor *vfr_bp = opaque_arg;
5114 unsigned long rep_fc_f2r;
5117 if (!value || !opaque_arg) {
5119 "Invalid parameter passed to rep_fc_f2r "
5124 rep_fc_f2r = strtoul(value, &end, 10);
5125 if (end == NULL || *end != '\0' ||
5126 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5128 "Invalid parameter passed to rep_fc_f2r "
5133 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5135 "Invalid value passed to rep_fc_f2r devargs.\n");
5139 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5140 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5141 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5147 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5149 struct rte_kvargs *kvlist;
5151 if (devargs == NULL)
5154 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5159 * Handler for "truflow" devarg.
5160 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5162 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5163 bnxt_parse_devarg_truflow, bp);
5166 * Handler for "flow_xstat" devarg.
5167 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5169 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5170 bnxt_parse_devarg_flow_xstat, bp);
5173 * Handler for "max_num_kflows" devarg.
5174 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5176 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5177 bnxt_parse_devarg_max_num_kflows, bp);
5179 rte_kvargs_free(kvlist);
5182 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5186 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5187 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5190 "Failed to alloc switch domain: %d\n", rc);
5193 "Switch domain allocated %d\n",
5194 bp->switch_domain_id);
5201 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5203 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5204 static int version_printed;
5208 if (version_printed++ == 0)
5209 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5211 eth_dev->dev_ops = &bnxt_dev_ops;
5212 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5213 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5214 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5215 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5216 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5219 * For secondary processes, we don't initialise any further
5220 * as primary has already done this work.
5222 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5225 rte_eth_copy_pci_info(eth_dev, pci_dev);
5226 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5228 bp = eth_dev->data->dev_private;
5230 /* Parse dev arguments passed on when starting the DPDK application. */
5231 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5233 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5235 if (bnxt_vf_pciid(pci_dev->id.device_id))
5236 bp->flags |= BNXT_FLAG_VF;
5238 if (bnxt_p5_device(pci_dev->id.device_id))
5239 bp->flags |= BNXT_FLAG_CHIP_P5;
5241 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5242 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5243 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5244 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5245 bp->flags |= BNXT_FLAG_STINGRAY;
5247 if (BNXT_TRUFLOW_EN(bp)) {
5248 /* extra mbuf field is required to store CFA code from mark */
5249 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5250 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5251 .size = sizeof(bnxt_cfa_code_dynfield_t),
5252 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5254 bnxt_cfa_code_dynfield_offset =
5255 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5256 if (bnxt_cfa_code_dynfield_offset < 0) {
5258 "Failed to register mbuf field for TruFlow mark\n");
5263 rc = bnxt_init_board(eth_dev);
5266 "Failed to initialize board rc: %x\n", rc);
5270 rc = bnxt_alloc_pf_info(bp);
5274 rc = bnxt_alloc_link_info(bp);
5278 rc = bnxt_alloc_parent_info(bp);
5282 rc = bnxt_alloc_hwrm_resources(bp);
5285 "Failed to allocate hwrm resource rc: %x\n", rc);
5288 rc = bnxt_alloc_leds_info(bp);
5292 rc = bnxt_alloc_cos_queues(bp);
5296 rc = bnxt_init_resources(bp, false);
5300 rc = bnxt_alloc_stats_mem(bp);
5304 bnxt_alloc_switch_domain(bp);
5307 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5308 pci_dev->mem_resource[0].phys_addr,
5309 pci_dev->mem_resource[0].addr);
5314 bnxt_dev_uninit(eth_dev);
5319 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5328 ctx->dma = RTE_BAD_IOVA;
5329 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5332 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5334 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5335 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5336 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5337 bp->flow_stat->max_fc,
5340 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5341 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5342 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5343 bp->flow_stat->max_fc,
5346 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5347 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5348 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5350 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5351 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5352 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5354 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5355 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5356 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5358 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5359 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5360 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5363 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5365 bnxt_unregister_fc_ctx_mem(bp);
5367 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5368 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5369 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5370 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5373 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5375 if (BNXT_FLOW_XSTATS_EN(bp))
5376 bnxt_uninit_fc_ctx_mem(bp);
5380 bnxt_free_error_recovery_info(struct bnxt *bp)
5382 rte_free(bp->recovery_info);
5383 bp->recovery_info = NULL;
5384 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5388 bnxt_uninit_locks(struct bnxt *bp)
5390 pthread_mutex_destroy(&bp->flow_lock);
5391 pthread_mutex_destroy(&bp->def_cp_lock);
5392 pthread_mutex_destroy(&bp->health_check_lock);
5394 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5395 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5400 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5405 bnxt_free_mem(bp, reconfig_dev);
5407 bnxt_hwrm_func_buf_unrgtr(bp);
5408 rte_free(bp->pf->vf_req_buf);
5410 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5411 bp->flags &= ~BNXT_FLAG_REGISTERED;
5412 bnxt_free_ctx_mem(bp);
5413 if (!reconfig_dev) {
5414 bnxt_free_hwrm_resources(bp);
5415 bnxt_free_error_recovery_info(bp);
5418 bnxt_uninit_ctx_mem(bp);
5420 bnxt_uninit_locks(bp);
5421 bnxt_free_flow_stats_info(bp);
5422 bnxt_free_rep_info(bp);
5423 rte_free(bp->ptp_cfg);
5429 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5431 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5434 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5436 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5437 bnxt_dev_close_op(eth_dev);
5442 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5444 struct bnxt *bp = eth_dev->data->dev_private;
5445 struct rte_eth_dev *vf_rep_eth_dev;
5451 for (i = 0; i < bp->num_reps; i++) {
5452 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5453 if (!vf_rep_eth_dev)
5455 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5456 vf_rep_eth_dev->data->port_id);
5457 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5459 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5460 eth_dev->data->port_id);
5461 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5466 static void bnxt_free_rep_info(struct bnxt *bp)
5468 rte_free(bp->rep_info);
5469 bp->rep_info = NULL;
5470 rte_free(bp->cfa_code_map);
5471 bp->cfa_code_map = NULL;
5474 static int bnxt_init_rep_info(struct bnxt *bp)
5481 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5482 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5484 if (!bp->rep_info) {
5485 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5488 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5489 sizeof(*bp->cfa_code_map) *
5490 BNXT_MAX_CFA_CODE, 0);
5491 if (!bp->cfa_code_map) {
5492 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5493 bnxt_free_rep_info(bp);
5497 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5498 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5500 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5502 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5503 bnxt_free_rep_info(bp);
5507 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5509 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5510 bnxt_free_rep_info(bp);
5517 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5518 struct rte_eth_devargs *eth_da,
5519 struct rte_eth_dev *backing_eth_dev,
5520 const char *dev_args)
5522 struct rte_eth_dev *vf_rep_eth_dev;
5523 char name[RTE_ETH_NAME_MAX_LEN];
5524 struct bnxt *backing_bp;
5527 struct rte_kvargs *kvlist = NULL;
5529 num_rep = eth_da->nb_representor_ports;
5530 if (num_rep > BNXT_MAX_VF_REPS) {
5531 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5532 num_rep, BNXT_MAX_VF_REPS);
5536 if (num_rep >= RTE_MAX_ETHPORTS) {
5538 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5539 num_rep, RTE_MAX_ETHPORTS);
5543 backing_bp = backing_eth_dev->data->dev_private;
5545 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5547 "Not a PF or trusted VF. No Representor support\n");
5548 /* Returning an error is not an option.
5549 * Applications are not handling this correctly
5554 if (bnxt_init_rep_info(backing_bp))
5557 for (i = 0; i < num_rep; i++) {
5558 struct bnxt_representor representor = {
5559 .vf_id = eth_da->representor_ports[i],
5560 .switch_domain_id = backing_bp->switch_domain_id,
5561 .parent_dev = backing_eth_dev
5564 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5565 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5566 representor.vf_id, BNXT_MAX_VF_REPS);
5570 /* representor port net_bdf_port */
5571 snprintf(name, sizeof(name), "net_%s_representor_%d",
5572 pci_dev->device.name, eth_da->representor_ports[i]);
5574 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5577 * Handler for "rep_is_pf" devarg.
5578 * Invoked as for ex: "-a 000:00:0d.0,
5579 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5581 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5582 bnxt_parse_devarg_rep_is_pf,
5583 (void *)&representor);
5589 * Handler for "rep_based_pf" devarg.
5590 * Invoked as for ex: "-a 000:00:0d.0,
5591 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5593 ret = rte_kvargs_process(kvlist,
5594 BNXT_DEVARG_REP_BASED_PF,
5595 bnxt_parse_devarg_rep_based_pf,
5596 (void *)&representor);
5602 * Handler for "rep_based_pf" devarg.
5603 * Invoked as for ex: "-a 000:00:0d.0,
5604 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5606 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5607 bnxt_parse_devarg_rep_q_r2f,
5608 (void *)&representor);
5614 * Handler for "rep_based_pf" devarg.
5615 * Invoked as for ex: "-a 000:00:0d.0,
5616 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5618 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5619 bnxt_parse_devarg_rep_q_f2r,
5620 (void *)&representor);
5626 * Handler for "rep_based_pf" devarg.
5627 * Invoked as for ex: "-a 000:00:0d.0,
5628 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5630 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5631 bnxt_parse_devarg_rep_fc_r2f,
5632 (void *)&representor);
5638 * Handler for "rep_based_pf" devarg.
5639 * Invoked as for ex: "-a 000:00:0d.0,
5640 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5642 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5643 bnxt_parse_devarg_rep_fc_f2r,
5644 (void *)&representor);
5651 ret = rte_eth_dev_create(&pci_dev->device, name,
5652 sizeof(struct bnxt_representor),
5654 bnxt_representor_init,
5657 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5658 "representor %s.", name);
5662 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5663 if (!vf_rep_eth_dev) {
5664 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5665 " for VF-Rep: %s.", name);
5670 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5671 backing_eth_dev->data->port_id);
5672 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5674 backing_bp->num_reps++;
5678 rte_kvargs_free(kvlist);
5682 /* If num_rep > 1, then rollback already created
5683 * ports, since we'll be failing the probe anyway
5686 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5688 rte_kvargs_free(kvlist);
5693 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5694 struct rte_pci_device *pci_dev)
5696 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5697 struct rte_eth_dev *backing_eth_dev;
5701 if (pci_dev->device.devargs) {
5702 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5708 num_rep = eth_da.nb_representor_ports;
5709 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5712 /* We could come here after first level of probe is already invoked
5713 * as part of an application bringup(OVS-DPDK vswitchd), so first check
5714 * for already allocated eth_dev for the backing device (PF/Trusted VF)
5716 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5717 if (backing_eth_dev == NULL) {
5718 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5719 sizeof(struct bnxt),
5720 eth_dev_pci_specific_init, pci_dev,
5721 bnxt_dev_init, NULL);
5723 if (ret || !num_rep)
5726 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5728 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5729 backing_eth_dev->data->port_id);
5734 /* probe representor ports now */
5735 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
5736 pci_dev->device.devargs->args);
5741 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5743 struct rte_eth_dev *eth_dev;
5745 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5747 return 0; /* Invoked typically only by OVS-DPDK, by the
5748 * time it comes here the eth_dev is already
5749 * deleted by rte_eth_dev_close(), so returning
5750 * +ve value will at least help in proper cleanup
5753 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5754 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5755 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5756 return rte_eth_dev_destroy(eth_dev,
5757 bnxt_representor_uninit);
5759 return rte_eth_dev_destroy(eth_dev,
5762 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5766 static struct rte_pci_driver bnxt_rte_pmd = {
5767 .id_table = bnxt_pci_id_map,
5768 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5769 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5772 .probe = bnxt_pci_probe,
5773 .remove = bnxt_pci_remove,
5777 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5779 if (strcmp(dev->device->driver->name, drv->driver.name))
5785 bool is_bnxt_supported(struct rte_eth_dev *dev)
5787 return is_device_supported(dev, &bnxt_rte_pmd);
5790 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5791 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5792 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5793 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");