1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
100 #define BNXT_DEVARG_APP_ID "app-id"
102 static const char *const bnxt_dev_args[] = {
103 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_ACCUM_STATS,
105 BNXT_DEVARG_FLOW_XSTAT,
106 BNXT_DEVARG_MAX_NUM_KFLOWS,
107 BNXT_DEVARG_REP_BASED_PF,
108 BNXT_DEVARG_REP_IS_PF,
109 BNXT_DEVARG_REP_Q_R2F,
110 BNXT_DEVARG_REP_Q_F2R,
111 BNXT_DEVARG_REP_FC_R2F,
112 BNXT_DEVARG_REP_FC_F2R,
118 * accum-stats == false to disable flow counter accumulation
119 * accum-stats == true to enable flow counter accumulation
121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1)
124 * app-id = an non-negative 8-bit number
126 #define BNXT_DEVARG_APP_ID_INVALID(val) ((val) > 255)
129 * flow_xstat == false to disable the feature
130 * flow_xstat == true to enable the feature
132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
135 * rep_is_pf == false to indicate VF representor
136 * rep_is_pf == true to indicate PF representor
138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
141 * rep_based_pf == Physical index of the PF
143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
145 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
150 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
155 * rep_fc_r2f == Flow control for the representor to endpoint direction
157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
160 * rep_fc_f2r == Flow control for the endpoint to representor direction
162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
164 int bnxt_cfa_code_dynfield_offset = -1;
167 * max_num_kflows must be >= 32
168 * and must be a power-of-2 supported value
169 * return: 1 -> invalid
172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
174 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
183 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
184 static int bnxt_restore_vlan_filters(struct bnxt *bp);
185 static void bnxt_dev_recover(void *arg);
186 static void bnxt_free_error_recovery_info(struct bnxt *bp);
187 static void bnxt_free_rep_info(struct bnxt *bp);
189 int is_bnxt_in_error(struct bnxt *bp)
191 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
193 if (bp->flags & BNXT_FLAG_FW_RESET)
199 /***********************/
202 * High level utility functions
205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
207 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
208 BNXT_RSS_TBL_SIZE_P5);
210 if (!BNXT_CHIP_P5(bp))
213 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
214 BNXT_RSS_ENTRIES_PER_CTX_P5) /
215 BNXT_RSS_ENTRIES_PER_CTX_P5;
218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
220 if (!BNXT_CHIP_P5(bp))
221 return HW_HASH_INDEX_SIZE;
223 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
226 static void bnxt_free_parent_info(struct bnxt *bp)
228 rte_free(bp->parent);
232 static void bnxt_free_pf_info(struct bnxt *bp)
238 static void bnxt_free_link_info(struct bnxt *bp)
240 rte_free(bp->link_info);
241 bp->link_info = NULL;
244 static void bnxt_free_leds_info(struct bnxt *bp)
253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
255 rte_free(bp->flow_stat);
256 bp->flow_stat = NULL;
259 static void bnxt_free_cos_queues(struct bnxt *bp)
261 rte_free(bp->rx_cos_queue);
262 bp->rx_cos_queue = NULL;
263 rte_free(bp->tx_cos_queue);
264 bp->tx_cos_queue = NULL;
267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
269 bnxt_free_filter_mem(bp);
270 bnxt_free_vnic_attributes(bp);
271 bnxt_free_vnic_mem(bp);
273 /* tx/rx rings are configured as part of *_queue_setup callbacks.
274 * If the number of rings change across fw update,
275 * we don't have much choice except to warn the user.
279 bnxt_free_tx_rings(bp);
280 bnxt_free_rx_rings(bp);
282 bnxt_free_async_cp_ring(bp);
283 bnxt_free_rxtx_nq_ring(bp);
285 rte_free(bp->grp_info);
289 static int bnxt_alloc_parent_info(struct bnxt *bp)
291 bp->parent = rte_zmalloc("bnxt_parent_info",
292 sizeof(struct bnxt_parent_info), 0);
293 if (bp->parent == NULL)
299 static int bnxt_alloc_pf_info(struct bnxt *bp)
301 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
308 static int bnxt_alloc_link_info(struct bnxt *bp)
311 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
312 if (bp->link_info == NULL)
318 static int bnxt_alloc_leds_info(struct bnxt *bp)
323 bp->leds = rte_zmalloc("bnxt_leds",
324 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
326 if (bp->leds == NULL)
332 static int bnxt_alloc_cos_queues(struct bnxt *bp)
335 rte_zmalloc("bnxt_rx_cosq",
336 BNXT_COS_QUEUE_COUNT *
337 sizeof(struct bnxt_cos_queue_info),
339 if (bp->rx_cos_queue == NULL)
343 rte_zmalloc("bnxt_tx_cosq",
344 BNXT_COS_QUEUE_COUNT *
345 sizeof(struct bnxt_cos_queue_info),
347 if (bp->tx_cos_queue == NULL)
353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
355 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
356 sizeof(struct bnxt_flow_stat_info), 0);
357 if (bp->flow_stat == NULL)
363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
367 rc = bnxt_alloc_ring_grps(bp);
371 rc = bnxt_alloc_async_ring_struct(bp);
375 rc = bnxt_alloc_vnic_mem(bp);
379 rc = bnxt_alloc_vnic_attributes(bp);
383 rc = bnxt_alloc_filter_mem(bp);
387 rc = bnxt_alloc_async_cp_ring(bp);
391 rc = bnxt_alloc_rxtx_nq_ring(bp);
395 if (BNXT_FLOW_XSTATS_EN(bp)) {
396 rc = bnxt_alloc_flow_stats_info(bp);
404 bnxt_free_mem(bp, reconfig);
408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
410 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
411 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
412 uint64_t rx_offloads = dev_conf->rxmode.offloads;
413 struct bnxt_rx_queue *rxq;
417 rc = bnxt_vnic_grp_alloc(bp, vnic);
421 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
422 vnic_id, vnic, vnic->fw_grp_ids);
424 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
428 /* Alloc RSS context only if RSS mode is enabled */
429 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
430 int j, nr_ctxs = bnxt_rss_ctxts(bp);
432 /* RSS table size in Thor is 512.
433 * Cap max Rx rings to same value
435 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
436 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
437 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
442 for (j = 0; j < nr_ctxs; j++) {
443 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
449 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
453 vnic->num_lb_ctxts = nr_ctxs;
457 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
458 * setting is not available at this time, it will not be
459 * configured correctly in the CFA.
461 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
462 vnic->vlan_strip = true;
464 vnic->vlan_strip = false;
466 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
470 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
474 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
475 rxq = bp->eth_dev->data->rx_queues[j];
478 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
479 j, rxq->vnic, rxq->vnic->fw_grp_ids);
481 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
482 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
484 vnic->rx_queue_cnt++;
487 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
489 rc = bnxt_vnic_rss_configure(bp, vnic);
493 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
495 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
496 (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
503 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
512 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
513 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
518 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
519 " rx_fc_in_tbl.ctx_id = %d\n",
520 bp->flow_stat->rx_fc_in_tbl.va,
521 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
522 bp->flow_stat->rx_fc_in_tbl.ctx_id);
524 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
525 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
530 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
531 " rx_fc_out_tbl.ctx_id = %d\n",
532 bp->flow_stat->rx_fc_out_tbl.va,
533 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
534 bp->flow_stat->rx_fc_out_tbl.ctx_id);
536 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
537 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
542 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
543 " tx_fc_in_tbl.ctx_id = %d\n",
544 bp->flow_stat->tx_fc_in_tbl.va,
545 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
546 bp->flow_stat->tx_fc_in_tbl.ctx_id);
548 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
549 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
554 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
555 " tx_fc_out_tbl.ctx_id = %d\n",
556 bp->flow_stat->tx_fc_out_tbl.va,
557 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
558 bp->flow_stat->tx_fc_out_tbl.ctx_id);
560 memset(bp->flow_stat->rx_fc_out_tbl.va,
562 bp->flow_stat->rx_fc_out_tbl.size);
563 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
564 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
565 bp->flow_stat->rx_fc_out_tbl.ctx_id,
566 bp->flow_stat->max_fc,
571 memset(bp->flow_stat->tx_fc_out_tbl.va,
573 bp->flow_stat->tx_fc_out_tbl.size);
574 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
575 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
576 bp->flow_stat->tx_fc_out_tbl.ctx_id,
577 bp->flow_stat->max_fc,
583 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
584 struct bnxt_ctx_mem_buf_info *ctx)
589 ctx->va = rte_zmalloc_socket(type, size, 0,
590 bp->eth_dev->device->numa_node);
593 rte_mem_lock_page(ctx->va);
595 ctx->dma = rte_mem_virt2iova(ctx->va);
596 if (ctx->dma == RTE_BAD_IOVA)
602 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
604 struct rte_pci_device *pdev = bp->pdev;
605 char type[RTE_MEMZONE_NAMESIZE];
609 max_fc = bp->flow_stat->max_fc;
611 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
612 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
613 /* 4 bytes for each counter-id */
614 rc = bnxt_alloc_ctx_mem_buf(bp, type,
616 &bp->flow_stat->rx_fc_in_tbl);
620 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
621 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
622 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
623 rc = bnxt_alloc_ctx_mem_buf(bp, type,
625 &bp->flow_stat->rx_fc_out_tbl);
629 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
630 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
631 /* 4 bytes for each counter-id */
632 rc = bnxt_alloc_ctx_mem_buf(bp, type,
634 &bp->flow_stat->tx_fc_in_tbl);
638 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
639 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
640 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
641 rc = bnxt_alloc_ctx_mem_buf(bp, type,
643 &bp->flow_stat->tx_fc_out_tbl);
647 rc = bnxt_register_fc_ctx_mem(bp);
652 static int bnxt_init_ctx_mem(struct bnxt *bp)
656 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
657 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
658 !BNXT_FLOW_XSTATS_EN(bp))
661 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
665 rc = bnxt_init_fc_ctx_mem(bp);
670 static int bnxt_update_phy_setting(struct bnxt *bp)
672 struct rte_eth_link new;
675 rc = bnxt_get_hwrm_link_config(bp, &new);
677 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
682 * On BCM957508-N2100 adapters, FW will not allow any user other
683 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
684 * always returns link up. Force phy update always in that case.
686 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
687 rc = bnxt_set_hwrm_link_config(bp, true);
689 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
697 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
699 rte_free(bp->prev_rx_ring_stats);
700 rte_free(bp->prev_tx_ring_stats);
702 bp->prev_rx_ring_stats = NULL;
703 bp->prev_tx_ring_stats = NULL;
706 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
708 bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats",
709 sizeof(struct bnxt_ring_stats) *
712 if (bp->prev_rx_ring_stats == NULL)
715 bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
716 sizeof(struct bnxt_ring_stats) *
719 if (bp->prev_tx_ring_stats == NULL)
725 bnxt_free_prev_ring_stats(bp);
729 static int bnxt_start_nic(struct bnxt *bp)
731 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
732 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
733 uint32_t intr_vector = 0;
734 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
735 uint32_t vec = BNXT_MISC_VEC_ID;
739 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
740 bp->eth_dev->data->dev_conf.rxmode.offloads |=
741 DEV_RX_OFFLOAD_JUMBO_FRAME;
742 bp->flags |= BNXT_FLAG_JUMBO;
744 bp->eth_dev->data->dev_conf.rxmode.offloads &=
745 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
746 bp->flags &= ~BNXT_FLAG_JUMBO;
749 /* THOR does not support ring groups.
750 * But we will use the array to save RSS context IDs.
752 if (BNXT_CHIP_P5(bp))
753 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
755 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
757 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
761 rc = bnxt_alloc_hwrm_rings(bp);
763 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
767 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
769 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
773 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
776 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
777 if (bp->rx_cos_queue[i].id != 0xff) {
778 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
782 "Num pools more than FW profile\n");
786 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
792 rc = bnxt_mq_rx_configure(bp);
794 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
799 rc = bnxt_setup_one_vnic(bp, 0);
802 /* VNIC configuration */
803 if (BNXT_RFS_NEEDS_VNIC(bp)) {
804 for (i = 1; i < bp->nr_vnics; i++) {
805 rc = bnxt_setup_one_vnic(bp, i);
811 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
814 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
818 /* check and configure queue intr-vector mapping */
819 if ((rte_intr_cap_multiple(intr_handle) ||
820 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
821 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
822 intr_vector = bp->eth_dev->data->nb_rx_queues;
823 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
824 if (intr_vector > bp->rx_cp_nr_rings) {
825 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
829 rc = rte_intr_efd_enable(intr_handle, intr_vector);
834 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
835 intr_handle->intr_vec =
836 rte_zmalloc("intr_vec",
837 bp->eth_dev->data->nb_rx_queues *
839 if (intr_handle->intr_vec == NULL) {
840 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
841 " intr_vec", bp->eth_dev->data->nb_rx_queues);
845 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
846 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
847 intr_handle->intr_vec, intr_handle->nb_efd,
848 intr_handle->max_intr);
849 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
851 intr_handle->intr_vec[queue_id] =
852 vec + BNXT_RX_VEC_START;
853 if (vec < base + intr_handle->nb_efd - 1)
858 /* enable uio/vfio intr/eventfd mapping */
859 rc = rte_intr_enable(intr_handle);
860 #ifndef RTE_EXEC_ENV_FREEBSD
861 /* In FreeBSD OS, nic_uio driver does not support interrupts */
866 rc = bnxt_update_phy_setting(bp);
870 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
872 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
877 /* Some of the error status returned by FW may not be from errno.h */
884 static int bnxt_shutdown_nic(struct bnxt *bp)
886 bnxt_free_all_hwrm_resources(bp);
887 bnxt_free_all_filters(bp);
888 bnxt_free_all_vnics(bp);
893 * Device configuration and status function
896 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
898 uint32_t link_speed = 0;
899 uint32_t speed_capa = 0;
901 if (bp->link_info == NULL)
904 link_speed = bp->link_info->support_speeds;
906 /* If PAM4 is configured, use PAM4 supported speed */
907 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
908 link_speed = bp->link_info->support_pam4_speeds;
910 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
911 speed_capa |= ETH_LINK_SPEED_100M;
912 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
913 speed_capa |= ETH_LINK_SPEED_100M_HD;
914 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
915 speed_capa |= ETH_LINK_SPEED_1G;
916 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
917 speed_capa |= ETH_LINK_SPEED_2_5G;
918 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
919 speed_capa |= ETH_LINK_SPEED_10G;
920 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
921 speed_capa |= ETH_LINK_SPEED_20G;
922 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
923 speed_capa |= ETH_LINK_SPEED_25G;
924 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
925 speed_capa |= ETH_LINK_SPEED_40G;
926 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
927 speed_capa |= ETH_LINK_SPEED_50G;
928 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
929 speed_capa |= ETH_LINK_SPEED_100G;
930 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
931 speed_capa |= ETH_LINK_SPEED_50G;
932 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
933 speed_capa |= ETH_LINK_SPEED_100G;
934 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
935 speed_capa |= ETH_LINK_SPEED_200G;
937 if (bp->link_info->auto_mode ==
938 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
939 speed_capa |= ETH_LINK_SPEED_FIXED;
944 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
945 struct rte_eth_dev_info *dev_info)
947 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
948 struct bnxt *bp = eth_dev->data->dev_private;
949 uint16_t max_vnics, i, j, vpool, vrxq;
950 unsigned int max_rx_rings;
953 rc = is_bnxt_in_error(bp);
958 dev_info->max_mac_addrs = bp->max_l2_ctx;
959 dev_info->max_hash_mac_addrs = 0;
961 /* PF/VF specifics */
963 dev_info->max_vfs = pdev->max_vfs;
965 max_rx_rings = bnxt_max_rings(bp);
966 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
967 dev_info->max_rx_queues = max_rx_rings;
968 dev_info->max_tx_queues = max_rx_rings;
969 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
970 dev_info->hash_key_size = HW_HASH_KEY_SIZE;
971 max_vnics = bp->max_vnics;
974 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
975 dev_info->max_mtu = BNXT_MAX_MTU;
977 /* Fast path specifics */
978 dev_info->min_rx_bufsize = 1;
979 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
981 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
982 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
983 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
984 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
985 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
986 dev_info->tx_queue_offload_capa;
987 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
989 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
991 dev_info->default_rxconf = (struct rte_eth_rxconf) {
997 .rx_free_thresh = 32,
998 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
1001 dev_info->default_txconf = (struct rte_eth_txconf) {
1007 .tx_free_thresh = 32,
1010 eth_dev->data->dev_conf.intr_conf.lsc = 1;
1012 eth_dev->data->dev_conf.intr_conf.rxq = 1;
1013 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1014 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1015 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1016 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1018 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1019 dev_info->switch_info.name = eth_dev->device->name;
1020 dev_info->switch_info.domain_id = bp->switch_domain_id;
1021 dev_info->switch_info.port_id =
1022 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1023 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1027 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1028 * need further investigation.
1031 /* VMDq resources */
1032 vpool = 64; /* ETH_64_POOLS */
1033 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1034 for (i = 0; i < 4; vpool >>= 1, i++) {
1035 if (max_vnics > vpool) {
1036 for (j = 0; j < 5; vrxq >>= 1, j++) {
1037 if (dev_info->max_rx_queues > vrxq) {
1043 /* Not enough resources to support VMDq */
1047 /* Not enough resources to support VMDq */
1051 dev_info->max_vmdq_pools = vpool;
1052 dev_info->vmdq_queue_num = vrxq;
1054 dev_info->vmdq_pool_base = 0;
1055 dev_info->vmdq_queue_base = 0;
1060 /* Configure the device based on the configuration provided */
1061 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1063 struct bnxt *bp = eth_dev->data->dev_private;
1064 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1067 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1068 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1069 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1070 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1072 rc = is_bnxt_in_error(bp);
1076 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1077 rc = bnxt_hwrm_check_vf_rings(bp);
1079 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1083 /* If a resource has already been allocated - in this case
1084 * it is the async completion ring, free it. Reallocate it after
1085 * resource reservation. This will ensure the resource counts
1086 * are calculated correctly.
1089 pthread_mutex_lock(&bp->def_cp_lock);
1091 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1092 bnxt_disable_int(bp);
1093 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1096 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1098 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1099 pthread_mutex_unlock(&bp->def_cp_lock);
1103 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1104 rc = bnxt_alloc_async_cp_ring(bp);
1106 pthread_mutex_unlock(&bp->def_cp_lock);
1109 bnxt_enable_int(bp);
1112 pthread_mutex_unlock(&bp->def_cp_lock);
1115 /* Inherit new configurations */
1116 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1117 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1118 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1119 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1120 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1122 goto resource_error;
1124 if (BNXT_HAS_RING_GRPS(bp) &&
1125 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1126 goto resource_error;
1128 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1129 bp->max_vnics < eth_dev->data->nb_rx_queues)
1130 goto resource_error;
1132 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1133 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1135 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1136 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1137 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1139 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1140 eth_dev->data->mtu =
1141 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1142 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1144 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1150 "Insufficient resources to support requested config\n");
1152 "Num Queues Requested: Tx %d, Rx %d\n",
1153 eth_dev->data->nb_tx_queues,
1154 eth_dev->data->nb_rx_queues);
1156 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1157 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1158 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1162 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1164 struct rte_eth_link *link = ð_dev->data->dev_link;
1166 if (link->link_status)
1167 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1168 eth_dev->data->port_id,
1169 (uint32_t)link->link_speed,
1170 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1171 ("full-duplex") : ("half-duplex\n"));
1173 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1174 eth_dev->data->port_id);
1178 * Determine whether the current configuration requires support for scattered
1179 * receive; return 1 if scattered receive is required and 0 if not.
1181 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1186 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1189 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1192 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1193 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1195 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1196 RTE_PKTMBUF_HEADROOM);
1197 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1203 static eth_rx_burst_t
1204 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1206 struct bnxt *bp = eth_dev->data->dev_private;
1208 /* Disable vector mode RX for Stingray2 for now */
1209 if (BNXT_CHIP_SR2(bp)) {
1210 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1211 return bnxt_recv_pkts;
1214 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1215 !defined(RTE_LIBRTE_IEEE1588)
1217 /* Vector mode receive cannot be enabled if scattered rx is in use. */
1218 if (eth_dev->data->scattered_rx)
1222 * Vector mode receive cannot be enabled if Truflow is enabled or if
1223 * asynchronous completions and receive completions can be placed in
1224 * the same completion ring.
1226 if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1230 * Vector mode receive cannot be enabled if any receive offloads outside
1231 * a limited subset have been enabled.
1233 if (eth_dev->data->dev_conf.rxmode.offloads &
1234 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1235 DEV_RX_OFFLOAD_KEEP_CRC |
1236 DEV_RX_OFFLOAD_JUMBO_FRAME |
1237 DEV_RX_OFFLOAD_IPV4_CKSUM |
1238 DEV_RX_OFFLOAD_UDP_CKSUM |
1239 DEV_RX_OFFLOAD_TCP_CKSUM |
1240 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1241 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1242 DEV_RX_OFFLOAD_RSS_HASH |
1243 DEV_RX_OFFLOAD_VLAN_FILTER))
1246 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1247 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1248 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1250 "Using AVX2 vector mode receive for port %d\n",
1251 eth_dev->data->port_id);
1252 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1253 return bnxt_recv_pkts_vec_avx2;
1256 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1258 "Using SSE vector mode receive for port %d\n",
1259 eth_dev->data->port_id);
1260 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1261 return bnxt_recv_pkts_vec;
1265 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1266 eth_dev->data->port_id);
1268 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1269 eth_dev->data->port_id,
1270 eth_dev->data->scattered_rx,
1271 eth_dev->data->dev_conf.rxmode.offloads);
1273 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1274 return bnxt_recv_pkts;
1277 static eth_tx_burst_t
1278 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1280 struct bnxt *bp = eth_dev->data->dev_private;
1282 /* Disable vector mode TX for Stingray2 for now */
1283 if (BNXT_CHIP_SR2(bp))
1284 return bnxt_xmit_pkts;
1286 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1287 !defined(RTE_LIBRTE_IEEE1588)
1288 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1291 * Vector mode transmit can be enabled only if not using scatter rx
1294 if (eth_dev->data->scattered_rx ||
1295 (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1296 BNXT_TRUFLOW_EN(bp))
1299 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1300 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1301 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1303 "Using AVX2 vector mode transmit for port %d\n",
1304 eth_dev->data->port_id);
1305 return bnxt_xmit_pkts_vec_avx2;
1308 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1310 "Using SSE vector mode transmit for port %d\n",
1311 eth_dev->data->port_id);
1312 return bnxt_xmit_pkts_vec;
1316 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1317 eth_dev->data->port_id);
1319 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1320 eth_dev->data->port_id,
1321 eth_dev->data->scattered_rx,
1324 return bnxt_xmit_pkts;
1327 static int bnxt_handle_if_change_status(struct bnxt *bp)
1331 /* Since fw has undergone a reset and lost all contexts,
1332 * set fatal flag to not issue hwrm during cleanup
1334 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1335 bnxt_uninit_resources(bp, true);
1337 /* clear fatal flag so that re-init happens */
1338 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1339 rc = bnxt_init_resources(bp, true);
1341 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1346 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1348 struct bnxt *bp = eth_dev->data->dev_private;
1351 if (!BNXT_SINGLE_PF(bp))
1354 if (!bp->link_info->link_up)
1355 rc = bnxt_set_hwrm_link_config(bp, true);
1357 eth_dev->data->dev_link.link_status = 1;
1359 bnxt_print_link_info(eth_dev);
1363 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1365 struct bnxt *bp = eth_dev->data->dev_private;
1367 if (!BNXT_SINGLE_PF(bp))
1370 eth_dev->data->dev_link.link_status = 0;
1371 bnxt_set_hwrm_link_config(bp, false);
1372 bp->link_info->link_up = 0;
1377 static void bnxt_free_switch_domain(struct bnxt *bp)
1381 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1384 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1386 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1387 bp->switch_domain_id, rc);
1390 static void bnxt_ptp_get_current_time(void *arg)
1392 struct bnxt *bp = arg;
1393 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1396 rc = is_bnxt_in_error(bp);
1403 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1404 &ptp->current_time);
1406 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1408 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1409 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1413 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1415 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1418 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1421 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1422 &ptp->current_time);
1424 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1428 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1430 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1431 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1432 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1436 static void bnxt_ptp_stop(struct bnxt *bp)
1438 bnxt_cancel_ptp_alarm(bp);
1439 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1442 static int bnxt_ptp_start(struct bnxt *bp)
1446 rc = bnxt_schedule_ptp_alarm(bp);
1448 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1450 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1451 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1457 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1459 struct bnxt *bp = eth_dev->data->dev_private;
1460 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1461 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1462 struct rte_eth_link link;
1465 eth_dev->data->dev_started = 0;
1466 eth_dev->data->scattered_rx = 0;
1468 /* Prevent crashes when queues are still in use */
1469 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1470 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1472 bnxt_disable_int(bp);
1474 /* disable uio/vfio intr/eventfd mapping */
1475 rte_intr_disable(intr_handle);
1477 /* Stop the child representors for this device */
1478 ret = bnxt_rep_stop_all(bp);
1482 /* delete the bnxt ULP port details */
1483 bnxt_ulp_port_deinit(bp);
1485 bnxt_cancel_fw_health_check(bp);
1487 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1488 bnxt_cancel_ptp_alarm(bp);
1490 /* Do not bring link down during reset recovery */
1491 if (!is_bnxt_in_error(bp)) {
1492 bnxt_dev_set_link_down_op(eth_dev);
1493 /* Wait for link to be reset */
1494 if (BNXT_SINGLE_PF(bp))
1496 /* clear the recorded link status */
1497 memset(&link, 0, sizeof(link));
1498 rte_eth_linkstatus_set(eth_dev, &link);
1501 /* Clean queue intr-vector mapping */
1502 rte_intr_efd_disable(intr_handle);
1503 if (intr_handle->intr_vec != NULL) {
1504 rte_free(intr_handle->intr_vec);
1505 intr_handle->intr_vec = NULL;
1508 bnxt_hwrm_port_clr_stats(bp);
1509 bnxt_free_tx_mbufs(bp);
1510 bnxt_free_rx_mbufs(bp);
1511 /* Process any remaining notifications in default completion queue */
1512 bnxt_int_handler(eth_dev);
1513 bnxt_shutdown_nic(bp);
1514 bnxt_hwrm_if_change(bp, false);
1516 bnxt_free_prev_ring_stats(bp);
1517 rte_free(bp->mark_table);
1518 bp->mark_table = NULL;
1520 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1521 bp->rx_cosq_cnt = 0;
1522 /* All filters are deleted on a port stop. */
1523 if (BNXT_FLOW_XSTATS_EN(bp))
1524 bp->flow_stat->flow_count = 0;
1529 /* Unload the driver, release resources */
1530 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1532 struct bnxt *bp = eth_dev->data->dev_private;
1534 pthread_mutex_lock(&bp->err_recovery_lock);
1535 if (bp->flags & BNXT_FLAG_FW_RESET) {
1537 "Adapter recovering from error..Please retry\n");
1538 pthread_mutex_unlock(&bp->err_recovery_lock);
1541 pthread_mutex_unlock(&bp->err_recovery_lock);
1543 return bnxt_dev_stop(eth_dev);
1546 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1548 struct bnxt *bp = eth_dev->data->dev_private;
1549 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1551 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1553 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1554 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1558 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1560 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1561 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1564 rc = bnxt_hwrm_if_change(bp, true);
1565 if (rc == 0 || rc != -EAGAIN)
1568 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1569 } while (retry_cnt--);
1574 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1575 rc = bnxt_handle_if_change_status(bp);
1580 bnxt_enable_int(bp);
1582 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1584 rc = bnxt_start_nic(bp);
1588 rc = bnxt_alloc_prev_ring_stats(bp);
1592 eth_dev->data->dev_started = 1;
1594 bnxt_link_update_op(eth_dev, 1);
1596 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1597 vlan_mask |= ETH_VLAN_FILTER_MASK;
1598 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1599 vlan_mask |= ETH_VLAN_STRIP_MASK;
1600 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1604 /* Initialize bnxt ULP port details */
1605 rc = bnxt_ulp_port_init(bp);
1609 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1610 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1612 bnxt_schedule_fw_health_check(bp);
1614 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1615 bnxt_schedule_ptp_alarm(bp);
1620 bnxt_dev_stop(eth_dev);
1625 bnxt_uninit_locks(struct bnxt *bp)
1627 pthread_mutex_destroy(&bp->flow_lock);
1628 pthread_mutex_destroy(&bp->def_cp_lock);
1629 pthread_mutex_destroy(&bp->health_check_lock);
1630 pthread_mutex_destroy(&bp->err_recovery_lock);
1632 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1633 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1637 static void bnxt_drv_uninit(struct bnxt *bp)
1639 bnxt_free_leds_info(bp);
1640 bnxt_free_cos_queues(bp);
1641 bnxt_free_link_info(bp);
1642 bnxt_free_parent_info(bp);
1643 bnxt_uninit_locks(bp);
1645 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1646 bp->tx_mem_zone = NULL;
1647 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1648 bp->rx_mem_zone = NULL;
1650 bnxt_free_vf_info(bp);
1651 bnxt_free_pf_info(bp);
1653 rte_free(bp->grp_info);
1654 bp->grp_info = NULL;
1657 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1659 struct bnxt *bp = eth_dev->data->dev_private;
1662 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1665 pthread_mutex_lock(&bp->err_recovery_lock);
1666 if (bp->flags & BNXT_FLAG_FW_RESET) {
1668 "Adapter recovering from error...Please retry\n");
1669 pthread_mutex_unlock(&bp->err_recovery_lock);
1672 pthread_mutex_unlock(&bp->err_recovery_lock);
1674 /* cancel the recovery handler before remove dev */
1675 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1676 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1677 bnxt_cancel_fc_thread(bp);
1679 if (eth_dev->data->dev_started)
1680 ret = bnxt_dev_stop(eth_dev);
1682 bnxt_uninit_resources(bp, false);
1684 bnxt_drv_uninit(bp);
1689 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1692 struct bnxt *bp = eth_dev->data->dev_private;
1693 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1694 struct bnxt_vnic_info *vnic;
1695 struct bnxt_filter_info *filter, *temp_filter;
1698 if (is_bnxt_in_error(bp))
1702 * Loop through all VNICs from the specified filter flow pools to
1703 * remove the corresponding MAC addr filter
1705 for (i = 0; i < bp->nr_vnics; i++) {
1706 if (!(pool_mask & (1ULL << i)))
1709 vnic = &bp->vnic_info[i];
1710 filter = STAILQ_FIRST(&vnic->filter);
1712 temp_filter = STAILQ_NEXT(filter, next);
1713 if (filter->mac_index == index) {
1714 STAILQ_REMOVE(&vnic->filter, filter,
1715 bnxt_filter_info, next);
1716 bnxt_hwrm_clear_l2_filter(bp, filter);
1717 bnxt_free_filter(bp, filter);
1719 filter = temp_filter;
1724 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1725 struct rte_ether_addr *mac_addr, uint32_t index,
1728 struct bnxt_filter_info *filter;
1731 /* Attach requested MAC address to the new l2_filter */
1732 STAILQ_FOREACH(filter, &vnic->filter, next) {
1733 if (filter->mac_index == index) {
1735 "MAC addr already existed for pool %d\n",
1741 filter = bnxt_alloc_filter(bp);
1743 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1747 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1748 * if the MAC that's been programmed now is a different one, then,
1749 * copy that addr to filter->l2_addr
1752 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1753 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1755 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1757 filter->mac_index = index;
1758 if (filter->mac_index == 0)
1759 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1761 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1763 bnxt_free_filter(bp, filter);
1769 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1770 struct rte_ether_addr *mac_addr,
1771 uint32_t index, uint32_t pool)
1773 struct bnxt *bp = eth_dev->data->dev_private;
1774 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1777 rc = is_bnxt_in_error(bp);
1781 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1782 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1787 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1791 /* Filter settings will get applied when port is started */
1792 if (!eth_dev->data->dev_started)
1795 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1800 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1803 struct bnxt *bp = eth_dev->data->dev_private;
1804 struct rte_eth_link new;
1805 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1806 BNXT_MIN_LINK_WAIT_CNT;
1808 rc = is_bnxt_in_error(bp);
1812 memset(&new, 0, sizeof(new));
1814 if (bp->link_info == NULL)
1818 /* Retrieve link info from hardware */
1819 rc = bnxt_get_hwrm_link_config(bp, &new);
1821 new.link_speed = ETH_LINK_SPEED_100M;
1822 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1824 "Failed to retrieve link rc = 0x%x!\n", rc);
1828 if (!wait_to_complete || new.link_status)
1831 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1834 /* Only single function PF can bring phy down.
1835 * When port is stopped, report link down for VF/MH/NPAR functions.
1837 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1838 memset(&new, 0, sizeof(new));
1841 /* Timed out or success */
1842 if (new.link_status != eth_dev->data->dev_link.link_status ||
1843 new.link_speed != eth_dev->data->dev_link.link_speed) {
1844 rte_eth_linkstatus_set(eth_dev, &new);
1846 rte_eth_dev_callback_process(eth_dev,
1847 RTE_ETH_EVENT_INTR_LSC,
1850 bnxt_print_link_info(eth_dev);
1856 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1858 struct bnxt *bp = eth_dev->data->dev_private;
1859 struct bnxt_vnic_info *vnic;
1863 rc = is_bnxt_in_error(bp);
1867 /* Filter settings will get applied when port is started */
1868 if (!eth_dev->data->dev_started)
1871 if (bp->vnic_info == NULL)
1874 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1876 old_flags = vnic->flags;
1877 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1878 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1880 vnic->flags = old_flags;
1885 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1887 struct bnxt *bp = eth_dev->data->dev_private;
1888 struct bnxt_vnic_info *vnic;
1892 rc = is_bnxt_in_error(bp);
1896 /* Filter settings will get applied when port is started */
1897 if (!eth_dev->data->dev_started)
1900 if (bp->vnic_info == NULL)
1903 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1905 old_flags = vnic->flags;
1906 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1907 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1909 vnic->flags = old_flags;
1914 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1916 struct bnxt *bp = eth_dev->data->dev_private;
1917 struct bnxt_vnic_info *vnic;
1921 rc = is_bnxt_in_error(bp);
1925 /* Filter settings will get applied when port is started */
1926 if (!eth_dev->data->dev_started)
1929 if (bp->vnic_info == NULL)
1932 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1934 old_flags = vnic->flags;
1935 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1936 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1938 vnic->flags = old_flags;
1943 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1945 struct bnxt *bp = eth_dev->data->dev_private;
1946 struct bnxt_vnic_info *vnic;
1950 rc = is_bnxt_in_error(bp);
1954 /* Filter settings will get applied when port is started */
1955 if (!eth_dev->data->dev_started)
1958 if (bp->vnic_info == NULL)
1961 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1963 old_flags = vnic->flags;
1964 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1965 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1967 vnic->flags = old_flags;
1972 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1973 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1975 if (qid >= bp->rx_nr_rings)
1978 return bp->eth_dev->data->rx_queues[qid];
1981 /* Return rxq corresponding to a given rss table ring/group ID. */
1982 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1984 struct bnxt_rx_queue *rxq;
1987 if (!BNXT_HAS_RING_GRPS(bp)) {
1988 for (i = 0; i < bp->rx_nr_rings; i++) {
1989 rxq = bp->eth_dev->data->rx_queues[i];
1990 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1994 for (i = 0; i < bp->rx_nr_rings; i++) {
1995 if (bp->grp_info[i].fw_grp_id == fwr)
2000 return INVALID_HW_RING_ID;
2003 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2004 struct rte_eth_rss_reta_entry64 *reta_conf,
2007 struct bnxt *bp = eth_dev->data->dev_private;
2008 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2009 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2010 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2014 rc = is_bnxt_in_error(bp);
2018 if (!vnic->rss_table)
2021 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2024 if (reta_size != tbl_size) {
2025 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2026 "(%d) must equal the size supported by the hardware "
2027 "(%d)\n", reta_size, tbl_size);
2031 for (i = 0; i < reta_size; i++) {
2032 struct bnxt_rx_queue *rxq;
2034 idx = i / RTE_RETA_GROUP_SIZE;
2035 sft = i % RTE_RETA_GROUP_SIZE;
2037 if (!(reta_conf[idx].mask & (1ULL << sft)))
2040 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2042 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2046 if (BNXT_CHIP_P5(bp)) {
2047 vnic->rss_table[i * 2] =
2048 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2049 vnic->rss_table[i * 2 + 1] =
2050 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2052 vnic->rss_table[i] =
2053 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2057 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2061 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2062 struct rte_eth_rss_reta_entry64 *reta_conf,
2065 struct bnxt *bp = eth_dev->data->dev_private;
2066 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2067 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2068 uint16_t idx, sft, i;
2071 rc = is_bnxt_in_error(bp);
2077 if (!vnic->rss_table)
2080 if (reta_size != tbl_size) {
2081 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2082 "(%d) must equal the size supported by the hardware "
2083 "(%d)\n", reta_size, tbl_size);
2087 for (idx = 0, i = 0; i < reta_size; i++) {
2088 idx = i / RTE_RETA_GROUP_SIZE;
2089 sft = i % RTE_RETA_GROUP_SIZE;
2091 if (reta_conf[idx].mask & (1ULL << sft)) {
2094 if (BNXT_CHIP_P5(bp))
2095 qid = bnxt_rss_to_qid(bp,
2096 vnic->rss_table[i * 2]);
2098 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2100 if (qid == INVALID_HW_RING_ID) {
2101 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2104 reta_conf[idx].reta[sft] = qid;
2111 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2112 struct rte_eth_rss_conf *rss_conf)
2114 struct bnxt *bp = eth_dev->data->dev_private;
2115 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2116 struct bnxt_vnic_info *vnic;
2119 rc = is_bnxt_in_error(bp);
2124 * If RSS enablement were different than dev_configure,
2125 * then return -EINVAL
2127 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2128 if (!rss_conf->rss_hf)
2129 PMD_DRV_LOG(ERR, "Hash type NONE\n");
2131 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2135 bp->flags |= BNXT_FLAG_UPDATE_HASH;
2136 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
2140 /* Update the default RSS VNIC(s) */
2141 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2142 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2144 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2145 ETH_RSS_LEVEL(rss_conf->rss_hf));
2148 * If hashkey is not specified, use the previously configured
2151 if (!rss_conf->rss_key)
2154 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2156 "Invalid hashkey length, should be %d bytes\n",
2160 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2163 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2167 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2168 struct rte_eth_rss_conf *rss_conf)
2170 struct bnxt *bp = eth_dev->data->dev_private;
2171 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2173 uint32_t hash_types;
2175 rc = is_bnxt_in_error(bp);
2179 /* RSS configuration is the same for all VNICs */
2180 if (vnic && vnic->rss_hash_key) {
2181 if (rss_conf->rss_key) {
2182 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2183 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2184 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2187 hash_types = vnic->hash_type;
2188 rss_conf->rss_hf = 0;
2189 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2190 rss_conf->rss_hf |= ETH_RSS_IPV4;
2191 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2193 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2194 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2196 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2198 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2199 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2201 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2203 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2204 rss_conf->rss_hf |= ETH_RSS_IPV6;
2205 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2207 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2208 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2210 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2212 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2213 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2215 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2219 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2223 "Unknown RSS config from firmware (%08x), RSS disabled",
2228 rss_conf->rss_hf = 0;
2233 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2234 struct rte_eth_fc_conf *fc_conf)
2236 struct bnxt *bp = dev->data->dev_private;
2237 struct rte_eth_link link_info;
2240 rc = is_bnxt_in_error(bp);
2244 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2248 memset(fc_conf, 0, sizeof(*fc_conf));
2249 if (bp->link_info->auto_pause)
2250 fc_conf->autoneg = 1;
2251 switch (bp->link_info->pause) {
2253 fc_conf->mode = RTE_FC_NONE;
2255 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2256 fc_conf->mode = RTE_FC_TX_PAUSE;
2258 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2259 fc_conf->mode = RTE_FC_RX_PAUSE;
2261 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2262 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2263 fc_conf->mode = RTE_FC_FULL;
2269 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2270 struct rte_eth_fc_conf *fc_conf)
2272 struct bnxt *bp = dev->data->dev_private;
2275 rc = is_bnxt_in_error(bp);
2279 if (!BNXT_SINGLE_PF(bp)) {
2281 "Flow Control Settings cannot be modified on VF or on shared PF\n");
2285 switch (fc_conf->mode) {
2287 bp->link_info->auto_pause = 0;
2288 bp->link_info->force_pause = 0;
2290 case RTE_FC_RX_PAUSE:
2291 if (fc_conf->autoneg) {
2292 bp->link_info->auto_pause =
2293 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2294 bp->link_info->force_pause = 0;
2296 bp->link_info->auto_pause = 0;
2297 bp->link_info->force_pause =
2298 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2301 case RTE_FC_TX_PAUSE:
2302 if (fc_conf->autoneg) {
2303 bp->link_info->auto_pause =
2304 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2305 bp->link_info->force_pause = 0;
2307 bp->link_info->auto_pause = 0;
2308 bp->link_info->force_pause =
2309 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2313 if (fc_conf->autoneg) {
2314 bp->link_info->auto_pause =
2315 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2316 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2317 bp->link_info->force_pause = 0;
2319 bp->link_info->auto_pause = 0;
2320 bp->link_info->force_pause =
2321 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2322 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2326 return bnxt_set_hwrm_link_config(bp, true);
2329 /* Add UDP tunneling port */
2331 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2332 struct rte_eth_udp_tunnel *udp_tunnel)
2334 struct bnxt *bp = eth_dev->data->dev_private;
2335 uint16_t tunnel_type = 0;
2338 rc = is_bnxt_in_error(bp);
2342 switch (udp_tunnel->prot_type) {
2343 case RTE_TUNNEL_TYPE_VXLAN:
2344 if (bp->vxlan_port_cnt) {
2345 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2346 udp_tunnel->udp_port);
2347 if (bp->vxlan_port != udp_tunnel->udp_port) {
2348 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2351 bp->vxlan_port_cnt++;
2355 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2356 bp->vxlan_port_cnt++;
2358 case RTE_TUNNEL_TYPE_GENEVE:
2359 if (bp->geneve_port_cnt) {
2360 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2361 udp_tunnel->udp_port);
2362 if (bp->geneve_port != udp_tunnel->udp_port) {
2363 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2366 bp->geneve_port_cnt++;
2370 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2371 bp->geneve_port_cnt++;
2374 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2377 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2383 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2384 struct rte_eth_udp_tunnel *udp_tunnel)
2386 struct bnxt *bp = eth_dev->data->dev_private;
2387 uint16_t tunnel_type = 0;
2391 rc = is_bnxt_in_error(bp);
2395 switch (udp_tunnel->prot_type) {
2396 case RTE_TUNNEL_TYPE_VXLAN:
2397 if (!bp->vxlan_port_cnt) {
2398 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2401 if (bp->vxlan_port != udp_tunnel->udp_port) {
2402 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2403 udp_tunnel->udp_port, bp->vxlan_port);
2406 if (--bp->vxlan_port_cnt)
2410 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2411 port = bp->vxlan_fw_dst_port_id;
2413 case RTE_TUNNEL_TYPE_GENEVE:
2414 if (!bp->geneve_port_cnt) {
2415 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2418 if (bp->geneve_port != udp_tunnel->udp_port) {
2419 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2420 udp_tunnel->udp_port, bp->geneve_port);
2423 if (--bp->geneve_port_cnt)
2427 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2428 port = bp->geneve_fw_dst_port_id;
2431 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2435 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2439 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2441 struct bnxt_filter_info *filter;
2442 struct bnxt_vnic_info *vnic;
2444 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2446 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2447 filter = STAILQ_FIRST(&vnic->filter);
2449 /* Search for this matching MAC+VLAN filter */
2450 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2451 /* Delete the filter */
2452 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2455 STAILQ_REMOVE(&vnic->filter, filter,
2456 bnxt_filter_info, next);
2457 bnxt_free_filter(bp, filter);
2459 "Deleted vlan filter for %d\n",
2463 filter = STAILQ_NEXT(filter, next);
2468 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2470 struct bnxt_filter_info *filter;
2471 struct bnxt_vnic_info *vnic;
2473 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2474 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2475 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2477 /* Implementation notes on the use of VNIC in this command:
2479 * By default, these filters belong to default vnic for the function.
2480 * Once these filters are set up, only destination VNIC can be modified.
2481 * If the destination VNIC is not specified in this command,
2482 * then the HWRM shall only create an l2 context id.
2485 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2486 filter = STAILQ_FIRST(&vnic->filter);
2487 /* Check if the VLAN has already been added */
2489 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2492 filter = STAILQ_NEXT(filter, next);
2495 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2496 * command to create MAC+VLAN filter with the right flags, enables set.
2498 filter = bnxt_alloc_filter(bp);
2501 "MAC/VLAN filter alloc failed\n");
2504 /* MAC + VLAN ID filter */
2505 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2506 * untagged packets are received
2508 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2509 * packets and only the programmed vlan's packets are received
2511 filter->l2_ivlan = vlan_id;
2512 filter->l2_ivlan_mask = 0x0FFF;
2513 filter->enables |= en;
2514 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2516 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2518 /* Free the newly allocated filter as we were
2519 * not able to create the filter in hardware.
2521 bnxt_free_filter(bp, filter);
2525 filter->mac_index = 0;
2526 /* Add this new filter to the list */
2528 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2530 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2533 "Added Vlan filter for %d\n", vlan_id);
2537 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2538 uint16_t vlan_id, int on)
2540 struct bnxt *bp = eth_dev->data->dev_private;
2543 rc = is_bnxt_in_error(bp);
2547 if (!eth_dev->data->dev_started) {
2548 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2552 /* These operations apply to ALL existing MAC/VLAN filters */
2554 return bnxt_add_vlan_filter(bp, vlan_id);
2556 return bnxt_del_vlan_filter(bp, vlan_id);
2559 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2560 struct bnxt_vnic_info *vnic)
2562 struct bnxt_filter_info *filter;
2565 filter = STAILQ_FIRST(&vnic->filter);
2567 if (filter->mac_index == 0 &&
2568 !memcmp(filter->l2_addr, bp->mac_addr,
2569 RTE_ETHER_ADDR_LEN)) {
2570 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2572 STAILQ_REMOVE(&vnic->filter, filter,
2573 bnxt_filter_info, next);
2574 bnxt_free_filter(bp, filter);
2578 filter = STAILQ_NEXT(filter, next);
2584 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2586 struct bnxt_vnic_info *vnic;
2590 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2591 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2592 /* Remove any VLAN filters programmed */
2593 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2594 bnxt_del_vlan_filter(bp, i);
2596 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2600 /* Default filter will allow packets that match the
2601 * dest mac. So, it has to be deleted, otherwise, we
2602 * will endup receiving vlan packets for which the
2603 * filter is not programmed, when hw-vlan-filter
2604 * configuration is ON
2606 bnxt_del_dflt_mac_filter(bp, vnic);
2607 /* This filter will allow only untagged packets */
2608 bnxt_add_vlan_filter(bp, 0);
2610 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2611 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2616 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2618 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2622 /* Destroy vnic filters and vnic */
2623 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2624 DEV_RX_OFFLOAD_VLAN_FILTER) {
2625 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2626 bnxt_del_vlan_filter(bp, i);
2628 bnxt_del_dflt_mac_filter(bp, vnic);
2630 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2634 rc = bnxt_hwrm_vnic_free(bp, vnic);
2638 rte_free(vnic->fw_grp_ids);
2639 vnic->fw_grp_ids = NULL;
2641 vnic->rx_queue_cnt = 0;
2647 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2649 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2652 /* Destroy, recreate and reconfigure the default vnic */
2653 rc = bnxt_free_one_vnic(bp, 0);
2657 /* default vnic 0 */
2658 rc = bnxt_setup_one_vnic(bp, 0);
2662 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2663 DEV_RX_OFFLOAD_VLAN_FILTER) {
2664 rc = bnxt_add_vlan_filter(bp, 0);
2667 rc = bnxt_restore_vlan_filters(bp);
2671 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2676 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2680 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2681 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2687 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2689 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2690 struct bnxt *bp = dev->data->dev_private;
2693 rc = is_bnxt_in_error(bp);
2697 /* Filter settings will get applied when port is started */
2698 if (!dev->data->dev_started)
2701 if (mask & ETH_VLAN_FILTER_MASK) {
2702 /* Enable or disable VLAN filtering */
2703 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2708 if (mask & ETH_VLAN_STRIP_MASK) {
2709 /* Enable or disable VLAN stripping */
2710 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2715 if (mask & ETH_VLAN_EXTEND_MASK) {
2716 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2717 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2719 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2726 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2729 struct bnxt *bp = dev->data->dev_private;
2730 int qinq = dev->data->dev_conf.rxmode.offloads &
2731 DEV_RX_OFFLOAD_VLAN_EXTEND;
2733 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2734 vlan_type != ETH_VLAN_TYPE_OUTER) {
2736 "Unsupported vlan type.");
2741 "QinQ not enabled. Needs to be ON as we can "
2742 "accelerate only outer vlan\n");
2746 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2748 case RTE_ETHER_TYPE_QINQ:
2750 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2752 case RTE_ETHER_TYPE_VLAN:
2754 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2756 case RTE_ETHER_TYPE_QINQ1:
2758 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2760 case RTE_ETHER_TYPE_QINQ2:
2762 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2764 case RTE_ETHER_TYPE_QINQ3:
2766 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2769 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2772 bp->outer_tpid_bd |= tpid;
2773 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2774 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2776 "Can accelerate only outer vlan in QinQ\n");
2784 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2785 struct rte_ether_addr *addr)
2787 struct bnxt *bp = dev->data->dev_private;
2788 /* Default Filter is tied to VNIC 0 */
2789 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2792 rc = is_bnxt_in_error(bp);
2796 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2799 if (rte_is_zero_ether_addr(addr))
2802 /* Filter settings will get applied when port is started */
2803 if (!dev->data->dev_started)
2806 /* Check if the requested MAC is already added */
2807 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2810 /* Destroy filter and re-create it */
2811 bnxt_del_dflt_mac_filter(bp, vnic);
2813 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2814 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2815 /* This filter will allow only untagged packets */
2816 rc = bnxt_add_vlan_filter(bp, 0);
2818 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2821 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2826 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2827 struct rte_ether_addr *mc_addr_set,
2828 uint32_t nb_mc_addr)
2830 struct bnxt *bp = eth_dev->data->dev_private;
2831 char *mc_addr_list = (char *)mc_addr_set;
2832 struct bnxt_vnic_info *vnic;
2833 uint32_t off = 0, i = 0;
2836 rc = is_bnxt_in_error(bp);
2840 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2842 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2843 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2847 /* TODO Check for Duplicate mcast addresses */
2848 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2849 for (i = 0; i < nb_mc_addr; i++) {
2850 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2851 RTE_ETHER_ADDR_LEN);
2852 off += RTE_ETHER_ADDR_LEN;
2855 vnic->mc_addr_cnt = i;
2856 if (vnic->mc_addr_cnt)
2857 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2859 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2862 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2866 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2868 struct bnxt *bp = dev->data->dev_private;
2869 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2870 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2871 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2872 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2875 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2876 fw_major, fw_minor, fw_updt, fw_rsvd);
2880 ret += 1; /* add the size of '\0' */
2881 if (fw_size < (size_t)ret)
2888 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2889 struct rte_eth_rxq_info *qinfo)
2891 struct bnxt *bp = dev->data->dev_private;
2892 struct bnxt_rx_queue *rxq;
2894 if (is_bnxt_in_error(bp))
2897 rxq = dev->data->rx_queues[queue_id];
2899 qinfo->mp = rxq->mb_pool;
2900 qinfo->scattered_rx = dev->data->scattered_rx;
2901 qinfo->nb_desc = rxq->nb_rx_desc;
2903 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2904 qinfo->conf.rx_drop_en = rxq->drop_en;
2905 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2906 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2910 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2911 struct rte_eth_txq_info *qinfo)
2913 struct bnxt *bp = dev->data->dev_private;
2914 struct bnxt_tx_queue *txq;
2916 if (is_bnxt_in_error(bp))
2919 txq = dev->data->tx_queues[queue_id];
2921 qinfo->nb_desc = txq->nb_tx_desc;
2923 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2924 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2925 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2927 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2928 qinfo->conf.tx_rs_thresh = 0;
2929 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2930 qinfo->conf.offloads = txq->offloads;
2933 static const struct {
2934 eth_rx_burst_t pkt_burst;
2936 } bnxt_rx_burst_info[] = {
2937 {bnxt_recv_pkts, "Scalar"},
2938 #if defined(RTE_ARCH_X86)
2939 {bnxt_recv_pkts_vec, "Vector SSE"},
2941 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2942 {bnxt_recv_pkts_vec_avx2, "Vector AVX2"},
2944 #if defined(RTE_ARCH_ARM64)
2945 {bnxt_recv_pkts_vec, "Vector Neon"},
2950 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2951 struct rte_eth_burst_mode *mode)
2953 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2956 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2957 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2958 snprintf(mode->info, sizeof(mode->info), "%s",
2959 bnxt_rx_burst_info[i].info);
2967 static const struct {
2968 eth_tx_burst_t pkt_burst;
2970 } bnxt_tx_burst_info[] = {
2971 {bnxt_xmit_pkts, "Scalar"},
2972 #if defined(RTE_ARCH_X86)
2973 {bnxt_xmit_pkts_vec, "Vector SSE"},
2975 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2976 {bnxt_xmit_pkts_vec_avx2, "Vector AVX2"},
2978 #if defined(RTE_ARCH_ARM64)
2979 {bnxt_xmit_pkts_vec, "Vector Neon"},
2984 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2985 struct rte_eth_burst_mode *mode)
2987 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2990 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2991 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2992 snprintf(mode->info, sizeof(mode->info), "%s",
2993 bnxt_tx_burst_info[i].info);
3001 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
3003 struct bnxt *bp = eth_dev->data->dev_private;
3004 uint32_t new_pkt_size;
3008 rc = is_bnxt_in_error(bp);
3012 /* Exit if receive queues are not configured yet */
3013 if (!eth_dev->data->nb_rx_queues)
3016 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
3017 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
3020 * Disallow any MTU change that would require scattered receive support
3021 * if it is not already enabled.
3023 if (eth_dev->data->dev_started &&
3024 !eth_dev->data->scattered_rx &&
3026 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3028 "MTU change would require scattered rx support. ");
3029 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3033 if (new_mtu > RTE_ETHER_MTU) {
3034 bp->flags |= BNXT_FLAG_JUMBO;
3035 bp->eth_dev->data->dev_conf.rxmode.offloads |=
3036 DEV_RX_OFFLOAD_JUMBO_FRAME;
3038 bp->eth_dev->data->dev_conf.rxmode.offloads &=
3039 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3040 bp->flags &= ~BNXT_FLAG_JUMBO;
3043 /* Is there a change in mtu setting? */
3044 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
3047 for (i = 0; i < bp->nr_vnics; i++) {
3048 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3051 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3052 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3056 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3057 size -= RTE_PKTMBUF_HEADROOM;
3059 if (size < new_mtu) {
3060 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3067 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
3069 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3075 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3077 struct bnxt *bp = dev->data->dev_private;
3078 uint16_t vlan = bp->vlan;
3081 rc = is_bnxt_in_error(bp);
3085 if (!BNXT_SINGLE_PF(bp)) {
3086 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3089 bp->vlan = on ? pvid : 0;
3091 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3098 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3100 struct bnxt *bp = dev->data->dev_private;
3103 rc = is_bnxt_in_error(bp);
3107 return bnxt_hwrm_port_led_cfg(bp, true);
3111 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3113 struct bnxt *bp = dev->data->dev_private;
3116 rc = is_bnxt_in_error(bp);
3120 return bnxt_hwrm_port_led_cfg(bp, false);
3124 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3126 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3127 struct bnxt_cp_ring_info *cpr;
3128 uint32_t desc = 0, raw_cons;
3129 struct bnxt_rx_queue *rxq;
3130 struct rx_pkt_cmpl *rxcmp;
3133 rc = is_bnxt_in_error(bp);
3137 rxq = dev->data->rx_queues[rx_queue_id];
3139 raw_cons = cpr->cp_raw_cons;
3142 uint32_t agg_cnt, cons, cmpl_type;
3144 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3145 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3147 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3150 cmpl_type = CMP_TYPE(rxcmp);
3152 switch (cmpl_type) {
3153 case CMPL_BASE_TYPE_RX_L2:
3154 case CMPL_BASE_TYPE_RX_L2_V2:
3155 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3156 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3160 case CMPL_BASE_TYPE_RX_TPA_END:
3161 if (BNXT_CHIP_P5(rxq->bp)) {
3162 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3164 p5_tpa_end = (void *)rxcmp;
3165 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3167 struct rx_tpa_end_cmpl *tpa_end;
3169 tpa_end = (void *)rxcmp;
3170 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3173 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3178 raw_cons += CMP_LEN(cmpl_type);
3186 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3188 struct bnxt_rx_queue *rxq = rx_queue;
3189 struct bnxt_cp_ring_info *cpr;
3190 struct bnxt_rx_ring_info *rxr;
3191 uint32_t desc, raw_cons;
3192 struct bnxt *bp = rxq->bp;
3193 struct rx_pkt_cmpl *rxcmp;
3196 rc = is_bnxt_in_error(bp);
3200 if (offset >= rxq->nb_rx_desc)
3207 * For the vector receive case, the completion at the requested
3208 * offset can be indexed directly.
3210 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3211 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3212 struct rx_pkt_cmpl *rxcmp;
3215 /* Check status of completion descriptor. */
3216 raw_cons = cpr->cp_raw_cons +
3217 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3218 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3219 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3221 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3222 return RTE_ETH_RX_DESC_DONE;
3224 /* Check whether rx desc has an mbuf attached. */
3225 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3226 if (cons >= rxq->rxrearm_start &&
3227 cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3228 return RTE_ETH_RX_DESC_UNAVAIL;
3231 return RTE_ETH_RX_DESC_AVAIL;
3236 * For the non-vector receive case, scan the completion ring to
3237 * locate the completion descriptor for the requested offset.
3239 raw_cons = cpr->cp_raw_cons;
3242 uint32_t agg_cnt, cons, cmpl_type;
3244 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3245 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3247 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3250 cmpl_type = CMP_TYPE(rxcmp);
3252 switch (cmpl_type) {
3253 case CMPL_BASE_TYPE_RX_L2:
3254 case CMPL_BASE_TYPE_RX_L2_V2:
3255 if (desc == offset) {
3256 cons = rxcmp->opaque;
3257 if (rxr->rx_buf_ring[cons])
3258 return RTE_ETH_RX_DESC_DONE;
3260 return RTE_ETH_RX_DESC_UNAVAIL;
3262 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3263 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3267 case CMPL_BASE_TYPE_RX_TPA_END:
3269 return RTE_ETH_RX_DESC_DONE;
3271 if (BNXT_CHIP_P5(rxq->bp)) {
3272 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3274 p5_tpa_end = (void *)rxcmp;
3275 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3277 struct rx_tpa_end_cmpl *tpa_end;
3279 tpa_end = (void *)rxcmp;
3280 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3283 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3288 raw_cons += CMP_LEN(cmpl_type);
3292 return RTE_ETH_RX_DESC_AVAIL;
3296 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3298 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3299 struct bnxt_tx_ring_info *txr;
3300 struct bnxt_cp_ring_info *cpr;
3301 struct rte_mbuf **tx_buf;
3302 struct tx_pkt_cmpl *txcmp;
3303 uint32_t cons, cp_cons;
3309 rc = is_bnxt_in_error(txq->bp);
3316 if (offset >= txq->nb_tx_desc)
3319 cons = RING_CMP(cpr->cp_ring_struct, offset);
3320 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3321 cp_cons = cpr->cp_raw_cons;
3323 if (cons > cp_cons) {
3324 if (CMPL_VALID(txcmp, cpr->valid))
3325 return RTE_ETH_TX_DESC_UNAVAIL;
3327 if (CMPL_VALID(txcmp, !cpr->valid))
3328 return RTE_ETH_TX_DESC_UNAVAIL;
3330 tx_buf = &txr->tx_buf_ring[cons];
3331 if (*tx_buf == NULL)
3332 return RTE_ETH_TX_DESC_DONE;
3334 return RTE_ETH_TX_DESC_FULL;
3338 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3339 const struct rte_flow_ops **ops)
3341 struct bnxt *bp = dev->data->dev_private;
3347 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3348 struct bnxt_representor *vfr = dev->data->dev_private;
3349 bp = vfr->parent_dev->data->dev_private;
3350 /* parent is deleted while children are still valid */
3352 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3353 dev->data->port_id);
3358 ret = is_bnxt_in_error(bp);
3362 /* PMD supports thread-safe flow operations. rte_flow API
3363 * functions can avoid mutex for multi-thread safety.
3365 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3367 if (BNXT_TRUFLOW_EN(bp))
3368 *ops = &bnxt_ulp_rte_flow_ops;
3370 *ops = &bnxt_flow_ops;
3375 static const uint32_t *
3376 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3378 static const uint32_t ptypes[] = {
3379 RTE_PTYPE_L2_ETHER_VLAN,
3380 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3381 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3385 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3386 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3387 RTE_PTYPE_INNER_L4_ICMP,
3388 RTE_PTYPE_INNER_L4_TCP,
3389 RTE_PTYPE_INNER_L4_UDP,
3393 if (!dev->rx_pkt_burst)
3399 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3402 uint32_t reg_base = *reg_arr & 0xfffff000;
3406 for (i = 0; i < count; i++) {
3407 if ((reg_arr[i] & 0xfffff000) != reg_base)
3410 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3411 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3415 static int bnxt_map_ptp_regs(struct bnxt *bp)
3417 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3421 reg_arr = ptp->rx_regs;
3422 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3426 reg_arr = ptp->tx_regs;
3427 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3431 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3432 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3434 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3435 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3440 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3442 rte_write32(0, (uint8_t *)bp->bar0 +
3443 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3444 rte_write32(0, (uint8_t *)bp->bar0 +
3445 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3448 static uint64_t bnxt_cc_read(struct bnxt *bp)
3452 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3453 BNXT_GRCPF_REG_SYNC_TIME));
3454 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3455 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3459 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3461 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3464 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3465 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3466 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3469 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3470 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3471 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3472 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3473 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3474 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3475 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3480 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3482 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3483 struct bnxt_pf_info *pf = bp->pf;
3488 if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3491 port_id = pf->port_id;
3492 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3493 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3494 while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3495 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3496 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3497 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3498 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3499 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3500 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3501 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3502 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3506 if (i >= BNXT_PTP_RX_PND_CNT)
3512 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3514 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3515 struct bnxt_pf_info *pf = bp->pf;
3519 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3520 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3521 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3524 port_id = pf->port_id;
3525 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3526 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3528 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3529 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3530 if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3531 return bnxt_clr_rx_ts(bp, ts);
3533 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3534 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3535 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3536 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3542 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3545 struct bnxt *bp = dev->data->dev_private;
3546 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3551 ns = rte_timespec_to_ns(ts);
3552 /* Set the timecounters to a new value. */
3554 ptp->tx_tstamp_tc.nsec = ns;
3555 ptp->rx_tstamp_tc.nsec = ns;
3561 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3563 struct bnxt *bp = dev->data->dev_private;
3564 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3565 uint64_t ns, systime_cycles = 0;
3571 if (BNXT_CHIP_P5(bp))
3572 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3575 systime_cycles = bnxt_cc_read(bp);
3577 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3578 *ts = rte_ns_to_timespec(ns);
3583 bnxt_timesync_enable(struct rte_eth_dev *dev)
3585 struct bnxt *bp = dev->data->dev_private;
3586 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3594 ptp->tx_tstamp_en = 1;
3595 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3597 rc = bnxt_hwrm_ptp_cfg(bp);
3601 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3602 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3603 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3605 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3606 ptp->tc.cc_shift = shift;
3607 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3609 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3610 ptp->rx_tstamp_tc.cc_shift = shift;
3611 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3613 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3614 ptp->tx_tstamp_tc.cc_shift = shift;
3615 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3617 if (!BNXT_CHIP_P5(bp))
3618 bnxt_map_ptp_regs(bp);
3620 rc = bnxt_ptp_start(bp);
3626 bnxt_timesync_disable(struct rte_eth_dev *dev)
3628 struct bnxt *bp = dev->data->dev_private;
3629 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3635 ptp->tx_tstamp_en = 0;
3638 bnxt_hwrm_ptp_cfg(bp);
3640 if (!BNXT_CHIP_P5(bp))
3641 bnxt_unmap_ptp_regs(bp);
3649 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3650 struct timespec *timestamp,
3651 uint32_t flags __rte_unused)
3653 struct bnxt *bp = dev->data->dev_private;
3654 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3655 uint64_t rx_tstamp_cycles = 0;
3661 if (BNXT_CHIP_P5(bp))
3662 rx_tstamp_cycles = ptp->rx_timestamp;
3664 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3666 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3667 *timestamp = rte_ns_to_timespec(ns);
3672 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3673 struct timespec *timestamp)
3675 struct bnxt *bp = dev->data->dev_private;
3676 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3677 uint64_t tx_tstamp_cycles = 0;
3684 if (BNXT_CHIP_P5(bp))
3685 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3688 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3690 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3691 *timestamp = rte_ns_to_timespec(ns);
3697 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3699 struct bnxt *bp = dev->data->dev_private;
3700 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3705 ptp->tc.nsec += delta;
3706 ptp->tx_tstamp_tc.nsec += delta;
3707 ptp->rx_tstamp_tc.nsec += delta;
3713 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3715 struct bnxt *bp = dev->data->dev_private;
3717 uint32_t dir_entries;
3718 uint32_t entry_length;
3720 rc = is_bnxt_in_error(bp);
3724 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3725 bp->pdev->addr.domain, bp->pdev->addr.bus,
3726 bp->pdev->addr.devid, bp->pdev->addr.function);
3728 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3732 return dir_entries * entry_length;
3736 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3737 struct rte_dev_eeprom_info *in_eeprom)
3739 struct bnxt *bp = dev->data->dev_private;
3744 rc = is_bnxt_in_error(bp);
3748 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3749 bp->pdev->addr.domain, bp->pdev->addr.bus,
3750 bp->pdev->addr.devid, bp->pdev->addr.function,
3751 in_eeprom->offset, in_eeprom->length);
3753 if (in_eeprom->offset == 0) /* special offset value to get directory */
3754 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3757 index = in_eeprom->offset >> 24;
3758 offset = in_eeprom->offset & 0xffffff;
3761 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3762 in_eeprom->length, in_eeprom->data);
3767 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3770 case BNX_DIR_TYPE_CHIMP_PATCH:
3771 case BNX_DIR_TYPE_BOOTCODE:
3772 case BNX_DIR_TYPE_BOOTCODE_2:
3773 case BNX_DIR_TYPE_APE_FW:
3774 case BNX_DIR_TYPE_APE_PATCH:
3775 case BNX_DIR_TYPE_KONG_FW:
3776 case BNX_DIR_TYPE_KONG_PATCH:
3777 case BNX_DIR_TYPE_BONO_FW:
3778 case BNX_DIR_TYPE_BONO_PATCH:
3786 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3789 case BNX_DIR_TYPE_AVS:
3790 case BNX_DIR_TYPE_EXP_ROM_MBA:
3791 case BNX_DIR_TYPE_PCIE:
3792 case BNX_DIR_TYPE_TSCF_UCODE:
3793 case BNX_DIR_TYPE_EXT_PHY:
3794 case BNX_DIR_TYPE_CCM:
3795 case BNX_DIR_TYPE_ISCSI_BOOT:
3796 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3797 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3805 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3807 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3808 bnxt_dir_type_is_other_exec_format(dir_type);
3812 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3813 struct rte_dev_eeprom_info *in_eeprom)
3815 struct bnxt *bp = dev->data->dev_private;
3816 uint8_t index, dir_op;
3817 uint16_t type, ext, ordinal, attr;
3820 rc = is_bnxt_in_error(bp);
3824 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3825 bp->pdev->addr.domain, bp->pdev->addr.bus,
3826 bp->pdev->addr.devid, bp->pdev->addr.function,
3827 in_eeprom->offset, in_eeprom->length);
3830 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3834 type = in_eeprom->magic >> 16;
3836 if (type == 0xffff) { /* special value for directory operations */
3837 index = in_eeprom->magic & 0xff;
3838 dir_op = in_eeprom->magic >> 8;
3842 case 0x0e: /* erase */
3843 if (in_eeprom->offset != ~in_eeprom->magic)
3845 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3851 /* Create or re-write an NVM item: */
3852 if (bnxt_dir_type_is_executable(type) == true)
3854 ext = in_eeprom->magic & 0xffff;
3855 ordinal = in_eeprom->offset >> 16;
3856 attr = in_eeprom->offset & 0xffff;
3858 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3859 in_eeprom->data, in_eeprom->length);
3862 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3863 struct rte_eth_dev_module_info *modinfo)
3865 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3866 struct bnxt *bp = dev->data->dev_private;
3869 /* No point in going further if phy status indicates
3870 * module is not inserted or if it is powered down or
3871 * if it is of type 10GBase-T
3873 if (bp->link_info->module_status >
3874 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3875 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3876 dev->data->port_id);
3880 /* This feature is not supported in older firmware versions */
3881 if (bp->hwrm_spec_code < 0x10202) {
3882 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3883 dev->data->port_id);
3887 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3888 SFF_DIAG_SUPPORT_OFFSET + 1,
3894 switch (module_info[0]) {
3895 case SFF_MODULE_ID_SFP:
3896 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3897 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3898 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3899 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3901 case SFF_MODULE_ID_QSFP:
3902 case SFF_MODULE_ID_QSFP_PLUS:
3903 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3904 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3906 case SFF_MODULE_ID_QSFP28:
3907 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3908 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3909 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3910 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3913 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3917 PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3918 dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3923 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3924 struct rte_dev_eeprom_info *info)
3926 uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3927 uint32_t offset = info->offset, length = info->length;
3928 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3929 struct bnxt *bp = dev->data->dev_private;
3930 uint8_t *data = info->data;
3931 uint8_t page = offset >> 7;
3932 uint8_t max_pages = 2;
3936 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3937 SFF_DIAG_SUPPORT_OFFSET + 1,
3942 switch (module_info[0]) {
3943 case SFF_MODULE_ID_SFP:
3944 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3945 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3946 pg_addr[2] = I2C_DEV_ADDR_A2;
3947 pg_addr[3] = I2C_DEV_ADDR_A2;
3951 case SFF_MODULE_ID_QSFP28:
3952 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3953 SFF8636_OPT_PAGES_OFFSET,
3958 if (opt_pages & SFF8636_PAGE1_MASK) {
3959 pg_addr[2] = I2C_DEV_ADDR_A0;
3962 if (opt_pages & SFF8636_PAGE2_MASK) {
3963 pg_addr[3] = I2C_DEV_ADDR_A0;
3966 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
3967 pg_addr[4] = I2C_DEV_ADDR_A0;
3975 memset(data, 0, length);
3978 while (length && page < max_pages) {
3979 uint8_t raw_page = page ? page - 1 : 0;
3982 if (pg_addr[page] == I2C_DEV_ADDR_A2)
3986 chunk = RTE_MIN(length, 256 - offset);
3988 if (pg_addr[page]) {
3989 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
3999 page += 1 + (chunk > 128);
4002 return length ? -EINVAL : 0;
4009 static const struct eth_dev_ops bnxt_dev_ops = {
4010 .dev_infos_get = bnxt_dev_info_get_op,
4011 .dev_close = bnxt_dev_close_op,
4012 .dev_configure = bnxt_dev_configure_op,
4013 .dev_start = bnxt_dev_start_op,
4014 .dev_stop = bnxt_dev_stop_op,
4015 .dev_set_link_up = bnxt_dev_set_link_up_op,
4016 .dev_set_link_down = bnxt_dev_set_link_down_op,
4017 .stats_get = bnxt_stats_get_op,
4018 .stats_reset = bnxt_stats_reset_op,
4019 .rx_queue_setup = bnxt_rx_queue_setup_op,
4020 .rx_queue_release = bnxt_rx_queue_release_op,
4021 .tx_queue_setup = bnxt_tx_queue_setup_op,
4022 .tx_queue_release = bnxt_tx_queue_release_op,
4023 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4024 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4025 .reta_update = bnxt_reta_update_op,
4026 .reta_query = bnxt_reta_query_op,
4027 .rss_hash_update = bnxt_rss_hash_update_op,
4028 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4029 .link_update = bnxt_link_update_op,
4030 .promiscuous_enable = bnxt_promiscuous_enable_op,
4031 .promiscuous_disable = bnxt_promiscuous_disable_op,
4032 .allmulticast_enable = bnxt_allmulticast_enable_op,
4033 .allmulticast_disable = bnxt_allmulticast_disable_op,
4034 .mac_addr_add = bnxt_mac_addr_add_op,
4035 .mac_addr_remove = bnxt_mac_addr_remove_op,
4036 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4037 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4038 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4039 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4040 .vlan_filter_set = bnxt_vlan_filter_set_op,
4041 .vlan_offload_set = bnxt_vlan_offload_set_op,
4042 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4043 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4044 .mtu_set = bnxt_mtu_set_op,
4045 .mac_addr_set = bnxt_set_default_mac_addr_op,
4046 .xstats_get = bnxt_dev_xstats_get_op,
4047 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4048 .xstats_reset = bnxt_dev_xstats_reset_op,
4049 .fw_version_get = bnxt_fw_version_get,
4050 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4051 .rxq_info_get = bnxt_rxq_info_get_op,
4052 .txq_info_get = bnxt_txq_info_get_op,
4053 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4054 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4055 .dev_led_on = bnxt_dev_led_on_op,
4056 .dev_led_off = bnxt_dev_led_off_op,
4057 .rx_queue_start = bnxt_rx_queue_start,
4058 .rx_queue_stop = bnxt_rx_queue_stop,
4059 .tx_queue_start = bnxt_tx_queue_start,
4060 .tx_queue_stop = bnxt_tx_queue_stop,
4061 .flow_ops_get = bnxt_flow_ops_get_op,
4062 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4063 .get_eeprom_length = bnxt_get_eeprom_length_op,
4064 .get_eeprom = bnxt_get_eeprom_op,
4065 .set_eeprom = bnxt_set_eeprom_op,
4066 .get_module_info = bnxt_get_module_info,
4067 .get_module_eeprom = bnxt_get_module_eeprom,
4068 .timesync_enable = bnxt_timesync_enable,
4069 .timesync_disable = bnxt_timesync_disable,
4070 .timesync_read_time = bnxt_timesync_read_time,
4071 .timesync_write_time = bnxt_timesync_write_time,
4072 .timesync_adjust_time = bnxt_timesync_adjust_time,
4073 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4074 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4077 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4081 /* Only pre-map the reset GRC registers using window 3 */
4082 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4083 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4085 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4090 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4092 struct bnxt_error_recovery_info *info = bp->recovery_info;
4093 uint32_t reg_base = 0xffffffff;
4096 /* Only pre-map the monitoring GRC registers using window 2 */
4097 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4098 uint32_t reg = info->status_regs[i];
4100 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4103 if (reg_base == 0xffffffff)
4104 reg_base = reg & 0xfffff000;
4105 if ((reg & 0xfffff000) != reg_base)
4108 /* Use mask 0xffc as the Lower 2 bits indicates
4109 * address space location
4111 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4115 if (reg_base == 0xffffffff)
4118 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4119 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4124 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4126 struct bnxt_error_recovery_info *info = bp->recovery_info;
4127 uint32_t delay = info->delay_after_reset[index];
4128 uint32_t val = info->reset_reg_val[index];
4129 uint32_t reg = info->reset_reg[index];
4130 uint32_t type, offset;
4133 type = BNXT_FW_STATUS_REG_TYPE(reg);
4134 offset = BNXT_FW_STATUS_REG_OFF(reg);
4137 case BNXT_FW_STATUS_REG_TYPE_CFG:
4138 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4140 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4145 case BNXT_FW_STATUS_REG_TYPE_GRC:
4146 offset = bnxt_map_reset_regs(bp, offset);
4147 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4149 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4150 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4153 /* wait on a specific interval of time until core reset is complete */
4155 rte_delay_ms(delay);
4158 static void bnxt_dev_cleanup(struct bnxt *bp)
4160 bp->eth_dev->data->dev_link.link_status = 0;
4161 bp->link_info->link_up = 0;
4162 if (bp->eth_dev->data->dev_started)
4163 bnxt_dev_stop(bp->eth_dev);
4165 bnxt_uninit_resources(bp, true);
4169 bnxt_check_fw_reset_done(struct bnxt *bp)
4171 int timeout = bp->fw_reset_max_msecs;
4176 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4178 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4184 } while (timeout--);
4186 if (val == 0xffff) {
4187 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4194 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4196 struct rte_eth_dev *dev = bp->eth_dev;
4197 struct rte_vlan_filter_conf *vfc;
4201 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4202 vfc = &dev->data->vlan_filter_conf;
4203 vidx = vlan_id / 64;
4204 vbit = vlan_id % 64;
4206 /* Each bit corresponds to a VLAN id */
4207 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4208 rc = bnxt_add_vlan_filter(bp, vlan_id);
4217 static int bnxt_restore_mac_filters(struct bnxt *bp)
4219 struct rte_eth_dev *dev = bp->eth_dev;
4220 struct rte_eth_dev_info dev_info;
4221 struct rte_ether_addr *addr;
4227 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4230 rc = bnxt_dev_info_get_op(dev, &dev_info);
4234 /* replay MAC address configuration */
4235 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4236 addr = &dev->data->mac_addrs[i];
4238 /* skip zero address */
4239 if (rte_is_zero_ether_addr(addr))
4243 pool_mask = dev->data->mac_pool_sel[i];
4246 if (pool_mask & 1ULL) {
4247 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4253 } while (pool_mask);
4259 static int bnxt_restore_filters(struct bnxt *bp)
4261 struct rte_eth_dev *dev = bp->eth_dev;
4264 if (dev->data->all_multicast) {
4265 ret = bnxt_allmulticast_enable_op(dev);
4269 if (dev->data->promiscuous) {
4270 ret = bnxt_promiscuous_enable_op(dev);
4275 ret = bnxt_restore_mac_filters(bp);
4279 ret = bnxt_restore_vlan_filters(bp);
4280 /* TODO restore other filters as well */
4284 static int bnxt_check_fw_ready(struct bnxt *bp)
4286 int timeout = bp->fw_reset_max_msecs;
4290 rc = bnxt_hwrm_poll_ver_get(bp);
4293 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4294 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4295 } while (rc && timeout > 0);
4298 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4303 static void bnxt_dev_recover(void *arg)
4305 struct bnxt *bp = arg;
4308 pthread_mutex_lock(&bp->err_recovery_lock);
4310 if (!bp->fw_reset_min_msecs) {
4311 rc = bnxt_check_fw_reset_done(bp);
4316 /* Clear Error flag so that device re-init should happen */
4317 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4319 rc = bnxt_check_fw_ready(bp);
4323 rc = bnxt_init_resources(bp, true);
4326 "Failed to initialize resources after reset\n");
4329 /* clear reset flag as the device is initialized now */
4330 bp->flags &= ~BNXT_FLAG_FW_RESET;
4332 rc = bnxt_dev_start_op(bp->eth_dev);
4334 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4338 rc = bnxt_restore_filters(bp);
4342 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4343 pthread_mutex_unlock(&bp->err_recovery_lock);
4347 bnxt_dev_stop(bp->eth_dev);
4349 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4350 bnxt_uninit_resources(bp, false);
4351 if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4352 rte_eth_dev_callback_process(bp->eth_dev,
4353 RTE_ETH_EVENT_INTR_RMV,
4355 pthread_mutex_unlock(&bp->err_recovery_lock);
4356 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4359 void bnxt_dev_reset_and_resume(void *arg)
4361 struct bnxt *bp = arg;
4362 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4366 bnxt_dev_cleanup(bp);
4368 bnxt_wait_for_device_shutdown(bp);
4370 /* During some fatal firmware error conditions, the PCI config space
4371 * register 0x2e which normally contains the subsystem ID will become
4372 * 0xffff. This register will revert back to the normal value after
4373 * the chip has completed core reset. If we detect this condition,
4374 * we can poll this config register immediately for the value to revert.
4376 if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4377 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4379 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4382 if (val == 0xffff) {
4383 bp->fw_reset_min_msecs = 0;
4388 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4390 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4393 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4395 struct bnxt_error_recovery_info *info = bp->recovery_info;
4396 uint32_t reg = info->status_regs[index];
4397 uint32_t type, offset, val = 0;
4400 type = BNXT_FW_STATUS_REG_TYPE(reg);
4401 offset = BNXT_FW_STATUS_REG_OFF(reg);
4404 case BNXT_FW_STATUS_REG_TYPE_CFG:
4405 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4407 PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4410 case BNXT_FW_STATUS_REG_TYPE_GRC:
4411 offset = info->mapped_status_regs[index];
4413 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4414 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4422 static int bnxt_fw_reset_all(struct bnxt *bp)
4424 struct bnxt_error_recovery_info *info = bp->recovery_info;
4428 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4429 /* Reset through master function driver */
4430 for (i = 0; i < info->reg_array_cnt; i++)
4431 bnxt_write_fw_reset_reg(bp, i);
4432 /* Wait for time specified by FW after triggering reset */
4433 rte_delay_ms(info->master_func_wait_period_after_reset);
4434 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4435 /* Reset with the help of Kong processor */
4436 rc = bnxt_hwrm_fw_reset(bp);
4438 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4444 static void bnxt_fw_reset_cb(void *arg)
4446 struct bnxt *bp = arg;
4447 struct bnxt_error_recovery_info *info = bp->recovery_info;
4450 /* Only Master function can do FW reset */
4451 if (bnxt_is_master_func(bp) &&
4452 bnxt_is_recovery_enabled(bp)) {
4453 rc = bnxt_fw_reset_all(bp);
4455 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4460 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4461 * EXCEPTION_FATAL_ASYNC event to all the functions
4462 * (including MASTER FUNC). After receiving this Async, all the active
4463 * drivers should treat this case as FW initiated recovery
4465 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4466 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4467 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4469 /* To recover from error */
4470 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4475 /* Driver should poll FW heartbeat, reset_counter with the frequency
4476 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4477 * When the driver detects heartbeat stop or change in reset_counter,
4478 * it has to trigger a reset to recover from the error condition.
4479 * A “master PF” is the function who will have the privilege to
4480 * initiate the chimp reset. The master PF will be elected by the
4481 * firmware and will be notified through async message.
4483 static void bnxt_check_fw_health(void *arg)
4485 struct bnxt *bp = arg;
4486 struct bnxt_error_recovery_info *info = bp->recovery_info;
4487 uint32_t val = 0, wait_msec;
4489 if (!info || !bnxt_is_recovery_enabled(bp) ||
4490 is_bnxt_in_error(bp))
4493 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4494 if (val == info->last_heart_beat)
4497 info->last_heart_beat = val;
4499 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4500 if (val != info->last_reset_counter)
4503 info->last_reset_counter = val;
4505 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4506 bnxt_check_fw_health, (void *)bp);
4510 /* Stop DMA to/from device */
4511 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4512 bp->flags |= BNXT_FLAG_FW_RESET;
4516 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4518 if (bnxt_is_master_func(bp))
4519 wait_msec = info->master_func_wait_period;
4521 wait_msec = info->normal_func_wait_period;
4523 rte_eal_alarm_set(US_PER_MS * wait_msec,
4524 bnxt_fw_reset_cb, (void *)bp);
4527 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4529 uint32_t polling_freq;
4531 pthread_mutex_lock(&bp->health_check_lock);
4533 if (!bnxt_is_recovery_enabled(bp))
4536 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4539 polling_freq = bp->recovery_info->driver_polling_freq;
4541 rte_eal_alarm_set(US_PER_MS * polling_freq,
4542 bnxt_check_fw_health, (void *)bp);
4543 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4546 pthread_mutex_unlock(&bp->health_check_lock);
4549 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4551 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4552 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4555 static bool bnxt_vf_pciid(uint16_t device_id)
4557 switch (device_id) {
4558 case BROADCOM_DEV_ID_57304_VF:
4559 case BROADCOM_DEV_ID_57406_VF:
4560 case BROADCOM_DEV_ID_5731X_VF:
4561 case BROADCOM_DEV_ID_5741X_VF:
4562 case BROADCOM_DEV_ID_57414_VF:
4563 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4564 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4565 case BROADCOM_DEV_ID_58802_VF:
4566 case BROADCOM_DEV_ID_57500_VF1:
4567 case BROADCOM_DEV_ID_57500_VF2:
4568 case BROADCOM_DEV_ID_58818_VF:
4576 /* Phase 5 device */
4577 static bool bnxt_p5_device(uint16_t device_id)
4579 switch (device_id) {
4580 case BROADCOM_DEV_ID_57508:
4581 case BROADCOM_DEV_ID_57504:
4582 case BROADCOM_DEV_ID_57502:
4583 case BROADCOM_DEV_ID_57508_MF1:
4584 case BROADCOM_DEV_ID_57504_MF1:
4585 case BROADCOM_DEV_ID_57502_MF1:
4586 case BROADCOM_DEV_ID_57508_MF2:
4587 case BROADCOM_DEV_ID_57504_MF2:
4588 case BROADCOM_DEV_ID_57502_MF2:
4589 case BROADCOM_DEV_ID_57500_VF1:
4590 case BROADCOM_DEV_ID_57500_VF2:
4591 case BROADCOM_DEV_ID_58812:
4592 case BROADCOM_DEV_ID_58814:
4593 case BROADCOM_DEV_ID_58818:
4594 case BROADCOM_DEV_ID_58818_VF:
4602 bool bnxt_stratus_device(struct bnxt *bp)
4604 uint16_t device_id = bp->pdev->id.device_id;
4606 switch (device_id) {
4607 case BROADCOM_DEV_ID_STRATUS_NIC:
4608 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4609 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4617 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4619 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4620 struct bnxt *bp = eth_dev->data->dev_private;
4622 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4623 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4624 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4625 if (!bp->bar0 || !bp->doorbell_base) {
4626 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4630 bp->eth_dev = eth_dev;
4636 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4637 struct bnxt_ctx_pg_info *ctx_pg,
4642 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4643 const struct rte_memzone *mz = NULL;
4644 char mz_name[RTE_MEMZONE_NAMESIZE];
4645 rte_iova_t mz_phys_addr;
4646 uint64_t valid_bits = 0;
4653 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4655 rmem->page_size = BNXT_PAGE_SIZE;
4656 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4657 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4658 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4660 valid_bits = PTU_PTE_VALID;
4662 if (rmem->nr_pages > 1) {
4663 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4664 "bnxt_ctx_pg_tbl%s_%x_%d",
4665 suffix, idx, bp->eth_dev->data->port_id);
4666 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4667 mz = rte_memzone_lookup(mz_name);
4669 mz = rte_memzone_reserve_aligned(mz_name,
4671 bp->eth_dev->device->numa_node,
4673 RTE_MEMZONE_SIZE_HINT_ONLY |
4674 RTE_MEMZONE_IOVA_CONTIG,
4680 memset(mz->addr, 0, mz->len);
4681 mz_phys_addr = mz->iova;
4683 rmem->pg_tbl = mz->addr;
4684 rmem->pg_tbl_map = mz_phys_addr;
4685 rmem->pg_tbl_mz = mz;
4688 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4689 suffix, idx, bp->eth_dev->data->port_id);
4690 mz = rte_memzone_lookup(mz_name);
4692 mz = rte_memzone_reserve_aligned(mz_name,
4694 bp->eth_dev->device->numa_node,
4696 RTE_MEMZONE_SIZE_HINT_ONLY |
4697 RTE_MEMZONE_IOVA_CONTIG,
4703 memset(mz->addr, 0, mz->len);
4704 mz_phys_addr = mz->iova;
4706 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4707 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4708 rmem->dma_arr[i] = mz_phys_addr + sz;
4710 if (rmem->nr_pages > 1) {
4711 if (i == rmem->nr_pages - 2 &&
4712 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4713 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4714 else if (i == rmem->nr_pages - 1 &&
4715 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4716 valid_bits |= PTU_PTE_LAST;
4718 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4724 if (rmem->vmem_size)
4725 rmem->vmem = (void **)mz->addr;
4726 rmem->dma_arr[0] = mz_phys_addr;
4730 static void bnxt_free_ctx_mem(struct bnxt *bp)
4734 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4737 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4738 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4739 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4740 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4741 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4742 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4743 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4744 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4745 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4746 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4747 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4749 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4750 if (bp->ctx->tqm_mem[i])
4751 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4758 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4760 #define min_t(type, x, y) ({ \
4761 type __min1 = (x); \
4762 type __min2 = (y); \
4763 __min1 < __min2 ? __min1 : __min2; })
4765 #define max_t(type, x, y) ({ \
4766 type __max1 = (x); \
4767 type __max2 = (y); \
4768 __max1 > __max2 ? __max1 : __max2; })
4770 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4772 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4774 struct bnxt_ctx_pg_info *ctx_pg;
4775 struct bnxt_ctx_mem_info *ctx;
4776 uint32_t mem_size, ena, entries;
4777 uint32_t entries_sp, min;
4780 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4782 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4786 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4789 ctx_pg = &ctx->qp_mem;
4790 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4791 if (ctx->qp_entry_size) {
4792 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4793 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4798 ctx_pg = &ctx->srq_mem;
4799 ctx_pg->entries = ctx->srq_max_l2_entries;
4800 if (ctx->srq_entry_size) {
4801 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4802 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4807 ctx_pg = &ctx->cq_mem;
4808 ctx_pg->entries = ctx->cq_max_l2_entries;
4809 if (ctx->cq_entry_size) {
4810 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4811 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4816 ctx_pg = &ctx->vnic_mem;
4817 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4818 ctx->vnic_max_ring_table_entries;
4819 if (ctx->vnic_entry_size) {
4820 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4821 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4826 ctx_pg = &ctx->stat_mem;
4827 ctx_pg->entries = ctx->stat_max_entries;
4828 if (ctx->stat_entry_size) {
4829 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4830 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4835 min = ctx->tqm_min_entries_per_ring;
4837 entries_sp = ctx->qp_max_l2_entries +
4838 ctx->vnic_max_vnic_entries +
4839 2 * ctx->qp_min_qp1_entries + min;
4840 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4842 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4843 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4844 entries = clamp_t(uint32_t, entries, min,
4845 ctx->tqm_max_entries_per_ring);
4846 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4847 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4848 * i > 8 is other ext rings.
4850 ctx_pg = ctx->tqm_mem[i];
4851 ctx_pg->entries = i ? entries : entries_sp;
4852 if (ctx->tqm_entry_size) {
4853 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4854 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4859 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4860 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4862 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4865 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4866 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4869 "Failed to configure context mem: rc = %d\n", rc);
4871 ctx->flags |= BNXT_CTX_FLAG_INITED;
4876 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4878 struct rte_pci_device *pci_dev = bp->pdev;
4879 char mz_name[RTE_MEMZONE_NAMESIZE];
4880 const struct rte_memzone *mz = NULL;
4881 uint32_t total_alloc_len;
4882 rte_iova_t mz_phys_addr;
4884 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4887 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4888 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4889 pci_dev->addr.bus, pci_dev->addr.devid,
4890 pci_dev->addr.function, "rx_port_stats");
4891 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4892 mz = rte_memzone_lookup(mz_name);
4894 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4895 sizeof(struct rx_port_stats_ext) + 512);
4897 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4900 RTE_MEMZONE_SIZE_HINT_ONLY |
4901 RTE_MEMZONE_IOVA_CONTIG);
4905 memset(mz->addr, 0, mz->len);
4906 mz_phys_addr = mz->iova;
4908 bp->rx_mem_zone = (const void *)mz;
4909 bp->hw_rx_port_stats = mz->addr;
4910 bp->hw_rx_port_stats_map = mz_phys_addr;
4912 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4913 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4914 pci_dev->addr.bus, pci_dev->addr.devid,
4915 pci_dev->addr.function, "tx_port_stats");
4916 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4917 mz = rte_memzone_lookup(mz_name);
4919 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4920 sizeof(struct tx_port_stats_ext) + 512);
4922 mz = rte_memzone_reserve(mz_name,
4926 RTE_MEMZONE_SIZE_HINT_ONLY |
4927 RTE_MEMZONE_IOVA_CONTIG);
4931 memset(mz->addr, 0, mz->len);
4932 mz_phys_addr = mz->iova;
4934 bp->tx_mem_zone = (const void *)mz;
4935 bp->hw_tx_port_stats = mz->addr;
4936 bp->hw_tx_port_stats_map = mz_phys_addr;
4937 bp->flags |= BNXT_FLAG_PORT_STATS;
4939 /* Display extended statistics if FW supports it */
4940 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4941 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4942 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4945 bp->hw_rx_port_stats_ext = (void *)
4946 ((uint8_t *)bp->hw_rx_port_stats +
4947 sizeof(struct rx_port_stats));
4948 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4949 sizeof(struct rx_port_stats);
4950 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4952 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4953 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4954 bp->hw_tx_port_stats_ext = (void *)
4955 ((uint8_t *)bp->hw_tx_port_stats +
4956 sizeof(struct tx_port_stats));
4957 bp->hw_tx_port_stats_ext_map =
4958 bp->hw_tx_port_stats_map +
4959 sizeof(struct tx_port_stats);
4960 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4966 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4968 struct bnxt *bp = eth_dev->data->dev_private;
4971 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4972 RTE_ETHER_ADDR_LEN *
4975 if (eth_dev->data->mac_addrs == NULL) {
4976 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4980 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4984 /* Generate a random MAC address, if none was assigned by PF */
4985 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4986 bnxt_eth_hw_addr_random(bp->mac_addr);
4988 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4989 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4990 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4992 rc = bnxt_hwrm_set_mac(bp);
4997 /* Copy the permanent MAC from the FUNC_QCAPS response */
4998 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5003 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5007 /* MAC is already configured in FW */
5008 if (BNXT_HAS_DFLT_MAC_SET(bp))
5011 /* Restore the old MAC configured */
5012 rc = bnxt_hwrm_set_mac(bp);
5014 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5019 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5024 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5026 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5027 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5028 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5029 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5030 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5031 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5035 bnxt_get_bp(uint16_t port)
5038 struct rte_eth_dev *dev;
5040 if (!rte_eth_dev_is_valid_port(port)) {
5041 PMD_DRV_LOG(ERR, "Invalid port %d\n", port);
5045 dev = &rte_eth_devices[port];
5046 if (!is_bnxt_supported(dev)) {
5047 PMD_DRV_LOG(ERR, "Device %d not supported\n", port);
5051 bp = (struct bnxt *)dev->data->dev_private;
5052 if (!BNXT_TRUFLOW_EN(bp)) {
5053 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n");
5061 bnxt_get_svif(uint16_t port_id, bool func_svif,
5062 enum bnxt_ulp_intf_type type)
5064 struct rte_eth_dev *eth_dev;
5067 eth_dev = &rte_eth_devices[port_id];
5068 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5069 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5073 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5076 eth_dev = vfr->parent_dev;
5079 bp = eth_dev->data->dev_private;
5081 return func_svif ? bp->func_svif : bp->port_svif;
5085 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
5086 uint8_t *mac, uint8_t *parent_mac)
5088 struct rte_eth_dev *eth_dev;
5091 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF &&
5092 type != BNXT_ULP_INTF_TYPE_PF)
5095 eth_dev = &rte_eth_devices[port];
5096 bp = eth_dev->data->dev_private;
5097 memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5099 if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5100 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN);
5104 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5106 struct rte_eth_dev *eth_dev;
5109 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5112 eth_dev = &rte_eth_devices[port];
5113 bp = eth_dev->data->dev_private;
5115 return bp->parent->vnic;
5118 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5120 struct rte_eth_dev *eth_dev;
5121 struct bnxt_vnic_info *vnic;
5124 eth_dev = &rte_eth_devices[port];
5125 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5126 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5130 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5131 return vfr->dflt_vnic_id;
5133 eth_dev = vfr->parent_dev;
5136 bp = eth_dev->data->dev_private;
5138 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5140 return vnic->fw_vnic_id;
5144 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5146 struct rte_eth_dev *eth_dev;
5149 eth_dev = &rte_eth_devices[port];
5150 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5151 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5155 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5158 eth_dev = vfr->parent_dev;
5161 bp = eth_dev->data->dev_private;
5166 enum bnxt_ulp_intf_type
5167 bnxt_get_interface_type(uint16_t port)
5169 struct rte_eth_dev *eth_dev;
5172 eth_dev = &rte_eth_devices[port];
5173 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5174 return BNXT_ULP_INTF_TYPE_VF_REP;
5176 bp = eth_dev->data->dev_private;
5178 return BNXT_ULP_INTF_TYPE_PF;
5179 else if (BNXT_VF_IS_TRUSTED(bp))
5180 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5181 else if (BNXT_VF(bp))
5182 return BNXT_ULP_INTF_TYPE_VF;
5184 return BNXT_ULP_INTF_TYPE_INVALID;
5188 bnxt_get_phy_port_id(uint16_t port_id)
5190 struct bnxt_representor *vfr;
5191 struct rte_eth_dev *eth_dev;
5194 eth_dev = &rte_eth_devices[port_id];
5195 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5196 vfr = eth_dev->data->dev_private;
5200 eth_dev = vfr->parent_dev;
5203 bp = eth_dev->data->dev_private;
5205 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5209 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5211 struct rte_eth_dev *eth_dev;
5214 eth_dev = &rte_eth_devices[port_id];
5215 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5216 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5220 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5221 return vfr->fw_fid - 1;
5223 eth_dev = vfr->parent_dev;
5226 bp = eth_dev->data->dev_private;
5228 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5232 bnxt_get_vport(uint16_t port_id)
5234 return (1 << bnxt_get_phy_port_id(port_id));
5237 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5239 struct bnxt_error_recovery_info *info = bp->recovery_info;
5242 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5243 memset(info, 0, sizeof(*info));
5247 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5250 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5253 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5255 bp->recovery_info = info;
5258 static void bnxt_check_fw_status(struct bnxt *bp)
5262 if (!(bp->recovery_info &&
5263 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5266 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5267 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5268 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5272 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5274 struct bnxt_error_recovery_info *info = bp->recovery_info;
5275 uint32_t status_loc;
5278 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5279 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5280 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5281 BNXT_GRCP_WINDOW_2_BASE +
5282 offsetof(struct hcomm_status,
5284 /* If the signature is absent, then FW does not support this feature */
5285 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5286 HCOMM_STATUS_SIGNATURE_VAL)
5290 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5294 bp->recovery_info = info;
5296 memset(info, 0, sizeof(*info));
5299 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5300 BNXT_GRCP_WINDOW_2_BASE +
5301 offsetof(struct hcomm_status,
5304 /* Only pre-map the FW health status GRC register */
5305 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5308 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5309 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5310 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5312 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5313 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5315 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5320 /* This function gets the FW version along with the
5321 * capabilities(MAX and current) of the function, vnic,
5322 * error recovery, phy and other chip related info
5324 static int bnxt_get_config(struct bnxt *bp)
5331 rc = bnxt_map_hcomm_fw_status_reg(bp);
5335 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5337 bnxt_check_fw_status(bp);
5341 rc = bnxt_hwrm_func_reset(bp);
5345 rc = bnxt_hwrm_vnic_qcaps(bp);
5349 rc = bnxt_hwrm_queue_qportcfg(bp);
5353 /* Get the MAX capabilities for this function.
5354 * This function also allocates context memory for TQM rings and
5355 * informs the firmware about this allocated backing store memory.
5357 rc = bnxt_hwrm_func_qcaps(bp);
5361 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5365 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5369 bnxt_hwrm_port_mac_qcfg(bp);
5371 bnxt_hwrm_parent_pf_qcfg(bp);
5373 bnxt_hwrm_port_phy_qcaps(bp);
5375 bnxt_alloc_error_recovery_info(bp);
5376 /* Get the adapter error recovery support info */
5377 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5379 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5381 bnxt_hwrm_port_led_qcaps(bp);
5387 bnxt_init_locks(struct bnxt *bp)
5391 err = pthread_mutex_init(&bp->flow_lock, NULL);
5393 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5397 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5399 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5403 err = pthread_mutex_init(&bp->health_check_lock, NULL);
5405 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5409 err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5411 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5416 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5420 rc = bnxt_get_config(bp);
5424 if (!reconfig_dev) {
5425 rc = bnxt_setup_mac_addr(bp->eth_dev);
5429 rc = bnxt_restore_dflt_mac(bp);
5434 bnxt_config_vf_req_fwd(bp);
5436 rc = bnxt_hwrm_func_driver_register(bp);
5438 PMD_DRV_LOG(ERR, "Failed to register driver");
5443 if (bp->pdev->max_vfs) {
5444 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5446 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5450 rc = bnxt_hwrm_allocate_pf_only(bp);
5453 "Failed to allocate PF resources");
5459 rc = bnxt_alloc_mem(bp, reconfig_dev);
5463 rc = bnxt_setup_int(bp);
5467 rc = bnxt_request_int(bp);
5471 rc = bnxt_init_ctx_mem(bp);
5473 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5481 bnxt_parse_devarg_accum_stats(__rte_unused const char *key,
5482 const char *value, void *opaque_arg)
5484 struct bnxt *bp = opaque_arg;
5485 unsigned long accum_stats;
5488 if (!value || !opaque_arg) {
5490 "Invalid parameter passed to accum-stats devargs.\n");
5494 accum_stats = strtoul(value, &end, 10);
5495 if (end == NULL || *end != '\0' ||
5496 (accum_stats == ULONG_MAX && errno == ERANGE)) {
5498 "Invalid parameter passed to accum-stats devargs.\n");
5502 if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) {
5504 "Invalid value passed to accum-stats devargs.\n");
5509 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN;
5510 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n");
5512 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN;
5513 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n");
5520 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5521 const char *value, void *opaque_arg)
5523 struct bnxt *bp = opaque_arg;
5524 unsigned long flow_xstat;
5527 if (!value || !opaque_arg) {
5529 "Invalid parameter passed to flow_xstat devarg.\n");
5533 flow_xstat = strtoul(value, &end, 10);
5534 if (end == NULL || *end != '\0' ||
5535 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5537 "Invalid parameter passed to flow_xstat devarg.\n");
5541 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5543 "Invalid value passed to flow_xstat devarg.\n");
5547 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5548 if (BNXT_FLOW_XSTATS_EN(bp))
5549 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5555 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5556 const char *value, void *opaque_arg)
5558 struct bnxt *bp = opaque_arg;
5559 unsigned long max_num_kflows;
5562 if (!value || !opaque_arg) {
5564 "Invalid parameter passed to max_num_kflows devarg.\n");
5568 max_num_kflows = strtoul(value, &end, 10);
5569 if (end == NULL || *end != '\0' ||
5570 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5572 "Invalid parameter passed to max_num_kflows devarg.\n");
5576 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5578 "Invalid value passed to max_num_kflows devarg.\n");
5582 bp->max_num_kflows = max_num_kflows;
5583 if (bp->max_num_kflows)
5584 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5591 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5592 const char *value, void *opaque_arg)
5594 struct bnxt *bp = opaque_arg;
5595 unsigned long app_id;
5598 if (!value || !opaque_arg) {
5600 "Invalid parameter passed to app-id "
5605 app_id = strtoul(value, &end, 10);
5606 if (end == NULL || *end != '\0' ||
5607 (app_id == ULONG_MAX && errno == ERANGE)) {
5609 "Invalid parameter passed to app_id "
5614 if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5615 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5620 bp->app_id = app_id;
5621 PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5627 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5628 const char *value, void *opaque_arg)
5630 struct bnxt_representor *vfr_bp = opaque_arg;
5631 unsigned long rep_is_pf;
5634 if (!value || !opaque_arg) {
5636 "Invalid parameter passed to rep_is_pf devargs.\n");
5640 rep_is_pf = strtoul(value, &end, 10);
5641 if (end == NULL || *end != '\0' ||
5642 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5644 "Invalid parameter passed to rep_is_pf devargs.\n");
5648 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5650 "Invalid value passed to rep_is_pf devargs.\n");
5654 vfr_bp->flags |= rep_is_pf;
5655 if (BNXT_REP_PF(vfr_bp))
5656 PMD_DRV_LOG(INFO, "PF representor\n");
5658 PMD_DRV_LOG(INFO, "VF representor\n");
5664 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5665 const char *value, void *opaque_arg)
5667 struct bnxt_representor *vfr_bp = opaque_arg;
5668 unsigned long rep_based_pf;
5671 if (!value || !opaque_arg) {
5673 "Invalid parameter passed to rep_based_pf "
5678 rep_based_pf = strtoul(value, &end, 10);
5679 if (end == NULL || *end != '\0' ||
5680 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5682 "Invalid parameter passed to rep_based_pf "
5687 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5689 "Invalid value passed to rep_based_pf devargs.\n");
5693 vfr_bp->rep_based_pf = rep_based_pf;
5694 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5696 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5702 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5703 const char *value, void *opaque_arg)
5705 struct bnxt_representor *vfr_bp = opaque_arg;
5706 unsigned long rep_q_r2f;
5709 if (!value || !opaque_arg) {
5711 "Invalid parameter passed to rep_q_r2f "
5716 rep_q_r2f = strtoul(value, &end, 10);
5717 if (end == NULL || *end != '\0' ||
5718 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5720 "Invalid parameter passed to rep_q_r2f "
5725 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5727 "Invalid value passed to rep_q_r2f devargs.\n");
5731 vfr_bp->rep_q_r2f = rep_q_r2f;
5732 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5733 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5739 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5740 const char *value, void *opaque_arg)
5742 struct bnxt_representor *vfr_bp = opaque_arg;
5743 unsigned long rep_q_f2r;
5746 if (!value || !opaque_arg) {
5748 "Invalid parameter passed to rep_q_f2r "
5753 rep_q_f2r = strtoul(value, &end, 10);
5754 if (end == NULL || *end != '\0' ||
5755 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5757 "Invalid parameter passed to rep_q_f2r "
5762 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5764 "Invalid value passed to rep_q_f2r devargs.\n");
5768 vfr_bp->rep_q_f2r = rep_q_f2r;
5769 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5770 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5776 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5777 const char *value, void *opaque_arg)
5779 struct bnxt_representor *vfr_bp = opaque_arg;
5780 unsigned long rep_fc_r2f;
5783 if (!value || !opaque_arg) {
5785 "Invalid parameter passed to rep_fc_r2f "
5790 rep_fc_r2f = strtoul(value, &end, 10);
5791 if (end == NULL || *end != '\0' ||
5792 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5794 "Invalid parameter passed to rep_fc_r2f "
5799 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5801 "Invalid value passed to rep_fc_r2f devargs.\n");
5805 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5806 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5807 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5813 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5814 const char *value, void *opaque_arg)
5816 struct bnxt_representor *vfr_bp = opaque_arg;
5817 unsigned long rep_fc_f2r;
5820 if (!value || !opaque_arg) {
5822 "Invalid parameter passed to rep_fc_f2r "
5827 rep_fc_f2r = strtoul(value, &end, 10);
5828 if (end == NULL || *end != '\0' ||
5829 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5831 "Invalid parameter passed to rep_fc_f2r "
5836 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5838 "Invalid value passed to rep_fc_f2r devargs.\n");
5842 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5843 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5844 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5850 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5852 struct rte_kvargs *kvlist;
5855 if (devargs == NULL)
5858 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5863 * Handler for "flow_xstat" devarg.
5864 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5866 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5867 bnxt_parse_devarg_flow_xstat, bp);
5872 * Handler for "accum-stats" devarg.
5873 * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1"
5875 rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS,
5876 bnxt_parse_devarg_accum_stats, bp);
5878 * Handler for "max_num_kflows" devarg.
5879 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5881 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5882 bnxt_parse_devarg_max_num_kflows, bp);
5888 * Handler for "app-id" devarg.
5889 * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5891 rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5892 bnxt_parse_devarg_app_id, bp);
5894 rte_kvargs_free(kvlist);
5898 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5902 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5903 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5906 "Failed to alloc switch domain: %d\n", rc);
5909 "Switch domain allocated %d\n",
5910 bp->switch_domain_id);
5916 /* Allocate and initialize various fields in bnxt struct that
5917 * need to be allocated/destroyed only once in the lifetime of the driver
5919 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5921 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5922 struct bnxt *bp = eth_dev->data->dev_private;
5925 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5927 if (bnxt_vf_pciid(pci_dev->id.device_id))
5928 bp->flags |= BNXT_FLAG_VF;
5930 if (bnxt_p5_device(pci_dev->id.device_id))
5931 bp->flags |= BNXT_FLAG_CHIP_P5;
5933 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5934 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5935 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5936 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5937 bp->flags |= BNXT_FLAG_STINGRAY;
5939 if (BNXT_TRUFLOW_EN(bp)) {
5940 /* extra mbuf field is required to store CFA code from mark */
5941 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5942 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5943 .size = sizeof(bnxt_cfa_code_dynfield_t),
5944 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5946 bnxt_cfa_code_dynfield_offset =
5947 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5948 if (bnxt_cfa_code_dynfield_offset < 0) {
5950 "Failed to register mbuf field for TruFlow mark\n");
5955 rc = bnxt_map_pci_bars(eth_dev);
5958 "Failed to initialize board rc: %x\n", rc);
5962 rc = bnxt_alloc_pf_info(bp);
5966 rc = bnxt_alloc_link_info(bp);
5970 rc = bnxt_alloc_parent_info(bp);
5974 rc = bnxt_alloc_hwrm_resources(bp);
5977 "Failed to allocate response buffer rc: %x\n", rc);
5980 rc = bnxt_alloc_leds_info(bp);
5984 rc = bnxt_alloc_cos_queues(bp);
5988 rc = bnxt_init_locks(bp);
5992 rc = bnxt_alloc_switch_domain(bp);
6000 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
6002 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
6003 static int version_printed;
6007 if (version_printed++ == 0)
6008 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6010 eth_dev->dev_ops = &bnxt_dev_ops;
6011 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6012 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6013 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6014 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6015 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6018 * For secondary processes, we don't initialise any further
6019 * as primary has already done this work.
6021 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6024 rte_eth_copy_pci_info(eth_dev, pci_dev);
6025 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6027 bp = eth_dev->data->dev_private;
6029 /* Parse dev arguments passed on when starting the DPDK application. */
6030 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6034 rc = bnxt_drv_init(eth_dev);
6038 rc = bnxt_init_resources(bp, false);
6042 rc = bnxt_alloc_stats_mem(bp);
6047 "Found %s device at mem %" PRIX64 ", node addr %pM\n",
6049 pci_dev->mem_resource[0].phys_addr,
6050 pci_dev->mem_resource[0].addr);
6055 bnxt_dev_uninit(eth_dev);
6060 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6069 ctx->dma = RTE_BAD_IOVA;
6070 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6073 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6075 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6076 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6077 bp->flow_stat->rx_fc_out_tbl.ctx_id,
6078 bp->flow_stat->max_fc,
6081 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6082 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6083 bp->flow_stat->tx_fc_out_tbl.ctx_id,
6084 bp->flow_stat->max_fc,
6087 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6088 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6089 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6091 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6092 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6093 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6095 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6096 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6097 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6099 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6100 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6101 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6104 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6106 bnxt_unregister_fc_ctx_mem(bp);
6108 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6109 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6110 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6111 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6114 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6116 if (BNXT_FLOW_XSTATS_EN(bp))
6117 bnxt_uninit_fc_ctx_mem(bp);
6121 bnxt_free_error_recovery_info(struct bnxt *bp)
6123 rte_free(bp->recovery_info);
6124 bp->recovery_info = NULL;
6125 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6129 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6134 bnxt_free_mem(bp, reconfig_dev);
6136 bnxt_hwrm_func_buf_unrgtr(bp);
6137 if (bp->pf != NULL) {
6138 rte_free(bp->pf->vf_req_buf);
6139 bp->pf->vf_req_buf = NULL;
6142 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6143 bp->flags &= ~BNXT_FLAG_REGISTERED;
6144 bnxt_free_ctx_mem(bp);
6145 if (!reconfig_dev) {
6146 bnxt_free_hwrm_resources(bp);
6147 bnxt_free_error_recovery_info(bp);
6150 bnxt_uninit_ctx_mem(bp);
6152 bnxt_free_flow_stats_info(bp);
6153 if (bp->rep_info != NULL)
6154 bnxt_free_switch_domain(bp);
6155 bnxt_free_rep_info(bp);
6156 rte_free(bp->ptp_cfg);
6162 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6164 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6167 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6169 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6170 bnxt_dev_close_op(eth_dev);
6175 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6177 struct bnxt *bp = eth_dev->data->dev_private;
6178 struct rte_eth_dev *vf_rep_eth_dev;
6184 for (i = 0; i < bp->num_reps; i++) {
6185 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6186 if (!vf_rep_eth_dev)
6188 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6189 vf_rep_eth_dev->data->port_id);
6190 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6192 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6193 eth_dev->data->port_id);
6194 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6199 static void bnxt_free_rep_info(struct bnxt *bp)
6201 rte_free(bp->rep_info);
6202 bp->rep_info = NULL;
6203 rte_free(bp->cfa_code_map);
6204 bp->cfa_code_map = NULL;
6207 static int bnxt_init_rep_info(struct bnxt *bp)
6214 bp->rep_info = rte_zmalloc("bnxt_rep_info",
6215 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6217 if (!bp->rep_info) {
6218 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6221 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6222 sizeof(*bp->cfa_code_map) *
6223 BNXT_MAX_CFA_CODE, 0);
6224 if (!bp->cfa_code_map) {
6225 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6226 bnxt_free_rep_info(bp);
6230 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6231 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6233 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6235 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6236 bnxt_free_rep_info(bp);
6240 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6242 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6243 bnxt_free_rep_info(bp);
6250 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6251 struct rte_eth_devargs *eth_da,
6252 struct rte_eth_dev *backing_eth_dev,
6253 const char *dev_args)
6255 struct rte_eth_dev *vf_rep_eth_dev;
6256 char name[RTE_ETH_NAME_MAX_LEN];
6257 struct bnxt *backing_bp;
6260 struct rte_kvargs *kvlist = NULL;
6262 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6264 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6265 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6269 num_rep = eth_da->nb_representor_ports;
6270 if (num_rep > BNXT_MAX_VF_REPS) {
6271 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6272 num_rep, BNXT_MAX_VF_REPS);
6276 if (num_rep >= RTE_MAX_ETHPORTS) {
6278 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6279 num_rep, RTE_MAX_ETHPORTS);
6283 backing_bp = backing_eth_dev->data->dev_private;
6285 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6287 "Not a PF or trusted VF. No Representor support\n");
6288 /* Returning an error is not an option.
6289 * Applications are not handling this correctly
6294 if (bnxt_init_rep_info(backing_bp))
6297 for (i = 0; i < num_rep; i++) {
6298 struct bnxt_representor representor = {
6299 .vf_id = eth_da->representor_ports[i],
6300 .switch_domain_id = backing_bp->switch_domain_id,
6301 .parent_dev = backing_eth_dev
6304 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6305 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6306 representor.vf_id, BNXT_MAX_VF_REPS);
6310 /* representor port net_bdf_port */
6311 snprintf(name, sizeof(name), "net_%s_representor_%d",
6312 pci_dev->device.name, eth_da->representor_ports[i]);
6314 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6317 * Handler for "rep_is_pf" devarg.
6318 * Invoked as for ex: "-a 000:00:0d.0,
6319 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6321 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6322 bnxt_parse_devarg_rep_is_pf,
6323 (void *)&representor);
6329 * Handler for "rep_based_pf" devarg.
6330 * Invoked as for ex: "-a 000:00:0d.0,
6331 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6333 ret = rte_kvargs_process(kvlist,
6334 BNXT_DEVARG_REP_BASED_PF,
6335 bnxt_parse_devarg_rep_based_pf,
6336 (void *)&representor);
6342 * Handler for "rep_based_pf" devarg.
6343 * Invoked as for ex: "-a 000:00:0d.0,
6344 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6346 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6347 bnxt_parse_devarg_rep_q_r2f,
6348 (void *)&representor);
6354 * Handler for "rep_based_pf" devarg.
6355 * Invoked as for ex: "-a 000:00:0d.0,
6356 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6358 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6359 bnxt_parse_devarg_rep_q_f2r,
6360 (void *)&representor);
6366 * Handler for "rep_based_pf" devarg.
6367 * Invoked as for ex: "-a 000:00:0d.0,
6368 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6370 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6371 bnxt_parse_devarg_rep_fc_r2f,
6372 (void *)&representor);
6378 * Handler for "rep_based_pf" devarg.
6379 * Invoked as for ex: "-a 000:00:0d.0,
6380 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6382 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6383 bnxt_parse_devarg_rep_fc_f2r,
6384 (void *)&representor);
6391 ret = rte_eth_dev_create(&pci_dev->device, name,
6392 sizeof(struct bnxt_representor),
6394 bnxt_representor_init,
6397 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6398 "representor %s.", name);
6402 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6403 if (!vf_rep_eth_dev) {
6404 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6405 " for VF-Rep: %s.", name);
6410 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6411 backing_eth_dev->data->port_id);
6412 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6414 backing_bp->num_reps++;
6418 rte_kvargs_free(kvlist);
6422 /* If num_rep > 1, then rollback already created
6423 * ports, since we'll be failing the probe anyway
6426 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6428 rte_kvargs_free(kvlist);
6433 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6434 struct rte_pci_device *pci_dev)
6436 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6437 struct rte_eth_dev *backing_eth_dev;
6441 if (pci_dev->device.devargs) {
6442 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6448 num_rep = eth_da.nb_representor_ports;
6449 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6452 /* We could come here after first level of probe is already invoked
6453 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6454 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6456 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6457 if (backing_eth_dev == NULL) {
6458 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6459 sizeof(struct bnxt),
6460 eth_dev_pci_specific_init, pci_dev,
6461 bnxt_dev_init, NULL);
6463 if (ret || !num_rep)
6466 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6468 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6469 backing_eth_dev->data->port_id);
6474 /* probe representor ports now */
6475 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
6476 pci_dev->device.devargs->args);
6481 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6483 struct rte_eth_dev *eth_dev;
6485 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6487 return 0; /* Invoked typically only by OVS-DPDK, by the
6488 * time it comes here the eth_dev is already
6489 * deleted by rte_eth_dev_close(), so returning
6490 * +ve value will at least help in proper cleanup
6493 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6494 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6495 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6496 return rte_eth_dev_destroy(eth_dev,
6497 bnxt_representor_uninit);
6499 return rte_eth_dev_destroy(eth_dev,
6502 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6506 static struct rte_pci_driver bnxt_rte_pmd = {
6507 .id_table = bnxt_pci_id_map,
6508 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6509 RTE_PCI_DRV_INTR_RMV |
6510 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6513 .probe = bnxt_pci_probe,
6514 .remove = bnxt_pci_remove,
6518 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6520 if (strcmp(dev->device->driver->name, drv->driver.name))
6526 bool is_bnxt_supported(struct rte_eth_dev *dev)
6528 return is_device_supported(dev, &bnxt_rte_pmd);
6531 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6532 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6533 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6534 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");