drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_TRUFLOW,
 104         BNXT_DEVARG_FLOW_XSTAT,
 105         BNXT_DEVARG_MAX_NUM_KFLOWS,
 106         BNXT_DEVARG_REP_BASED_PF,
 107         BNXT_DEVARG_REP_IS_PF,
 108         BNXT_DEVARG_REP_Q_R2F,
 109         BNXT_DEVARG_REP_Q_F2R,
 110         BNXT_DEVARG_REP_FC_R2F,
 111         BNXT_DEVARG_REP_FC_F2R,
 112         NULL
 113 };
 114
 115 /*
 116  * truflow == false to disable the feature
 117  * truflow == true to enable the feature
 118  */
 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 120
 121 /*
 122  * flow_xstat == false to disable the feature
 123  * flow_xstat == true to enable the feature
 124  */
 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 126
 127 /*
 128  * rep_is_pf == false to indicate VF representor
 129  * rep_is_pf == true to indicate PF representor
 130  */
 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 132
 133 /*
 134  * rep_based_pf == Physical index of the PF
 135  */
 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 137 /*
 138  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 139  */
 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 141
 142 /*
 143  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 144  */
 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 146
 147 /*
 148  * rep_fc_r2f == Flow control for the representor to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 151
 152 /*
 153  * rep_fc_f2r == Flow control for the endpoint to representor direction
 154  */
 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 156
 157 int bnxt_cfa_code_dynfield_offset = -1;
 158
 159 /*
 160  * max_num_kflows must be >= 32
 161  * and must be a power-of-2 supported value
 162  * return: 1 -> invalid
 163  *         0 -> valid
 164  */
 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 166 {
 167         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 168                 return 1;
 169         return 0;
 170 }
 171
 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 178 static void bnxt_dev_recover(void *arg);
 179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 180 static void bnxt_free_rep_info(struct bnxt *bp);
 181
 182 int is_bnxt_in_error(struct bnxt *bp)
 183 {
 184         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 185                 return -EIO;
 186         if (bp->flags & BNXT_FLAG_FW_RESET)
 187                 return -EBUSY;
 188
 189         return 0;
 190 }
 191
 192 /***********************/
 193
 194 /*
 195  * High level utility functions
 196  */
 197
 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 199 {
 200         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 201                                              BNXT_RSS_TBL_SIZE_P5);
 202
 203         if (!BNXT_CHIP_P5(bp))
 204                 return 1;
 205
 206         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 208                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 212 {
 213         if (!BNXT_CHIP_P5(bp))
 214                 return HW_HASH_INDEX_SIZE;
 215
 216         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 217 }
 218
 219 static void bnxt_free_parent_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->parent);
 222 }
 223
 224 static void bnxt_free_pf_info(struct bnxt *bp)
 225 {
 226         rte_free(bp->pf);
 227 }
 228
 229 static void bnxt_free_link_info(struct bnxt *bp)
 230 {
 231         rte_free(bp->link_info);
 232 }
 233
 234 static void bnxt_free_leds_info(struct bnxt *bp)
 235 {
 236         if (BNXT_VF(bp))
 237                 return;
 238
 239         rte_free(bp->leds);
 240         bp->leds = NULL;
 241 }
 242
 243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 244 {
 245         rte_free(bp->flow_stat);
 246         bp->flow_stat = NULL;
 247 }
 248
 249 static void bnxt_free_cos_queues(struct bnxt *bp)
 250 {
 251         rte_free(bp->rx_cos_queue);
 252         rte_free(bp->tx_cos_queue);
 253 }
 254
 255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 256 {
 257         bnxt_free_filter_mem(bp);
 258         bnxt_free_vnic_attributes(bp);
 259         bnxt_free_vnic_mem(bp);
 260
 261         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 262          * If the number of rings change across fw update,
 263          * we don't have much choice except to warn the user.
 264          */
 265         if (!reconfig) {
 266                 bnxt_free_stats(bp);
 267                 bnxt_free_tx_rings(bp);
 268                 bnxt_free_rx_rings(bp);
 269         }
 270         bnxt_free_async_cp_ring(bp);
 271         bnxt_free_rxtx_nq_ring(bp);
 272
 273         rte_free(bp->grp_info);
 274         bp->grp_info = NULL;
 275 }
 276
 277 static int bnxt_alloc_parent_info(struct bnxt *bp)
 278 {
 279         bp->parent = rte_zmalloc("bnxt_parent_info",
 280                                  sizeof(struct bnxt_parent_info), 0);
 281         if (bp->parent == NULL)
 282                 return -ENOMEM;
 283
 284         return 0;
 285 }
 286
 287 static int bnxt_alloc_pf_info(struct bnxt *bp)
 288 {
 289         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 290         if (bp->pf == NULL)
 291                 return -ENOMEM;
 292
 293         return 0;
 294 }
 295
 296 static int bnxt_alloc_link_info(struct bnxt *bp)
 297 {
 298         bp->link_info =
 299                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 300         if (bp->link_info == NULL)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int bnxt_alloc_leds_info(struct bnxt *bp)
 307 {
 308         if (BNXT_VF(bp))
 309                 return 0;
 310
 311         bp->leds = rte_zmalloc("bnxt_leds",
 312                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 313                                0);
 314         if (bp->leds == NULL)
 315                 return -ENOMEM;
 316
 317         return 0;
 318 }
 319
 320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 321 {
 322         bp->rx_cos_queue =
 323                 rte_zmalloc("bnxt_rx_cosq",
 324                             BNXT_COS_QUEUE_COUNT *
 325                             sizeof(struct bnxt_cos_queue_info),
 326                             0);
 327         if (bp->rx_cos_queue == NULL)
 328                 return -ENOMEM;
 329
 330         bp->tx_cos_queue =
 331                 rte_zmalloc("bnxt_tx_cosq",
 332                             BNXT_COS_QUEUE_COUNT *
 333                             sizeof(struct bnxt_cos_queue_info),
 334                             0);
 335         if (bp->tx_cos_queue == NULL)
 336                 return -ENOMEM;
 337
 338         return 0;
 339 }
 340
 341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 342 {
 343         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 344                                     sizeof(struct bnxt_flow_stat_info), 0);
 345         if (bp->flow_stat == NULL)
 346                 return -ENOMEM;
 347
 348         return 0;
 349 }
 350
 351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 352 {
 353         int rc;
 354
 355         rc = bnxt_alloc_ring_grps(bp);
 356         if (rc)
 357                 goto alloc_mem_err;
 358
 359         rc = bnxt_alloc_async_ring_struct(bp);
 360         if (rc)
 361                 goto alloc_mem_err;
 362
 363         rc = bnxt_alloc_vnic_mem(bp);
 364         if (rc)
 365                 goto alloc_mem_err;
 366
 367         rc = bnxt_alloc_vnic_attributes(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_filter_mem(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_async_cp_ring(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_rxtx_nq_ring(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         if (BNXT_FLOW_XSTATS_EN(bp)) {
 384                 rc = bnxt_alloc_flow_stats_info(bp);
 385                 if (rc)
 386                         goto alloc_mem_err;
 387         }
 388
 389         return 0;
 390
 391 alloc_mem_err:
 392         bnxt_free_mem(bp, reconfig);
 393         return rc;
 394 }
 395
 396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 397 {
 398         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 399         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 400         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 401         struct bnxt_rx_queue *rxq;
 402         unsigned int j;
 403         int rc;
 404
 405         rc = bnxt_vnic_grp_alloc(bp, vnic);
 406         if (rc)
 407                 goto err_out;
 408
 409         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 410                     vnic_id, vnic, vnic->fw_grp_ids);
 411
 412         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 413         if (rc)
 414                 goto err_out;
 415
 416         /* Alloc RSS context only if RSS mode is enabled */
 417         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 418                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 419
 420                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 421                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 422                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 423                         PMD_DRV_LOG(ERR,
 424                                     "Only queues 0-%d will be in RSS table\n",
 425                                     BNXT_RSS_TBL_SIZE_P5 - 1);
 426                 }
 427
 428                 rc = 0;
 429                 for (j = 0; j < nr_ctxs; j++) {
 430                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 431                         if (rc)
 432                                 break;
 433                 }
 434                 if (rc) {
 435                         PMD_DRV_LOG(ERR,
 436                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 437                                     vnic_id, j, rc);
 438                         goto err_out;
 439                 }
 440                 vnic->num_lb_ctxts = nr_ctxs;
 441         }
 442
 443         /*
 444          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 445          * setting is not available at this time, it will not be
 446          * configured correctly in the CFA.
 447          */
 448         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 449                 vnic->vlan_strip = true;
 450         else
 451                 vnic->vlan_strip = false;
 452
 453         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 454         if (rc)
 455                 goto err_out;
 456
 457         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 458         if (rc)
 459                 goto err_out;
 460
 461         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 462                 rxq = bp->eth_dev->data->rx_queues[j];
 463
 464                 PMD_DRV_LOG(DEBUG,
 465                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 466                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 467
 468                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 469                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 470                 else
 471                         vnic->rx_queue_cnt++;
 472         }
 473
 474         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 475
 476         rc = bnxt_vnic_rss_configure(bp, vnic);
 477         if (rc)
 478                 goto err_out;
 479
 480         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 481
 482         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 483                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 484         else
 485                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 486
 487         return 0;
 488 err_out:
 489         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 490                     vnic_id, rc);
 491         return rc;
 492 }
 493
 494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 495 {
 496         int rc = 0;
 497
 498         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 499                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 500         if (rc)
 501                 return rc;
 502
 503         PMD_DRV_LOG(DEBUG,
 504                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 505                     " rx_fc_in_tbl.ctx_id = %d\n",
 506                     bp->flow_stat->rx_fc_in_tbl.va,
 507                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 508                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 509
 510         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 511                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 512         if (rc)
 513                 return rc;
 514
 515         PMD_DRV_LOG(DEBUG,
 516                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 517                     " rx_fc_out_tbl.ctx_id = %d\n",
 518                     bp->flow_stat->rx_fc_out_tbl.va,
 519                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 520                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 521
 522         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 523                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 524         if (rc)
 525                 return rc;
 526
 527         PMD_DRV_LOG(DEBUG,
 528                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 529                     " tx_fc_in_tbl.ctx_id = %d\n",
 530                     bp->flow_stat->tx_fc_in_tbl.va,
 531                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 532                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 533
 534         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 535                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 536         if (rc)
 537                 return rc;
 538
 539         PMD_DRV_LOG(DEBUG,
 540                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 541                     " tx_fc_out_tbl.ctx_id = %d\n",
 542                     bp->flow_stat->tx_fc_out_tbl.va,
 543                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 544                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 545
 546         memset(bp->flow_stat->rx_fc_out_tbl.va,
 547                0,
 548                bp->flow_stat->rx_fc_out_tbl.size);
 549         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 550                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 551                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 552                                        bp->flow_stat->max_fc,
 553                                        true);
 554         if (rc)
 555                 return rc;
 556
 557         memset(bp->flow_stat->tx_fc_out_tbl.va,
 558                0,
 559                bp->flow_stat->tx_fc_out_tbl.size);
 560         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 561                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 562                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 563                                        bp->flow_stat->max_fc,
 564                                        true);
 565
 566         return rc;
 567 }
 568
 569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 570                                   struct bnxt_ctx_mem_buf_info *ctx)
 571 {
 572         if (!ctx)
 573                 return -EINVAL;
 574
 575         ctx->va = rte_zmalloc(type, size, 0);
 576         if (ctx->va == NULL)
 577                 return -ENOMEM;
 578         rte_mem_lock_page(ctx->va);
 579         ctx->size = size;
 580         ctx->dma = rte_mem_virt2iova(ctx->va);
 581         if (ctx->dma == RTE_BAD_IOVA)
 582                 return -ENOMEM;
 583
 584         return 0;
 585 }
 586
 587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 588 {
 589         struct rte_pci_device *pdev = bp->pdev;
 590         char type[RTE_MEMZONE_NAMESIZE];
 591         uint16_t max_fc;
 592         int rc = 0;
 593
 594         max_fc = bp->flow_stat->max_fc;
 595
 596         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 597                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 598         /* 4 bytes for each counter-id */
 599         rc = bnxt_alloc_ctx_mem_buf(type,
 600                                     max_fc * 4,
 601                                     &bp->flow_stat->rx_fc_in_tbl);
 602         if (rc)
 603                 return rc;
 604
 605         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 606                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 607         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 608         rc = bnxt_alloc_ctx_mem_buf(type,
 609                                     max_fc * 16,
 610                                     &bp->flow_stat->rx_fc_out_tbl);
 611         if (rc)
 612                 return rc;
 613
 614         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 615                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 616         /* 4 bytes for each counter-id */
 617         rc = bnxt_alloc_ctx_mem_buf(type,
 618                                     max_fc * 4,
 619                                     &bp->flow_stat->tx_fc_in_tbl);
 620         if (rc)
 621                 return rc;
 622
 623         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 624                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 625         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 626         rc = bnxt_alloc_ctx_mem_buf(type,
 627                                     max_fc * 16,
 628                                     &bp->flow_stat->tx_fc_out_tbl);
 629         if (rc)
 630                 return rc;
 631
 632         rc = bnxt_register_fc_ctx_mem(bp);
 633
 634         return rc;
 635 }
 636
 637 static int bnxt_init_ctx_mem(struct bnxt *bp)
 638 {
 639         int rc = 0;
 640
 641         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 642             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 643             !BNXT_FLOW_XSTATS_EN(bp))
 644                 return 0;
 645
 646         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 647         if (rc)
 648                 return rc;
 649
 650         rc = bnxt_init_fc_ctx_mem(bp);
 651
 652         return rc;
 653 }
 654
 655 static int bnxt_update_phy_setting(struct bnxt *bp)
 656 {
 657         struct rte_eth_link new;
 658         int rc;
 659
 660         rc = bnxt_get_hwrm_link_config(bp, &new);
 661         if (rc) {
 662                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 663                 return rc;
 664         }
 665
 666         /*
 667          * On BCM957508-N2100 adapters, FW will not allow any user other
 668          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 669          * always returns link up. Force phy update always in that case.
 670          */
 671         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 672                 rc = bnxt_set_hwrm_link_config(bp, true);
 673                 if (rc) {
 674                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 675                         return rc;
 676                 }
 677         }
 678
 679         return rc;
 680 }
 681
 682 static int bnxt_init_chip(struct bnxt *bp)
 683 {
 684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 686         uint32_t intr_vector = 0;
 687         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 688         uint32_t vec = BNXT_MISC_VEC_ID;
 689         unsigned int i, j;
 690         int rc;
 691
 692         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 693                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 694                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 695                 bp->flags |= BNXT_FLAG_JUMBO;
 696         } else {
 697                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 698                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 699                 bp->flags &= ~BNXT_FLAG_JUMBO;
 700         }
 701
 702         /* THOR does not support ring groups.
 703          * But we will use the array to save RSS context IDs.
 704          */
 705         if (BNXT_CHIP_P5(bp))
 706                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 707
 708         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 709         if (rc) {
 710                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 711                 goto err_out;
 712         }
 713
 714         rc = bnxt_alloc_hwrm_rings(bp);
 715         if (rc) {
 716                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 717                 goto err_out;
 718         }
 719
 720         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 721         if (rc) {
 722                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 723                 goto err_out;
 724         }
 725
 726         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 727                 goto skip_cosq_cfg;
 728
 729         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 730                 if (bp->rx_cos_queue[i].id != 0xff) {
 731                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 732
 733                         if (!vnic) {
 734                                 PMD_DRV_LOG(ERR,
 735                                             "Num pools more than FW profile\n");
 736                                 rc = -EINVAL;
 737                                 goto err_out;
 738                         }
 739                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 740                         bp->rx_cosq_cnt++;
 741                 }
 742         }
 743
 744 skip_cosq_cfg:
 745         rc = bnxt_mq_rx_configure(bp);
 746         if (rc) {
 747                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 748                 goto err_out;
 749         }
 750
 751         /* default vnic 0 */
 752         rc = bnxt_setup_one_vnic(bp, 0);
 753         if (rc)
 754                 goto err_out;
 755         /* VNIC configuration */
 756         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 757                 for (i = 1; i < bp->nr_vnics; i++) {
 758                         rc = bnxt_setup_one_vnic(bp, i);
 759                         if (rc)
 760                                 goto err_out;
 761                 }
 762         }
 763
 764         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 765         if (rc) {
 766                 PMD_DRV_LOG(ERR,
 767                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 768                 goto err_out;
 769         }
 770
 771         /* check and configure queue intr-vector mapping */
 772         if ((rte_intr_cap_multiple(intr_handle) ||
 773              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 774             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 775                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 776                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 777                 if (intr_vector > bp->rx_cp_nr_rings) {
 778                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 779                                         bp->rx_cp_nr_rings);
 780                         return -ENOTSUP;
 781                 }
 782                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 783                 if (rc)
 784                         return rc;
 785         }
 786
 787         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 788                 intr_handle->intr_vec =
 789                         rte_zmalloc("intr_vec",
 790                                     bp->eth_dev->data->nb_rx_queues *
 791                                     sizeof(int), 0);
 792                 if (intr_handle->intr_vec == NULL) {
 793                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 794                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 795                         rc = -ENOMEM;
 796                         goto err_disable;
 797                 }
 798                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 799                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 800                          intr_handle->intr_vec, intr_handle->nb_efd,
 801                         intr_handle->max_intr);
 802                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 803                      queue_id++) {
 804                         intr_handle->intr_vec[queue_id] =
 805                                                         vec + BNXT_RX_VEC_START;
 806                         if (vec < base + intr_handle->nb_efd - 1)
 807                                 vec++;
 808                 }
 809         }
 810
 811         /* enable uio/vfio intr/eventfd mapping */
 812         rc = rte_intr_enable(intr_handle);
 813 #ifndef RTE_EXEC_ENV_FREEBSD
 814         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 815         if (rc)
 816                 goto err_free;
 817 #endif
 818
 819         rc = bnxt_update_phy_setting(bp);
 820         if (rc)
 821                 goto err_free;
 822
 823         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 824         if (!bp->mark_table)
 825                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 826
 827         return 0;
 828
 829 err_free:
 830         rte_free(intr_handle->intr_vec);
 831 err_disable:
 832         rte_intr_efd_disable(intr_handle);
 833 err_out:
 834         /* Some of the error status returned by FW may not be from errno.h */
 835         if (rc > 0)
 836                 rc = -EIO;
 837
 838         return rc;
 839 }
 840
 841 static int bnxt_shutdown_nic(struct bnxt *bp)
 842 {
 843         bnxt_free_all_hwrm_resources(bp);
 844         bnxt_free_all_filters(bp);
 845         bnxt_free_all_vnics(bp);
 846         return 0;
 847 }
 848
 849 /*
 850  * Device configuration and status function
 851  */
 852
 853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 854 {
 855         uint32_t link_speed = bp->link_info->support_speeds;
 856         uint32_t speed_capa = 0;
 857
 858         /* If PAM4 is configured, use PAM4 supported speed */
 859         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 860                 link_speed = bp->link_info->support_pam4_speeds;
 861
 862         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 863                 speed_capa |= ETH_LINK_SPEED_100M;
 864         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 865                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 866         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 867                 speed_capa |= ETH_LINK_SPEED_1G;
 868         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 869                 speed_capa |= ETH_LINK_SPEED_2_5G;
 870         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 871                 speed_capa |= ETH_LINK_SPEED_10G;
 872         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 873                 speed_capa |= ETH_LINK_SPEED_20G;
 874         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 875                 speed_capa |= ETH_LINK_SPEED_25G;
 876         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 877                 speed_capa |= ETH_LINK_SPEED_40G;
 878         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 879                 speed_capa |= ETH_LINK_SPEED_50G;
 880         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 881                 speed_capa |= ETH_LINK_SPEED_100G;
 882         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 883                 speed_capa |= ETH_LINK_SPEED_50G;
 884         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 885                 speed_capa |= ETH_LINK_SPEED_100G;
 886         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 887                 speed_capa |= ETH_LINK_SPEED_200G;
 888
 889         if (bp->link_info->auto_mode ==
 890             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 891                 speed_capa |= ETH_LINK_SPEED_FIXED;
 892         else
 893                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 894
 895         return speed_capa;
 896 }
 897
 898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 899                                 struct rte_eth_dev_info *dev_info)
 900 {
 901         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 902         struct bnxt *bp = eth_dev->data->dev_private;
 903         uint16_t max_vnics, i, j, vpool, vrxq;
 904         unsigned int max_rx_rings;
 905         int rc;
 906
 907         rc = is_bnxt_in_error(bp);
 908         if (rc)
 909                 return rc;
 910
 911         /* MAC Specifics */
 912         dev_info->max_mac_addrs = bp->max_l2_ctx;
 913         dev_info->max_hash_mac_addrs = 0;
 914
 915         /* PF/VF specifics */
 916         if (BNXT_PF(bp))
 917                 dev_info->max_vfs = pdev->max_vfs;
 918
 919         max_rx_rings = bnxt_max_rings(bp);
 920         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 921         dev_info->max_rx_queues = max_rx_rings;
 922         dev_info->max_tx_queues = max_rx_rings;
 923         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 924         dev_info->hash_key_size = 40;
 925         max_vnics = bp->max_vnics;
 926
 927         /* MTU specifics */
 928         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 929         dev_info->max_mtu = BNXT_MAX_MTU;
 930
 931         /* Fast path specifics */
 932         dev_info->min_rx_bufsize = 1;
 933         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 934
 935         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 936         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 937                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 938         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 939         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 940                                     dev_info->tx_queue_offload_capa;
 941         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 942
 943         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 944
 945         /* *INDENT-OFF* */
 946         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 947                 .rx_thresh = {
 948                         .pthresh = 8,
 949                         .hthresh = 8,
 950                         .wthresh = 0,
 951                 },
 952                 .rx_free_thresh = 32,
 953                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 954         };
 955
 956         dev_info->default_txconf = (struct rte_eth_txconf) {
 957                 .tx_thresh = {
 958                         .pthresh = 32,
 959                         .hthresh = 0,
 960                         .wthresh = 0,
 961                 },
 962                 .tx_free_thresh = 32,
 963                 .tx_rs_thresh = 32,
 964         };
 965         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 966
 967         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 968         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 969         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 970         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 971         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 972
 973         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 974                 dev_info->switch_info.name = eth_dev->device->name;
 975                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 976                 dev_info->switch_info.port_id =
 977                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 978                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 979         }
 980
 981         /* *INDENT-ON* */
 982
 983         /*
 984          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 985          *       need further investigation.
 986          */
 987
 988         /* VMDq resources */
 989         vpool = 64; /* ETH_64_POOLS */
 990         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 991         for (i = 0; i < 4; vpool >>= 1, i++) {
 992                 if (max_vnics > vpool) {
 993                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 994                                 if (dev_info->max_rx_queues > vrxq) {
 995                                         if (vpool > vrxq)
 996                                                 vpool = vrxq;
 997                                         goto found;
 998                                 }
 999                         }
1000                         /* Not enough resources to support VMDq */
1001                         break;
1002                 }
1003         }
1004         /* Not enough resources to support VMDq */
1005         vpool = 0;
1006         vrxq = 0;
1007 found:
1008         dev_info->max_vmdq_pools = vpool;
1009         dev_info->vmdq_queue_num = vrxq;
1010
1011         dev_info->vmdq_pool_base = 0;
1012         dev_info->vmdq_queue_base = 0;
1013
1014         return 0;
1015 }
1016
1017 /* Configure the device based on the configuration provided */
1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1019 {
1020         struct bnxt *bp = eth_dev->data->dev_private;
1021         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1022         int rc;
1023
1024         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1025         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1026         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1027         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1028
1029         rc = is_bnxt_in_error(bp);
1030         if (rc)
1031                 return rc;
1032
1033         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1034                 rc = bnxt_hwrm_check_vf_rings(bp);
1035                 if (rc) {
1036                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1037                         return -ENOSPC;
1038                 }
1039
1040                 /* If a resource has already been allocated - in this case
1041                  * it is the async completion ring, free it. Reallocate it after
1042                  * resource reservation. This will ensure the resource counts
1043                  * are calculated correctly.
1044                  */
1045
1046                 pthread_mutex_lock(&bp->def_cp_lock);
1047
1048                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1049                         bnxt_disable_int(bp);
1050                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1051                 }
1052
1053                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1054                 if (rc) {
1055                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1056                         pthread_mutex_unlock(&bp->def_cp_lock);
1057                         return -ENOSPC;
1058                 }
1059
1060                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1061                         rc = bnxt_alloc_async_cp_ring(bp);
1062                         if (rc) {
1063                                 pthread_mutex_unlock(&bp->def_cp_lock);
1064                                 return rc;
1065                         }
1066                         bnxt_enable_int(bp);
1067                 }
1068
1069                 pthread_mutex_unlock(&bp->def_cp_lock);
1070         }
1071
1072         /* Inherit new configurations */
1073         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1074             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1075             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1076                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1077             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1078             bp->max_stat_ctx)
1079                 goto resource_error;
1080
1081         if (BNXT_HAS_RING_GRPS(bp) &&
1082             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1083                 goto resource_error;
1084
1085         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1086             bp->max_vnics < eth_dev->data->nb_rx_queues)
1087                 goto resource_error;
1088
1089         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1090         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1091
1092         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1093                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1094         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1095
1096         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1097                 eth_dev->data->mtu =
1098                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1099                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1100                         BNXT_NUM_VLANS;
1101                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1102         }
1103         return 0;
1104
1105 resource_error:
1106         PMD_DRV_LOG(ERR,
1107                     "Insufficient resources to support requested config\n");
1108         PMD_DRV_LOG(ERR,
1109                     "Num Queues Requested: Tx %d, Rx %d\n",
1110                     eth_dev->data->nb_tx_queues,
1111                     eth_dev->data->nb_rx_queues);
1112         PMD_DRV_LOG(ERR,
1113                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1114                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1115                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1116         return -ENOSPC;
1117 }
1118
1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1120 {
1121         struct rte_eth_link *link = &eth_dev->data->dev_link;
1122
1123         if (link->link_status)
1124                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1125                         eth_dev->data->port_id,
1126                         (uint32_t)link->link_speed,
1127                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1128                         ("full-duplex") : ("half-duplex\n"));
1129         else
1130                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1131                         eth_dev->data->port_id);
1132 }
1133
1134 /*
1135  * Determine whether the current configuration requires support for scattered
1136  * receive; return 1 if scattered receive is required and 0 if not.
1137  */
1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1139 {
1140         uint16_t buf_size;
1141         int i;
1142
1143         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1144                 return 1;
1145
1146         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1147                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1148
1149                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1150                                       RTE_PKTMBUF_HEADROOM);
1151                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1152                         return 1;
1153         }
1154         return 0;
1155 }
1156
1157 static eth_rx_burst_t
1158 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1159 {
1160         struct bnxt *bp = eth_dev->data->dev_private;
1161
1162         /* Disable vector mode RX for Stingray2 for now */
1163         if (BNXT_CHIP_SR2(bp)) {
1164                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1165                 return bnxt_recv_pkts;
1166         }
1167
1168 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1169 #ifndef RTE_LIBRTE_IEEE1588
1170         /*
1171          * Vector mode receive can be enabled only if scatter rx is not
1172          * in use and rx offloads are limited to VLAN stripping and
1173          * CRC stripping.
1174          */
1175         if (!eth_dev->data->scattered_rx &&
1176             !(eth_dev->data->dev_conf.rxmode.offloads &
1177               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1178                 DEV_RX_OFFLOAD_KEEP_CRC |
1179                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1180                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1181                 DEV_RX_OFFLOAD_UDP_CKSUM |
1182                 DEV_RX_OFFLOAD_TCP_CKSUM |
1183                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1184                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1185                 DEV_RX_OFFLOAD_RSS_HASH |
1186                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1187             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1188             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1189                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1190                             eth_dev->data->port_id);
1191                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1192                 return bnxt_recv_pkts_vec;
1193         }
1194         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1195                     eth_dev->data->port_id);
1196         PMD_DRV_LOG(INFO,
1197                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1198                     eth_dev->data->port_id,
1199                     eth_dev->data->scattered_rx,
1200                     eth_dev->data->dev_conf.rxmode.offloads);
1201 #endif
1202 #endif
1203         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1204         return bnxt_recv_pkts;
1205 }
1206
1207 static eth_tx_burst_t
1208 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1209 {
1210         struct bnxt *bp = eth_dev->data->dev_private;
1211
1212         /* Disable vector mode TX for Stingray2 for now */
1213         if (BNXT_CHIP_SR2(bp))
1214                 return bnxt_xmit_pkts;
1215
1216 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1217 #ifndef RTE_LIBRTE_IEEE1588
1218         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1219
1220         /*
1221          * Vector mode transmit can be enabled only if not using scatter rx
1222          * or tx offloads.
1223          */
1224         if (!eth_dev->data->scattered_rx &&
1225             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1226             !BNXT_TRUFLOW_EN(bp) &&
1227             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1228                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1229                             eth_dev->data->port_id);
1230                 return bnxt_xmit_pkts_vec;
1231         }
1232         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1233                     eth_dev->data->port_id);
1234         PMD_DRV_LOG(INFO,
1235                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1236                     eth_dev->data->port_id,
1237                     eth_dev->data->scattered_rx,
1238                     offloads);
1239 #endif
1240 #endif
1241         return bnxt_xmit_pkts;
1242 }
1243
1244 static int bnxt_handle_if_change_status(struct bnxt *bp)
1245 {
1246         int rc;
1247
1248         /* Since fw has undergone a reset and lost all contexts,
1249          * set fatal flag to not issue hwrm during cleanup
1250          */
1251         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1252         bnxt_uninit_resources(bp, true);
1253
1254         /* clear fatal flag so that re-init happens */
1255         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1256         rc = bnxt_init_resources(bp, true);
1257
1258         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1259
1260         return rc;
1261 }
1262
1263 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1264 {
1265         struct bnxt *bp = eth_dev->data->dev_private;
1266         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1267         int vlan_mask = 0;
1268         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1269
1270         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1271                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1272                 return -EINVAL;
1273         }
1274
1275         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1276                 PMD_DRV_LOG(ERR,
1277                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1278                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1279
1280         do {
1281                 rc = bnxt_hwrm_if_change(bp, true);
1282                 if (rc == 0 || rc != -EAGAIN)
1283                         break;
1284
1285                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1286         } while (retry_cnt--);
1287
1288         if (rc)
1289                 return rc;
1290
1291         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1292                 rc = bnxt_handle_if_change_status(bp);
1293                 if (rc)
1294                         return rc;
1295         }
1296
1297         bnxt_enable_int(bp);
1298
1299         rc = bnxt_init_chip(bp);
1300         if (rc)
1301                 goto error;
1302
1303         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1304         eth_dev->data->dev_started = 1;
1305
1306         bnxt_link_update_op(eth_dev, 1);
1307
1308         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1309                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1310         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1311                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1312         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1313         if (rc)
1314                 goto error;
1315
1316         /* Initialize bnxt ULP port details */
1317         rc = bnxt_ulp_port_init(bp);
1318         if (rc)
1319                 goto error;
1320
1321         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1322         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1323
1324         bnxt_schedule_fw_health_check(bp);
1325
1326         return 0;
1327
1328 error:
1329         bnxt_shutdown_nic(bp);
1330         bnxt_free_tx_mbufs(bp);
1331         bnxt_free_rx_mbufs(bp);
1332         bnxt_hwrm_if_change(bp, false);
1333         eth_dev->data->dev_started = 0;
1334         return rc;
1335 }
1336
1337 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1338 {
1339         struct bnxt *bp = eth_dev->data->dev_private;
1340         int rc = 0;
1341
1342         if (!bp->link_info->link_up)
1343                 rc = bnxt_set_hwrm_link_config(bp, true);
1344         if (!rc)
1345                 eth_dev->data->dev_link.link_status = 1;
1346
1347         bnxt_print_link_info(eth_dev);
1348         return rc;
1349 }
1350
1351 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1352 {
1353         struct bnxt *bp = eth_dev->data->dev_private;
1354
1355         eth_dev->data->dev_link.link_status = 0;
1356         bnxt_set_hwrm_link_config(bp, false);
1357         bp->link_info->link_up = 0;
1358
1359         return 0;
1360 }
1361
1362 static void bnxt_free_switch_domain(struct bnxt *bp)
1363 {
1364         int rc = 0;
1365
1366         if (bp->switch_domain_id) {
1367                 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1368                 if (rc)
1369                         PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1370                                     bp->switch_domain_id, rc);
1371         }
1372 }
1373
1374 /* Unload the driver, release resources */
1375 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1376 {
1377         struct bnxt *bp = eth_dev->data->dev_private;
1378         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1379         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1380         struct rte_eth_link link;
1381         int ret;
1382
1383         eth_dev->data->dev_started = 0;
1384         eth_dev->data->scattered_rx = 0;
1385
1386         /* Prevent crashes when queues are still in use */
1387         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1388         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1389
1390         bnxt_disable_int(bp);
1391
1392         /* disable uio/vfio intr/eventfd mapping */
1393         rte_intr_disable(intr_handle);
1394
1395         /* Stop the child representors for this device */
1396         ret = bnxt_rep_stop_all(bp);
1397         if (ret != 0)
1398                 return ret;
1399
1400         /* delete the bnxt ULP port details */
1401         bnxt_ulp_port_deinit(bp);
1402
1403         bnxt_cancel_fw_health_check(bp);
1404
1405         /* Do not bring link down during reset recovery */
1406         if (!is_bnxt_in_error(bp)) {
1407                 bnxt_dev_set_link_down_op(eth_dev);
1408                 /* Wait for link to be reset */
1409                 if (BNXT_SINGLE_PF(bp))
1410                         rte_delay_ms(500);
1411                 /* clear the recorded link status */
1412                 memset(&link, 0, sizeof(link));
1413                 rte_eth_linkstatus_set(eth_dev, &link);
1414         }
1415
1416         /* Clean queue intr-vector mapping */
1417         rte_intr_efd_disable(intr_handle);
1418         if (intr_handle->intr_vec != NULL) {
1419                 rte_free(intr_handle->intr_vec);
1420                 intr_handle->intr_vec = NULL;
1421         }
1422
1423         bnxt_hwrm_port_clr_stats(bp);
1424         bnxt_free_tx_mbufs(bp);
1425         bnxt_free_rx_mbufs(bp);
1426         /* Process any remaining notifications in default completion queue */
1427         bnxt_int_handler(eth_dev);
1428         bnxt_shutdown_nic(bp);
1429         bnxt_hwrm_if_change(bp, false);
1430
1431         rte_free(bp->mark_table);
1432         bp->mark_table = NULL;
1433
1434         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1435         bp->rx_cosq_cnt = 0;
1436         /* All filters are deleted on a port stop. */
1437         if (BNXT_FLOW_XSTATS_EN(bp))
1438                 bp->flow_stat->flow_count = 0;
1439
1440         return 0;
1441 }
1442
1443 static void
1444 bnxt_uninit_locks(struct bnxt *bp)
1445 {
1446         pthread_mutex_destroy(&bp->flow_lock);
1447         pthread_mutex_destroy(&bp->def_cp_lock);
1448         pthread_mutex_destroy(&bp->health_check_lock);
1449         if (bp->rep_info) {
1450                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1451                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1452         }
1453 }
1454
1455 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1456 {
1457         struct bnxt *bp = eth_dev->data->dev_private;
1458         int ret = 0;
1459
1460         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1461                 return 0;
1462
1463         /* cancel the recovery handler before remove dev */
1464         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1465         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1466         bnxt_cancel_fc_thread(bp);
1467
1468         if (eth_dev->data->dev_started)
1469                 ret = bnxt_dev_stop_op(eth_dev);
1470
1471         bnxt_free_switch_domain(bp);
1472
1473         bnxt_uninit_resources(bp, false);
1474
1475         bnxt_free_leds_info(bp);
1476         bnxt_free_cos_queues(bp);
1477         bnxt_free_link_info(bp);
1478         bnxt_free_pf_info(bp);
1479         bnxt_free_parent_info(bp);
1480         bnxt_uninit_locks(bp);
1481
1482         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1483         bp->tx_mem_zone = NULL;
1484         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1485         bp->rx_mem_zone = NULL;
1486
1487         bnxt_hwrm_free_vf_info(bp);
1488
1489         rte_free(bp->grp_info);
1490         bp->grp_info = NULL;
1491
1492         return ret;
1493 }
1494
1495 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1496                                     uint32_t index)
1497 {
1498         struct bnxt *bp = eth_dev->data->dev_private;
1499         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1500         struct bnxt_vnic_info *vnic;
1501         struct bnxt_filter_info *filter, *temp_filter;
1502         uint32_t i;
1503
1504         if (is_bnxt_in_error(bp))
1505                 return;
1506
1507         /*
1508          * Loop through all VNICs from the specified filter flow pools to
1509          * remove the corresponding MAC addr filter
1510          */
1511         for (i = 0; i < bp->nr_vnics; i++) {
1512                 if (!(pool_mask & (1ULL << i)))
1513                         continue;
1514
1515                 vnic = &bp->vnic_info[i];
1516                 filter = STAILQ_FIRST(&vnic->filter);
1517                 while (filter) {
1518                         temp_filter = STAILQ_NEXT(filter, next);
1519                         if (filter->mac_index == index) {
1520                                 STAILQ_REMOVE(&vnic->filter, filter,
1521                                                 bnxt_filter_info, next);
1522                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1523                                 bnxt_free_filter(bp, filter);
1524                         }
1525                         filter = temp_filter;
1526                 }
1527         }
1528 }
1529
1530 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1531                                struct rte_ether_addr *mac_addr, uint32_t index,
1532                                uint32_t pool)
1533 {
1534         struct bnxt_filter_info *filter;
1535         int rc = 0;
1536
1537         /* Attach requested MAC address to the new l2_filter */
1538         STAILQ_FOREACH(filter, &vnic->filter, next) {
1539                 if (filter->mac_index == index) {
1540                         PMD_DRV_LOG(DEBUG,
1541                                     "MAC addr already existed for pool %d\n",
1542                                     pool);
1543                         return 0;
1544                 }
1545         }
1546
1547         filter = bnxt_alloc_filter(bp);
1548         if (!filter) {
1549                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1550                 return -ENODEV;
1551         }
1552
1553         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1554          * if the MAC that's been programmed now is a different one, then,
1555          * copy that addr to filter->l2_addr
1556          */
1557         if (mac_addr)
1558                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1559         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1560
1561         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1562         if (!rc) {
1563                 filter->mac_index = index;
1564                 if (filter->mac_index == 0)
1565                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1566                 else
1567                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1568         } else {
1569                 bnxt_free_filter(bp, filter);
1570         }
1571
1572         return rc;
1573 }
1574
1575 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1576                                 struct rte_ether_addr *mac_addr,
1577                                 uint32_t index, uint32_t pool)
1578 {
1579         struct bnxt *bp = eth_dev->data->dev_private;
1580         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1581         int rc = 0;
1582
1583         rc = is_bnxt_in_error(bp);
1584         if (rc)
1585                 return rc;
1586
1587         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1588                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1589                 return -ENOTSUP;
1590         }
1591
1592         if (!vnic) {
1593                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1594                 return -EINVAL;
1595         }
1596
1597         /* Filter settings will get applied when port is started */
1598         if (!eth_dev->data->dev_started)
1599                 return 0;
1600
1601         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1602
1603         return rc;
1604 }
1605
1606 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1607 {
1608         int rc = 0;
1609         struct bnxt *bp = eth_dev->data->dev_private;
1610         struct rte_eth_link new;
1611         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1612                         BNXT_MIN_LINK_WAIT_CNT;
1613
1614         rc = is_bnxt_in_error(bp);
1615         if (rc)
1616                 return rc;
1617
1618         memset(&new, 0, sizeof(new));
1619         do {
1620                 /* Retrieve link info from hardware */
1621                 rc = bnxt_get_hwrm_link_config(bp, &new);
1622                 if (rc) {
1623                         new.link_speed = ETH_LINK_SPEED_100M;
1624                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1625                         PMD_DRV_LOG(ERR,
1626                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1627                         goto out;
1628                 }
1629
1630                 if (!wait_to_complete || new.link_status)
1631                         break;
1632
1633                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1634         } while (cnt--);
1635
1636         /* Only single function PF can bring phy down.
1637          * When port is stopped, report link down for VF/MH/NPAR functions.
1638          */
1639         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1640                 memset(&new, 0, sizeof(new));
1641
1642 out:
1643         /* Timed out or success */
1644         if (new.link_status != eth_dev->data->dev_link.link_status ||
1645             new.link_speed != eth_dev->data->dev_link.link_speed) {
1646                 rte_eth_linkstatus_set(eth_dev, &new);
1647
1648                 rte_eth_dev_callback_process(eth_dev,
1649                                              RTE_ETH_EVENT_INTR_LSC,
1650                                              NULL);
1651
1652                 bnxt_print_link_info(eth_dev);
1653         }
1654
1655         return rc;
1656 }
1657
1658 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1659 {
1660         struct bnxt *bp = eth_dev->data->dev_private;
1661         struct bnxt_vnic_info *vnic;
1662         uint32_t old_flags;
1663         int rc;
1664
1665         rc = is_bnxt_in_error(bp);
1666         if (rc)
1667                 return rc;
1668
1669         /* Filter settings will get applied when port is started */
1670         if (!eth_dev->data->dev_started)
1671                 return 0;
1672
1673         if (bp->vnic_info == NULL)
1674                 return 0;
1675
1676         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1677
1678         old_flags = vnic->flags;
1679         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1680         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1681         if (rc != 0)
1682                 vnic->flags = old_flags;
1683
1684         return rc;
1685 }
1686
1687 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1688 {
1689         struct bnxt *bp = eth_dev->data->dev_private;
1690         struct bnxt_vnic_info *vnic;
1691         uint32_t old_flags;
1692         int rc;
1693
1694         rc = is_bnxt_in_error(bp);
1695         if (rc)
1696                 return rc;
1697
1698         /* Filter settings will get applied when port is started */
1699         if (!eth_dev->data->dev_started)
1700                 return 0;
1701
1702         if (bp->vnic_info == NULL)
1703                 return 0;
1704
1705         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1706
1707         old_flags = vnic->flags;
1708         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1709         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1710         if (rc != 0)
1711                 vnic->flags = old_flags;
1712
1713         return rc;
1714 }
1715
1716 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1717 {
1718         struct bnxt *bp = eth_dev->data->dev_private;
1719         struct bnxt_vnic_info *vnic;
1720         uint32_t old_flags;
1721         int rc;
1722
1723         rc = is_bnxt_in_error(bp);
1724         if (rc)
1725                 return rc;
1726
1727         /* Filter settings will get applied when port is started */
1728         if (!eth_dev->data->dev_started)
1729                 return 0;
1730
1731         if (bp->vnic_info == NULL)
1732                 return 0;
1733
1734         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1735
1736         old_flags = vnic->flags;
1737         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1738         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1739         if (rc != 0)
1740                 vnic->flags = old_flags;
1741
1742         return rc;
1743 }
1744
1745 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1746 {
1747         struct bnxt *bp = eth_dev->data->dev_private;
1748         struct bnxt_vnic_info *vnic;
1749         uint32_t old_flags;
1750         int rc;
1751
1752         rc = is_bnxt_in_error(bp);
1753         if (rc)
1754                 return rc;
1755
1756         /* Filter settings will get applied when port is started */
1757         if (!eth_dev->data->dev_started)
1758                 return 0;
1759
1760         if (bp->vnic_info == NULL)
1761                 return 0;
1762
1763         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1764
1765         old_flags = vnic->flags;
1766         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1767         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1768         if (rc != 0)
1769                 vnic->flags = old_flags;
1770
1771         return rc;
1772 }
1773
1774 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1775 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1776 {
1777         if (qid >= bp->rx_nr_rings)
1778                 return NULL;
1779
1780         return bp->eth_dev->data->rx_queues[qid];
1781 }
1782
1783 /* Return rxq corresponding to a given rss table ring/group ID. */
1784 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1785 {
1786         struct bnxt_rx_queue *rxq;
1787         unsigned int i;
1788
1789         if (!BNXT_HAS_RING_GRPS(bp)) {
1790                 for (i = 0; i < bp->rx_nr_rings; i++) {
1791                         rxq = bp->eth_dev->data->rx_queues[i];
1792                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1793                                 return rxq->index;
1794                 }
1795         } else {
1796                 for (i = 0; i < bp->rx_nr_rings; i++) {
1797                         if (bp->grp_info[i].fw_grp_id == fwr)
1798                                 return i;
1799                 }
1800         }
1801
1802         return INVALID_HW_RING_ID;
1803 }
1804
1805 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1806                             struct rte_eth_rss_reta_entry64 *reta_conf,
1807                             uint16_t reta_size)
1808 {
1809         struct bnxt *bp = eth_dev->data->dev_private;
1810         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1811         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1812         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1813         uint16_t idx, sft;
1814         int i, rc;
1815
1816         rc = is_bnxt_in_error(bp);
1817         if (rc)
1818                 return rc;
1819
1820         if (!vnic->rss_table)
1821                 return -EINVAL;
1822
1823         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1824                 return -EINVAL;
1825
1826         if (reta_size != tbl_size) {
1827                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1828                         "(%d) must equal the size supported by the hardware "
1829                         "(%d)\n", reta_size, tbl_size);
1830                 return -EINVAL;
1831         }
1832
1833         for (i = 0; i < reta_size; i++) {
1834                 struct bnxt_rx_queue *rxq;
1835
1836                 idx = i / RTE_RETA_GROUP_SIZE;
1837                 sft = i % RTE_RETA_GROUP_SIZE;
1838
1839                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1840                         continue;
1841
1842                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1843                 if (!rxq) {
1844                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1845                         return -EINVAL;
1846                 }
1847
1848                 if (BNXT_CHIP_P5(bp)) {
1849                         vnic->rss_table[i * 2] =
1850                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1851                         vnic->rss_table[i * 2 + 1] =
1852                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1853                 } else {
1854                         vnic->rss_table[i] =
1855                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1856                 }
1857         }
1858
1859         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1860         return rc;
1861 }
1862
1863 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1864                               struct rte_eth_rss_reta_entry64 *reta_conf,
1865                               uint16_t reta_size)
1866 {
1867         struct bnxt *bp = eth_dev->data->dev_private;
1868         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1869         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1870         uint16_t idx, sft, i;
1871         int rc;
1872
1873         rc = is_bnxt_in_error(bp);
1874         if (rc)
1875                 return rc;
1876
1877         /* Retrieve from the default VNIC */
1878         if (!vnic)
1879                 return -EINVAL;
1880         if (!vnic->rss_table)
1881                 return -EINVAL;
1882
1883         if (reta_size != tbl_size) {
1884                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1885                         "(%d) must equal the size supported by the hardware "
1886                         "(%d)\n", reta_size, tbl_size);
1887                 return -EINVAL;
1888         }
1889
1890         for (idx = 0, i = 0; i < reta_size; i++) {
1891                 idx = i / RTE_RETA_GROUP_SIZE;
1892                 sft = i % RTE_RETA_GROUP_SIZE;
1893
1894                 if (reta_conf[idx].mask & (1ULL << sft)) {
1895                         uint16_t qid;
1896
1897                         if (BNXT_CHIP_P5(bp))
1898                                 qid = bnxt_rss_to_qid(bp,
1899                                                       vnic->rss_table[i * 2]);
1900                         else
1901                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1902
1903                         if (qid == INVALID_HW_RING_ID) {
1904                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1905                                 return -EINVAL;
1906                         }
1907                         reta_conf[idx].reta[sft] = qid;
1908                 }
1909         }
1910
1911         return 0;
1912 }
1913
1914 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1915                                    struct rte_eth_rss_conf *rss_conf)
1916 {
1917         struct bnxt *bp = eth_dev->data->dev_private;
1918         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1919         struct bnxt_vnic_info *vnic;
1920         int rc;
1921
1922         rc = is_bnxt_in_error(bp);
1923         if (rc)
1924                 return rc;
1925
1926         /*
1927          * If RSS enablement were different than dev_configure,
1928          * then return -EINVAL
1929          */
1930         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1931                 if (!rss_conf->rss_hf)
1932                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1933         } else {
1934                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1935                         return -EINVAL;
1936         }
1937
1938         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1939         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1940                rss_conf,
1941                sizeof(*rss_conf));
1942
1943         /* Update the default RSS VNIC(s) */
1944         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1945         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1946         vnic->hash_mode =
1947                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1948                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1949
1950         /*
1951          * If hashkey is not specified, use the previously configured
1952          * hashkey
1953          */
1954         if (!rss_conf->rss_key)
1955                 goto rss_config;
1956
1957         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1958                 PMD_DRV_LOG(ERR,
1959                             "Invalid hashkey length, should be 16 bytes\n");
1960                 return -EINVAL;
1961         }
1962         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1963
1964 rss_config:
1965         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1966         return rc;
1967 }
1968
1969 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1970                                      struct rte_eth_rss_conf *rss_conf)
1971 {
1972         struct bnxt *bp = eth_dev->data->dev_private;
1973         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1974         int len, rc;
1975         uint32_t hash_types;
1976
1977         rc = is_bnxt_in_error(bp);
1978         if (rc)
1979                 return rc;
1980
1981         /* RSS configuration is the same for all VNICs */
1982         if (vnic && vnic->rss_hash_key) {
1983                 if (rss_conf->rss_key) {
1984                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1985                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1986                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1987                 }
1988
1989                 hash_types = vnic->hash_type;
1990                 rss_conf->rss_hf = 0;
1991                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1992                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1993                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1994                 }
1995                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1996                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1997                         hash_types &=
1998                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1999                 }
2000                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2001                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2002                         hash_types &=
2003                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2004                 }
2005                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2006                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2007                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2008                 }
2009                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2010                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2011                         hash_types &=
2012                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2013                 }
2014                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2015                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2016                         hash_types &=
2017                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2018                 }
2019
2020                 rss_conf->rss_hf |=
2021                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2022
2023                 if (hash_types) {
2024                         PMD_DRV_LOG(ERR,
2025                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2026                                 vnic->hash_type);
2027                         return -ENOTSUP;
2028                 }
2029         } else {
2030                 rss_conf->rss_hf = 0;
2031         }
2032         return 0;
2033 }
2034
2035 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2036                                struct rte_eth_fc_conf *fc_conf)
2037 {
2038         struct bnxt *bp = dev->data->dev_private;
2039         struct rte_eth_link link_info;
2040         int rc;
2041
2042         rc = is_bnxt_in_error(bp);
2043         if (rc)
2044                 return rc;
2045
2046         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2047         if (rc)
2048                 return rc;
2049
2050         memset(fc_conf, 0, sizeof(*fc_conf));
2051         if (bp->link_info->auto_pause)
2052                 fc_conf->autoneg = 1;
2053         switch (bp->link_info->pause) {
2054         case 0:
2055                 fc_conf->mode = RTE_FC_NONE;
2056                 break;
2057         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2058                 fc_conf->mode = RTE_FC_TX_PAUSE;
2059                 break;
2060         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2061                 fc_conf->mode = RTE_FC_RX_PAUSE;
2062                 break;
2063         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2064                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2065                 fc_conf->mode = RTE_FC_FULL;
2066                 break;
2067         }
2068         return 0;
2069 }
2070
2071 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2072                                struct rte_eth_fc_conf *fc_conf)
2073 {
2074         struct bnxt *bp = dev->data->dev_private;
2075         int rc;
2076
2077         rc = is_bnxt_in_error(bp);
2078         if (rc)
2079                 return rc;
2080
2081         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2082                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2083                 return -ENOTSUP;
2084         }
2085
2086         switch (fc_conf->mode) {
2087         case RTE_FC_NONE:
2088                 bp->link_info->auto_pause = 0;
2089                 bp->link_info->force_pause = 0;
2090                 break;
2091         case RTE_FC_RX_PAUSE:
2092                 if (fc_conf->autoneg) {
2093                         bp->link_info->auto_pause =
2094                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2095                         bp->link_info->force_pause = 0;
2096                 } else {
2097                         bp->link_info->auto_pause = 0;
2098                         bp->link_info->force_pause =
2099                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2100                 }
2101                 break;
2102         case RTE_FC_TX_PAUSE:
2103                 if (fc_conf->autoneg) {
2104                         bp->link_info->auto_pause =
2105                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2106                         bp->link_info->force_pause = 0;
2107                 } else {
2108                         bp->link_info->auto_pause = 0;
2109                         bp->link_info->force_pause =
2110                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2111                 }
2112                 break;
2113         case RTE_FC_FULL:
2114                 if (fc_conf->autoneg) {
2115                         bp->link_info->auto_pause =
2116                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2117                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2118                         bp->link_info->force_pause = 0;
2119                 } else {
2120                         bp->link_info->auto_pause = 0;
2121                         bp->link_info->force_pause =
2122                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2123                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2124                 }
2125                 break;
2126         }
2127         return bnxt_set_hwrm_link_config(bp, true);
2128 }
2129
2130 /* Add UDP tunneling port */
2131 static int
2132 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2133                          struct rte_eth_udp_tunnel *udp_tunnel)
2134 {
2135         struct bnxt *bp = eth_dev->data->dev_private;
2136         uint16_t tunnel_type = 0;
2137         int rc = 0;
2138
2139         rc = is_bnxt_in_error(bp);
2140         if (rc)
2141                 return rc;
2142
2143         switch (udp_tunnel->prot_type) {
2144         case RTE_TUNNEL_TYPE_VXLAN:
2145                 if (bp->vxlan_port_cnt) {
2146                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2147                                 udp_tunnel->udp_port);
2148                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2149                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2150                                 return -ENOSPC;
2151                         }
2152                         bp->vxlan_port_cnt++;
2153                         return 0;
2154                 }
2155                 tunnel_type =
2156                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2157                 bp->vxlan_port_cnt++;
2158                 break;
2159         case RTE_TUNNEL_TYPE_GENEVE:
2160                 if (bp->geneve_port_cnt) {
2161                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2162                                 udp_tunnel->udp_port);
2163                         if (bp->geneve_port != udp_tunnel->udp_port) {
2164                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2165                                 return -ENOSPC;
2166                         }
2167                         bp->geneve_port_cnt++;
2168                         return 0;
2169                 }
2170                 tunnel_type =
2171                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2172                 bp->geneve_port_cnt++;
2173                 break;
2174         default:
2175                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2176                 return -ENOTSUP;
2177         }
2178         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2179                                              tunnel_type);
2180         return rc;
2181 }
2182
2183 static int
2184 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2185                          struct rte_eth_udp_tunnel *udp_tunnel)
2186 {
2187         struct bnxt *bp = eth_dev->data->dev_private;
2188         uint16_t tunnel_type = 0;
2189         uint16_t port = 0;
2190         int rc = 0;
2191
2192         rc = is_bnxt_in_error(bp);
2193         if (rc)
2194                 return rc;
2195
2196         switch (udp_tunnel->prot_type) {
2197         case RTE_TUNNEL_TYPE_VXLAN:
2198                 if (!bp->vxlan_port_cnt) {
2199                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2200                         return -EINVAL;
2201                 }
2202                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2203                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2204                                 udp_tunnel->udp_port, bp->vxlan_port);
2205                         return -EINVAL;
2206                 }
2207                 if (--bp->vxlan_port_cnt)
2208                         return 0;
2209
2210                 tunnel_type =
2211                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2212                 port = bp->vxlan_fw_dst_port_id;
2213                 break;
2214         case RTE_TUNNEL_TYPE_GENEVE:
2215                 if (!bp->geneve_port_cnt) {
2216                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2217                         return -EINVAL;
2218                 }
2219                 if (bp->geneve_port != udp_tunnel->udp_port) {
2220                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2221                                 udp_tunnel->udp_port, bp->geneve_port);
2222                         return -EINVAL;
2223                 }
2224                 if (--bp->geneve_port_cnt)
2225                         return 0;
2226
2227                 tunnel_type =
2228                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2229                 port = bp->geneve_fw_dst_port_id;
2230                 break;
2231         default:
2232                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2233                 return -ENOTSUP;
2234         }
2235
2236         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2237         return rc;
2238 }
2239
2240 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2241 {
2242         struct bnxt_filter_info *filter;
2243         struct bnxt_vnic_info *vnic;
2244         int rc = 0;
2245         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2246
2247         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2248         filter = STAILQ_FIRST(&vnic->filter);
2249         while (filter) {
2250                 /* Search for this matching MAC+VLAN filter */
2251                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2252                         /* Delete the filter */
2253                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2254                         if (rc)
2255                                 return rc;
2256                         STAILQ_REMOVE(&vnic->filter, filter,
2257                                       bnxt_filter_info, next);
2258                         bnxt_free_filter(bp, filter);
2259                         PMD_DRV_LOG(INFO,
2260                                     "Deleted vlan filter for %d\n",
2261                                     vlan_id);
2262                         return 0;
2263                 }
2264                 filter = STAILQ_NEXT(filter, next);
2265         }
2266         return -ENOENT;
2267 }
2268
2269 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2270 {
2271         struct bnxt_filter_info *filter;
2272         struct bnxt_vnic_info *vnic;
2273         int rc = 0;
2274         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2275                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2276         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2277
2278         /* Implementation notes on the use of VNIC in this command:
2279          *
2280          * By default, these filters belong to default vnic for the function.
2281          * Once these filters are set up, only destination VNIC can be modified.
2282          * If the destination VNIC is not specified in this command,
2283          * then the HWRM shall only create an l2 context id.
2284          */
2285
2286         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2287         filter = STAILQ_FIRST(&vnic->filter);
2288         /* Check if the VLAN has already been added */
2289         while (filter) {
2290                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2291                         return -EEXIST;
2292
2293                 filter = STAILQ_NEXT(filter, next);
2294         }
2295
2296         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2297          * command to create MAC+VLAN filter with the right flags, enables set.
2298          */
2299         filter = bnxt_alloc_filter(bp);
2300         if (!filter) {
2301                 PMD_DRV_LOG(ERR,
2302                             "MAC/VLAN filter alloc failed\n");
2303                 return -ENOMEM;
2304         }
2305         /* MAC + VLAN ID filter */
2306         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2307          * untagged packets are received
2308          *
2309          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2310          * packets and only the programmed vlan's packets are received
2311          */
2312         filter->l2_ivlan = vlan_id;
2313         filter->l2_ivlan_mask = 0x0FFF;
2314         filter->enables |= en;
2315         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2316
2317         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2318         if (rc) {
2319                 /* Free the newly allocated filter as we were
2320                  * not able to create the filter in hardware.
2321                  */
2322                 bnxt_free_filter(bp, filter);
2323                 return rc;
2324         }
2325
2326         filter->mac_index = 0;
2327         /* Add this new filter to the list */
2328         if (vlan_id == 0)
2329                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2330         else
2331                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2332
2333         PMD_DRV_LOG(INFO,
2334                     "Added Vlan filter for %d\n", vlan_id);
2335         return rc;
2336 }
2337
2338 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2339                 uint16_t vlan_id, int on)
2340 {
2341         struct bnxt *bp = eth_dev->data->dev_private;
2342         int rc;
2343
2344         rc = is_bnxt_in_error(bp);
2345         if (rc)
2346                 return rc;
2347
2348         if (!eth_dev->data->dev_started) {
2349                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2350                 return -EINVAL;
2351         }
2352
2353         /* These operations apply to ALL existing MAC/VLAN filters */
2354         if (on)
2355                 return bnxt_add_vlan_filter(bp, vlan_id);
2356         else
2357                 return bnxt_del_vlan_filter(bp, vlan_id);
2358 }
2359
2360 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2361                                     struct bnxt_vnic_info *vnic)
2362 {
2363         struct bnxt_filter_info *filter;
2364         int rc;
2365
2366         filter = STAILQ_FIRST(&vnic->filter);
2367         while (filter) {
2368                 if (filter->mac_index == 0 &&
2369                     !memcmp(filter->l2_addr, bp->mac_addr,
2370                             RTE_ETHER_ADDR_LEN)) {
2371                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2372                         if (!rc) {
2373                                 STAILQ_REMOVE(&vnic->filter, filter,
2374                                               bnxt_filter_info, next);
2375                                 bnxt_free_filter(bp, filter);
2376                         }
2377                         return rc;
2378                 }
2379                 filter = STAILQ_NEXT(filter, next);
2380         }
2381         return 0;
2382 }
2383
2384 static int
2385 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2386 {
2387         struct bnxt_vnic_info *vnic;
2388         unsigned int i;
2389         int rc;
2390
2391         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2392         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2393                 /* Remove any VLAN filters programmed */
2394                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2395                         bnxt_del_vlan_filter(bp, i);
2396
2397                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2398                 if (rc)
2399                         return rc;
2400         } else {
2401                 /* Default filter will allow packets that match the
2402                  * dest mac. So, it has to be deleted, otherwise, we
2403                  * will endup receiving vlan packets for which the
2404                  * filter is not programmed, when hw-vlan-filter
2405                  * configuration is ON
2406                  */
2407                 bnxt_del_dflt_mac_filter(bp, vnic);
2408                 /* This filter will allow only untagged packets */
2409                 bnxt_add_vlan_filter(bp, 0);
2410         }
2411         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2412                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2413
2414         return 0;
2415 }
2416
2417 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2418 {
2419         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2420         unsigned int i;
2421         int rc;
2422
2423         /* Destroy vnic filters and vnic */
2424         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2425             DEV_RX_OFFLOAD_VLAN_FILTER) {
2426                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2427                         bnxt_del_vlan_filter(bp, i);
2428         }
2429         bnxt_del_dflt_mac_filter(bp, vnic);
2430
2431         rc = bnxt_hwrm_vnic_free(bp, vnic);
2432         if (rc)
2433                 return rc;
2434
2435         rte_free(vnic->fw_grp_ids);
2436         vnic->fw_grp_ids = NULL;
2437
2438         vnic->rx_queue_cnt = 0;
2439
2440         return 0;
2441 }
2442
2443 static int
2444 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2445 {
2446         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2447         int rc;
2448
2449         /* Destroy, recreate and reconfigure the default vnic */
2450         rc = bnxt_free_one_vnic(bp, 0);
2451         if (rc)
2452                 return rc;
2453
2454         /* default vnic 0 */
2455         rc = bnxt_setup_one_vnic(bp, 0);
2456         if (rc)
2457                 return rc;
2458
2459         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2460             DEV_RX_OFFLOAD_VLAN_FILTER) {
2461                 rc = bnxt_add_vlan_filter(bp, 0);
2462                 if (rc)
2463                         return rc;
2464                 rc = bnxt_restore_vlan_filters(bp);
2465                 if (rc)
2466                         return rc;
2467         } else {
2468                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2469                 if (rc)
2470                         return rc;
2471         }
2472
2473         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2474         if (rc)
2475                 return rc;
2476
2477         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2478                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2479
2480         return rc;
2481 }
2482
2483 static int
2484 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2485 {
2486         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2487         struct bnxt *bp = dev->data->dev_private;
2488         int rc;
2489
2490         rc = is_bnxt_in_error(bp);
2491         if (rc)
2492                 return rc;
2493
2494         /* Filter settings will get applied when port is started */
2495         if (!dev->data->dev_started)
2496                 return 0;
2497
2498         if (mask & ETH_VLAN_FILTER_MASK) {
2499                 /* Enable or disable VLAN filtering */
2500                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2501                 if (rc)
2502                         return rc;
2503         }
2504
2505         if (mask & ETH_VLAN_STRIP_MASK) {
2506                 /* Enable or disable VLAN stripping */
2507                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2508                 if (rc)
2509                         return rc;
2510         }
2511
2512         if (mask & ETH_VLAN_EXTEND_MASK) {
2513                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2514                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2515                 else
2516                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2517         }
2518
2519         return 0;
2520 }
2521
2522 static int
2523 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2524                       uint16_t tpid)
2525 {
2526         struct bnxt *bp = dev->data->dev_private;
2527         int qinq = dev->data->dev_conf.rxmode.offloads &
2528                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2529
2530         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2531             vlan_type != ETH_VLAN_TYPE_OUTER) {
2532                 PMD_DRV_LOG(ERR,
2533                             "Unsupported vlan type.");
2534                 return -EINVAL;
2535         }
2536         if (!qinq) {
2537                 PMD_DRV_LOG(ERR,
2538                             "QinQ not enabled. Needs to be ON as we can "
2539                             "accelerate only outer vlan\n");
2540                 return -EINVAL;
2541         }
2542
2543         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2544                 switch (tpid) {
2545                 case RTE_ETHER_TYPE_QINQ:
2546                         bp->outer_tpid_bd =
2547                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2548                                 break;
2549                 case RTE_ETHER_TYPE_VLAN:
2550                         bp->outer_tpid_bd =
2551                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2552                                 break;
2553                 case RTE_ETHER_TYPE_QINQ1:
2554                         bp->outer_tpid_bd =
2555                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2556                                 break;
2557                 case RTE_ETHER_TYPE_QINQ2:
2558                         bp->outer_tpid_bd =
2559                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2560                                 break;
2561                 case RTE_ETHER_TYPE_QINQ3:
2562                         bp->outer_tpid_bd =
2563                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2564                                 break;
2565                 default:
2566                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2567                         return -EINVAL;
2568                 }
2569                 bp->outer_tpid_bd |= tpid;
2570                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2571         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2572                 PMD_DRV_LOG(ERR,
2573                             "Can accelerate only outer vlan in QinQ\n");
2574                 return -EINVAL;
2575         }
2576
2577         return 0;
2578 }
2579
2580 static int
2581 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2582                              struct rte_ether_addr *addr)
2583 {
2584         struct bnxt *bp = dev->data->dev_private;
2585         /* Default Filter is tied to VNIC 0 */
2586         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2587         int rc;
2588
2589         rc = is_bnxt_in_error(bp);
2590         if (rc)
2591                 return rc;
2592
2593         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2594                 return -EPERM;
2595
2596         if (rte_is_zero_ether_addr(addr))
2597                 return -EINVAL;
2598
2599         /* Filter settings will get applied when port is started */
2600         if (!dev->data->dev_started)
2601                 return 0;
2602
2603         /* Check if the requested MAC is already added */
2604         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2605                 return 0;
2606
2607         /* Destroy filter and re-create it */
2608         bnxt_del_dflt_mac_filter(bp, vnic);
2609
2610         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2611         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2612                 /* This filter will allow only untagged packets */
2613                 rc = bnxt_add_vlan_filter(bp, 0);
2614         } else {
2615                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2616         }
2617
2618         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2619         return rc;
2620 }
2621
2622 static int
2623 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2624                           struct rte_ether_addr *mc_addr_set,
2625                           uint32_t nb_mc_addr)
2626 {
2627         struct bnxt *bp = eth_dev->data->dev_private;
2628         char *mc_addr_list = (char *)mc_addr_set;
2629         struct bnxt_vnic_info *vnic;
2630         uint32_t off = 0, i = 0;
2631         int rc;
2632
2633         rc = is_bnxt_in_error(bp);
2634         if (rc)
2635                 return rc;
2636
2637         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2638
2639         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2640                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2641                 goto allmulti;
2642         }
2643
2644         /* TODO Check for Duplicate mcast addresses */
2645         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2646         for (i = 0; i < nb_mc_addr; i++) {
2647                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2648                         RTE_ETHER_ADDR_LEN);
2649                 off += RTE_ETHER_ADDR_LEN;
2650         }
2651
2652         vnic->mc_addr_cnt = i;
2653         if (vnic->mc_addr_cnt)
2654                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2655         else
2656                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2657
2658 allmulti:
2659         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2660 }
2661
2662 static int
2663 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2664 {
2665         struct bnxt *bp = dev->data->dev_private;
2666         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2667         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2668         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2669         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2670         int ret;
2671
2672         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2673                         fw_major, fw_minor, fw_updt, fw_rsvd);
2674
2675         ret += 1; /* add the size of '\0' */
2676         if (fw_size < (uint32_t)ret)
2677                 return ret;
2678         else
2679                 return 0;
2680 }
2681
2682 static void
2683 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2684         struct rte_eth_rxq_info *qinfo)
2685 {
2686         struct bnxt *bp = dev->data->dev_private;
2687         struct bnxt_rx_queue *rxq;
2688
2689         if (is_bnxt_in_error(bp))
2690                 return;
2691
2692         rxq = dev->data->rx_queues[queue_id];
2693
2694         qinfo->mp = rxq->mb_pool;
2695         qinfo->scattered_rx = dev->data->scattered_rx;
2696         qinfo->nb_desc = rxq->nb_rx_desc;
2697
2698         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2699         qinfo->conf.rx_drop_en = rxq->drop_en;
2700         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2701         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2702 }
2703
2704 static void
2705 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2706         struct rte_eth_txq_info *qinfo)
2707 {
2708         struct bnxt *bp = dev->data->dev_private;
2709         struct bnxt_tx_queue *txq;
2710
2711         if (is_bnxt_in_error(bp))
2712                 return;
2713
2714         txq = dev->data->tx_queues[queue_id];
2715
2716         qinfo->nb_desc = txq->nb_tx_desc;
2717
2718         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2719         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2720         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2721
2722         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2723         qinfo->conf.tx_rs_thresh = 0;
2724         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2725         qinfo->conf.offloads = txq->offloads;
2726 }
2727
2728 static const struct {
2729         eth_rx_burst_t pkt_burst;
2730         const char *info;
2731 } bnxt_rx_burst_info[] = {
2732         {bnxt_recv_pkts,        "Scalar"},
2733 #if defined(RTE_ARCH_X86)
2734         {bnxt_recv_pkts_vec,    "Vector SSE"},
2735 #elif defined(RTE_ARCH_ARM64)
2736         {bnxt_recv_pkts_vec,    "Vector Neon"},
2737 #endif
2738 };
2739
2740 static int
2741 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2742                        struct rte_eth_burst_mode *mode)
2743 {
2744         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2745         size_t i;
2746
2747         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2748                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2749                         snprintf(mode->info, sizeof(mode->info), "%s",
2750                                  bnxt_rx_burst_info[i].info);
2751                         return 0;
2752                 }
2753         }
2754
2755         return -EINVAL;
2756 }
2757
2758 static const struct {
2759         eth_tx_burst_t pkt_burst;
2760         const char *info;
2761 } bnxt_tx_burst_info[] = {
2762         {bnxt_xmit_pkts,        "Scalar"},
2763 #if defined(RTE_ARCH_X86)
2764         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2765 #elif defined(RTE_ARCH_ARM64)
2766         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2767 #endif
2768 };
2769
2770 static int
2771 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2772                        struct rte_eth_burst_mode *mode)
2773 {
2774         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2775         size_t i;
2776
2777         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2778                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2779                         snprintf(mode->info, sizeof(mode->info), "%s",
2780                                  bnxt_tx_burst_info[i].info);
2781                         return 0;
2782                 }
2783         }
2784
2785         return -EINVAL;
2786 }
2787
2788 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2789 {
2790         struct bnxt *bp = eth_dev->data->dev_private;
2791         uint32_t new_pkt_size;
2792         uint32_t rc = 0;
2793         uint32_t i;
2794
2795         rc = is_bnxt_in_error(bp);
2796         if (rc)
2797                 return rc;
2798
2799         /* Exit if receive queues are not configured yet */
2800         if (!eth_dev->data->nb_rx_queues)
2801                 return rc;
2802
2803         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2804                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2805
2806         /*
2807          * Disallow any MTU change that would require scattered receive support
2808          * if it is not already enabled.
2809          */
2810         if (eth_dev->data->dev_started &&
2811             !eth_dev->data->scattered_rx &&
2812             (new_pkt_size >
2813              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2814                 PMD_DRV_LOG(ERR,
2815                             "MTU change would require scattered rx support. ");
2816                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2817                 return -EINVAL;
2818         }
2819
2820         if (new_mtu > RTE_ETHER_MTU) {
2821                 bp->flags |= BNXT_FLAG_JUMBO;
2822                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2823                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2824         } else {
2825                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2826                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2827                 bp->flags &= ~BNXT_FLAG_JUMBO;
2828         }
2829
2830         /* Is there a change in mtu setting? */
2831         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2832                 return rc;
2833
2834         for (i = 0; i < bp->nr_vnics; i++) {
2835                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2836                 uint16_t size = 0;
2837
2838                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2839                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2840                 if (rc)
2841                         break;
2842
2843                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2844                 size -= RTE_PKTMBUF_HEADROOM;
2845
2846                 if (size < new_mtu) {
2847                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2848                         if (rc)
2849                                 return rc;
2850                 }
2851         }
2852
2853         if (!rc)
2854                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2855
2856         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2857
2858         return rc;
2859 }
2860
2861 static int
2862 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2863 {
2864         struct bnxt *bp = dev->data->dev_private;
2865         uint16_t vlan = bp->vlan;
2866         int rc;
2867
2868         rc = is_bnxt_in_error(bp);
2869         if (rc)
2870                 return rc;
2871
2872         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2873                 PMD_DRV_LOG(ERR,
2874                         "PVID cannot be modified for this function\n");
2875                 return -ENOTSUP;
2876         }
2877         bp->vlan = on ? pvid : 0;
2878
2879         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2880         if (rc)
2881                 bp->vlan = vlan;
2882         return rc;
2883 }
2884
2885 static int
2886 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2887 {
2888         struct bnxt *bp = dev->data->dev_private;
2889         int rc;
2890
2891         rc = is_bnxt_in_error(bp);
2892         if (rc)
2893                 return rc;
2894
2895         return bnxt_hwrm_port_led_cfg(bp, true);
2896 }
2897
2898 static int
2899 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2900 {
2901         struct bnxt *bp = dev->data->dev_private;
2902         int rc;
2903
2904         rc = is_bnxt_in_error(bp);
2905         if (rc)
2906                 return rc;
2907
2908         return bnxt_hwrm_port_led_cfg(bp, false);
2909 }
2910
2911 static uint32_t
2912 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2913 {
2914         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2915         uint32_t desc = 0, raw_cons = 0, cons;
2916         struct bnxt_cp_ring_info *cpr;
2917         struct bnxt_rx_queue *rxq;
2918         struct rx_pkt_cmpl *rxcmp;
2919         int rc;
2920
2921         rc = is_bnxt_in_error(bp);
2922         if (rc)
2923                 return rc;
2924
2925         rxq = dev->data->rx_queues[rx_queue_id];
2926         cpr = rxq->cp_ring;
2927         raw_cons = cpr->cp_raw_cons;
2928
2929         while (1) {
2930                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2931                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2932                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2933
2934                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2935                         break;
2936                 } else {
2937                         raw_cons++;
2938                         desc++;
2939                 }
2940         }
2941
2942         return desc;
2943 }
2944
2945 static int
2946 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2947 {
2948         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2949         struct bnxt_rx_ring_info *rxr;
2950         struct bnxt_cp_ring_info *cpr;
2951         struct rte_mbuf *rx_buf;
2952         struct rx_pkt_cmpl *rxcmp;
2953         uint32_t cons, cp_cons;
2954         int rc;
2955
2956         if (!rxq)
2957                 return -EINVAL;
2958
2959         rc = is_bnxt_in_error(rxq->bp);
2960         if (rc)
2961                 return rc;
2962
2963         cpr = rxq->cp_ring;
2964         rxr = rxq->rx_ring;
2965
2966         if (offset >= rxq->nb_rx_desc)
2967                 return -EINVAL;
2968
2969         cons = RING_CMP(cpr->cp_ring_struct, offset);
2970         cp_cons = cpr->cp_raw_cons;
2971         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2972
2973         if (cons > cp_cons) {
2974                 if (CMPL_VALID(rxcmp, cpr->valid))
2975                         return RTE_ETH_RX_DESC_DONE;
2976         } else {
2977                 if (CMPL_VALID(rxcmp, !cpr->valid))
2978                         return RTE_ETH_RX_DESC_DONE;
2979         }
2980         rx_buf = rxr->rx_buf_ring[cons];
2981         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2982                 return RTE_ETH_RX_DESC_UNAVAIL;
2983
2984
2985         return RTE_ETH_RX_DESC_AVAIL;
2986 }
2987
2988 static int
2989 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2990 {
2991         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2992         struct bnxt_tx_ring_info *txr;
2993         struct bnxt_cp_ring_info *cpr;
2994         struct bnxt_sw_tx_bd *tx_buf;
2995         struct tx_pkt_cmpl *txcmp;
2996         uint32_t cons, cp_cons;
2997         int rc;
2998
2999         if (!txq)
3000                 return -EINVAL;
3001
3002         rc = is_bnxt_in_error(txq->bp);
3003         if (rc)
3004                 return rc;
3005
3006         cpr = txq->cp_ring;
3007         txr = txq->tx_ring;
3008
3009         if (offset >= txq->nb_tx_desc)
3010                 return -EINVAL;
3011
3012         cons = RING_CMP(cpr->cp_ring_struct, offset);
3013         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3014         cp_cons = cpr->cp_raw_cons;
3015
3016         if (cons > cp_cons) {
3017                 if (CMPL_VALID(txcmp, cpr->valid))
3018                         return RTE_ETH_TX_DESC_UNAVAIL;
3019         } else {
3020                 if (CMPL_VALID(txcmp, !cpr->valid))
3021                         return RTE_ETH_TX_DESC_UNAVAIL;
3022         }
3023         tx_buf = &txr->tx_buf_ring[cons];
3024         if (tx_buf->mbuf == NULL)
3025                 return RTE_ETH_TX_DESC_DONE;
3026
3027         return RTE_ETH_TX_DESC_FULL;
3028 }
3029
3030 int
3031 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3032                     enum rte_filter_type filter_type,
3033                     enum rte_filter_op filter_op, void *arg)
3034 {
3035         struct bnxt *bp = dev->data->dev_private;
3036         int ret = 0;
3037
3038         if (!bp)
3039                 return -EIO;
3040
3041         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3042                 struct bnxt_representor *vfr = dev->data->dev_private;
3043                 bp = vfr->parent_dev->data->dev_private;
3044                 /* parent is deleted while children are still valid */
3045                 if (!bp) {
3046                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3047                                     dev->data->port_id,
3048                                     filter_type,
3049                                     filter_op);
3050                         return -EIO;
3051                 }
3052         }
3053
3054         ret = is_bnxt_in_error(bp);
3055         if (ret)
3056                 return ret;
3057
3058         switch (filter_type) {
3059         case RTE_ETH_FILTER_GENERIC:
3060                 if (filter_op != RTE_ETH_FILTER_GET)
3061                         return -EINVAL;
3062
3063                 /* PMD supports thread-safe flow operations.  rte_flow API
3064                  * functions can avoid mutex for multi-thread safety.
3065                  */
3066                 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3067
3068                 if (BNXT_TRUFLOW_EN(bp))
3069                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3070                 else
3071                         *(const void **)arg = &bnxt_flow_ops;
3072                 break;
3073         default:
3074                 PMD_DRV_LOG(ERR,
3075                         "Filter type (%d) not supported", filter_type);
3076                 ret = -EINVAL;
3077                 break;
3078         }
3079         return ret;
3080 }
3081
3082 static const uint32_t *
3083 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3084 {
3085         static const uint32_t ptypes[] = {
3086                 RTE_PTYPE_L2_ETHER_VLAN,
3087                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3088                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3089                 RTE_PTYPE_L4_ICMP,
3090                 RTE_PTYPE_L4_TCP,
3091                 RTE_PTYPE_L4_UDP,
3092                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3093                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3094                 RTE_PTYPE_INNER_L4_ICMP,
3095                 RTE_PTYPE_INNER_L4_TCP,
3096                 RTE_PTYPE_INNER_L4_UDP,
3097                 RTE_PTYPE_UNKNOWN
3098         };
3099
3100         if (!dev->rx_pkt_burst)
3101                 return NULL;
3102
3103         return ptypes;
3104 }
3105
3106 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3107                          int reg_win)
3108 {
3109         uint32_t reg_base = *reg_arr & 0xfffff000;
3110         uint32_t win_off;
3111         int i;
3112
3113         for (i = 0; i < count; i++) {
3114                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3115                         return -ERANGE;
3116         }
3117         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3118         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3119         return 0;
3120 }
3121
3122 static int bnxt_map_ptp_regs(struct bnxt *bp)
3123 {
3124         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3125         uint32_t *reg_arr;
3126         int rc, i;
3127
3128         reg_arr = ptp->rx_regs;
3129         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3130         if (rc)
3131                 return rc;
3132
3133         reg_arr = ptp->tx_regs;
3134         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3135         if (rc)
3136                 return rc;
3137
3138         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3139                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3140
3141         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3142                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3143
3144         return 0;
3145 }
3146
3147 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3148 {
3149         rte_write32(0, (uint8_t *)bp->bar0 +
3150                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3151         rte_write32(0, (uint8_t *)bp->bar0 +
3152                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3153 }
3154
3155 static uint64_t bnxt_cc_read(struct bnxt *bp)
3156 {
3157         uint64_t ns;
3158
3159         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3160                               BNXT_GRCPF_REG_SYNC_TIME));
3161         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3162                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3163         return ns;
3164 }
3165
3166 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3167 {
3168         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3169         uint32_t fifo;
3170
3171         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3172                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3173         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3174                 return -EAGAIN;
3175
3176         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3177                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3178         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3179                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3180         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3181                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3182
3183         return 0;
3184 }
3185
3186 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3187 {
3188         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3189         struct bnxt_pf_info *pf = bp->pf;
3190         uint16_t port_id;
3191         uint32_t fifo;
3192
3193         if (!ptp)
3194                 return -ENODEV;
3195
3196         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3197                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3198         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3199                 return -EAGAIN;
3200
3201         port_id = pf->port_id;
3202         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3203                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3204
3205         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3206                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3207         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3208 /*              bnxt_clr_rx_ts(bp);       TBD  */
3209                 return -EBUSY;
3210         }
3211
3212         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3213                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3214         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3215                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3216
3217         return 0;
3218 }
3219
3220 static int
3221 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3222 {
3223         uint64_t ns;
3224         struct bnxt *bp = dev->data->dev_private;
3225         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3226
3227         if (!ptp)
3228                 return 0;
3229
3230         ns = rte_timespec_to_ns(ts);
3231         /* Set the timecounters to a new value. */
3232         ptp->tc.nsec = ns;
3233
3234         return 0;
3235 }
3236
3237 static int
3238 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3239 {
3240         struct bnxt *bp = dev->data->dev_private;
3241         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3242         uint64_t ns, systime_cycles = 0;
3243         int rc = 0;
3244
3245         if (!ptp)
3246                 return 0;
3247
3248         if (BNXT_CHIP_P5(bp))
3249                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3250                                              &systime_cycles);
3251         else
3252                 systime_cycles = bnxt_cc_read(bp);
3253
3254         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3255         *ts = rte_ns_to_timespec(ns);
3256
3257         return rc;
3258 }
3259 static int
3260 bnxt_timesync_enable(struct rte_eth_dev *dev)
3261 {
3262         struct bnxt *bp = dev->data->dev_private;
3263         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3264         uint32_t shift = 0;
3265         int rc;
3266
3267         if (!ptp)
3268                 return 0;
3269
3270         ptp->rx_filter = 1;
3271         ptp->tx_tstamp_en = 1;
3272         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3273
3274         rc = bnxt_hwrm_ptp_cfg(bp);
3275         if (rc)
3276                 return rc;
3277
3278         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3279         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3280         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3281
3282         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3283         ptp->tc.cc_shift = shift;
3284         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3285
3286         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3287         ptp->rx_tstamp_tc.cc_shift = shift;
3288         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3289
3290         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3291         ptp->tx_tstamp_tc.cc_shift = shift;
3292         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3293
3294         if (!BNXT_CHIP_P5(bp))
3295                 bnxt_map_ptp_regs(bp);
3296
3297         return 0;
3298 }
3299
3300 static int
3301 bnxt_timesync_disable(struct rte_eth_dev *dev)
3302 {
3303         struct bnxt *bp = dev->data->dev_private;
3304         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3305
3306         if (!ptp)
3307                 return 0;
3308
3309         ptp->rx_filter = 0;
3310         ptp->tx_tstamp_en = 0;
3311         ptp->rxctl = 0;
3312
3313         bnxt_hwrm_ptp_cfg(bp);
3314
3315         if (!BNXT_CHIP_P5(bp))
3316                 bnxt_unmap_ptp_regs(bp);
3317
3318         return 0;
3319 }
3320
3321 static int
3322 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3323                                  struct timespec *timestamp,
3324                                  uint32_t flags __rte_unused)
3325 {
3326         struct bnxt *bp = dev->data->dev_private;
3327         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3328         uint64_t rx_tstamp_cycles = 0;
3329         uint64_t ns;
3330
3331         if (!ptp)
3332                 return 0;
3333
3334         if (BNXT_CHIP_P5(bp))
3335                 rx_tstamp_cycles = ptp->rx_timestamp;
3336         else
3337                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3338
3339         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3340         *timestamp = rte_ns_to_timespec(ns);
3341         return  0;
3342 }
3343
3344 static int
3345 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3346                                  struct timespec *timestamp)
3347 {
3348         struct bnxt *bp = dev->data->dev_private;
3349         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3350         uint64_t tx_tstamp_cycles = 0;
3351         uint64_t ns;
3352         int rc = 0;
3353
3354         if (!ptp)
3355                 return 0;
3356
3357         if (BNXT_CHIP_P5(bp))
3358                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3359                                              &tx_tstamp_cycles);
3360         else
3361                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3362
3363         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3364         *timestamp = rte_ns_to_timespec(ns);
3365
3366         return rc;
3367 }
3368
3369 static int
3370 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3371 {
3372         struct bnxt *bp = dev->data->dev_private;
3373         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3374
3375         if (!ptp)
3376                 return 0;
3377
3378         ptp->tc.nsec += delta;
3379
3380         return 0;
3381 }
3382
3383 static int
3384 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3385 {
3386         struct bnxt *bp = dev->data->dev_private;
3387         int rc;
3388         uint32_t dir_entries;
3389         uint32_t entry_length;
3390
3391         rc = is_bnxt_in_error(bp);
3392         if (rc)
3393                 return rc;
3394
3395         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3396                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3397                     bp->pdev->addr.devid, bp->pdev->addr.function);
3398
3399         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3400         if (rc != 0)
3401                 return rc;
3402
3403         return dir_entries * entry_length;
3404 }
3405
3406 static int
3407 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3408                 struct rte_dev_eeprom_info *in_eeprom)
3409 {
3410         struct bnxt *bp = dev->data->dev_private;
3411         uint32_t index;
3412         uint32_t offset;
3413         int rc;
3414
3415         rc = is_bnxt_in_error(bp);
3416         if (rc)
3417                 return rc;
3418
3419         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3420                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3421                     bp->pdev->addr.devid, bp->pdev->addr.function,
3422                     in_eeprom->offset, in_eeprom->length);
3423
3424         if (in_eeprom->offset == 0) /* special offset value to get directory */
3425                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3426                                                 in_eeprom->data);
3427
3428         index = in_eeprom->offset >> 24;
3429         offset = in_eeprom->offset & 0xffffff;
3430
3431         if (index != 0)
3432                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3433                                            in_eeprom->length, in_eeprom->data);
3434
3435         return 0;
3436 }
3437
3438 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3439 {
3440         switch (dir_type) {
3441         case BNX_DIR_TYPE_CHIMP_PATCH:
3442         case BNX_DIR_TYPE_BOOTCODE:
3443         case BNX_DIR_TYPE_BOOTCODE_2:
3444         case BNX_DIR_TYPE_APE_FW:
3445         case BNX_DIR_TYPE_APE_PATCH:
3446         case BNX_DIR_TYPE_KONG_FW:
3447         case BNX_DIR_TYPE_KONG_PATCH:
3448         case BNX_DIR_TYPE_BONO_FW:
3449         case BNX_DIR_TYPE_BONO_PATCH:
3450                 /* FALLTHROUGH */
3451                 return true;
3452         }
3453
3454         return false;
3455 }
3456
3457 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3458 {
3459         switch (dir_type) {
3460         case BNX_DIR_TYPE_AVS:
3461         case BNX_DIR_TYPE_EXP_ROM_MBA:
3462         case BNX_DIR_TYPE_PCIE:
3463         case BNX_DIR_TYPE_TSCF_UCODE:
3464         case BNX_DIR_TYPE_EXT_PHY:
3465         case BNX_DIR_TYPE_CCM:
3466         case BNX_DIR_TYPE_ISCSI_BOOT:
3467         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3468         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3469                 /* FALLTHROUGH */
3470                 return true;
3471         }
3472
3473         return false;
3474 }
3475
3476 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3477 {
3478         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3479                 bnxt_dir_type_is_other_exec_format(dir_type);
3480 }
3481
3482 static int
3483 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3484                 struct rte_dev_eeprom_info *in_eeprom)
3485 {
3486         struct bnxt *bp = dev->data->dev_private;
3487         uint8_t index, dir_op;
3488         uint16_t type, ext, ordinal, attr;
3489         int rc;
3490
3491         rc = is_bnxt_in_error(bp);
3492         if (rc)
3493                 return rc;
3494
3495         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3496                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3497                     bp->pdev->addr.devid, bp->pdev->addr.function,
3498                     in_eeprom->offset, in_eeprom->length);
3499
3500         if (!BNXT_PF(bp)) {
3501                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3502                 return -EINVAL;
3503         }
3504
3505         type = in_eeprom->magic >> 16;
3506
3507         if (type == 0xffff) { /* special value for directory operations */
3508                 index = in_eeprom->magic & 0xff;
3509                 dir_op = in_eeprom->magic >> 8;
3510                 if (index == 0)
3511                         return -EINVAL;
3512                 switch (dir_op) {
3513                 case 0x0e: /* erase */
3514                         if (in_eeprom->offset != ~in_eeprom->magic)
3515                                 return -EINVAL;
3516                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3517                 default:
3518                         return -EINVAL;
3519                 }
3520         }
3521
3522         /* Create or re-write an NVM item: */
3523         if (bnxt_dir_type_is_executable(type) == true)
3524                 return -EOPNOTSUPP;
3525         ext = in_eeprom->magic & 0xffff;
3526         ordinal = in_eeprom->offset >> 16;
3527         attr = in_eeprom->offset & 0xffff;
3528
3529         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3530                                      in_eeprom->data, in_eeprom->length);
3531 }
3532
3533 /*
3534  * Initialization
3535  */
3536
3537 static const struct eth_dev_ops bnxt_dev_ops = {
3538         .dev_infos_get = bnxt_dev_info_get_op,
3539         .dev_close = bnxt_dev_close_op,
3540         .dev_configure = bnxt_dev_configure_op,
3541         .dev_start = bnxt_dev_start_op,
3542         .dev_stop = bnxt_dev_stop_op,
3543         .dev_set_link_up = bnxt_dev_set_link_up_op,
3544         .dev_set_link_down = bnxt_dev_set_link_down_op,
3545         .stats_get = bnxt_stats_get_op,
3546         .stats_reset = bnxt_stats_reset_op,
3547         .rx_queue_setup = bnxt_rx_queue_setup_op,
3548         .rx_queue_release = bnxt_rx_queue_release_op,
3549         .tx_queue_setup = bnxt_tx_queue_setup_op,
3550         .tx_queue_release = bnxt_tx_queue_release_op,
3551         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3552         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3553         .reta_update = bnxt_reta_update_op,
3554         .reta_query = bnxt_reta_query_op,
3555         .rss_hash_update = bnxt_rss_hash_update_op,
3556         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3557         .link_update = bnxt_link_update_op,
3558         .promiscuous_enable = bnxt_promiscuous_enable_op,
3559         .promiscuous_disable = bnxt_promiscuous_disable_op,
3560         .allmulticast_enable = bnxt_allmulticast_enable_op,
3561         .allmulticast_disable = bnxt_allmulticast_disable_op,
3562         .mac_addr_add = bnxt_mac_addr_add_op,
3563         .mac_addr_remove = bnxt_mac_addr_remove_op,
3564         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3565         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3566         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3567         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3568         .vlan_filter_set = bnxt_vlan_filter_set_op,
3569         .vlan_offload_set = bnxt_vlan_offload_set_op,
3570         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3571         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3572         .mtu_set = bnxt_mtu_set_op,
3573         .mac_addr_set = bnxt_set_default_mac_addr_op,
3574         .xstats_get = bnxt_dev_xstats_get_op,
3575         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3576         .xstats_reset = bnxt_dev_xstats_reset_op,
3577         .fw_version_get = bnxt_fw_version_get,
3578         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3579         .rxq_info_get = bnxt_rxq_info_get_op,
3580         .txq_info_get = bnxt_txq_info_get_op,
3581         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3582         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3583         .dev_led_on = bnxt_dev_led_on_op,
3584         .dev_led_off = bnxt_dev_led_off_op,
3585         .rx_queue_start = bnxt_rx_queue_start,
3586         .rx_queue_stop = bnxt_rx_queue_stop,
3587         .tx_queue_start = bnxt_tx_queue_start,
3588         .tx_queue_stop = bnxt_tx_queue_stop,
3589         .filter_ctrl = bnxt_filter_ctrl_op,
3590         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3591         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3592         .get_eeprom           = bnxt_get_eeprom_op,
3593         .set_eeprom           = bnxt_set_eeprom_op,
3594         .timesync_enable      = bnxt_timesync_enable,
3595         .timesync_disable     = bnxt_timesync_disable,
3596         .timesync_read_time   = bnxt_timesync_read_time,
3597         .timesync_write_time   = bnxt_timesync_write_time,
3598         .timesync_adjust_time = bnxt_timesync_adjust_time,
3599         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3600         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3601 };
3602
3603 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3604 {
3605         uint32_t offset;
3606
3607         /* Only pre-map the reset GRC registers using window 3 */
3608         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3609                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3610
3611         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3612
3613         return offset;
3614 }
3615
3616 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3617 {
3618         struct bnxt_error_recovery_info *info = bp->recovery_info;
3619         uint32_t reg_base = 0xffffffff;
3620         int i;
3621
3622         /* Only pre-map the monitoring GRC registers using window 2 */
3623         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3624                 uint32_t reg = info->status_regs[i];
3625
3626                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3627                         continue;
3628
3629                 if (reg_base == 0xffffffff)
3630                         reg_base = reg & 0xfffff000;
3631                 if ((reg & 0xfffff000) != reg_base)
3632                         return -ERANGE;
3633
3634                 /* Use mask 0xffc as the Lower 2 bits indicates
3635                  * address space location
3636                  */
3637                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3638                                                 (reg & 0xffc);
3639         }
3640
3641         if (reg_base == 0xffffffff)
3642                 return 0;
3643
3644         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3645                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3646
3647         return 0;
3648 }
3649
3650 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3651 {
3652         struct bnxt_error_recovery_info *info = bp->recovery_info;
3653         uint32_t delay = info->delay_after_reset[index];
3654         uint32_t val = info->reset_reg_val[index];
3655         uint32_t reg = info->reset_reg[index];
3656         uint32_t type, offset;
3657
3658         type = BNXT_FW_STATUS_REG_TYPE(reg);
3659         offset = BNXT_FW_STATUS_REG_OFF(reg);
3660
3661         switch (type) {
3662         case BNXT_FW_STATUS_REG_TYPE_CFG:
3663                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3664                 break;
3665         case BNXT_FW_STATUS_REG_TYPE_GRC:
3666                 offset = bnxt_map_reset_regs(bp, offset);
3667                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3668                 break;
3669         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3670                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3671                 break;
3672         }
3673         /* wait on a specific interval of time until core reset is complete */
3674         if (delay)
3675                 rte_delay_ms(delay);
3676 }
3677
3678 static void bnxt_dev_cleanup(struct bnxt *bp)
3679 {
3680         bp->eth_dev->data->dev_link.link_status = 0;
3681         bp->link_info->link_up = 0;
3682         if (bp->eth_dev->data->dev_started)
3683                 bnxt_dev_stop_op(bp->eth_dev);
3684
3685         bnxt_uninit_resources(bp, true);
3686 }
3687
3688 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3689 {
3690         struct rte_eth_dev *dev = bp->eth_dev;
3691         struct rte_vlan_filter_conf *vfc;
3692         int vidx, vbit, rc;
3693         uint16_t vlan_id;
3694
3695         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3696                 vfc = &dev->data->vlan_filter_conf;
3697                 vidx = vlan_id / 64;
3698                 vbit = vlan_id % 64;
3699
3700                 /* Each bit corresponds to a VLAN id */
3701                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3702                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3703                         if (rc)
3704                                 return rc;
3705                 }
3706         }
3707
3708         return 0;
3709 }
3710
3711 static int bnxt_restore_mac_filters(struct bnxt *bp)
3712 {
3713         struct rte_eth_dev *dev = bp->eth_dev;
3714         struct rte_eth_dev_info dev_info;
3715         struct rte_ether_addr *addr;
3716         uint64_t pool_mask;
3717         uint32_t pool = 0;
3718         uint16_t i;
3719         int rc;
3720
3721         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3722                 return 0;
3723
3724         rc = bnxt_dev_info_get_op(dev, &dev_info);
3725         if (rc)
3726                 return rc;
3727
3728         /* replay MAC address configuration */
3729         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3730                 addr = &dev->data->mac_addrs[i];
3731
3732                 /* skip zero address */
3733                 if (rte_is_zero_ether_addr(addr))
3734                         continue;
3735
3736                 pool = 0;
3737                 pool_mask = dev->data->mac_pool_sel[i];
3738
3739                 do {
3740                         if (pool_mask & 1ULL) {
3741                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3742                                 if (rc)
3743                                         return rc;
3744                         }
3745                         pool_mask >>= 1;
3746                         pool++;
3747                 } while (pool_mask);
3748         }
3749
3750         return 0;
3751 }
3752
3753 static int bnxt_restore_filters(struct bnxt *bp)
3754 {
3755         struct rte_eth_dev *dev = bp->eth_dev;
3756         int ret = 0;
3757
3758         if (dev->data->all_multicast) {
3759                 ret = bnxt_allmulticast_enable_op(dev);
3760                 if (ret)
3761                         return ret;
3762         }
3763         if (dev->data->promiscuous) {
3764                 ret = bnxt_promiscuous_enable_op(dev);
3765                 if (ret)
3766                         return ret;
3767         }
3768
3769         ret = bnxt_restore_mac_filters(bp);
3770         if (ret)
3771                 return ret;
3772
3773         ret = bnxt_restore_vlan_filters(bp);
3774         /* TODO restore other filters as well */
3775         return ret;
3776 }
3777
3778 static void bnxt_dev_recover(void *arg)
3779 {
3780         struct bnxt *bp = arg;
3781         int timeout = bp->fw_reset_max_msecs;
3782         int rc = 0;
3783
3784         /* Clear Error flag so that device re-init should happen */
3785         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3786
3787         do {
3788                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3789                 if (rc == 0)
3790                         break;
3791                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3792                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3793         } while (rc && timeout);
3794
3795         if (rc) {
3796                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3797                 goto err;
3798         }
3799
3800         rc = bnxt_init_resources(bp, true);
3801         if (rc) {
3802                 PMD_DRV_LOG(ERR,
3803                             "Failed to initialize resources after reset\n");
3804                 goto err;
3805         }
3806         /* clear reset flag as the device is initialized now */
3807         bp->flags &= ~BNXT_FLAG_FW_RESET;
3808
3809         rc = bnxt_dev_start_op(bp->eth_dev);
3810         if (rc) {
3811                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3812                 goto err_start;
3813         }
3814
3815         rc = bnxt_restore_filters(bp);
3816         if (rc)
3817                 goto err_start;
3818
3819         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3820         return;
3821 err_start:
3822         bnxt_dev_stop_op(bp->eth_dev);
3823 err:
3824         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3825         bnxt_uninit_resources(bp, false);
3826         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3827 }
3828
3829 void bnxt_dev_reset_and_resume(void *arg)
3830 {
3831         struct bnxt *bp = arg;
3832         int rc;
3833
3834         bnxt_dev_cleanup(bp);
3835
3836         bnxt_wait_for_device_shutdown(bp);
3837
3838         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3839                                bnxt_dev_recover, (void *)bp);
3840         if (rc)
3841                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3842 }
3843
3844 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3845 {
3846         struct bnxt_error_recovery_info *info = bp->recovery_info;
3847         uint32_t reg = info->status_regs[index];
3848         uint32_t type, offset, val = 0;
3849
3850         type = BNXT_FW_STATUS_REG_TYPE(reg);
3851         offset = BNXT_FW_STATUS_REG_OFF(reg);
3852
3853         switch (type) {
3854         case BNXT_FW_STATUS_REG_TYPE_CFG:
3855                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3856                 break;
3857         case BNXT_FW_STATUS_REG_TYPE_GRC:
3858                 offset = info->mapped_status_regs[index];
3859                 /* FALLTHROUGH */
3860         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3861                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3862                                        offset));
3863                 break;
3864         }
3865
3866         return val;
3867 }
3868
3869 static int bnxt_fw_reset_all(struct bnxt *bp)
3870 {
3871         struct bnxt_error_recovery_info *info = bp->recovery_info;
3872         uint32_t i;
3873         int rc = 0;
3874
3875         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3876                 /* Reset through master function driver */
3877                 for (i = 0; i < info->reg_array_cnt; i++)
3878                         bnxt_write_fw_reset_reg(bp, i);
3879                 /* Wait for time specified by FW after triggering reset */
3880                 rte_delay_ms(info->master_func_wait_period_after_reset);
3881         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3882                 /* Reset with the help of Kong processor */
3883                 rc = bnxt_hwrm_fw_reset(bp);
3884                 if (rc)
3885                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3886         }
3887
3888         return rc;
3889 }
3890
3891 static void bnxt_fw_reset_cb(void *arg)
3892 {
3893         struct bnxt *bp = arg;
3894         struct bnxt_error_recovery_info *info = bp->recovery_info;
3895         int rc = 0;
3896
3897         /* Only Master function can do FW reset */
3898         if (bnxt_is_master_func(bp) &&
3899             bnxt_is_recovery_enabled(bp)) {
3900                 rc = bnxt_fw_reset_all(bp);
3901                 if (rc) {
3902                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3903                         return;
3904                 }
3905         }
3906
3907         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3908          * EXCEPTION_FATAL_ASYNC event to all the functions
3909          * (including MASTER FUNC). After receiving this Async, all the active
3910          * drivers should treat this case as FW initiated recovery
3911          */
3912         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3913                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3914                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3915
3916                 /* To recover from error */
3917                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3918                                   (void *)bp);
3919         }
3920 }
3921
3922 /* Driver should poll FW heartbeat, reset_counter with the frequency
3923  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3924  * When the driver detects heartbeat stop or change in reset_counter,
3925  * it has to trigger a reset to recover from the error condition.
3926  * A “master PF” is the function who will have the privilege to
3927  * initiate the chimp reset. The master PF will be elected by the
3928  * firmware and will be notified through async message.
3929  */
3930 static void bnxt_check_fw_health(void *arg)
3931 {
3932         struct bnxt *bp = arg;
3933         struct bnxt_error_recovery_info *info = bp->recovery_info;
3934         uint32_t val = 0, wait_msec;
3935
3936         if (!info || !bnxt_is_recovery_enabled(bp) ||
3937             is_bnxt_in_error(bp))
3938                 return;
3939
3940         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3941         if (val == info->last_heart_beat)
3942                 goto reset;
3943
3944         info->last_heart_beat = val;
3945
3946         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3947         if (val != info->last_reset_counter)
3948                 goto reset;
3949
3950         info->last_reset_counter = val;
3951
3952         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3953                           bnxt_check_fw_health, (void *)bp);
3954
3955         return;
3956 reset:
3957         /* Stop DMA to/from device */
3958         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3959         bp->flags |= BNXT_FLAG_FW_RESET;
3960
3961         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3962
3963         if (bnxt_is_master_func(bp))
3964                 wait_msec = info->master_func_wait_period;
3965         else
3966                 wait_msec = info->normal_func_wait_period;
3967
3968         rte_eal_alarm_set(US_PER_MS * wait_msec,
3969                           bnxt_fw_reset_cb, (void *)bp);
3970 }
3971
3972 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3973 {
3974         uint32_t polling_freq;
3975
3976         pthread_mutex_lock(&bp->health_check_lock);
3977
3978         if (!bnxt_is_recovery_enabled(bp))
3979                 goto done;
3980
3981         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3982                 goto done;
3983
3984         polling_freq = bp->recovery_info->driver_polling_freq;
3985
3986         rte_eal_alarm_set(US_PER_MS * polling_freq,
3987                           bnxt_check_fw_health, (void *)bp);
3988         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3989
3990 done:
3991         pthread_mutex_unlock(&bp->health_check_lock);
3992 }
3993
3994 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3995 {
3996         if (!bnxt_is_recovery_enabled(bp))
3997                 return;
3998
3999         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4000         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4001 }
4002
4003 static bool bnxt_vf_pciid(uint16_t device_id)
4004 {
4005         switch (device_id) {
4006         case BROADCOM_DEV_ID_57304_VF:
4007         case BROADCOM_DEV_ID_57406_VF:
4008         case BROADCOM_DEV_ID_5731X_VF:
4009         case BROADCOM_DEV_ID_5741X_VF:
4010         case BROADCOM_DEV_ID_57414_VF:
4011         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4012         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4013         case BROADCOM_DEV_ID_58802_VF:
4014         case BROADCOM_DEV_ID_57500_VF1:
4015         case BROADCOM_DEV_ID_57500_VF2:
4016         case BROADCOM_DEV_ID_58818_VF:
4017                 /* FALLTHROUGH */
4018                 return true;
4019         default:
4020                 return false;
4021         }
4022 }
4023
4024 /* Phase 5 device */
4025 static bool bnxt_p5_device(uint16_t device_id)
4026 {
4027         switch (device_id) {
4028         case BROADCOM_DEV_ID_57508:
4029         case BROADCOM_DEV_ID_57504:
4030         case BROADCOM_DEV_ID_57502:
4031         case BROADCOM_DEV_ID_57508_MF1:
4032         case BROADCOM_DEV_ID_57504_MF1:
4033         case BROADCOM_DEV_ID_57502_MF1:
4034         case BROADCOM_DEV_ID_57508_MF2:
4035         case BROADCOM_DEV_ID_57504_MF2:
4036         case BROADCOM_DEV_ID_57502_MF2:
4037         case BROADCOM_DEV_ID_57500_VF1:
4038         case BROADCOM_DEV_ID_57500_VF2:
4039         case BROADCOM_DEV_ID_58812:
4040         case BROADCOM_DEV_ID_58814:
4041         case BROADCOM_DEV_ID_58818:
4042         case BROADCOM_DEV_ID_58818_VF:
4043                 /* FALLTHROUGH */
4044                 return true;
4045         default:
4046                 return false;
4047         }
4048 }
4049
4050 bool bnxt_stratus_device(struct bnxt *bp)
4051 {
4052         uint16_t device_id = bp->pdev->id.device_id;
4053
4054         switch (device_id) {
4055         case BROADCOM_DEV_ID_STRATUS_NIC:
4056         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4057         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4058                 /* FALLTHROUGH */
4059                 return true;
4060         default:
4061                 return false;
4062         }
4063 }
4064
4065 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4066 {
4067         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4068         struct bnxt *bp = eth_dev->data->dev_private;
4069
4070         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4071         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4072         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4073         if (!bp->bar0 || !bp->doorbell_base) {
4074                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4075                 return -ENODEV;
4076         }
4077
4078         bp->eth_dev = eth_dev;
4079         bp->pdev = pci_dev;
4080
4081         return 0;
4082 }
4083
4084 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4085                                   struct bnxt_ctx_pg_info *ctx_pg,
4086                                   uint32_t mem_size,
4087                                   const char *suffix,
4088                                   uint16_t idx)
4089 {
4090         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4091         const struct rte_memzone *mz = NULL;
4092         char mz_name[RTE_MEMZONE_NAMESIZE];
4093         rte_iova_t mz_phys_addr;
4094         uint64_t valid_bits = 0;
4095         uint32_t sz;
4096         int i;
4097
4098         if (!mem_size)
4099                 return 0;
4100
4101         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4102                          BNXT_PAGE_SIZE;
4103         rmem->page_size = BNXT_PAGE_SIZE;
4104         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4105         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4106         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4107
4108         valid_bits = PTU_PTE_VALID;
4109
4110         if (rmem->nr_pages > 1) {
4111                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4112                          "bnxt_ctx_pg_tbl%s_%x_%d",
4113                          suffix, idx, bp->eth_dev->data->port_id);
4114                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4115                 mz = rte_memzone_lookup(mz_name);
4116                 if (!mz) {
4117                         mz = rte_memzone_reserve_aligned(mz_name,
4118                                                 rmem->nr_pages * 8,
4119                                                 SOCKET_ID_ANY,
4120                                                 RTE_MEMZONE_2MB |
4121                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4122                                                 RTE_MEMZONE_IOVA_CONTIG,
4123                                                 BNXT_PAGE_SIZE);
4124                         if (mz == NULL)
4125                                 return -ENOMEM;
4126                 }
4127
4128                 memset(mz->addr, 0, mz->len);
4129                 mz_phys_addr = mz->iova;
4130
4131                 rmem->pg_tbl = mz->addr;
4132                 rmem->pg_tbl_map = mz_phys_addr;
4133                 rmem->pg_tbl_mz = mz;
4134         }
4135
4136         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4137                  suffix, idx, bp->eth_dev->data->port_id);
4138         mz = rte_memzone_lookup(mz_name);
4139         if (!mz) {
4140                 mz = rte_memzone_reserve_aligned(mz_name,
4141                                                  mem_size,
4142                                                  SOCKET_ID_ANY,
4143                                                  RTE_MEMZONE_1GB |
4144                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4145                                                  RTE_MEMZONE_IOVA_CONTIG,
4146                                                  BNXT_PAGE_SIZE);
4147                 if (mz == NULL)
4148                         return -ENOMEM;
4149         }
4150
4151         memset(mz->addr, 0, mz->len);
4152         mz_phys_addr = mz->iova;
4153
4154         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4155                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4156                 rmem->dma_arr[i] = mz_phys_addr + sz;
4157
4158                 if (rmem->nr_pages > 1) {
4159                         if (i == rmem->nr_pages - 2 &&
4160                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4161                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4162                         else if (i == rmem->nr_pages - 1 &&
4163                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4164                                 valid_bits |= PTU_PTE_LAST;
4165
4166                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4167                                                            valid_bits);
4168                 }
4169         }
4170
4171         rmem->mz = mz;
4172         if (rmem->vmem_size)
4173                 rmem->vmem = (void **)mz->addr;
4174         rmem->dma_arr[0] = mz_phys_addr;
4175         return 0;
4176 }
4177
4178 static void bnxt_free_ctx_mem(struct bnxt *bp)
4179 {
4180         int i;
4181
4182         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4183                 return;
4184
4185         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4186         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4187         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4188         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4189         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4190         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4191         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4192         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4193         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4194         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4195         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4196
4197         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4198                 if (bp->ctx->tqm_mem[i])
4199                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4200         }
4201
4202         rte_free(bp->ctx);
4203         bp->ctx = NULL;
4204 }
4205
4206 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4207
4208 #define min_t(type, x, y) ({                    \
4209         type __min1 = (x);                      \
4210         type __min2 = (y);                      \
4211         __min1 < __min2 ? __min1 : __min2; })
4212
4213 #define max_t(type, x, y) ({                    \
4214         type __max1 = (x);                      \
4215         type __max2 = (y);                      \
4216         __max1 > __max2 ? __max1 : __max2; })
4217
4218 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4219
4220 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4221 {
4222         struct bnxt_ctx_pg_info *ctx_pg;
4223         struct bnxt_ctx_mem_info *ctx;
4224         uint32_t mem_size, ena, entries;
4225         uint32_t entries_sp, min;
4226         int i, rc;
4227
4228         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4229         if (rc) {
4230                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4231                 return rc;
4232         }
4233         ctx = bp->ctx;
4234         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4235                 return 0;
4236
4237         ctx_pg = &ctx->qp_mem;
4238         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4239         if (ctx->qp_entry_size) {
4240                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4241                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4242                 if (rc)
4243                         return rc;
4244         }
4245
4246         ctx_pg = &ctx->srq_mem;
4247         ctx_pg->entries = ctx->srq_max_l2_entries;
4248         if (ctx->srq_entry_size) {
4249                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4250                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4251                 if (rc)
4252                         return rc;
4253         }
4254
4255         ctx_pg = &ctx->cq_mem;
4256         ctx_pg->entries = ctx->cq_max_l2_entries;
4257         if (ctx->cq_entry_size) {
4258                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4259                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4260                 if (rc)
4261                         return rc;
4262         }
4263
4264         ctx_pg = &ctx->vnic_mem;
4265         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4266                 ctx->vnic_max_ring_table_entries;
4267         if (ctx->vnic_entry_size) {
4268                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4269                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4270                 if (rc)
4271                         return rc;
4272         }
4273
4274         ctx_pg = &ctx->stat_mem;
4275         ctx_pg->entries = ctx->stat_max_entries;
4276         if (ctx->stat_entry_size) {
4277                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4278                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4279                 if (rc)
4280                         return rc;
4281         }
4282
4283         min = ctx->tqm_min_entries_per_ring;
4284
4285         entries_sp = ctx->qp_max_l2_entries +
4286                      ctx->vnic_max_vnic_entries +
4287                      2 * ctx->qp_min_qp1_entries + min;
4288         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4289
4290         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4291         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4292         entries = clamp_t(uint32_t, entries, min,
4293                           ctx->tqm_max_entries_per_ring);
4294         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4295                 ctx_pg = ctx->tqm_mem[i];
4296                 ctx_pg->entries = i ? entries : entries_sp;
4297                 if (ctx->tqm_entry_size) {
4298                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4299                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4300                         if (rc)
4301                                 return rc;
4302                 }
4303                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4304         }
4305
4306         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4307         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4308         if (rc)
4309                 PMD_DRV_LOG(ERR,
4310                             "Failed to configure context mem: rc = %d\n", rc);
4311         else
4312                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4313
4314         return rc;
4315 }
4316
4317 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4318 {
4319         struct rte_pci_device *pci_dev = bp->pdev;
4320         char mz_name[RTE_MEMZONE_NAMESIZE];
4321         const struct rte_memzone *mz = NULL;
4322         uint32_t total_alloc_len;
4323         rte_iova_t mz_phys_addr;
4324
4325         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4326                 return 0;
4327
4328         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4329                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4330                  pci_dev->addr.bus, pci_dev->addr.devid,
4331                  pci_dev->addr.function, "rx_port_stats");
4332         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4333         mz = rte_memzone_lookup(mz_name);
4334         total_alloc_len =
4335                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4336                                        sizeof(struct rx_port_stats_ext) + 512);
4337         if (!mz) {
4338                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4339                                          SOCKET_ID_ANY,
4340                                          RTE_MEMZONE_2MB |
4341                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4342                                          RTE_MEMZONE_IOVA_CONTIG);
4343                 if (mz == NULL)
4344                         return -ENOMEM;
4345         }
4346         memset(mz->addr, 0, mz->len);
4347         mz_phys_addr = mz->iova;
4348
4349         bp->rx_mem_zone = (const void *)mz;
4350         bp->hw_rx_port_stats = mz->addr;
4351         bp->hw_rx_port_stats_map = mz_phys_addr;
4352
4353         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4354                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4355                  pci_dev->addr.bus, pci_dev->addr.devid,
4356                  pci_dev->addr.function, "tx_port_stats");
4357         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4358         mz = rte_memzone_lookup(mz_name);
4359         total_alloc_len =
4360                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4361                                        sizeof(struct tx_port_stats_ext) + 512);
4362         if (!mz) {
4363                 mz = rte_memzone_reserve(mz_name,
4364                                          total_alloc_len,
4365                                          SOCKET_ID_ANY,
4366                                          RTE_MEMZONE_2MB |
4367                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4368                                          RTE_MEMZONE_IOVA_CONTIG);
4369                 if (mz == NULL)
4370                         return -ENOMEM;
4371         }
4372         memset(mz->addr, 0, mz->len);
4373         mz_phys_addr = mz->iova;
4374
4375         bp->tx_mem_zone = (const void *)mz;
4376         bp->hw_tx_port_stats = mz->addr;
4377         bp->hw_tx_port_stats_map = mz_phys_addr;
4378         bp->flags |= BNXT_FLAG_PORT_STATS;
4379
4380         /* Display extended statistics if FW supports it */
4381         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4382             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4383             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4384                 return 0;
4385
4386         bp->hw_rx_port_stats_ext = (void *)
4387                 ((uint8_t *)bp->hw_rx_port_stats +
4388                  sizeof(struct rx_port_stats));
4389         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4390                 sizeof(struct rx_port_stats);
4391         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4392
4393         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4394             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4395                 bp->hw_tx_port_stats_ext = (void *)
4396                         ((uint8_t *)bp->hw_tx_port_stats +
4397                          sizeof(struct tx_port_stats));
4398                 bp->hw_tx_port_stats_ext_map =
4399                         bp->hw_tx_port_stats_map +
4400                         sizeof(struct tx_port_stats);
4401                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4402         }
4403
4404         return 0;
4405 }
4406
4407 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4408 {
4409         struct bnxt *bp = eth_dev->data->dev_private;
4410         int rc = 0;
4411
4412         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4413                                                RTE_ETHER_ADDR_LEN *
4414                                                bp->max_l2_ctx,
4415                                                0);
4416         if (eth_dev->data->mac_addrs == NULL) {
4417                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4418                 return -ENOMEM;
4419         }
4420
4421         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4422                 if (BNXT_PF(bp))
4423                         return -EINVAL;
4424
4425                 /* Generate a random MAC address, if none was assigned by PF */
4426                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4427                 bnxt_eth_hw_addr_random(bp->mac_addr);
4428                 PMD_DRV_LOG(INFO,
4429                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4430                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4431                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4432
4433                 rc = bnxt_hwrm_set_mac(bp);
4434                 if (rc)
4435                         return rc;
4436         }
4437
4438         /* Copy the permanent MAC from the FUNC_QCAPS response */
4439         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4440
4441         return rc;
4442 }
4443
4444 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4445 {
4446         int rc = 0;
4447
4448         /* MAC is already configured in FW */
4449         if (BNXT_HAS_DFLT_MAC_SET(bp))
4450                 return 0;
4451
4452         /* Restore the old MAC configured */
4453         rc = bnxt_hwrm_set_mac(bp);
4454         if (rc)
4455                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4456
4457         return rc;
4458 }
4459
4460 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4461 {
4462         if (!BNXT_PF(bp))
4463                 return;
4464
4465         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4466
4467         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4468                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4469         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4470         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4471         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4472         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4473 }
4474
4475 uint16_t
4476 bnxt_get_svif(uint16_t port_id, bool func_svif,
4477               enum bnxt_ulp_intf_type type)
4478 {
4479         struct rte_eth_dev *eth_dev;
4480         struct bnxt *bp;
4481
4482         eth_dev = &rte_eth_devices[port_id];
4483         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4484                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4485                 if (!vfr)
4486                         return 0;
4487
4488                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4489                         return vfr->svif;
4490
4491                 eth_dev = vfr->parent_dev;
4492         }
4493
4494         bp = eth_dev->data->dev_private;
4495
4496         return func_svif ? bp->func_svif : bp->port_svif;
4497 }
4498
4499 uint16_t
4500 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4501 {
4502         struct rte_eth_dev *eth_dev;
4503         struct bnxt_vnic_info *vnic;
4504         struct bnxt *bp;
4505
4506         eth_dev = &rte_eth_devices[port];
4507         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4508                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4509                 if (!vfr)
4510                         return 0;
4511
4512                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4513                         return vfr->dflt_vnic_id;
4514
4515                 eth_dev = vfr->parent_dev;
4516         }
4517
4518         bp = eth_dev->data->dev_private;
4519
4520         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4521
4522         return vnic->fw_vnic_id;
4523 }
4524
4525 uint16_t
4526 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4527 {
4528         struct rte_eth_dev *eth_dev;
4529         struct bnxt *bp;
4530
4531         eth_dev = &rte_eth_devices[port];
4532         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4533                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4534                 if (!vfr)
4535                         return 0;
4536
4537                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4538                         return vfr->fw_fid;
4539
4540                 eth_dev = vfr->parent_dev;
4541         }
4542
4543         bp = eth_dev->data->dev_private;
4544
4545         return bp->fw_fid;
4546 }
4547
4548 enum bnxt_ulp_intf_type
4549 bnxt_get_interface_type(uint16_t port)
4550 {
4551         struct rte_eth_dev *eth_dev;
4552         struct bnxt *bp;
4553
4554         eth_dev = &rte_eth_devices[port];
4555         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4556                 return BNXT_ULP_INTF_TYPE_VF_REP;
4557
4558         bp = eth_dev->data->dev_private;
4559         if (BNXT_PF(bp))
4560                 return BNXT_ULP_INTF_TYPE_PF;
4561         else if (BNXT_VF_IS_TRUSTED(bp))
4562                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4563         else if (BNXT_VF(bp))
4564                 return BNXT_ULP_INTF_TYPE_VF;
4565
4566         return BNXT_ULP_INTF_TYPE_INVALID;
4567 }
4568
4569 uint16_t
4570 bnxt_get_phy_port_id(uint16_t port_id)
4571 {
4572         struct bnxt_representor *vfr;
4573         struct rte_eth_dev *eth_dev;
4574         struct bnxt *bp;
4575
4576         eth_dev = &rte_eth_devices[port_id];
4577         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4578                 vfr = eth_dev->data->dev_private;
4579                 if (!vfr)
4580                         return 0;
4581
4582                 eth_dev = vfr->parent_dev;
4583         }
4584
4585         bp = eth_dev->data->dev_private;
4586
4587         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4588 }
4589
4590 uint16_t
4591 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4592 {
4593         struct rte_eth_dev *eth_dev;
4594         struct bnxt *bp;
4595
4596         eth_dev = &rte_eth_devices[port_id];
4597         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4598                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4599                 if (!vfr)
4600                         return 0;
4601
4602                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4603                         return vfr->fw_fid - 1;
4604
4605                 eth_dev = vfr->parent_dev;
4606         }
4607
4608         bp = eth_dev->data->dev_private;
4609
4610         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4611 }
4612
4613 uint16_t
4614 bnxt_get_vport(uint16_t port_id)
4615 {
4616         return (1 << bnxt_get_phy_port_id(port_id));
4617 }
4618
4619 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4620 {
4621         struct bnxt_error_recovery_info *info = bp->recovery_info;
4622
4623         if (info) {
4624                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4625                         memset(info, 0, sizeof(*info));
4626                 return;
4627         }
4628
4629         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4630                 return;
4631
4632         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4633                            sizeof(*info), 0);
4634         if (!info)
4635                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4636
4637         bp->recovery_info = info;
4638 }
4639
4640 static void bnxt_check_fw_status(struct bnxt *bp)
4641 {
4642         uint32_t fw_status;
4643
4644         if (!(bp->recovery_info &&
4645               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4646                 return;
4647
4648         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4649         if (fw_status != BNXT_FW_STATUS_HEALTHY)
4650                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4651                             fw_status);
4652 }
4653
4654 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4655 {
4656         struct bnxt_error_recovery_info *info = bp->recovery_info;
4657         uint32_t status_loc;
4658         uint32_t sig_ver;
4659
4660         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4661                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4662         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4663                                    BNXT_GRCP_WINDOW_2_BASE +
4664                                    offsetof(struct hcomm_status,
4665                                             sig_ver)));
4666         /* If the signature is absent, then FW does not support this feature */
4667         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4668             HCOMM_STATUS_SIGNATURE_VAL)
4669                 return 0;
4670
4671         if (!info) {
4672                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4673                                    sizeof(*info), 0);
4674                 if (!info)
4675                         return -ENOMEM;
4676                 bp->recovery_info = info;
4677         } else {
4678                 memset(info, 0, sizeof(*info));
4679         }
4680
4681         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4682                                       BNXT_GRCP_WINDOW_2_BASE +
4683                                       offsetof(struct hcomm_status,
4684                                                fw_status_loc)));
4685
4686         /* Only pre-map the FW health status GRC register */
4687         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4688                 return 0;
4689
4690         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4691         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4692                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4693
4694         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4695                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4696
4697         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4698
4699         return 0;
4700 }
4701
4702 static int bnxt_init_fw(struct bnxt *bp)
4703 {
4704         uint16_t mtu;
4705         int rc = 0;
4706
4707         bp->fw_cap = 0;
4708
4709         rc = bnxt_map_hcomm_fw_status_reg(bp);
4710         if (rc)
4711                 return rc;
4712
4713         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4714         if (rc) {
4715                 bnxt_check_fw_status(bp);
4716                 return rc;
4717         }
4718
4719         rc = bnxt_hwrm_func_reset(bp);
4720         if (rc)
4721                 return -EIO;
4722
4723         rc = bnxt_hwrm_vnic_qcaps(bp);
4724         if (rc)
4725                 return rc;
4726
4727         rc = bnxt_hwrm_queue_qportcfg(bp);
4728         if (rc)
4729                 return rc;
4730
4731         /* Get the MAX capabilities for this function.
4732          * This function also allocates context memory for TQM rings and
4733          * informs the firmware about this allocated backing store memory.
4734          */
4735         rc = bnxt_hwrm_func_qcaps(bp);
4736         if (rc)
4737                 return rc;
4738
4739         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4740         if (rc)
4741                 return rc;
4742
4743         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4744         if (rc)
4745                 return rc;
4746
4747         bnxt_hwrm_port_mac_qcfg(bp);
4748
4749         bnxt_hwrm_parent_pf_qcfg(bp);
4750
4751         bnxt_hwrm_port_phy_qcaps(bp);
4752
4753         bnxt_alloc_error_recovery_info(bp);
4754         /* Get the adapter error recovery support info */
4755         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4756         if (rc)
4757                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4758
4759         bnxt_hwrm_port_led_qcaps(bp);
4760
4761         return 0;
4762 }
4763
4764 static int
4765 bnxt_init_locks(struct bnxt *bp)
4766 {
4767         int err;
4768
4769         err = pthread_mutex_init(&bp->flow_lock, NULL);
4770         if (err) {
4771                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4772                 return err;
4773         }
4774
4775         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4776         if (err) {
4777                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4778                 return err;
4779         }
4780
4781         err = pthread_mutex_init(&bp->health_check_lock, NULL);
4782         if (err)
4783                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4784         return err;
4785 }
4786
4787 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4788 {
4789         int rc = 0;
4790
4791         rc = bnxt_init_fw(bp);
4792         if (rc)
4793                 return rc;
4794
4795         if (!reconfig_dev) {
4796                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4797                 if (rc)
4798                         return rc;
4799         } else {
4800                 rc = bnxt_restore_dflt_mac(bp);
4801                 if (rc)
4802                         return rc;
4803         }
4804
4805         bnxt_config_vf_req_fwd(bp);
4806
4807         rc = bnxt_hwrm_func_driver_register(bp);
4808         if (rc) {
4809                 PMD_DRV_LOG(ERR, "Failed to register driver");
4810                 return -EBUSY;
4811         }
4812
4813         if (BNXT_PF(bp)) {
4814                 if (bp->pdev->max_vfs) {
4815                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4816                         if (rc) {
4817                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4818                                 return rc;
4819                         }
4820                 } else {
4821                         rc = bnxt_hwrm_allocate_pf_only(bp);
4822                         if (rc) {
4823                                 PMD_DRV_LOG(ERR,
4824                                             "Failed to allocate PF resources");
4825                                 return rc;
4826                         }
4827                 }
4828         }
4829
4830         rc = bnxt_alloc_mem(bp, reconfig_dev);
4831         if (rc)
4832                 return rc;
4833
4834         rc = bnxt_setup_int(bp);
4835         if (rc)
4836                 return rc;
4837
4838         rc = bnxt_request_int(bp);
4839         if (rc)
4840                 return rc;
4841
4842         rc = bnxt_init_ctx_mem(bp);
4843         if (rc) {
4844                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4845                 return rc;
4846         }
4847
4848         return 0;
4849 }
4850
4851 static int
4852 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4853                           const char *value, void *opaque_arg)
4854 {
4855         struct bnxt *bp = opaque_arg;
4856         unsigned long truflow;
4857         char *end = NULL;
4858
4859         if (!value || !opaque_arg) {
4860                 PMD_DRV_LOG(ERR,
4861                             "Invalid parameter passed to truflow devargs.\n");
4862                 return -EINVAL;
4863         }
4864
4865         truflow = strtoul(value, &end, 10);
4866         if (end == NULL || *end != '\0' ||
4867             (truflow == ULONG_MAX && errno == ERANGE)) {
4868                 PMD_DRV_LOG(ERR,
4869                             "Invalid parameter passed to truflow devargs.\n");
4870                 return -EINVAL;
4871         }
4872
4873         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4874                 PMD_DRV_LOG(ERR,
4875                             "Invalid value passed to truflow devargs.\n");
4876                 return -EINVAL;
4877         }
4878
4879         if (truflow) {
4880                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4881                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4882         } else {
4883                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4884                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4885         }
4886
4887         return 0;
4888 }
4889
4890 static int
4891 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4892                              const char *value, void *opaque_arg)
4893 {
4894         struct bnxt *bp = opaque_arg;
4895         unsigned long flow_xstat;
4896         char *end = NULL;
4897
4898         if (!value || !opaque_arg) {
4899                 PMD_DRV_LOG(ERR,
4900                             "Invalid parameter passed to flow_xstat devarg.\n");
4901                 return -EINVAL;
4902         }
4903
4904         flow_xstat = strtoul(value, &end, 10);
4905         if (end == NULL || *end != '\0' ||
4906             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4907                 PMD_DRV_LOG(ERR,
4908                             "Invalid parameter passed to flow_xstat devarg.\n");
4909                 return -EINVAL;
4910         }
4911
4912         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4913                 PMD_DRV_LOG(ERR,
4914                             "Invalid value passed to flow_xstat devarg.\n");
4915                 return -EINVAL;
4916         }
4917
4918         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4919         if (BNXT_FLOW_XSTATS_EN(bp))
4920                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4921
4922         return 0;
4923 }
4924
4925 static int
4926 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4927                                         const char *value, void *opaque_arg)
4928 {
4929         struct bnxt *bp = opaque_arg;
4930         unsigned long max_num_kflows;
4931         char *end = NULL;
4932
4933         if (!value || !opaque_arg) {
4934                 PMD_DRV_LOG(ERR,
4935                         "Invalid parameter passed to max_num_kflows devarg.\n");
4936                 return -EINVAL;
4937         }
4938
4939         max_num_kflows = strtoul(value, &end, 10);
4940         if (end == NULL || *end != '\0' ||
4941                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4942                 PMD_DRV_LOG(ERR,
4943                         "Invalid parameter passed to max_num_kflows devarg.\n");
4944                 return -EINVAL;
4945         }
4946
4947         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4948                 PMD_DRV_LOG(ERR,
4949                         "Invalid value passed to max_num_kflows devarg.\n");
4950                 return -EINVAL;
4951         }
4952
4953         bp->max_num_kflows = max_num_kflows;
4954         if (bp->max_num_kflows)
4955                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
4956                                 max_num_kflows);
4957
4958         return 0;
4959 }
4960
4961 static int
4962 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
4963                             const char *value, void *opaque_arg)
4964 {
4965         struct bnxt_representor *vfr_bp = opaque_arg;
4966         unsigned long rep_is_pf;
4967         char *end = NULL;
4968
4969         if (!value || !opaque_arg) {
4970                 PMD_DRV_LOG(ERR,
4971                             "Invalid parameter passed to rep_is_pf devargs.\n");
4972                 return -EINVAL;
4973         }
4974
4975         rep_is_pf = strtoul(value, &end, 10);
4976         if (end == NULL || *end != '\0' ||
4977             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
4978                 PMD_DRV_LOG(ERR,
4979                             "Invalid parameter passed to rep_is_pf devargs.\n");
4980                 return -EINVAL;
4981         }
4982
4983         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
4984                 PMD_DRV_LOG(ERR,
4985                             "Invalid value passed to rep_is_pf devargs.\n");
4986                 return -EINVAL;
4987         }
4988
4989         vfr_bp->flags |= rep_is_pf;
4990         if (BNXT_REP_PF(vfr_bp))
4991                 PMD_DRV_LOG(INFO, "PF representor\n");
4992         else
4993                 PMD_DRV_LOG(INFO, "VF representor\n");
4994
4995         return 0;
4996 }
4997
4998 static int
4999 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5000                                const char *value, void *opaque_arg)
5001 {
5002         struct bnxt_representor *vfr_bp = opaque_arg;
5003         unsigned long rep_based_pf;
5004         char *end = NULL;
5005
5006         if (!value || !opaque_arg) {
5007                 PMD_DRV_LOG(ERR,
5008                             "Invalid parameter passed to rep_based_pf "
5009                             "devargs.\n");
5010                 return -EINVAL;
5011         }
5012
5013         rep_based_pf = strtoul(value, &end, 10);
5014         if (end == NULL || *end != '\0' ||
5015             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5016                 PMD_DRV_LOG(ERR,
5017                             "Invalid parameter passed to rep_based_pf "
5018                             "devargs.\n");
5019                 return -EINVAL;
5020         }
5021
5022         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5023                 PMD_DRV_LOG(ERR,
5024                             "Invalid value passed to rep_based_pf devargs.\n");
5025                 return -EINVAL;
5026         }
5027
5028         vfr_bp->rep_based_pf = rep_based_pf;
5029         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5030
5031         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5032
5033         return 0;
5034 }
5035
5036 static int
5037 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5038                             const char *value, void *opaque_arg)
5039 {
5040         struct bnxt_representor *vfr_bp = opaque_arg;
5041         unsigned long rep_q_r2f;
5042         char *end = NULL;
5043
5044         if (!value || !opaque_arg) {
5045                 PMD_DRV_LOG(ERR,
5046                             "Invalid parameter passed to rep_q_r2f "
5047                             "devargs.\n");
5048                 return -EINVAL;
5049         }
5050
5051         rep_q_r2f = strtoul(value, &end, 10);
5052         if (end == NULL || *end != '\0' ||
5053             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5054                 PMD_DRV_LOG(ERR,
5055                             "Invalid parameter passed to rep_q_r2f "
5056                             "devargs.\n");
5057                 return -EINVAL;
5058         }
5059
5060         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5061                 PMD_DRV_LOG(ERR,
5062                             "Invalid value passed to rep_q_r2f devargs.\n");
5063                 return -EINVAL;
5064         }
5065
5066         vfr_bp->rep_q_r2f = rep_q_r2f;
5067         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5068         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5069
5070         return 0;
5071 }
5072
5073 static int
5074 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5075                             const char *value, void *opaque_arg)
5076 {
5077         struct bnxt_representor *vfr_bp = opaque_arg;
5078         unsigned long rep_q_f2r;
5079         char *end = NULL;
5080
5081         if (!value || !opaque_arg) {
5082                 PMD_DRV_LOG(ERR,
5083                             "Invalid parameter passed to rep_q_f2r "
5084                             "devargs.\n");
5085                 return -EINVAL;
5086         }
5087
5088         rep_q_f2r = strtoul(value, &end, 10);
5089         if (end == NULL || *end != '\0' ||
5090             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5091                 PMD_DRV_LOG(ERR,
5092                             "Invalid parameter passed to rep_q_f2r "
5093                             "devargs.\n");
5094                 return -EINVAL;
5095         }
5096
5097         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5098                 PMD_DRV_LOG(ERR,
5099                             "Invalid value passed to rep_q_f2r devargs.\n");
5100                 return -EINVAL;
5101         }
5102
5103         vfr_bp->rep_q_f2r = rep_q_f2r;
5104         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5105         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5106
5107         return 0;
5108 }
5109
5110 static int
5111 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5112                              const char *value, void *opaque_arg)
5113 {
5114         struct bnxt_representor *vfr_bp = opaque_arg;
5115         unsigned long rep_fc_r2f;
5116         char *end = NULL;
5117
5118         if (!value || !opaque_arg) {
5119                 PMD_DRV_LOG(ERR,
5120                             "Invalid parameter passed to rep_fc_r2f "
5121                             "devargs.\n");
5122                 return -EINVAL;
5123         }
5124
5125         rep_fc_r2f = strtoul(value, &end, 10);
5126         if (end == NULL || *end != '\0' ||
5127             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5128                 PMD_DRV_LOG(ERR,
5129                             "Invalid parameter passed to rep_fc_r2f "
5130                             "devargs.\n");
5131                 return -EINVAL;
5132         }
5133
5134         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5135                 PMD_DRV_LOG(ERR,
5136                             "Invalid value passed to rep_fc_r2f devargs.\n");
5137                 return -EINVAL;
5138         }
5139
5140         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5141         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5142         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5143
5144         return 0;
5145 }
5146
5147 static int
5148 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5149                              const char *value, void *opaque_arg)
5150 {
5151         struct bnxt_representor *vfr_bp = opaque_arg;
5152         unsigned long rep_fc_f2r;
5153         char *end = NULL;
5154
5155         if (!value || !opaque_arg) {
5156                 PMD_DRV_LOG(ERR,
5157                             "Invalid parameter passed to rep_fc_f2r "
5158                             "devargs.\n");
5159                 return -EINVAL;
5160         }
5161
5162         rep_fc_f2r = strtoul(value, &end, 10);
5163         if (end == NULL || *end != '\0' ||
5164             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5165                 PMD_DRV_LOG(ERR,
5166                             "Invalid parameter passed to rep_fc_f2r "
5167                             "devargs.\n");
5168                 return -EINVAL;
5169         }
5170
5171         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5172                 PMD_DRV_LOG(ERR,
5173                             "Invalid value passed to rep_fc_f2r devargs.\n");
5174                 return -EINVAL;
5175         }
5176
5177         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5178         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5179         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5180
5181         return 0;
5182 }
5183
5184 static void
5185 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5186 {
5187         struct rte_kvargs *kvlist;
5188
5189         if (devargs == NULL)
5190                 return;
5191
5192         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5193         if (kvlist == NULL)
5194                 return;
5195
5196         /*
5197          * Handler for "truflow" devarg.
5198          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5199          */
5200         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5201                            bnxt_parse_devarg_truflow, bp);
5202
5203         /*
5204          * Handler for "flow_xstat" devarg.
5205          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5206          */
5207         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5208                            bnxt_parse_devarg_flow_xstat, bp);
5209
5210         /*
5211          * Handler for "max_num_kflows" devarg.
5212          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5213          */
5214         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5215                            bnxt_parse_devarg_max_num_kflows, bp);
5216
5217         rte_kvargs_free(kvlist);
5218 }
5219
5220 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5221 {
5222         int rc = 0;
5223
5224         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5225                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5226                 if (rc)
5227                         PMD_DRV_LOG(ERR,
5228                                     "Failed to alloc switch domain: %d\n", rc);
5229                 else
5230                         PMD_DRV_LOG(INFO,
5231                                     "Switch domain allocated %d\n",
5232                                     bp->switch_domain_id);
5233         }
5234
5235         return rc;
5236 }
5237
5238 static int
5239 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5240 {
5241         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5242         static int version_printed;
5243         struct bnxt *bp;
5244         int rc;
5245
5246         if (version_printed++ == 0)
5247                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5248
5249         eth_dev->dev_ops = &bnxt_dev_ops;
5250         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5251         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5252         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5253         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5254         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5255
5256         /*
5257          * For secondary processes, we don't initialise any further
5258          * as primary has already done this work.
5259          */
5260         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5261                 return 0;
5262
5263         rte_eth_copy_pci_info(eth_dev, pci_dev);
5264         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5265
5266         bp = eth_dev->data->dev_private;
5267
5268         /* Parse dev arguments passed on when starting the DPDK application. */
5269         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5270
5271         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5272
5273         if (bnxt_vf_pciid(pci_dev->id.device_id))
5274                 bp->flags |= BNXT_FLAG_VF;
5275
5276         if (bnxt_p5_device(pci_dev->id.device_id))
5277                 bp->flags |= BNXT_FLAG_CHIP_P5;
5278
5279         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5280             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5281             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5282             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5283                 bp->flags |= BNXT_FLAG_STINGRAY;
5284
5285         if (BNXT_TRUFLOW_EN(bp)) {
5286                 /* extra mbuf field is required to store CFA code from mark */
5287                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5288                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5289                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5290                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5291                 };
5292                 bnxt_cfa_code_dynfield_offset =
5293                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5294                 if (bnxt_cfa_code_dynfield_offset < 0) {
5295                         PMD_DRV_LOG(ERR,
5296                             "Failed to register mbuf field for TruFlow mark\n");
5297                         return -rte_errno;
5298                 }
5299         }
5300
5301         rc = bnxt_init_board(eth_dev);
5302         if (rc) {
5303                 PMD_DRV_LOG(ERR,
5304                             "Failed to initialize board rc: %x\n", rc);
5305                 return rc;
5306         }
5307
5308         rc = bnxt_alloc_pf_info(bp);
5309         if (rc)
5310                 goto error_free;
5311
5312         rc = bnxt_alloc_link_info(bp);
5313         if (rc)
5314                 goto error_free;
5315
5316         rc = bnxt_alloc_parent_info(bp);
5317         if (rc)
5318                 goto error_free;
5319
5320         rc = bnxt_alloc_hwrm_resources(bp);
5321         if (rc) {
5322                 PMD_DRV_LOG(ERR,
5323                             "Failed to allocate hwrm resource rc: %x\n", rc);
5324                 goto error_free;
5325         }
5326         rc = bnxt_alloc_leds_info(bp);
5327         if (rc)
5328                 goto error_free;
5329
5330         rc = bnxt_alloc_cos_queues(bp);
5331         if (rc)
5332                 goto error_free;
5333
5334         rc = bnxt_init_locks(bp);
5335         if (rc)
5336                 goto error_free;
5337
5338         rc = bnxt_init_resources(bp, false);
5339         if (rc)
5340                 goto error_free;
5341
5342         rc = bnxt_alloc_stats_mem(bp);
5343         if (rc)
5344                 goto error_free;
5345
5346         bnxt_alloc_switch_domain(bp);
5347
5348         PMD_DRV_LOG(INFO,
5349                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5350                     pci_dev->mem_resource[0].phys_addr,
5351                     pci_dev->mem_resource[0].addr);
5352
5353         return 0;
5354
5355 error_free:
5356         bnxt_dev_uninit(eth_dev);
5357         return rc;
5358 }
5359
5360
5361 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5362 {
5363         if (!ctx)
5364                 return;
5365
5366         if (ctx->va)
5367                 rte_free(ctx->va);
5368
5369         ctx->va = NULL;
5370         ctx->dma = RTE_BAD_IOVA;
5371         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5372 }
5373
5374 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5375 {
5376         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5377                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5378                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5379                                   bp->flow_stat->max_fc,
5380                                   false);
5381
5382         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5383                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5384                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5385                                   bp->flow_stat->max_fc,
5386                                   false);
5387
5388         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5389                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5390         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5391
5392         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5393                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5394         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5395
5396         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5397                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5398         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5399
5400         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5401                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5402         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5403 }
5404
5405 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5406 {
5407         bnxt_unregister_fc_ctx_mem(bp);
5408
5409         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5410         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5411         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5412         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5413 }
5414
5415 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5416 {
5417         if (BNXT_FLOW_XSTATS_EN(bp))
5418                 bnxt_uninit_fc_ctx_mem(bp);
5419 }
5420
5421 static void
5422 bnxt_free_error_recovery_info(struct bnxt *bp)
5423 {
5424         rte_free(bp->recovery_info);
5425         bp->recovery_info = NULL;
5426         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5427 }
5428
5429 static int
5430 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5431 {
5432         int rc;
5433
5434         bnxt_free_int(bp);
5435         bnxt_free_mem(bp, reconfig_dev);
5436
5437         bnxt_hwrm_func_buf_unrgtr(bp);
5438         rte_free(bp->pf->vf_req_buf);
5439
5440         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5441         bp->flags &= ~BNXT_FLAG_REGISTERED;
5442         bnxt_free_ctx_mem(bp);
5443         if (!reconfig_dev) {
5444                 bnxt_free_hwrm_resources(bp);
5445                 bnxt_free_error_recovery_info(bp);
5446         }
5447
5448         bnxt_uninit_ctx_mem(bp);
5449
5450         bnxt_free_flow_stats_info(bp);
5451         bnxt_free_rep_info(bp);
5452         rte_free(bp->ptp_cfg);
5453         bp->ptp_cfg = NULL;
5454         return rc;
5455 }
5456
5457 static int
5458 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5459 {
5460         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5461                 return -EPERM;
5462
5463         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5464
5465         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5466                 bnxt_dev_close_op(eth_dev);
5467
5468         return 0;
5469 }
5470
5471 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5472 {
5473         struct bnxt *bp = eth_dev->data->dev_private;
5474         struct rte_eth_dev *vf_rep_eth_dev;
5475         int ret = 0, i;
5476
5477         if (!bp)
5478                 return -EINVAL;
5479
5480         for (i = 0; i < bp->num_reps; i++) {
5481                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5482                 if (!vf_rep_eth_dev)
5483                         continue;
5484                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5485                             vf_rep_eth_dev->data->port_id);
5486                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5487         }
5488         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5489                     eth_dev->data->port_id);
5490         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5491
5492         return ret;
5493 }
5494
5495 static void bnxt_free_rep_info(struct bnxt *bp)
5496 {
5497         rte_free(bp->rep_info);
5498         bp->rep_info = NULL;
5499         rte_free(bp->cfa_code_map);
5500         bp->cfa_code_map = NULL;
5501 }
5502
5503 static int bnxt_init_rep_info(struct bnxt *bp)
5504 {
5505         int i = 0, rc;
5506
5507         if (bp->rep_info)
5508                 return 0;
5509
5510         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5511                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5512                                    0);
5513         if (!bp->rep_info) {
5514                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5515                 return -ENOMEM;
5516         }
5517         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5518                                        sizeof(*bp->cfa_code_map) *
5519                                        BNXT_MAX_CFA_CODE, 0);
5520         if (!bp->cfa_code_map) {
5521                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5522                 bnxt_free_rep_info(bp);
5523                 return -ENOMEM;
5524         }
5525
5526         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5527                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5528
5529         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5530         if (rc) {
5531                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5532                 bnxt_free_rep_info(bp);
5533                 return rc;
5534         }
5535
5536         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5537         if (rc) {
5538                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5539                 bnxt_free_rep_info(bp);
5540                 return rc;
5541         }
5542
5543         return rc;
5544 }
5545
5546 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5547                                struct rte_eth_devargs *eth_da,
5548                                struct rte_eth_dev *backing_eth_dev,
5549                                const char *dev_args)
5550 {
5551         struct rte_eth_dev *vf_rep_eth_dev;
5552         char name[RTE_ETH_NAME_MAX_LEN];
5553         struct bnxt *backing_bp;
5554         uint16_t num_rep;
5555         int i, ret = 0;
5556         struct rte_kvargs *kvlist = NULL;
5557
5558         num_rep = eth_da->nb_representor_ports;
5559         if (num_rep > BNXT_MAX_VF_REPS) {
5560                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5561                             num_rep, BNXT_MAX_VF_REPS);
5562                 return -EINVAL;
5563         }
5564
5565         if (num_rep >= RTE_MAX_ETHPORTS) {
5566                 PMD_DRV_LOG(ERR,
5567                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5568                             num_rep, RTE_MAX_ETHPORTS);
5569                 return -EINVAL;
5570         }
5571
5572         backing_bp = backing_eth_dev->data->dev_private;
5573
5574         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5575                 PMD_DRV_LOG(ERR,
5576                             "Not a PF or trusted VF. No Representor support\n");
5577                 /* Returning an error is not an option.
5578                  * Applications are not handling this correctly
5579                  */
5580                 return 0;
5581         }
5582
5583         if (bnxt_init_rep_info(backing_bp))
5584                 return 0;
5585
5586         for (i = 0; i < num_rep; i++) {
5587                 struct bnxt_representor representor = {
5588                         .vf_id = eth_da->representor_ports[i],
5589                         .switch_domain_id = backing_bp->switch_domain_id,
5590                         .parent_dev = backing_eth_dev
5591                 };
5592
5593                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5594                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5595                                     representor.vf_id, BNXT_MAX_VF_REPS);
5596                         continue;
5597                 }
5598
5599                 /* representor port net_bdf_port */
5600                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5601                          pci_dev->device.name, eth_da->representor_ports[i]);
5602
5603                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5604                 if (kvlist) {
5605                         /*
5606                          * Handler for "rep_is_pf" devarg.
5607                          * Invoked as for ex: "-a 000:00:0d.0,
5608                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5609                          */
5610                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5611                                                  bnxt_parse_devarg_rep_is_pf,
5612                                                  (void *)&representor);
5613                         if (ret) {
5614                                 ret = -EINVAL;
5615                                 goto err;
5616                         }
5617                         /*
5618                          * Handler for "rep_based_pf" devarg.
5619                          * Invoked as for ex: "-a 000:00:0d.0,
5620                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5621                          */
5622                         ret = rte_kvargs_process(kvlist,
5623                                                  BNXT_DEVARG_REP_BASED_PF,
5624                                                  bnxt_parse_devarg_rep_based_pf,
5625                                                  (void *)&representor);
5626                         if (ret) {
5627                                 ret = -EINVAL;
5628                                 goto err;
5629                         }
5630                         /*
5631                          * Handler for "rep_based_pf" devarg.
5632                          * Invoked as for ex: "-a 000:00:0d.0,
5633                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5634                          */
5635                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5636                                                  bnxt_parse_devarg_rep_q_r2f,
5637                                                  (void *)&representor);
5638                         if (ret) {
5639                                 ret = -EINVAL;
5640                                 goto err;
5641                         }
5642                         /*
5643                          * Handler for "rep_based_pf" devarg.
5644                          * Invoked as for ex: "-a 000:00:0d.0,
5645                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5646                          */
5647                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5648                                                  bnxt_parse_devarg_rep_q_f2r,
5649                                                  (void *)&representor);
5650                         if (ret) {
5651                                 ret = -EINVAL;
5652                                 goto err;
5653                         }
5654                         /*
5655                          * Handler for "rep_based_pf" devarg.
5656                          * Invoked as for ex: "-a 000:00:0d.0,
5657                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5658                          */
5659                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5660                                                  bnxt_parse_devarg_rep_fc_r2f,
5661                                                  (void *)&representor);
5662                         if (ret) {
5663                                 ret = -EINVAL;
5664                                 goto err;
5665                         }
5666                         /*
5667                          * Handler for "rep_based_pf" devarg.
5668                          * Invoked as for ex: "-a 000:00:0d.0,
5669                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5670                          */
5671                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5672                                                  bnxt_parse_devarg_rep_fc_f2r,
5673                                                  (void *)&representor);
5674                         if (ret) {
5675                                 ret = -EINVAL;
5676                                 goto err;
5677                         }
5678                 }
5679
5680                 ret = rte_eth_dev_create(&pci_dev->device, name,
5681                                          sizeof(struct bnxt_representor),
5682                                          NULL, NULL,
5683                                          bnxt_representor_init,
5684                                          &representor);
5685                 if (ret) {
5686                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5687                                     "representor %s.", name);
5688                         goto err;
5689                 }
5690
5691                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5692                 if (!vf_rep_eth_dev) {
5693                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5694                                     " for VF-Rep: %s.", name);
5695                         ret = -ENODEV;
5696                         goto err;
5697                 }
5698
5699                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5700                             backing_eth_dev->data->port_id);
5701                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5702                                                          vf_rep_eth_dev;
5703                 backing_bp->num_reps++;
5704
5705         }
5706
5707         rte_kvargs_free(kvlist);
5708         return 0;
5709
5710 err:
5711         /* If num_rep > 1, then rollback already created
5712          * ports, since we'll be failing the probe anyway
5713          */
5714         if (num_rep > 1)
5715                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5716         rte_errno = -ret;
5717         rte_kvargs_free(kvlist);
5718
5719         return ret;
5720 }
5721
5722 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5723                           struct rte_pci_device *pci_dev)
5724 {
5725         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5726         struct rte_eth_dev *backing_eth_dev;
5727         uint16_t num_rep;
5728         int ret = 0;
5729
5730         if (pci_dev->device.devargs) {
5731                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5732                                             &eth_da);
5733                 if (ret)
5734                         return ret;
5735         }
5736
5737         num_rep = eth_da.nb_representor_ports;
5738         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5739                     num_rep);
5740
5741         /* We could come here after first level of probe is already invoked
5742          * as part of an application bringup(OVS-DPDK vswitchd), so first check
5743          * for already allocated eth_dev for the backing device (PF/Trusted VF)
5744          */
5745         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5746         if (backing_eth_dev == NULL) {
5747                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5748                                          sizeof(struct bnxt),
5749                                          eth_dev_pci_specific_init, pci_dev,
5750                                          bnxt_dev_init, NULL);
5751
5752                 if (ret || !num_rep)
5753                         return ret;
5754
5755                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5756         }
5757         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5758                     backing_eth_dev->data->port_id);
5759
5760         if (!num_rep)
5761                 return ret;
5762
5763         /* probe representor ports now */
5764         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
5765                                   pci_dev->device.devargs->args);
5766
5767         return ret;
5768 }
5769
5770 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5771 {
5772         struct rte_eth_dev *eth_dev;
5773
5774         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5775         if (!eth_dev)
5776                 return 0; /* Invoked typically only by OVS-DPDK, by the
5777                            * time it comes here the eth_dev is already
5778                            * deleted by rte_eth_dev_close(), so returning
5779                            * +ve value will at least help in proper cleanup
5780                            */
5781
5782         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5783         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5784                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5785                         return rte_eth_dev_destroy(eth_dev,
5786                                                    bnxt_representor_uninit);
5787                 else
5788                         return rte_eth_dev_destroy(eth_dev,
5789                                                    bnxt_dev_uninit);
5790         } else {
5791                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5792         }
5793 }
5794
5795 static struct rte_pci_driver bnxt_rte_pmd = {
5796         .id_table = bnxt_pci_id_map,
5797         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5798                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5799                                                   * and OVS-DPDK
5800                                                   */
5801         .probe = bnxt_pci_probe,
5802         .remove = bnxt_pci_remove,
5803 };
5804
5805 static bool
5806 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5807 {
5808         if (strcmp(dev->device->driver->name, drv->driver.name))
5809                 return false;
5810
5811         return true;
5812 }
5813
5814 bool is_bnxt_supported(struct rte_eth_dev *dev)
5815 {
5816         return is_device_supported(dev, &bnxt_rte_pmd);
5817 }
5818
5819 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5820 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5821 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5822 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");