1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
91 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
92 #define BNXT_DEVARG_REPRESENTOR "representor"
93 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
94 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
95 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
96 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
97 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
98 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
100 static const char *const bnxt_dev_args[] = {
101 BNXT_DEVARG_REPRESENTOR,
102 BNXT_DEVARG_FLOW_XSTAT,
103 BNXT_DEVARG_MAX_NUM_KFLOWS,
104 BNXT_DEVARG_REP_BASED_PF,
105 BNXT_DEVARG_REP_IS_PF,
106 BNXT_DEVARG_REP_Q_R2F,
107 BNXT_DEVARG_REP_Q_F2R,
108 BNXT_DEVARG_REP_FC_R2F,
109 BNXT_DEVARG_REP_FC_F2R,
114 * flow_xstat == false to disable the feature
115 * flow_xstat == true to enable the feature
117 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
120 * rep_is_pf == false to indicate VF representor
121 * rep_is_pf == true to indicate PF representor
123 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
126 * rep_based_pf == Physical index of the PF
128 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
130 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
132 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
135 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
137 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
140 * rep_fc_r2f == Flow control for the representor to endpoint direction
142 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
145 * rep_fc_f2r == Flow control for the endpoint to representor direction
147 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
149 int bnxt_cfa_code_dynfield_offset = -1;
152 * max_num_kflows must be >= 32
153 * and must be a power-of-2 supported value
154 * return: 1 -> invalid
157 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
159 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
164 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
165 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
166 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
167 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
168 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
169 static int bnxt_restore_vlan_filters(struct bnxt *bp);
170 static void bnxt_dev_recover(void *arg);
171 static void bnxt_free_error_recovery_info(struct bnxt *bp);
172 static void bnxt_free_rep_info(struct bnxt *bp);
174 int is_bnxt_in_error(struct bnxt *bp)
176 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
178 if (bp->flags & BNXT_FLAG_FW_RESET)
184 /***********************/
187 * High level utility functions
190 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
192 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
193 BNXT_RSS_TBL_SIZE_P5);
195 if (!BNXT_CHIP_P5(bp))
198 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
199 BNXT_RSS_ENTRIES_PER_CTX_P5) /
200 BNXT_RSS_ENTRIES_PER_CTX_P5;
203 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
205 if (!BNXT_CHIP_P5(bp))
206 return HW_HASH_INDEX_SIZE;
208 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
211 static void bnxt_free_parent_info(struct bnxt *bp)
213 rte_free(bp->parent);
217 static void bnxt_free_pf_info(struct bnxt *bp)
223 static void bnxt_free_link_info(struct bnxt *bp)
225 rte_free(bp->link_info);
226 bp->link_info = NULL;
229 static void bnxt_free_leds_info(struct bnxt *bp)
238 static void bnxt_free_flow_stats_info(struct bnxt *bp)
240 rte_free(bp->flow_stat);
241 bp->flow_stat = NULL;
244 static void bnxt_free_cos_queues(struct bnxt *bp)
246 rte_free(bp->rx_cos_queue);
247 bp->rx_cos_queue = NULL;
248 rte_free(bp->tx_cos_queue);
249 bp->tx_cos_queue = NULL;
252 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
254 bnxt_free_filter_mem(bp);
255 bnxt_free_vnic_attributes(bp);
256 bnxt_free_vnic_mem(bp);
258 /* tx/rx rings are configured as part of *_queue_setup callbacks.
259 * If the number of rings change across fw update,
260 * we don't have much choice except to warn the user.
264 bnxt_free_tx_rings(bp);
265 bnxt_free_rx_rings(bp);
267 bnxt_free_async_cp_ring(bp);
268 bnxt_free_rxtx_nq_ring(bp);
270 rte_free(bp->grp_info);
274 static int bnxt_alloc_parent_info(struct bnxt *bp)
276 bp->parent = rte_zmalloc("bnxt_parent_info",
277 sizeof(struct bnxt_parent_info), 0);
278 if (bp->parent == NULL)
284 static int bnxt_alloc_pf_info(struct bnxt *bp)
286 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
293 static int bnxt_alloc_link_info(struct bnxt *bp)
296 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
297 if (bp->link_info == NULL)
303 static int bnxt_alloc_leds_info(struct bnxt *bp)
308 bp->leds = rte_zmalloc("bnxt_leds",
309 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
311 if (bp->leds == NULL)
317 static int bnxt_alloc_cos_queues(struct bnxt *bp)
320 rte_zmalloc("bnxt_rx_cosq",
321 BNXT_COS_QUEUE_COUNT *
322 sizeof(struct bnxt_cos_queue_info),
324 if (bp->rx_cos_queue == NULL)
328 rte_zmalloc("bnxt_tx_cosq",
329 BNXT_COS_QUEUE_COUNT *
330 sizeof(struct bnxt_cos_queue_info),
332 if (bp->tx_cos_queue == NULL)
338 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
340 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
341 sizeof(struct bnxt_flow_stat_info), 0);
342 if (bp->flow_stat == NULL)
348 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
352 rc = bnxt_alloc_ring_grps(bp);
356 rc = bnxt_alloc_async_ring_struct(bp);
360 rc = bnxt_alloc_vnic_mem(bp);
364 rc = bnxt_alloc_vnic_attributes(bp);
368 rc = bnxt_alloc_filter_mem(bp);
372 rc = bnxt_alloc_async_cp_ring(bp);
376 rc = bnxt_alloc_rxtx_nq_ring(bp);
380 if (BNXT_FLOW_XSTATS_EN(bp)) {
381 rc = bnxt_alloc_flow_stats_info(bp);
389 bnxt_free_mem(bp, reconfig);
393 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
395 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
396 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
397 uint64_t rx_offloads = dev_conf->rxmode.offloads;
398 struct bnxt_rx_queue *rxq;
402 rc = bnxt_vnic_grp_alloc(bp, vnic);
406 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
407 vnic_id, vnic, vnic->fw_grp_ids);
409 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
413 /* Alloc RSS context only if RSS mode is enabled */
414 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
415 int j, nr_ctxs = bnxt_rss_ctxts(bp);
417 /* RSS table size in Thor is 512.
418 * Cap max Rx rings to same value
420 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
421 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
422 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
427 for (j = 0; j < nr_ctxs; j++) {
428 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
434 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
438 vnic->num_lb_ctxts = nr_ctxs;
442 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
443 * setting is not available at this time, it will not be
444 * configured correctly in the CFA.
446 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
447 vnic->vlan_strip = true;
449 vnic->vlan_strip = false;
451 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
455 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
459 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
460 rxq = bp->eth_dev->data->rx_queues[j];
463 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
464 j, rxq->vnic, rxq->vnic->fw_grp_ids);
466 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
467 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
469 vnic->rx_queue_cnt++;
472 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
474 rc = bnxt_vnic_rss_configure(bp, vnic);
478 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
480 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
481 (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
488 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
493 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
497 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
498 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
503 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
504 " rx_fc_in_tbl.ctx_id = %d\n",
505 bp->flow_stat->rx_fc_in_tbl.va,
506 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
507 bp->flow_stat->rx_fc_in_tbl.ctx_id);
509 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
510 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
515 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
516 " rx_fc_out_tbl.ctx_id = %d\n",
517 bp->flow_stat->rx_fc_out_tbl.va,
518 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
519 bp->flow_stat->rx_fc_out_tbl.ctx_id);
521 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
522 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
527 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
528 " tx_fc_in_tbl.ctx_id = %d\n",
529 bp->flow_stat->tx_fc_in_tbl.va,
530 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
531 bp->flow_stat->tx_fc_in_tbl.ctx_id);
533 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
534 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
539 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
540 " tx_fc_out_tbl.ctx_id = %d\n",
541 bp->flow_stat->tx_fc_out_tbl.va,
542 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
543 bp->flow_stat->tx_fc_out_tbl.ctx_id);
545 memset(bp->flow_stat->rx_fc_out_tbl.va,
547 bp->flow_stat->rx_fc_out_tbl.size);
548 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
549 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
550 bp->flow_stat->rx_fc_out_tbl.ctx_id,
551 bp->flow_stat->max_fc,
556 memset(bp->flow_stat->tx_fc_out_tbl.va,
558 bp->flow_stat->tx_fc_out_tbl.size);
559 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
560 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
561 bp->flow_stat->tx_fc_out_tbl.ctx_id,
562 bp->flow_stat->max_fc,
568 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
569 struct bnxt_ctx_mem_buf_info *ctx)
574 ctx->va = rte_zmalloc(type, size, 0);
577 rte_mem_lock_page(ctx->va);
579 ctx->dma = rte_mem_virt2iova(ctx->va);
580 if (ctx->dma == RTE_BAD_IOVA)
586 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
588 struct rte_pci_device *pdev = bp->pdev;
589 char type[RTE_MEMZONE_NAMESIZE];
593 max_fc = bp->flow_stat->max_fc;
595 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
596 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
597 /* 4 bytes for each counter-id */
598 rc = bnxt_alloc_ctx_mem_buf(type,
600 &bp->flow_stat->rx_fc_in_tbl);
604 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
605 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
606 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
607 rc = bnxt_alloc_ctx_mem_buf(type,
609 &bp->flow_stat->rx_fc_out_tbl);
613 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
614 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
615 /* 4 bytes for each counter-id */
616 rc = bnxt_alloc_ctx_mem_buf(type,
618 &bp->flow_stat->tx_fc_in_tbl);
622 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
623 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
624 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
625 rc = bnxt_alloc_ctx_mem_buf(type,
627 &bp->flow_stat->tx_fc_out_tbl);
631 rc = bnxt_register_fc_ctx_mem(bp);
636 static int bnxt_init_ctx_mem(struct bnxt *bp)
640 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
641 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
642 !BNXT_FLOW_XSTATS_EN(bp))
645 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
649 rc = bnxt_init_fc_ctx_mem(bp);
654 static int bnxt_update_phy_setting(struct bnxt *bp)
656 struct rte_eth_link new;
659 rc = bnxt_get_hwrm_link_config(bp, &new);
661 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
666 * On BCM957508-N2100 adapters, FW will not allow any user other
667 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
668 * always returns link up. Force phy update always in that case.
670 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
671 rc = bnxt_set_hwrm_link_config(bp, true);
673 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
681 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
683 rte_free(bp->prev_rx_ring_stats);
684 rte_free(bp->prev_tx_ring_stats);
686 bp->prev_rx_ring_stats = NULL;
687 bp->prev_tx_ring_stats = NULL;
690 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
692 bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats",
693 sizeof(struct bnxt_ring_stats) *
696 if (bp->prev_rx_ring_stats == NULL)
699 bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
700 sizeof(struct bnxt_ring_stats) *
703 if (bp->prev_tx_ring_stats == NULL)
709 bnxt_free_prev_ring_stats(bp);
713 static int bnxt_start_nic(struct bnxt *bp)
715 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
716 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
717 uint32_t intr_vector = 0;
718 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
719 uint32_t vec = BNXT_MISC_VEC_ID;
723 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
724 bp->eth_dev->data->dev_conf.rxmode.offloads |=
725 DEV_RX_OFFLOAD_JUMBO_FRAME;
726 bp->flags |= BNXT_FLAG_JUMBO;
728 bp->eth_dev->data->dev_conf.rxmode.offloads &=
729 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
730 bp->flags &= ~BNXT_FLAG_JUMBO;
733 /* THOR does not support ring groups.
734 * But we will use the array to save RSS context IDs.
736 if (BNXT_CHIP_P5(bp))
737 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
739 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
741 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
745 rc = bnxt_alloc_hwrm_rings(bp);
747 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
751 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
753 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
757 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
760 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
761 if (bp->rx_cos_queue[i].id != 0xff) {
762 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
766 "Num pools more than FW profile\n");
770 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
776 rc = bnxt_mq_rx_configure(bp);
778 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
783 rc = bnxt_setup_one_vnic(bp, 0);
786 /* VNIC configuration */
787 if (BNXT_RFS_NEEDS_VNIC(bp)) {
788 for (i = 1; i < bp->nr_vnics; i++) {
789 rc = bnxt_setup_one_vnic(bp, i);
795 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
798 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
802 /* check and configure queue intr-vector mapping */
803 if ((rte_intr_cap_multiple(intr_handle) ||
804 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
805 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
806 intr_vector = bp->eth_dev->data->nb_rx_queues;
807 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
808 if (intr_vector > bp->rx_cp_nr_rings) {
809 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
813 rc = rte_intr_efd_enable(intr_handle, intr_vector);
818 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
819 intr_handle->intr_vec =
820 rte_zmalloc("intr_vec",
821 bp->eth_dev->data->nb_rx_queues *
823 if (intr_handle->intr_vec == NULL) {
824 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
825 " intr_vec", bp->eth_dev->data->nb_rx_queues);
829 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
830 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
831 intr_handle->intr_vec, intr_handle->nb_efd,
832 intr_handle->max_intr);
833 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
835 intr_handle->intr_vec[queue_id] =
836 vec + BNXT_RX_VEC_START;
837 if (vec < base + intr_handle->nb_efd - 1)
842 /* enable uio/vfio intr/eventfd mapping */
843 rc = rte_intr_enable(intr_handle);
844 #ifndef RTE_EXEC_ENV_FREEBSD
845 /* In FreeBSD OS, nic_uio driver does not support interrupts */
850 rc = bnxt_update_phy_setting(bp);
854 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
856 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
861 /* Some of the error status returned by FW may not be from errno.h */
868 static int bnxt_shutdown_nic(struct bnxt *bp)
870 bnxt_free_all_hwrm_resources(bp);
871 bnxt_free_all_filters(bp);
872 bnxt_free_all_vnics(bp);
877 * Device configuration and status function
880 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
882 uint32_t link_speed = 0;
883 uint32_t speed_capa = 0;
885 if (bp->link_info == NULL)
888 link_speed = bp->link_info->support_speeds;
890 /* If PAM4 is configured, use PAM4 supported speed */
891 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
892 link_speed = bp->link_info->support_pam4_speeds;
894 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
895 speed_capa |= ETH_LINK_SPEED_100M;
896 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
897 speed_capa |= ETH_LINK_SPEED_100M_HD;
898 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
899 speed_capa |= ETH_LINK_SPEED_1G;
900 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
901 speed_capa |= ETH_LINK_SPEED_2_5G;
902 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
903 speed_capa |= ETH_LINK_SPEED_10G;
904 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
905 speed_capa |= ETH_LINK_SPEED_20G;
906 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
907 speed_capa |= ETH_LINK_SPEED_25G;
908 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
909 speed_capa |= ETH_LINK_SPEED_40G;
910 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
911 speed_capa |= ETH_LINK_SPEED_50G;
912 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
913 speed_capa |= ETH_LINK_SPEED_100G;
914 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
915 speed_capa |= ETH_LINK_SPEED_50G;
916 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
917 speed_capa |= ETH_LINK_SPEED_100G;
918 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
919 speed_capa |= ETH_LINK_SPEED_200G;
921 if (bp->link_info->auto_mode ==
922 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
923 speed_capa |= ETH_LINK_SPEED_FIXED;
928 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
929 struct rte_eth_dev_info *dev_info)
931 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
932 struct bnxt *bp = eth_dev->data->dev_private;
933 uint16_t max_vnics, i, j, vpool, vrxq;
934 unsigned int max_rx_rings;
937 rc = is_bnxt_in_error(bp);
942 dev_info->max_mac_addrs = bp->max_l2_ctx;
943 dev_info->max_hash_mac_addrs = 0;
945 /* PF/VF specifics */
947 dev_info->max_vfs = pdev->max_vfs;
949 max_rx_rings = bnxt_max_rings(bp);
950 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
951 dev_info->max_rx_queues = max_rx_rings;
952 dev_info->max_tx_queues = max_rx_rings;
953 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
954 dev_info->hash_key_size = 40;
955 max_vnics = bp->max_vnics;
958 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
959 dev_info->max_mtu = BNXT_MAX_MTU;
961 /* Fast path specifics */
962 dev_info->min_rx_bufsize = 1;
963 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
965 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
966 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
967 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
968 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
969 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
970 dev_info->tx_queue_offload_capa;
971 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
973 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
975 dev_info->default_rxconf = (struct rte_eth_rxconf) {
981 .rx_free_thresh = 32,
982 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
985 dev_info->default_txconf = (struct rte_eth_txconf) {
991 .tx_free_thresh = 32,
994 eth_dev->data->dev_conf.intr_conf.lsc = 1;
996 eth_dev->data->dev_conf.intr_conf.rxq = 1;
997 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
998 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
999 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1000 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1002 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1003 dev_info->switch_info.name = eth_dev->device->name;
1004 dev_info->switch_info.domain_id = bp->switch_domain_id;
1005 dev_info->switch_info.port_id =
1006 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1007 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1011 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1012 * need further investigation.
1015 /* VMDq resources */
1016 vpool = 64; /* ETH_64_POOLS */
1017 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1018 for (i = 0; i < 4; vpool >>= 1, i++) {
1019 if (max_vnics > vpool) {
1020 for (j = 0; j < 5; vrxq >>= 1, j++) {
1021 if (dev_info->max_rx_queues > vrxq) {
1027 /* Not enough resources to support VMDq */
1031 /* Not enough resources to support VMDq */
1035 dev_info->max_vmdq_pools = vpool;
1036 dev_info->vmdq_queue_num = vrxq;
1038 dev_info->vmdq_pool_base = 0;
1039 dev_info->vmdq_queue_base = 0;
1044 /* Configure the device based on the configuration provided */
1045 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1047 struct bnxt *bp = eth_dev->data->dev_private;
1048 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1051 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1052 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1053 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1054 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1056 rc = is_bnxt_in_error(bp);
1060 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1061 rc = bnxt_hwrm_check_vf_rings(bp);
1063 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1067 /* If a resource has already been allocated - in this case
1068 * it is the async completion ring, free it. Reallocate it after
1069 * resource reservation. This will ensure the resource counts
1070 * are calculated correctly.
1073 pthread_mutex_lock(&bp->def_cp_lock);
1075 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1076 bnxt_disable_int(bp);
1077 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1080 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1082 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1083 pthread_mutex_unlock(&bp->def_cp_lock);
1087 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1088 rc = bnxt_alloc_async_cp_ring(bp);
1090 pthread_mutex_unlock(&bp->def_cp_lock);
1093 bnxt_enable_int(bp);
1096 pthread_mutex_unlock(&bp->def_cp_lock);
1099 /* Inherit new configurations */
1100 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1101 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1102 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1103 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1104 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1106 goto resource_error;
1108 if (BNXT_HAS_RING_GRPS(bp) &&
1109 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1110 goto resource_error;
1112 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1113 bp->max_vnics < eth_dev->data->nb_rx_queues)
1114 goto resource_error;
1116 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1117 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1119 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1120 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1121 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1123 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1124 eth_dev->data->mtu =
1125 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1126 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1128 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1134 "Insufficient resources to support requested config\n");
1136 "Num Queues Requested: Tx %d, Rx %d\n",
1137 eth_dev->data->nb_tx_queues,
1138 eth_dev->data->nb_rx_queues);
1140 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1141 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1142 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1146 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1148 struct rte_eth_link *link = ð_dev->data->dev_link;
1150 if (link->link_status)
1151 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1152 eth_dev->data->port_id,
1153 (uint32_t)link->link_speed,
1154 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1155 ("full-duplex") : ("half-duplex\n"));
1157 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1158 eth_dev->data->port_id);
1162 * Determine whether the current configuration requires support for scattered
1163 * receive; return 1 if scattered receive is required and 0 if not.
1165 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1170 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1173 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1176 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1177 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1179 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1180 RTE_PKTMBUF_HEADROOM);
1181 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1187 static eth_rx_burst_t
1188 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1190 struct bnxt *bp = eth_dev->data->dev_private;
1192 /* Disable vector mode RX for Stingray2 for now */
1193 if (BNXT_CHIP_SR2(bp)) {
1194 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1195 return bnxt_recv_pkts;
1198 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1199 !defined(RTE_LIBRTE_IEEE1588)
1201 /* Vector mode receive cannot be enabled if scattered rx is in use. */
1202 if (eth_dev->data->scattered_rx)
1206 * Vector mode receive cannot be enabled if Truflow is enabled or if
1207 * asynchronous completions and receive completions can be placed in
1208 * the same completion ring.
1210 if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1214 * Vector mode receive cannot be enabled if any receive offloads outside
1215 * a limited subset have been enabled.
1217 if (eth_dev->data->dev_conf.rxmode.offloads &
1218 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1219 DEV_RX_OFFLOAD_KEEP_CRC |
1220 DEV_RX_OFFLOAD_JUMBO_FRAME |
1221 DEV_RX_OFFLOAD_IPV4_CKSUM |
1222 DEV_RX_OFFLOAD_UDP_CKSUM |
1223 DEV_RX_OFFLOAD_TCP_CKSUM |
1224 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1225 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1226 DEV_RX_OFFLOAD_RSS_HASH |
1227 DEV_RX_OFFLOAD_VLAN_FILTER))
1230 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1231 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1232 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1234 "Using AVX2 vector mode receive for port %d\n",
1235 eth_dev->data->port_id);
1236 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1237 return bnxt_recv_pkts_vec_avx2;
1240 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1242 "Using SSE vector mode receive for port %d\n",
1243 eth_dev->data->port_id);
1244 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1245 return bnxt_recv_pkts_vec;
1249 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1250 eth_dev->data->port_id);
1252 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1253 eth_dev->data->port_id,
1254 eth_dev->data->scattered_rx,
1255 eth_dev->data->dev_conf.rxmode.offloads);
1257 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1258 return bnxt_recv_pkts;
1261 static eth_tx_burst_t
1262 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1264 struct bnxt *bp = eth_dev->data->dev_private;
1266 /* Disable vector mode TX for Stingray2 for now */
1267 if (BNXT_CHIP_SR2(bp))
1268 return bnxt_xmit_pkts;
1270 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1271 !defined(RTE_LIBRTE_IEEE1588)
1272 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1275 * Vector mode transmit can be enabled only if not using scatter rx
1278 if (eth_dev->data->scattered_rx ||
1279 (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1280 BNXT_TRUFLOW_EN(bp))
1283 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1284 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1285 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1287 "Using AVX2 vector mode transmit for port %d\n",
1288 eth_dev->data->port_id);
1289 return bnxt_xmit_pkts_vec_avx2;
1292 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1294 "Using SSE vector mode transmit for port %d\n",
1295 eth_dev->data->port_id);
1296 return bnxt_xmit_pkts_vec;
1300 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1301 eth_dev->data->port_id);
1303 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1304 eth_dev->data->port_id,
1305 eth_dev->data->scattered_rx,
1308 return bnxt_xmit_pkts;
1311 static int bnxt_handle_if_change_status(struct bnxt *bp)
1315 /* Since fw has undergone a reset and lost all contexts,
1316 * set fatal flag to not issue hwrm during cleanup
1318 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1319 bnxt_uninit_resources(bp, true);
1321 /* clear fatal flag so that re-init happens */
1322 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1323 rc = bnxt_init_resources(bp, true);
1325 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1330 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1332 struct bnxt *bp = eth_dev->data->dev_private;
1335 if (!BNXT_SINGLE_PF(bp))
1338 if (!bp->link_info->link_up)
1339 rc = bnxt_set_hwrm_link_config(bp, true);
1341 eth_dev->data->dev_link.link_status = 1;
1343 bnxt_print_link_info(eth_dev);
1347 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1349 struct bnxt *bp = eth_dev->data->dev_private;
1351 if (!BNXT_SINGLE_PF(bp))
1354 eth_dev->data->dev_link.link_status = 0;
1355 bnxt_set_hwrm_link_config(bp, false);
1356 bp->link_info->link_up = 0;
1361 static void bnxt_free_switch_domain(struct bnxt *bp)
1365 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1368 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1370 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1371 bp->switch_domain_id, rc);
1374 static void bnxt_ptp_get_current_time(void *arg)
1376 struct bnxt *bp = arg;
1377 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1380 rc = is_bnxt_in_error(bp);
1387 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1388 &ptp->current_time);
1390 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1392 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1393 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1397 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1399 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1402 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1405 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1406 &ptp->current_time);
1408 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1412 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1414 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1415 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1416 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1420 static void bnxt_ptp_stop(struct bnxt *bp)
1422 bnxt_cancel_ptp_alarm(bp);
1423 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1426 static int bnxt_ptp_start(struct bnxt *bp)
1430 rc = bnxt_schedule_ptp_alarm(bp);
1432 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1434 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1435 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1441 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1443 struct bnxt *bp = eth_dev->data->dev_private;
1444 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1445 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1446 struct rte_eth_link link;
1449 eth_dev->data->dev_started = 0;
1450 eth_dev->data->scattered_rx = 0;
1452 /* Prevent crashes when queues are still in use */
1453 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1454 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1456 bnxt_disable_int(bp);
1458 /* disable uio/vfio intr/eventfd mapping */
1459 rte_intr_disable(intr_handle);
1461 /* Stop the child representors for this device */
1462 ret = bnxt_rep_stop_all(bp);
1466 /* delete the bnxt ULP port details */
1467 bnxt_ulp_port_deinit(bp);
1469 bnxt_cancel_fw_health_check(bp);
1471 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1472 bnxt_cancel_ptp_alarm(bp);
1474 /* Do not bring link down during reset recovery */
1475 if (!is_bnxt_in_error(bp)) {
1476 bnxt_dev_set_link_down_op(eth_dev);
1477 /* Wait for link to be reset */
1478 if (BNXT_SINGLE_PF(bp))
1480 /* clear the recorded link status */
1481 memset(&link, 0, sizeof(link));
1482 rte_eth_linkstatus_set(eth_dev, &link);
1485 /* Clean queue intr-vector mapping */
1486 rte_intr_efd_disable(intr_handle);
1487 if (intr_handle->intr_vec != NULL) {
1488 rte_free(intr_handle->intr_vec);
1489 intr_handle->intr_vec = NULL;
1492 bnxt_hwrm_port_clr_stats(bp);
1493 bnxt_free_tx_mbufs(bp);
1494 bnxt_free_rx_mbufs(bp);
1495 /* Process any remaining notifications in default completion queue */
1496 bnxt_int_handler(eth_dev);
1497 bnxt_shutdown_nic(bp);
1498 bnxt_hwrm_if_change(bp, false);
1500 bnxt_free_prev_ring_stats(bp);
1501 rte_free(bp->mark_table);
1502 bp->mark_table = NULL;
1504 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1505 bp->rx_cosq_cnt = 0;
1506 /* All filters are deleted on a port stop. */
1507 if (BNXT_FLOW_XSTATS_EN(bp))
1508 bp->flow_stat->flow_count = 0;
1513 /* Unload the driver, release resources */
1514 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1516 struct bnxt *bp = eth_dev->data->dev_private;
1518 pthread_mutex_lock(&bp->err_recovery_lock);
1519 if (bp->flags & BNXT_FLAG_FW_RESET) {
1521 "Adapter recovering from error..Please retry\n");
1522 pthread_mutex_unlock(&bp->err_recovery_lock);
1525 pthread_mutex_unlock(&bp->err_recovery_lock);
1527 return bnxt_dev_stop(eth_dev);
1530 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1532 struct bnxt *bp = eth_dev->data->dev_private;
1533 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1535 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1537 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1538 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1542 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1544 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1545 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1548 rc = bnxt_hwrm_if_change(bp, true);
1549 if (rc == 0 || rc != -EAGAIN)
1552 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1553 } while (retry_cnt--);
1558 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1559 rc = bnxt_handle_if_change_status(bp);
1564 bnxt_enable_int(bp);
1566 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1568 rc = bnxt_start_nic(bp);
1572 rc = bnxt_alloc_prev_ring_stats(bp);
1576 eth_dev->data->dev_started = 1;
1578 bnxt_link_update_op(eth_dev, 1);
1580 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1581 vlan_mask |= ETH_VLAN_FILTER_MASK;
1582 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1583 vlan_mask |= ETH_VLAN_STRIP_MASK;
1584 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1588 /* Initialize bnxt ULP port details */
1589 rc = bnxt_ulp_port_init(bp);
1593 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1594 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1596 bnxt_schedule_fw_health_check(bp);
1598 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1599 bnxt_schedule_ptp_alarm(bp);
1604 bnxt_dev_stop(eth_dev);
1609 bnxt_uninit_locks(struct bnxt *bp)
1611 pthread_mutex_destroy(&bp->flow_lock);
1612 pthread_mutex_destroy(&bp->def_cp_lock);
1613 pthread_mutex_destroy(&bp->health_check_lock);
1614 pthread_mutex_destroy(&bp->err_recovery_lock);
1616 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1617 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1621 static void bnxt_drv_uninit(struct bnxt *bp)
1623 bnxt_free_leds_info(bp);
1624 bnxt_free_cos_queues(bp);
1625 bnxt_free_link_info(bp);
1626 bnxt_free_parent_info(bp);
1627 bnxt_uninit_locks(bp);
1629 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1630 bp->tx_mem_zone = NULL;
1631 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1632 bp->rx_mem_zone = NULL;
1634 bnxt_free_vf_info(bp);
1635 bnxt_free_pf_info(bp);
1637 rte_free(bp->grp_info);
1638 bp->grp_info = NULL;
1641 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1643 struct bnxt *bp = eth_dev->data->dev_private;
1646 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1649 pthread_mutex_lock(&bp->err_recovery_lock);
1650 if (bp->flags & BNXT_FLAG_FW_RESET) {
1652 "Adapter recovering from error...Please retry\n");
1653 pthread_mutex_unlock(&bp->err_recovery_lock);
1656 pthread_mutex_unlock(&bp->err_recovery_lock);
1658 /* cancel the recovery handler before remove dev */
1659 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1660 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1661 bnxt_cancel_fc_thread(bp);
1663 if (eth_dev->data->dev_started)
1664 ret = bnxt_dev_stop(eth_dev);
1666 bnxt_uninit_resources(bp, false);
1668 bnxt_drv_uninit(bp);
1673 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1676 struct bnxt *bp = eth_dev->data->dev_private;
1677 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1678 struct bnxt_vnic_info *vnic;
1679 struct bnxt_filter_info *filter, *temp_filter;
1682 if (is_bnxt_in_error(bp))
1686 * Loop through all VNICs from the specified filter flow pools to
1687 * remove the corresponding MAC addr filter
1689 for (i = 0; i < bp->nr_vnics; i++) {
1690 if (!(pool_mask & (1ULL << i)))
1693 vnic = &bp->vnic_info[i];
1694 filter = STAILQ_FIRST(&vnic->filter);
1696 temp_filter = STAILQ_NEXT(filter, next);
1697 if (filter->mac_index == index) {
1698 STAILQ_REMOVE(&vnic->filter, filter,
1699 bnxt_filter_info, next);
1700 bnxt_hwrm_clear_l2_filter(bp, filter);
1701 bnxt_free_filter(bp, filter);
1703 filter = temp_filter;
1708 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1709 struct rte_ether_addr *mac_addr, uint32_t index,
1712 struct bnxt_filter_info *filter;
1715 /* Attach requested MAC address to the new l2_filter */
1716 STAILQ_FOREACH(filter, &vnic->filter, next) {
1717 if (filter->mac_index == index) {
1719 "MAC addr already existed for pool %d\n",
1725 filter = bnxt_alloc_filter(bp);
1727 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1731 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1732 * if the MAC that's been programmed now is a different one, then,
1733 * copy that addr to filter->l2_addr
1736 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1737 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1739 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1741 filter->mac_index = index;
1742 if (filter->mac_index == 0)
1743 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1745 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1747 bnxt_free_filter(bp, filter);
1753 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1754 struct rte_ether_addr *mac_addr,
1755 uint32_t index, uint32_t pool)
1757 struct bnxt *bp = eth_dev->data->dev_private;
1758 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1761 rc = is_bnxt_in_error(bp);
1765 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1766 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1771 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1775 /* Filter settings will get applied when port is started */
1776 if (!eth_dev->data->dev_started)
1779 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1784 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1787 struct bnxt *bp = eth_dev->data->dev_private;
1788 struct rte_eth_link new;
1789 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1790 BNXT_MIN_LINK_WAIT_CNT;
1792 rc = is_bnxt_in_error(bp);
1796 memset(&new, 0, sizeof(new));
1798 if (bp->link_info == NULL)
1802 /* Retrieve link info from hardware */
1803 rc = bnxt_get_hwrm_link_config(bp, &new);
1805 new.link_speed = ETH_LINK_SPEED_100M;
1806 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1808 "Failed to retrieve link rc = 0x%x!\n", rc);
1812 if (!wait_to_complete || new.link_status)
1815 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1818 /* Only single function PF can bring phy down.
1819 * When port is stopped, report link down for VF/MH/NPAR functions.
1821 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1822 memset(&new, 0, sizeof(new));
1825 /* Timed out or success */
1826 if (new.link_status != eth_dev->data->dev_link.link_status ||
1827 new.link_speed != eth_dev->data->dev_link.link_speed) {
1828 rte_eth_linkstatus_set(eth_dev, &new);
1830 rte_eth_dev_callback_process(eth_dev,
1831 RTE_ETH_EVENT_INTR_LSC,
1834 bnxt_print_link_info(eth_dev);
1840 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1842 struct bnxt *bp = eth_dev->data->dev_private;
1843 struct bnxt_vnic_info *vnic;
1847 rc = is_bnxt_in_error(bp);
1851 /* Filter settings will get applied when port is started */
1852 if (!eth_dev->data->dev_started)
1855 if (bp->vnic_info == NULL)
1858 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1860 old_flags = vnic->flags;
1861 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1862 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1864 vnic->flags = old_flags;
1869 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1871 struct bnxt *bp = eth_dev->data->dev_private;
1872 struct bnxt_vnic_info *vnic;
1876 rc = is_bnxt_in_error(bp);
1880 /* Filter settings will get applied when port is started */
1881 if (!eth_dev->data->dev_started)
1884 if (bp->vnic_info == NULL)
1887 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1889 old_flags = vnic->flags;
1890 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1891 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1893 vnic->flags = old_flags;
1898 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1900 struct bnxt *bp = eth_dev->data->dev_private;
1901 struct bnxt_vnic_info *vnic;
1905 rc = is_bnxt_in_error(bp);
1909 /* Filter settings will get applied when port is started */
1910 if (!eth_dev->data->dev_started)
1913 if (bp->vnic_info == NULL)
1916 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1918 old_flags = vnic->flags;
1919 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1920 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1922 vnic->flags = old_flags;
1927 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1929 struct bnxt *bp = eth_dev->data->dev_private;
1930 struct bnxt_vnic_info *vnic;
1934 rc = is_bnxt_in_error(bp);
1938 /* Filter settings will get applied when port is started */
1939 if (!eth_dev->data->dev_started)
1942 if (bp->vnic_info == NULL)
1945 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1947 old_flags = vnic->flags;
1948 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1949 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1951 vnic->flags = old_flags;
1956 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1957 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1959 if (qid >= bp->rx_nr_rings)
1962 return bp->eth_dev->data->rx_queues[qid];
1965 /* Return rxq corresponding to a given rss table ring/group ID. */
1966 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1968 struct bnxt_rx_queue *rxq;
1971 if (!BNXT_HAS_RING_GRPS(bp)) {
1972 for (i = 0; i < bp->rx_nr_rings; i++) {
1973 rxq = bp->eth_dev->data->rx_queues[i];
1974 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1978 for (i = 0; i < bp->rx_nr_rings; i++) {
1979 if (bp->grp_info[i].fw_grp_id == fwr)
1984 return INVALID_HW_RING_ID;
1987 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1988 struct rte_eth_rss_reta_entry64 *reta_conf,
1991 struct bnxt *bp = eth_dev->data->dev_private;
1992 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1993 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1994 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1998 rc = is_bnxt_in_error(bp);
2002 if (!vnic->rss_table)
2005 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2008 if (reta_size != tbl_size) {
2009 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2010 "(%d) must equal the size supported by the hardware "
2011 "(%d)\n", reta_size, tbl_size);
2015 for (i = 0; i < reta_size; i++) {
2016 struct bnxt_rx_queue *rxq;
2018 idx = i / RTE_RETA_GROUP_SIZE;
2019 sft = i % RTE_RETA_GROUP_SIZE;
2021 if (!(reta_conf[idx].mask & (1ULL << sft)))
2024 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2026 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2030 if (BNXT_CHIP_P5(bp)) {
2031 vnic->rss_table[i * 2] =
2032 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2033 vnic->rss_table[i * 2 + 1] =
2034 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2036 vnic->rss_table[i] =
2037 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2041 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2045 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2046 struct rte_eth_rss_reta_entry64 *reta_conf,
2049 struct bnxt *bp = eth_dev->data->dev_private;
2050 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2051 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2052 uint16_t idx, sft, i;
2055 rc = is_bnxt_in_error(bp);
2059 /* Retrieve from the default VNIC */
2062 if (!vnic->rss_table)
2065 if (reta_size != tbl_size) {
2066 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2067 "(%d) must equal the size supported by the hardware "
2068 "(%d)\n", reta_size, tbl_size);
2072 for (idx = 0, i = 0; i < reta_size; i++) {
2073 idx = i / RTE_RETA_GROUP_SIZE;
2074 sft = i % RTE_RETA_GROUP_SIZE;
2076 if (reta_conf[idx].mask & (1ULL << sft)) {
2079 if (BNXT_CHIP_P5(bp))
2080 qid = bnxt_rss_to_qid(bp,
2081 vnic->rss_table[i * 2]);
2083 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2085 if (qid == INVALID_HW_RING_ID) {
2086 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2089 reta_conf[idx].reta[sft] = qid;
2096 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2097 struct rte_eth_rss_conf *rss_conf)
2099 struct bnxt *bp = eth_dev->data->dev_private;
2100 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2101 struct bnxt_vnic_info *vnic;
2104 rc = is_bnxt_in_error(bp);
2109 * If RSS enablement were different than dev_configure,
2110 * then return -EINVAL
2112 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2113 if (!rss_conf->rss_hf)
2114 PMD_DRV_LOG(ERR, "Hash type NONE\n");
2116 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2120 bp->flags |= BNXT_FLAG_UPDATE_HASH;
2121 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
2125 /* Update the default RSS VNIC(s) */
2126 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2127 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2129 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2130 ETH_RSS_LEVEL(rss_conf->rss_hf));
2133 * If hashkey is not specified, use the previously configured
2136 if (!rss_conf->rss_key)
2139 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2141 "Invalid hashkey length, should be 16 bytes\n");
2144 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2147 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2151 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2152 struct rte_eth_rss_conf *rss_conf)
2154 struct bnxt *bp = eth_dev->data->dev_private;
2155 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2157 uint32_t hash_types;
2159 rc = is_bnxt_in_error(bp);
2163 /* RSS configuration is the same for all VNICs */
2164 if (vnic && vnic->rss_hash_key) {
2165 if (rss_conf->rss_key) {
2166 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2167 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2168 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2171 hash_types = vnic->hash_type;
2172 rss_conf->rss_hf = 0;
2173 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2174 rss_conf->rss_hf |= ETH_RSS_IPV4;
2175 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2177 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2178 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2180 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2182 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2183 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2185 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2187 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2188 rss_conf->rss_hf |= ETH_RSS_IPV6;
2189 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2191 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2192 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2194 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2196 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2197 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2199 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2203 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2207 "Unknown RSS config from firmware (%08x), RSS disabled",
2212 rss_conf->rss_hf = 0;
2217 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2218 struct rte_eth_fc_conf *fc_conf)
2220 struct bnxt *bp = dev->data->dev_private;
2221 struct rte_eth_link link_info;
2224 rc = is_bnxt_in_error(bp);
2228 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2232 memset(fc_conf, 0, sizeof(*fc_conf));
2233 if (bp->link_info->auto_pause)
2234 fc_conf->autoneg = 1;
2235 switch (bp->link_info->pause) {
2237 fc_conf->mode = RTE_FC_NONE;
2239 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2240 fc_conf->mode = RTE_FC_TX_PAUSE;
2242 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2243 fc_conf->mode = RTE_FC_RX_PAUSE;
2245 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2246 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2247 fc_conf->mode = RTE_FC_FULL;
2253 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2254 struct rte_eth_fc_conf *fc_conf)
2256 struct bnxt *bp = dev->data->dev_private;
2259 rc = is_bnxt_in_error(bp);
2263 if (!BNXT_SINGLE_PF(bp)) {
2265 "Flow Control Settings cannot be modified on VF or on shared PF\n");
2269 switch (fc_conf->mode) {
2271 bp->link_info->auto_pause = 0;
2272 bp->link_info->force_pause = 0;
2274 case RTE_FC_RX_PAUSE:
2275 if (fc_conf->autoneg) {
2276 bp->link_info->auto_pause =
2277 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2278 bp->link_info->force_pause = 0;
2280 bp->link_info->auto_pause = 0;
2281 bp->link_info->force_pause =
2282 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2285 case RTE_FC_TX_PAUSE:
2286 if (fc_conf->autoneg) {
2287 bp->link_info->auto_pause =
2288 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2289 bp->link_info->force_pause = 0;
2291 bp->link_info->auto_pause = 0;
2292 bp->link_info->force_pause =
2293 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2297 if (fc_conf->autoneg) {
2298 bp->link_info->auto_pause =
2299 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2300 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2301 bp->link_info->force_pause = 0;
2303 bp->link_info->auto_pause = 0;
2304 bp->link_info->force_pause =
2305 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2306 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2310 return bnxt_set_hwrm_link_config(bp, true);
2313 /* Add UDP tunneling port */
2315 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2316 struct rte_eth_udp_tunnel *udp_tunnel)
2318 struct bnxt *bp = eth_dev->data->dev_private;
2319 uint16_t tunnel_type = 0;
2322 rc = is_bnxt_in_error(bp);
2326 switch (udp_tunnel->prot_type) {
2327 case RTE_TUNNEL_TYPE_VXLAN:
2328 if (bp->vxlan_port_cnt) {
2329 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2330 udp_tunnel->udp_port);
2331 if (bp->vxlan_port != udp_tunnel->udp_port) {
2332 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2335 bp->vxlan_port_cnt++;
2339 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2340 bp->vxlan_port_cnt++;
2342 case RTE_TUNNEL_TYPE_GENEVE:
2343 if (bp->geneve_port_cnt) {
2344 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2345 udp_tunnel->udp_port);
2346 if (bp->geneve_port != udp_tunnel->udp_port) {
2347 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2350 bp->geneve_port_cnt++;
2354 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2355 bp->geneve_port_cnt++;
2358 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2361 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2367 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2368 struct rte_eth_udp_tunnel *udp_tunnel)
2370 struct bnxt *bp = eth_dev->data->dev_private;
2371 uint16_t tunnel_type = 0;
2375 rc = is_bnxt_in_error(bp);
2379 switch (udp_tunnel->prot_type) {
2380 case RTE_TUNNEL_TYPE_VXLAN:
2381 if (!bp->vxlan_port_cnt) {
2382 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2385 if (bp->vxlan_port != udp_tunnel->udp_port) {
2386 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2387 udp_tunnel->udp_port, bp->vxlan_port);
2390 if (--bp->vxlan_port_cnt)
2394 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2395 port = bp->vxlan_fw_dst_port_id;
2397 case RTE_TUNNEL_TYPE_GENEVE:
2398 if (!bp->geneve_port_cnt) {
2399 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2402 if (bp->geneve_port != udp_tunnel->udp_port) {
2403 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2404 udp_tunnel->udp_port, bp->geneve_port);
2407 if (--bp->geneve_port_cnt)
2411 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2412 port = bp->geneve_fw_dst_port_id;
2415 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2419 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2423 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2425 struct bnxt_filter_info *filter;
2426 struct bnxt_vnic_info *vnic;
2428 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2430 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2431 filter = STAILQ_FIRST(&vnic->filter);
2433 /* Search for this matching MAC+VLAN filter */
2434 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2435 /* Delete the filter */
2436 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2439 STAILQ_REMOVE(&vnic->filter, filter,
2440 bnxt_filter_info, next);
2441 bnxt_free_filter(bp, filter);
2443 "Deleted vlan filter for %d\n",
2447 filter = STAILQ_NEXT(filter, next);
2452 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2454 struct bnxt_filter_info *filter;
2455 struct bnxt_vnic_info *vnic;
2457 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2458 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2459 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2461 /* Implementation notes on the use of VNIC in this command:
2463 * By default, these filters belong to default vnic for the function.
2464 * Once these filters are set up, only destination VNIC can be modified.
2465 * If the destination VNIC is not specified in this command,
2466 * then the HWRM shall only create an l2 context id.
2469 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2470 filter = STAILQ_FIRST(&vnic->filter);
2471 /* Check if the VLAN has already been added */
2473 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2476 filter = STAILQ_NEXT(filter, next);
2479 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2480 * command to create MAC+VLAN filter with the right flags, enables set.
2482 filter = bnxt_alloc_filter(bp);
2485 "MAC/VLAN filter alloc failed\n");
2488 /* MAC + VLAN ID filter */
2489 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2490 * untagged packets are received
2492 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2493 * packets and only the programmed vlan's packets are received
2495 filter->l2_ivlan = vlan_id;
2496 filter->l2_ivlan_mask = 0x0FFF;
2497 filter->enables |= en;
2498 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2500 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2502 /* Free the newly allocated filter as we were
2503 * not able to create the filter in hardware.
2505 bnxt_free_filter(bp, filter);
2509 filter->mac_index = 0;
2510 /* Add this new filter to the list */
2512 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2514 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2517 "Added Vlan filter for %d\n", vlan_id);
2521 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2522 uint16_t vlan_id, int on)
2524 struct bnxt *bp = eth_dev->data->dev_private;
2527 rc = is_bnxt_in_error(bp);
2531 if (!eth_dev->data->dev_started) {
2532 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2536 /* These operations apply to ALL existing MAC/VLAN filters */
2538 return bnxt_add_vlan_filter(bp, vlan_id);
2540 return bnxt_del_vlan_filter(bp, vlan_id);
2543 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2544 struct bnxt_vnic_info *vnic)
2546 struct bnxt_filter_info *filter;
2549 filter = STAILQ_FIRST(&vnic->filter);
2551 if (filter->mac_index == 0 &&
2552 !memcmp(filter->l2_addr, bp->mac_addr,
2553 RTE_ETHER_ADDR_LEN)) {
2554 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2556 STAILQ_REMOVE(&vnic->filter, filter,
2557 bnxt_filter_info, next);
2558 bnxt_free_filter(bp, filter);
2562 filter = STAILQ_NEXT(filter, next);
2568 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2570 struct bnxt_vnic_info *vnic;
2574 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2575 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2576 /* Remove any VLAN filters programmed */
2577 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2578 bnxt_del_vlan_filter(bp, i);
2580 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2584 /* Default filter will allow packets that match the
2585 * dest mac. So, it has to be deleted, otherwise, we
2586 * will endup receiving vlan packets for which the
2587 * filter is not programmed, when hw-vlan-filter
2588 * configuration is ON
2590 bnxt_del_dflt_mac_filter(bp, vnic);
2591 /* This filter will allow only untagged packets */
2592 bnxt_add_vlan_filter(bp, 0);
2594 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2595 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2600 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2602 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2606 /* Destroy vnic filters and vnic */
2607 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2608 DEV_RX_OFFLOAD_VLAN_FILTER) {
2609 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2610 bnxt_del_vlan_filter(bp, i);
2612 bnxt_del_dflt_mac_filter(bp, vnic);
2614 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2618 rc = bnxt_hwrm_vnic_free(bp, vnic);
2622 rte_free(vnic->fw_grp_ids);
2623 vnic->fw_grp_ids = NULL;
2625 vnic->rx_queue_cnt = 0;
2631 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2633 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2636 /* Destroy, recreate and reconfigure the default vnic */
2637 rc = bnxt_free_one_vnic(bp, 0);
2641 /* default vnic 0 */
2642 rc = bnxt_setup_one_vnic(bp, 0);
2646 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2647 DEV_RX_OFFLOAD_VLAN_FILTER) {
2648 rc = bnxt_add_vlan_filter(bp, 0);
2651 rc = bnxt_restore_vlan_filters(bp);
2655 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2660 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2664 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2665 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2671 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2673 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2674 struct bnxt *bp = dev->data->dev_private;
2677 rc = is_bnxt_in_error(bp);
2681 /* Filter settings will get applied when port is started */
2682 if (!dev->data->dev_started)
2685 if (mask & ETH_VLAN_FILTER_MASK) {
2686 /* Enable or disable VLAN filtering */
2687 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2692 if (mask & ETH_VLAN_STRIP_MASK) {
2693 /* Enable or disable VLAN stripping */
2694 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2699 if (mask & ETH_VLAN_EXTEND_MASK) {
2700 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2701 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2703 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2710 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2713 struct bnxt *bp = dev->data->dev_private;
2714 int qinq = dev->data->dev_conf.rxmode.offloads &
2715 DEV_RX_OFFLOAD_VLAN_EXTEND;
2717 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2718 vlan_type != ETH_VLAN_TYPE_OUTER) {
2720 "Unsupported vlan type.");
2725 "QinQ not enabled. Needs to be ON as we can "
2726 "accelerate only outer vlan\n");
2730 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2732 case RTE_ETHER_TYPE_QINQ:
2734 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2736 case RTE_ETHER_TYPE_VLAN:
2738 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2740 case RTE_ETHER_TYPE_QINQ1:
2742 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2744 case RTE_ETHER_TYPE_QINQ2:
2746 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2748 case RTE_ETHER_TYPE_QINQ3:
2750 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2753 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2756 bp->outer_tpid_bd |= tpid;
2757 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2758 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2760 "Can accelerate only outer vlan in QinQ\n");
2768 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2769 struct rte_ether_addr *addr)
2771 struct bnxt *bp = dev->data->dev_private;
2772 /* Default Filter is tied to VNIC 0 */
2773 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2776 rc = is_bnxt_in_error(bp);
2780 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2783 if (rte_is_zero_ether_addr(addr))
2786 /* Filter settings will get applied when port is started */
2787 if (!dev->data->dev_started)
2790 /* Check if the requested MAC is already added */
2791 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2794 /* Destroy filter and re-create it */
2795 bnxt_del_dflt_mac_filter(bp, vnic);
2797 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2798 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2799 /* This filter will allow only untagged packets */
2800 rc = bnxt_add_vlan_filter(bp, 0);
2802 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2805 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2810 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2811 struct rte_ether_addr *mc_addr_set,
2812 uint32_t nb_mc_addr)
2814 struct bnxt *bp = eth_dev->data->dev_private;
2815 char *mc_addr_list = (char *)mc_addr_set;
2816 struct bnxt_vnic_info *vnic;
2817 uint32_t off = 0, i = 0;
2820 rc = is_bnxt_in_error(bp);
2824 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2826 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2827 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2831 /* TODO Check for Duplicate mcast addresses */
2832 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2833 for (i = 0; i < nb_mc_addr; i++) {
2834 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2835 RTE_ETHER_ADDR_LEN);
2836 off += RTE_ETHER_ADDR_LEN;
2839 vnic->mc_addr_cnt = i;
2840 if (vnic->mc_addr_cnt)
2841 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2843 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2846 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2850 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2852 struct bnxt *bp = dev->data->dev_private;
2853 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2854 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2855 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2856 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2859 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2860 fw_major, fw_minor, fw_updt, fw_rsvd);
2864 ret += 1; /* add the size of '\0' */
2865 if (fw_size < (size_t)ret)
2872 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2873 struct rte_eth_rxq_info *qinfo)
2875 struct bnxt *bp = dev->data->dev_private;
2876 struct bnxt_rx_queue *rxq;
2878 if (is_bnxt_in_error(bp))
2881 rxq = dev->data->rx_queues[queue_id];
2883 qinfo->mp = rxq->mb_pool;
2884 qinfo->scattered_rx = dev->data->scattered_rx;
2885 qinfo->nb_desc = rxq->nb_rx_desc;
2887 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2888 qinfo->conf.rx_drop_en = rxq->drop_en;
2889 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2890 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2894 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2895 struct rte_eth_txq_info *qinfo)
2897 struct bnxt *bp = dev->data->dev_private;
2898 struct bnxt_tx_queue *txq;
2900 if (is_bnxt_in_error(bp))
2903 txq = dev->data->tx_queues[queue_id];
2905 qinfo->nb_desc = txq->nb_tx_desc;
2907 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2908 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2909 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2911 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2912 qinfo->conf.tx_rs_thresh = 0;
2913 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2914 qinfo->conf.offloads = txq->offloads;
2917 static const struct {
2918 eth_rx_burst_t pkt_burst;
2920 } bnxt_rx_burst_info[] = {
2921 {bnxt_recv_pkts, "Scalar"},
2922 #if defined(RTE_ARCH_X86)
2923 {bnxt_recv_pkts_vec, "Vector SSE"},
2925 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2926 {bnxt_recv_pkts_vec_avx2, "Vector AVX2"},
2928 #if defined(RTE_ARCH_ARM64)
2929 {bnxt_recv_pkts_vec, "Vector Neon"},
2934 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2935 struct rte_eth_burst_mode *mode)
2937 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2940 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2941 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2942 snprintf(mode->info, sizeof(mode->info), "%s",
2943 bnxt_rx_burst_info[i].info);
2951 static const struct {
2952 eth_tx_burst_t pkt_burst;
2954 } bnxt_tx_burst_info[] = {
2955 {bnxt_xmit_pkts, "Scalar"},
2956 #if defined(RTE_ARCH_X86)
2957 {bnxt_xmit_pkts_vec, "Vector SSE"},
2959 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2960 {bnxt_xmit_pkts_vec_avx2, "Vector AVX2"},
2962 #if defined(RTE_ARCH_ARM64)
2963 {bnxt_xmit_pkts_vec, "Vector Neon"},
2968 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2969 struct rte_eth_burst_mode *mode)
2971 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2974 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2975 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2976 snprintf(mode->info, sizeof(mode->info), "%s",
2977 bnxt_tx_burst_info[i].info);
2985 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2987 struct bnxt *bp = eth_dev->data->dev_private;
2988 uint32_t new_pkt_size;
2992 rc = is_bnxt_in_error(bp);
2996 /* Exit if receive queues are not configured yet */
2997 if (!eth_dev->data->nb_rx_queues)
3000 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
3001 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
3004 * Disallow any MTU change that would require scattered receive support
3005 * if it is not already enabled.
3007 if (eth_dev->data->dev_started &&
3008 !eth_dev->data->scattered_rx &&
3010 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3012 "MTU change would require scattered rx support. ");
3013 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3017 if (new_mtu > RTE_ETHER_MTU) {
3018 bp->flags |= BNXT_FLAG_JUMBO;
3019 bp->eth_dev->data->dev_conf.rxmode.offloads |=
3020 DEV_RX_OFFLOAD_JUMBO_FRAME;
3022 bp->eth_dev->data->dev_conf.rxmode.offloads &=
3023 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3024 bp->flags &= ~BNXT_FLAG_JUMBO;
3027 /* Is there a change in mtu setting? */
3028 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
3031 for (i = 0; i < bp->nr_vnics; i++) {
3032 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3035 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3036 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3040 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3041 size -= RTE_PKTMBUF_HEADROOM;
3043 if (size < new_mtu) {
3044 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3051 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
3053 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3059 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3061 struct bnxt *bp = dev->data->dev_private;
3062 uint16_t vlan = bp->vlan;
3065 rc = is_bnxt_in_error(bp);
3069 if (!BNXT_SINGLE_PF(bp)) {
3070 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3073 bp->vlan = on ? pvid : 0;
3075 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3082 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3084 struct bnxt *bp = dev->data->dev_private;
3087 rc = is_bnxt_in_error(bp);
3091 return bnxt_hwrm_port_led_cfg(bp, true);
3095 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3097 struct bnxt *bp = dev->data->dev_private;
3100 rc = is_bnxt_in_error(bp);
3104 return bnxt_hwrm_port_led_cfg(bp, false);
3108 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3110 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3111 struct bnxt_cp_ring_info *cpr;
3112 uint32_t desc = 0, raw_cons;
3113 struct bnxt_rx_queue *rxq;
3114 struct rx_pkt_cmpl *rxcmp;
3117 rc = is_bnxt_in_error(bp);
3121 rxq = dev->data->rx_queues[rx_queue_id];
3123 raw_cons = cpr->cp_raw_cons;
3126 uint32_t agg_cnt, cons, cmpl_type;
3128 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3129 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3131 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3134 cmpl_type = CMP_TYPE(rxcmp);
3136 switch (cmpl_type) {
3137 case CMPL_BASE_TYPE_RX_L2:
3138 case CMPL_BASE_TYPE_RX_L2_V2:
3139 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3140 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3144 case CMPL_BASE_TYPE_RX_TPA_END:
3145 if (BNXT_CHIP_P5(rxq->bp)) {
3146 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3148 p5_tpa_end = (void *)rxcmp;
3149 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3151 struct rx_tpa_end_cmpl *tpa_end;
3153 tpa_end = (void *)rxcmp;
3154 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3157 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3162 raw_cons += CMP_LEN(cmpl_type);
3170 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3172 struct bnxt_rx_queue *rxq = rx_queue;
3173 struct bnxt_cp_ring_info *cpr;
3174 struct bnxt_rx_ring_info *rxr;
3175 uint32_t desc, raw_cons;
3176 struct bnxt *bp = rxq->bp;
3177 struct rx_pkt_cmpl *rxcmp;
3180 rc = is_bnxt_in_error(bp);
3184 if (offset >= rxq->nb_rx_desc)
3191 * For the vector receive case, the completion at the requested
3192 * offset can be indexed directly.
3194 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3195 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3196 struct rx_pkt_cmpl *rxcmp;
3199 /* Check status of completion descriptor. */
3200 raw_cons = cpr->cp_raw_cons +
3201 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3202 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3203 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3205 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3206 return RTE_ETH_RX_DESC_DONE;
3208 /* Check whether rx desc has an mbuf attached. */
3209 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3210 if (cons >= rxq->rxrearm_start &&
3211 cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3212 return RTE_ETH_RX_DESC_UNAVAIL;
3215 return RTE_ETH_RX_DESC_AVAIL;
3220 * For the non-vector receive case, scan the completion ring to
3221 * locate the completion descriptor for the requested offset.
3223 raw_cons = cpr->cp_raw_cons;
3226 uint32_t agg_cnt, cons, cmpl_type;
3228 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3229 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3231 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3234 cmpl_type = CMP_TYPE(rxcmp);
3236 switch (cmpl_type) {
3237 case CMPL_BASE_TYPE_RX_L2:
3238 case CMPL_BASE_TYPE_RX_L2_V2:
3239 if (desc == offset) {
3240 cons = rxcmp->opaque;
3241 if (rxr->rx_buf_ring[cons])
3242 return RTE_ETH_RX_DESC_DONE;
3244 return RTE_ETH_RX_DESC_UNAVAIL;
3246 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3247 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3251 case CMPL_BASE_TYPE_RX_TPA_END:
3253 return RTE_ETH_RX_DESC_DONE;
3255 if (BNXT_CHIP_P5(rxq->bp)) {
3256 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3258 p5_tpa_end = (void *)rxcmp;
3259 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3261 struct rx_tpa_end_cmpl *tpa_end;
3263 tpa_end = (void *)rxcmp;
3264 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3267 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3272 raw_cons += CMP_LEN(cmpl_type);
3276 return RTE_ETH_RX_DESC_AVAIL;
3280 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3282 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3283 struct bnxt_tx_ring_info *txr;
3284 struct bnxt_cp_ring_info *cpr;
3285 struct rte_mbuf **tx_buf;
3286 struct tx_pkt_cmpl *txcmp;
3287 uint32_t cons, cp_cons;
3293 rc = is_bnxt_in_error(txq->bp);
3300 if (offset >= txq->nb_tx_desc)
3303 cons = RING_CMP(cpr->cp_ring_struct, offset);
3304 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3305 cp_cons = cpr->cp_raw_cons;
3307 if (cons > cp_cons) {
3308 if (CMPL_VALID(txcmp, cpr->valid))
3309 return RTE_ETH_TX_DESC_UNAVAIL;
3311 if (CMPL_VALID(txcmp, !cpr->valid))
3312 return RTE_ETH_TX_DESC_UNAVAIL;
3314 tx_buf = &txr->tx_buf_ring[cons];
3315 if (*tx_buf == NULL)
3316 return RTE_ETH_TX_DESC_DONE;
3318 return RTE_ETH_TX_DESC_FULL;
3322 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3323 const struct rte_flow_ops **ops)
3325 struct bnxt *bp = dev->data->dev_private;
3331 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3332 struct bnxt_representor *vfr = dev->data->dev_private;
3333 bp = vfr->parent_dev->data->dev_private;
3334 /* parent is deleted while children are still valid */
3336 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3337 dev->data->port_id);
3342 ret = is_bnxt_in_error(bp);
3346 /* PMD supports thread-safe flow operations. rte_flow API
3347 * functions can avoid mutex for multi-thread safety.
3349 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3351 if (BNXT_TRUFLOW_EN(bp))
3352 *ops = &bnxt_ulp_rte_flow_ops;
3354 *ops = &bnxt_flow_ops;
3359 static const uint32_t *
3360 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3362 static const uint32_t ptypes[] = {
3363 RTE_PTYPE_L2_ETHER_VLAN,
3364 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3365 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3369 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3370 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3371 RTE_PTYPE_INNER_L4_ICMP,
3372 RTE_PTYPE_INNER_L4_TCP,
3373 RTE_PTYPE_INNER_L4_UDP,
3377 if (!dev->rx_pkt_burst)
3383 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3386 uint32_t reg_base = *reg_arr & 0xfffff000;
3390 for (i = 0; i < count; i++) {
3391 if ((reg_arr[i] & 0xfffff000) != reg_base)
3394 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3395 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3399 static int bnxt_map_ptp_regs(struct bnxt *bp)
3401 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3405 reg_arr = ptp->rx_regs;
3406 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3410 reg_arr = ptp->tx_regs;
3411 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3415 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3416 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3418 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3419 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3424 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3426 rte_write32(0, (uint8_t *)bp->bar0 +
3427 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3428 rte_write32(0, (uint8_t *)bp->bar0 +
3429 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3432 static uint64_t bnxt_cc_read(struct bnxt *bp)
3436 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3437 BNXT_GRCPF_REG_SYNC_TIME));
3438 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3439 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3443 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3445 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3448 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3449 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3450 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3453 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3454 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3455 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3456 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3457 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3458 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3459 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3464 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3466 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3467 struct bnxt_pf_info *pf = bp->pf;
3472 if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3475 port_id = pf->port_id;
3476 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3477 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3478 while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3479 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3480 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3481 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3482 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3483 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3484 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3485 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3486 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3490 if (i >= BNXT_PTP_RX_PND_CNT)
3496 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3498 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3499 struct bnxt_pf_info *pf = bp->pf;
3503 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3504 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3505 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3508 port_id = pf->port_id;
3509 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3510 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3512 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3513 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3514 if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3515 return bnxt_clr_rx_ts(bp, ts);
3517 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3518 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3519 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3520 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3526 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3529 struct bnxt *bp = dev->data->dev_private;
3530 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3535 ns = rte_timespec_to_ns(ts);
3536 /* Set the timecounters to a new value. */
3538 ptp->tx_tstamp_tc.nsec = ns;
3539 ptp->rx_tstamp_tc.nsec = ns;
3545 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3547 struct bnxt *bp = dev->data->dev_private;
3548 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3549 uint64_t ns, systime_cycles = 0;
3555 if (BNXT_CHIP_P5(bp))
3556 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3559 systime_cycles = bnxt_cc_read(bp);
3561 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3562 *ts = rte_ns_to_timespec(ns);
3567 bnxt_timesync_enable(struct rte_eth_dev *dev)
3569 struct bnxt *bp = dev->data->dev_private;
3570 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3578 ptp->tx_tstamp_en = 1;
3579 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3581 rc = bnxt_hwrm_ptp_cfg(bp);
3585 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3586 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3587 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3589 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3590 ptp->tc.cc_shift = shift;
3591 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3593 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3594 ptp->rx_tstamp_tc.cc_shift = shift;
3595 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3597 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3598 ptp->tx_tstamp_tc.cc_shift = shift;
3599 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3601 if (!BNXT_CHIP_P5(bp))
3602 bnxt_map_ptp_regs(bp);
3604 rc = bnxt_ptp_start(bp);
3610 bnxt_timesync_disable(struct rte_eth_dev *dev)
3612 struct bnxt *bp = dev->data->dev_private;
3613 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3619 ptp->tx_tstamp_en = 0;
3622 bnxt_hwrm_ptp_cfg(bp);
3624 if (!BNXT_CHIP_P5(bp))
3625 bnxt_unmap_ptp_regs(bp);
3633 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3634 struct timespec *timestamp,
3635 uint32_t flags __rte_unused)
3637 struct bnxt *bp = dev->data->dev_private;
3638 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3639 uint64_t rx_tstamp_cycles = 0;
3645 if (BNXT_CHIP_P5(bp))
3646 rx_tstamp_cycles = ptp->rx_timestamp;
3648 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3650 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3651 *timestamp = rte_ns_to_timespec(ns);
3656 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3657 struct timespec *timestamp)
3659 struct bnxt *bp = dev->data->dev_private;
3660 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3661 uint64_t tx_tstamp_cycles = 0;
3668 if (BNXT_CHIP_P5(bp))
3669 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3672 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3674 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3675 *timestamp = rte_ns_to_timespec(ns);
3681 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3683 struct bnxt *bp = dev->data->dev_private;
3684 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3689 ptp->tc.nsec += delta;
3690 ptp->tx_tstamp_tc.nsec += delta;
3691 ptp->rx_tstamp_tc.nsec += delta;
3697 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3699 struct bnxt *bp = dev->data->dev_private;
3701 uint32_t dir_entries;
3702 uint32_t entry_length;
3704 rc = is_bnxt_in_error(bp);
3708 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3709 bp->pdev->addr.domain, bp->pdev->addr.bus,
3710 bp->pdev->addr.devid, bp->pdev->addr.function);
3712 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3716 return dir_entries * entry_length;
3720 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3721 struct rte_dev_eeprom_info *in_eeprom)
3723 struct bnxt *bp = dev->data->dev_private;
3728 rc = is_bnxt_in_error(bp);
3732 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3733 bp->pdev->addr.domain, bp->pdev->addr.bus,
3734 bp->pdev->addr.devid, bp->pdev->addr.function,
3735 in_eeprom->offset, in_eeprom->length);
3737 if (in_eeprom->offset == 0) /* special offset value to get directory */
3738 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3741 index = in_eeprom->offset >> 24;
3742 offset = in_eeprom->offset & 0xffffff;
3745 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3746 in_eeprom->length, in_eeprom->data);
3751 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3754 case BNX_DIR_TYPE_CHIMP_PATCH:
3755 case BNX_DIR_TYPE_BOOTCODE:
3756 case BNX_DIR_TYPE_BOOTCODE_2:
3757 case BNX_DIR_TYPE_APE_FW:
3758 case BNX_DIR_TYPE_APE_PATCH:
3759 case BNX_DIR_TYPE_KONG_FW:
3760 case BNX_DIR_TYPE_KONG_PATCH:
3761 case BNX_DIR_TYPE_BONO_FW:
3762 case BNX_DIR_TYPE_BONO_PATCH:
3770 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3773 case BNX_DIR_TYPE_AVS:
3774 case BNX_DIR_TYPE_EXP_ROM_MBA:
3775 case BNX_DIR_TYPE_PCIE:
3776 case BNX_DIR_TYPE_TSCF_UCODE:
3777 case BNX_DIR_TYPE_EXT_PHY:
3778 case BNX_DIR_TYPE_CCM:
3779 case BNX_DIR_TYPE_ISCSI_BOOT:
3780 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3781 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3789 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3791 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3792 bnxt_dir_type_is_other_exec_format(dir_type);
3796 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3797 struct rte_dev_eeprom_info *in_eeprom)
3799 struct bnxt *bp = dev->data->dev_private;
3800 uint8_t index, dir_op;
3801 uint16_t type, ext, ordinal, attr;
3804 rc = is_bnxt_in_error(bp);
3808 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3809 bp->pdev->addr.domain, bp->pdev->addr.bus,
3810 bp->pdev->addr.devid, bp->pdev->addr.function,
3811 in_eeprom->offset, in_eeprom->length);
3814 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3818 type = in_eeprom->magic >> 16;
3820 if (type == 0xffff) { /* special value for directory operations */
3821 index = in_eeprom->magic & 0xff;
3822 dir_op = in_eeprom->magic >> 8;
3826 case 0x0e: /* erase */
3827 if (in_eeprom->offset != ~in_eeprom->magic)
3829 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3835 /* Create or re-write an NVM item: */
3836 if (bnxt_dir_type_is_executable(type) == true)
3838 ext = in_eeprom->magic & 0xffff;
3839 ordinal = in_eeprom->offset >> 16;
3840 attr = in_eeprom->offset & 0xffff;
3842 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3843 in_eeprom->data, in_eeprom->length);
3850 static const struct eth_dev_ops bnxt_dev_ops = {
3851 .dev_infos_get = bnxt_dev_info_get_op,
3852 .dev_close = bnxt_dev_close_op,
3853 .dev_configure = bnxt_dev_configure_op,
3854 .dev_start = bnxt_dev_start_op,
3855 .dev_stop = bnxt_dev_stop_op,
3856 .dev_set_link_up = bnxt_dev_set_link_up_op,
3857 .dev_set_link_down = bnxt_dev_set_link_down_op,
3858 .stats_get = bnxt_stats_get_op,
3859 .stats_reset = bnxt_stats_reset_op,
3860 .rx_queue_setup = bnxt_rx_queue_setup_op,
3861 .rx_queue_release = bnxt_rx_queue_release_op,
3862 .tx_queue_setup = bnxt_tx_queue_setup_op,
3863 .tx_queue_release = bnxt_tx_queue_release_op,
3864 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3865 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3866 .reta_update = bnxt_reta_update_op,
3867 .reta_query = bnxt_reta_query_op,
3868 .rss_hash_update = bnxt_rss_hash_update_op,
3869 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3870 .link_update = bnxt_link_update_op,
3871 .promiscuous_enable = bnxt_promiscuous_enable_op,
3872 .promiscuous_disable = bnxt_promiscuous_disable_op,
3873 .allmulticast_enable = bnxt_allmulticast_enable_op,
3874 .allmulticast_disable = bnxt_allmulticast_disable_op,
3875 .mac_addr_add = bnxt_mac_addr_add_op,
3876 .mac_addr_remove = bnxt_mac_addr_remove_op,
3877 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3878 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3879 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3880 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3881 .vlan_filter_set = bnxt_vlan_filter_set_op,
3882 .vlan_offload_set = bnxt_vlan_offload_set_op,
3883 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3884 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3885 .mtu_set = bnxt_mtu_set_op,
3886 .mac_addr_set = bnxt_set_default_mac_addr_op,
3887 .xstats_get = bnxt_dev_xstats_get_op,
3888 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3889 .xstats_reset = bnxt_dev_xstats_reset_op,
3890 .fw_version_get = bnxt_fw_version_get,
3891 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3892 .rxq_info_get = bnxt_rxq_info_get_op,
3893 .txq_info_get = bnxt_txq_info_get_op,
3894 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3895 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3896 .dev_led_on = bnxt_dev_led_on_op,
3897 .dev_led_off = bnxt_dev_led_off_op,
3898 .rx_queue_start = bnxt_rx_queue_start,
3899 .rx_queue_stop = bnxt_rx_queue_stop,
3900 .tx_queue_start = bnxt_tx_queue_start,
3901 .tx_queue_stop = bnxt_tx_queue_stop,
3902 .flow_ops_get = bnxt_flow_ops_get_op,
3903 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3904 .get_eeprom_length = bnxt_get_eeprom_length_op,
3905 .get_eeprom = bnxt_get_eeprom_op,
3906 .set_eeprom = bnxt_set_eeprom_op,
3907 .timesync_enable = bnxt_timesync_enable,
3908 .timesync_disable = bnxt_timesync_disable,
3909 .timesync_read_time = bnxt_timesync_read_time,
3910 .timesync_write_time = bnxt_timesync_write_time,
3911 .timesync_adjust_time = bnxt_timesync_adjust_time,
3912 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3913 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3916 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3920 /* Only pre-map the reset GRC registers using window 3 */
3921 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3922 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3924 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3929 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3931 struct bnxt_error_recovery_info *info = bp->recovery_info;
3932 uint32_t reg_base = 0xffffffff;
3935 /* Only pre-map the monitoring GRC registers using window 2 */
3936 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3937 uint32_t reg = info->status_regs[i];
3939 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3942 if (reg_base == 0xffffffff)
3943 reg_base = reg & 0xfffff000;
3944 if ((reg & 0xfffff000) != reg_base)
3947 /* Use mask 0xffc as the Lower 2 bits indicates
3948 * address space location
3950 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3954 if (reg_base == 0xffffffff)
3957 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3958 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3963 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3965 struct bnxt_error_recovery_info *info = bp->recovery_info;
3966 uint32_t delay = info->delay_after_reset[index];
3967 uint32_t val = info->reset_reg_val[index];
3968 uint32_t reg = info->reset_reg[index];
3969 uint32_t type, offset;
3972 type = BNXT_FW_STATUS_REG_TYPE(reg);
3973 offset = BNXT_FW_STATUS_REG_OFF(reg);
3976 case BNXT_FW_STATUS_REG_TYPE_CFG:
3977 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3979 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
3984 case BNXT_FW_STATUS_REG_TYPE_GRC:
3985 offset = bnxt_map_reset_regs(bp, offset);
3986 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3988 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3989 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3992 /* wait on a specific interval of time until core reset is complete */
3994 rte_delay_ms(delay);
3997 static void bnxt_dev_cleanup(struct bnxt *bp)
3999 bp->eth_dev->data->dev_link.link_status = 0;
4000 bp->link_info->link_up = 0;
4001 if (bp->eth_dev->data->dev_started)
4002 bnxt_dev_stop(bp->eth_dev);
4004 bnxt_uninit_resources(bp, true);
4008 bnxt_check_fw_reset_done(struct bnxt *bp)
4010 int timeout = bp->fw_reset_max_msecs;
4015 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4017 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4023 } while (timeout--);
4025 if (val == 0xffff) {
4026 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4033 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4035 struct rte_eth_dev *dev = bp->eth_dev;
4036 struct rte_vlan_filter_conf *vfc;
4040 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4041 vfc = &dev->data->vlan_filter_conf;
4042 vidx = vlan_id / 64;
4043 vbit = vlan_id % 64;
4045 /* Each bit corresponds to a VLAN id */
4046 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4047 rc = bnxt_add_vlan_filter(bp, vlan_id);
4056 static int bnxt_restore_mac_filters(struct bnxt *bp)
4058 struct rte_eth_dev *dev = bp->eth_dev;
4059 struct rte_eth_dev_info dev_info;
4060 struct rte_ether_addr *addr;
4066 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4069 rc = bnxt_dev_info_get_op(dev, &dev_info);
4073 /* replay MAC address configuration */
4074 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4075 addr = &dev->data->mac_addrs[i];
4077 /* skip zero address */
4078 if (rte_is_zero_ether_addr(addr))
4082 pool_mask = dev->data->mac_pool_sel[i];
4085 if (pool_mask & 1ULL) {
4086 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4092 } while (pool_mask);
4098 static int bnxt_restore_filters(struct bnxt *bp)
4100 struct rte_eth_dev *dev = bp->eth_dev;
4103 if (dev->data->all_multicast) {
4104 ret = bnxt_allmulticast_enable_op(dev);
4108 if (dev->data->promiscuous) {
4109 ret = bnxt_promiscuous_enable_op(dev);
4114 ret = bnxt_restore_mac_filters(bp);
4118 ret = bnxt_restore_vlan_filters(bp);
4119 /* TODO restore other filters as well */
4123 static int bnxt_check_fw_ready(struct bnxt *bp)
4125 int timeout = bp->fw_reset_max_msecs;
4129 rc = bnxt_hwrm_poll_ver_get(bp);
4132 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4133 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4134 } while (rc && timeout > 0);
4137 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4142 static void bnxt_dev_recover(void *arg)
4144 struct bnxt *bp = arg;
4147 pthread_mutex_lock(&bp->err_recovery_lock);
4149 if (!bp->fw_reset_min_msecs) {
4150 rc = bnxt_check_fw_reset_done(bp);
4155 /* Clear Error flag so that device re-init should happen */
4156 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4158 rc = bnxt_check_fw_ready(bp);
4162 rc = bnxt_init_resources(bp, true);
4165 "Failed to initialize resources after reset\n");
4168 /* clear reset flag as the device is initialized now */
4169 bp->flags &= ~BNXT_FLAG_FW_RESET;
4171 rc = bnxt_dev_start_op(bp->eth_dev);
4173 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4177 rc = bnxt_restore_filters(bp);
4181 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4182 pthread_mutex_unlock(&bp->err_recovery_lock);
4186 bnxt_dev_stop(bp->eth_dev);
4188 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4189 bnxt_uninit_resources(bp, false);
4190 pthread_mutex_unlock(&bp->err_recovery_lock);
4191 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4194 void bnxt_dev_reset_and_resume(void *arg)
4196 struct bnxt *bp = arg;
4197 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4201 bnxt_dev_cleanup(bp);
4203 bnxt_wait_for_device_shutdown(bp);
4205 /* During some fatal firmware error conditions, the PCI config space
4206 * register 0x2e which normally contains the subsystem ID will become
4207 * 0xffff. This register will revert back to the normal value after
4208 * the chip has completed core reset. If we detect this condition,
4209 * we can poll this config register immediately for the value to revert.
4211 if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4212 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4214 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4217 if (val == 0xffff) {
4218 bp->fw_reset_min_msecs = 0;
4223 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4225 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4228 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4230 struct bnxt_error_recovery_info *info = bp->recovery_info;
4231 uint32_t reg = info->status_regs[index];
4232 uint32_t type, offset, val = 0;
4235 type = BNXT_FW_STATUS_REG_TYPE(reg);
4236 offset = BNXT_FW_STATUS_REG_OFF(reg);
4239 case BNXT_FW_STATUS_REG_TYPE_CFG:
4240 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4242 PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4245 case BNXT_FW_STATUS_REG_TYPE_GRC:
4246 offset = info->mapped_status_regs[index];
4248 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4249 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4257 static int bnxt_fw_reset_all(struct bnxt *bp)
4259 struct bnxt_error_recovery_info *info = bp->recovery_info;
4263 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4264 /* Reset through master function driver */
4265 for (i = 0; i < info->reg_array_cnt; i++)
4266 bnxt_write_fw_reset_reg(bp, i);
4267 /* Wait for time specified by FW after triggering reset */
4268 rte_delay_ms(info->master_func_wait_period_after_reset);
4269 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4270 /* Reset with the help of Kong processor */
4271 rc = bnxt_hwrm_fw_reset(bp);
4273 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4279 static void bnxt_fw_reset_cb(void *arg)
4281 struct bnxt *bp = arg;
4282 struct bnxt_error_recovery_info *info = bp->recovery_info;
4285 /* Only Master function can do FW reset */
4286 if (bnxt_is_master_func(bp) &&
4287 bnxt_is_recovery_enabled(bp)) {
4288 rc = bnxt_fw_reset_all(bp);
4290 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4295 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4296 * EXCEPTION_FATAL_ASYNC event to all the functions
4297 * (including MASTER FUNC). After receiving this Async, all the active
4298 * drivers should treat this case as FW initiated recovery
4300 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4301 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4302 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4304 /* To recover from error */
4305 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4310 /* Driver should poll FW heartbeat, reset_counter with the frequency
4311 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4312 * When the driver detects heartbeat stop or change in reset_counter,
4313 * it has to trigger a reset to recover from the error condition.
4314 * A “master PF” is the function who will have the privilege to
4315 * initiate the chimp reset. The master PF will be elected by the
4316 * firmware and will be notified through async message.
4318 static void bnxt_check_fw_health(void *arg)
4320 struct bnxt *bp = arg;
4321 struct bnxt_error_recovery_info *info = bp->recovery_info;
4322 uint32_t val = 0, wait_msec;
4324 if (!info || !bnxt_is_recovery_enabled(bp) ||
4325 is_bnxt_in_error(bp))
4328 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4329 if (val == info->last_heart_beat)
4332 info->last_heart_beat = val;
4334 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4335 if (val != info->last_reset_counter)
4338 info->last_reset_counter = val;
4340 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4341 bnxt_check_fw_health, (void *)bp);
4345 /* Stop DMA to/from device */
4346 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4347 bp->flags |= BNXT_FLAG_FW_RESET;
4351 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4353 if (bnxt_is_master_func(bp))
4354 wait_msec = info->master_func_wait_period;
4356 wait_msec = info->normal_func_wait_period;
4358 rte_eal_alarm_set(US_PER_MS * wait_msec,
4359 bnxt_fw_reset_cb, (void *)bp);
4362 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4364 uint32_t polling_freq;
4366 pthread_mutex_lock(&bp->health_check_lock);
4368 if (!bnxt_is_recovery_enabled(bp))
4371 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4374 polling_freq = bp->recovery_info->driver_polling_freq;
4376 rte_eal_alarm_set(US_PER_MS * polling_freq,
4377 bnxt_check_fw_health, (void *)bp);
4378 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4381 pthread_mutex_unlock(&bp->health_check_lock);
4384 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4386 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4387 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4390 static bool bnxt_vf_pciid(uint16_t device_id)
4392 switch (device_id) {
4393 case BROADCOM_DEV_ID_57304_VF:
4394 case BROADCOM_DEV_ID_57406_VF:
4395 case BROADCOM_DEV_ID_5731X_VF:
4396 case BROADCOM_DEV_ID_5741X_VF:
4397 case BROADCOM_DEV_ID_57414_VF:
4398 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4399 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4400 case BROADCOM_DEV_ID_58802_VF:
4401 case BROADCOM_DEV_ID_57500_VF1:
4402 case BROADCOM_DEV_ID_57500_VF2:
4403 case BROADCOM_DEV_ID_58818_VF:
4411 /* Phase 5 device */
4412 static bool bnxt_p5_device(uint16_t device_id)
4414 switch (device_id) {
4415 case BROADCOM_DEV_ID_57508:
4416 case BROADCOM_DEV_ID_57504:
4417 case BROADCOM_DEV_ID_57502:
4418 case BROADCOM_DEV_ID_57508_MF1:
4419 case BROADCOM_DEV_ID_57504_MF1:
4420 case BROADCOM_DEV_ID_57502_MF1:
4421 case BROADCOM_DEV_ID_57508_MF2:
4422 case BROADCOM_DEV_ID_57504_MF2:
4423 case BROADCOM_DEV_ID_57502_MF2:
4424 case BROADCOM_DEV_ID_57500_VF1:
4425 case BROADCOM_DEV_ID_57500_VF2:
4426 case BROADCOM_DEV_ID_58812:
4427 case BROADCOM_DEV_ID_58814:
4428 case BROADCOM_DEV_ID_58818:
4429 case BROADCOM_DEV_ID_58818_VF:
4437 bool bnxt_stratus_device(struct bnxt *bp)
4439 uint16_t device_id = bp->pdev->id.device_id;
4441 switch (device_id) {
4442 case BROADCOM_DEV_ID_STRATUS_NIC:
4443 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4444 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4452 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4454 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4455 struct bnxt *bp = eth_dev->data->dev_private;
4457 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4458 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4459 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4460 if (!bp->bar0 || !bp->doorbell_base) {
4461 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4465 bp->eth_dev = eth_dev;
4471 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4472 struct bnxt_ctx_pg_info *ctx_pg,
4477 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4478 const struct rte_memzone *mz = NULL;
4479 char mz_name[RTE_MEMZONE_NAMESIZE];
4480 rte_iova_t mz_phys_addr;
4481 uint64_t valid_bits = 0;
4488 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4490 rmem->page_size = BNXT_PAGE_SIZE;
4491 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4492 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4493 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4495 valid_bits = PTU_PTE_VALID;
4497 if (rmem->nr_pages > 1) {
4498 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4499 "bnxt_ctx_pg_tbl%s_%x_%d",
4500 suffix, idx, bp->eth_dev->data->port_id);
4501 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4502 mz = rte_memzone_lookup(mz_name);
4504 mz = rte_memzone_reserve_aligned(mz_name,
4508 RTE_MEMZONE_SIZE_HINT_ONLY |
4509 RTE_MEMZONE_IOVA_CONTIG,
4515 memset(mz->addr, 0, mz->len);
4516 mz_phys_addr = mz->iova;
4518 rmem->pg_tbl = mz->addr;
4519 rmem->pg_tbl_map = mz_phys_addr;
4520 rmem->pg_tbl_mz = mz;
4523 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4524 suffix, idx, bp->eth_dev->data->port_id);
4525 mz = rte_memzone_lookup(mz_name);
4527 mz = rte_memzone_reserve_aligned(mz_name,
4531 RTE_MEMZONE_SIZE_HINT_ONLY |
4532 RTE_MEMZONE_IOVA_CONTIG,
4538 memset(mz->addr, 0, mz->len);
4539 mz_phys_addr = mz->iova;
4541 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4542 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4543 rmem->dma_arr[i] = mz_phys_addr + sz;
4545 if (rmem->nr_pages > 1) {
4546 if (i == rmem->nr_pages - 2 &&
4547 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4548 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4549 else if (i == rmem->nr_pages - 1 &&
4550 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4551 valid_bits |= PTU_PTE_LAST;
4553 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4559 if (rmem->vmem_size)
4560 rmem->vmem = (void **)mz->addr;
4561 rmem->dma_arr[0] = mz_phys_addr;
4565 static void bnxt_free_ctx_mem(struct bnxt *bp)
4569 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4572 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4573 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4574 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4575 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4576 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4577 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4578 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4579 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4580 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4581 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4582 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4584 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4585 if (bp->ctx->tqm_mem[i])
4586 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4593 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4595 #define min_t(type, x, y) ({ \
4596 type __min1 = (x); \
4597 type __min2 = (y); \
4598 __min1 < __min2 ? __min1 : __min2; })
4600 #define max_t(type, x, y) ({ \
4601 type __max1 = (x); \
4602 type __max2 = (y); \
4603 __max1 > __max2 ? __max1 : __max2; })
4605 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4607 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4609 struct bnxt_ctx_pg_info *ctx_pg;
4610 struct bnxt_ctx_mem_info *ctx;
4611 uint32_t mem_size, ena, entries;
4612 uint32_t entries_sp, min;
4615 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4617 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4621 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4624 ctx_pg = &ctx->qp_mem;
4625 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4626 if (ctx->qp_entry_size) {
4627 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4628 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4633 ctx_pg = &ctx->srq_mem;
4634 ctx_pg->entries = ctx->srq_max_l2_entries;
4635 if (ctx->srq_entry_size) {
4636 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4637 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4642 ctx_pg = &ctx->cq_mem;
4643 ctx_pg->entries = ctx->cq_max_l2_entries;
4644 if (ctx->cq_entry_size) {
4645 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4646 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4651 ctx_pg = &ctx->vnic_mem;
4652 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4653 ctx->vnic_max_ring_table_entries;
4654 if (ctx->vnic_entry_size) {
4655 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4656 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4661 ctx_pg = &ctx->stat_mem;
4662 ctx_pg->entries = ctx->stat_max_entries;
4663 if (ctx->stat_entry_size) {
4664 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4665 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4670 min = ctx->tqm_min_entries_per_ring;
4672 entries_sp = ctx->qp_max_l2_entries +
4673 ctx->vnic_max_vnic_entries +
4674 2 * ctx->qp_min_qp1_entries + min;
4675 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4677 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4678 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4679 entries = clamp_t(uint32_t, entries, min,
4680 ctx->tqm_max_entries_per_ring);
4681 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4682 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4683 * i > 8 is other ext rings.
4685 ctx_pg = ctx->tqm_mem[i];
4686 ctx_pg->entries = i ? entries : entries_sp;
4687 if (ctx->tqm_entry_size) {
4688 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4689 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4694 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4695 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4697 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4700 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4701 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4704 "Failed to configure context mem: rc = %d\n", rc);
4706 ctx->flags |= BNXT_CTX_FLAG_INITED;
4711 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4713 struct rte_pci_device *pci_dev = bp->pdev;
4714 char mz_name[RTE_MEMZONE_NAMESIZE];
4715 const struct rte_memzone *mz = NULL;
4716 uint32_t total_alloc_len;
4717 rte_iova_t mz_phys_addr;
4719 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4722 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4723 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4724 pci_dev->addr.bus, pci_dev->addr.devid,
4725 pci_dev->addr.function, "rx_port_stats");
4726 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4727 mz = rte_memzone_lookup(mz_name);
4729 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4730 sizeof(struct rx_port_stats_ext) + 512);
4732 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4735 RTE_MEMZONE_SIZE_HINT_ONLY |
4736 RTE_MEMZONE_IOVA_CONTIG);
4740 memset(mz->addr, 0, mz->len);
4741 mz_phys_addr = mz->iova;
4743 bp->rx_mem_zone = (const void *)mz;
4744 bp->hw_rx_port_stats = mz->addr;
4745 bp->hw_rx_port_stats_map = mz_phys_addr;
4747 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4748 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4749 pci_dev->addr.bus, pci_dev->addr.devid,
4750 pci_dev->addr.function, "tx_port_stats");
4751 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4752 mz = rte_memzone_lookup(mz_name);
4754 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4755 sizeof(struct tx_port_stats_ext) + 512);
4757 mz = rte_memzone_reserve(mz_name,
4761 RTE_MEMZONE_SIZE_HINT_ONLY |
4762 RTE_MEMZONE_IOVA_CONTIG);
4766 memset(mz->addr, 0, mz->len);
4767 mz_phys_addr = mz->iova;
4769 bp->tx_mem_zone = (const void *)mz;
4770 bp->hw_tx_port_stats = mz->addr;
4771 bp->hw_tx_port_stats_map = mz_phys_addr;
4772 bp->flags |= BNXT_FLAG_PORT_STATS;
4774 /* Display extended statistics if FW supports it */
4775 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4776 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4777 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4780 bp->hw_rx_port_stats_ext = (void *)
4781 ((uint8_t *)bp->hw_rx_port_stats +
4782 sizeof(struct rx_port_stats));
4783 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4784 sizeof(struct rx_port_stats);
4785 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4787 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4788 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4789 bp->hw_tx_port_stats_ext = (void *)
4790 ((uint8_t *)bp->hw_tx_port_stats +
4791 sizeof(struct tx_port_stats));
4792 bp->hw_tx_port_stats_ext_map =
4793 bp->hw_tx_port_stats_map +
4794 sizeof(struct tx_port_stats);
4795 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4801 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4803 struct bnxt *bp = eth_dev->data->dev_private;
4806 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4807 RTE_ETHER_ADDR_LEN *
4810 if (eth_dev->data->mac_addrs == NULL) {
4811 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4815 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4819 /* Generate a random MAC address, if none was assigned by PF */
4820 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4821 bnxt_eth_hw_addr_random(bp->mac_addr);
4823 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4824 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4825 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4827 rc = bnxt_hwrm_set_mac(bp);
4832 /* Copy the permanent MAC from the FUNC_QCAPS response */
4833 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4838 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4842 /* MAC is already configured in FW */
4843 if (BNXT_HAS_DFLT_MAC_SET(bp))
4846 /* Restore the old MAC configured */
4847 rc = bnxt_hwrm_set_mac(bp);
4849 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4854 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4859 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4861 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4862 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4863 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4864 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4865 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4866 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4870 bnxt_get_svif(uint16_t port_id, bool func_svif,
4871 enum bnxt_ulp_intf_type type)
4873 struct rte_eth_dev *eth_dev;
4876 eth_dev = &rte_eth_devices[port_id];
4877 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4878 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4882 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4885 eth_dev = vfr->parent_dev;
4888 bp = eth_dev->data->dev_private;
4890 return func_svif ? bp->func_svif : bp->port_svif;
4894 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4896 struct rte_eth_dev *eth_dev;
4897 struct bnxt_vnic_info *vnic;
4900 eth_dev = &rte_eth_devices[port];
4901 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4902 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4906 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4907 return vfr->dflt_vnic_id;
4909 eth_dev = vfr->parent_dev;
4912 bp = eth_dev->data->dev_private;
4914 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4916 return vnic->fw_vnic_id;
4920 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4922 struct rte_eth_dev *eth_dev;
4925 eth_dev = &rte_eth_devices[port];
4926 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4927 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4931 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4934 eth_dev = vfr->parent_dev;
4937 bp = eth_dev->data->dev_private;
4942 enum bnxt_ulp_intf_type
4943 bnxt_get_interface_type(uint16_t port)
4945 struct rte_eth_dev *eth_dev;
4948 eth_dev = &rte_eth_devices[port];
4949 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4950 return BNXT_ULP_INTF_TYPE_VF_REP;
4952 bp = eth_dev->data->dev_private;
4954 return BNXT_ULP_INTF_TYPE_PF;
4955 else if (BNXT_VF_IS_TRUSTED(bp))
4956 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4957 else if (BNXT_VF(bp))
4958 return BNXT_ULP_INTF_TYPE_VF;
4960 return BNXT_ULP_INTF_TYPE_INVALID;
4964 bnxt_get_phy_port_id(uint16_t port_id)
4966 struct bnxt_representor *vfr;
4967 struct rte_eth_dev *eth_dev;
4970 eth_dev = &rte_eth_devices[port_id];
4971 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4972 vfr = eth_dev->data->dev_private;
4976 eth_dev = vfr->parent_dev;
4979 bp = eth_dev->data->dev_private;
4981 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4985 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4987 struct rte_eth_dev *eth_dev;
4990 eth_dev = &rte_eth_devices[port_id];
4991 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4992 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4996 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4997 return vfr->fw_fid - 1;
4999 eth_dev = vfr->parent_dev;
5002 bp = eth_dev->data->dev_private;
5004 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5008 bnxt_get_vport(uint16_t port_id)
5010 return (1 << bnxt_get_phy_port_id(port_id));
5013 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5015 struct bnxt_error_recovery_info *info = bp->recovery_info;
5018 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5019 memset(info, 0, sizeof(*info));
5023 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5026 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5029 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5031 bp->recovery_info = info;
5034 static void bnxt_check_fw_status(struct bnxt *bp)
5038 if (!(bp->recovery_info &&
5039 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5042 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5043 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5044 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5048 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5050 struct bnxt_error_recovery_info *info = bp->recovery_info;
5051 uint32_t status_loc;
5054 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5055 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5056 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5057 BNXT_GRCP_WINDOW_2_BASE +
5058 offsetof(struct hcomm_status,
5060 /* If the signature is absent, then FW does not support this feature */
5061 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5062 HCOMM_STATUS_SIGNATURE_VAL)
5066 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5070 bp->recovery_info = info;
5072 memset(info, 0, sizeof(*info));
5075 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5076 BNXT_GRCP_WINDOW_2_BASE +
5077 offsetof(struct hcomm_status,
5080 /* Only pre-map the FW health status GRC register */
5081 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5084 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5085 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5086 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5088 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5089 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5091 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5096 /* This function gets the FW version along with the
5097 * capabilities(MAX and current) of the function, vnic,
5098 * error recovery, phy and other chip related info
5100 static int bnxt_get_config(struct bnxt *bp)
5107 rc = bnxt_map_hcomm_fw_status_reg(bp);
5111 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5113 bnxt_check_fw_status(bp);
5117 rc = bnxt_hwrm_func_reset(bp);
5121 rc = bnxt_hwrm_vnic_qcaps(bp);
5125 rc = bnxt_hwrm_queue_qportcfg(bp);
5129 /* Get the MAX capabilities for this function.
5130 * This function also allocates context memory for TQM rings and
5131 * informs the firmware about this allocated backing store memory.
5133 rc = bnxt_hwrm_func_qcaps(bp);
5137 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5141 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5145 bnxt_hwrm_port_mac_qcfg(bp);
5147 bnxt_hwrm_parent_pf_qcfg(bp);
5149 bnxt_hwrm_port_phy_qcaps(bp);
5151 bnxt_alloc_error_recovery_info(bp);
5152 /* Get the adapter error recovery support info */
5153 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5155 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5157 bnxt_hwrm_port_led_qcaps(bp);
5163 bnxt_init_locks(struct bnxt *bp)
5167 err = pthread_mutex_init(&bp->flow_lock, NULL);
5169 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5173 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5175 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5179 err = pthread_mutex_init(&bp->health_check_lock, NULL);
5181 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5185 err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5187 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5192 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5196 rc = bnxt_get_config(bp);
5200 if (!reconfig_dev) {
5201 rc = bnxt_setup_mac_addr(bp->eth_dev);
5205 rc = bnxt_restore_dflt_mac(bp);
5210 bnxt_config_vf_req_fwd(bp);
5212 rc = bnxt_hwrm_func_driver_register(bp);
5214 PMD_DRV_LOG(ERR, "Failed to register driver");
5219 if (bp->pdev->max_vfs) {
5220 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5222 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5226 rc = bnxt_hwrm_allocate_pf_only(bp);
5229 "Failed to allocate PF resources");
5235 rc = bnxt_alloc_mem(bp, reconfig_dev);
5239 rc = bnxt_setup_int(bp);
5243 rc = bnxt_request_int(bp);
5247 rc = bnxt_init_ctx_mem(bp);
5249 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5257 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5258 const char *value, void *opaque_arg)
5260 struct bnxt *bp = opaque_arg;
5261 unsigned long flow_xstat;
5264 if (!value || !opaque_arg) {
5266 "Invalid parameter passed to flow_xstat devarg.\n");
5270 flow_xstat = strtoul(value, &end, 10);
5271 if (end == NULL || *end != '\0' ||
5272 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5274 "Invalid parameter passed to flow_xstat devarg.\n");
5278 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5280 "Invalid value passed to flow_xstat devarg.\n");
5284 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5285 if (BNXT_FLOW_XSTATS_EN(bp))
5286 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5292 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5293 const char *value, void *opaque_arg)
5295 struct bnxt *bp = opaque_arg;
5296 unsigned long max_num_kflows;
5299 if (!value || !opaque_arg) {
5301 "Invalid parameter passed to max_num_kflows devarg.\n");
5305 max_num_kflows = strtoul(value, &end, 10);
5306 if (end == NULL || *end != '\0' ||
5307 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5309 "Invalid parameter passed to max_num_kflows devarg.\n");
5313 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5315 "Invalid value passed to max_num_kflows devarg.\n");
5319 bp->max_num_kflows = max_num_kflows;
5320 if (bp->max_num_kflows)
5321 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5328 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5329 const char *value, void *opaque_arg)
5331 struct bnxt_representor *vfr_bp = opaque_arg;
5332 unsigned long rep_is_pf;
5335 if (!value || !opaque_arg) {
5337 "Invalid parameter passed to rep_is_pf devargs.\n");
5341 rep_is_pf = strtoul(value, &end, 10);
5342 if (end == NULL || *end != '\0' ||
5343 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5345 "Invalid parameter passed to rep_is_pf devargs.\n");
5349 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5351 "Invalid value passed to rep_is_pf devargs.\n");
5355 vfr_bp->flags |= rep_is_pf;
5356 if (BNXT_REP_PF(vfr_bp))
5357 PMD_DRV_LOG(INFO, "PF representor\n");
5359 PMD_DRV_LOG(INFO, "VF representor\n");
5365 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5366 const char *value, void *opaque_arg)
5368 struct bnxt_representor *vfr_bp = opaque_arg;
5369 unsigned long rep_based_pf;
5372 if (!value || !opaque_arg) {
5374 "Invalid parameter passed to rep_based_pf "
5379 rep_based_pf = strtoul(value, &end, 10);
5380 if (end == NULL || *end != '\0' ||
5381 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5383 "Invalid parameter passed to rep_based_pf "
5388 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5390 "Invalid value passed to rep_based_pf devargs.\n");
5394 vfr_bp->rep_based_pf = rep_based_pf;
5395 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5397 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5403 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5404 const char *value, void *opaque_arg)
5406 struct bnxt_representor *vfr_bp = opaque_arg;
5407 unsigned long rep_q_r2f;
5410 if (!value || !opaque_arg) {
5412 "Invalid parameter passed to rep_q_r2f "
5417 rep_q_r2f = strtoul(value, &end, 10);
5418 if (end == NULL || *end != '\0' ||
5419 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5421 "Invalid parameter passed to rep_q_r2f "
5426 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5428 "Invalid value passed to rep_q_r2f devargs.\n");
5432 vfr_bp->rep_q_r2f = rep_q_r2f;
5433 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5434 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5440 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5441 const char *value, void *opaque_arg)
5443 struct bnxt_representor *vfr_bp = opaque_arg;
5444 unsigned long rep_q_f2r;
5447 if (!value || !opaque_arg) {
5449 "Invalid parameter passed to rep_q_f2r "
5454 rep_q_f2r = strtoul(value, &end, 10);
5455 if (end == NULL || *end != '\0' ||
5456 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5458 "Invalid parameter passed to rep_q_f2r "
5463 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5465 "Invalid value passed to rep_q_f2r devargs.\n");
5469 vfr_bp->rep_q_f2r = rep_q_f2r;
5470 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5471 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5477 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5478 const char *value, void *opaque_arg)
5480 struct bnxt_representor *vfr_bp = opaque_arg;
5481 unsigned long rep_fc_r2f;
5484 if (!value || !opaque_arg) {
5486 "Invalid parameter passed to rep_fc_r2f "
5491 rep_fc_r2f = strtoul(value, &end, 10);
5492 if (end == NULL || *end != '\0' ||
5493 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5495 "Invalid parameter passed to rep_fc_r2f "
5500 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5502 "Invalid value passed to rep_fc_r2f devargs.\n");
5506 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5507 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5508 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5514 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5515 const char *value, void *opaque_arg)
5517 struct bnxt_representor *vfr_bp = opaque_arg;
5518 unsigned long rep_fc_f2r;
5521 if (!value || !opaque_arg) {
5523 "Invalid parameter passed to rep_fc_f2r "
5528 rep_fc_f2r = strtoul(value, &end, 10);
5529 if (end == NULL || *end != '\0' ||
5530 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5532 "Invalid parameter passed to rep_fc_f2r "
5537 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5539 "Invalid value passed to rep_fc_f2r devargs.\n");
5543 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5544 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5545 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5551 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5553 struct rte_kvargs *kvlist;
5556 if (devargs == NULL)
5559 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5564 * Handler for "flow_xstat" devarg.
5565 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5567 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5568 bnxt_parse_devarg_flow_xstat, bp);
5573 * Handler for "max_num_kflows" devarg.
5574 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5576 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5577 bnxt_parse_devarg_max_num_kflows, bp);
5582 rte_kvargs_free(kvlist);
5586 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5590 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5591 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5594 "Failed to alloc switch domain: %d\n", rc);
5597 "Switch domain allocated %d\n",
5598 bp->switch_domain_id);
5604 /* Allocate and initialize various fields in bnxt struct that
5605 * need to be allocated/destroyed only once in the lifetime of the driver
5607 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5609 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5610 struct bnxt *bp = eth_dev->data->dev_private;
5613 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5615 if (bnxt_vf_pciid(pci_dev->id.device_id))
5616 bp->flags |= BNXT_FLAG_VF;
5618 if (bnxt_p5_device(pci_dev->id.device_id))
5619 bp->flags |= BNXT_FLAG_CHIP_P5;
5621 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5622 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5623 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5624 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5625 bp->flags |= BNXT_FLAG_STINGRAY;
5627 if (BNXT_TRUFLOW_EN(bp)) {
5628 /* extra mbuf field is required to store CFA code from mark */
5629 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5630 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5631 .size = sizeof(bnxt_cfa_code_dynfield_t),
5632 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5634 bnxt_cfa_code_dynfield_offset =
5635 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5636 if (bnxt_cfa_code_dynfield_offset < 0) {
5638 "Failed to register mbuf field for TruFlow mark\n");
5643 rc = bnxt_map_pci_bars(eth_dev);
5646 "Failed to initialize board rc: %x\n", rc);
5650 rc = bnxt_alloc_pf_info(bp);
5654 rc = bnxt_alloc_link_info(bp);
5658 rc = bnxt_alloc_parent_info(bp);
5662 rc = bnxt_alloc_hwrm_resources(bp);
5665 "Failed to allocate response buffer rc: %x\n", rc);
5668 rc = bnxt_alloc_leds_info(bp);
5672 rc = bnxt_alloc_cos_queues(bp);
5676 rc = bnxt_init_locks(bp);
5680 rc = bnxt_alloc_switch_domain(bp);
5688 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5690 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5691 static int version_printed;
5695 if (version_printed++ == 0)
5696 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5698 eth_dev->dev_ops = &bnxt_dev_ops;
5699 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5700 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5701 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5702 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5703 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5706 * For secondary processes, we don't initialise any further
5707 * as primary has already done this work.
5709 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5712 rte_eth_copy_pci_info(eth_dev, pci_dev);
5713 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5715 bp = eth_dev->data->dev_private;
5717 /* Parse dev arguments passed on when starting the DPDK application. */
5718 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5722 rc = bnxt_drv_init(eth_dev);
5726 rc = bnxt_init_resources(bp, false);
5730 rc = bnxt_alloc_stats_mem(bp);
5735 "Found %s device at mem %" PRIX64 ", node addr %pM\n",
5737 pci_dev->mem_resource[0].phys_addr,
5738 pci_dev->mem_resource[0].addr);
5743 bnxt_dev_uninit(eth_dev);
5748 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5757 ctx->dma = RTE_BAD_IOVA;
5758 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5761 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5763 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5764 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5765 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5766 bp->flow_stat->max_fc,
5769 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5770 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5771 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5772 bp->flow_stat->max_fc,
5775 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5776 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5777 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5779 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5780 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5781 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5783 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5784 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5785 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5787 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5788 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5789 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5792 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5794 bnxt_unregister_fc_ctx_mem(bp);
5796 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5797 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5798 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5799 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5802 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5804 if (BNXT_FLOW_XSTATS_EN(bp))
5805 bnxt_uninit_fc_ctx_mem(bp);
5809 bnxt_free_error_recovery_info(struct bnxt *bp)
5811 rte_free(bp->recovery_info);
5812 bp->recovery_info = NULL;
5813 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5817 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5822 bnxt_free_mem(bp, reconfig_dev);
5824 bnxt_hwrm_func_buf_unrgtr(bp);
5825 if (bp->pf != NULL) {
5826 rte_free(bp->pf->vf_req_buf);
5827 bp->pf->vf_req_buf = NULL;
5830 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5831 bp->flags &= ~BNXT_FLAG_REGISTERED;
5832 bnxt_free_ctx_mem(bp);
5833 if (!reconfig_dev) {
5834 bnxt_free_hwrm_resources(bp);
5835 bnxt_free_error_recovery_info(bp);
5838 bnxt_uninit_ctx_mem(bp);
5840 bnxt_free_flow_stats_info(bp);
5841 if (bp->rep_info != NULL)
5842 bnxt_free_switch_domain(bp);
5843 bnxt_free_rep_info(bp);
5844 rte_free(bp->ptp_cfg);
5850 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5852 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5855 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5857 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5858 bnxt_dev_close_op(eth_dev);
5863 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5865 struct bnxt *bp = eth_dev->data->dev_private;
5866 struct rte_eth_dev *vf_rep_eth_dev;
5872 for (i = 0; i < bp->num_reps; i++) {
5873 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5874 if (!vf_rep_eth_dev)
5876 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5877 vf_rep_eth_dev->data->port_id);
5878 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5880 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5881 eth_dev->data->port_id);
5882 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5887 static void bnxt_free_rep_info(struct bnxt *bp)
5889 rte_free(bp->rep_info);
5890 bp->rep_info = NULL;
5891 rte_free(bp->cfa_code_map);
5892 bp->cfa_code_map = NULL;
5895 static int bnxt_init_rep_info(struct bnxt *bp)
5902 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5903 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5905 if (!bp->rep_info) {
5906 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5909 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5910 sizeof(*bp->cfa_code_map) *
5911 BNXT_MAX_CFA_CODE, 0);
5912 if (!bp->cfa_code_map) {
5913 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5914 bnxt_free_rep_info(bp);
5918 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5919 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5921 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5923 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5924 bnxt_free_rep_info(bp);
5928 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5930 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5931 bnxt_free_rep_info(bp);
5938 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5939 struct rte_eth_devargs *eth_da,
5940 struct rte_eth_dev *backing_eth_dev,
5941 const char *dev_args)
5943 struct rte_eth_dev *vf_rep_eth_dev;
5944 char name[RTE_ETH_NAME_MAX_LEN];
5945 struct bnxt *backing_bp;
5948 struct rte_kvargs *kvlist = NULL;
5950 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
5952 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
5953 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
5957 num_rep = eth_da->nb_representor_ports;
5958 if (num_rep > BNXT_MAX_VF_REPS) {
5959 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5960 num_rep, BNXT_MAX_VF_REPS);
5964 if (num_rep >= RTE_MAX_ETHPORTS) {
5966 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5967 num_rep, RTE_MAX_ETHPORTS);
5971 backing_bp = backing_eth_dev->data->dev_private;
5973 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5975 "Not a PF or trusted VF. No Representor support\n");
5976 /* Returning an error is not an option.
5977 * Applications are not handling this correctly
5982 if (bnxt_init_rep_info(backing_bp))
5985 for (i = 0; i < num_rep; i++) {
5986 struct bnxt_representor representor = {
5987 .vf_id = eth_da->representor_ports[i],
5988 .switch_domain_id = backing_bp->switch_domain_id,
5989 .parent_dev = backing_eth_dev
5992 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5993 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5994 representor.vf_id, BNXT_MAX_VF_REPS);
5998 /* representor port net_bdf_port */
5999 snprintf(name, sizeof(name), "net_%s_representor_%d",
6000 pci_dev->device.name, eth_da->representor_ports[i]);
6002 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6005 * Handler for "rep_is_pf" devarg.
6006 * Invoked as for ex: "-a 000:00:0d.0,
6007 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6009 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6010 bnxt_parse_devarg_rep_is_pf,
6011 (void *)&representor);
6017 * Handler for "rep_based_pf" devarg.
6018 * Invoked as for ex: "-a 000:00:0d.0,
6019 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6021 ret = rte_kvargs_process(kvlist,
6022 BNXT_DEVARG_REP_BASED_PF,
6023 bnxt_parse_devarg_rep_based_pf,
6024 (void *)&representor);
6030 * Handler for "rep_based_pf" devarg.
6031 * Invoked as for ex: "-a 000:00:0d.0,
6032 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6034 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6035 bnxt_parse_devarg_rep_q_r2f,
6036 (void *)&representor);
6042 * Handler for "rep_based_pf" devarg.
6043 * Invoked as for ex: "-a 000:00:0d.0,
6044 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6046 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6047 bnxt_parse_devarg_rep_q_f2r,
6048 (void *)&representor);
6054 * Handler for "rep_based_pf" devarg.
6055 * Invoked as for ex: "-a 000:00:0d.0,
6056 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6058 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6059 bnxt_parse_devarg_rep_fc_r2f,
6060 (void *)&representor);
6066 * Handler for "rep_based_pf" devarg.
6067 * Invoked as for ex: "-a 000:00:0d.0,
6068 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6070 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6071 bnxt_parse_devarg_rep_fc_f2r,
6072 (void *)&representor);
6079 ret = rte_eth_dev_create(&pci_dev->device, name,
6080 sizeof(struct bnxt_representor),
6082 bnxt_representor_init,
6085 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6086 "representor %s.", name);
6090 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6091 if (!vf_rep_eth_dev) {
6092 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6093 " for VF-Rep: %s.", name);
6098 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6099 backing_eth_dev->data->port_id);
6100 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6102 backing_bp->num_reps++;
6106 rte_kvargs_free(kvlist);
6110 /* If num_rep > 1, then rollback already created
6111 * ports, since we'll be failing the probe anyway
6114 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6116 rte_kvargs_free(kvlist);
6121 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6122 struct rte_pci_device *pci_dev)
6124 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6125 struct rte_eth_dev *backing_eth_dev;
6129 if (pci_dev->device.devargs) {
6130 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6136 num_rep = eth_da.nb_representor_ports;
6137 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6140 /* We could come here after first level of probe is already invoked
6141 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6142 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6144 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6145 if (backing_eth_dev == NULL) {
6146 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6147 sizeof(struct bnxt),
6148 eth_dev_pci_specific_init, pci_dev,
6149 bnxt_dev_init, NULL);
6151 if (ret || !num_rep)
6154 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6156 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6157 backing_eth_dev->data->port_id);
6162 /* probe representor ports now */
6163 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
6164 pci_dev->device.devargs->args);
6169 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6171 struct rte_eth_dev *eth_dev;
6173 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6175 return 0; /* Invoked typically only by OVS-DPDK, by the
6176 * time it comes here the eth_dev is already
6177 * deleted by rte_eth_dev_close(), so returning
6178 * +ve value will at least help in proper cleanup
6181 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6182 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6183 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6184 return rte_eth_dev_destroy(eth_dev,
6185 bnxt_representor_uninit);
6187 return rte_eth_dev_destroy(eth_dev,
6190 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6194 static struct rte_pci_driver bnxt_rte_pmd = {
6195 .id_table = bnxt_pci_id_map,
6196 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6197 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6200 .probe = bnxt_pci_probe,
6201 .remove = bnxt_pci_remove,
6205 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6207 if (strcmp(dev->device->driver->name, drv->driver.name))
6213 bool is_bnxt_supported(struct rte_eth_dev *dev)
6215 return is_device_supported(dev, &bnxt_rte_pmd);
6218 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6219 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6220 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6221 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");