1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
97 { .vendor_id = 0, /* sentinel */ },
100 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
101 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
102 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
103 #define BNXT_DEVARG_REPRESENTOR "representor"
104 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
105 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
106 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
107 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
108 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
109 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
111 static const char *const bnxt_dev_args[] = {
112 BNXT_DEVARG_REPRESENTOR,
114 BNXT_DEVARG_FLOW_XSTAT,
115 BNXT_DEVARG_MAX_NUM_KFLOWS,
116 BNXT_DEVARG_REP_BASED_PF,
117 BNXT_DEVARG_REP_IS_PF,
118 BNXT_DEVARG_REP_Q_R2F,
119 BNXT_DEVARG_REP_Q_F2R,
120 BNXT_DEVARG_REP_FC_R2F,
121 BNXT_DEVARG_REP_FC_F2R,
126 * truflow == false to disable the feature
127 * truflow == true to enable the feature
129 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
132 * flow_xstat == false to disable the feature
133 * flow_xstat == true to enable the feature
135 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
138 * rep_is_pf == false to indicate VF representor
139 * rep_is_pf == true to indicate PF representor
141 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
144 * rep_based_pf == Physical index of the PF
146 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
148 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
150 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
153 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
155 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
158 * rep_fc_r2f == Flow control for the representor to endpoint direction
160 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
163 * rep_fc_f2r == Flow control for the endpoint to representor direction
165 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
167 int bnxt_cfa_code_dynfield_offset = -1;
170 * max_num_kflows must be >= 32
171 * and must be a power-of-2 supported value
172 * return: 1 -> invalid
175 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
177 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
182 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
183 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
184 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
185 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
186 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
187 static int bnxt_restore_vlan_filters(struct bnxt *bp);
188 static void bnxt_dev_recover(void *arg);
189 static void bnxt_free_error_recovery_info(struct bnxt *bp);
190 static void bnxt_free_rep_info(struct bnxt *bp);
192 int is_bnxt_in_error(struct bnxt *bp)
194 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
196 if (bp->flags & BNXT_FLAG_FW_RESET)
202 /***********************/
205 * High level utility functions
208 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
210 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
211 BNXT_RSS_TBL_SIZE_P5);
213 if (!BNXT_CHIP_P5(bp))
216 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
217 BNXT_RSS_ENTRIES_PER_CTX_P5) /
218 BNXT_RSS_ENTRIES_PER_CTX_P5;
221 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
223 if (!BNXT_CHIP_P5(bp))
224 return HW_HASH_INDEX_SIZE;
226 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
229 static void bnxt_free_parent_info(struct bnxt *bp)
231 rte_free(bp->parent);
234 static void bnxt_free_pf_info(struct bnxt *bp)
239 static void bnxt_free_link_info(struct bnxt *bp)
241 rte_free(bp->link_info);
244 static void bnxt_free_leds_info(struct bnxt *bp)
253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
255 rte_free(bp->flow_stat);
256 bp->flow_stat = NULL;
259 static void bnxt_free_cos_queues(struct bnxt *bp)
261 rte_free(bp->rx_cos_queue);
262 rte_free(bp->tx_cos_queue);
265 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
267 bnxt_free_filter_mem(bp);
268 bnxt_free_vnic_attributes(bp);
269 bnxt_free_vnic_mem(bp);
271 /* tx/rx rings are configured as part of *_queue_setup callbacks.
272 * If the number of rings change across fw update,
273 * we don't have much choice except to warn the user.
277 bnxt_free_tx_rings(bp);
278 bnxt_free_rx_rings(bp);
280 bnxt_free_async_cp_ring(bp);
281 bnxt_free_rxtx_nq_ring(bp);
283 rte_free(bp->grp_info);
287 static int bnxt_alloc_parent_info(struct bnxt *bp)
289 bp->parent = rte_zmalloc("bnxt_parent_info",
290 sizeof(struct bnxt_parent_info), 0);
291 if (bp->parent == NULL)
297 static int bnxt_alloc_pf_info(struct bnxt *bp)
299 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
306 static int bnxt_alloc_link_info(struct bnxt *bp)
309 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
310 if (bp->link_info == NULL)
316 static int bnxt_alloc_leds_info(struct bnxt *bp)
321 bp->leds = rte_zmalloc("bnxt_leds",
322 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
324 if (bp->leds == NULL)
330 static int bnxt_alloc_cos_queues(struct bnxt *bp)
333 rte_zmalloc("bnxt_rx_cosq",
334 BNXT_COS_QUEUE_COUNT *
335 sizeof(struct bnxt_cos_queue_info),
337 if (bp->rx_cos_queue == NULL)
341 rte_zmalloc("bnxt_tx_cosq",
342 BNXT_COS_QUEUE_COUNT *
343 sizeof(struct bnxt_cos_queue_info),
345 if (bp->tx_cos_queue == NULL)
351 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
353 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
354 sizeof(struct bnxt_flow_stat_info), 0);
355 if (bp->flow_stat == NULL)
361 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
365 rc = bnxt_alloc_ring_grps(bp);
369 rc = bnxt_alloc_async_ring_struct(bp);
373 rc = bnxt_alloc_vnic_mem(bp);
377 rc = bnxt_alloc_vnic_attributes(bp);
381 rc = bnxt_alloc_filter_mem(bp);
385 rc = bnxt_alloc_async_cp_ring(bp);
389 rc = bnxt_alloc_rxtx_nq_ring(bp);
393 if (BNXT_FLOW_XSTATS_EN(bp)) {
394 rc = bnxt_alloc_flow_stats_info(bp);
402 bnxt_free_mem(bp, reconfig);
406 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
408 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
409 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
410 uint64_t rx_offloads = dev_conf->rxmode.offloads;
411 struct bnxt_rx_queue *rxq;
415 rc = bnxt_vnic_grp_alloc(bp, vnic);
419 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
420 vnic_id, vnic, vnic->fw_grp_ids);
422 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
426 /* Alloc RSS context only if RSS mode is enabled */
427 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
428 int j, nr_ctxs = bnxt_rss_ctxts(bp);
430 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
431 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
432 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
434 "Only queues 0-%d will be in RSS table\n",
435 BNXT_RSS_TBL_SIZE_P5 - 1);
439 for (j = 0; j < nr_ctxs; j++) {
440 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
446 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
450 vnic->num_lb_ctxts = nr_ctxs;
454 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
455 * setting is not available at this time, it will not be
456 * configured correctly in the CFA.
458 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
459 vnic->vlan_strip = true;
461 vnic->vlan_strip = false;
463 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
467 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
471 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
472 rxq = bp->eth_dev->data->rx_queues[j];
475 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
476 j, rxq->vnic, rxq->vnic->fw_grp_ids);
478 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
479 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
481 vnic->rx_queue_cnt++;
484 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
486 rc = bnxt_vnic_rss_configure(bp, vnic);
490 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
492 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
493 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
495 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
499 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
504 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
508 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
509 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
514 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
515 " rx_fc_in_tbl.ctx_id = %d\n",
516 bp->flow_stat->rx_fc_in_tbl.va,
517 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
518 bp->flow_stat->rx_fc_in_tbl.ctx_id);
520 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
521 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
526 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
527 " rx_fc_out_tbl.ctx_id = %d\n",
528 bp->flow_stat->rx_fc_out_tbl.va,
529 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
530 bp->flow_stat->rx_fc_out_tbl.ctx_id);
532 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
533 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
538 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
539 " tx_fc_in_tbl.ctx_id = %d\n",
540 bp->flow_stat->tx_fc_in_tbl.va,
541 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
542 bp->flow_stat->tx_fc_in_tbl.ctx_id);
544 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
545 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
550 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
551 " tx_fc_out_tbl.ctx_id = %d\n",
552 bp->flow_stat->tx_fc_out_tbl.va,
553 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
554 bp->flow_stat->tx_fc_out_tbl.ctx_id);
556 memset(bp->flow_stat->rx_fc_out_tbl.va,
558 bp->flow_stat->rx_fc_out_tbl.size);
559 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
560 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
561 bp->flow_stat->rx_fc_out_tbl.ctx_id,
562 bp->flow_stat->max_fc,
567 memset(bp->flow_stat->tx_fc_out_tbl.va,
569 bp->flow_stat->tx_fc_out_tbl.size);
570 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
571 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
572 bp->flow_stat->tx_fc_out_tbl.ctx_id,
573 bp->flow_stat->max_fc,
579 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
580 struct bnxt_ctx_mem_buf_info *ctx)
585 ctx->va = rte_zmalloc(type, size, 0);
588 rte_mem_lock_page(ctx->va);
590 ctx->dma = rte_mem_virt2iova(ctx->va);
591 if (ctx->dma == RTE_BAD_IOVA)
597 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
599 struct rte_pci_device *pdev = bp->pdev;
600 char type[RTE_MEMZONE_NAMESIZE];
604 max_fc = bp->flow_stat->max_fc;
606 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
607 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
608 /* 4 bytes for each counter-id */
609 rc = bnxt_alloc_ctx_mem_buf(type,
611 &bp->flow_stat->rx_fc_in_tbl);
615 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
616 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
617 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
618 rc = bnxt_alloc_ctx_mem_buf(type,
620 &bp->flow_stat->rx_fc_out_tbl);
624 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
625 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
626 /* 4 bytes for each counter-id */
627 rc = bnxt_alloc_ctx_mem_buf(type,
629 &bp->flow_stat->tx_fc_in_tbl);
633 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
634 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
635 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
636 rc = bnxt_alloc_ctx_mem_buf(type,
638 &bp->flow_stat->tx_fc_out_tbl);
642 rc = bnxt_register_fc_ctx_mem(bp);
647 static int bnxt_init_ctx_mem(struct bnxt *bp)
651 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
652 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
653 !BNXT_FLOW_XSTATS_EN(bp))
656 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
660 rc = bnxt_init_fc_ctx_mem(bp);
665 static int bnxt_update_phy_setting(struct bnxt *bp)
667 struct rte_eth_link new;
670 rc = bnxt_get_hwrm_link_config(bp, &new);
672 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
677 * On BCM957508-N2100 adapters, FW will not allow any user other
678 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
679 * always returns link up. Force phy update always in that case.
681 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
682 rc = bnxt_set_hwrm_link_config(bp, true);
684 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
692 static int bnxt_init_chip(struct bnxt *bp)
694 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
695 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
696 uint32_t intr_vector = 0;
697 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
698 uint32_t vec = BNXT_MISC_VEC_ID;
702 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
703 bp->eth_dev->data->dev_conf.rxmode.offloads |=
704 DEV_RX_OFFLOAD_JUMBO_FRAME;
705 bp->flags |= BNXT_FLAG_JUMBO;
707 bp->eth_dev->data->dev_conf.rxmode.offloads &=
708 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
709 bp->flags &= ~BNXT_FLAG_JUMBO;
712 /* THOR does not support ring groups.
713 * But we will use the array to save RSS context IDs.
715 if (BNXT_CHIP_P5(bp))
716 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
718 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
720 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
724 rc = bnxt_alloc_hwrm_rings(bp);
726 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
730 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
732 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
736 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
739 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
740 if (bp->rx_cos_queue[i].id != 0xff) {
741 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
745 "Num pools more than FW profile\n");
749 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
755 rc = bnxt_mq_rx_configure(bp);
757 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
761 /* VNIC configuration */
762 for (i = 0; i < bp->nr_vnics; i++) {
763 rc = bnxt_setup_one_vnic(bp, i);
768 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
771 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
775 /* check and configure queue intr-vector mapping */
776 if ((rte_intr_cap_multiple(intr_handle) ||
777 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
778 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
779 intr_vector = bp->eth_dev->data->nb_rx_queues;
780 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
781 if (intr_vector > bp->rx_cp_nr_rings) {
782 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
786 rc = rte_intr_efd_enable(intr_handle, intr_vector);
791 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
792 intr_handle->intr_vec =
793 rte_zmalloc("intr_vec",
794 bp->eth_dev->data->nb_rx_queues *
796 if (intr_handle->intr_vec == NULL) {
797 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
798 " intr_vec", bp->eth_dev->data->nb_rx_queues);
802 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
803 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
804 intr_handle->intr_vec, intr_handle->nb_efd,
805 intr_handle->max_intr);
806 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
808 intr_handle->intr_vec[queue_id] =
809 vec + BNXT_RX_VEC_START;
810 if (vec < base + intr_handle->nb_efd - 1)
815 /* enable uio/vfio intr/eventfd mapping */
816 rc = rte_intr_enable(intr_handle);
817 #ifndef RTE_EXEC_ENV_FREEBSD
818 /* In FreeBSD OS, nic_uio driver does not support interrupts */
823 rc = bnxt_update_phy_setting(bp);
827 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
829 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
834 rte_free(intr_handle->intr_vec);
836 rte_intr_efd_disable(intr_handle);
838 /* Some of the error status returned by FW may not be from errno.h */
845 static int bnxt_shutdown_nic(struct bnxt *bp)
847 bnxt_free_all_hwrm_resources(bp);
848 bnxt_free_all_filters(bp);
849 bnxt_free_all_vnics(bp);
854 * Device configuration and status function
857 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
859 uint32_t link_speed = bp->link_info->support_speeds;
860 uint32_t speed_capa = 0;
862 /* If PAM4 is configured, use PAM4 supported speed */
863 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
864 link_speed = bp->link_info->support_pam4_speeds;
866 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
867 speed_capa |= ETH_LINK_SPEED_100M;
868 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
869 speed_capa |= ETH_LINK_SPEED_100M_HD;
870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
871 speed_capa |= ETH_LINK_SPEED_1G;
872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
873 speed_capa |= ETH_LINK_SPEED_2_5G;
874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
875 speed_capa |= ETH_LINK_SPEED_10G;
876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
877 speed_capa |= ETH_LINK_SPEED_20G;
878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
879 speed_capa |= ETH_LINK_SPEED_25G;
880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
881 speed_capa |= ETH_LINK_SPEED_40G;
882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
883 speed_capa |= ETH_LINK_SPEED_50G;
884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
885 speed_capa |= ETH_LINK_SPEED_100G;
886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
887 speed_capa |= ETH_LINK_SPEED_50G;
888 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
889 speed_capa |= ETH_LINK_SPEED_100G;
890 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
891 speed_capa |= ETH_LINK_SPEED_200G;
893 if (bp->link_info->auto_mode ==
894 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
895 speed_capa |= ETH_LINK_SPEED_FIXED;
897 speed_capa |= ETH_LINK_SPEED_AUTONEG;
902 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
903 struct rte_eth_dev_info *dev_info)
905 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
906 struct bnxt *bp = eth_dev->data->dev_private;
907 uint16_t max_vnics, i, j, vpool, vrxq;
908 unsigned int max_rx_rings;
911 rc = is_bnxt_in_error(bp);
916 dev_info->max_mac_addrs = bp->max_l2_ctx;
917 dev_info->max_hash_mac_addrs = 0;
919 /* PF/VF specifics */
921 dev_info->max_vfs = pdev->max_vfs;
923 max_rx_rings = bnxt_max_rings(bp);
924 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
925 dev_info->max_rx_queues = max_rx_rings;
926 dev_info->max_tx_queues = max_rx_rings;
927 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
928 dev_info->hash_key_size = 40;
929 max_vnics = bp->max_vnics;
932 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
933 dev_info->max_mtu = BNXT_MAX_MTU;
935 /* Fast path specifics */
936 dev_info->min_rx_bufsize = 1;
937 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
939 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
940 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
941 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
942 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
943 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
944 dev_info->tx_queue_offload_capa;
945 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
947 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
950 dev_info->default_rxconf = (struct rte_eth_rxconf) {
956 .rx_free_thresh = 32,
957 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
960 dev_info->default_txconf = (struct rte_eth_txconf) {
966 .tx_free_thresh = 32,
969 eth_dev->data->dev_conf.intr_conf.lsc = 1;
971 eth_dev->data->dev_conf.intr_conf.rxq = 1;
972 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
973 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
974 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
975 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
977 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
978 dev_info->switch_info.name = eth_dev->device->name;
979 dev_info->switch_info.domain_id = bp->switch_domain_id;
980 dev_info->switch_info.port_id =
981 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
982 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
988 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
989 * need further investigation.
993 vpool = 64; /* ETH_64_POOLS */
994 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
995 for (i = 0; i < 4; vpool >>= 1, i++) {
996 if (max_vnics > vpool) {
997 for (j = 0; j < 5; vrxq >>= 1, j++) {
998 if (dev_info->max_rx_queues > vrxq) {
1004 /* Not enough resources to support VMDq */
1008 /* Not enough resources to support VMDq */
1012 dev_info->max_vmdq_pools = vpool;
1013 dev_info->vmdq_queue_num = vrxq;
1015 dev_info->vmdq_pool_base = 0;
1016 dev_info->vmdq_queue_base = 0;
1021 /* Configure the device based on the configuration provided */
1022 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1024 struct bnxt *bp = eth_dev->data->dev_private;
1025 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1028 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1029 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1030 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1031 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1033 rc = is_bnxt_in_error(bp);
1037 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1038 rc = bnxt_hwrm_check_vf_rings(bp);
1040 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1044 /* If a resource has already been allocated - in this case
1045 * it is the async completion ring, free it. Reallocate it after
1046 * resource reservation. This will ensure the resource counts
1047 * are calculated correctly.
1050 pthread_mutex_lock(&bp->def_cp_lock);
1052 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1053 bnxt_disable_int(bp);
1054 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1057 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1059 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1060 pthread_mutex_unlock(&bp->def_cp_lock);
1064 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1065 rc = bnxt_alloc_async_cp_ring(bp);
1067 pthread_mutex_unlock(&bp->def_cp_lock);
1070 bnxt_enable_int(bp);
1073 pthread_mutex_unlock(&bp->def_cp_lock);
1076 /* Inherit new configurations */
1077 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1078 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1079 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1080 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1081 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1083 goto resource_error;
1085 if (BNXT_HAS_RING_GRPS(bp) &&
1086 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1087 goto resource_error;
1089 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1090 bp->max_vnics < eth_dev->data->nb_rx_queues)
1091 goto resource_error;
1093 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1094 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1096 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1097 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1098 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1100 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1101 eth_dev->data->mtu =
1102 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1103 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1105 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1111 "Insufficient resources to support requested config\n");
1113 "Num Queues Requested: Tx %d, Rx %d\n",
1114 eth_dev->data->nb_tx_queues,
1115 eth_dev->data->nb_rx_queues);
1117 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1118 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1119 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1123 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1125 struct rte_eth_link *link = ð_dev->data->dev_link;
1127 if (link->link_status)
1128 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1129 eth_dev->data->port_id,
1130 (uint32_t)link->link_speed,
1131 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1132 ("full-duplex") : ("half-duplex\n"));
1134 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1135 eth_dev->data->port_id);
1139 * Determine whether the current configuration requires support for scattered
1140 * receive; return 1 if scattered receive is required and 0 if not.
1142 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1147 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1150 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1151 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1153 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1154 RTE_PKTMBUF_HEADROOM);
1155 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1161 static eth_rx_burst_t
1162 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1164 struct bnxt *bp = eth_dev->data->dev_private;
1166 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1167 #ifndef RTE_LIBRTE_IEEE1588
1169 * Vector mode receive can be enabled only if scatter rx is not
1170 * in use and rx offloads are limited to VLAN stripping and
1173 if (!eth_dev->data->scattered_rx &&
1174 !(eth_dev->data->dev_conf.rxmode.offloads &
1175 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1176 DEV_RX_OFFLOAD_KEEP_CRC |
1177 DEV_RX_OFFLOAD_JUMBO_FRAME |
1178 DEV_RX_OFFLOAD_IPV4_CKSUM |
1179 DEV_RX_OFFLOAD_UDP_CKSUM |
1180 DEV_RX_OFFLOAD_TCP_CKSUM |
1181 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1182 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1183 DEV_RX_OFFLOAD_RSS_HASH |
1184 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1185 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1186 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1187 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1188 eth_dev->data->port_id);
1189 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1190 return bnxt_recv_pkts_vec;
1192 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1193 eth_dev->data->port_id);
1195 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1196 eth_dev->data->port_id,
1197 eth_dev->data->scattered_rx,
1198 eth_dev->data->dev_conf.rxmode.offloads);
1201 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1202 return bnxt_recv_pkts;
1205 static eth_tx_burst_t
1206 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1208 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1209 #ifndef RTE_LIBRTE_IEEE1588
1210 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1211 struct bnxt *bp = eth_dev->data->dev_private;
1214 * Vector mode transmit can be enabled only if not using scatter rx
1217 if (!eth_dev->data->scattered_rx &&
1218 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1219 !BNXT_TRUFLOW_EN(bp) &&
1220 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1221 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1222 eth_dev->data->port_id);
1223 return bnxt_xmit_pkts_vec;
1225 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1226 eth_dev->data->port_id);
1228 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1229 eth_dev->data->port_id,
1230 eth_dev->data->scattered_rx,
1234 return bnxt_xmit_pkts;
1237 static int bnxt_handle_if_change_status(struct bnxt *bp)
1241 /* Since fw has undergone a reset and lost all contexts,
1242 * set fatal flag to not issue hwrm during cleanup
1244 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1245 bnxt_uninit_resources(bp, true);
1247 /* clear fatal flag so that re-init happens */
1248 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1249 rc = bnxt_init_resources(bp, true);
1251 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1256 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1258 struct bnxt *bp = eth_dev->data->dev_private;
1259 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1261 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1263 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1264 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1268 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1270 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1271 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1274 rc = bnxt_hwrm_if_change(bp, true);
1275 if (rc == 0 || rc != -EAGAIN)
1278 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1279 } while (retry_cnt--);
1284 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1285 rc = bnxt_handle_if_change_status(bp);
1290 bnxt_enable_int(bp);
1292 rc = bnxt_init_chip(bp);
1296 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1297 eth_dev->data->dev_started = 1;
1299 bnxt_link_update_op(eth_dev, 1);
1301 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1302 vlan_mask |= ETH_VLAN_FILTER_MASK;
1303 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1304 vlan_mask |= ETH_VLAN_STRIP_MASK;
1305 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1309 /* Initialize bnxt ULP port details */
1310 rc = bnxt_ulp_port_init(bp);
1314 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1315 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1317 bnxt_schedule_fw_health_check(bp);
1322 bnxt_shutdown_nic(bp);
1323 bnxt_free_tx_mbufs(bp);
1324 bnxt_free_rx_mbufs(bp);
1325 bnxt_hwrm_if_change(bp, false);
1326 eth_dev->data->dev_started = 0;
1330 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1332 struct bnxt *bp = eth_dev->data->dev_private;
1335 if (!bp->link_info->link_up)
1336 rc = bnxt_set_hwrm_link_config(bp, true);
1338 eth_dev->data->dev_link.link_status = 1;
1340 bnxt_print_link_info(eth_dev);
1344 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1346 struct bnxt *bp = eth_dev->data->dev_private;
1348 eth_dev->data->dev_link.link_status = 0;
1349 bnxt_set_hwrm_link_config(bp, false);
1350 bp->link_info->link_up = 0;
1355 static void bnxt_free_switch_domain(struct bnxt *bp)
1359 if (bp->switch_domain_id) {
1360 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1362 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1363 bp->switch_domain_id, rc);
1367 /* Unload the driver, release resources */
1368 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1370 struct bnxt *bp = eth_dev->data->dev_private;
1371 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1372 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1373 struct rte_eth_link link;
1376 eth_dev->data->dev_started = 0;
1377 eth_dev->data->scattered_rx = 0;
1379 /* Prevent crashes when queues are still in use */
1380 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1381 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1383 bnxt_disable_int(bp);
1385 /* disable uio/vfio intr/eventfd mapping */
1386 rte_intr_disable(intr_handle);
1388 /* Stop the child representors for this device */
1389 ret = bnxt_rep_stop_all(bp);
1393 /* delete the bnxt ULP port details */
1394 bnxt_ulp_port_deinit(bp);
1396 bnxt_cancel_fw_health_check(bp);
1398 /* Do not bring link down during reset recovery */
1399 if (!is_bnxt_in_error(bp)) {
1400 bnxt_dev_set_link_down_op(eth_dev);
1401 /* Wait for link to be reset */
1402 if (BNXT_SINGLE_PF(bp))
1404 /* clear the recorded link status */
1405 memset(&link, 0, sizeof(link));
1406 rte_eth_linkstatus_set(eth_dev, &link);
1409 /* Clean queue intr-vector mapping */
1410 rte_intr_efd_disable(intr_handle);
1411 if (intr_handle->intr_vec != NULL) {
1412 rte_free(intr_handle->intr_vec);
1413 intr_handle->intr_vec = NULL;
1416 bnxt_hwrm_port_clr_stats(bp);
1417 bnxt_free_tx_mbufs(bp);
1418 bnxt_free_rx_mbufs(bp);
1419 /* Process any remaining notifications in default completion queue */
1420 bnxt_int_handler(eth_dev);
1421 bnxt_shutdown_nic(bp);
1422 bnxt_hwrm_if_change(bp, false);
1424 rte_free(bp->mark_table);
1425 bp->mark_table = NULL;
1427 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1428 bp->rx_cosq_cnt = 0;
1429 /* All filters are deleted on a port stop. */
1430 if (BNXT_FLOW_XSTATS_EN(bp))
1431 bp->flow_stat->flow_count = 0;
1436 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1438 struct bnxt *bp = eth_dev->data->dev_private;
1441 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1444 /* cancel the recovery handler before remove dev */
1445 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1446 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1447 bnxt_cancel_fc_thread(bp);
1449 if (eth_dev->data->dev_started)
1450 ret = bnxt_dev_stop_op(eth_dev);
1452 bnxt_free_switch_domain(bp);
1454 bnxt_uninit_resources(bp, false);
1456 bnxt_free_leds_info(bp);
1457 bnxt_free_cos_queues(bp);
1458 bnxt_free_link_info(bp);
1459 bnxt_free_pf_info(bp);
1460 bnxt_free_parent_info(bp);
1462 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1463 bp->tx_mem_zone = NULL;
1464 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1465 bp->rx_mem_zone = NULL;
1467 bnxt_hwrm_free_vf_info(bp);
1469 rte_free(bp->grp_info);
1470 bp->grp_info = NULL;
1475 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1478 struct bnxt *bp = eth_dev->data->dev_private;
1479 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1480 struct bnxt_vnic_info *vnic;
1481 struct bnxt_filter_info *filter, *temp_filter;
1484 if (is_bnxt_in_error(bp))
1488 * Loop through all VNICs from the specified filter flow pools to
1489 * remove the corresponding MAC addr filter
1491 for (i = 0; i < bp->nr_vnics; i++) {
1492 if (!(pool_mask & (1ULL << i)))
1495 vnic = &bp->vnic_info[i];
1496 filter = STAILQ_FIRST(&vnic->filter);
1498 temp_filter = STAILQ_NEXT(filter, next);
1499 if (filter->mac_index == index) {
1500 STAILQ_REMOVE(&vnic->filter, filter,
1501 bnxt_filter_info, next);
1502 bnxt_hwrm_clear_l2_filter(bp, filter);
1503 bnxt_free_filter(bp, filter);
1505 filter = temp_filter;
1510 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1511 struct rte_ether_addr *mac_addr, uint32_t index,
1514 struct bnxt_filter_info *filter;
1517 /* Attach requested MAC address to the new l2_filter */
1518 STAILQ_FOREACH(filter, &vnic->filter, next) {
1519 if (filter->mac_index == index) {
1521 "MAC addr already existed for pool %d\n",
1527 filter = bnxt_alloc_filter(bp);
1529 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1533 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1534 * if the MAC that's been programmed now is a different one, then,
1535 * copy that addr to filter->l2_addr
1538 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1539 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1541 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1543 filter->mac_index = index;
1544 if (filter->mac_index == 0)
1545 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1547 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1549 bnxt_free_filter(bp, filter);
1555 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1556 struct rte_ether_addr *mac_addr,
1557 uint32_t index, uint32_t pool)
1559 struct bnxt *bp = eth_dev->data->dev_private;
1560 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1563 rc = is_bnxt_in_error(bp);
1567 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1568 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1573 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1577 /* Filter settings will get applied when port is started */
1578 if (!eth_dev->data->dev_started)
1581 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1586 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1589 struct bnxt *bp = eth_dev->data->dev_private;
1590 struct rte_eth_link new;
1591 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1592 BNXT_MIN_LINK_WAIT_CNT;
1594 rc = is_bnxt_in_error(bp);
1598 memset(&new, 0, sizeof(new));
1600 /* Retrieve link info from hardware */
1601 rc = bnxt_get_hwrm_link_config(bp, &new);
1603 new.link_speed = ETH_LINK_SPEED_100M;
1604 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1606 "Failed to retrieve link rc = 0x%x!\n", rc);
1610 if (!wait_to_complete || new.link_status)
1613 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1616 /* Only single function PF can bring phy down.
1617 * When port is stopped, report link down for VF/MH/NPAR functions.
1619 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1620 memset(&new, 0, sizeof(new));
1623 /* Timed out or success */
1624 if (new.link_status != eth_dev->data->dev_link.link_status ||
1625 new.link_speed != eth_dev->data->dev_link.link_speed) {
1626 rte_eth_linkstatus_set(eth_dev, &new);
1628 rte_eth_dev_callback_process(eth_dev,
1629 RTE_ETH_EVENT_INTR_LSC,
1632 bnxt_print_link_info(eth_dev);
1638 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1640 struct bnxt *bp = eth_dev->data->dev_private;
1641 struct bnxt_vnic_info *vnic;
1645 rc = is_bnxt_in_error(bp);
1649 /* Filter settings will get applied when port is started */
1650 if (!eth_dev->data->dev_started)
1653 if (bp->vnic_info == NULL)
1656 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1658 old_flags = vnic->flags;
1659 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1660 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1662 vnic->flags = old_flags;
1667 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1669 struct bnxt *bp = eth_dev->data->dev_private;
1670 struct bnxt_vnic_info *vnic;
1674 rc = is_bnxt_in_error(bp);
1678 /* Filter settings will get applied when port is started */
1679 if (!eth_dev->data->dev_started)
1682 if (bp->vnic_info == NULL)
1685 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1687 old_flags = vnic->flags;
1688 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1689 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1691 vnic->flags = old_flags;
1696 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1698 struct bnxt *bp = eth_dev->data->dev_private;
1699 struct bnxt_vnic_info *vnic;
1703 rc = is_bnxt_in_error(bp);
1707 /* Filter settings will get applied when port is started */
1708 if (!eth_dev->data->dev_started)
1711 if (bp->vnic_info == NULL)
1714 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1716 old_flags = vnic->flags;
1717 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1718 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1720 vnic->flags = old_flags;
1725 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1727 struct bnxt *bp = eth_dev->data->dev_private;
1728 struct bnxt_vnic_info *vnic;
1732 rc = is_bnxt_in_error(bp);
1736 /* Filter settings will get applied when port is started */
1737 if (!eth_dev->data->dev_started)
1740 if (bp->vnic_info == NULL)
1743 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1745 old_flags = vnic->flags;
1746 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1747 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1749 vnic->flags = old_flags;
1754 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1755 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1757 if (qid >= bp->rx_nr_rings)
1760 return bp->eth_dev->data->rx_queues[qid];
1763 /* Return rxq corresponding to a given rss table ring/group ID. */
1764 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1766 struct bnxt_rx_queue *rxq;
1769 if (!BNXT_HAS_RING_GRPS(bp)) {
1770 for (i = 0; i < bp->rx_nr_rings; i++) {
1771 rxq = bp->eth_dev->data->rx_queues[i];
1772 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1776 for (i = 0; i < bp->rx_nr_rings; i++) {
1777 if (bp->grp_info[i].fw_grp_id == fwr)
1782 return INVALID_HW_RING_ID;
1785 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1786 struct rte_eth_rss_reta_entry64 *reta_conf,
1789 struct bnxt *bp = eth_dev->data->dev_private;
1790 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1791 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1792 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1796 rc = is_bnxt_in_error(bp);
1800 if (!vnic->rss_table)
1803 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1806 if (reta_size != tbl_size) {
1807 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1808 "(%d) must equal the size supported by the hardware "
1809 "(%d)\n", reta_size, tbl_size);
1813 for (i = 0; i < reta_size; i++) {
1814 struct bnxt_rx_queue *rxq;
1816 idx = i / RTE_RETA_GROUP_SIZE;
1817 sft = i % RTE_RETA_GROUP_SIZE;
1819 if (!(reta_conf[idx].mask & (1ULL << sft)))
1822 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1824 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1828 if (BNXT_CHIP_P5(bp)) {
1829 vnic->rss_table[i * 2] =
1830 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1831 vnic->rss_table[i * 2 + 1] =
1832 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1834 vnic->rss_table[i] =
1835 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1839 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1843 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1844 struct rte_eth_rss_reta_entry64 *reta_conf,
1847 struct bnxt *bp = eth_dev->data->dev_private;
1848 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1849 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1850 uint16_t idx, sft, i;
1853 rc = is_bnxt_in_error(bp);
1857 /* Retrieve from the default VNIC */
1860 if (!vnic->rss_table)
1863 if (reta_size != tbl_size) {
1864 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1865 "(%d) must equal the size supported by the hardware "
1866 "(%d)\n", reta_size, tbl_size);
1870 for (idx = 0, i = 0; i < reta_size; i++) {
1871 idx = i / RTE_RETA_GROUP_SIZE;
1872 sft = i % RTE_RETA_GROUP_SIZE;
1874 if (reta_conf[idx].mask & (1ULL << sft)) {
1877 if (BNXT_CHIP_P5(bp))
1878 qid = bnxt_rss_to_qid(bp,
1879 vnic->rss_table[i * 2]);
1881 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1883 if (qid == INVALID_HW_RING_ID) {
1884 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1887 reta_conf[idx].reta[sft] = qid;
1894 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1895 struct rte_eth_rss_conf *rss_conf)
1897 struct bnxt *bp = eth_dev->data->dev_private;
1898 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1899 struct bnxt_vnic_info *vnic;
1902 rc = is_bnxt_in_error(bp);
1907 * If RSS enablement were different than dev_configure,
1908 * then return -EINVAL
1910 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1911 if (!rss_conf->rss_hf)
1912 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1914 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1918 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1919 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1923 /* Update the default RSS VNIC(s) */
1924 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1925 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1927 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1928 ETH_RSS_LEVEL(rss_conf->rss_hf));
1931 * If hashkey is not specified, use the previously configured
1934 if (!rss_conf->rss_key)
1937 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1939 "Invalid hashkey length, should be 16 bytes\n");
1942 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1945 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1949 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1950 struct rte_eth_rss_conf *rss_conf)
1952 struct bnxt *bp = eth_dev->data->dev_private;
1953 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1955 uint32_t hash_types;
1957 rc = is_bnxt_in_error(bp);
1961 /* RSS configuration is the same for all VNICs */
1962 if (vnic && vnic->rss_hash_key) {
1963 if (rss_conf->rss_key) {
1964 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1965 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1966 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1969 hash_types = vnic->hash_type;
1970 rss_conf->rss_hf = 0;
1971 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1972 rss_conf->rss_hf |= ETH_RSS_IPV4;
1973 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1975 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1976 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1978 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1980 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1981 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1983 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1985 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1986 rss_conf->rss_hf |= ETH_RSS_IPV6;
1987 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1989 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1990 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1992 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1994 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1995 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1997 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2001 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2005 "Unknown RSS config from firmware (%08x), RSS disabled",
2010 rss_conf->rss_hf = 0;
2015 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2016 struct rte_eth_fc_conf *fc_conf)
2018 struct bnxt *bp = dev->data->dev_private;
2019 struct rte_eth_link link_info;
2022 rc = is_bnxt_in_error(bp);
2026 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2030 memset(fc_conf, 0, sizeof(*fc_conf));
2031 if (bp->link_info->auto_pause)
2032 fc_conf->autoneg = 1;
2033 switch (bp->link_info->pause) {
2035 fc_conf->mode = RTE_FC_NONE;
2037 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2038 fc_conf->mode = RTE_FC_TX_PAUSE;
2040 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2041 fc_conf->mode = RTE_FC_RX_PAUSE;
2043 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2044 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2045 fc_conf->mode = RTE_FC_FULL;
2051 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2052 struct rte_eth_fc_conf *fc_conf)
2054 struct bnxt *bp = dev->data->dev_private;
2057 rc = is_bnxt_in_error(bp);
2061 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2062 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2066 switch (fc_conf->mode) {
2068 bp->link_info->auto_pause = 0;
2069 bp->link_info->force_pause = 0;
2071 case RTE_FC_RX_PAUSE:
2072 if (fc_conf->autoneg) {
2073 bp->link_info->auto_pause =
2074 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2075 bp->link_info->force_pause = 0;
2077 bp->link_info->auto_pause = 0;
2078 bp->link_info->force_pause =
2079 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2082 case RTE_FC_TX_PAUSE:
2083 if (fc_conf->autoneg) {
2084 bp->link_info->auto_pause =
2085 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2086 bp->link_info->force_pause = 0;
2088 bp->link_info->auto_pause = 0;
2089 bp->link_info->force_pause =
2090 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2094 if (fc_conf->autoneg) {
2095 bp->link_info->auto_pause =
2096 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2097 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2098 bp->link_info->force_pause = 0;
2100 bp->link_info->auto_pause = 0;
2101 bp->link_info->force_pause =
2102 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2103 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2107 return bnxt_set_hwrm_link_config(bp, true);
2110 /* Add UDP tunneling port */
2112 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2113 struct rte_eth_udp_tunnel *udp_tunnel)
2115 struct bnxt *bp = eth_dev->data->dev_private;
2116 uint16_t tunnel_type = 0;
2119 rc = is_bnxt_in_error(bp);
2123 switch (udp_tunnel->prot_type) {
2124 case RTE_TUNNEL_TYPE_VXLAN:
2125 if (bp->vxlan_port_cnt) {
2126 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2127 udp_tunnel->udp_port);
2128 if (bp->vxlan_port != udp_tunnel->udp_port) {
2129 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2132 bp->vxlan_port_cnt++;
2136 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2137 bp->vxlan_port_cnt++;
2139 case RTE_TUNNEL_TYPE_GENEVE:
2140 if (bp->geneve_port_cnt) {
2141 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2142 udp_tunnel->udp_port);
2143 if (bp->geneve_port != udp_tunnel->udp_port) {
2144 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2147 bp->geneve_port_cnt++;
2151 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2152 bp->geneve_port_cnt++;
2155 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2158 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2164 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2165 struct rte_eth_udp_tunnel *udp_tunnel)
2167 struct bnxt *bp = eth_dev->data->dev_private;
2168 uint16_t tunnel_type = 0;
2172 rc = is_bnxt_in_error(bp);
2176 switch (udp_tunnel->prot_type) {
2177 case RTE_TUNNEL_TYPE_VXLAN:
2178 if (!bp->vxlan_port_cnt) {
2179 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2182 if (bp->vxlan_port != udp_tunnel->udp_port) {
2183 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2184 udp_tunnel->udp_port, bp->vxlan_port);
2187 if (--bp->vxlan_port_cnt)
2191 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2192 port = bp->vxlan_fw_dst_port_id;
2194 case RTE_TUNNEL_TYPE_GENEVE:
2195 if (!bp->geneve_port_cnt) {
2196 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2199 if (bp->geneve_port != udp_tunnel->udp_port) {
2200 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2201 udp_tunnel->udp_port, bp->geneve_port);
2204 if (--bp->geneve_port_cnt)
2208 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2209 port = bp->geneve_fw_dst_port_id;
2212 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2216 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2220 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2222 struct bnxt_filter_info *filter;
2223 struct bnxt_vnic_info *vnic;
2225 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2227 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2228 filter = STAILQ_FIRST(&vnic->filter);
2230 /* Search for this matching MAC+VLAN filter */
2231 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2232 /* Delete the filter */
2233 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2236 STAILQ_REMOVE(&vnic->filter, filter,
2237 bnxt_filter_info, next);
2238 bnxt_free_filter(bp, filter);
2240 "Deleted vlan filter for %d\n",
2244 filter = STAILQ_NEXT(filter, next);
2249 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2251 struct bnxt_filter_info *filter;
2252 struct bnxt_vnic_info *vnic;
2254 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2255 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2256 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2258 /* Implementation notes on the use of VNIC in this command:
2260 * By default, these filters belong to default vnic for the function.
2261 * Once these filters are set up, only destination VNIC can be modified.
2262 * If the destination VNIC is not specified in this command,
2263 * then the HWRM shall only create an l2 context id.
2266 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2267 filter = STAILQ_FIRST(&vnic->filter);
2268 /* Check if the VLAN has already been added */
2270 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2273 filter = STAILQ_NEXT(filter, next);
2276 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2277 * command to create MAC+VLAN filter with the right flags, enables set.
2279 filter = bnxt_alloc_filter(bp);
2282 "MAC/VLAN filter alloc failed\n");
2285 /* MAC + VLAN ID filter */
2286 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2287 * untagged packets are received
2289 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2290 * packets and only the programmed vlan's packets are received
2292 filter->l2_ivlan = vlan_id;
2293 filter->l2_ivlan_mask = 0x0FFF;
2294 filter->enables |= en;
2295 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2297 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2299 /* Free the newly allocated filter as we were
2300 * not able to create the filter in hardware.
2302 bnxt_free_filter(bp, filter);
2306 filter->mac_index = 0;
2307 /* Add this new filter to the list */
2309 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2311 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2314 "Added Vlan filter for %d\n", vlan_id);
2318 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2319 uint16_t vlan_id, int on)
2321 struct bnxt *bp = eth_dev->data->dev_private;
2324 rc = is_bnxt_in_error(bp);
2328 if (!eth_dev->data->dev_started) {
2329 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2333 /* These operations apply to ALL existing MAC/VLAN filters */
2335 return bnxt_add_vlan_filter(bp, vlan_id);
2337 return bnxt_del_vlan_filter(bp, vlan_id);
2340 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2341 struct bnxt_vnic_info *vnic)
2343 struct bnxt_filter_info *filter;
2346 filter = STAILQ_FIRST(&vnic->filter);
2348 if (filter->mac_index == 0 &&
2349 !memcmp(filter->l2_addr, bp->mac_addr,
2350 RTE_ETHER_ADDR_LEN)) {
2351 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2353 STAILQ_REMOVE(&vnic->filter, filter,
2354 bnxt_filter_info, next);
2355 bnxt_free_filter(bp, filter);
2359 filter = STAILQ_NEXT(filter, next);
2365 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2367 struct bnxt_vnic_info *vnic;
2371 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2372 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2373 /* Remove any VLAN filters programmed */
2374 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2375 bnxt_del_vlan_filter(bp, i);
2377 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2381 /* Default filter will allow packets that match the
2382 * dest mac. So, it has to be deleted, otherwise, we
2383 * will endup receiving vlan packets for which the
2384 * filter is not programmed, when hw-vlan-filter
2385 * configuration is ON
2387 bnxt_del_dflt_mac_filter(bp, vnic);
2388 /* This filter will allow only untagged packets */
2389 bnxt_add_vlan_filter(bp, 0);
2391 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2392 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2397 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2399 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2403 /* Destroy vnic filters and vnic */
2404 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2405 DEV_RX_OFFLOAD_VLAN_FILTER) {
2406 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2407 bnxt_del_vlan_filter(bp, i);
2409 bnxt_del_dflt_mac_filter(bp, vnic);
2411 rc = bnxt_hwrm_vnic_free(bp, vnic);
2415 rte_free(vnic->fw_grp_ids);
2416 vnic->fw_grp_ids = NULL;
2418 vnic->rx_queue_cnt = 0;
2424 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2426 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2429 /* Destroy, recreate and reconfigure the default vnic */
2430 rc = bnxt_free_one_vnic(bp, 0);
2434 /* default vnic 0 */
2435 rc = bnxt_setup_one_vnic(bp, 0);
2439 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2440 DEV_RX_OFFLOAD_VLAN_FILTER) {
2441 rc = bnxt_add_vlan_filter(bp, 0);
2444 rc = bnxt_restore_vlan_filters(bp);
2448 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2453 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2457 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2458 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2464 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2466 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2467 struct bnxt *bp = dev->data->dev_private;
2470 rc = is_bnxt_in_error(bp);
2474 /* Filter settings will get applied when port is started */
2475 if (!dev->data->dev_started)
2478 if (mask & ETH_VLAN_FILTER_MASK) {
2479 /* Enable or disable VLAN filtering */
2480 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2485 if (mask & ETH_VLAN_STRIP_MASK) {
2486 /* Enable or disable VLAN stripping */
2487 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2492 if (mask & ETH_VLAN_EXTEND_MASK) {
2493 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2494 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2496 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2503 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2506 struct bnxt *bp = dev->data->dev_private;
2507 int qinq = dev->data->dev_conf.rxmode.offloads &
2508 DEV_RX_OFFLOAD_VLAN_EXTEND;
2510 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2511 vlan_type != ETH_VLAN_TYPE_OUTER) {
2513 "Unsupported vlan type.");
2518 "QinQ not enabled. Needs to be ON as we can "
2519 "accelerate only outer vlan\n");
2523 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2525 case RTE_ETHER_TYPE_QINQ:
2527 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2529 case RTE_ETHER_TYPE_VLAN:
2531 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2533 case RTE_ETHER_TYPE_QINQ1:
2535 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2537 case RTE_ETHER_TYPE_QINQ2:
2539 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2541 case RTE_ETHER_TYPE_QINQ3:
2543 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2546 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2549 bp->outer_tpid_bd |= tpid;
2550 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2551 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2553 "Can accelerate only outer vlan in QinQ\n");
2561 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2562 struct rte_ether_addr *addr)
2564 struct bnxt *bp = dev->data->dev_private;
2565 /* Default Filter is tied to VNIC 0 */
2566 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2569 rc = is_bnxt_in_error(bp);
2573 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2576 if (rte_is_zero_ether_addr(addr))
2579 /* Filter settings will get applied when port is started */
2580 if (!dev->data->dev_started)
2583 /* Check if the requested MAC is already added */
2584 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2587 /* Destroy filter and re-create it */
2588 bnxt_del_dflt_mac_filter(bp, vnic);
2590 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2591 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2592 /* This filter will allow only untagged packets */
2593 rc = bnxt_add_vlan_filter(bp, 0);
2595 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2598 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2603 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2604 struct rte_ether_addr *mc_addr_set,
2605 uint32_t nb_mc_addr)
2607 struct bnxt *bp = eth_dev->data->dev_private;
2608 char *mc_addr_list = (char *)mc_addr_set;
2609 struct bnxt_vnic_info *vnic;
2610 uint32_t off = 0, i = 0;
2613 rc = is_bnxt_in_error(bp);
2617 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2619 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2620 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2624 /* TODO Check for Duplicate mcast addresses */
2625 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2626 for (i = 0; i < nb_mc_addr; i++) {
2627 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2628 RTE_ETHER_ADDR_LEN);
2629 off += RTE_ETHER_ADDR_LEN;
2632 vnic->mc_addr_cnt = i;
2633 if (vnic->mc_addr_cnt)
2634 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2636 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2639 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2643 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2645 struct bnxt *bp = dev->data->dev_private;
2646 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2647 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2648 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2649 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2652 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2653 fw_major, fw_minor, fw_updt, fw_rsvd);
2655 ret += 1; /* add the size of '\0' */
2656 if (fw_size < (uint32_t)ret)
2663 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2664 struct rte_eth_rxq_info *qinfo)
2666 struct bnxt *bp = dev->data->dev_private;
2667 struct bnxt_rx_queue *rxq;
2669 if (is_bnxt_in_error(bp))
2672 rxq = dev->data->rx_queues[queue_id];
2674 qinfo->mp = rxq->mb_pool;
2675 qinfo->scattered_rx = dev->data->scattered_rx;
2676 qinfo->nb_desc = rxq->nb_rx_desc;
2678 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2679 qinfo->conf.rx_drop_en = rxq->drop_en;
2680 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2681 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2685 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2686 struct rte_eth_txq_info *qinfo)
2688 struct bnxt *bp = dev->data->dev_private;
2689 struct bnxt_tx_queue *txq;
2691 if (is_bnxt_in_error(bp))
2694 txq = dev->data->tx_queues[queue_id];
2696 qinfo->nb_desc = txq->nb_tx_desc;
2698 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2699 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2700 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2702 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2703 qinfo->conf.tx_rs_thresh = 0;
2704 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2705 qinfo->conf.offloads = txq->offloads;
2708 static const struct {
2709 eth_rx_burst_t pkt_burst;
2711 } bnxt_rx_burst_info[] = {
2712 {bnxt_recv_pkts, "Scalar"},
2713 #if defined(RTE_ARCH_X86)
2714 {bnxt_recv_pkts_vec, "Vector SSE"},
2715 #elif defined(RTE_ARCH_ARM64)
2716 {bnxt_recv_pkts_vec, "Vector Neon"},
2721 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2722 struct rte_eth_burst_mode *mode)
2724 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2727 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2728 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2729 snprintf(mode->info, sizeof(mode->info), "%s",
2730 bnxt_rx_burst_info[i].info);
2738 static const struct {
2739 eth_tx_burst_t pkt_burst;
2741 } bnxt_tx_burst_info[] = {
2742 {bnxt_xmit_pkts, "Scalar"},
2743 #if defined(RTE_ARCH_X86)
2744 {bnxt_xmit_pkts_vec, "Vector SSE"},
2745 #elif defined(RTE_ARCH_ARM64)
2746 {bnxt_xmit_pkts_vec, "Vector Neon"},
2751 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2752 struct rte_eth_burst_mode *mode)
2754 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2757 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2758 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2759 snprintf(mode->info, sizeof(mode->info), "%s",
2760 bnxt_tx_burst_info[i].info);
2768 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2770 struct bnxt *bp = eth_dev->data->dev_private;
2771 uint32_t new_pkt_size;
2775 rc = is_bnxt_in_error(bp);
2779 /* Exit if receive queues are not configured yet */
2780 if (!eth_dev->data->nb_rx_queues)
2783 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2784 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2787 * Disallow any MTU change that would require scattered receive support
2788 * if it is not already enabled.
2790 if (eth_dev->data->dev_started &&
2791 !eth_dev->data->scattered_rx &&
2793 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2795 "MTU change would require scattered rx support. ");
2796 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2800 if (new_mtu > RTE_ETHER_MTU) {
2801 bp->flags |= BNXT_FLAG_JUMBO;
2802 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2803 DEV_RX_OFFLOAD_JUMBO_FRAME;
2805 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2806 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2807 bp->flags &= ~BNXT_FLAG_JUMBO;
2810 /* Is there a change in mtu setting? */
2811 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2814 for (i = 0; i < bp->nr_vnics; i++) {
2815 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2818 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2819 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2823 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2824 size -= RTE_PKTMBUF_HEADROOM;
2826 if (size < new_mtu) {
2827 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2834 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2836 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2842 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2844 struct bnxt *bp = dev->data->dev_private;
2845 uint16_t vlan = bp->vlan;
2848 rc = is_bnxt_in_error(bp);
2852 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2854 "PVID cannot be modified for this function\n");
2857 bp->vlan = on ? pvid : 0;
2859 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2866 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2868 struct bnxt *bp = dev->data->dev_private;
2871 rc = is_bnxt_in_error(bp);
2875 return bnxt_hwrm_port_led_cfg(bp, true);
2879 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2881 struct bnxt *bp = dev->data->dev_private;
2884 rc = is_bnxt_in_error(bp);
2888 return bnxt_hwrm_port_led_cfg(bp, false);
2892 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2894 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2895 uint32_t desc = 0, raw_cons = 0, cons;
2896 struct bnxt_cp_ring_info *cpr;
2897 struct bnxt_rx_queue *rxq;
2898 struct rx_pkt_cmpl *rxcmp;
2901 rc = is_bnxt_in_error(bp);
2905 rxq = dev->data->rx_queues[rx_queue_id];
2907 raw_cons = cpr->cp_raw_cons;
2910 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2911 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2912 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2914 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2926 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2928 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2929 struct bnxt_rx_ring_info *rxr;
2930 struct bnxt_cp_ring_info *cpr;
2931 struct rte_mbuf *rx_buf;
2932 struct rx_pkt_cmpl *rxcmp;
2933 uint32_t cons, cp_cons;
2939 rc = is_bnxt_in_error(rxq->bp);
2946 if (offset >= rxq->nb_rx_desc)
2949 cons = RING_CMP(cpr->cp_ring_struct, offset);
2950 cp_cons = cpr->cp_raw_cons;
2951 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2953 if (cons > cp_cons) {
2954 if (CMPL_VALID(rxcmp, cpr->valid))
2955 return RTE_ETH_RX_DESC_DONE;
2957 if (CMPL_VALID(rxcmp, !cpr->valid))
2958 return RTE_ETH_RX_DESC_DONE;
2960 rx_buf = rxr->rx_buf_ring[cons];
2961 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2962 return RTE_ETH_RX_DESC_UNAVAIL;
2965 return RTE_ETH_RX_DESC_AVAIL;
2969 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2971 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2972 struct bnxt_tx_ring_info *txr;
2973 struct bnxt_cp_ring_info *cpr;
2974 struct bnxt_sw_tx_bd *tx_buf;
2975 struct tx_pkt_cmpl *txcmp;
2976 uint32_t cons, cp_cons;
2982 rc = is_bnxt_in_error(txq->bp);
2989 if (offset >= txq->nb_tx_desc)
2992 cons = RING_CMP(cpr->cp_ring_struct, offset);
2993 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2994 cp_cons = cpr->cp_raw_cons;
2996 if (cons > cp_cons) {
2997 if (CMPL_VALID(txcmp, cpr->valid))
2998 return RTE_ETH_TX_DESC_UNAVAIL;
3000 if (CMPL_VALID(txcmp, !cpr->valid))
3001 return RTE_ETH_TX_DESC_UNAVAIL;
3003 tx_buf = &txr->tx_buf_ring[cons];
3004 if (tx_buf->mbuf == NULL)
3005 return RTE_ETH_TX_DESC_DONE;
3007 return RTE_ETH_TX_DESC_FULL;
3011 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3012 enum rte_filter_type filter_type,
3013 enum rte_filter_op filter_op, void *arg)
3015 struct bnxt *bp = dev->data->dev_private;
3021 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3022 struct bnxt_representor *vfr = dev->data->dev_private;
3023 bp = vfr->parent_dev->data->dev_private;
3024 /* parent is deleted while children are still valid */
3026 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3034 ret = is_bnxt_in_error(bp);
3038 switch (filter_type) {
3039 case RTE_ETH_FILTER_GENERIC:
3040 if (filter_op != RTE_ETH_FILTER_GET)
3043 /* PMD supports thread-safe flow operations. rte_flow API
3044 * functions can avoid mutex for multi-thread safety.
3046 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3048 if (BNXT_TRUFLOW_EN(bp))
3049 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3051 *(const void **)arg = &bnxt_flow_ops;
3055 "Filter type (%d) not supported", filter_type);
3062 static const uint32_t *
3063 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3065 static const uint32_t ptypes[] = {
3066 RTE_PTYPE_L2_ETHER_VLAN,
3067 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3068 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3072 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3073 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3074 RTE_PTYPE_INNER_L4_ICMP,
3075 RTE_PTYPE_INNER_L4_TCP,
3076 RTE_PTYPE_INNER_L4_UDP,
3080 if (!dev->rx_pkt_burst)
3086 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3089 uint32_t reg_base = *reg_arr & 0xfffff000;
3093 for (i = 0; i < count; i++) {
3094 if ((reg_arr[i] & 0xfffff000) != reg_base)
3097 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3098 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3102 static int bnxt_map_ptp_regs(struct bnxt *bp)
3104 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3108 reg_arr = ptp->rx_regs;
3109 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3113 reg_arr = ptp->tx_regs;
3114 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3118 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3119 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3121 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3122 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3127 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3129 rte_write32(0, (uint8_t *)bp->bar0 +
3130 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3131 rte_write32(0, (uint8_t *)bp->bar0 +
3132 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3135 static uint64_t bnxt_cc_read(struct bnxt *bp)
3139 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3140 BNXT_GRCPF_REG_SYNC_TIME));
3141 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3142 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3146 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3148 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3151 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3152 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3153 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3156 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3157 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3158 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3159 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3160 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3161 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3166 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3168 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3169 struct bnxt_pf_info *pf = bp->pf;
3176 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3177 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3178 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3181 port_id = pf->port_id;
3182 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3183 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3185 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3186 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3187 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3188 /* bnxt_clr_rx_ts(bp); TBD */
3192 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3193 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3194 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3195 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3201 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3204 struct bnxt *bp = dev->data->dev_private;
3205 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3210 ns = rte_timespec_to_ns(ts);
3211 /* Set the timecounters to a new value. */
3218 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3220 struct bnxt *bp = dev->data->dev_private;
3221 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3222 uint64_t ns, systime_cycles = 0;
3228 if (BNXT_CHIP_P5(bp))
3229 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3232 systime_cycles = bnxt_cc_read(bp);
3234 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3235 *ts = rte_ns_to_timespec(ns);
3240 bnxt_timesync_enable(struct rte_eth_dev *dev)
3242 struct bnxt *bp = dev->data->dev_private;
3243 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3251 ptp->tx_tstamp_en = 1;
3252 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3254 rc = bnxt_hwrm_ptp_cfg(bp);
3258 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3259 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3260 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3262 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3263 ptp->tc.cc_shift = shift;
3264 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3266 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3267 ptp->rx_tstamp_tc.cc_shift = shift;
3268 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3270 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3271 ptp->tx_tstamp_tc.cc_shift = shift;
3272 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3274 if (!BNXT_CHIP_P5(bp))
3275 bnxt_map_ptp_regs(bp);
3281 bnxt_timesync_disable(struct rte_eth_dev *dev)
3283 struct bnxt *bp = dev->data->dev_private;
3284 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3290 ptp->tx_tstamp_en = 0;
3293 bnxt_hwrm_ptp_cfg(bp);
3295 if (!BNXT_CHIP_P5(bp))
3296 bnxt_unmap_ptp_regs(bp);
3302 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3303 struct timespec *timestamp,
3304 uint32_t flags __rte_unused)
3306 struct bnxt *bp = dev->data->dev_private;
3307 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3308 uint64_t rx_tstamp_cycles = 0;
3314 if (BNXT_CHIP_P5(bp))
3315 rx_tstamp_cycles = ptp->rx_timestamp;
3317 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3319 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3320 *timestamp = rte_ns_to_timespec(ns);
3325 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3326 struct timespec *timestamp)
3328 struct bnxt *bp = dev->data->dev_private;
3329 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3330 uint64_t tx_tstamp_cycles = 0;
3337 if (BNXT_CHIP_P5(bp))
3338 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3341 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3343 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3344 *timestamp = rte_ns_to_timespec(ns);
3350 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3352 struct bnxt *bp = dev->data->dev_private;
3353 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3358 ptp->tc.nsec += delta;
3364 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3366 struct bnxt *bp = dev->data->dev_private;
3368 uint32_t dir_entries;
3369 uint32_t entry_length;
3371 rc = is_bnxt_in_error(bp);
3375 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3376 bp->pdev->addr.domain, bp->pdev->addr.bus,
3377 bp->pdev->addr.devid, bp->pdev->addr.function);
3379 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3383 return dir_entries * entry_length;
3387 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3388 struct rte_dev_eeprom_info *in_eeprom)
3390 struct bnxt *bp = dev->data->dev_private;
3395 rc = is_bnxt_in_error(bp);
3399 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3400 bp->pdev->addr.domain, bp->pdev->addr.bus,
3401 bp->pdev->addr.devid, bp->pdev->addr.function,
3402 in_eeprom->offset, in_eeprom->length);
3404 if (in_eeprom->offset == 0) /* special offset value to get directory */
3405 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3408 index = in_eeprom->offset >> 24;
3409 offset = in_eeprom->offset & 0xffffff;
3412 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3413 in_eeprom->length, in_eeprom->data);
3418 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3421 case BNX_DIR_TYPE_CHIMP_PATCH:
3422 case BNX_DIR_TYPE_BOOTCODE:
3423 case BNX_DIR_TYPE_BOOTCODE_2:
3424 case BNX_DIR_TYPE_APE_FW:
3425 case BNX_DIR_TYPE_APE_PATCH:
3426 case BNX_DIR_TYPE_KONG_FW:
3427 case BNX_DIR_TYPE_KONG_PATCH:
3428 case BNX_DIR_TYPE_BONO_FW:
3429 case BNX_DIR_TYPE_BONO_PATCH:
3437 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3440 case BNX_DIR_TYPE_AVS:
3441 case BNX_DIR_TYPE_EXP_ROM_MBA:
3442 case BNX_DIR_TYPE_PCIE:
3443 case BNX_DIR_TYPE_TSCF_UCODE:
3444 case BNX_DIR_TYPE_EXT_PHY:
3445 case BNX_DIR_TYPE_CCM:
3446 case BNX_DIR_TYPE_ISCSI_BOOT:
3447 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3448 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3456 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3458 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3459 bnxt_dir_type_is_other_exec_format(dir_type);
3463 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3464 struct rte_dev_eeprom_info *in_eeprom)
3466 struct bnxt *bp = dev->data->dev_private;
3467 uint8_t index, dir_op;
3468 uint16_t type, ext, ordinal, attr;
3471 rc = is_bnxt_in_error(bp);
3475 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3476 bp->pdev->addr.domain, bp->pdev->addr.bus,
3477 bp->pdev->addr.devid, bp->pdev->addr.function,
3478 in_eeprom->offset, in_eeprom->length);
3481 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3485 type = in_eeprom->magic >> 16;
3487 if (type == 0xffff) { /* special value for directory operations */
3488 index = in_eeprom->magic & 0xff;
3489 dir_op = in_eeprom->magic >> 8;
3493 case 0x0e: /* erase */
3494 if (in_eeprom->offset != ~in_eeprom->magic)
3496 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3502 /* Create or re-write an NVM item: */
3503 if (bnxt_dir_type_is_executable(type) == true)
3505 ext = in_eeprom->magic & 0xffff;
3506 ordinal = in_eeprom->offset >> 16;
3507 attr = in_eeprom->offset & 0xffff;
3509 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3510 in_eeprom->data, in_eeprom->length);
3517 static const struct eth_dev_ops bnxt_dev_ops = {
3518 .dev_infos_get = bnxt_dev_info_get_op,
3519 .dev_close = bnxt_dev_close_op,
3520 .dev_configure = bnxt_dev_configure_op,
3521 .dev_start = bnxt_dev_start_op,
3522 .dev_stop = bnxt_dev_stop_op,
3523 .dev_set_link_up = bnxt_dev_set_link_up_op,
3524 .dev_set_link_down = bnxt_dev_set_link_down_op,
3525 .stats_get = bnxt_stats_get_op,
3526 .stats_reset = bnxt_stats_reset_op,
3527 .rx_queue_setup = bnxt_rx_queue_setup_op,
3528 .rx_queue_release = bnxt_rx_queue_release_op,
3529 .tx_queue_setup = bnxt_tx_queue_setup_op,
3530 .tx_queue_release = bnxt_tx_queue_release_op,
3531 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3532 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3533 .reta_update = bnxt_reta_update_op,
3534 .reta_query = bnxt_reta_query_op,
3535 .rss_hash_update = bnxt_rss_hash_update_op,
3536 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3537 .link_update = bnxt_link_update_op,
3538 .promiscuous_enable = bnxt_promiscuous_enable_op,
3539 .promiscuous_disable = bnxt_promiscuous_disable_op,
3540 .allmulticast_enable = bnxt_allmulticast_enable_op,
3541 .allmulticast_disable = bnxt_allmulticast_disable_op,
3542 .mac_addr_add = bnxt_mac_addr_add_op,
3543 .mac_addr_remove = bnxt_mac_addr_remove_op,
3544 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3545 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3546 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3547 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3548 .vlan_filter_set = bnxt_vlan_filter_set_op,
3549 .vlan_offload_set = bnxt_vlan_offload_set_op,
3550 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3551 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3552 .mtu_set = bnxt_mtu_set_op,
3553 .mac_addr_set = bnxt_set_default_mac_addr_op,
3554 .xstats_get = bnxt_dev_xstats_get_op,
3555 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3556 .xstats_reset = bnxt_dev_xstats_reset_op,
3557 .fw_version_get = bnxt_fw_version_get,
3558 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3559 .rxq_info_get = bnxt_rxq_info_get_op,
3560 .txq_info_get = bnxt_txq_info_get_op,
3561 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3562 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3563 .dev_led_on = bnxt_dev_led_on_op,
3564 .dev_led_off = bnxt_dev_led_off_op,
3565 .rx_queue_start = bnxt_rx_queue_start,
3566 .rx_queue_stop = bnxt_rx_queue_stop,
3567 .tx_queue_start = bnxt_tx_queue_start,
3568 .tx_queue_stop = bnxt_tx_queue_stop,
3569 .filter_ctrl = bnxt_filter_ctrl_op,
3570 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3571 .get_eeprom_length = bnxt_get_eeprom_length_op,
3572 .get_eeprom = bnxt_get_eeprom_op,
3573 .set_eeprom = bnxt_set_eeprom_op,
3574 .timesync_enable = bnxt_timesync_enable,
3575 .timesync_disable = bnxt_timesync_disable,
3576 .timesync_read_time = bnxt_timesync_read_time,
3577 .timesync_write_time = bnxt_timesync_write_time,
3578 .timesync_adjust_time = bnxt_timesync_adjust_time,
3579 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3580 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3583 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3587 /* Only pre-map the reset GRC registers using window 3 */
3588 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3589 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3591 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3596 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3598 struct bnxt_error_recovery_info *info = bp->recovery_info;
3599 uint32_t reg_base = 0xffffffff;
3602 /* Only pre-map the monitoring GRC registers using window 2 */
3603 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3604 uint32_t reg = info->status_regs[i];
3606 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3609 if (reg_base == 0xffffffff)
3610 reg_base = reg & 0xfffff000;
3611 if ((reg & 0xfffff000) != reg_base)
3614 /* Use mask 0xffc as the Lower 2 bits indicates
3615 * address space location
3617 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3621 if (reg_base == 0xffffffff)
3624 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3625 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3630 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3632 struct bnxt_error_recovery_info *info = bp->recovery_info;
3633 uint32_t delay = info->delay_after_reset[index];
3634 uint32_t val = info->reset_reg_val[index];
3635 uint32_t reg = info->reset_reg[index];
3636 uint32_t type, offset;
3638 type = BNXT_FW_STATUS_REG_TYPE(reg);
3639 offset = BNXT_FW_STATUS_REG_OFF(reg);
3642 case BNXT_FW_STATUS_REG_TYPE_CFG:
3643 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3645 case BNXT_FW_STATUS_REG_TYPE_GRC:
3646 offset = bnxt_map_reset_regs(bp, offset);
3647 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3649 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3650 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3653 /* wait on a specific interval of time until core reset is complete */
3655 rte_delay_ms(delay);
3658 static void bnxt_dev_cleanup(struct bnxt *bp)
3660 bp->eth_dev->data->dev_link.link_status = 0;
3661 bp->link_info->link_up = 0;
3662 if (bp->eth_dev->data->dev_started)
3663 bnxt_dev_stop_op(bp->eth_dev);
3665 bnxt_uninit_resources(bp, true);
3668 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3670 struct rte_eth_dev *dev = bp->eth_dev;
3671 struct rte_vlan_filter_conf *vfc;
3675 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3676 vfc = &dev->data->vlan_filter_conf;
3677 vidx = vlan_id / 64;
3678 vbit = vlan_id % 64;
3680 /* Each bit corresponds to a VLAN id */
3681 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3682 rc = bnxt_add_vlan_filter(bp, vlan_id);
3691 static int bnxt_restore_mac_filters(struct bnxt *bp)
3693 struct rte_eth_dev *dev = bp->eth_dev;
3694 struct rte_eth_dev_info dev_info;
3695 struct rte_ether_addr *addr;
3701 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3704 rc = bnxt_dev_info_get_op(dev, &dev_info);
3708 /* replay MAC address configuration */
3709 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3710 addr = &dev->data->mac_addrs[i];
3712 /* skip zero address */
3713 if (rte_is_zero_ether_addr(addr))
3717 pool_mask = dev->data->mac_pool_sel[i];
3720 if (pool_mask & 1ULL) {
3721 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3727 } while (pool_mask);
3733 static int bnxt_restore_filters(struct bnxt *bp)
3735 struct rte_eth_dev *dev = bp->eth_dev;
3738 if (dev->data->all_multicast) {
3739 ret = bnxt_allmulticast_enable_op(dev);
3743 if (dev->data->promiscuous) {
3744 ret = bnxt_promiscuous_enable_op(dev);
3749 ret = bnxt_restore_mac_filters(bp);
3753 ret = bnxt_restore_vlan_filters(bp);
3754 /* TODO restore other filters as well */
3758 static void bnxt_dev_recover(void *arg)
3760 struct bnxt *bp = arg;
3761 int timeout = bp->fw_reset_max_msecs;
3764 /* Clear Error flag so that device re-init should happen */
3765 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3768 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3771 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3772 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3773 } while (rc && timeout);
3776 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3780 rc = bnxt_init_resources(bp, true);
3783 "Failed to initialize resources after reset\n");
3786 /* clear reset flag as the device is initialized now */
3787 bp->flags &= ~BNXT_FLAG_FW_RESET;
3789 rc = bnxt_dev_start_op(bp->eth_dev);
3791 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3795 rc = bnxt_restore_filters(bp);
3799 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3802 bnxt_dev_stop_op(bp->eth_dev);
3804 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3805 bnxt_uninit_resources(bp, false);
3806 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3809 void bnxt_dev_reset_and_resume(void *arg)
3811 struct bnxt *bp = arg;
3814 bnxt_dev_cleanup(bp);
3816 bnxt_wait_for_device_shutdown(bp);
3818 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3819 bnxt_dev_recover, (void *)bp);
3821 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3824 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3826 struct bnxt_error_recovery_info *info = bp->recovery_info;
3827 uint32_t reg = info->status_regs[index];
3828 uint32_t type, offset, val = 0;
3830 type = BNXT_FW_STATUS_REG_TYPE(reg);
3831 offset = BNXT_FW_STATUS_REG_OFF(reg);
3834 case BNXT_FW_STATUS_REG_TYPE_CFG:
3835 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3837 case BNXT_FW_STATUS_REG_TYPE_GRC:
3838 offset = info->mapped_status_regs[index];
3840 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3841 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3849 static int bnxt_fw_reset_all(struct bnxt *bp)
3851 struct bnxt_error_recovery_info *info = bp->recovery_info;
3855 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3856 /* Reset through master function driver */
3857 for (i = 0; i < info->reg_array_cnt; i++)
3858 bnxt_write_fw_reset_reg(bp, i);
3859 /* Wait for time specified by FW after triggering reset */
3860 rte_delay_ms(info->master_func_wait_period_after_reset);
3861 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3862 /* Reset with the help of Kong processor */
3863 rc = bnxt_hwrm_fw_reset(bp);
3865 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3871 static void bnxt_fw_reset_cb(void *arg)
3873 struct bnxt *bp = arg;
3874 struct bnxt_error_recovery_info *info = bp->recovery_info;
3877 /* Only Master function can do FW reset */
3878 if (bnxt_is_master_func(bp) &&
3879 bnxt_is_recovery_enabled(bp)) {
3880 rc = bnxt_fw_reset_all(bp);
3882 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3887 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3888 * EXCEPTION_FATAL_ASYNC event to all the functions
3889 * (including MASTER FUNC). After receiving this Async, all the active
3890 * drivers should treat this case as FW initiated recovery
3892 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3893 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3894 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3896 /* To recover from error */
3897 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3902 /* Driver should poll FW heartbeat, reset_counter with the frequency
3903 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3904 * When the driver detects heartbeat stop or change in reset_counter,
3905 * it has to trigger a reset to recover from the error condition.
3906 * A “master PF” is the function who will have the privilege to
3907 * initiate the chimp reset. The master PF will be elected by the
3908 * firmware and will be notified through async message.
3910 static void bnxt_check_fw_health(void *arg)
3912 struct bnxt *bp = arg;
3913 struct bnxt_error_recovery_info *info = bp->recovery_info;
3914 uint32_t val = 0, wait_msec;
3916 if (!info || !bnxt_is_recovery_enabled(bp) ||
3917 is_bnxt_in_error(bp))
3920 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3921 if (val == info->last_heart_beat)
3924 info->last_heart_beat = val;
3926 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3927 if (val != info->last_reset_counter)
3930 info->last_reset_counter = val;
3932 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3933 bnxt_check_fw_health, (void *)bp);
3937 /* Stop DMA to/from device */
3938 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3939 bp->flags |= BNXT_FLAG_FW_RESET;
3941 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3943 if (bnxt_is_master_func(bp))
3944 wait_msec = info->master_func_wait_period;
3946 wait_msec = info->normal_func_wait_period;
3948 rte_eal_alarm_set(US_PER_MS * wait_msec,
3949 bnxt_fw_reset_cb, (void *)bp);
3952 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3954 uint32_t polling_freq;
3956 pthread_mutex_lock(&bp->health_check_lock);
3958 if (!bnxt_is_recovery_enabled(bp))
3961 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3964 polling_freq = bp->recovery_info->driver_polling_freq;
3966 rte_eal_alarm_set(US_PER_MS * polling_freq,
3967 bnxt_check_fw_health, (void *)bp);
3968 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3971 pthread_mutex_unlock(&bp->health_check_lock);
3974 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3976 if (!bnxt_is_recovery_enabled(bp))
3979 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3980 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3983 static bool bnxt_vf_pciid(uint16_t device_id)
3985 switch (device_id) {
3986 case BROADCOM_DEV_ID_57304_VF:
3987 case BROADCOM_DEV_ID_57406_VF:
3988 case BROADCOM_DEV_ID_5731X_VF:
3989 case BROADCOM_DEV_ID_5741X_VF:
3990 case BROADCOM_DEV_ID_57414_VF:
3991 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
3992 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
3993 case BROADCOM_DEV_ID_58802_VF:
3994 case BROADCOM_DEV_ID_57500_VF1:
3995 case BROADCOM_DEV_ID_57500_VF2:
4003 /* Phase 5 device */
4004 static bool bnxt_p5_device(uint16_t device_id)
4006 switch (device_id) {
4007 case BROADCOM_DEV_ID_57508:
4008 case BROADCOM_DEV_ID_57504:
4009 case BROADCOM_DEV_ID_57502:
4010 case BROADCOM_DEV_ID_57508_MF1:
4011 case BROADCOM_DEV_ID_57504_MF1:
4012 case BROADCOM_DEV_ID_57502_MF1:
4013 case BROADCOM_DEV_ID_57508_MF2:
4014 case BROADCOM_DEV_ID_57504_MF2:
4015 case BROADCOM_DEV_ID_57502_MF2:
4016 case BROADCOM_DEV_ID_57500_VF1:
4017 case BROADCOM_DEV_ID_57500_VF2:
4025 bool bnxt_stratus_device(struct bnxt *bp)
4027 uint16_t device_id = bp->pdev->id.device_id;
4029 switch (device_id) {
4030 case BROADCOM_DEV_ID_STRATUS_NIC:
4031 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4032 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4040 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4042 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4043 struct bnxt *bp = eth_dev->data->dev_private;
4045 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4046 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4047 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4048 if (!bp->bar0 || !bp->doorbell_base) {
4049 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4053 bp->eth_dev = eth_dev;
4059 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4060 struct bnxt_ctx_pg_info *ctx_pg,
4065 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4066 const struct rte_memzone *mz = NULL;
4067 char mz_name[RTE_MEMZONE_NAMESIZE];
4068 rte_iova_t mz_phys_addr;
4069 uint64_t valid_bits = 0;
4076 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4078 rmem->page_size = BNXT_PAGE_SIZE;
4079 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4080 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4081 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4083 valid_bits = PTU_PTE_VALID;
4085 if (rmem->nr_pages > 1) {
4086 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4087 "bnxt_ctx_pg_tbl%s_%x_%d",
4088 suffix, idx, bp->eth_dev->data->port_id);
4089 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4090 mz = rte_memzone_lookup(mz_name);
4092 mz = rte_memzone_reserve_aligned(mz_name,
4096 RTE_MEMZONE_SIZE_HINT_ONLY |
4097 RTE_MEMZONE_IOVA_CONTIG,
4103 memset(mz->addr, 0, mz->len);
4104 mz_phys_addr = mz->iova;
4106 rmem->pg_tbl = mz->addr;
4107 rmem->pg_tbl_map = mz_phys_addr;
4108 rmem->pg_tbl_mz = mz;
4111 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4112 suffix, idx, bp->eth_dev->data->port_id);
4113 mz = rte_memzone_lookup(mz_name);
4115 mz = rte_memzone_reserve_aligned(mz_name,
4119 RTE_MEMZONE_SIZE_HINT_ONLY |
4120 RTE_MEMZONE_IOVA_CONTIG,
4126 memset(mz->addr, 0, mz->len);
4127 mz_phys_addr = mz->iova;
4129 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4130 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4131 rmem->dma_arr[i] = mz_phys_addr + sz;
4133 if (rmem->nr_pages > 1) {
4134 if (i == rmem->nr_pages - 2 &&
4135 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4136 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4137 else if (i == rmem->nr_pages - 1 &&
4138 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4139 valid_bits |= PTU_PTE_LAST;
4141 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4147 if (rmem->vmem_size)
4148 rmem->vmem = (void **)mz->addr;
4149 rmem->dma_arr[0] = mz_phys_addr;
4153 static void bnxt_free_ctx_mem(struct bnxt *bp)
4157 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4160 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4161 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4162 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4163 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4164 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4165 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4166 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4167 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4168 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4169 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4170 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4172 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4173 if (bp->ctx->tqm_mem[i])
4174 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4181 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4183 #define min_t(type, x, y) ({ \
4184 type __min1 = (x); \
4185 type __min2 = (y); \
4186 __min1 < __min2 ? __min1 : __min2; })
4188 #define max_t(type, x, y) ({ \
4189 type __max1 = (x); \
4190 type __max2 = (y); \
4191 __max1 > __max2 ? __max1 : __max2; })
4193 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4195 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4197 struct bnxt_ctx_pg_info *ctx_pg;
4198 struct bnxt_ctx_mem_info *ctx;
4199 uint32_t mem_size, ena, entries;
4200 uint32_t entries_sp, min;
4203 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4205 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4209 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4212 ctx_pg = &ctx->qp_mem;
4213 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4214 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4215 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4219 ctx_pg = &ctx->srq_mem;
4220 ctx_pg->entries = ctx->srq_max_l2_entries;
4221 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4222 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4226 ctx_pg = &ctx->cq_mem;
4227 ctx_pg->entries = ctx->cq_max_l2_entries;
4228 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4229 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4233 ctx_pg = &ctx->vnic_mem;
4234 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4235 ctx->vnic_max_ring_table_entries;
4236 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4237 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4241 ctx_pg = &ctx->stat_mem;
4242 ctx_pg->entries = ctx->stat_max_entries;
4243 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4244 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4248 min = ctx->tqm_min_entries_per_ring;
4250 entries_sp = ctx->qp_max_l2_entries +
4251 ctx->vnic_max_vnic_entries +
4252 2 * ctx->qp_min_qp1_entries + min;
4253 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4255 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4256 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4257 entries = clamp_t(uint32_t, entries, min,
4258 ctx->tqm_max_entries_per_ring);
4259 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4260 ctx_pg = ctx->tqm_mem[i];
4261 ctx_pg->entries = i ? entries : entries_sp;
4262 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4263 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4266 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4269 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4270 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4273 "Failed to configure context mem: rc = %d\n", rc);
4275 ctx->flags |= BNXT_CTX_FLAG_INITED;
4280 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4282 struct rte_pci_device *pci_dev = bp->pdev;
4283 char mz_name[RTE_MEMZONE_NAMESIZE];
4284 const struct rte_memzone *mz = NULL;
4285 uint32_t total_alloc_len;
4286 rte_iova_t mz_phys_addr;
4288 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4291 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4292 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4293 pci_dev->addr.bus, pci_dev->addr.devid,
4294 pci_dev->addr.function, "rx_port_stats");
4295 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4296 mz = rte_memzone_lookup(mz_name);
4298 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4299 sizeof(struct rx_port_stats_ext) + 512);
4301 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4304 RTE_MEMZONE_SIZE_HINT_ONLY |
4305 RTE_MEMZONE_IOVA_CONTIG);
4309 memset(mz->addr, 0, mz->len);
4310 mz_phys_addr = mz->iova;
4312 bp->rx_mem_zone = (const void *)mz;
4313 bp->hw_rx_port_stats = mz->addr;
4314 bp->hw_rx_port_stats_map = mz_phys_addr;
4316 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4317 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4318 pci_dev->addr.bus, pci_dev->addr.devid,
4319 pci_dev->addr.function, "tx_port_stats");
4320 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4321 mz = rte_memzone_lookup(mz_name);
4323 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4324 sizeof(struct tx_port_stats_ext) + 512);
4326 mz = rte_memzone_reserve(mz_name,
4330 RTE_MEMZONE_SIZE_HINT_ONLY |
4331 RTE_MEMZONE_IOVA_CONTIG);
4335 memset(mz->addr, 0, mz->len);
4336 mz_phys_addr = mz->iova;
4338 bp->tx_mem_zone = (const void *)mz;
4339 bp->hw_tx_port_stats = mz->addr;
4340 bp->hw_tx_port_stats_map = mz_phys_addr;
4341 bp->flags |= BNXT_FLAG_PORT_STATS;
4343 /* Display extended statistics if FW supports it */
4344 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4345 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4346 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4349 bp->hw_rx_port_stats_ext = (void *)
4350 ((uint8_t *)bp->hw_rx_port_stats +
4351 sizeof(struct rx_port_stats));
4352 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4353 sizeof(struct rx_port_stats);
4354 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4356 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4357 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4358 bp->hw_tx_port_stats_ext = (void *)
4359 ((uint8_t *)bp->hw_tx_port_stats +
4360 sizeof(struct tx_port_stats));
4361 bp->hw_tx_port_stats_ext_map =
4362 bp->hw_tx_port_stats_map +
4363 sizeof(struct tx_port_stats);
4364 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4370 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4372 struct bnxt *bp = eth_dev->data->dev_private;
4375 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4376 RTE_ETHER_ADDR_LEN *
4379 if (eth_dev->data->mac_addrs == NULL) {
4380 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4384 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4388 /* Generate a random MAC address, if none was assigned by PF */
4389 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4390 bnxt_eth_hw_addr_random(bp->mac_addr);
4392 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4393 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4394 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4396 rc = bnxt_hwrm_set_mac(bp);
4401 /* Copy the permanent MAC from the FUNC_QCAPS response */
4402 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4407 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4411 /* MAC is already configured in FW */
4412 if (BNXT_HAS_DFLT_MAC_SET(bp))
4415 /* Restore the old MAC configured */
4416 rc = bnxt_hwrm_set_mac(bp);
4418 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4423 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4428 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4430 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4431 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4432 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4433 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4434 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4435 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4439 bnxt_get_svif(uint16_t port_id, bool func_svif,
4440 enum bnxt_ulp_intf_type type)
4442 struct rte_eth_dev *eth_dev;
4445 eth_dev = &rte_eth_devices[port_id];
4446 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4447 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4451 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4454 eth_dev = vfr->parent_dev;
4457 bp = eth_dev->data->dev_private;
4459 return func_svif ? bp->func_svif : bp->port_svif;
4463 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4465 struct rte_eth_dev *eth_dev;
4466 struct bnxt_vnic_info *vnic;
4469 eth_dev = &rte_eth_devices[port];
4470 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4471 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4475 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4476 return vfr->dflt_vnic_id;
4478 eth_dev = vfr->parent_dev;
4481 bp = eth_dev->data->dev_private;
4483 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4485 return vnic->fw_vnic_id;
4489 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4491 struct rte_eth_dev *eth_dev;
4494 eth_dev = &rte_eth_devices[port];
4495 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4496 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4500 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4503 eth_dev = vfr->parent_dev;
4506 bp = eth_dev->data->dev_private;
4511 enum bnxt_ulp_intf_type
4512 bnxt_get_interface_type(uint16_t port)
4514 struct rte_eth_dev *eth_dev;
4517 eth_dev = &rte_eth_devices[port];
4518 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4519 return BNXT_ULP_INTF_TYPE_VF_REP;
4521 bp = eth_dev->data->dev_private;
4523 return BNXT_ULP_INTF_TYPE_PF;
4524 else if (BNXT_VF_IS_TRUSTED(bp))
4525 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4526 else if (BNXT_VF(bp))
4527 return BNXT_ULP_INTF_TYPE_VF;
4529 return BNXT_ULP_INTF_TYPE_INVALID;
4533 bnxt_get_phy_port_id(uint16_t port_id)
4535 struct bnxt_representor *vfr;
4536 struct rte_eth_dev *eth_dev;
4539 eth_dev = &rte_eth_devices[port_id];
4540 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4541 vfr = eth_dev->data->dev_private;
4545 eth_dev = vfr->parent_dev;
4548 bp = eth_dev->data->dev_private;
4550 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4554 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4556 struct rte_eth_dev *eth_dev;
4559 eth_dev = &rte_eth_devices[port_id];
4560 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4561 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4565 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4566 return vfr->fw_fid - 1;
4568 eth_dev = vfr->parent_dev;
4571 bp = eth_dev->data->dev_private;
4573 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4577 bnxt_get_vport(uint16_t port_id)
4579 return (1 << bnxt_get_phy_port_id(port_id));
4582 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4584 struct bnxt_error_recovery_info *info = bp->recovery_info;
4587 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4588 memset(info, 0, sizeof(*info));
4592 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4595 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4598 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4600 bp->recovery_info = info;
4603 static void bnxt_check_fw_status(struct bnxt *bp)
4607 if (!(bp->recovery_info &&
4608 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4611 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4612 if (fw_status != BNXT_FW_STATUS_HEALTHY)
4613 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4617 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4619 struct bnxt_error_recovery_info *info = bp->recovery_info;
4620 uint32_t status_loc;
4623 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4624 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4625 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4626 BNXT_GRCP_WINDOW_2_BASE +
4627 offsetof(struct hcomm_status,
4629 /* If the signature is absent, then FW does not support this feature */
4630 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4631 HCOMM_STATUS_SIGNATURE_VAL)
4635 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4639 bp->recovery_info = info;
4641 memset(info, 0, sizeof(*info));
4644 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4645 BNXT_GRCP_WINDOW_2_BASE +
4646 offsetof(struct hcomm_status,
4649 /* Only pre-map the FW health status GRC register */
4650 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4653 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4654 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4655 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4657 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4658 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4660 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4665 static int bnxt_init_fw(struct bnxt *bp)
4672 rc = bnxt_map_hcomm_fw_status_reg(bp);
4676 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4678 bnxt_check_fw_status(bp);
4682 rc = bnxt_hwrm_func_reset(bp);
4686 rc = bnxt_hwrm_vnic_qcaps(bp);
4690 rc = bnxt_hwrm_queue_qportcfg(bp);
4694 /* Get the MAX capabilities for this function.
4695 * This function also allocates context memory for TQM rings and
4696 * informs the firmware about this allocated backing store memory.
4698 rc = bnxt_hwrm_func_qcaps(bp);
4702 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4706 bnxt_hwrm_port_mac_qcfg(bp);
4708 bnxt_hwrm_parent_pf_qcfg(bp);
4710 bnxt_hwrm_port_phy_qcaps(bp);
4712 bnxt_alloc_error_recovery_info(bp);
4713 /* Get the adapter error recovery support info */
4714 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4716 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4718 bnxt_hwrm_port_led_qcaps(bp);
4724 bnxt_init_locks(struct bnxt *bp)
4728 err = pthread_mutex_init(&bp->flow_lock, NULL);
4730 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4734 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4736 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4740 err = pthread_mutex_init(&bp->health_check_lock, NULL);
4742 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4746 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4750 rc = bnxt_init_fw(bp);
4754 if (!reconfig_dev) {
4755 rc = bnxt_setup_mac_addr(bp->eth_dev);
4759 rc = bnxt_restore_dflt_mac(bp);
4764 bnxt_config_vf_req_fwd(bp);
4766 rc = bnxt_hwrm_func_driver_register(bp);
4768 PMD_DRV_LOG(ERR, "Failed to register driver");
4773 if (bp->pdev->max_vfs) {
4774 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4776 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4780 rc = bnxt_hwrm_allocate_pf_only(bp);
4783 "Failed to allocate PF resources");
4789 rc = bnxt_alloc_mem(bp, reconfig_dev);
4793 rc = bnxt_setup_int(bp);
4797 rc = bnxt_request_int(bp);
4801 rc = bnxt_init_ctx_mem(bp);
4803 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4807 rc = bnxt_init_locks(bp);
4815 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4816 const char *value, void *opaque_arg)
4818 struct bnxt *bp = opaque_arg;
4819 unsigned long truflow;
4822 if (!value || !opaque_arg) {
4824 "Invalid parameter passed to truflow devargs.\n");
4828 truflow = strtoul(value, &end, 10);
4829 if (end == NULL || *end != '\0' ||
4830 (truflow == ULONG_MAX && errno == ERANGE)) {
4832 "Invalid parameter passed to truflow devargs.\n");
4836 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4838 "Invalid value passed to truflow devargs.\n");
4843 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4844 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4846 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4847 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4854 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4855 const char *value, void *opaque_arg)
4857 struct bnxt *bp = opaque_arg;
4858 unsigned long flow_xstat;
4861 if (!value || !opaque_arg) {
4863 "Invalid parameter passed to flow_xstat devarg.\n");
4867 flow_xstat = strtoul(value, &end, 10);
4868 if (end == NULL || *end != '\0' ||
4869 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4871 "Invalid parameter passed to flow_xstat devarg.\n");
4875 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4877 "Invalid value passed to flow_xstat devarg.\n");
4881 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4882 if (BNXT_FLOW_XSTATS_EN(bp))
4883 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4889 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4890 const char *value, void *opaque_arg)
4892 struct bnxt *bp = opaque_arg;
4893 unsigned long max_num_kflows;
4896 if (!value || !opaque_arg) {
4898 "Invalid parameter passed to max_num_kflows devarg.\n");
4902 max_num_kflows = strtoul(value, &end, 10);
4903 if (end == NULL || *end != '\0' ||
4904 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4906 "Invalid parameter passed to max_num_kflows devarg.\n");
4910 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4912 "Invalid value passed to max_num_kflows devarg.\n");
4916 bp->max_num_kflows = max_num_kflows;
4917 if (bp->max_num_kflows)
4918 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
4925 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
4926 const char *value, void *opaque_arg)
4928 struct bnxt_representor *vfr_bp = opaque_arg;
4929 unsigned long rep_is_pf;
4932 if (!value || !opaque_arg) {
4934 "Invalid parameter passed to rep_is_pf devargs.\n");
4938 rep_is_pf = strtoul(value, &end, 10);
4939 if (end == NULL || *end != '\0' ||
4940 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
4942 "Invalid parameter passed to rep_is_pf devargs.\n");
4946 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
4948 "Invalid value passed to rep_is_pf devargs.\n");
4952 vfr_bp->flags |= rep_is_pf;
4953 if (BNXT_REP_PF(vfr_bp))
4954 PMD_DRV_LOG(INFO, "PF representor\n");
4956 PMD_DRV_LOG(INFO, "VF representor\n");
4962 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
4963 const char *value, void *opaque_arg)
4965 struct bnxt_representor *vfr_bp = opaque_arg;
4966 unsigned long rep_based_pf;
4969 if (!value || !opaque_arg) {
4971 "Invalid parameter passed to rep_based_pf "
4976 rep_based_pf = strtoul(value, &end, 10);
4977 if (end == NULL || *end != '\0' ||
4978 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
4980 "Invalid parameter passed to rep_based_pf "
4985 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
4987 "Invalid value passed to rep_based_pf devargs.\n");
4991 vfr_bp->rep_based_pf = rep_based_pf;
4992 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
4994 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5000 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5001 const char *value, void *opaque_arg)
5003 struct bnxt_representor *vfr_bp = opaque_arg;
5004 unsigned long rep_q_r2f;
5007 if (!value || !opaque_arg) {
5009 "Invalid parameter passed to rep_q_r2f "
5014 rep_q_r2f = strtoul(value, &end, 10);
5015 if (end == NULL || *end != '\0' ||
5016 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5018 "Invalid parameter passed to rep_q_r2f "
5023 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5025 "Invalid value passed to rep_q_r2f devargs.\n");
5029 vfr_bp->rep_q_r2f = rep_q_r2f;
5030 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5031 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5037 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5038 const char *value, void *opaque_arg)
5040 struct bnxt_representor *vfr_bp = opaque_arg;
5041 unsigned long rep_q_f2r;
5044 if (!value || !opaque_arg) {
5046 "Invalid parameter passed to rep_q_f2r "
5051 rep_q_f2r = strtoul(value, &end, 10);
5052 if (end == NULL || *end != '\0' ||
5053 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5055 "Invalid parameter passed to rep_q_f2r "
5060 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5062 "Invalid value passed to rep_q_f2r devargs.\n");
5066 vfr_bp->rep_q_f2r = rep_q_f2r;
5067 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5068 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5074 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5075 const char *value, void *opaque_arg)
5077 struct bnxt_representor *vfr_bp = opaque_arg;
5078 unsigned long rep_fc_r2f;
5081 if (!value || !opaque_arg) {
5083 "Invalid parameter passed to rep_fc_r2f "
5088 rep_fc_r2f = strtoul(value, &end, 10);
5089 if (end == NULL || *end != '\0' ||
5090 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5092 "Invalid parameter passed to rep_fc_r2f "
5097 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5099 "Invalid value passed to rep_fc_r2f devargs.\n");
5103 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5104 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5105 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5111 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5112 const char *value, void *opaque_arg)
5114 struct bnxt_representor *vfr_bp = opaque_arg;
5115 unsigned long rep_fc_f2r;
5118 if (!value || !opaque_arg) {
5120 "Invalid parameter passed to rep_fc_f2r "
5125 rep_fc_f2r = strtoul(value, &end, 10);
5126 if (end == NULL || *end != '\0' ||
5127 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5129 "Invalid parameter passed to rep_fc_f2r "
5134 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5136 "Invalid value passed to rep_fc_f2r devargs.\n");
5140 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5141 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5142 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5148 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5150 struct rte_kvargs *kvlist;
5152 if (devargs == NULL)
5155 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5160 * Handler for "truflow" devarg.
5161 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5163 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5164 bnxt_parse_devarg_truflow, bp);
5167 * Handler for "flow_xstat" devarg.
5168 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5170 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5171 bnxt_parse_devarg_flow_xstat, bp);
5174 * Handler for "max_num_kflows" devarg.
5175 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5177 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5178 bnxt_parse_devarg_max_num_kflows, bp);
5180 rte_kvargs_free(kvlist);
5183 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5187 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5188 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5191 "Failed to alloc switch domain: %d\n", rc);
5194 "Switch domain allocated %d\n",
5195 bp->switch_domain_id);
5202 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5204 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5205 static int version_printed;
5209 if (version_printed++ == 0)
5210 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5212 eth_dev->dev_ops = &bnxt_dev_ops;
5213 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5214 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5215 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5216 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5217 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5220 * For secondary processes, we don't initialise any further
5221 * as primary has already done this work.
5223 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5226 rte_eth_copy_pci_info(eth_dev, pci_dev);
5227 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5229 bp = eth_dev->data->dev_private;
5231 /* Parse dev arguments passed on when starting the DPDK application. */
5232 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5234 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5236 if (bnxt_vf_pciid(pci_dev->id.device_id))
5237 bp->flags |= BNXT_FLAG_VF;
5239 if (bnxt_p5_device(pci_dev->id.device_id))
5240 bp->flags |= BNXT_FLAG_CHIP_P5;
5242 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5243 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5244 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5245 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5246 bp->flags |= BNXT_FLAG_STINGRAY;
5248 if (BNXT_TRUFLOW_EN(bp)) {
5249 /* extra mbuf field is required to store CFA code from mark */
5250 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5251 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5252 .size = sizeof(bnxt_cfa_code_dynfield_t),
5253 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5255 bnxt_cfa_code_dynfield_offset =
5256 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5257 if (bnxt_cfa_code_dynfield_offset < 0) {
5259 "Failed to register mbuf field for TruFlow mark\n");
5264 rc = bnxt_init_board(eth_dev);
5267 "Failed to initialize board rc: %x\n", rc);
5271 rc = bnxt_alloc_pf_info(bp);
5275 rc = bnxt_alloc_link_info(bp);
5279 rc = bnxt_alloc_parent_info(bp);
5283 rc = bnxt_alloc_hwrm_resources(bp);
5286 "Failed to allocate hwrm resource rc: %x\n", rc);
5289 rc = bnxt_alloc_leds_info(bp);
5293 rc = bnxt_alloc_cos_queues(bp);
5297 rc = bnxt_init_resources(bp, false);
5301 rc = bnxt_alloc_stats_mem(bp);
5305 bnxt_alloc_switch_domain(bp);
5308 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5309 pci_dev->mem_resource[0].phys_addr,
5310 pci_dev->mem_resource[0].addr);
5315 bnxt_dev_uninit(eth_dev);
5320 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5329 ctx->dma = RTE_BAD_IOVA;
5330 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5333 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5335 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5336 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5337 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5338 bp->flow_stat->max_fc,
5341 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5342 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5343 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5344 bp->flow_stat->max_fc,
5347 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5348 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5349 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5351 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5352 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5353 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5355 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5356 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5357 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5359 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5360 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5361 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5364 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5366 bnxt_unregister_fc_ctx_mem(bp);
5368 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5369 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5370 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5371 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5374 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5376 if (BNXT_FLOW_XSTATS_EN(bp))
5377 bnxt_uninit_fc_ctx_mem(bp);
5381 bnxt_free_error_recovery_info(struct bnxt *bp)
5383 rte_free(bp->recovery_info);
5384 bp->recovery_info = NULL;
5385 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5389 bnxt_uninit_locks(struct bnxt *bp)
5391 pthread_mutex_destroy(&bp->flow_lock);
5392 pthread_mutex_destroy(&bp->def_cp_lock);
5393 pthread_mutex_destroy(&bp->health_check_lock);
5395 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5396 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5401 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5406 bnxt_free_mem(bp, reconfig_dev);
5408 bnxt_hwrm_func_buf_unrgtr(bp);
5409 rte_free(bp->pf->vf_req_buf);
5411 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5412 bp->flags &= ~BNXT_FLAG_REGISTERED;
5413 bnxt_free_ctx_mem(bp);
5414 if (!reconfig_dev) {
5415 bnxt_free_hwrm_resources(bp);
5416 bnxt_free_error_recovery_info(bp);
5419 bnxt_uninit_ctx_mem(bp);
5421 bnxt_uninit_locks(bp);
5422 bnxt_free_flow_stats_info(bp);
5423 bnxt_free_rep_info(bp);
5424 rte_free(bp->ptp_cfg);
5430 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5432 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5435 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5437 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5438 bnxt_dev_close_op(eth_dev);
5443 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5445 struct bnxt *bp = eth_dev->data->dev_private;
5446 struct rte_eth_dev *vf_rep_eth_dev;
5452 for (i = 0; i < bp->num_reps; i++) {
5453 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5454 if (!vf_rep_eth_dev)
5456 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5457 vf_rep_eth_dev->data->port_id);
5458 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5460 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5461 eth_dev->data->port_id);
5462 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5467 static void bnxt_free_rep_info(struct bnxt *bp)
5469 rte_free(bp->rep_info);
5470 bp->rep_info = NULL;
5471 rte_free(bp->cfa_code_map);
5472 bp->cfa_code_map = NULL;
5475 static int bnxt_init_rep_info(struct bnxt *bp)
5482 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5483 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5485 if (!bp->rep_info) {
5486 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5489 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5490 sizeof(*bp->cfa_code_map) *
5491 BNXT_MAX_CFA_CODE, 0);
5492 if (!bp->cfa_code_map) {
5493 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5494 bnxt_free_rep_info(bp);
5498 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5499 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5501 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5503 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5504 bnxt_free_rep_info(bp);
5508 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5510 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5511 bnxt_free_rep_info(bp);
5518 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5519 struct rte_eth_devargs *eth_da,
5520 struct rte_eth_dev *backing_eth_dev,
5521 const char *dev_args)
5523 struct rte_eth_dev *vf_rep_eth_dev;
5524 char name[RTE_ETH_NAME_MAX_LEN];
5525 struct bnxt *backing_bp;
5528 struct rte_kvargs *kvlist = NULL;
5530 num_rep = eth_da->nb_representor_ports;
5531 if (num_rep > BNXT_MAX_VF_REPS) {
5532 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5533 num_rep, BNXT_MAX_VF_REPS);
5537 if (num_rep >= RTE_MAX_ETHPORTS) {
5539 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5540 num_rep, RTE_MAX_ETHPORTS);
5544 backing_bp = backing_eth_dev->data->dev_private;
5546 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5548 "Not a PF or trusted VF. No Representor support\n");
5549 /* Returning an error is not an option.
5550 * Applications are not handling this correctly
5555 if (bnxt_init_rep_info(backing_bp))
5558 for (i = 0; i < num_rep; i++) {
5559 struct bnxt_representor representor = {
5560 .vf_id = eth_da->representor_ports[i],
5561 .switch_domain_id = backing_bp->switch_domain_id,
5562 .parent_dev = backing_eth_dev
5565 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5566 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5567 representor.vf_id, BNXT_MAX_VF_REPS);
5571 /* representor port net_bdf_port */
5572 snprintf(name, sizeof(name), "net_%s_representor_%d",
5573 pci_dev->device.name, eth_da->representor_ports[i]);
5575 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5578 * Handler for "rep_is_pf" devarg.
5579 * Invoked as for ex: "-a 000:00:0d.0,
5580 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5582 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5583 bnxt_parse_devarg_rep_is_pf,
5584 (void *)&representor);
5590 * Handler for "rep_based_pf" devarg.
5591 * Invoked as for ex: "-a 000:00:0d.0,
5592 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5594 ret = rte_kvargs_process(kvlist,
5595 BNXT_DEVARG_REP_BASED_PF,
5596 bnxt_parse_devarg_rep_based_pf,
5597 (void *)&representor);
5603 * Handler for "rep_based_pf" devarg.
5604 * Invoked as for ex: "-a 000:00:0d.0,
5605 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5607 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5608 bnxt_parse_devarg_rep_q_r2f,
5609 (void *)&representor);
5615 * Handler for "rep_based_pf" devarg.
5616 * Invoked as for ex: "-a 000:00:0d.0,
5617 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5619 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5620 bnxt_parse_devarg_rep_q_f2r,
5621 (void *)&representor);
5627 * Handler for "rep_based_pf" devarg.
5628 * Invoked as for ex: "-a 000:00:0d.0,
5629 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5631 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5632 bnxt_parse_devarg_rep_fc_r2f,
5633 (void *)&representor);
5639 * Handler for "rep_based_pf" devarg.
5640 * Invoked as for ex: "-a 000:00:0d.0,
5641 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5643 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5644 bnxt_parse_devarg_rep_fc_f2r,
5645 (void *)&representor);
5652 ret = rte_eth_dev_create(&pci_dev->device, name,
5653 sizeof(struct bnxt_representor),
5655 bnxt_representor_init,
5658 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5659 "representor %s.", name);
5663 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5664 if (!vf_rep_eth_dev) {
5665 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5666 " for VF-Rep: %s.", name);
5671 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5672 backing_eth_dev->data->port_id);
5673 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5675 backing_bp->num_reps++;
5679 rte_kvargs_free(kvlist);
5683 /* If num_rep > 1, then rollback already created
5684 * ports, since we'll be failing the probe anyway
5687 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5689 rte_kvargs_free(kvlist);
5694 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5695 struct rte_pci_device *pci_dev)
5697 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5698 struct rte_eth_dev *backing_eth_dev;
5702 if (pci_dev->device.devargs) {
5703 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5709 num_rep = eth_da.nb_representor_ports;
5710 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5713 /* We could come here after first level of probe is already invoked
5714 * as part of an application bringup(OVS-DPDK vswitchd), so first check
5715 * for already allocated eth_dev for the backing device (PF/Trusted VF)
5717 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5718 if (backing_eth_dev == NULL) {
5719 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5720 sizeof(struct bnxt),
5721 eth_dev_pci_specific_init, pci_dev,
5722 bnxt_dev_init, NULL);
5724 if (ret || !num_rep)
5727 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5729 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5730 backing_eth_dev->data->port_id);
5735 /* probe representor ports now */
5736 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
5737 pci_dev->device.devargs->args);
5742 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5744 struct rte_eth_dev *eth_dev;
5746 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5748 return 0; /* Invoked typically only by OVS-DPDK, by the
5749 * time it comes here the eth_dev is already
5750 * deleted by rte_eth_dev_close(), so returning
5751 * +ve value will at least help in proper cleanup
5754 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5755 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5756 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5757 return rte_eth_dev_destroy(eth_dev,
5758 bnxt_representor_uninit);
5760 return rte_eth_dev_destroy(eth_dev,
5763 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5767 static struct rte_pci_driver bnxt_rte_pmd = {
5768 .id_table = bnxt_pci_id_map,
5769 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5770 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5773 .probe = bnxt_pci_probe,
5774 .remove = bnxt_pci_remove,
5778 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5780 if (strcmp(dev->device->driver->name, drv->driver.name))
5786 bool is_bnxt_supported(struct rte_eth_dev *dev)
5788 return is_device_supported(dev, &bnxt_rte_pmd);
5791 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5792 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5793 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5794 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");