drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  97         { .vendor_id = 0, /* sentinel */ },
  98 };
  99
 100 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 101 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 102 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 103 #define BNXT_DEVARG_REPRESENTOR "representor"
 104 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
 105 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
 106 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
 107 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
 108 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
 109 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 110
 111 static const char *const bnxt_dev_args[] = {
 112         BNXT_DEVARG_REPRESENTOR,
 113         BNXT_DEVARG_TRUFLOW,
 114         BNXT_DEVARG_FLOW_XSTAT,
 115         BNXT_DEVARG_MAX_NUM_KFLOWS,
 116         BNXT_DEVARG_REP_BASED_PF,
 117         BNXT_DEVARG_REP_IS_PF,
 118         BNXT_DEVARG_REP_Q_R2F,
 119         BNXT_DEVARG_REP_Q_F2R,
 120         BNXT_DEVARG_REP_FC_R2F,
 121         BNXT_DEVARG_REP_FC_F2R,
 122         NULL
 123 };
 124
 125 /*
 126  * truflow == false to disable the feature
 127  * truflow == true to enable the feature
 128  */
 129 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 130
 131 /*
 132  * flow_xstat == false to disable the feature
 133  * flow_xstat == true to enable the feature
 134  */
 135 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 136
 137 /*
 138  * rep_is_pf == false to indicate VF representor
 139  * rep_is_pf == true to indicate PF representor
 140  */
 141 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 142
 143 /*
 144  * rep_based_pf == Physical index of the PF
 145  */
 146 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 147 /*
 148  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 151
 152 /*
 153  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 154  */
 155 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 156
 157 /*
 158  * rep_fc_r2f == Flow control for the representor to endpoint direction
 159  */
 160 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 161
 162 /*
 163  * rep_fc_f2r == Flow control for the endpoint to representor direction
 164  */
 165 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 166
 167 int bnxt_cfa_code_dynfield_offset = -1;
 168
 169 /*
 170  * max_num_kflows must be >= 32
 171  * and must be a power-of-2 supported value
 172  * return: 1 -> invalid
 173  *         0 -> valid
 174  */
 175 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 176 {
 177         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 178                 return 1;
 179         return 0;
 180 }
 181
 182 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 183 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 184 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 185 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 186 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 187 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 188 static void bnxt_dev_recover(void *arg);
 189 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 190 static void bnxt_free_rep_info(struct bnxt *bp);
 191
 192 int is_bnxt_in_error(struct bnxt *bp)
 193 {
 194         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 195                 return -EIO;
 196         if (bp->flags & BNXT_FLAG_FW_RESET)
 197                 return -EBUSY;
 198
 199         return 0;
 200 }
 201
 202 /***********************/
 203
 204 /*
 205  * High level utility functions
 206  */
 207
 208 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 209 {
 210         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 211                                              BNXT_RSS_TBL_SIZE_P5);
 212
 213         if (!BNXT_CHIP_P5(bp))
 214                 return 1;
 215
 216         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 217                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 218                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 219 }
 220
 221 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 222 {
 223         if (!BNXT_CHIP_P5(bp))
 224                 return HW_HASH_INDEX_SIZE;
 225
 226         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 227 }
 228
 229 static void bnxt_free_parent_info(struct bnxt *bp)
 230 {
 231         rte_free(bp->parent);
 232 }
 233
 234 static void bnxt_free_pf_info(struct bnxt *bp)
 235 {
 236         rte_free(bp->pf);
 237 }
 238
 239 static void bnxt_free_link_info(struct bnxt *bp)
 240 {
 241         rte_free(bp->link_info);
 242 }
 243
 244 static void bnxt_free_leds_info(struct bnxt *bp)
 245 {
 246         if (BNXT_VF(bp))
 247                 return;
 248
 249         rte_free(bp->leds);
 250         bp->leds = NULL;
 251 }
 252
 253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 254 {
 255         rte_free(bp->flow_stat);
 256         bp->flow_stat = NULL;
 257 }
 258
 259 static void bnxt_free_cos_queues(struct bnxt *bp)
 260 {
 261         rte_free(bp->rx_cos_queue);
 262         rte_free(bp->tx_cos_queue);
 263 }
 264
 265 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 266 {
 267         bnxt_free_filter_mem(bp);
 268         bnxt_free_vnic_attributes(bp);
 269         bnxt_free_vnic_mem(bp);
 270
 271         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 272          * If the number of rings change across fw update,
 273          * we don't have much choice except to warn the user.
 274          */
 275         if (!reconfig) {
 276                 bnxt_free_stats(bp);
 277                 bnxt_free_tx_rings(bp);
 278                 bnxt_free_rx_rings(bp);
 279         }
 280         bnxt_free_async_cp_ring(bp);
 281         bnxt_free_rxtx_nq_ring(bp);
 282
 283         rte_free(bp->grp_info);
 284         bp->grp_info = NULL;
 285 }
 286
 287 static int bnxt_alloc_parent_info(struct bnxt *bp)
 288 {
 289         bp->parent = rte_zmalloc("bnxt_parent_info",
 290                                  sizeof(struct bnxt_parent_info), 0);
 291         if (bp->parent == NULL)
 292                 return -ENOMEM;
 293
 294         return 0;
 295 }
 296
 297 static int bnxt_alloc_pf_info(struct bnxt *bp)
 298 {
 299         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 300         if (bp->pf == NULL)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int bnxt_alloc_link_info(struct bnxt *bp)
 307 {
 308         bp->link_info =
 309                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 310         if (bp->link_info == NULL)
 311                 return -ENOMEM;
 312
 313         return 0;
 314 }
 315
 316 static int bnxt_alloc_leds_info(struct bnxt *bp)
 317 {
 318         if (BNXT_VF(bp))
 319                 return 0;
 320
 321         bp->leds = rte_zmalloc("bnxt_leds",
 322                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 323                                0);
 324         if (bp->leds == NULL)
 325                 return -ENOMEM;
 326
 327         return 0;
 328 }
 329
 330 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 331 {
 332         bp->rx_cos_queue =
 333                 rte_zmalloc("bnxt_rx_cosq",
 334                             BNXT_COS_QUEUE_COUNT *
 335                             sizeof(struct bnxt_cos_queue_info),
 336                             0);
 337         if (bp->rx_cos_queue == NULL)
 338                 return -ENOMEM;
 339
 340         bp->tx_cos_queue =
 341                 rte_zmalloc("bnxt_tx_cosq",
 342                             BNXT_COS_QUEUE_COUNT *
 343                             sizeof(struct bnxt_cos_queue_info),
 344                             0);
 345         if (bp->tx_cos_queue == NULL)
 346                 return -ENOMEM;
 347
 348         return 0;
 349 }
 350
 351 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 352 {
 353         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 354                                     sizeof(struct bnxt_flow_stat_info), 0);
 355         if (bp->flow_stat == NULL)
 356                 return -ENOMEM;
 357
 358         return 0;
 359 }
 360
 361 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 362 {
 363         int rc;
 364
 365         rc = bnxt_alloc_ring_grps(bp);
 366         if (rc)
 367                 goto alloc_mem_err;
 368
 369         rc = bnxt_alloc_async_ring_struct(bp);
 370         if (rc)
 371                 goto alloc_mem_err;
 372
 373         rc = bnxt_alloc_vnic_mem(bp);
 374         if (rc)
 375                 goto alloc_mem_err;
 376
 377         rc = bnxt_alloc_vnic_attributes(bp);
 378         if (rc)
 379                 goto alloc_mem_err;
 380
 381         rc = bnxt_alloc_filter_mem(bp);
 382         if (rc)
 383                 goto alloc_mem_err;
 384
 385         rc = bnxt_alloc_async_cp_ring(bp);
 386         if (rc)
 387                 goto alloc_mem_err;
 388
 389         rc = bnxt_alloc_rxtx_nq_ring(bp);
 390         if (rc)
 391                 goto alloc_mem_err;
 392
 393         if (BNXT_FLOW_XSTATS_EN(bp)) {
 394                 rc = bnxt_alloc_flow_stats_info(bp);
 395                 if (rc)
 396                         goto alloc_mem_err;
 397         }
 398
 399         return 0;
 400
 401 alloc_mem_err:
 402         bnxt_free_mem(bp, reconfig);
 403         return rc;
 404 }
 405
 406 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 407 {
 408         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 409         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 410         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 411         struct bnxt_rx_queue *rxq;
 412         unsigned int j;
 413         int rc;
 414
 415         rc = bnxt_vnic_grp_alloc(bp, vnic);
 416         if (rc)
 417                 goto err_out;
 418
 419         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 420                     vnic_id, vnic, vnic->fw_grp_ids);
 421
 422         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 423         if (rc)
 424                 goto err_out;
 425
 426         /* Alloc RSS context only if RSS mode is enabled */
 427         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 428                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 429
 430                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 431                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 432                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 433                         PMD_DRV_LOG(ERR,
 434                                     "Only queues 0-%d will be in RSS table\n",
 435                                     BNXT_RSS_TBL_SIZE_P5 - 1);
 436                 }
 437
 438                 rc = 0;
 439                 for (j = 0; j < nr_ctxs; j++) {
 440                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 441                         if (rc)
 442                                 break;
 443                 }
 444                 if (rc) {
 445                         PMD_DRV_LOG(ERR,
 446                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 447                                     vnic_id, j, rc);
 448                         goto err_out;
 449                 }
 450                 vnic->num_lb_ctxts = nr_ctxs;
 451         }
 452
 453         /*
 454          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 455          * setting is not available at this time, it will not be
 456          * configured correctly in the CFA.
 457          */
 458         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 459                 vnic->vlan_strip = true;
 460         else
 461                 vnic->vlan_strip = false;
 462
 463         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 464         if (rc)
 465                 goto err_out;
 466
 467         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 468         if (rc)
 469                 goto err_out;
 470
 471         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 472                 rxq = bp->eth_dev->data->rx_queues[j];
 473
 474                 PMD_DRV_LOG(DEBUG,
 475                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 476                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 477
 478                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 479                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 480                 else
 481                         vnic->rx_queue_cnt++;
 482         }
 483
 484         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 485
 486         rc = bnxt_vnic_rss_configure(bp, vnic);
 487         if (rc)
 488                 goto err_out;
 489
 490         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 491
 492         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 493                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 494         else
 495                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 496
 497         return 0;
 498 err_out:
 499         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 500                     vnic_id, rc);
 501         return rc;
 502 }
 503
 504 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 505 {
 506         int rc = 0;
 507
 508         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 509                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 510         if (rc)
 511                 return rc;
 512
 513         PMD_DRV_LOG(DEBUG,
 514                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 515                     " rx_fc_in_tbl.ctx_id = %d\n",
 516                     bp->flow_stat->rx_fc_in_tbl.va,
 517                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 518                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 519
 520         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 521                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 522         if (rc)
 523                 return rc;
 524
 525         PMD_DRV_LOG(DEBUG,
 526                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 527                     " rx_fc_out_tbl.ctx_id = %d\n",
 528                     bp->flow_stat->rx_fc_out_tbl.va,
 529                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 530                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 531
 532         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 533                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 534         if (rc)
 535                 return rc;
 536
 537         PMD_DRV_LOG(DEBUG,
 538                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 539                     " tx_fc_in_tbl.ctx_id = %d\n",
 540                     bp->flow_stat->tx_fc_in_tbl.va,
 541                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 542                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 543
 544         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 545                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 546         if (rc)
 547                 return rc;
 548
 549         PMD_DRV_LOG(DEBUG,
 550                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 551                     " tx_fc_out_tbl.ctx_id = %d\n",
 552                     bp->flow_stat->tx_fc_out_tbl.va,
 553                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 554                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 555
 556         memset(bp->flow_stat->rx_fc_out_tbl.va,
 557                0,
 558                bp->flow_stat->rx_fc_out_tbl.size);
 559         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 560                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 561                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 562                                        bp->flow_stat->max_fc,
 563                                        true);
 564         if (rc)
 565                 return rc;
 566
 567         memset(bp->flow_stat->tx_fc_out_tbl.va,
 568                0,
 569                bp->flow_stat->tx_fc_out_tbl.size);
 570         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 571                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 572                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 573                                        bp->flow_stat->max_fc,
 574                                        true);
 575
 576         return rc;
 577 }
 578
 579 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 580                                   struct bnxt_ctx_mem_buf_info *ctx)
 581 {
 582         if (!ctx)
 583                 return -EINVAL;
 584
 585         ctx->va = rte_zmalloc(type, size, 0);
 586         if (ctx->va == NULL)
 587                 return -ENOMEM;
 588         rte_mem_lock_page(ctx->va);
 589         ctx->size = size;
 590         ctx->dma = rte_mem_virt2iova(ctx->va);
 591         if (ctx->dma == RTE_BAD_IOVA)
 592                 return -ENOMEM;
 593
 594         return 0;
 595 }
 596
 597 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 598 {
 599         struct rte_pci_device *pdev = bp->pdev;
 600         char type[RTE_MEMZONE_NAMESIZE];
 601         uint16_t max_fc;
 602         int rc = 0;
 603
 604         max_fc = bp->flow_stat->max_fc;
 605
 606         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 607                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 608         /* 4 bytes for each counter-id */
 609         rc = bnxt_alloc_ctx_mem_buf(type,
 610                                     max_fc * 4,
 611                                     &bp->flow_stat->rx_fc_in_tbl);
 612         if (rc)
 613                 return rc;
 614
 615         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 616                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 617         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 618         rc = bnxt_alloc_ctx_mem_buf(type,
 619                                     max_fc * 16,
 620                                     &bp->flow_stat->rx_fc_out_tbl);
 621         if (rc)
 622                 return rc;
 623
 624         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 625                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 626         /* 4 bytes for each counter-id */
 627         rc = bnxt_alloc_ctx_mem_buf(type,
 628                                     max_fc * 4,
 629                                     &bp->flow_stat->tx_fc_in_tbl);
 630         if (rc)
 631                 return rc;
 632
 633         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 634                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 635         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 636         rc = bnxt_alloc_ctx_mem_buf(type,
 637                                     max_fc * 16,
 638                                     &bp->flow_stat->tx_fc_out_tbl);
 639         if (rc)
 640                 return rc;
 641
 642         rc = bnxt_register_fc_ctx_mem(bp);
 643
 644         return rc;
 645 }
 646
 647 static int bnxt_init_ctx_mem(struct bnxt *bp)
 648 {
 649         int rc = 0;
 650
 651         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 652             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 653             !BNXT_FLOW_XSTATS_EN(bp))
 654                 return 0;
 655
 656         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 657         if (rc)
 658                 return rc;
 659
 660         rc = bnxt_init_fc_ctx_mem(bp);
 661
 662         return rc;
 663 }
 664
 665 static int bnxt_update_phy_setting(struct bnxt *bp)
 666 {
 667         struct rte_eth_link new;
 668         int rc;
 669
 670         rc = bnxt_get_hwrm_link_config(bp, &new);
 671         if (rc) {
 672                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 673                 return rc;
 674         }
 675
 676         /*
 677          * On BCM957508-N2100 adapters, FW will not allow any user other
 678          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 679          * always returns link up. Force phy update always in that case.
 680          */
 681         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 682                 rc = bnxt_set_hwrm_link_config(bp, true);
 683                 if (rc) {
 684                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 685                         return rc;
 686                 }
 687         }
 688
 689         return rc;
 690 }
 691
 692 static int bnxt_init_chip(struct bnxt *bp)
 693 {
 694         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 695         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 696         uint32_t intr_vector = 0;
 697         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 698         uint32_t vec = BNXT_MISC_VEC_ID;
 699         unsigned int i, j;
 700         int rc;
 701
 702         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 703                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 704                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 705                 bp->flags |= BNXT_FLAG_JUMBO;
 706         } else {
 707                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 708                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 709                 bp->flags &= ~BNXT_FLAG_JUMBO;
 710         }
 711
 712         /* THOR does not support ring groups.
 713          * But we will use the array to save RSS context IDs.
 714          */
 715         if (BNXT_CHIP_P5(bp))
 716                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 717
 718         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 719         if (rc) {
 720                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 721                 goto err_out;
 722         }
 723
 724         rc = bnxt_alloc_hwrm_rings(bp);
 725         if (rc) {
 726                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 727                 goto err_out;
 728         }
 729
 730         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 731         if (rc) {
 732                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 733                 goto err_out;
 734         }
 735
 736         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 737                 goto skip_cosq_cfg;
 738
 739         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 740                 if (bp->rx_cos_queue[i].id != 0xff) {
 741                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 742
 743                         if (!vnic) {
 744                                 PMD_DRV_LOG(ERR,
 745                                             "Num pools more than FW profile\n");
 746                                 rc = -EINVAL;
 747                                 goto err_out;
 748                         }
 749                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 750                         bp->rx_cosq_cnt++;
 751                 }
 752         }
 753
 754 skip_cosq_cfg:
 755         rc = bnxt_mq_rx_configure(bp);
 756         if (rc) {
 757                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 758                 goto err_out;
 759         }
 760
 761         /* VNIC configuration */
 762         for (i = 0; i < bp->nr_vnics; i++) {
 763                 rc = bnxt_setup_one_vnic(bp, i);
 764                 if (rc)
 765                         goto err_out;
 766         }
 767
 768         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 769         if (rc) {
 770                 PMD_DRV_LOG(ERR,
 771                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 772                 goto err_out;
 773         }
 774
 775         /* check and configure queue intr-vector mapping */
 776         if ((rte_intr_cap_multiple(intr_handle) ||
 777              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 778             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 779                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 780                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 781                 if (intr_vector > bp->rx_cp_nr_rings) {
 782                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 783                                         bp->rx_cp_nr_rings);
 784                         return -ENOTSUP;
 785                 }
 786                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 787                 if (rc)
 788                         return rc;
 789         }
 790
 791         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 792                 intr_handle->intr_vec =
 793                         rte_zmalloc("intr_vec",
 794                                     bp->eth_dev->data->nb_rx_queues *
 795                                     sizeof(int), 0);
 796                 if (intr_handle->intr_vec == NULL) {
 797                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 798                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 799                         rc = -ENOMEM;
 800                         goto err_disable;
 801                 }
 802                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 803                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 804                          intr_handle->intr_vec, intr_handle->nb_efd,
 805                         intr_handle->max_intr);
 806                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 807                      queue_id++) {
 808                         intr_handle->intr_vec[queue_id] =
 809                                                         vec + BNXT_RX_VEC_START;
 810                         if (vec < base + intr_handle->nb_efd - 1)
 811                                 vec++;
 812                 }
 813         }
 814
 815         /* enable uio/vfio intr/eventfd mapping */
 816         rc = rte_intr_enable(intr_handle);
 817 #ifndef RTE_EXEC_ENV_FREEBSD
 818         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 819         if (rc)
 820                 goto err_free;
 821 #endif
 822
 823         rc = bnxt_update_phy_setting(bp);
 824         if (rc)
 825                 goto err_free;
 826
 827         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 828         if (!bp->mark_table)
 829                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 830
 831         return 0;
 832
 833 err_free:
 834         rte_free(intr_handle->intr_vec);
 835 err_disable:
 836         rte_intr_efd_disable(intr_handle);
 837 err_out:
 838         /* Some of the error status returned by FW may not be from errno.h */
 839         if (rc > 0)
 840                 rc = -EIO;
 841
 842         return rc;
 843 }
 844
 845 static int bnxt_shutdown_nic(struct bnxt *bp)
 846 {
 847         bnxt_free_all_hwrm_resources(bp);
 848         bnxt_free_all_filters(bp);
 849         bnxt_free_all_vnics(bp);
 850         return 0;
 851 }
 852
 853 /*
 854  * Device configuration and status function
 855  */
 856
 857 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 858 {
 859         uint32_t link_speed = bp->link_info->support_speeds;
 860         uint32_t speed_capa = 0;
 861
 862         /* If PAM4 is configured, use PAM4 supported speed */
 863         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 864                 link_speed = bp->link_info->support_pam4_speeds;
 865
 866         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 867                 speed_capa |= ETH_LINK_SPEED_100M;
 868         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 869                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 870         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 871                 speed_capa |= ETH_LINK_SPEED_1G;
 872         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 873                 speed_capa |= ETH_LINK_SPEED_2_5G;
 874         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 875                 speed_capa |= ETH_LINK_SPEED_10G;
 876         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 877                 speed_capa |= ETH_LINK_SPEED_20G;
 878         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 879                 speed_capa |= ETH_LINK_SPEED_25G;
 880         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 881                 speed_capa |= ETH_LINK_SPEED_40G;
 882         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 883                 speed_capa |= ETH_LINK_SPEED_50G;
 884         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 885                 speed_capa |= ETH_LINK_SPEED_100G;
 886         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 887                 speed_capa |= ETH_LINK_SPEED_50G;
 888         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 889                 speed_capa |= ETH_LINK_SPEED_100G;
 890         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 891                 speed_capa |= ETH_LINK_SPEED_200G;
 892
 893         if (bp->link_info->auto_mode ==
 894             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 895                 speed_capa |= ETH_LINK_SPEED_FIXED;
 896         else
 897                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 898
 899         return speed_capa;
 900 }
 901
 902 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 903                                 struct rte_eth_dev_info *dev_info)
 904 {
 905         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 906         struct bnxt *bp = eth_dev->data->dev_private;
 907         uint16_t max_vnics, i, j, vpool, vrxq;
 908         unsigned int max_rx_rings;
 909         int rc;
 910
 911         rc = is_bnxt_in_error(bp);
 912         if (rc)
 913                 return rc;
 914
 915         /* MAC Specifics */
 916         dev_info->max_mac_addrs = bp->max_l2_ctx;
 917         dev_info->max_hash_mac_addrs = 0;
 918
 919         /* PF/VF specifics */
 920         if (BNXT_PF(bp))
 921                 dev_info->max_vfs = pdev->max_vfs;
 922
 923         max_rx_rings = bnxt_max_rings(bp);
 924         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 925         dev_info->max_rx_queues = max_rx_rings;
 926         dev_info->max_tx_queues = max_rx_rings;
 927         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 928         dev_info->hash_key_size = 40;
 929         max_vnics = bp->max_vnics;
 930
 931         /* MTU specifics */
 932         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 933         dev_info->max_mtu = BNXT_MAX_MTU;
 934
 935         /* Fast path specifics */
 936         dev_info->min_rx_bufsize = 1;
 937         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 938
 939         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 940         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 941                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 942         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 943         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 944                                     dev_info->tx_queue_offload_capa;
 945         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 946
 947         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 948
 949         /* *INDENT-OFF* */
 950         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 951                 .rx_thresh = {
 952                         .pthresh = 8,
 953                         .hthresh = 8,
 954                         .wthresh = 0,
 955                 },
 956                 .rx_free_thresh = 32,
 957                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 958         };
 959
 960         dev_info->default_txconf = (struct rte_eth_txconf) {
 961                 .tx_thresh = {
 962                         .pthresh = 32,
 963                         .hthresh = 0,
 964                         .wthresh = 0,
 965                 },
 966                 .tx_free_thresh = 32,
 967                 .tx_rs_thresh = 32,
 968         };
 969         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 970
 971         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 972         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 973         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 974         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 975         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 976
 977         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 978                 dev_info->switch_info.name = eth_dev->device->name;
 979                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 980                 dev_info->switch_info.port_id =
 981                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 982                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 983         }
 984
 985         /* *INDENT-ON* */
 986
 987         /*
 988          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 989          *       need further investigation.
 990          */
 991
 992         /* VMDq resources */
 993         vpool = 64; /* ETH_64_POOLS */
 994         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 995         for (i = 0; i < 4; vpool >>= 1, i++) {
 996                 if (max_vnics > vpool) {
 997                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 998                                 if (dev_info->max_rx_queues > vrxq) {
 999                                         if (vpool > vrxq)
1000                                                 vpool = vrxq;
1001                                         goto found;
1002                                 }
1003                         }
1004                         /* Not enough resources to support VMDq */
1005                         break;
1006                 }
1007         }
1008         /* Not enough resources to support VMDq */
1009         vpool = 0;
1010         vrxq = 0;
1011 found:
1012         dev_info->max_vmdq_pools = vpool;
1013         dev_info->vmdq_queue_num = vrxq;
1014
1015         dev_info->vmdq_pool_base = 0;
1016         dev_info->vmdq_queue_base = 0;
1017
1018         return 0;
1019 }
1020
1021 /* Configure the device based on the configuration provided */
1022 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1023 {
1024         struct bnxt *bp = eth_dev->data->dev_private;
1025         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1026         int rc;
1027
1028         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1029         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1030         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1031         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1032
1033         rc = is_bnxt_in_error(bp);
1034         if (rc)
1035                 return rc;
1036
1037         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1038                 rc = bnxt_hwrm_check_vf_rings(bp);
1039                 if (rc) {
1040                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1041                         return -ENOSPC;
1042                 }
1043
1044                 /* If a resource has already been allocated - in this case
1045                  * it is the async completion ring, free it. Reallocate it after
1046                  * resource reservation. This will ensure the resource counts
1047                  * are calculated correctly.
1048                  */
1049
1050                 pthread_mutex_lock(&bp->def_cp_lock);
1051
1052                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1053                         bnxt_disable_int(bp);
1054                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1055                 }
1056
1057                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1058                 if (rc) {
1059                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1060                         pthread_mutex_unlock(&bp->def_cp_lock);
1061                         return -ENOSPC;
1062                 }
1063
1064                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1065                         rc = bnxt_alloc_async_cp_ring(bp);
1066                         if (rc) {
1067                                 pthread_mutex_unlock(&bp->def_cp_lock);
1068                                 return rc;
1069                         }
1070                         bnxt_enable_int(bp);
1071                 }
1072
1073                 pthread_mutex_unlock(&bp->def_cp_lock);
1074         }
1075
1076         /* Inherit new configurations */
1077         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1078             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1079             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1080                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1081             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1082             bp->max_stat_ctx)
1083                 goto resource_error;
1084
1085         if (BNXT_HAS_RING_GRPS(bp) &&
1086             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1087                 goto resource_error;
1088
1089         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1090             bp->max_vnics < eth_dev->data->nb_rx_queues)
1091                 goto resource_error;
1092
1093         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1094         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1095
1096         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1097                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1098         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1099
1100         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1101                 eth_dev->data->mtu =
1102                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1103                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1104                         BNXT_NUM_VLANS;
1105                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1106         }
1107         return 0;
1108
1109 resource_error:
1110         PMD_DRV_LOG(ERR,
1111                     "Insufficient resources to support requested config\n");
1112         PMD_DRV_LOG(ERR,
1113                     "Num Queues Requested: Tx %d, Rx %d\n",
1114                     eth_dev->data->nb_tx_queues,
1115                     eth_dev->data->nb_rx_queues);
1116         PMD_DRV_LOG(ERR,
1117                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1118                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1119                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1120         return -ENOSPC;
1121 }
1122
1123 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1124 {
1125         struct rte_eth_link *link = &eth_dev->data->dev_link;
1126
1127         if (link->link_status)
1128                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1129                         eth_dev->data->port_id,
1130                         (uint32_t)link->link_speed,
1131                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1132                         ("full-duplex") : ("half-duplex\n"));
1133         else
1134                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1135                         eth_dev->data->port_id);
1136 }
1137
1138 /*
1139  * Determine whether the current configuration requires support for scattered
1140  * receive; return 1 if scattered receive is required and 0 if not.
1141  */
1142 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1143 {
1144         uint16_t buf_size;
1145         int i;
1146
1147         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1148                 return 1;
1149
1150         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1151                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1152
1153                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1154                                       RTE_PKTMBUF_HEADROOM);
1155                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1156                         return 1;
1157         }
1158         return 0;
1159 }
1160
1161 static eth_rx_burst_t
1162 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1163 {
1164         struct bnxt *bp = eth_dev->data->dev_private;
1165
1166 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1167 #ifndef RTE_LIBRTE_IEEE1588
1168         /*
1169          * Vector mode receive can be enabled only if scatter rx is not
1170          * in use and rx offloads are limited to VLAN stripping and
1171          * CRC stripping.
1172          */
1173         if (!eth_dev->data->scattered_rx &&
1174             !(eth_dev->data->dev_conf.rxmode.offloads &
1175               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1176                 DEV_RX_OFFLOAD_KEEP_CRC |
1177                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1178                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1179                 DEV_RX_OFFLOAD_UDP_CKSUM |
1180                 DEV_RX_OFFLOAD_TCP_CKSUM |
1181                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1182                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1183                 DEV_RX_OFFLOAD_RSS_HASH |
1184                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1185             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1186             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1187                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1188                             eth_dev->data->port_id);
1189                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1190                 return bnxt_recv_pkts_vec;
1191         }
1192         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1193                     eth_dev->data->port_id);
1194         PMD_DRV_LOG(INFO,
1195                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1196                     eth_dev->data->port_id,
1197                     eth_dev->data->scattered_rx,
1198                     eth_dev->data->dev_conf.rxmode.offloads);
1199 #endif
1200 #endif
1201         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1202         return bnxt_recv_pkts;
1203 }
1204
1205 static eth_tx_burst_t
1206 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1207 {
1208 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1209 #ifndef RTE_LIBRTE_IEEE1588
1210         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1211         struct bnxt *bp = eth_dev->data->dev_private;
1212
1213         /*
1214          * Vector mode transmit can be enabled only if not using scatter rx
1215          * or tx offloads.
1216          */
1217         if (!eth_dev->data->scattered_rx &&
1218             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1219             !BNXT_TRUFLOW_EN(bp) &&
1220             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1221                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1222                             eth_dev->data->port_id);
1223                 return bnxt_xmit_pkts_vec;
1224         }
1225         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1226                     eth_dev->data->port_id);
1227         PMD_DRV_LOG(INFO,
1228                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1229                     eth_dev->data->port_id,
1230                     eth_dev->data->scattered_rx,
1231                     offloads);
1232 #endif
1233 #endif
1234         return bnxt_xmit_pkts;
1235 }
1236
1237 static int bnxt_handle_if_change_status(struct bnxt *bp)
1238 {
1239         int rc;
1240
1241         /* Since fw has undergone a reset and lost all contexts,
1242          * set fatal flag to not issue hwrm during cleanup
1243          */
1244         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1245         bnxt_uninit_resources(bp, true);
1246
1247         /* clear fatal flag so that re-init happens */
1248         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1249         rc = bnxt_init_resources(bp, true);
1250
1251         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1252
1253         return rc;
1254 }
1255
1256 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1257 {
1258         struct bnxt *bp = eth_dev->data->dev_private;
1259         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1260         int vlan_mask = 0;
1261         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1262
1263         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1264                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1265                 return -EINVAL;
1266         }
1267
1268         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1269                 PMD_DRV_LOG(ERR,
1270                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1271                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1272
1273         do {
1274                 rc = bnxt_hwrm_if_change(bp, true);
1275                 if (rc == 0 || rc != -EAGAIN)
1276                         break;
1277
1278                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1279         } while (retry_cnt--);
1280
1281         if (rc)
1282                 return rc;
1283
1284         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1285                 rc = bnxt_handle_if_change_status(bp);
1286                 if (rc)
1287                         return rc;
1288         }
1289
1290         bnxt_enable_int(bp);
1291
1292         rc = bnxt_init_chip(bp);
1293         if (rc)
1294                 goto error;
1295
1296         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1297         eth_dev->data->dev_started = 1;
1298
1299         bnxt_link_update_op(eth_dev, 1);
1300
1301         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1302                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1303         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1304                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1305         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1306         if (rc)
1307                 goto error;
1308
1309         /* Initialize bnxt ULP port details */
1310         rc = bnxt_ulp_port_init(bp);
1311         if (rc)
1312                 goto error;
1313
1314         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1315         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1316
1317         bnxt_schedule_fw_health_check(bp);
1318
1319         return 0;
1320
1321 error:
1322         bnxt_shutdown_nic(bp);
1323         bnxt_free_tx_mbufs(bp);
1324         bnxt_free_rx_mbufs(bp);
1325         bnxt_hwrm_if_change(bp, false);
1326         eth_dev->data->dev_started = 0;
1327         return rc;
1328 }
1329
1330 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1331 {
1332         struct bnxt *bp = eth_dev->data->dev_private;
1333         int rc = 0;
1334
1335         if (!bp->link_info->link_up)
1336                 rc = bnxt_set_hwrm_link_config(bp, true);
1337         if (!rc)
1338                 eth_dev->data->dev_link.link_status = 1;
1339
1340         bnxt_print_link_info(eth_dev);
1341         return rc;
1342 }
1343
1344 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1345 {
1346         struct bnxt *bp = eth_dev->data->dev_private;
1347
1348         eth_dev->data->dev_link.link_status = 0;
1349         bnxt_set_hwrm_link_config(bp, false);
1350         bp->link_info->link_up = 0;
1351
1352         return 0;
1353 }
1354
1355 static void bnxt_free_switch_domain(struct bnxt *bp)
1356 {
1357         int rc = 0;
1358
1359         if (bp->switch_domain_id) {
1360                 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1361                 if (rc)
1362                         PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1363                                     bp->switch_domain_id, rc);
1364         }
1365 }
1366
1367 /* Unload the driver, release resources */
1368 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1369 {
1370         struct bnxt *bp = eth_dev->data->dev_private;
1371         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1372         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1373         struct rte_eth_link link;
1374         int ret;
1375
1376         eth_dev->data->dev_started = 0;
1377         eth_dev->data->scattered_rx = 0;
1378
1379         /* Prevent crashes when queues are still in use */
1380         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1381         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1382
1383         bnxt_disable_int(bp);
1384
1385         /* disable uio/vfio intr/eventfd mapping */
1386         rte_intr_disable(intr_handle);
1387
1388         /* Stop the child representors for this device */
1389         ret = bnxt_rep_stop_all(bp);
1390         if (ret != 0)
1391                 return ret;
1392
1393         /* delete the bnxt ULP port details */
1394         bnxt_ulp_port_deinit(bp);
1395
1396         bnxt_cancel_fw_health_check(bp);
1397
1398         /* Do not bring link down during reset recovery */
1399         if (!is_bnxt_in_error(bp)) {
1400                 bnxt_dev_set_link_down_op(eth_dev);
1401                 /* Wait for link to be reset */
1402                 if (BNXT_SINGLE_PF(bp))
1403                         rte_delay_ms(500);
1404                 /* clear the recorded link status */
1405                 memset(&link, 0, sizeof(link));
1406                 rte_eth_linkstatus_set(eth_dev, &link);
1407         }
1408
1409         /* Clean queue intr-vector mapping */
1410         rte_intr_efd_disable(intr_handle);
1411         if (intr_handle->intr_vec != NULL) {
1412                 rte_free(intr_handle->intr_vec);
1413                 intr_handle->intr_vec = NULL;
1414         }
1415
1416         bnxt_hwrm_port_clr_stats(bp);
1417         bnxt_free_tx_mbufs(bp);
1418         bnxt_free_rx_mbufs(bp);
1419         /* Process any remaining notifications in default completion queue */
1420         bnxt_int_handler(eth_dev);
1421         bnxt_shutdown_nic(bp);
1422         bnxt_hwrm_if_change(bp, false);
1423
1424         rte_free(bp->mark_table);
1425         bp->mark_table = NULL;
1426
1427         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1428         bp->rx_cosq_cnt = 0;
1429         /* All filters are deleted on a port stop. */
1430         if (BNXT_FLOW_XSTATS_EN(bp))
1431                 bp->flow_stat->flow_count = 0;
1432
1433         return 0;
1434 }
1435
1436 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1437 {
1438         struct bnxt *bp = eth_dev->data->dev_private;
1439         int ret = 0;
1440
1441         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1442                 return 0;
1443
1444         /* cancel the recovery handler before remove dev */
1445         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1446         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1447         bnxt_cancel_fc_thread(bp);
1448
1449         if (eth_dev->data->dev_started)
1450                 ret = bnxt_dev_stop_op(eth_dev);
1451
1452         bnxt_free_switch_domain(bp);
1453
1454         bnxt_uninit_resources(bp, false);
1455
1456         bnxt_free_leds_info(bp);
1457         bnxt_free_cos_queues(bp);
1458         bnxt_free_link_info(bp);
1459         bnxt_free_pf_info(bp);
1460         bnxt_free_parent_info(bp);
1461
1462         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1463         bp->tx_mem_zone = NULL;
1464         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1465         bp->rx_mem_zone = NULL;
1466
1467         bnxt_hwrm_free_vf_info(bp);
1468
1469         rte_free(bp->grp_info);
1470         bp->grp_info = NULL;
1471
1472         return ret;
1473 }
1474
1475 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1476                                     uint32_t index)
1477 {
1478         struct bnxt *bp = eth_dev->data->dev_private;
1479         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1480         struct bnxt_vnic_info *vnic;
1481         struct bnxt_filter_info *filter, *temp_filter;
1482         uint32_t i;
1483
1484         if (is_bnxt_in_error(bp))
1485                 return;
1486
1487         /*
1488          * Loop through all VNICs from the specified filter flow pools to
1489          * remove the corresponding MAC addr filter
1490          */
1491         for (i = 0; i < bp->nr_vnics; i++) {
1492                 if (!(pool_mask & (1ULL << i)))
1493                         continue;
1494
1495                 vnic = &bp->vnic_info[i];
1496                 filter = STAILQ_FIRST(&vnic->filter);
1497                 while (filter) {
1498                         temp_filter = STAILQ_NEXT(filter, next);
1499                         if (filter->mac_index == index) {
1500                                 STAILQ_REMOVE(&vnic->filter, filter,
1501                                                 bnxt_filter_info, next);
1502                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1503                                 bnxt_free_filter(bp, filter);
1504                         }
1505                         filter = temp_filter;
1506                 }
1507         }
1508 }
1509
1510 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1511                                struct rte_ether_addr *mac_addr, uint32_t index,
1512                                uint32_t pool)
1513 {
1514         struct bnxt_filter_info *filter;
1515         int rc = 0;
1516
1517         /* Attach requested MAC address to the new l2_filter */
1518         STAILQ_FOREACH(filter, &vnic->filter, next) {
1519                 if (filter->mac_index == index) {
1520                         PMD_DRV_LOG(DEBUG,
1521                                     "MAC addr already existed for pool %d\n",
1522                                     pool);
1523                         return 0;
1524                 }
1525         }
1526
1527         filter = bnxt_alloc_filter(bp);
1528         if (!filter) {
1529                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1530                 return -ENODEV;
1531         }
1532
1533         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1534          * if the MAC that's been programmed now is a different one, then,
1535          * copy that addr to filter->l2_addr
1536          */
1537         if (mac_addr)
1538                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1539         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1540
1541         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1542         if (!rc) {
1543                 filter->mac_index = index;
1544                 if (filter->mac_index == 0)
1545                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1546                 else
1547                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1548         } else {
1549                 bnxt_free_filter(bp, filter);
1550         }
1551
1552         return rc;
1553 }
1554
1555 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1556                                 struct rte_ether_addr *mac_addr,
1557                                 uint32_t index, uint32_t pool)
1558 {
1559         struct bnxt *bp = eth_dev->data->dev_private;
1560         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1561         int rc = 0;
1562
1563         rc = is_bnxt_in_error(bp);
1564         if (rc)
1565                 return rc;
1566
1567         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1568                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1569                 return -ENOTSUP;
1570         }
1571
1572         if (!vnic) {
1573                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1574                 return -EINVAL;
1575         }
1576
1577         /* Filter settings will get applied when port is started */
1578         if (!eth_dev->data->dev_started)
1579                 return 0;
1580
1581         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1582
1583         return rc;
1584 }
1585
1586 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1587 {
1588         int rc = 0;
1589         struct bnxt *bp = eth_dev->data->dev_private;
1590         struct rte_eth_link new;
1591         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1592                         BNXT_MIN_LINK_WAIT_CNT;
1593
1594         rc = is_bnxt_in_error(bp);
1595         if (rc)
1596                 return rc;
1597
1598         memset(&new, 0, sizeof(new));
1599         do {
1600                 /* Retrieve link info from hardware */
1601                 rc = bnxt_get_hwrm_link_config(bp, &new);
1602                 if (rc) {
1603                         new.link_speed = ETH_LINK_SPEED_100M;
1604                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1605                         PMD_DRV_LOG(ERR,
1606                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1607                         goto out;
1608                 }
1609
1610                 if (!wait_to_complete || new.link_status)
1611                         break;
1612
1613                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1614         } while (cnt--);
1615
1616         /* Only single function PF can bring phy down.
1617          * When port is stopped, report link down for VF/MH/NPAR functions.
1618          */
1619         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1620                 memset(&new, 0, sizeof(new));
1621
1622 out:
1623         /* Timed out or success */
1624         if (new.link_status != eth_dev->data->dev_link.link_status ||
1625             new.link_speed != eth_dev->data->dev_link.link_speed) {
1626                 rte_eth_linkstatus_set(eth_dev, &new);
1627
1628                 rte_eth_dev_callback_process(eth_dev,
1629                                              RTE_ETH_EVENT_INTR_LSC,
1630                                              NULL);
1631
1632                 bnxt_print_link_info(eth_dev);
1633         }
1634
1635         return rc;
1636 }
1637
1638 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1639 {
1640         struct bnxt *bp = eth_dev->data->dev_private;
1641         struct bnxt_vnic_info *vnic;
1642         uint32_t old_flags;
1643         int rc;
1644
1645         rc = is_bnxt_in_error(bp);
1646         if (rc)
1647                 return rc;
1648
1649         /* Filter settings will get applied when port is started */
1650         if (!eth_dev->data->dev_started)
1651                 return 0;
1652
1653         if (bp->vnic_info == NULL)
1654                 return 0;
1655
1656         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1657
1658         old_flags = vnic->flags;
1659         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1660         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1661         if (rc != 0)
1662                 vnic->flags = old_flags;
1663
1664         return rc;
1665 }
1666
1667 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1668 {
1669         struct bnxt *bp = eth_dev->data->dev_private;
1670         struct bnxt_vnic_info *vnic;
1671         uint32_t old_flags;
1672         int rc;
1673
1674         rc = is_bnxt_in_error(bp);
1675         if (rc)
1676                 return rc;
1677
1678         /* Filter settings will get applied when port is started */
1679         if (!eth_dev->data->dev_started)
1680                 return 0;
1681
1682         if (bp->vnic_info == NULL)
1683                 return 0;
1684
1685         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1686
1687         old_flags = vnic->flags;
1688         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1689         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1690         if (rc != 0)
1691                 vnic->flags = old_flags;
1692
1693         return rc;
1694 }
1695
1696 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1697 {
1698         struct bnxt *bp = eth_dev->data->dev_private;
1699         struct bnxt_vnic_info *vnic;
1700         uint32_t old_flags;
1701         int rc;
1702
1703         rc = is_bnxt_in_error(bp);
1704         if (rc)
1705                 return rc;
1706
1707         /* Filter settings will get applied when port is started */
1708         if (!eth_dev->data->dev_started)
1709                 return 0;
1710
1711         if (bp->vnic_info == NULL)
1712                 return 0;
1713
1714         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1715
1716         old_flags = vnic->flags;
1717         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1718         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1719         if (rc != 0)
1720                 vnic->flags = old_flags;
1721
1722         return rc;
1723 }
1724
1725 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1726 {
1727         struct bnxt *bp = eth_dev->data->dev_private;
1728         struct bnxt_vnic_info *vnic;
1729         uint32_t old_flags;
1730         int rc;
1731
1732         rc = is_bnxt_in_error(bp);
1733         if (rc)
1734                 return rc;
1735
1736         /* Filter settings will get applied when port is started */
1737         if (!eth_dev->data->dev_started)
1738                 return 0;
1739
1740         if (bp->vnic_info == NULL)
1741                 return 0;
1742
1743         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1744
1745         old_flags = vnic->flags;
1746         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1747         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1748         if (rc != 0)
1749                 vnic->flags = old_flags;
1750
1751         return rc;
1752 }
1753
1754 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1755 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1756 {
1757         if (qid >= bp->rx_nr_rings)
1758                 return NULL;
1759
1760         return bp->eth_dev->data->rx_queues[qid];
1761 }
1762
1763 /* Return rxq corresponding to a given rss table ring/group ID. */
1764 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1765 {
1766         struct bnxt_rx_queue *rxq;
1767         unsigned int i;
1768
1769         if (!BNXT_HAS_RING_GRPS(bp)) {
1770                 for (i = 0; i < bp->rx_nr_rings; i++) {
1771                         rxq = bp->eth_dev->data->rx_queues[i];
1772                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1773                                 return rxq->index;
1774                 }
1775         } else {
1776                 for (i = 0; i < bp->rx_nr_rings; i++) {
1777                         if (bp->grp_info[i].fw_grp_id == fwr)
1778                                 return i;
1779                 }
1780         }
1781
1782         return INVALID_HW_RING_ID;
1783 }
1784
1785 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1786                             struct rte_eth_rss_reta_entry64 *reta_conf,
1787                             uint16_t reta_size)
1788 {
1789         struct bnxt *bp = eth_dev->data->dev_private;
1790         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1791         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1792         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1793         uint16_t idx, sft;
1794         int i, rc;
1795
1796         rc = is_bnxt_in_error(bp);
1797         if (rc)
1798                 return rc;
1799
1800         if (!vnic->rss_table)
1801                 return -EINVAL;
1802
1803         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1804                 return -EINVAL;
1805
1806         if (reta_size != tbl_size) {
1807                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1808                         "(%d) must equal the size supported by the hardware "
1809                         "(%d)\n", reta_size, tbl_size);
1810                 return -EINVAL;
1811         }
1812
1813         for (i = 0; i < reta_size; i++) {
1814                 struct bnxt_rx_queue *rxq;
1815
1816                 idx = i / RTE_RETA_GROUP_SIZE;
1817                 sft = i % RTE_RETA_GROUP_SIZE;
1818
1819                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1820                         continue;
1821
1822                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1823                 if (!rxq) {
1824                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1825                         return -EINVAL;
1826                 }
1827
1828                 if (BNXT_CHIP_P5(bp)) {
1829                         vnic->rss_table[i * 2] =
1830                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1831                         vnic->rss_table[i * 2 + 1] =
1832                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1833                 } else {
1834                         vnic->rss_table[i] =
1835                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1836                 }
1837         }
1838
1839         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1840         return rc;
1841 }
1842
1843 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1844                               struct rte_eth_rss_reta_entry64 *reta_conf,
1845                               uint16_t reta_size)
1846 {
1847         struct bnxt *bp = eth_dev->data->dev_private;
1848         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1849         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1850         uint16_t idx, sft, i;
1851         int rc;
1852
1853         rc = is_bnxt_in_error(bp);
1854         if (rc)
1855                 return rc;
1856
1857         /* Retrieve from the default VNIC */
1858         if (!vnic)
1859                 return -EINVAL;
1860         if (!vnic->rss_table)
1861                 return -EINVAL;
1862
1863         if (reta_size != tbl_size) {
1864                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1865                         "(%d) must equal the size supported by the hardware "
1866                         "(%d)\n", reta_size, tbl_size);
1867                 return -EINVAL;
1868         }
1869
1870         for (idx = 0, i = 0; i < reta_size; i++) {
1871                 idx = i / RTE_RETA_GROUP_SIZE;
1872                 sft = i % RTE_RETA_GROUP_SIZE;
1873
1874                 if (reta_conf[idx].mask & (1ULL << sft)) {
1875                         uint16_t qid;
1876
1877                         if (BNXT_CHIP_P5(bp))
1878                                 qid = bnxt_rss_to_qid(bp,
1879                                                       vnic->rss_table[i * 2]);
1880                         else
1881                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1882
1883                         if (qid == INVALID_HW_RING_ID) {
1884                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1885                                 return -EINVAL;
1886                         }
1887                         reta_conf[idx].reta[sft] = qid;
1888                 }
1889         }
1890
1891         return 0;
1892 }
1893
1894 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1895                                    struct rte_eth_rss_conf *rss_conf)
1896 {
1897         struct bnxt *bp = eth_dev->data->dev_private;
1898         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1899         struct bnxt_vnic_info *vnic;
1900         int rc;
1901
1902         rc = is_bnxt_in_error(bp);
1903         if (rc)
1904                 return rc;
1905
1906         /*
1907          * If RSS enablement were different than dev_configure,
1908          * then return -EINVAL
1909          */
1910         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1911                 if (!rss_conf->rss_hf)
1912                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1913         } else {
1914                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1915                         return -EINVAL;
1916         }
1917
1918         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1919         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1920                rss_conf,
1921                sizeof(*rss_conf));
1922
1923         /* Update the default RSS VNIC(s) */
1924         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1925         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1926         vnic->hash_mode =
1927                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1928                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1929
1930         /*
1931          * If hashkey is not specified, use the previously configured
1932          * hashkey
1933          */
1934         if (!rss_conf->rss_key)
1935                 goto rss_config;
1936
1937         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1938                 PMD_DRV_LOG(ERR,
1939                             "Invalid hashkey length, should be 16 bytes\n");
1940                 return -EINVAL;
1941         }
1942         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1943
1944 rss_config:
1945         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1946         return rc;
1947 }
1948
1949 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1950                                      struct rte_eth_rss_conf *rss_conf)
1951 {
1952         struct bnxt *bp = eth_dev->data->dev_private;
1953         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1954         int len, rc;
1955         uint32_t hash_types;
1956
1957         rc = is_bnxt_in_error(bp);
1958         if (rc)
1959                 return rc;
1960
1961         /* RSS configuration is the same for all VNICs */
1962         if (vnic && vnic->rss_hash_key) {
1963                 if (rss_conf->rss_key) {
1964                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1965                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1966                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1967                 }
1968
1969                 hash_types = vnic->hash_type;
1970                 rss_conf->rss_hf = 0;
1971                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1972                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1973                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1974                 }
1975                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1976                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1977                         hash_types &=
1978                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1979                 }
1980                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1981                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1982                         hash_types &=
1983                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1984                 }
1985                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1986                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1987                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1988                 }
1989                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1990                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1991                         hash_types &=
1992                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1993                 }
1994                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1995                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1996                         hash_types &=
1997                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1998                 }
1999
2000                 rss_conf->rss_hf |=
2001                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2002
2003                 if (hash_types) {
2004                         PMD_DRV_LOG(ERR,
2005                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2006                                 vnic->hash_type);
2007                         return -ENOTSUP;
2008                 }
2009         } else {
2010                 rss_conf->rss_hf = 0;
2011         }
2012         return 0;
2013 }
2014
2015 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2016                                struct rte_eth_fc_conf *fc_conf)
2017 {
2018         struct bnxt *bp = dev->data->dev_private;
2019         struct rte_eth_link link_info;
2020         int rc;
2021
2022         rc = is_bnxt_in_error(bp);
2023         if (rc)
2024                 return rc;
2025
2026         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2027         if (rc)
2028                 return rc;
2029
2030         memset(fc_conf, 0, sizeof(*fc_conf));
2031         if (bp->link_info->auto_pause)
2032                 fc_conf->autoneg = 1;
2033         switch (bp->link_info->pause) {
2034         case 0:
2035                 fc_conf->mode = RTE_FC_NONE;
2036                 break;
2037         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2038                 fc_conf->mode = RTE_FC_TX_PAUSE;
2039                 break;
2040         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2041                 fc_conf->mode = RTE_FC_RX_PAUSE;
2042                 break;
2043         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2044                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2045                 fc_conf->mode = RTE_FC_FULL;
2046                 break;
2047         }
2048         return 0;
2049 }
2050
2051 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2052                                struct rte_eth_fc_conf *fc_conf)
2053 {
2054         struct bnxt *bp = dev->data->dev_private;
2055         int rc;
2056
2057         rc = is_bnxt_in_error(bp);
2058         if (rc)
2059                 return rc;
2060
2061         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2062                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2063                 return -ENOTSUP;
2064         }
2065
2066         switch (fc_conf->mode) {
2067         case RTE_FC_NONE:
2068                 bp->link_info->auto_pause = 0;
2069                 bp->link_info->force_pause = 0;
2070                 break;
2071         case RTE_FC_RX_PAUSE:
2072                 if (fc_conf->autoneg) {
2073                         bp->link_info->auto_pause =
2074                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2075                         bp->link_info->force_pause = 0;
2076                 } else {
2077                         bp->link_info->auto_pause = 0;
2078                         bp->link_info->force_pause =
2079                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2080                 }
2081                 break;
2082         case RTE_FC_TX_PAUSE:
2083                 if (fc_conf->autoneg) {
2084                         bp->link_info->auto_pause =
2085                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2086                         bp->link_info->force_pause = 0;
2087                 } else {
2088                         bp->link_info->auto_pause = 0;
2089                         bp->link_info->force_pause =
2090                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2091                 }
2092                 break;
2093         case RTE_FC_FULL:
2094                 if (fc_conf->autoneg) {
2095                         bp->link_info->auto_pause =
2096                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2097                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2098                         bp->link_info->force_pause = 0;
2099                 } else {
2100                         bp->link_info->auto_pause = 0;
2101                         bp->link_info->force_pause =
2102                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2103                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2104                 }
2105                 break;
2106         }
2107         return bnxt_set_hwrm_link_config(bp, true);
2108 }
2109
2110 /* Add UDP tunneling port */
2111 static int
2112 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2113                          struct rte_eth_udp_tunnel *udp_tunnel)
2114 {
2115         struct bnxt *bp = eth_dev->data->dev_private;
2116         uint16_t tunnel_type = 0;
2117         int rc = 0;
2118
2119         rc = is_bnxt_in_error(bp);
2120         if (rc)
2121                 return rc;
2122
2123         switch (udp_tunnel->prot_type) {
2124         case RTE_TUNNEL_TYPE_VXLAN:
2125                 if (bp->vxlan_port_cnt) {
2126                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2127                                 udp_tunnel->udp_port);
2128                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2129                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2130                                 return -ENOSPC;
2131                         }
2132                         bp->vxlan_port_cnt++;
2133                         return 0;
2134                 }
2135                 tunnel_type =
2136                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2137                 bp->vxlan_port_cnt++;
2138                 break;
2139         case RTE_TUNNEL_TYPE_GENEVE:
2140                 if (bp->geneve_port_cnt) {
2141                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2142                                 udp_tunnel->udp_port);
2143                         if (bp->geneve_port != udp_tunnel->udp_port) {
2144                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2145                                 return -ENOSPC;
2146                         }
2147                         bp->geneve_port_cnt++;
2148                         return 0;
2149                 }
2150                 tunnel_type =
2151                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2152                 bp->geneve_port_cnt++;
2153                 break;
2154         default:
2155                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2156                 return -ENOTSUP;
2157         }
2158         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2159                                              tunnel_type);
2160         return rc;
2161 }
2162
2163 static int
2164 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2165                          struct rte_eth_udp_tunnel *udp_tunnel)
2166 {
2167         struct bnxt *bp = eth_dev->data->dev_private;
2168         uint16_t tunnel_type = 0;
2169         uint16_t port = 0;
2170         int rc = 0;
2171
2172         rc = is_bnxt_in_error(bp);
2173         if (rc)
2174                 return rc;
2175
2176         switch (udp_tunnel->prot_type) {
2177         case RTE_TUNNEL_TYPE_VXLAN:
2178                 if (!bp->vxlan_port_cnt) {
2179                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2180                         return -EINVAL;
2181                 }
2182                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2183                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2184                                 udp_tunnel->udp_port, bp->vxlan_port);
2185                         return -EINVAL;
2186                 }
2187                 if (--bp->vxlan_port_cnt)
2188                         return 0;
2189
2190                 tunnel_type =
2191                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2192                 port = bp->vxlan_fw_dst_port_id;
2193                 break;
2194         case RTE_TUNNEL_TYPE_GENEVE:
2195                 if (!bp->geneve_port_cnt) {
2196                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2197                         return -EINVAL;
2198                 }
2199                 if (bp->geneve_port != udp_tunnel->udp_port) {
2200                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2201                                 udp_tunnel->udp_port, bp->geneve_port);
2202                         return -EINVAL;
2203                 }
2204                 if (--bp->geneve_port_cnt)
2205                         return 0;
2206
2207                 tunnel_type =
2208                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2209                 port = bp->geneve_fw_dst_port_id;
2210                 break;
2211         default:
2212                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2213                 return -ENOTSUP;
2214         }
2215
2216         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2217         return rc;
2218 }
2219
2220 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2221 {
2222         struct bnxt_filter_info *filter;
2223         struct bnxt_vnic_info *vnic;
2224         int rc = 0;
2225         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2226
2227         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2228         filter = STAILQ_FIRST(&vnic->filter);
2229         while (filter) {
2230                 /* Search for this matching MAC+VLAN filter */
2231                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2232                         /* Delete the filter */
2233                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2234                         if (rc)
2235                                 return rc;
2236                         STAILQ_REMOVE(&vnic->filter, filter,
2237                                       bnxt_filter_info, next);
2238                         bnxt_free_filter(bp, filter);
2239                         PMD_DRV_LOG(INFO,
2240                                     "Deleted vlan filter for %d\n",
2241                                     vlan_id);
2242                         return 0;
2243                 }
2244                 filter = STAILQ_NEXT(filter, next);
2245         }
2246         return -ENOENT;
2247 }
2248
2249 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2250 {
2251         struct bnxt_filter_info *filter;
2252         struct bnxt_vnic_info *vnic;
2253         int rc = 0;
2254         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2255                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2256         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2257
2258         /* Implementation notes on the use of VNIC in this command:
2259          *
2260          * By default, these filters belong to default vnic for the function.
2261          * Once these filters are set up, only destination VNIC can be modified.
2262          * If the destination VNIC is not specified in this command,
2263          * then the HWRM shall only create an l2 context id.
2264          */
2265
2266         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2267         filter = STAILQ_FIRST(&vnic->filter);
2268         /* Check if the VLAN has already been added */
2269         while (filter) {
2270                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2271                         return -EEXIST;
2272
2273                 filter = STAILQ_NEXT(filter, next);
2274         }
2275
2276         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2277          * command to create MAC+VLAN filter with the right flags, enables set.
2278          */
2279         filter = bnxt_alloc_filter(bp);
2280         if (!filter) {
2281                 PMD_DRV_LOG(ERR,
2282                             "MAC/VLAN filter alloc failed\n");
2283                 return -ENOMEM;
2284         }
2285         /* MAC + VLAN ID filter */
2286         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2287          * untagged packets are received
2288          *
2289          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2290          * packets and only the programmed vlan's packets are received
2291          */
2292         filter->l2_ivlan = vlan_id;
2293         filter->l2_ivlan_mask = 0x0FFF;
2294         filter->enables |= en;
2295         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2296
2297         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2298         if (rc) {
2299                 /* Free the newly allocated filter as we were
2300                  * not able to create the filter in hardware.
2301                  */
2302                 bnxt_free_filter(bp, filter);
2303                 return rc;
2304         }
2305
2306         filter->mac_index = 0;
2307         /* Add this new filter to the list */
2308         if (vlan_id == 0)
2309                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2310         else
2311                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2312
2313         PMD_DRV_LOG(INFO,
2314                     "Added Vlan filter for %d\n", vlan_id);
2315         return rc;
2316 }
2317
2318 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2319                 uint16_t vlan_id, int on)
2320 {
2321         struct bnxt *bp = eth_dev->data->dev_private;
2322         int rc;
2323
2324         rc = is_bnxt_in_error(bp);
2325         if (rc)
2326                 return rc;
2327
2328         if (!eth_dev->data->dev_started) {
2329                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2330                 return -EINVAL;
2331         }
2332
2333         /* These operations apply to ALL existing MAC/VLAN filters */
2334         if (on)
2335                 return bnxt_add_vlan_filter(bp, vlan_id);
2336         else
2337                 return bnxt_del_vlan_filter(bp, vlan_id);
2338 }
2339
2340 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2341                                     struct bnxt_vnic_info *vnic)
2342 {
2343         struct bnxt_filter_info *filter;
2344         int rc;
2345
2346         filter = STAILQ_FIRST(&vnic->filter);
2347         while (filter) {
2348                 if (filter->mac_index == 0 &&
2349                     !memcmp(filter->l2_addr, bp->mac_addr,
2350                             RTE_ETHER_ADDR_LEN)) {
2351                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2352                         if (!rc) {
2353                                 STAILQ_REMOVE(&vnic->filter, filter,
2354                                               bnxt_filter_info, next);
2355                                 bnxt_free_filter(bp, filter);
2356                         }
2357                         return rc;
2358                 }
2359                 filter = STAILQ_NEXT(filter, next);
2360         }
2361         return 0;
2362 }
2363
2364 static int
2365 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2366 {
2367         struct bnxt_vnic_info *vnic;
2368         unsigned int i;
2369         int rc;
2370
2371         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2372         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2373                 /* Remove any VLAN filters programmed */
2374                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2375                         bnxt_del_vlan_filter(bp, i);
2376
2377                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2378                 if (rc)
2379                         return rc;
2380         } else {
2381                 /* Default filter will allow packets that match the
2382                  * dest mac. So, it has to be deleted, otherwise, we
2383                  * will endup receiving vlan packets for which the
2384                  * filter is not programmed, when hw-vlan-filter
2385                  * configuration is ON
2386                  */
2387                 bnxt_del_dflt_mac_filter(bp, vnic);
2388                 /* This filter will allow only untagged packets */
2389                 bnxt_add_vlan_filter(bp, 0);
2390         }
2391         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2392                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2393
2394         return 0;
2395 }
2396
2397 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2398 {
2399         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2400         unsigned int i;
2401         int rc;
2402
2403         /* Destroy vnic filters and vnic */
2404         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2405             DEV_RX_OFFLOAD_VLAN_FILTER) {
2406                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2407                         bnxt_del_vlan_filter(bp, i);
2408         }
2409         bnxt_del_dflt_mac_filter(bp, vnic);
2410
2411         rc = bnxt_hwrm_vnic_free(bp, vnic);
2412         if (rc)
2413                 return rc;
2414
2415         rte_free(vnic->fw_grp_ids);
2416         vnic->fw_grp_ids = NULL;
2417
2418         vnic->rx_queue_cnt = 0;
2419
2420         return 0;
2421 }
2422
2423 static int
2424 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2425 {
2426         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2427         int rc;
2428
2429         /* Destroy, recreate and reconfigure the default vnic */
2430         rc = bnxt_free_one_vnic(bp, 0);
2431         if (rc)
2432                 return rc;
2433
2434         /* default vnic 0 */
2435         rc = bnxt_setup_one_vnic(bp, 0);
2436         if (rc)
2437                 return rc;
2438
2439         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2440             DEV_RX_OFFLOAD_VLAN_FILTER) {
2441                 rc = bnxt_add_vlan_filter(bp, 0);
2442                 if (rc)
2443                         return rc;
2444                 rc = bnxt_restore_vlan_filters(bp);
2445                 if (rc)
2446                         return rc;
2447         } else {
2448                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2449                 if (rc)
2450                         return rc;
2451         }
2452
2453         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2454         if (rc)
2455                 return rc;
2456
2457         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2458                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2459
2460         return rc;
2461 }
2462
2463 static int
2464 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2465 {
2466         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2467         struct bnxt *bp = dev->data->dev_private;
2468         int rc;
2469
2470         rc = is_bnxt_in_error(bp);
2471         if (rc)
2472                 return rc;
2473
2474         /* Filter settings will get applied when port is started */
2475         if (!dev->data->dev_started)
2476                 return 0;
2477
2478         if (mask & ETH_VLAN_FILTER_MASK) {
2479                 /* Enable or disable VLAN filtering */
2480                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2481                 if (rc)
2482                         return rc;
2483         }
2484
2485         if (mask & ETH_VLAN_STRIP_MASK) {
2486                 /* Enable or disable VLAN stripping */
2487                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2488                 if (rc)
2489                         return rc;
2490         }
2491
2492         if (mask & ETH_VLAN_EXTEND_MASK) {
2493                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2494                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2495                 else
2496                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2497         }
2498
2499         return 0;
2500 }
2501
2502 static int
2503 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2504                       uint16_t tpid)
2505 {
2506         struct bnxt *bp = dev->data->dev_private;
2507         int qinq = dev->data->dev_conf.rxmode.offloads &
2508                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2509
2510         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2511             vlan_type != ETH_VLAN_TYPE_OUTER) {
2512                 PMD_DRV_LOG(ERR,
2513                             "Unsupported vlan type.");
2514                 return -EINVAL;
2515         }
2516         if (!qinq) {
2517                 PMD_DRV_LOG(ERR,
2518                             "QinQ not enabled. Needs to be ON as we can "
2519                             "accelerate only outer vlan\n");
2520                 return -EINVAL;
2521         }
2522
2523         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2524                 switch (tpid) {
2525                 case RTE_ETHER_TYPE_QINQ:
2526                         bp->outer_tpid_bd =
2527                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2528                                 break;
2529                 case RTE_ETHER_TYPE_VLAN:
2530                         bp->outer_tpid_bd =
2531                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2532                                 break;
2533                 case RTE_ETHER_TYPE_QINQ1:
2534                         bp->outer_tpid_bd =
2535                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2536                                 break;
2537                 case RTE_ETHER_TYPE_QINQ2:
2538                         bp->outer_tpid_bd =
2539                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2540                                 break;
2541                 case RTE_ETHER_TYPE_QINQ3:
2542                         bp->outer_tpid_bd =
2543                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2544                                 break;
2545                 default:
2546                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2547                         return -EINVAL;
2548                 }
2549                 bp->outer_tpid_bd |= tpid;
2550                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2551         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2552                 PMD_DRV_LOG(ERR,
2553                             "Can accelerate only outer vlan in QinQ\n");
2554                 return -EINVAL;
2555         }
2556
2557         return 0;
2558 }
2559
2560 static int
2561 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2562                              struct rte_ether_addr *addr)
2563 {
2564         struct bnxt *bp = dev->data->dev_private;
2565         /* Default Filter is tied to VNIC 0 */
2566         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2567         int rc;
2568
2569         rc = is_bnxt_in_error(bp);
2570         if (rc)
2571                 return rc;
2572
2573         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2574                 return -EPERM;
2575
2576         if (rte_is_zero_ether_addr(addr))
2577                 return -EINVAL;
2578
2579         /* Filter settings will get applied when port is started */
2580         if (!dev->data->dev_started)
2581                 return 0;
2582
2583         /* Check if the requested MAC is already added */
2584         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2585                 return 0;
2586
2587         /* Destroy filter and re-create it */
2588         bnxt_del_dflt_mac_filter(bp, vnic);
2589
2590         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2591         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2592                 /* This filter will allow only untagged packets */
2593                 rc = bnxt_add_vlan_filter(bp, 0);
2594         } else {
2595                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2596         }
2597
2598         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2599         return rc;
2600 }
2601
2602 static int
2603 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2604                           struct rte_ether_addr *mc_addr_set,
2605                           uint32_t nb_mc_addr)
2606 {
2607         struct bnxt *bp = eth_dev->data->dev_private;
2608         char *mc_addr_list = (char *)mc_addr_set;
2609         struct bnxt_vnic_info *vnic;
2610         uint32_t off = 0, i = 0;
2611         int rc;
2612
2613         rc = is_bnxt_in_error(bp);
2614         if (rc)
2615                 return rc;
2616
2617         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2618
2619         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2620                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2621                 goto allmulti;
2622         }
2623
2624         /* TODO Check for Duplicate mcast addresses */
2625         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2626         for (i = 0; i < nb_mc_addr; i++) {
2627                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2628                         RTE_ETHER_ADDR_LEN);
2629                 off += RTE_ETHER_ADDR_LEN;
2630         }
2631
2632         vnic->mc_addr_cnt = i;
2633         if (vnic->mc_addr_cnt)
2634                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2635         else
2636                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2637
2638 allmulti:
2639         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2640 }
2641
2642 static int
2643 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2644 {
2645         struct bnxt *bp = dev->data->dev_private;
2646         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2647         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2648         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2649         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2650         int ret;
2651
2652         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2653                         fw_major, fw_minor, fw_updt, fw_rsvd);
2654
2655         ret += 1; /* add the size of '\0' */
2656         if (fw_size < (uint32_t)ret)
2657                 return ret;
2658         else
2659                 return 0;
2660 }
2661
2662 static void
2663 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2664         struct rte_eth_rxq_info *qinfo)
2665 {
2666         struct bnxt *bp = dev->data->dev_private;
2667         struct bnxt_rx_queue *rxq;
2668
2669         if (is_bnxt_in_error(bp))
2670                 return;
2671
2672         rxq = dev->data->rx_queues[queue_id];
2673
2674         qinfo->mp = rxq->mb_pool;
2675         qinfo->scattered_rx = dev->data->scattered_rx;
2676         qinfo->nb_desc = rxq->nb_rx_desc;
2677
2678         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2679         qinfo->conf.rx_drop_en = rxq->drop_en;
2680         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2681         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2682 }
2683
2684 static void
2685 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2686         struct rte_eth_txq_info *qinfo)
2687 {
2688         struct bnxt *bp = dev->data->dev_private;
2689         struct bnxt_tx_queue *txq;
2690
2691         if (is_bnxt_in_error(bp))
2692                 return;
2693
2694         txq = dev->data->tx_queues[queue_id];
2695
2696         qinfo->nb_desc = txq->nb_tx_desc;
2697
2698         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2699         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2700         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2701
2702         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2703         qinfo->conf.tx_rs_thresh = 0;
2704         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2705         qinfo->conf.offloads = txq->offloads;
2706 }
2707
2708 static const struct {
2709         eth_rx_burst_t pkt_burst;
2710         const char *info;
2711 } bnxt_rx_burst_info[] = {
2712         {bnxt_recv_pkts,        "Scalar"},
2713 #if defined(RTE_ARCH_X86)
2714         {bnxt_recv_pkts_vec,    "Vector SSE"},
2715 #elif defined(RTE_ARCH_ARM64)
2716         {bnxt_recv_pkts_vec,    "Vector Neon"},
2717 #endif
2718 };
2719
2720 static int
2721 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2722                        struct rte_eth_burst_mode *mode)
2723 {
2724         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2725         size_t i;
2726
2727         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2728                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2729                         snprintf(mode->info, sizeof(mode->info), "%s",
2730                                  bnxt_rx_burst_info[i].info);
2731                         return 0;
2732                 }
2733         }
2734
2735         return -EINVAL;
2736 }
2737
2738 static const struct {
2739         eth_tx_burst_t pkt_burst;
2740         const char *info;
2741 } bnxt_tx_burst_info[] = {
2742         {bnxt_xmit_pkts,        "Scalar"},
2743 #if defined(RTE_ARCH_X86)
2744         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2745 #elif defined(RTE_ARCH_ARM64)
2746         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2747 #endif
2748 };
2749
2750 static int
2751 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2752                        struct rte_eth_burst_mode *mode)
2753 {
2754         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2755         size_t i;
2756
2757         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2758                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2759                         snprintf(mode->info, sizeof(mode->info), "%s",
2760                                  bnxt_tx_burst_info[i].info);
2761                         return 0;
2762                 }
2763         }
2764
2765         return -EINVAL;
2766 }
2767
2768 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2769 {
2770         struct bnxt *bp = eth_dev->data->dev_private;
2771         uint32_t new_pkt_size;
2772         uint32_t rc = 0;
2773         uint32_t i;
2774
2775         rc = is_bnxt_in_error(bp);
2776         if (rc)
2777                 return rc;
2778
2779         /* Exit if receive queues are not configured yet */
2780         if (!eth_dev->data->nb_rx_queues)
2781                 return rc;
2782
2783         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2784                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2785
2786         /*
2787          * Disallow any MTU change that would require scattered receive support
2788          * if it is not already enabled.
2789          */
2790         if (eth_dev->data->dev_started &&
2791             !eth_dev->data->scattered_rx &&
2792             (new_pkt_size >
2793              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2794                 PMD_DRV_LOG(ERR,
2795                             "MTU change would require scattered rx support. ");
2796                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2797                 return -EINVAL;
2798         }
2799
2800         if (new_mtu > RTE_ETHER_MTU) {
2801                 bp->flags |= BNXT_FLAG_JUMBO;
2802                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2803                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2804         } else {
2805                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2806                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2807                 bp->flags &= ~BNXT_FLAG_JUMBO;
2808         }
2809
2810         /* Is there a change in mtu setting? */
2811         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2812                 return rc;
2813
2814         for (i = 0; i < bp->nr_vnics; i++) {
2815                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2816                 uint16_t size = 0;
2817
2818                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2819                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2820                 if (rc)
2821                         break;
2822
2823                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2824                 size -= RTE_PKTMBUF_HEADROOM;
2825
2826                 if (size < new_mtu) {
2827                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2828                         if (rc)
2829                                 return rc;
2830                 }
2831         }
2832
2833         if (!rc)
2834                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2835
2836         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2837
2838         return rc;
2839 }
2840
2841 static int
2842 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2843 {
2844         struct bnxt *bp = dev->data->dev_private;
2845         uint16_t vlan = bp->vlan;
2846         int rc;
2847
2848         rc = is_bnxt_in_error(bp);
2849         if (rc)
2850                 return rc;
2851
2852         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2853                 PMD_DRV_LOG(ERR,
2854                         "PVID cannot be modified for this function\n");
2855                 return -ENOTSUP;
2856         }
2857         bp->vlan = on ? pvid : 0;
2858
2859         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2860         if (rc)
2861                 bp->vlan = vlan;
2862         return rc;
2863 }
2864
2865 static int
2866 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2867 {
2868         struct bnxt *bp = dev->data->dev_private;
2869         int rc;
2870
2871         rc = is_bnxt_in_error(bp);
2872         if (rc)
2873                 return rc;
2874
2875         return bnxt_hwrm_port_led_cfg(bp, true);
2876 }
2877
2878 static int
2879 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2880 {
2881         struct bnxt *bp = dev->data->dev_private;
2882         int rc;
2883
2884         rc = is_bnxt_in_error(bp);
2885         if (rc)
2886                 return rc;
2887
2888         return bnxt_hwrm_port_led_cfg(bp, false);
2889 }
2890
2891 static uint32_t
2892 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2893 {
2894         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2895         uint32_t desc = 0, raw_cons = 0, cons;
2896         struct bnxt_cp_ring_info *cpr;
2897         struct bnxt_rx_queue *rxq;
2898         struct rx_pkt_cmpl *rxcmp;
2899         int rc;
2900
2901         rc = is_bnxt_in_error(bp);
2902         if (rc)
2903                 return rc;
2904
2905         rxq = dev->data->rx_queues[rx_queue_id];
2906         cpr = rxq->cp_ring;
2907         raw_cons = cpr->cp_raw_cons;
2908
2909         while (1) {
2910                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2911                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2912                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2913
2914                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2915                         break;
2916                 } else {
2917                         raw_cons++;
2918                         desc++;
2919                 }
2920         }
2921
2922         return desc;
2923 }
2924
2925 static int
2926 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2927 {
2928         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2929         struct bnxt_rx_ring_info *rxr;
2930         struct bnxt_cp_ring_info *cpr;
2931         struct rte_mbuf *rx_buf;
2932         struct rx_pkt_cmpl *rxcmp;
2933         uint32_t cons, cp_cons;
2934         int rc;
2935
2936         if (!rxq)
2937                 return -EINVAL;
2938
2939         rc = is_bnxt_in_error(rxq->bp);
2940         if (rc)
2941                 return rc;
2942
2943         cpr = rxq->cp_ring;
2944         rxr = rxq->rx_ring;
2945
2946         if (offset >= rxq->nb_rx_desc)
2947                 return -EINVAL;
2948
2949         cons = RING_CMP(cpr->cp_ring_struct, offset);
2950         cp_cons = cpr->cp_raw_cons;
2951         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2952
2953         if (cons > cp_cons) {
2954                 if (CMPL_VALID(rxcmp, cpr->valid))
2955                         return RTE_ETH_RX_DESC_DONE;
2956         } else {
2957                 if (CMPL_VALID(rxcmp, !cpr->valid))
2958                         return RTE_ETH_RX_DESC_DONE;
2959         }
2960         rx_buf = rxr->rx_buf_ring[cons];
2961         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2962                 return RTE_ETH_RX_DESC_UNAVAIL;
2963
2964
2965         return RTE_ETH_RX_DESC_AVAIL;
2966 }
2967
2968 static int
2969 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2970 {
2971         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2972         struct bnxt_tx_ring_info *txr;
2973         struct bnxt_cp_ring_info *cpr;
2974         struct bnxt_sw_tx_bd *tx_buf;
2975         struct tx_pkt_cmpl *txcmp;
2976         uint32_t cons, cp_cons;
2977         int rc;
2978
2979         if (!txq)
2980                 return -EINVAL;
2981
2982         rc = is_bnxt_in_error(txq->bp);
2983         if (rc)
2984                 return rc;
2985
2986         cpr = txq->cp_ring;
2987         txr = txq->tx_ring;
2988
2989         if (offset >= txq->nb_tx_desc)
2990                 return -EINVAL;
2991
2992         cons = RING_CMP(cpr->cp_ring_struct, offset);
2993         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2994         cp_cons = cpr->cp_raw_cons;
2995
2996         if (cons > cp_cons) {
2997                 if (CMPL_VALID(txcmp, cpr->valid))
2998                         return RTE_ETH_TX_DESC_UNAVAIL;
2999         } else {
3000                 if (CMPL_VALID(txcmp, !cpr->valid))
3001                         return RTE_ETH_TX_DESC_UNAVAIL;
3002         }
3003         tx_buf = &txr->tx_buf_ring[cons];
3004         if (tx_buf->mbuf == NULL)
3005                 return RTE_ETH_TX_DESC_DONE;
3006
3007         return RTE_ETH_TX_DESC_FULL;
3008 }
3009
3010 int
3011 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3012                     enum rte_filter_type filter_type,
3013                     enum rte_filter_op filter_op, void *arg)
3014 {
3015         struct bnxt *bp = dev->data->dev_private;
3016         int ret = 0;
3017
3018         if (!bp)
3019                 return -EIO;
3020
3021         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3022                 struct bnxt_representor *vfr = dev->data->dev_private;
3023                 bp = vfr->parent_dev->data->dev_private;
3024                 /* parent is deleted while children are still valid */
3025                 if (!bp) {
3026                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3027                                     dev->data->port_id,
3028                                     filter_type,
3029                                     filter_op);
3030                         return -EIO;
3031                 }
3032         }
3033
3034         ret = is_bnxt_in_error(bp);
3035         if (ret)
3036                 return ret;
3037
3038         switch (filter_type) {
3039         case RTE_ETH_FILTER_GENERIC:
3040                 if (filter_op != RTE_ETH_FILTER_GET)
3041                         return -EINVAL;
3042
3043                 /* PMD supports thread-safe flow operations.  rte_flow API
3044                  * functions can avoid mutex for multi-thread safety.
3045                  */
3046                 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3047
3048                 if (BNXT_TRUFLOW_EN(bp))
3049                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3050                 else
3051                         *(const void **)arg = &bnxt_flow_ops;
3052                 break;
3053         default:
3054                 PMD_DRV_LOG(ERR,
3055                         "Filter type (%d) not supported", filter_type);
3056                 ret = -EINVAL;
3057                 break;
3058         }
3059         return ret;
3060 }
3061
3062 static const uint32_t *
3063 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3064 {
3065         static const uint32_t ptypes[] = {
3066                 RTE_PTYPE_L2_ETHER_VLAN,
3067                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3068                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3069                 RTE_PTYPE_L4_ICMP,
3070                 RTE_PTYPE_L4_TCP,
3071                 RTE_PTYPE_L4_UDP,
3072                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3073                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3074                 RTE_PTYPE_INNER_L4_ICMP,
3075                 RTE_PTYPE_INNER_L4_TCP,
3076                 RTE_PTYPE_INNER_L4_UDP,
3077                 RTE_PTYPE_UNKNOWN
3078         };
3079
3080         if (!dev->rx_pkt_burst)
3081                 return NULL;
3082
3083         return ptypes;
3084 }
3085
3086 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3087                          int reg_win)
3088 {
3089         uint32_t reg_base = *reg_arr & 0xfffff000;
3090         uint32_t win_off;
3091         int i;
3092
3093         for (i = 0; i < count; i++) {
3094                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3095                         return -ERANGE;
3096         }
3097         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3098         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3099         return 0;
3100 }
3101
3102 static int bnxt_map_ptp_regs(struct bnxt *bp)
3103 {
3104         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3105         uint32_t *reg_arr;
3106         int rc, i;
3107
3108         reg_arr = ptp->rx_regs;
3109         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3110         if (rc)
3111                 return rc;
3112
3113         reg_arr = ptp->tx_regs;
3114         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3115         if (rc)
3116                 return rc;
3117
3118         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3119                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3120
3121         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3122                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3123
3124         return 0;
3125 }
3126
3127 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3128 {
3129         rte_write32(0, (uint8_t *)bp->bar0 +
3130                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3131         rte_write32(0, (uint8_t *)bp->bar0 +
3132                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3133 }
3134
3135 static uint64_t bnxt_cc_read(struct bnxt *bp)
3136 {
3137         uint64_t ns;
3138
3139         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3140                               BNXT_GRCPF_REG_SYNC_TIME));
3141         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3142                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3143         return ns;
3144 }
3145
3146 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3147 {
3148         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3149         uint32_t fifo;
3150
3151         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3152                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3153         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3154                 return -EAGAIN;
3155
3156         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3157                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3158         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3159                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3160         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3161                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3162
3163         return 0;
3164 }
3165
3166 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3167 {
3168         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3169         struct bnxt_pf_info *pf = bp->pf;
3170         uint16_t port_id;
3171         uint32_t fifo;
3172
3173         if (!ptp)
3174                 return -ENODEV;
3175
3176         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3177                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3178         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3179                 return -EAGAIN;
3180
3181         port_id = pf->port_id;
3182         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3183                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3184
3185         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3186                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3187         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3188 /*              bnxt_clr_rx_ts(bp);       TBD  */
3189                 return -EBUSY;
3190         }
3191
3192         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3193                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3194         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3195                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3196
3197         return 0;
3198 }
3199
3200 static int
3201 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3202 {
3203         uint64_t ns;
3204         struct bnxt *bp = dev->data->dev_private;
3205         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3206
3207         if (!ptp)
3208                 return 0;
3209
3210         ns = rte_timespec_to_ns(ts);
3211         /* Set the timecounters to a new value. */
3212         ptp->tc.nsec = ns;
3213
3214         return 0;
3215 }
3216
3217 static int
3218 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3219 {
3220         struct bnxt *bp = dev->data->dev_private;
3221         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3222         uint64_t ns, systime_cycles = 0;
3223         int rc = 0;
3224
3225         if (!ptp)
3226                 return 0;
3227
3228         if (BNXT_CHIP_P5(bp))
3229                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3230                                              &systime_cycles);
3231         else
3232                 systime_cycles = bnxt_cc_read(bp);
3233
3234         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3235         *ts = rte_ns_to_timespec(ns);
3236
3237         return rc;
3238 }
3239 static int
3240 bnxt_timesync_enable(struct rte_eth_dev *dev)
3241 {
3242         struct bnxt *bp = dev->data->dev_private;
3243         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3244         uint32_t shift = 0;
3245         int rc;
3246
3247         if (!ptp)
3248                 return 0;
3249
3250         ptp->rx_filter = 1;
3251         ptp->tx_tstamp_en = 1;
3252         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3253
3254         rc = bnxt_hwrm_ptp_cfg(bp);
3255         if (rc)
3256                 return rc;
3257
3258         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3259         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3260         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3261
3262         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3263         ptp->tc.cc_shift = shift;
3264         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3265
3266         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3267         ptp->rx_tstamp_tc.cc_shift = shift;
3268         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3269
3270         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3271         ptp->tx_tstamp_tc.cc_shift = shift;
3272         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3273
3274         if (!BNXT_CHIP_P5(bp))
3275                 bnxt_map_ptp_regs(bp);
3276
3277         return 0;
3278 }
3279
3280 static int
3281 bnxt_timesync_disable(struct rte_eth_dev *dev)
3282 {
3283         struct bnxt *bp = dev->data->dev_private;
3284         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3285
3286         if (!ptp)
3287                 return 0;
3288
3289         ptp->rx_filter = 0;
3290         ptp->tx_tstamp_en = 0;
3291         ptp->rxctl = 0;
3292
3293         bnxt_hwrm_ptp_cfg(bp);
3294
3295         if (!BNXT_CHIP_P5(bp))
3296                 bnxt_unmap_ptp_regs(bp);
3297
3298         return 0;
3299 }
3300
3301 static int
3302 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3303                                  struct timespec *timestamp,
3304                                  uint32_t flags __rte_unused)
3305 {
3306         struct bnxt *bp = dev->data->dev_private;
3307         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3308         uint64_t rx_tstamp_cycles = 0;
3309         uint64_t ns;
3310
3311         if (!ptp)
3312                 return 0;
3313
3314         if (BNXT_CHIP_P5(bp))
3315                 rx_tstamp_cycles = ptp->rx_timestamp;
3316         else
3317                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3318
3319         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3320         *timestamp = rte_ns_to_timespec(ns);
3321         return  0;
3322 }
3323
3324 static int
3325 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3326                                  struct timespec *timestamp)
3327 {
3328         struct bnxt *bp = dev->data->dev_private;
3329         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3330         uint64_t tx_tstamp_cycles = 0;
3331         uint64_t ns;
3332         int rc = 0;
3333
3334         if (!ptp)
3335                 return 0;
3336
3337         if (BNXT_CHIP_P5(bp))
3338                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3339                                              &tx_tstamp_cycles);
3340         else
3341                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3342
3343         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3344         *timestamp = rte_ns_to_timespec(ns);
3345
3346         return rc;
3347 }
3348
3349 static int
3350 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3351 {
3352         struct bnxt *bp = dev->data->dev_private;
3353         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3354
3355         if (!ptp)
3356                 return 0;
3357
3358         ptp->tc.nsec += delta;
3359
3360         return 0;
3361 }
3362
3363 static int
3364 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3365 {
3366         struct bnxt *bp = dev->data->dev_private;
3367         int rc;
3368         uint32_t dir_entries;
3369         uint32_t entry_length;
3370
3371         rc = is_bnxt_in_error(bp);
3372         if (rc)
3373                 return rc;
3374
3375         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3376                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3377                     bp->pdev->addr.devid, bp->pdev->addr.function);
3378
3379         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3380         if (rc != 0)
3381                 return rc;
3382
3383         return dir_entries * entry_length;
3384 }
3385
3386 static int
3387 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3388                 struct rte_dev_eeprom_info *in_eeprom)
3389 {
3390         struct bnxt *bp = dev->data->dev_private;
3391         uint32_t index;
3392         uint32_t offset;
3393         int rc;
3394
3395         rc = is_bnxt_in_error(bp);
3396         if (rc)
3397                 return rc;
3398
3399         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3400                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3401                     bp->pdev->addr.devid, bp->pdev->addr.function,
3402                     in_eeprom->offset, in_eeprom->length);
3403
3404         if (in_eeprom->offset == 0) /* special offset value to get directory */
3405                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3406                                                 in_eeprom->data);
3407
3408         index = in_eeprom->offset >> 24;
3409         offset = in_eeprom->offset & 0xffffff;
3410
3411         if (index != 0)
3412                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3413                                            in_eeprom->length, in_eeprom->data);
3414
3415         return 0;
3416 }
3417
3418 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3419 {
3420         switch (dir_type) {
3421         case BNX_DIR_TYPE_CHIMP_PATCH:
3422         case BNX_DIR_TYPE_BOOTCODE:
3423         case BNX_DIR_TYPE_BOOTCODE_2:
3424         case BNX_DIR_TYPE_APE_FW:
3425         case BNX_DIR_TYPE_APE_PATCH:
3426         case BNX_DIR_TYPE_KONG_FW:
3427         case BNX_DIR_TYPE_KONG_PATCH:
3428         case BNX_DIR_TYPE_BONO_FW:
3429         case BNX_DIR_TYPE_BONO_PATCH:
3430                 /* FALLTHROUGH */
3431                 return true;
3432         }
3433
3434         return false;
3435 }
3436
3437 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3438 {
3439         switch (dir_type) {
3440         case BNX_DIR_TYPE_AVS:
3441         case BNX_DIR_TYPE_EXP_ROM_MBA:
3442         case BNX_DIR_TYPE_PCIE:
3443         case BNX_DIR_TYPE_TSCF_UCODE:
3444         case BNX_DIR_TYPE_EXT_PHY:
3445         case BNX_DIR_TYPE_CCM:
3446         case BNX_DIR_TYPE_ISCSI_BOOT:
3447         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3448         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3449                 /* FALLTHROUGH */
3450                 return true;
3451         }
3452
3453         return false;
3454 }
3455
3456 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3457 {
3458         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3459                 bnxt_dir_type_is_other_exec_format(dir_type);
3460 }
3461
3462 static int
3463 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3464                 struct rte_dev_eeprom_info *in_eeprom)
3465 {
3466         struct bnxt *bp = dev->data->dev_private;
3467         uint8_t index, dir_op;
3468         uint16_t type, ext, ordinal, attr;
3469         int rc;
3470
3471         rc = is_bnxt_in_error(bp);
3472         if (rc)
3473                 return rc;
3474
3475         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3476                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3477                     bp->pdev->addr.devid, bp->pdev->addr.function,
3478                     in_eeprom->offset, in_eeprom->length);
3479
3480         if (!BNXT_PF(bp)) {
3481                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3482                 return -EINVAL;
3483         }
3484
3485         type = in_eeprom->magic >> 16;
3486
3487         if (type == 0xffff) { /* special value for directory operations */
3488                 index = in_eeprom->magic & 0xff;
3489                 dir_op = in_eeprom->magic >> 8;
3490                 if (index == 0)
3491                         return -EINVAL;
3492                 switch (dir_op) {
3493                 case 0x0e: /* erase */
3494                         if (in_eeprom->offset != ~in_eeprom->magic)
3495                                 return -EINVAL;
3496                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3497                 default:
3498                         return -EINVAL;
3499                 }
3500         }
3501
3502         /* Create or re-write an NVM item: */
3503         if (bnxt_dir_type_is_executable(type) == true)
3504                 return -EOPNOTSUPP;
3505         ext = in_eeprom->magic & 0xffff;
3506         ordinal = in_eeprom->offset >> 16;
3507         attr = in_eeprom->offset & 0xffff;
3508
3509         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3510                                      in_eeprom->data, in_eeprom->length);
3511 }
3512
3513 /*
3514  * Initialization
3515  */
3516
3517 static const struct eth_dev_ops bnxt_dev_ops = {
3518         .dev_infos_get = bnxt_dev_info_get_op,
3519         .dev_close = bnxt_dev_close_op,
3520         .dev_configure = bnxt_dev_configure_op,
3521         .dev_start = bnxt_dev_start_op,
3522         .dev_stop = bnxt_dev_stop_op,
3523         .dev_set_link_up = bnxt_dev_set_link_up_op,
3524         .dev_set_link_down = bnxt_dev_set_link_down_op,
3525         .stats_get = bnxt_stats_get_op,
3526         .stats_reset = bnxt_stats_reset_op,
3527         .rx_queue_setup = bnxt_rx_queue_setup_op,
3528         .rx_queue_release = bnxt_rx_queue_release_op,
3529         .tx_queue_setup = bnxt_tx_queue_setup_op,
3530         .tx_queue_release = bnxt_tx_queue_release_op,
3531         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3532         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3533         .reta_update = bnxt_reta_update_op,
3534         .reta_query = bnxt_reta_query_op,
3535         .rss_hash_update = bnxt_rss_hash_update_op,
3536         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3537         .link_update = bnxt_link_update_op,
3538         .promiscuous_enable = bnxt_promiscuous_enable_op,
3539         .promiscuous_disable = bnxt_promiscuous_disable_op,
3540         .allmulticast_enable = bnxt_allmulticast_enable_op,
3541         .allmulticast_disable = bnxt_allmulticast_disable_op,
3542         .mac_addr_add = bnxt_mac_addr_add_op,
3543         .mac_addr_remove = bnxt_mac_addr_remove_op,
3544         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3545         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3546         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3547         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3548         .vlan_filter_set = bnxt_vlan_filter_set_op,
3549         .vlan_offload_set = bnxt_vlan_offload_set_op,
3550         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3551         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3552         .mtu_set = bnxt_mtu_set_op,
3553         .mac_addr_set = bnxt_set_default_mac_addr_op,
3554         .xstats_get = bnxt_dev_xstats_get_op,
3555         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3556         .xstats_reset = bnxt_dev_xstats_reset_op,
3557         .fw_version_get = bnxt_fw_version_get,
3558         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3559         .rxq_info_get = bnxt_rxq_info_get_op,
3560         .txq_info_get = bnxt_txq_info_get_op,
3561         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3562         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3563         .dev_led_on = bnxt_dev_led_on_op,
3564         .dev_led_off = bnxt_dev_led_off_op,
3565         .rx_queue_start = bnxt_rx_queue_start,
3566         .rx_queue_stop = bnxt_rx_queue_stop,
3567         .tx_queue_start = bnxt_tx_queue_start,
3568         .tx_queue_stop = bnxt_tx_queue_stop,
3569         .filter_ctrl = bnxt_filter_ctrl_op,
3570         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3571         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3572         .get_eeprom           = bnxt_get_eeprom_op,
3573         .set_eeprom           = bnxt_set_eeprom_op,
3574         .timesync_enable      = bnxt_timesync_enable,
3575         .timesync_disable     = bnxt_timesync_disable,
3576         .timesync_read_time   = bnxt_timesync_read_time,
3577         .timesync_write_time   = bnxt_timesync_write_time,
3578         .timesync_adjust_time = bnxt_timesync_adjust_time,
3579         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3580         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3581 };
3582
3583 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3584 {
3585         uint32_t offset;
3586
3587         /* Only pre-map the reset GRC registers using window 3 */
3588         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3589                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3590
3591         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3592
3593         return offset;
3594 }
3595
3596 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3597 {
3598         struct bnxt_error_recovery_info *info = bp->recovery_info;
3599         uint32_t reg_base = 0xffffffff;
3600         int i;
3601
3602         /* Only pre-map the monitoring GRC registers using window 2 */
3603         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3604                 uint32_t reg = info->status_regs[i];
3605
3606                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3607                         continue;
3608
3609                 if (reg_base == 0xffffffff)
3610                         reg_base = reg & 0xfffff000;
3611                 if ((reg & 0xfffff000) != reg_base)
3612                         return -ERANGE;
3613
3614                 /* Use mask 0xffc as the Lower 2 bits indicates
3615                  * address space location
3616                  */
3617                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3618                                                 (reg & 0xffc);
3619         }
3620
3621         if (reg_base == 0xffffffff)
3622                 return 0;
3623
3624         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3625                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3626
3627         return 0;
3628 }
3629
3630 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3631 {
3632         struct bnxt_error_recovery_info *info = bp->recovery_info;
3633         uint32_t delay = info->delay_after_reset[index];
3634         uint32_t val = info->reset_reg_val[index];
3635         uint32_t reg = info->reset_reg[index];
3636         uint32_t type, offset;
3637
3638         type = BNXT_FW_STATUS_REG_TYPE(reg);
3639         offset = BNXT_FW_STATUS_REG_OFF(reg);
3640
3641         switch (type) {
3642         case BNXT_FW_STATUS_REG_TYPE_CFG:
3643                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3644                 break;
3645         case BNXT_FW_STATUS_REG_TYPE_GRC:
3646                 offset = bnxt_map_reset_regs(bp, offset);
3647                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3648                 break;
3649         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3650                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3651                 break;
3652         }
3653         /* wait on a specific interval of time until core reset is complete */
3654         if (delay)
3655                 rte_delay_ms(delay);
3656 }
3657
3658 static void bnxt_dev_cleanup(struct bnxt *bp)
3659 {
3660         bp->eth_dev->data->dev_link.link_status = 0;
3661         bp->link_info->link_up = 0;
3662         if (bp->eth_dev->data->dev_started)
3663                 bnxt_dev_stop_op(bp->eth_dev);
3664
3665         bnxt_uninit_resources(bp, true);
3666 }
3667
3668 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3669 {
3670         struct rte_eth_dev *dev = bp->eth_dev;
3671         struct rte_vlan_filter_conf *vfc;
3672         int vidx, vbit, rc;
3673         uint16_t vlan_id;
3674
3675         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3676                 vfc = &dev->data->vlan_filter_conf;
3677                 vidx = vlan_id / 64;
3678                 vbit = vlan_id % 64;
3679
3680                 /* Each bit corresponds to a VLAN id */
3681                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3682                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3683                         if (rc)
3684                                 return rc;
3685                 }
3686         }
3687
3688         return 0;
3689 }
3690
3691 static int bnxt_restore_mac_filters(struct bnxt *bp)
3692 {
3693         struct rte_eth_dev *dev = bp->eth_dev;
3694         struct rte_eth_dev_info dev_info;
3695         struct rte_ether_addr *addr;
3696         uint64_t pool_mask;
3697         uint32_t pool = 0;
3698         uint16_t i;
3699         int rc;
3700
3701         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3702                 return 0;
3703
3704         rc = bnxt_dev_info_get_op(dev, &dev_info);
3705         if (rc)
3706                 return rc;
3707
3708         /* replay MAC address configuration */
3709         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3710                 addr = &dev->data->mac_addrs[i];
3711
3712                 /* skip zero address */
3713                 if (rte_is_zero_ether_addr(addr))
3714                         continue;
3715
3716                 pool = 0;
3717                 pool_mask = dev->data->mac_pool_sel[i];
3718
3719                 do {
3720                         if (pool_mask & 1ULL) {
3721                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3722                                 if (rc)
3723                                         return rc;
3724                         }
3725                         pool_mask >>= 1;
3726                         pool++;
3727                 } while (pool_mask);
3728         }
3729
3730         return 0;
3731 }
3732
3733 static int bnxt_restore_filters(struct bnxt *bp)
3734 {
3735         struct rte_eth_dev *dev = bp->eth_dev;
3736         int ret = 0;
3737
3738         if (dev->data->all_multicast) {
3739                 ret = bnxt_allmulticast_enable_op(dev);
3740                 if (ret)
3741                         return ret;
3742         }
3743         if (dev->data->promiscuous) {
3744                 ret = bnxt_promiscuous_enable_op(dev);
3745                 if (ret)
3746                         return ret;
3747         }
3748
3749         ret = bnxt_restore_mac_filters(bp);
3750         if (ret)
3751                 return ret;
3752
3753         ret = bnxt_restore_vlan_filters(bp);
3754         /* TODO restore other filters as well */
3755         return ret;
3756 }
3757
3758 static void bnxt_dev_recover(void *arg)
3759 {
3760         struct bnxt *bp = arg;
3761         int timeout = bp->fw_reset_max_msecs;
3762         int rc = 0;
3763
3764         /* Clear Error flag so that device re-init should happen */
3765         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3766
3767         do {
3768                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3769                 if (rc == 0)
3770                         break;
3771                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3772                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3773         } while (rc && timeout);
3774
3775         if (rc) {
3776                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3777                 goto err;
3778         }
3779
3780         rc = bnxt_init_resources(bp, true);
3781         if (rc) {
3782                 PMD_DRV_LOG(ERR,
3783                             "Failed to initialize resources after reset\n");
3784                 goto err;
3785         }
3786         /* clear reset flag as the device is initialized now */
3787         bp->flags &= ~BNXT_FLAG_FW_RESET;
3788
3789         rc = bnxt_dev_start_op(bp->eth_dev);
3790         if (rc) {
3791                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3792                 goto err_start;
3793         }
3794
3795         rc = bnxt_restore_filters(bp);
3796         if (rc)
3797                 goto err_start;
3798
3799         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3800         return;
3801 err_start:
3802         bnxt_dev_stop_op(bp->eth_dev);
3803 err:
3804         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3805         bnxt_uninit_resources(bp, false);
3806         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3807 }
3808
3809 void bnxt_dev_reset_and_resume(void *arg)
3810 {
3811         struct bnxt *bp = arg;
3812         int rc;
3813
3814         bnxt_dev_cleanup(bp);
3815
3816         bnxt_wait_for_device_shutdown(bp);
3817
3818         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3819                                bnxt_dev_recover, (void *)bp);
3820         if (rc)
3821                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3822 }
3823
3824 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3825 {
3826         struct bnxt_error_recovery_info *info = bp->recovery_info;
3827         uint32_t reg = info->status_regs[index];
3828         uint32_t type, offset, val = 0;
3829
3830         type = BNXT_FW_STATUS_REG_TYPE(reg);
3831         offset = BNXT_FW_STATUS_REG_OFF(reg);
3832
3833         switch (type) {
3834         case BNXT_FW_STATUS_REG_TYPE_CFG:
3835                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3836                 break;
3837         case BNXT_FW_STATUS_REG_TYPE_GRC:
3838                 offset = info->mapped_status_regs[index];
3839                 /* FALLTHROUGH */
3840         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3841                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3842                                        offset));
3843                 break;
3844         }
3845
3846         return val;
3847 }
3848
3849 static int bnxt_fw_reset_all(struct bnxt *bp)
3850 {
3851         struct bnxt_error_recovery_info *info = bp->recovery_info;
3852         uint32_t i;
3853         int rc = 0;
3854
3855         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3856                 /* Reset through master function driver */
3857                 for (i = 0; i < info->reg_array_cnt; i++)
3858                         bnxt_write_fw_reset_reg(bp, i);
3859                 /* Wait for time specified by FW after triggering reset */
3860                 rte_delay_ms(info->master_func_wait_period_after_reset);
3861         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3862                 /* Reset with the help of Kong processor */
3863                 rc = bnxt_hwrm_fw_reset(bp);
3864                 if (rc)
3865                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3866         }
3867
3868         return rc;
3869 }
3870
3871 static void bnxt_fw_reset_cb(void *arg)
3872 {
3873         struct bnxt *bp = arg;
3874         struct bnxt_error_recovery_info *info = bp->recovery_info;
3875         int rc = 0;
3876
3877         /* Only Master function can do FW reset */
3878         if (bnxt_is_master_func(bp) &&
3879             bnxt_is_recovery_enabled(bp)) {
3880                 rc = bnxt_fw_reset_all(bp);
3881                 if (rc) {
3882                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3883                         return;
3884                 }
3885         }
3886
3887         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3888          * EXCEPTION_FATAL_ASYNC event to all the functions
3889          * (including MASTER FUNC). After receiving this Async, all the active
3890          * drivers should treat this case as FW initiated recovery
3891          */
3892         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3893                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3894                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3895
3896                 /* To recover from error */
3897                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3898                                   (void *)bp);
3899         }
3900 }
3901
3902 /* Driver should poll FW heartbeat, reset_counter with the frequency
3903  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3904  * When the driver detects heartbeat stop or change in reset_counter,
3905  * it has to trigger a reset to recover from the error condition.
3906  * A “master PF” is the function who will have the privilege to
3907  * initiate the chimp reset. The master PF will be elected by the
3908  * firmware and will be notified through async message.
3909  */
3910 static void bnxt_check_fw_health(void *arg)
3911 {
3912         struct bnxt *bp = arg;
3913         struct bnxt_error_recovery_info *info = bp->recovery_info;
3914         uint32_t val = 0, wait_msec;
3915
3916         if (!info || !bnxt_is_recovery_enabled(bp) ||
3917             is_bnxt_in_error(bp))
3918                 return;
3919
3920         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3921         if (val == info->last_heart_beat)
3922                 goto reset;
3923
3924         info->last_heart_beat = val;
3925
3926         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3927         if (val != info->last_reset_counter)
3928                 goto reset;
3929
3930         info->last_reset_counter = val;
3931
3932         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3933                           bnxt_check_fw_health, (void *)bp);
3934
3935         return;
3936 reset:
3937         /* Stop DMA to/from device */
3938         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3939         bp->flags |= BNXT_FLAG_FW_RESET;
3940
3941         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3942
3943         if (bnxt_is_master_func(bp))
3944                 wait_msec = info->master_func_wait_period;
3945         else
3946                 wait_msec = info->normal_func_wait_period;
3947
3948         rte_eal_alarm_set(US_PER_MS * wait_msec,
3949                           bnxt_fw_reset_cb, (void *)bp);
3950 }
3951
3952 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3953 {
3954         uint32_t polling_freq;
3955
3956         pthread_mutex_lock(&bp->health_check_lock);
3957
3958         if (!bnxt_is_recovery_enabled(bp))
3959                 goto done;
3960
3961         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3962                 goto done;
3963
3964         polling_freq = bp->recovery_info->driver_polling_freq;
3965
3966         rte_eal_alarm_set(US_PER_MS * polling_freq,
3967                           bnxt_check_fw_health, (void *)bp);
3968         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3969
3970 done:
3971         pthread_mutex_unlock(&bp->health_check_lock);
3972 }
3973
3974 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3975 {
3976         if (!bnxt_is_recovery_enabled(bp))
3977                 return;
3978
3979         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3980         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3981 }
3982
3983 static bool bnxt_vf_pciid(uint16_t device_id)
3984 {
3985         switch (device_id) {
3986         case BROADCOM_DEV_ID_57304_VF:
3987         case BROADCOM_DEV_ID_57406_VF:
3988         case BROADCOM_DEV_ID_5731X_VF:
3989         case BROADCOM_DEV_ID_5741X_VF:
3990         case BROADCOM_DEV_ID_57414_VF:
3991         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
3992         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
3993         case BROADCOM_DEV_ID_58802_VF:
3994         case BROADCOM_DEV_ID_57500_VF1:
3995         case BROADCOM_DEV_ID_57500_VF2:
3996                 /* FALLTHROUGH */
3997                 return true;
3998         default:
3999                 return false;
4000         }
4001 }
4002
4003 /* Phase 5 device */
4004 static bool bnxt_p5_device(uint16_t device_id)
4005 {
4006         switch (device_id) {
4007         case BROADCOM_DEV_ID_57508:
4008         case BROADCOM_DEV_ID_57504:
4009         case BROADCOM_DEV_ID_57502:
4010         case BROADCOM_DEV_ID_57508_MF1:
4011         case BROADCOM_DEV_ID_57504_MF1:
4012         case BROADCOM_DEV_ID_57502_MF1:
4013         case BROADCOM_DEV_ID_57508_MF2:
4014         case BROADCOM_DEV_ID_57504_MF2:
4015         case BROADCOM_DEV_ID_57502_MF2:
4016         case BROADCOM_DEV_ID_57500_VF1:
4017         case BROADCOM_DEV_ID_57500_VF2:
4018                 /* FALLTHROUGH */
4019                 return true;
4020         default:
4021                 return false;
4022         }
4023 }
4024
4025 bool bnxt_stratus_device(struct bnxt *bp)
4026 {
4027         uint16_t device_id = bp->pdev->id.device_id;
4028
4029         switch (device_id) {
4030         case BROADCOM_DEV_ID_STRATUS_NIC:
4031         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4032         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4033                 /* FALLTHROUGH */
4034                 return true;
4035         default:
4036                 return false;
4037         }
4038 }
4039
4040 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4041 {
4042         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4043         struct bnxt *bp = eth_dev->data->dev_private;
4044
4045         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4046         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4047         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4048         if (!bp->bar0 || !bp->doorbell_base) {
4049                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4050                 return -ENODEV;
4051         }
4052
4053         bp->eth_dev = eth_dev;
4054         bp->pdev = pci_dev;
4055
4056         return 0;
4057 }
4058
4059 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4060                                   struct bnxt_ctx_pg_info *ctx_pg,
4061                                   uint32_t mem_size,
4062                                   const char *suffix,
4063                                   uint16_t idx)
4064 {
4065         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4066         const struct rte_memzone *mz = NULL;
4067         char mz_name[RTE_MEMZONE_NAMESIZE];
4068         rte_iova_t mz_phys_addr;
4069         uint64_t valid_bits = 0;
4070         uint32_t sz;
4071         int i;
4072
4073         if (!mem_size)
4074                 return 0;
4075
4076         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4077                          BNXT_PAGE_SIZE;
4078         rmem->page_size = BNXT_PAGE_SIZE;
4079         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4080         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4081         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4082
4083         valid_bits = PTU_PTE_VALID;
4084
4085         if (rmem->nr_pages > 1) {
4086                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4087                          "bnxt_ctx_pg_tbl%s_%x_%d",
4088                          suffix, idx, bp->eth_dev->data->port_id);
4089                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4090                 mz = rte_memzone_lookup(mz_name);
4091                 if (!mz) {
4092                         mz = rte_memzone_reserve_aligned(mz_name,
4093                                                 rmem->nr_pages * 8,
4094                                                 SOCKET_ID_ANY,
4095                                                 RTE_MEMZONE_2MB |
4096                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4097                                                 RTE_MEMZONE_IOVA_CONTIG,
4098                                                 BNXT_PAGE_SIZE);
4099                         if (mz == NULL)
4100                                 return -ENOMEM;
4101                 }
4102
4103                 memset(mz->addr, 0, mz->len);
4104                 mz_phys_addr = mz->iova;
4105
4106                 rmem->pg_tbl = mz->addr;
4107                 rmem->pg_tbl_map = mz_phys_addr;
4108                 rmem->pg_tbl_mz = mz;
4109         }
4110
4111         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4112                  suffix, idx, bp->eth_dev->data->port_id);
4113         mz = rte_memzone_lookup(mz_name);
4114         if (!mz) {
4115                 mz = rte_memzone_reserve_aligned(mz_name,
4116                                                  mem_size,
4117                                                  SOCKET_ID_ANY,
4118                                                  RTE_MEMZONE_1GB |
4119                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4120                                                  RTE_MEMZONE_IOVA_CONTIG,
4121                                                  BNXT_PAGE_SIZE);
4122                 if (mz == NULL)
4123                         return -ENOMEM;
4124         }
4125
4126         memset(mz->addr, 0, mz->len);
4127         mz_phys_addr = mz->iova;
4128
4129         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4130                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4131                 rmem->dma_arr[i] = mz_phys_addr + sz;
4132
4133                 if (rmem->nr_pages > 1) {
4134                         if (i == rmem->nr_pages - 2 &&
4135                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4136                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4137                         else if (i == rmem->nr_pages - 1 &&
4138                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4139                                 valid_bits |= PTU_PTE_LAST;
4140
4141                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4142                                                            valid_bits);
4143                 }
4144         }
4145
4146         rmem->mz = mz;
4147         if (rmem->vmem_size)
4148                 rmem->vmem = (void **)mz->addr;
4149         rmem->dma_arr[0] = mz_phys_addr;
4150         return 0;
4151 }
4152
4153 static void bnxt_free_ctx_mem(struct bnxt *bp)
4154 {
4155         int i;
4156
4157         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4158                 return;
4159
4160         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4161         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4162         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4163         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4164         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4165         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4166         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4167         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4168         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4169         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4170         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4171
4172         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4173                 if (bp->ctx->tqm_mem[i])
4174                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4175         }
4176
4177         rte_free(bp->ctx);
4178         bp->ctx = NULL;
4179 }
4180
4181 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4182
4183 #define min_t(type, x, y) ({                    \
4184         type __min1 = (x);                      \
4185         type __min2 = (y);                      \
4186         __min1 < __min2 ? __min1 : __min2; })
4187
4188 #define max_t(type, x, y) ({                    \
4189         type __max1 = (x);                      \
4190         type __max2 = (y);                      \
4191         __max1 > __max2 ? __max1 : __max2; })
4192
4193 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4194
4195 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4196 {
4197         struct bnxt_ctx_pg_info *ctx_pg;
4198         struct bnxt_ctx_mem_info *ctx;
4199         uint32_t mem_size, ena, entries;
4200         uint32_t entries_sp, min;
4201         int i, rc;
4202
4203         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4204         if (rc) {
4205                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4206                 return rc;
4207         }
4208         ctx = bp->ctx;
4209         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4210                 return 0;
4211
4212         ctx_pg = &ctx->qp_mem;
4213         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4214         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4215         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4216         if (rc)
4217                 return rc;
4218
4219         ctx_pg = &ctx->srq_mem;
4220         ctx_pg->entries = ctx->srq_max_l2_entries;
4221         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4222         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4223         if (rc)
4224                 return rc;
4225
4226         ctx_pg = &ctx->cq_mem;
4227         ctx_pg->entries = ctx->cq_max_l2_entries;
4228         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4229         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4230         if (rc)
4231                 return rc;
4232
4233         ctx_pg = &ctx->vnic_mem;
4234         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4235                 ctx->vnic_max_ring_table_entries;
4236         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4237         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4238         if (rc)
4239                 return rc;
4240
4241         ctx_pg = &ctx->stat_mem;
4242         ctx_pg->entries = ctx->stat_max_entries;
4243         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4244         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4245         if (rc)
4246                 return rc;
4247
4248         min = ctx->tqm_min_entries_per_ring;
4249
4250         entries_sp = ctx->qp_max_l2_entries +
4251                      ctx->vnic_max_vnic_entries +
4252                      2 * ctx->qp_min_qp1_entries + min;
4253         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4254
4255         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4256         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4257         entries = clamp_t(uint32_t, entries, min,
4258                           ctx->tqm_max_entries_per_ring);
4259         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4260                 ctx_pg = ctx->tqm_mem[i];
4261                 ctx_pg->entries = i ? entries : entries_sp;
4262                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4263                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4264                 if (rc)
4265                         return rc;
4266                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4267         }
4268
4269         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4270         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4271         if (rc)
4272                 PMD_DRV_LOG(ERR,
4273                             "Failed to configure context mem: rc = %d\n", rc);
4274         else
4275                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4276
4277         return rc;
4278 }
4279
4280 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4281 {
4282         struct rte_pci_device *pci_dev = bp->pdev;
4283         char mz_name[RTE_MEMZONE_NAMESIZE];
4284         const struct rte_memzone *mz = NULL;
4285         uint32_t total_alloc_len;
4286         rte_iova_t mz_phys_addr;
4287
4288         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4289                 return 0;
4290
4291         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4292                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4293                  pci_dev->addr.bus, pci_dev->addr.devid,
4294                  pci_dev->addr.function, "rx_port_stats");
4295         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4296         mz = rte_memzone_lookup(mz_name);
4297         total_alloc_len =
4298                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4299                                        sizeof(struct rx_port_stats_ext) + 512);
4300         if (!mz) {
4301                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4302                                          SOCKET_ID_ANY,
4303                                          RTE_MEMZONE_2MB |
4304                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4305                                          RTE_MEMZONE_IOVA_CONTIG);
4306                 if (mz == NULL)
4307                         return -ENOMEM;
4308         }
4309         memset(mz->addr, 0, mz->len);
4310         mz_phys_addr = mz->iova;
4311
4312         bp->rx_mem_zone = (const void *)mz;
4313         bp->hw_rx_port_stats = mz->addr;
4314         bp->hw_rx_port_stats_map = mz_phys_addr;
4315
4316         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4317                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4318                  pci_dev->addr.bus, pci_dev->addr.devid,
4319                  pci_dev->addr.function, "tx_port_stats");
4320         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4321         mz = rte_memzone_lookup(mz_name);
4322         total_alloc_len =
4323                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4324                                        sizeof(struct tx_port_stats_ext) + 512);
4325         if (!mz) {
4326                 mz = rte_memzone_reserve(mz_name,
4327                                          total_alloc_len,
4328                                          SOCKET_ID_ANY,
4329                                          RTE_MEMZONE_2MB |
4330                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4331                                          RTE_MEMZONE_IOVA_CONTIG);
4332                 if (mz == NULL)
4333                         return -ENOMEM;
4334         }
4335         memset(mz->addr, 0, mz->len);
4336         mz_phys_addr = mz->iova;
4337
4338         bp->tx_mem_zone = (const void *)mz;
4339         bp->hw_tx_port_stats = mz->addr;
4340         bp->hw_tx_port_stats_map = mz_phys_addr;
4341         bp->flags |= BNXT_FLAG_PORT_STATS;
4342
4343         /* Display extended statistics if FW supports it */
4344         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4345             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4346             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4347                 return 0;
4348
4349         bp->hw_rx_port_stats_ext = (void *)
4350                 ((uint8_t *)bp->hw_rx_port_stats +
4351                  sizeof(struct rx_port_stats));
4352         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4353                 sizeof(struct rx_port_stats);
4354         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4355
4356         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4357             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4358                 bp->hw_tx_port_stats_ext = (void *)
4359                         ((uint8_t *)bp->hw_tx_port_stats +
4360                          sizeof(struct tx_port_stats));
4361                 bp->hw_tx_port_stats_ext_map =
4362                         bp->hw_tx_port_stats_map +
4363                         sizeof(struct tx_port_stats);
4364                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4365         }
4366
4367         return 0;
4368 }
4369
4370 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4371 {
4372         struct bnxt *bp = eth_dev->data->dev_private;
4373         int rc = 0;
4374
4375         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4376                                                RTE_ETHER_ADDR_LEN *
4377                                                bp->max_l2_ctx,
4378                                                0);
4379         if (eth_dev->data->mac_addrs == NULL) {
4380                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4381                 return -ENOMEM;
4382         }
4383
4384         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4385                 if (BNXT_PF(bp))
4386                         return -EINVAL;
4387
4388                 /* Generate a random MAC address, if none was assigned by PF */
4389                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4390                 bnxt_eth_hw_addr_random(bp->mac_addr);
4391                 PMD_DRV_LOG(INFO,
4392                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4393                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4394                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4395
4396                 rc = bnxt_hwrm_set_mac(bp);
4397                 if (rc)
4398                         return rc;
4399         }
4400
4401         /* Copy the permanent MAC from the FUNC_QCAPS response */
4402         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4403
4404         return rc;
4405 }
4406
4407 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4408 {
4409         int rc = 0;
4410
4411         /* MAC is already configured in FW */
4412         if (BNXT_HAS_DFLT_MAC_SET(bp))
4413                 return 0;
4414
4415         /* Restore the old MAC configured */
4416         rc = bnxt_hwrm_set_mac(bp);
4417         if (rc)
4418                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4419
4420         return rc;
4421 }
4422
4423 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4424 {
4425         if (!BNXT_PF(bp))
4426                 return;
4427
4428         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4429
4430         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4431                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4432         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4433         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4434         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4435         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4436 }
4437
4438 uint16_t
4439 bnxt_get_svif(uint16_t port_id, bool func_svif,
4440               enum bnxt_ulp_intf_type type)
4441 {
4442         struct rte_eth_dev *eth_dev;
4443         struct bnxt *bp;
4444
4445         eth_dev = &rte_eth_devices[port_id];
4446         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4447                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4448                 if (!vfr)
4449                         return 0;
4450
4451                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4452                         return vfr->svif;
4453
4454                 eth_dev = vfr->parent_dev;
4455         }
4456
4457         bp = eth_dev->data->dev_private;
4458
4459         return func_svif ? bp->func_svif : bp->port_svif;
4460 }
4461
4462 uint16_t
4463 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4464 {
4465         struct rte_eth_dev *eth_dev;
4466         struct bnxt_vnic_info *vnic;
4467         struct bnxt *bp;
4468
4469         eth_dev = &rte_eth_devices[port];
4470         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4471                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4472                 if (!vfr)
4473                         return 0;
4474
4475                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4476                         return vfr->dflt_vnic_id;
4477
4478                 eth_dev = vfr->parent_dev;
4479         }
4480
4481         bp = eth_dev->data->dev_private;
4482
4483         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4484
4485         return vnic->fw_vnic_id;
4486 }
4487
4488 uint16_t
4489 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4490 {
4491         struct rte_eth_dev *eth_dev;
4492         struct bnxt *bp;
4493
4494         eth_dev = &rte_eth_devices[port];
4495         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4496                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4497                 if (!vfr)
4498                         return 0;
4499
4500                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4501                         return vfr->fw_fid;
4502
4503                 eth_dev = vfr->parent_dev;
4504         }
4505
4506         bp = eth_dev->data->dev_private;
4507
4508         return bp->fw_fid;
4509 }
4510
4511 enum bnxt_ulp_intf_type
4512 bnxt_get_interface_type(uint16_t port)
4513 {
4514         struct rte_eth_dev *eth_dev;
4515         struct bnxt *bp;
4516
4517         eth_dev = &rte_eth_devices[port];
4518         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4519                 return BNXT_ULP_INTF_TYPE_VF_REP;
4520
4521         bp = eth_dev->data->dev_private;
4522         if (BNXT_PF(bp))
4523                 return BNXT_ULP_INTF_TYPE_PF;
4524         else if (BNXT_VF_IS_TRUSTED(bp))
4525                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4526         else if (BNXT_VF(bp))
4527                 return BNXT_ULP_INTF_TYPE_VF;
4528
4529         return BNXT_ULP_INTF_TYPE_INVALID;
4530 }
4531
4532 uint16_t
4533 bnxt_get_phy_port_id(uint16_t port_id)
4534 {
4535         struct bnxt_representor *vfr;
4536         struct rte_eth_dev *eth_dev;
4537         struct bnxt *bp;
4538
4539         eth_dev = &rte_eth_devices[port_id];
4540         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4541                 vfr = eth_dev->data->dev_private;
4542                 if (!vfr)
4543                         return 0;
4544
4545                 eth_dev = vfr->parent_dev;
4546         }
4547
4548         bp = eth_dev->data->dev_private;
4549
4550         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4551 }
4552
4553 uint16_t
4554 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4555 {
4556         struct rte_eth_dev *eth_dev;
4557         struct bnxt *bp;
4558
4559         eth_dev = &rte_eth_devices[port_id];
4560         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4561                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4562                 if (!vfr)
4563                         return 0;
4564
4565                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4566                         return vfr->fw_fid - 1;
4567
4568                 eth_dev = vfr->parent_dev;
4569         }
4570
4571         bp = eth_dev->data->dev_private;
4572
4573         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4574 }
4575
4576 uint16_t
4577 bnxt_get_vport(uint16_t port_id)
4578 {
4579         return (1 << bnxt_get_phy_port_id(port_id));
4580 }
4581
4582 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4583 {
4584         struct bnxt_error_recovery_info *info = bp->recovery_info;
4585
4586         if (info) {
4587                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4588                         memset(info, 0, sizeof(*info));
4589                 return;
4590         }
4591
4592         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4593                 return;
4594
4595         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4596                            sizeof(*info), 0);
4597         if (!info)
4598                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4599
4600         bp->recovery_info = info;
4601 }
4602
4603 static void bnxt_check_fw_status(struct bnxt *bp)
4604 {
4605         uint32_t fw_status;
4606
4607         if (!(bp->recovery_info &&
4608               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4609                 return;
4610
4611         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4612         if (fw_status != BNXT_FW_STATUS_HEALTHY)
4613                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4614                             fw_status);
4615 }
4616
4617 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4618 {
4619         struct bnxt_error_recovery_info *info = bp->recovery_info;
4620         uint32_t status_loc;
4621         uint32_t sig_ver;
4622
4623         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4624                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4625         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4626                                    BNXT_GRCP_WINDOW_2_BASE +
4627                                    offsetof(struct hcomm_status,
4628                                             sig_ver)));
4629         /* If the signature is absent, then FW does not support this feature */
4630         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4631             HCOMM_STATUS_SIGNATURE_VAL)
4632                 return 0;
4633
4634         if (!info) {
4635                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4636                                    sizeof(*info), 0);
4637                 if (!info)
4638                         return -ENOMEM;
4639                 bp->recovery_info = info;
4640         } else {
4641                 memset(info, 0, sizeof(*info));
4642         }
4643
4644         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4645                                       BNXT_GRCP_WINDOW_2_BASE +
4646                                       offsetof(struct hcomm_status,
4647                                                fw_status_loc)));
4648
4649         /* Only pre-map the FW health status GRC register */
4650         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4651                 return 0;
4652
4653         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4654         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4655                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4656
4657         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4658                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4659
4660         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4661
4662         return 0;
4663 }
4664
4665 static int bnxt_init_fw(struct bnxt *bp)
4666 {
4667         uint16_t mtu;
4668         int rc = 0;
4669
4670         bp->fw_cap = 0;
4671
4672         rc = bnxt_map_hcomm_fw_status_reg(bp);
4673         if (rc)
4674                 return rc;
4675
4676         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4677         if (rc) {
4678                 bnxt_check_fw_status(bp);
4679                 return rc;
4680         }
4681
4682         rc = bnxt_hwrm_func_reset(bp);
4683         if (rc)
4684                 return -EIO;
4685
4686         rc = bnxt_hwrm_vnic_qcaps(bp);
4687         if (rc)
4688                 return rc;
4689
4690         rc = bnxt_hwrm_queue_qportcfg(bp);
4691         if (rc)
4692                 return rc;
4693
4694         /* Get the MAX capabilities for this function.
4695          * This function also allocates context memory for TQM rings and
4696          * informs the firmware about this allocated backing store memory.
4697          */
4698         rc = bnxt_hwrm_func_qcaps(bp);
4699         if (rc)
4700                 return rc;
4701
4702         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4703         if (rc)
4704                 return rc;
4705
4706         bnxt_hwrm_port_mac_qcfg(bp);
4707
4708         bnxt_hwrm_parent_pf_qcfg(bp);
4709
4710         bnxt_hwrm_port_phy_qcaps(bp);
4711
4712         bnxt_alloc_error_recovery_info(bp);
4713         /* Get the adapter error recovery support info */
4714         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4715         if (rc)
4716                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4717
4718         bnxt_hwrm_port_led_qcaps(bp);
4719
4720         return 0;
4721 }
4722
4723 static int
4724 bnxt_init_locks(struct bnxt *bp)
4725 {
4726         int err;
4727
4728         err = pthread_mutex_init(&bp->flow_lock, NULL);
4729         if (err) {
4730                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4731                 return err;
4732         }
4733
4734         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4735         if (err) {
4736                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4737                 return err;
4738         }
4739
4740         err = pthread_mutex_init(&bp->health_check_lock, NULL);
4741         if (err)
4742                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4743         return err;
4744 }
4745
4746 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4747 {
4748         int rc = 0;
4749
4750         rc = bnxt_init_fw(bp);
4751         if (rc)
4752                 return rc;
4753
4754         if (!reconfig_dev) {
4755                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4756                 if (rc)
4757                         return rc;
4758         } else {
4759                 rc = bnxt_restore_dflt_mac(bp);
4760                 if (rc)
4761                         return rc;
4762         }
4763
4764         bnxt_config_vf_req_fwd(bp);
4765
4766         rc = bnxt_hwrm_func_driver_register(bp);
4767         if (rc) {
4768                 PMD_DRV_LOG(ERR, "Failed to register driver");
4769                 return -EBUSY;
4770         }
4771
4772         if (BNXT_PF(bp)) {
4773                 if (bp->pdev->max_vfs) {
4774                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4775                         if (rc) {
4776                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4777                                 return rc;
4778                         }
4779                 } else {
4780                         rc = bnxt_hwrm_allocate_pf_only(bp);
4781                         if (rc) {
4782                                 PMD_DRV_LOG(ERR,
4783                                             "Failed to allocate PF resources");
4784                                 return rc;
4785                         }
4786                 }
4787         }
4788
4789         rc = bnxt_alloc_mem(bp, reconfig_dev);
4790         if (rc)
4791                 return rc;
4792
4793         rc = bnxt_setup_int(bp);
4794         if (rc)
4795                 return rc;
4796
4797         rc = bnxt_request_int(bp);
4798         if (rc)
4799                 return rc;
4800
4801         rc = bnxt_init_ctx_mem(bp);
4802         if (rc) {
4803                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4804                 return rc;
4805         }
4806
4807         rc = bnxt_init_locks(bp);
4808         if (rc)
4809                 return rc;
4810
4811         return 0;
4812 }
4813
4814 static int
4815 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4816                           const char *value, void *opaque_arg)
4817 {
4818         struct bnxt *bp = opaque_arg;
4819         unsigned long truflow;
4820         char *end = NULL;
4821
4822         if (!value || !opaque_arg) {
4823                 PMD_DRV_LOG(ERR,
4824                             "Invalid parameter passed to truflow devargs.\n");
4825                 return -EINVAL;
4826         }
4827
4828         truflow = strtoul(value, &end, 10);
4829         if (end == NULL || *end != '\0' ||
4830             (truflow == ULONG_MAX && errno == ERANGE)) {
4831                 PMD_DRV_LOG(ERR,
4832                             "Invalid parameter passed to truflow devargs.\n");
4833                 return -EINVAL;
4834         }
4835
4836         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4837                 PMD_DRV_LOG(ERR,
4838                             "Invalid value passed to truflow devargs.\n");
4839                 return -EINVAL;
4840         }
4841
4842         if (truflow) {
4843                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4844                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4845         } else {
4846                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4847                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4848         }
4849
4850         return 0;
4851 }
4852
4853 static int
4854 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4855                              const char *value, void *opaque_arg)
4856 {
4857         struct bnxt *bp = opaque_arg;
4858         unsigned long flow_xstat;
4859         char *end = NULL;
4860
4861         if (!value || !opaque_arg) {
4862                 PMD_DRV_LOG(ERR,
4863                             "Invalid parameter passed to flow_xstat devarg.\n");
4864                 return -EINVAL;
4865         }
4866
4867         flow_xstat = strtoul(value, &end, 10);
4868         if (end == NULL || *end != '\0' ||
4869             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4870                 PMD_DRV_LOG(ERR,
4871                             "Invalid parameter passed to flow_xstat devarg.\n");
4872                 return -EINVAL;
4873         }
4874
4875         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4876                 PMD_DRV_LOG(ERR,
4877                             "Invalid value passed to flow_xstat devarg.\n");
4878                 return -EINVAL;
4879         }
4880
4881         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4882         if (BNXT_FLOW_XSTATS_EN(bp))
4883                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4884
4885         return 0;
4886 }
4887
4888 static int
4889 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4890                                         const char *value, void *opaque_arg)
4891 {
4892         struct bnxt *bp = opaque_arg;
4893         unsigned long max_num_kflows;
4894         char *end = NULL;
4895
4896         if (!value || !opaque_arg) {
4897                 PMD_DRV_LOG(ERR,
4898                         "Invalid parameter passed to max_num_kflows devarg.\n");
4899                 return -EINVAL;
4900         }
4901
4902         max_num_kflows = strtoul(value, &end, 10);
4903         if (end == NULL || *end != '\0' ||
4904                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4905                 PMD_DRV_LOG(ERR,
4906                         "Invalid parameter passed to max_num_kflows devarg.\n");
4907                 return -EINVAL;
4908         }
4909
4910         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4911                 PMD_DRV_LOG(ERR,
4912                         "Invalid value passed to max_num_kflows devarg.\n");
4913                 return -EINVAL;
4914         }
4915
4916         bp->max_num_kflows = max_num_kflows;
4917         if (bp->max_num_kflows)
4918                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
4919                                 max_num_kflows);
4920
4921         return 0;
4922 }
4923
4924 static int
4925 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
4926                             const char *value, void *opaque_arg)
4927 {
4928         struct bnxt_representor *vfr_bp = opaque_arg;
4929         unsigned long rep_is_pf;
4930         char *end = NULL;
4931
4932         if (!value || !opaque_arg) {
4933                 PMD_DRV_LOG(ERR,
4934                             "Invalid parameter passed to rep_is_pf devargs.\n");
4935                 return -EINVAL;
4936         }
4937
4938         rep_is_pf = strtoul(value, &end, 10);
4939         if (end == NULL || *end != '\0' ||
4940             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
4941                 PMD_DRV_LOG(ERR,
4942                             "Invalid parameter passed to rep_is_pf devargs.\n");
4943                 return -EINVAL;
4944         }
4945
4946         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
4947                 PMD_DRV_LOG(ERR,
4948                             "Invalid value passed to rep_is_pf devargs.\n");
4949                 return -EINVAL;
4950         }
4951
4952         vfr_bp->flags |= rep_is_pf;
4953         if (BNXT_REP_PF(vfr_bp))
4954                 PMD_DRV_LOG(INFO, "PF representor\n");
4955         else
4956                 PMD_DRV_LOG(INFO, "VF representor\n");
4957
4958         return 0;
4959 }
4960
4961 static int
4962 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
4963                                const char *value, void *opaque_arg)
4964 {
4965         struct bnxt_representor *vfr_bp = opaque_arg;
4966         unsigned long rep_based_pf;
4967         char *end = NULL;
4968
4969         if (!value || !opaque_arg) {
4970                 PMD_DRV_LOG(ERR,
4971                             "Invalid parameter passed to rep_based_pf "
4972                             "devargs.\n");
4973                 return -EINVAL;
4974         }
4975
4976         rep_based_pf = strtoul(value, &end, 10);
4977         if (end == NULL || *end != '\0' ||
4978             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
4979                 PMD_DRV_LOG(ERR,
4980                             "Invalid parameter passed to rep_based_pf "
4981                             "devargs.\n");
4982                 return -EINVAL;
4983         }
4984
4985         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
4986                 PMD_DRV_LOG(ERR,
4987                             "Invalid value passed to rep_based_pf devargs.\n");
4988                 return -EINVAL;
4989         }
4990
4991         vfr_bp->rep_based_pf = rep_based_pf;
4992         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
4993
4994         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
4995
4996         return 0;
4997 }
4998
4999 static int
5000 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5001                             const char *value, void *opaque_arg)
5002 {
5003         struct bnxt_representor *vfr_bp = opaque_arg;
5004         unsigned long rep_q_r2f;
5005         char *end = NULL;
5006
5007         if (!value || !opaque_arg) {
5008                 PMD_DRV_LOG(ERR,
5009                             "Invalid parameter passed to rep_q_r2f "
5010                             "devargs.\n");
5011                 return -EINVAL;
5012         }
5013
5014         rep_q_r2f = strtoul(value, &end, 10);
5015         if (end == NULL || *end != '\0' ||
5016             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5017                 PMD_DRV_LOG(ERR,
5018                             "Invalid parameter passed to rep_q_r2f "
5019                             "devargs.\n");
5020                 return -EINVAL;
5021         }
5022
5023         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5024                 PMD_DRV_LOG(ERR,
5025                             "Invalid value passed to rep_q_r2f devargs.\n");
5026                 return -EINVAL;
5027         }
5028
5029         vfr_bp->rep_q_r2f = rep_q_r2f;
5030         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5031         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5032
5033         return 0;
5034 }
5035
5036 static int
5037 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5038                             const char *value, void *opaque_arg)
5039 {
5040         struct bnxt_representor *vfr_bp = opaque_arg;
5041         unsigned long rep_q_f2r;
5042         char *end = NULL;
5043
5044         if (!value || !opaque_arg) {
5045                 PMD_DRV_LOG(ERR,
5046                             "Invalid parameter passed to rep_q_f2r "
5047                             "devargs.\n");
5048                 return -EINVAL;
5049         }
5050
5051         rep_q_f2r = strtoul(value, &end, 10);
5052         if (end == NULL || *end != '\0' ||
5053             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5054                 PMD_DRV_LOG(ERR,
5055                             "Invalid parameter passed to rep_q_f2r "
5056                             "devargs.\n");
5057                 return -EINVAL;
5058         }
5059
5060         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5061                 PMD_DRV_LOG(ERR,
5062                             "Invalid value passed to rep_q_f2r devargs.\n");
5063                 return -EINVAL;
5064         }
5065
5066         vfr_bp->rep_q_f2r = rep_q_f2r;
5067         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5068         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5069
5070         return 0;
5071 }
5072
5073 static int
5074 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5075                              const char *value, void *opaque_arg)
5076 {
5077         struct bnxt_representor *vfr_bp = opaque_arg;
5078         unsigned long rep_fc_r2f;
5079         char *end = NULL;
5080
5081         if (!value || !opaque_arg) {
5082                 PMD_DRV_LOG(ERR,
5083                             "Invalid parameter passed to rep_fc_r2f "
5084                             "devargs.\n");
5085                 return -EINVAL;
5086         }
5087
5088         rep_fc_r2f = strtoul(value, &end, 10);
5089         if (end == NULL || *end != '\0' ||
5090             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5091                 PMD_DRV_LOG(ERR,
5092                             "Invalid parameter passed to rep_fc_r2f "
5093                             "devargs.\n");
5094                 return -EINVAL;
5095         }
5096
5097         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5098                 PMD_DRV_LOG(ERR,
5099                             "Invalid value passed to rep_fc_r2f devargs.\n");
5100                 return -EINVAL;
5101         }
5102
5103         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5104         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5105         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5106
5107         return 0;
5108 }
5109
5110 static int
5111 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5112                              const char *value, void *opaque_arg)
5113 {
5114         struct bnxt_representor *vfr_bp = opaque_arg;
5115         unsigned long rep_fc_f2r;
5116         char *end = NULL;
5117
5118         if (!value || !opaque_arg) {
5119                 PMD_DRV_LOG(ERR,
5120                             "Invalid parameter passed to rep_fc_f2r "
5121                             "devargs.\n");
5122                 return -EINVAL;
5123         }
5124
5125         rep_fc_f2r = strtoul(value, &end, 10);
5126         if (end == NULL || *end != '\0' ||
5127             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5128                 PMD_DRV_LOG(ERR,
5129                             "Invalid parameter passed to rep_fc_f2r "
5130                             "devargs.\n");
5131                 return -EINVAL;
5132         }
5133
5134         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5135                 PMD_DRV_LOG(ERR,
5136                             "Invalid value passed to rep_fc_f2r devargs.\n");
5137                 return -EINVAL;
5138         }
5139
5140         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5141         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5142         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5143
5144         return 0;
5145 }
5146
5147 static void
5148 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5149 {
5150         struct rte_kvargs *kvlist;
5151
5152         if (devargs == NULL)
5153                 return;
5154
5155         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5156         if (kvlist == NULL)
5157                 return;
5158
5159         /*
5160          * Handler for "truflow" devarg.
5161          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5162          */
5163         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5164                            bnxt_parse_devarg_truflow, bp);
5165
5166         /*
5167          * Handler for "flow_xstat" devarg.
5168          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5169          */
5170         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5171                            bnxt_parse_devarg_flow_xstat, bp);
5172
5173         /*
5174          * Handler for "max_num_kflows" devarg.
5175          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5176          */
5177         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5178                            bnxt_parse_devarg_max_num_kflows, bp);
5179
5180         rte_kvargs_free(kvlist);
5181 }
5182
5183 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5184 {
5185         int rc = 0;
5186
5187         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5188                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5189                 if (rc)
5190                         PMD_DRV_LOG(ERR,
5191                                     "Failed to alloc switch domain: %d\n", rc);
5192                 else
5193                         PMD_DRV_LOG(INFO,
5194                                     "Switch domain allocated %d\n",
5195                                     bp->switch_domain_id);
5196         }
5197
5198         return rc;
5199 }
5200
5201 static int
5202 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5203 {
5204         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5205         static int version_printed;
5206         struct bnxt *bp;
5207         int rc;
5208
5209         if (version_printed++ == 0)
5210                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5211
5212         eth_dev->dev_ops = &bnxt_dev_ops;
5213         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5214         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5215         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5216         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5217         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5218
5219         /*
5220          * For secondary processes, we don't initialise any further
5221          * as primary has already done this work.
5222          */
5223         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5224                 return 0;
5225
5226         rte_eth_copy_pci_info(eth_dev, pci_dev);
5227         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5228
5229         bp = eth_dev->data->dev_private;
5230
5231         /* Parse dev arguments passed on when starting the DPDK application. */
5232         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5233
5234         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5235
5236         if (bnxt_vf_pciid(pci_dev->id.device_id))
5237                 bp->flags |= BNXT_FLAG_VF;
5238
5239         if (bnxt_p5_device(pci_dev->id.device_id))
5240                 bp->flags |= BNXT_FLAG_CHIP_P5;
5241
5242         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5243             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5244             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5245             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5246                 bp->flags |= BNXT_FLAG_STINGRAY;
5247
5248         if (BNXT_TRUFLOW_EN(bp)) {
5249                 /* extra mbuf field is required to store CFA code from mark */
5250                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5251                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5252                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5253                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5254                 };
5255                 bnxt_cfa_code_dynfield_offset =
5256                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5257                 if (bnxt_cfa_code_dynfield_offset < 0) {
5258                         PMD_DRV_LOG(ERR,
5259                             "Failed to register mbuf field for TruFlow mark\n");
5260                         return -rte_errno;
5261                 }
5262         }
5263
5264         rc = bnxt_init_board(eth_dev);
5265         if (rc) {
5266                 PMD_DRV_LOG(ERR,
5267                             "Failed to initialize board rc: %x\n", rc);
5268                 return rc;
5269         }
5270
5271         rc = bnxt_alloc_pf_info(bp);
5272         if (rc)
5273                 goto error_free;
5274
5275         rc = bnxt_alloc_link_info(bp);
5276         if (rc)
5277                 goto error_free;
5278
5279         rc = bnxt_alloc_parent_info(bp);
5280         if (rc)
5281                 goto error_free;
5282
5283         rc = bnxt_alloc_hwrm_resources(bp);
5284         if (rc) {
5285                 PMD_DRV_LOG(ERR,
5286                             "Failed to allocate hwrm resource rc: %x\n", rc);
5287                 goto error_free;
5288         }
5289         rc = bnxt_alloc_leds_info(bp);
5290         if (rc)
5291                 goto error_free;
5292
5293         rc = bnxt_alloc_cos_queues(bp);
5294         if (rc)
5295                 goto error_free;
5296
5297         rc = bnxt_init_resources(bp, false);
5298         if (rc)
5299                 goto error_free;
5300
5301         rc = bnxt_alloc_stats_mem(bp);
5302         if (rc)
5303                 goto error_free;
5304
5305         bnxt_alloc_switch_domain(bp);
5306
5307         PMD_DRV_LOG(INFO,
5308                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5309                     pci_dev->mem_resource[0].phys_addr,
5310                     pci_dev->mem_resource[0].addr);
5311
5312         return 0;
5313
5314 error_free:
5315         bnxt_dev_uninit(eth_dev);
5316         return rc;
5317 }
5318
5319
5320 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5321 {
5322         if (!ctx)
5323                 return;
5324
5325         if (ctx->va)
5326                 rte_free(ctx->va);
5327
5328         ctx->va = NULL;
5329         ctx->dma = RTE_BAD_IOVA;
5330         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5331 }
5332
5333 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5334 {
5335         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5336                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5337                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5338                                   bp->flow_stat->max_fc,
5339                                   false);
5340
5341         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5342                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5343                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5344                                   bp->flow_stat->max_fc,
5345                                   false);
5346
5347         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5348                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5349         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5350
5351         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5352                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5353         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5354
5355         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5356                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5357         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5358
5359         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5360                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5361         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5362 }
5363
5364 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5365 {
5366         bnxt_unregister_fc_ctx_mem(bp);
5367
5368         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5369         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5370         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5371         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5372 }
5373
5374 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5375 {
5376         if (BNXT_FLOW_XSTATS_EN(bp))
5377                 bnxt_uninit_fc_ctx_mem(bp);
5378 }
5379
5380 static void
5381 bnxt_free_error_recovery_info(struct bnxt *bp)
5382 {
5383         rte_free(bp->recovery_info);
5384         bp->recovery_info = NULL;
5385         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5386 }
5387
5388 static void
5389 bnxt_uninit_locks(struct bnxt *bp)
5390 {
5391         pthread_mutex_destroy(&bp->flow_lock);
5392         pthread_mutex_destroy(&bp->def_cp_lock);
5393         pthread_mutex_destroy(&bp->health_check_lock);
5394         if (bp->rep_info) {
5395                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5396                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5397         }
5398 }
5399
5400 static int
5401 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5402 {
5403         int rc;
5404
5405         bnxt_free_int(bp);
5406         bnxt_free_mem(bp, reconfig_dev);
5407
5408         bnxt_hwrm_func_buf_unrgtr(bp);
5409         rte_free(bp->pf->vf_req_buf);
5410
5411         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5412         bp->flags &= ~BNXT_FLAG_REGISTERED;
5413         bnxt_free_ctx_mem(bp);
5414         if (!reconfig_dev) {
5415                 bnxt_free_hwrm_resources(bp);
5416                 bnxt_free_error_recovery_info(bp);
5417         }
5418
5419         bnxt_uninit_ctx_mem(bp);
5420
5421         bnxt_uninit_locks(bp);
5422         bnxt_free_flow_stats_info(bp);
5423         bnxt_free_rep_info(bp);
5424         rte_free(bp->ptp_cfg);
5425         bp->ptp_cfg = NULL;
5426         return rc;
5427 }
5428
5429 static int
5430 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5431 {
5432         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5433                 return -EPERM;
5434
5435         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5436
5437         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5438                 bnxt_dev_close_op(eth_dev);
5439
5440         return 0;
5441 }
5442
5443 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5444 {
5445         struct bnxt *bp = eth_dev->data->dev_private;
5446         struct rte_eth_dev *vf_rep_eth_dev;
5447         int ret = 0, i;
5448
5449         if (!bp)
5450                 return -EINVAL;
5451
5452         for (i = 0; i < bp->num_reps; i++) {
5453                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5454                 if (!vf_rep_eth_dev)
5455                         continue;
5456                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5457                             vf_rep_eth_dev->data->port_id);
5458                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5459         }
5460         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5461                     eth_dev->data->port_id);
5462         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5463
5464         return ret;
5465 }
5466
5467 static void bnxt_free_rep_info(struct bnxt *bp)
5468 {
5469         rte_free(bp->rep_info);
5470         bp->rep_info = NULL;
5471         rte_free(bp->cfa_code_map);
5472         bp->cfa_code_map = NULL;
5473 }
5474
5475 static int bnxt_init_rep_info(struct bnxt *bp)
5476 {
5477         int i = 0, rc;
5478
5479         if (bp->rep_info)
5480                 return 0;
5481
5482         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5483                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5484                                    0);
5485         if (!bp->rep_info) {
5486                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5487                 return -ENOMEM;
5488         }
5489         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5490                                        sizeof(*bp->cfa_code_map) *
5491                                        BNXT_MAX_CFA_CODE, 0);
5492         if (!bp->cfa_code_map) {
5493                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5494                 bnxt_free_rep_info(bp);
5495                 return -ENOMEM;
5496         }
5497
5498         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5499                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5500
5501         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5502         if (rc) {
5503                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5504                 bnxt_free_rep_info(bp);
5505                 return rc;
5506         }
5507
5508         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5509         if (rc) {
5510                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5511                 bnxt_free_rep_info(bp);
5512                 return rc;
5513         }
5514
5515         return rc;
5516 }
5517
5518 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5519                                struct rte_eth_devargs *eth_da,
5520                                struct rte_eth_dev *backing_eth_dev,
5521                                const char *dev_args)
5522 {
5523         struct rte_eth_dev *vf_rep_eth_dev;
5524         char name[RTE_ETH_NAME_MAX_LEN];
5525         struct bnxt *backing_bp;
5526         uint16_t num_rep;
5527         int i, ret = 0;
5528         struct rte_kvargs *kvlist = NULL;
5529
5530         num_rep = eth_da->nb_representor_ports;
5531         if (num_rep > BNXT_MAX_VF_REPS) {
5532                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5533                             num_rep, BNXT_MAX_VF_REPS);
5534                 return -EINVAL;
5535         }
5536
5537         if (num_rep >= RTE_MAX_ETHPORTS) {
5538                 PMD_DRV_LOG(ERR,
5539                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5540                             num_rep, RTE_MAX_ETHPORTS);
5541                 return -EINVAL;
5542         }
5543
5544         backing_bp = backing_eth_dev->data->dev_private;
5545
5546         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5547                 PMD_DRV_LOG(ERR,
5548                             "Not a PF or trusted VF. No Representor support\n");
5549                 /* Returning an error is not an option.
5550                  * Applications are not handling this correctly
5551                  */
5552                 return 0;
5553         }
5554
5555         if (bnxt_init_rep_info(backing_bp))
5556                 return 0;
5557
5558         for (i = 0; i < num_rep; i++) {
5559                 struct bnxt_representor representor = {
5560                         .vf_id = eth_da->representor_ports[i],
5561                         .switch_domain_id = backing_bp->switch_domain_id,
5562                         .parent_dev = backing_eth_dev
5563                 };
5564
5565                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5566                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5567                                     representor.vf_id, BNXT_MAX_VF_REPS);
5568                         continue;
5569                 }
5570
5571                 /* representor port net_bdf_port */
5572                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5573                          pci_dev->device.name, eth_da->representor_ports[i]);
5574
5575                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5576                 if (kvlist) {
5577                         /*
5578                          * Handler for "rep_is_pf" devarg.
5579                          * Invoked as for ex: "-a 000:00:0d.0,
5580                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5581                          */
5582                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5583                                                  bnxt_parse_devarg_rep_is_pf,
5584                                                  (void *)&representor);
5585                         if (ret) {
5586                                 ret = -EINVAL;
5587                                 goto err;
5588                         }
5589                         /*
5590                          * Handler for "rep_based_pf" devarg.
5591                          * Invoked as for ex: "-a 000:00:0d.0,
5592                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5593                          */
5594                         ret = rte_kvargs_process(kvlist,
5595                                                  BNXT_DEVARG_REP_BASED_PF,
5596                                                  bnxt_parse_devarg_rep_based_pf,
5597                                                  (void *)&representor);
5598                         if (ret) {
5599                                 ret = -EINVAL;
5600                                 goto err;
5601                         }
5602                         /*
5603                          * Handler for "rep_based_pf" devarg.
5604                          * Invoked as for ex: "-a 000:00:0d.0,
5605                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5606                          */
5607                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5608                                                  bnxt_parse_devarg_rep_q_r2f,
5609                                                  (void *)&representor);
5610                         if (ret) {
5611                                 ret = -EINVAL;
5612                                 goto err;
5613                         }
5614                         /*
5615                          * Handler for "rep_based_pf" devarg.
5616                          * Invoked as for ex: "-a 000:00:0d.0,
5617                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5618                          */
5619                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5620                                                  bnxt_parse_devarg_rep_q_f2r,
5621                                                  (void *)&representor);
5622                         if (ret) {
5623                                 ret = -EINVAL;
5624                                 goto err;
5625                         }
5626                         /*
5627                          * Handler for "rep_based_pf" devarg.
5628                          * Invoked as for ex: "-a 000:00:0d.0,
5629                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5630                          */
5631                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5632                                                  bnxt_parse_devarg_rep_fc_r2f,
5633                                                  (void *)&representor);
5634                         if (ret) {
5635                                 ret = -EINVAL;
5636                                 goto err;
5637                         }
5638                         /*
5639                          * Handler for "rep_based_pf" devarg.
5640                          * Invoked as for ex: "-a 000:00:0d.0,
5641                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5642                          */
5643                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5644                                                  bnxt_parse_devarg_rep_fc_f2r,
5645                                                  (void *)&representor);
5646                         if (ret) {
5647                                 ret = -EINVAL;
5648                                 goto err;
5649                         }
5650                 }
5651
5652                 ret = rte_eth_dev_create(&pci_dev->device, name,
5653                                          sizeof(struct bnxt_representor),
5654                                          NULL, NULL,
5655                                          bnxt_representor_init,
5656                                          &representor);
5657                 if (ret) {
5658                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5659                                     "representor %s.", name);
5660                         goto err;
5661                 }
5662
5663                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5664                 if (!vf_rep_eth_dev) {
5665                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5666                                     " for VF-Rep: %s.", name);
5667                         ret = -ENODEV;
5668                         goto err;
5669                 }
5670
5671                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5672                             backing_eth_dev->data->port_id);
5673                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5674                                                          vf_rep_eth_dev;
5675                 backing_bp->num_reps++;
5676
5677         }
5678
5679         rte_kvargs_free(kvlist);
5680         return 0;
5681
5682 err:
5683         /* If num_rep > 1, then rollback already created
5684          * ports, since we'll be failing the probe anyway
5685          */
5686         if (num_rep > 1)
5687                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5688         rte_errno = -ret;
5689         rte_kvargs_free(kvlist);
5690
5691         return ret;
5692 }
5693
5694 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5695                           struct rte_pci_device *pci_dev)
5696 {
5697         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5698         struct rte_eth_dev *backing_eth_dev;
5699         uint16_t num_rep;
5700         int ret = 0;
5701
5702         if (pci_dev->device.devargs) {
5703                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5704                                             &eth_da);
5705                 if (ret)
5706                         return ret;
5707         }
5708
5709         num_rep = eth_da.nb_representor_ports;
5710         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5711                     num_rep);
5712
5713         /* We could come here after first level of probe is already invoked
5714          * as part of an application bringup(OVS-DPDK vswitchd), so first check
5715          * for already allocated eth_dev for the backing device (PF/Trusted VF)
5716          */
5717         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5718         if (backing_eth_dev == NULL) {
5719                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5720                                          sizeof(struct bnxt),
5721                                          eth_dev_pci_specific_init, pci_dev,
5722                                          bnxt_dev_init, NULL);
5723
5724                 if (ret || !num_rep)
5725                         return ret;
5726
5727                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5728         }
5729         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5730                     backing_eth_dev->data->port_id);
5731
5732         if (!num_rep)
5733                 return ret;
5734
5735         /* probe representor ports now */
5736         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
5737                                   pci_dev->device.devargs->args);
5738
5739         return ret;
5740 }
5741
5742 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5743 {
5744         struct rte_eth_dev *eth_dev;
5745
5746         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5747         if (!eth_dev)
5748                 return 0; /* Invoked typically only by OVS-DPDK, by the
5749                            * time it comes here the eth_dev is already
5750                            * deleted by rte_eth_dev_close(), so returning
5751                            * +ve value will at least help in proper cleanup
5752                            */
5753
5754         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5755         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5756                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5757                         return rte_eth_dev_destroy(eth_dev,
5758                                                    bnxt_representor_uninit);
5759                 else
5760                         return rte_eth_dev_destroy(eth_dev,
5761                                                    bnxt_dev_uninit);
5762         } else {
5763                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5764         }
5765 }
5766
5767 static struct rte_pci_driver bnxt_rte_pmd = {
5768         .id_table = bnxt_pci_id_map,
5769         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5770                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5771                                                   * and OVS-DPDK
5772                                                   */
5773         .probe = bnxt_pci_probe,
5774         .remove = bnxt_pci_remove,
5775 };
5776
5777 static bool
5778 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5779 {
5780         if (strcmp(dev->device->driver->name, drv->driver.name))
5781                 return false;
5782
5783         return true;
5784 }
5785
5786 bool is_bnxt_supported(struct rte_eth_dev *dev)
5787 {
5788         return is_device_supported(dev, &bnxt_rte_pmd);
5789 }
5790
5791 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5792 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5793 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5794 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");