drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_TRUFLOW,
 104         BNXT_DEVARG_FLOW_XSTAT,
 105         BNXT_DEVARG_MAX_NUM_KFLOWS,
 106         BNXT_DEVARG_REP_BASED_PF,
 107         BNXT_DEVARG_REP_IS_PF,
 108         BNXT_DEVARG_REP_Q_R2F,
 109         BNXT_DEVARG_REP_Q_F2R,
 110         BNXT_DEVARG_REP_FC_R2F,
 111         BNXT_DEVARG_REP_FC_F2R,
 112         NULL
 113 };
 114
 115 /*
 116  * truflow == false to disable the feature
 117  * truflow == true to enable the feature
 118  */
 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 120
 121 /*
 122  * flow_xstat == false to disable the feature
 123  * flow_xstat == true to enable the feature
 124  */
 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 126
 127 /*
 128  * rep_is_pf == false to indicate VF representor
 129  * rep_is_pf == true to indicate PF representor
 130  */
 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 132
 133 /*
 134  * rep_based_pf == Physical index of the PF
 135  */
 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 137 /*
 138  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 139  */
 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 141
 142 /*
 143  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 144  */
 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 146
 147 /*
 148  * rep_fc_r2f == Flow control for the representor to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 151
 152 /*
 153  * rep_fc_f2r == Flow control for the endpoint to representor direction
 154  */
 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 156
 157 int bnxt_cfa_code_dynfield_offset = -1;
 158
 159 /*
 160  * max_num_kflows must be >= 32
 161  * and must be a power-of-2 supported value
 162  * return: 1 -> invalid
 163  *         0 -> valid
 164  */
 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 166 {
 167         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 168                 return 1;
 169         return 0;
 170 }
 171
 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 178 static void bnxt_dev_recover(void *arg);
 179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 180 static void bnxt_free_rep_info(struct bnxt *bp);
 181
 182 int is_bnxt_in_error(struct bnxt *bp)
 183 {
 184         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 185                 return -EIO;
 186         if (bp->flags & BNXT_FLAG_FW_RESET)
 187                 return -EBUSY;
 188
 189         return 0;
 190 }
 191
 192 /***********************/
 193
 194 /*
 195  * High level utility functions
 196  */
 197
 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 199 {
 200         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 201                                              BNXT_RSS_TBL_SIZE_P5);
 202
 203         if (!BNXT_CHIP_P5(bp))
 204                 return 1;
 205
 206         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 208                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 212 {
 213         if (!BNXT_CHIP_P5(bp))
 214                 return HW_HASH_INDEX_SIZE;
 215
 216         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 217 }
 218
 219 static void bnxt_free_parent_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->parent);
 222         bp->parent = NULL;
 223 }
 224
 225 static void bnxt_free_pf_info(struct bnxt *bp)
 226 {
 227         rte_free(bp->pf);
 228         bp->pf = NULL;
 229 }
 230
 231 static void bnxt_free_link_info(struct bnxt *bp)
 232 {
 233         rte_free(bp->link_info);
 234         bp->link_info = NULL;
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         bp->rx_cos_queue = NULL;
 256         rte_free(bp->tx_cos_queue);
 257         bp->tx_cos_queue = NULL;
 258 }
 259
 260 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 261 {
 262         bnxt_free_filter_mem(bp);
 263         bnxt_free_vnic_attributes(bp);
 264         bnxt_free_vnic_mem(bp);
 265
 266         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 267          * If the number of rings change across fw update,
 268          * we don't have much choice except to warn the user.
 269          */
 270         if (!reconfig) {
 271                 bnxt_free_stats(bp);
 272                 bnxt_free_tx_rings(bp);
 273                 bnxt_free_rx_rings(bp);
 274         }
 275         bnxt_free_async_cp_ring(bp);
 276         bnxt_free_rxtx_nq_ring(bp);
 277
 278         rte_free(bp->grp_info);
 279         bp->grp_info = NULL;
 280 }
 281
 282 static int bnxt_alloc_parent_info(struct bnxt *bp)
 283 {
 284         bp->parent = rte_zmalloc("bnxt_parent_info",
 285                                  sizeof(struct bnxt_parent_info), 0);
 286         if (bp->parent == NULL)
 287                 return -ENOMEM;
 288
 289         return 0;
 290 }
 291
 292 static int bnxt_alloc_pf_info(struct bnxt *bp)
 293 {
 294         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 295         if (bp->pf == NULL)
 296                 return -ENOMEM;
 297
 298         return 0;
 299 }
 300
 301 static int bnxt_alloc_link_info(struct bnxt *bp)
 302 {
 303         bp->link_info =
 304                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 305         if (bp->link_info == NULL)
 306                 return -ENOMEM;
 307
 308         return 0;
 309 }
 310
 311 static int bnxt_alloc_leds_info(struct bnxt *bp)
 312 {
 313         if (BNXT_VF(bp))
 314                 return 0;
 315
 316         bp->leds = rte_zmalloc("bnxt_leds",
 317                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 318                                0);
 319         if (bp->leds == NULL)
 320                 return -ENOMEM;
 321
 322         return 0;
 323 }
 324
 325 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 326 {
 327         bp->rx_cos_queue =
 328                 rte_zmalloc("bnxt_rx_cosq",
 329                             BNXT_COS_QUEUE_COUNT *
 330                             sizeof(struct bnxt_cos_queue_info),
 331                             0);
 332         if (bp->rx_cos_queue == NULL)
 333                 return -ENOMEM;
 334
 335         bp->tx_cos_queue =
 336                 rte_zmalloc("bnxt_tx_cosq",
 337                             BNXT_COS_QUEUE_COUNT *
 338                             sizeof(struct bnxt_cos_queue_info),
 339                             0);
 340         if (bp->tx_cos_queue == NULL)
 341                 return -ENOMEM;
 342
 343         return 0;
 344 }
 345
 346 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 347 {
 348         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 349                                     sizeof(struct bnxt_flow_stat_info), 0);
 350         if (bp->flow_stat == NULL)
 351                 return -ENOMEM;
 352
 353         return 0;
 354 }
 355
 356 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 357 {
 358         int rc;
 359
 360         rc = bnxt_alloc_ring_grps(bp);
 361         if (rc)
 362                 goto alloc_mem_err;
 363
 364         rc = bnxt_alloc_async_ring_struct(bp);
 365         if (rc)
 366                 goto alloc_mem_err;
 367
 368         rc = bnxt_alloc_vnic_mem(bp);
 369         if (rc)
 370                 goto alloc_mem_err;
 371
 372         rc = bnxt_alloc_vnic_attributes(bp);
 373         if (rc)
 374                 goto alloc_mem_err;
 375
 376         rc = bnxt_alloc_filter_mem(bp);
 377         if (rc)
 378                 goto alloc_mem_err;
 379
 380         rc = bnxt_alloc_async_cp_ring(bp);
 381         if (rc)
 382                 goto alloc_mem_err;
 383
 384         rc = bnxt_alloc_rxtx_nq_ring(bp);
 385         if (rc)
 386                 goto alloc_mem_err;
 387
 388         if (BNXT_FLOW_XSTATS_EN(bp)) {
 389                 rc = bnxt_alloc_flow_stats_info(bp);
 390                 if (rc)
 391                         goto alloc_mem_err;
 392         }
 393
 394         return 0;
 395
 396 alloc_mem_err:
 397         bnxt_free_mem(bp, reconfig);
 398         return rc;
 399 }
 400
 401 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 402 {
 403         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 404         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 405         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 406         struct bnxt_rx_queue *rxq;
 407         unsigned int j;
 408         int rc;
 409
 410         rc = bnxt_vnic_grp_alloc(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 415                     vnic_id, vnic, vnic->fw_grp_ids);
 416
 417         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 418         if (rc)
 419                 goto err_out;
 420
 421         /* Alloc RSS context only if RSS mode is enabled */
 422         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 423                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 424
 425                 /* RSS table size in Thor is 512.
 426                  * Cap max Rx rings to same value
 427                  */
 428                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 429                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 430                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 431                         goto err_out;
 432                 }
 433
 434                 rc = 0;
 435                 for (j = 0; j < nr_ctxs; j++) {
 436                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 437                         if (rc)
 438                                 break;
 439                 }
 440                 if (rc) {
 441                         PMD_DRV_LOG(ERR,
 442                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 443                                     vnic_id, j, rc);
 444                         goto err_out;
 445                 }
 446                 vnic->num_lb_ctxts = nr_ctxs;
 447         }
 448
 449         /*
 450          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 451          * setting is not available at this time, it will not be
 452          * configured correctly in the CFA.
 453          */
 454         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 455                 vnic->vlan_strip = true;
 456         else
 457                 vnic->vlan_strip = false;
 458
 459         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 460         if (rc)
 461                 goto err_out;
 462
 463         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 464         if (rc)
 465                 goto err_out;
 466
 467         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 468                 rxq = bp->eth_dev->data->rx_queues[j];
 469
 470                 PMD_DRV_LOG(DEBUG,
 471                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 472                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 473
 474                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 475                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 476                 else
 477                         vnic->rx_queue_cnt++;
 478         }
 479
 480         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 481
 482         rc = bnxt_vnic_rss_configure(bp, vnic);
 483         if (rc)
 484                 goto err_out;
 485
 486         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 487
 488         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 489                                     (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
 490                                     true : false);
 491         if (rc)
 492                 goto err_out;
 493
 494         return 0;
 495 err_out:
 496         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 497                     vnic_id, rc);
 498         return rc;
 499 }
 500
 501 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 502 {
 503         int rc = 0;
 504
 505         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 506                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 507         if (rc)
 508                 return rc;
 509
 510         PMD_DRV_LOG(DEBUG,
 511                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 512                     " rx_fc_in_tbl.ctx_id = %d\n",
 513                     bp->flow_stat->rx_fc_in_tbl.va,
 514                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 515                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 516
 517         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 518                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 519         if (rc)
 520                 return rc;
 521
 522         PMD_DRV_LOG(DEBUG,
 523                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 524                     " rx_fc_out_tbl.ctx_id = %d\n",
 525                     bp->flow_stat->rx_fc_out_tbl.va,
 526                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 527                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 528
 529         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 530                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 531         if (rc)
 532                 return rc;
 533
 534         PMD_DRV_LOG(DEBUG,
 535                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 536                     " tx_fc_in_tbl.ctx_id = %d\n",
 537                     bp->flow_stat->tx_fc_in_tbl.va,
 538                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 539                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 540
 541         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 542                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 543         if (rc)
 544                 return rc;
 545
 546         PMD_DRV_LOG(DEBUG,
 547                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 548                     " tx_fc_out_tbl.ctx_id = %d\n",
 549                     bp->flow_stat->tx_fc_out_tbl.va,
 550                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 551                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 552
 553         memset(bp->flow_stat->rx_fc_out_tbl.va,
 554                0,
 555                bp->flow_stat->rx_fc_out_tbl.size);
 556         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 557                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 558                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 559                                        bp->flow_stat->max_fc,
 560                                        true);
 561         if (rc)
 562                 return rc;
 563
 564         memset(bp->flow_stat->tx_fc_out_tbl.va,
 565                0,
 566                bp->flow_stat->tx_fc_out_tbl.size);
 567         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 568                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 569                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 570                                        bp->flow_stat->max_fc,
 571                                        true);
 572
 573         return rc;
 574 }
 575
 576 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 577                                   struct bnxt_ctx_mem_buf_info *ctx)
 578 {
 579         if (!ctx)
 580                 return -EINVAL;
 581
 582         ctx->va = rte_zmalloc(type, size, 0);
 583         if (ctx->va == NULL)
 584                 return -ENOMEM;
 585         rte_mem_lock_page(ctx->va);
 586         ctx->size = size;
 587         ctx->dma = rte_mem_virt2iova(ctx->va);
 588         if (ctx->dma == RTE_BAD_IOVA)
 589                 return -ENOMEM;
 590
 591         return 0;
 592 }
 593
 594 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 595 {
 596         struct rte_pci_device *pdev = bp->pdev;
 597         char type[RTE_MEMZONE_NAMESIZE];
 598         uint16_t max_fc;
 599         int rc = 0;
 600
 601         max_fc = bp->flow_stat->max_fc;
 602
 603         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 604                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 605         /* 4 bytes for each counter-id */
 606         rc = bnxt_alloc_ctx_mem_buf(type,
 607                                     max_fc * 4,
 608                                     &bp->flow_stat->rx_fc_in_tbl);
 609         if (rc)
 610                 return rc;
 611
 612         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 613                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 614         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 615         rc = bnxt_alloc_ctx_mem_buf(type,
 616                                     max_fc * 16,
 617                                     &bp->flow_stat->rx_fc_out_tbl);
 618         if (rc)
 619                 return rc;
 620
 621         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 622                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 623         /* 4 bytes for each counter-id */
 624         rc = bnxt_alloc_ctx_mem_buf(type,
 625                                     max_fc * 4,
 626                                     &bp->flow_stat->tx_fc_in_tbl);
 627         if (rc)
 628                 return rc;
 629
 630         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 631                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 632         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 633         rc = bnxt_alloc_ctx_mem_buf(type,
 634                                     max_fc * 16,
 635                                     &bp->flow_stat->tx_fc_out_tbl);
 636         if (rc)
 637                 return rc;
 638
 639         rc = bnxt_register_fc_ctx_mem(bp);
 640
 641         return rc;
 642 }
 643
 644 static int bnxt_init_ctx_mem(struct bnxt *bp)
 645 {
 646         int rc = 0;
 647
 648         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 649             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 650             !BNXT_FLOW_XSTATS_EN(bp))
 651                 return 0;
 652
 653         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 654         if (rc)
 655                 return rc;
 656
 657         rc = bnxt_init_fc_ctx_mem(bp);
 658
 659         return rc;
 660 }
 661
 662 static int bnxt_update_phy_setting(struct bnxt *bp)
 663 {
 664         struct rte_eth_link new;
 665         int rc;
 666
 667         rc = bnxt_get_hwrm_link_config(bp, &new);
 668         if (rc) {
 669                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 670                 return rc;
 671         }
 672
 673         /*
 674          * On BCM957508-N2100 adapters, FW will not allow any user other
 675          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 676          * always returns link up. Force phy update always in that case.
 677          */
 678         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 679                 rc = bnxt_set_hwrm_link_config(bp, true);
 680                 if (rc) {
 681                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 682                         return rc;
 683                 }
 684         }
 685
 686         return rc;
 687 }
 688
 689 static int bnxt_start_nic(struct bnxt *bp)
 690 {
 691         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 692         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 693         uint32_t intr_vector = 0;
 694         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 695         uint32_t vec = BNXT_MISC_VEC_ID;
 696         unsigned int i, j;
 697         int rc;
 698
 699         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 700                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 701                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 702                 bp->flags |= BNXT_FLAG_JUMBO;
 703         } else {
 704                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 705                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 706                 bp->flags &= ~BNXT_FLAG_JUMBO;
 707         }
 708
 709         /* THOR does not support ring groups.
 710          * But we will use the array to save RSS context IDs.
 711          */
 712         if (BNXT_CHIP_P5(bp))
 713                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 714
 715         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 716         if (rc) {
 717                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 718                 goto err_out;
 719         }
 720
 721         rc = bnxt_alloc_hwrm_rings(bp);
 722         if (rc) {
 723                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 724                 goto err_out;
 725         }
 726
 727         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 728         if (rc) {
 729                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 730                 goto err_out;
 731         }
 732
 733         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 734                 goto skip_cosq_cfg;
 735
 736         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 737                 if (bp->rx_cos_queue[i].id != 0xff) {
 738                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 739
 740                         if (!vnic) {
 741                                 PMD_DRV_LOG(ERR,
 742                                             "Num pools more than FW profile\n");
 743                                 rc = -EINVAL;
 744                                 goto err_out;
 745                         }
 746                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 747                         bp->rx_cosq_cnt++;
 748                 }
 749         }
 750
 751 skip_cosq_cfg:
 752         rc = bnxt_mq_rx_configure(bp);
 753         if (rc) {
 754                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 755                 goto err_out;
 756         }
 757
 758         /* default vnic 0 */
 759         rc = bnxt_setup_one_vnic(bp, 0);
 760         if (rc)
 761                 goto err_out;
 762         /* VNIC configuration */
 763         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 764                 for (i = 1; i < bp->nr_vnics; i++) {
 765                         rc = bnxt_setup_one_vnic(bp, i);
 766                         if (rc)
 767                                 goto err_out;
 768                 }
 769         }
 770
 771         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 772         if (rc) {
 773                 PMD_DRV_LOG(ERR,
 774                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 775                 goto err_out;
 776         }
 777
 778         /* check and configure queue intr-vector mapping */
 779         if ((rte_intr_cap_multiple(intr_handle) ||
 780              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 781             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 782                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 783                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 784                 if (intr_vector > bp->rx_cp_nr_rings) {
 785                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 786                                         bp->rx_cp_nr_rings);
 787                         return -ENOTSUP;
 788                 }
 789                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 790                 if (rc)
 791                         return rc;
 792         }
 793
 794         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 795                 intr_handle->intr_vec =
 796                         rte_zmalloc("intr_vec",
 797                                     bp->eth_dev->data->nb_rx_queues *
 798                                     sizeof(int), 0);
 799                 if (intr_handle->intr_vec == NULL) {
 800                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 801                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 802                         rc = -ENOMEM;
 803                         goto err_out;
 804                 }
 805                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 806                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 807                          intr_handle->intr_vec, intr_handle->nb_efd,
 808                         intr_handle->max_intr);
 809                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 810                      queue_id++) {
 811                         intr_handle->intr_vec[queue_id] =
 812                                                         vec + BNXT_RX_VEC_START;
 813                         if (vec < base + intr_handle->nb_efd - 1)
 814                                 vec++;
 815                 }
 816         }
 817
 818         /* enable uio/vfio intr/eventfd mapping */
 819         rc = rte_intr_enable(intr_handle);
 820 #ifndef RTE_EXEC_ENV_FREEBSD
 821         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 822         if (rc)
 823                 goto err_out;
 824 #endif
 825
 826         rc = bnxt_update_phy_setting(bp);
 827         if (rc)
 828                 goto err_out;
 829
 830         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 831         if (!bp->mark_table)
 832                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 833
 834         return 0;
 835
 836 err_out:
 837         /* Some of the error status returned by FW may not be from errno.h */
 838         if (rc > 0)
 839                 rc = -EIO;
 840
 841         return rc;
 842 }
 843
 844 static int bnxt_shutdown_nic(struct bnxt *bp)
 845 {
 846         bnxt_free_all_hwrm_resources(bp);
 847         bnxt_free_all_filters(bp);
 848         bnxt_free_all_vnics(bp);
 849         return 0;
 850 }
 851
 852 /*
 853  * Device configuration and status function
 854  */
 855
 856 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 857 {
 858         uint32_t link_speed = 0;
 859         uint32_t speed_capa = 0;
 860
 861         if (bp->link_info == NULL)
 862                 return 0;
 863
 864         link_speed = bp->link_info->support_speeds;
 865
 866         /* If PAM4 is configured, use PAM4 supported speed */
 867         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 868                 link_speed = bp->link_info->support_pam4_speeds;
 869
 870         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 871                 speed_capa |= ETH_LINK_SPEED_100M;
 872         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 873                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 874         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 875                 speed_capa |= ETH_LINK_SPEED_1G;
 876         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 877                 speed_capa |= ETH_LINK_SPEED_2_5G;
 878         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 879                 speed_capa |= ETH_LINK_SPEED_10G;
 880         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 881                 speed_capa |= ETH_LINK_SPEED_20G;
 882         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 883                 speed_capa |= ETH_LINK_SPEED_25G;
 884         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 885                 speed_capa |= ETH_LINK_SPEED_40G;
 886         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 887                 speed_capa |= ETH_LINK_SPEED_50G;
 888         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 889                 speed_capa |= ETH_LINK_SPEED_100G;
 890         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 891                 speed_capa |= ETH_LINK_SPEED_50G;
 892         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 893                 speed_capa |= ETH_LINK_SPEED_100G;
 894         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 895                 speed_capa |= ETH_LINK_SPEED_200G;
 896
 897         if (bp->link_info->auto_mode ==
 898             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 899                 speed_capa |= ETH_LINK_SPEED_FIXED;
 900
 901         return speed_capa;
 902 }
 903
 904 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 905                                 struct rte_eth_dev_info *dev_info)
 906 {
 907         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 908         struct bnxt *bp = eth_dev->data->dev_private;
 909         uint16_t max_vnics, i, j, vpool, vrxq;
 910         unsigned int max_rx_rings;
 911         int rc;
 912
 913         rc = is_bnxt_in_error(bp);
 914         if (rc)
 915                 return rc;
 916
 917         /* MAC Specifics */
 918         dev_info->max_mac_addrs = bp->max_l2_ctx;
 919         dev_info->max_hash_mac_addrs = 0;
 920
 921         /* PF/VF specifics */
 922         if (BNXT_PF(bp))
 923                 dev_info->max_vfs = pdev->max_vfs;
 924
 925         max_rx_rings = bnxt_max_rings(bp);
 926         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 927         dev_info->max_rx_queues = max_rx_rings;
 928         dev_info->max_tx_queues = max_rx_rings;
 929         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 930         dev_info->hash_key_size = 40;
 931         max_vnics = bp->max_vnics;
 932
 933         /* MTU specifics */
 934         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 935         dev_info->max_mtu = BNXT_MAX_MTU;
 936
 937         /* Fast path specifics */
 938         dev_info->min_rx_bufsize = 1;
 939         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 940
 941         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 942         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 943                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 944         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 945         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 946                                     dev_info->tx_queue_offload_capa;
 947         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 948
 949         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 950
 951         /* *INDENT-OFF* */
 952         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 953                 .rx_thresh = {
 954                         .pthresh = 8,
 955                         .hthresh = 8,
 956                         .wthresh = 0,
 957                 },
 958                 .rx_free_thresh = 32,
 959                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 960         };
 961
 962         dev_info->default_txconf = (struct rte_eth_txconf) {
 963                 .tx_thresh = {
 964                         .pthresh = 32,
 965                         .hthresh = 0,
 966                         .wthresh = 0,
 967                 },
 968                 .tx_free_thresh = 32,
 969                 .tx_rs_thresh = 32,
 970         };
 971         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 972
 973         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 974         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 975         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 976         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 977         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 978
 979         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 980                 dev_info->switch_info.name = eth_dev->device->name;
 981                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 982                 dev_info->switch_info.port_id =
 983                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 984                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 985         }
 986
 987         /* *INDENT-ON* */
 988
 989         /*
 990          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 991          *       need further investigation.
 992          */
 993
 994         /* VMDq resources */
 995         vpool = 64; /* ETH_64_POOLS */
 996         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 997         for (i = 0; i < 4; vpool >>= 1, i++) {
 998                 if (max_vnics > vpool) {
 999                         for (j = 0; j < 5; vrxq >>= 1, j++) {
1000                                 if (dev_info->max_rx_queues > vrxq) {
1001                                         if (vpool > vrxq)
1002                                                 vpool = vrxq;
1003                                         goto found;
1004                                 }
1005                         }
1006                         /* Not enough resources to support VMDq */
1007                         break;
1008                 }
1009         }
1010         /* Not enough resources to support VMDq */
1011         vpool = 0;
1012         vrxq = 0;
1013 found:
1014         dev_info->max_vmdq_pools = vpool;
1015         dev_info->vmdq_queue_num = vrxq;
1016
1017         dev_info->vmdq_pool_base = 0;
1018         dev_info->vmdq_queue_base = 0;
1019
1020         return 0;
1021 }
1022
1023 /* Configure the device based on the configuration provided */
1024 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1025 {
1026         struct bnxt *bp = eth_dev->data->dev_private;
1027         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1028         int rc;
1029
1030         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1031         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1032         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1033         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1034
1035         rc = is_bnxt_in_error(bp);
1036         if (rc)
1037                 return rc;
1038
1039         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1040                 rc = bnxt_hwrm_check_vf_rings(bp);
1041                 if (rc) {
1042                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1043                         return -ENOSPC;
1044                 }
1045
1046                 /* If a resource has already been allocated - in this case
1047                  * it is the async completion ring, free it. Reallocate it after
1048                  * resource reservation. This will ensure the resource counts
1049                  * are calculated correctly.
1050                  */
1051
1052                 pthread_mutex_lock(&bp->def_cp_lock);
1053
1054                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1055                         bnxt_disable_int(bp);
1056                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1057                 }
1058
1059                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1060                 if (rc) {
1061                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1062                         pthread_mutex_unlock(&bp->def_cp_lock);
1063                         return -ENOSPC;
1064                 }
1065
1066                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1067                         rc = bnxt_alloc_async_cp_ring(bp);
1068                         if (rc) {
1069                                 pthread_mutex_unlock(&bp->def_cp_lock);
1070                                 return rc;
1071                         }
1072                         bnxt_enable_int(bp);
1073                 }
1074
1075                 pthread_mutex_unlock(&bp->def_cp_lock);
1076         }
1077
1078         /* Inherit new configurations */
1079         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1080             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1081             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1082                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1083             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1084             bp->max_stat_ctx)
1085                 goto resource_error;
1086
1087         if (BNXT_HAS_RING_GRPS(bp) &&
1088             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1089                 goto resource_error;
1090
1091         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1092             bp->max_vnics < eth_dev->data->nb_rx_queues)
1093                 goto resource_error;
1094
1095         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1096         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1097
1098         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1099                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1100         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1101
1102         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1103                 eth_dev->data->mtu =
1104                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1105                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1106                         BNXT_NUM_VLANS;
1107                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1108         }
1109         return 0;
1110
1111 resource_error:
1112         PMD_DRV_LOG(ERR,
1113                     "Insufficient resources to support requested config\n");
1114         PMD_DRV_LOG(ERR,
1115                     "Num Queues Requested: Tx %d, Rx %d\n",
1116                     eth_dev->data->nb_tx_queues,
1117                     eth_dev->data->nb_rx_queues);
1118         PMD_DRV_LOG(ERR,
1119                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1120                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1121                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1122         return -ENOSPC;
1123 }
1124
1125 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1126 {
1127         struct rte_eth_link *link = &eth_dev->data->dev_link;
1128
1129         if (link->link_status)
1130                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1131                         eth_dev->data->port_id,
1132                         (uint32_t)link->link_speed,
1133                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1134                         ("full-duplex") : ("half-duplex\n"));
1135         else
1136                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1137                         eth_dev->data->port_id);
1138 }
1139
1140 /*
1141  * Determine whether the current configuration requires support for scattered
1142  * receive; return 1 if scattered receive is required and 0 if not.
1143  */
1144 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1145 {
1146         uint16_t buf_size;
1147         int i;
1148
1149         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1150                 return 1;
1151
1152         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1153                 return 1;
1154
1155         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1156                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1157
1158                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1159                                       RTE_PKTMBUF_HEADROOM);
1160                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1161                         return 1;
1162         }
1163         return 0;
1164 }
1165
1166 static eth_rx_burst_t
1167 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1168 {
1169         struct bnxt *bp = eth_dev->data->dev_private;
1170
1171         /* Disable vector mode RX for Stingray2 for now */
1172         if (BNXT_CHIP_SR2(bp)) {
1173                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1174                 return bnxt_recv_pkts;
1175         }
1176
1177 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1178 #ifndef RTE_LIBRTE_IEEE1588
1179         /*
1180          * Vector mode receive can be enabled only if scatter rx is not
1181          * in use and rx offloads are limited to VLAN stripping and
1182          * CRC stripping.
1183          */
1184         if (!eth_dev->data->scattered_rx &&
1185             !(eth_dev->data->dev_conf.rxmode.offloads &
1186               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1187                 DEV_RX_OFFLOAD_KEEP_CRC |
1188                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1189                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1190                 DEV_RX_OFFLOAD_UDP_CKSUM |
1191                 DEV_RX_OFFLOAD_TCP_CKSUM |
1192                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1193                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1194                 DEV_RX_OFFLOAD_RSS_HASH |
1195                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1196             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1197             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1198                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1199                             eth_dev->data->port_id);
1200                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1201                 return bnxt_recv_pkts_vec;
1202         }
1203         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1204                     eth_dev->data->port_id);
1205         PMD_DRV_LOG(INFO,
1206                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1207                     eth_dev->data->port_id,
1208                     eth_dev->data->scattered_rx,
1209                     eth_dev->data->dev_conf.rxmode.offloads);
1210 #endif
1211 #endif
1212         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1213         return bnxt_recv_pkts;
1214 }
1215
1216 static eth_tx_burst_t
1217 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1218 {
1219         struct bnxt *bp = eth_dev->data->dev_private;
1220
1221         /* Disable vector mode TX for Stingray2 for now */
1222         if (BNXT_CHIP_SR2(bp))
1223                 return bnxt_xmit_pkts;
1224
1225 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1226 #ifndef RTE_LIBRTE_IEEE1588
1227         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1228
1229         /*
1230          * Vector mode transmit can be enabled only if not using scatter rx
1231          * or tx offloads.
1232          */
1233         if (!eth_dev->data->scattered_rx &&
1234             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1235             !BNXT_TRUFLOW_EN(bp) &&
1236             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1237                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1238                             eth_dev->data->port_id);
1239                 return bnxt_xmit_pkts_vec;
1240         }
1241         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1242                     eth_dev->data->port_id);
1243         PMD_DRV_LOG(INFO,
1244                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1245                     eth_dev->data->port_id,
1246                     eth_dev->data->scattered_rx,
1247                     offloads);
1248 #endif
1249 #endif
1250         return bnxt_xmit_pkts;
1251 }
1252
1253 static int bnxt_handle_if_change_status(struct bnxt *bp)
1254 {
1255         int rc;
1256
1257         /* Since fw has undergone a reset and lost all contexts,
1258          * set fatal flag to not issue hwrm during cleanup
1259          */
1260         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1261         bnxt_uninit_resources(bp, true);
1262
1263         /* clear fatal flag so that re-init happens */
1264         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1265         rc = bnxt_init_resources(bp, true);
1266
1267         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1268
1269         return rc;
1270 }
1271
1272 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1273 {
1274         struct bnxt *bp = eth_dev->data->dev_private;
1275         int rc = 0;
1276
1277         if (!BNXT_SINGLE_PF(bp))
1278                 return -ENOTSUP;
1279
1280         if (!bp->link_info->link_up)
1281                 rc = bnxt_set_hwrm_link_config(bp, true);
1282         if (!rc)
1283                 eth_dev->data->dev_link.link_status = 1;
1284
1285         bnxt_print_link_info(eth_dev);
1286         return rc;
1287 }
1288
1289 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1290 {
1291         struct bnxt *bp = eth_dev->data->dev_private;
1292
1293         if (!BNXT_SINGLE_PF(bp))
1294                 return -ENOTSUP;
1295
1296         eth_dev->data->dev_link.link_status = 0;
1297         bnxt_set_hwrm_link_config(bp, false);
1298         bp->link_info->link_up = 0;
1299
1300         return 0;
1301 }
1302
1303 static void bnxt_free_switch_domain(struct bnxt *bp)
1304 {
1305         int rc = 0;
1306
1307         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1308                 return;
1309
1310         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1311         if (rc)
1312                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1313                             bp->switch_domain_id, rc);
1314 }
1315
1316 static void bnxt_ptp_get_current_time(void *arg)
1317 {
1318         struct bnxt *bp = arg;
1319         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1320         int rc;
1321
1322         rc = is_bnxt_in_error(bp);
1323         if (rc)
1324                 return;
1325
1326         if (!ptp)
1327                 return;
1328
1329         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1330                                 &ptp->current_time);
1331
1332         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1333         if (rc != 0) {
1334                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1335                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1336         }
1337 }
1338
1339 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1340 {
1341         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1342         int rc;
1343
1344         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1345                 return 0;
1346
1347         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1348                                 &ptp->current_time);
1349
1350         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1351         return rc;
1352 }
1353
1354 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1355 {
1356         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1357                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1358                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1359         }
1360 }
1361
1362 static void bnxt_ptp_stop(struct bnxt *bp)
1363 {
1364         bnxt_cancel_ptp_alarm(bp);
1365         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1366 }
1367
1368 static int bnxt_ptp_start(struct bnxt *bp)
1369 {
1370         int rc;
1371
1372         rc = bnxt_schedule_ptp_alarm(bp);
1373         if (rc != 0) {
1374                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1375         } else {
1376                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1377                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1378         }
1379
1380         return rc;
1381 }
1382
1383 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1384 {
1385         struct bnxt *bp = eth_dev->data->dev_private;
1386         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1387         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1388         struct rte_eth_link link;
1389         int ret;
1390
1391         eth_dev->data->dev_started = 0;
1392         eth_dev->data->scattered_rx = 0;
1393
1394         /* Prevent crashes when queues are still in use */
1395         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1396         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1397
1398         bnxt_disable_int(bp);
1399
1400         /* disable uio/vfio intr/eventfd mapping */
1401         rte_intr_disable(intr_handle);
1402
1403         /* Stop the child representors for this device */
1404         ret = bnxt_rep_stop_all(bp);
1405         if (ret != 0)
1406                 return ret;
1407
1408         /* delete the bnxt ULP port details */
1409         bnxt_ulp_port_deinit(bp);
1410
1411         bnxt_cancel_fw_health_check(bp);
1412
1413         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1414                 bnxt_cancel_ptp_alarm(bp);
1415
1416         /* Do not bring link down during reset recovery */
1417         if (!is_bnxt_in_error(bp)) {
1418                 bnxt_dev_set_link_down_op(eth_dev);
1419                 /* Wait for link to be reset */
1420                 if (BNXT_SINGLE_PF(bp))
1421                         rte_delay_ms(500);
1422                 /* clear the recorded link status */
1423                 memset(&link, 0, sizeof(link));
1424                 rte_eth_linkstatus_set(eth_dev, &link);
1425         }
1426
1427         /* Clean queue intr-vector mapping */
1428         rte_intr_efd_disable(intr_handle);
1429         if (intr_handle->intr_vec != NULL) {
1430                 rte_free(intr_handle->intr_vec);
1431                 intr_handle->intr_vec = NULL;
1432         }
1433
1434         bnxt_hwrm_port_clr_stats(bp);
1435         bnxt_free_tx_mbufs(bp);
1436         bnxt_free_rx_mbufs(bp);
1437         /* Process any remaining notifications in default completion queue */
1438         bnxt_int_handler(eth_dev);
1439         bnxt_shutdown_nic(bp);
1440         bnxt_hwrm_if_change(bp, false);
1441
1442         rte_free(bp->mark_table);
1443         bp->mark_table = NULL;
1444
1445         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1446         bp->rx_cosq_cnt = 0;
1447         /* All filters are deleted on a port stop. */
1448         if (BNXT_FLOW_XSTATS_EN(bp))
1449                 bp->flow_stat->flow_count = 0;
1450
1451         return 0;
1452 }
1453
1454 /* Unload the driver, release resources */
1455 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1456 {
1457         struct bnxt *bp = eth_dev->data->dev_private;
1458
1459         pthread_mutex_lock(&bp->err_recovery_lock);
1460         if (bp->flags & BNXT_FLAG_FW_RESET) {
1461                 PMD_DRV_LOG(ERR,
1462                             "Adapter recovering from error..Please retry\n");
1463                 pthread_mutex_unlock(&bp->err_recovery_lock);
1464                 return -EAGAIN;
1465         }
1466         pthread_mutex_unlock(&bp->err_recovery_lock);
1467
1468         return bnxt_dev_stop(eth_dev);
1469 }
1470
1471 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1472 {
1473         struct bnxt *bp = eth_dev->data->dev_private;
1474         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1475         int vlan_mask = 0;
1476         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1477
1478         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1479                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1480                 return -EINVAL;
1481         }
1482
1483         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1484                 PMD_DRV_LOG(ERR,
1485                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1486                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1487
1488         do {
1489                 rc = bnxt_hwrm_if_change(bp, true);
1490                 if (rc == 0 || rc != -EAGAIN)
1491                         break;
1492
1493                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1494         } while (retry_cnt--);
1495
1496         if (rc)
1497                 return rc;
1498
1499         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1500                 rc = bnxt_handle_if_change_status(bp);
1501                 if (rc)
1502                         return rc;
1503         }
1504
1505         bnxt_enable_int(bp);
1506
1507         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1508
1509         rc = bnxt_start_nic(bp);
1510         if (rc)
1511                 goto error;
1512
1513         eth_dev->data->dev_started = 1;
1514
1515         bnxt_link_update_op(eth_dev, 1);
1516
1517         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1518                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1519         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1520                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1521         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1522         if (rc)
1523                 goto error;
1524
1525         /* Initialize bnxt ULP port details */
1526         rc = bnxt_ulp_port_init(bp);
1527         if (rc)
1528                 goto error;
1529
1530         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1531         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1532
1533         bnxt_schedule_fw_health_check(bp);
1534
1535         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1536                 bnxt_schedule_ptp_alarm(bp);
1537
1538         return 0;
1539
1540 error:
1541         bnxt_dev_stop(eth_dev);
1542         return rc;
1543 }
1544
1545 static void
1546 bnxt_uninit_locks(struct bnxt *bp)
1547 {
1548         pthread_mutex_destroy(&bp->flow_lock);
1549         pthread_mutex_destroy(&bp->def_cp_lock);
1550         pthread_mutex_destroy(&bp->health_check_lock);
1551         pthread_mutex_destroy(&bp->err_recovery_lock);
1552         if (bp->rep_info) {
1553                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1554                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1555         }
1556 }
1557
1558 static void bnxt_drv_uninit(struct bnxt *bp)
1559 {
1560         bnxt_free_leds_info(bp);
1561         bnxt_free_cos_queues(bp);
1562         bnxt_free_link_info(bp);
1563         bnxt_free_parent_info(bp);
1564         bnxt_uninit_locks(bp);
1565
1566         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1567         bp->tx_mem_zone = NULL;
1568         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1569         bp->rx_mem_zone = NULL;
1570
1571         bnxt_free_vf_info(bp);
1572         bnxt_free_pf_info(bp);
1573
1574         rte_free(bp->grp_info);
1575         bp->grp_info = NULL;
1576 }
1577
1578 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1579 {
1580         struct bnxt *bp = eth_dev->data->dev_private;
1581         int ret = 0;
1582
1583         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1584                 return 0;
1585
1586         pthread_mutex_lock(&bp->err_recovery_lock);
1587         if (bp->flags & BNXT_FLAG_FW_RESET) {
1588                 PMD_DRV_LOG(ERR,
1589                             "Adapter recovering from error...Please retry\n");
1590                 pthread_mutex_unlock(&bp->err_recovery_lock);
1591                 return -EAGAIN;
1592         }
1593         pthread_mutex_unlock(&bp->err_recovery_lock);
1594
1595         /* cancel the recovery handler before remove dev */
1596         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1597         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1598         bnxt_cancel_fc_thread(bp);
1599
1600         if (eth_dev->data->dev_started)
1601                 ret = bnxt_dev_stop(eth_dev);
1602
1603         bnxt_uninit_resources(bp, false);
1604
1605         bnxt_drv_uninit(bp);
1606
1607         return ret;
1608 }
1609
1610 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1611                                     uint32_t index)
1612 {
1613         struct bnxt *bp = eth_dev->data->dev_private;
1614         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1615         struct bnxt_vnic_info *vnic;
1616         struct bnxt_filter_info *filter, *temp_filter;
1617         uint32_t i;
1618
1619         if (is_bnxt_in_error(bp))
1620                 return;
1621
1622         /*
1623          * Loop through all VNICs from the specified filter flow pools to
1624          * remove the corresponding MAC addr filter
1625          */
1626         for (i = 0; i < bp->nr_vnics; i++) {
1627                 if (!(pool_mask & (1ULL << i)))
1628                         continue;
1629
1630                 vnic = &bp->vnic_info[i];
1631                 filter = STAILQ_FIRST(&vnic->filter);
1632                 while (filter) {
1633                         temp_filter = STAILQ_NEXT(filter, next);
1634                         if (filter->mac_index == index) {
1635                                 STAILQ_REMOVE(&vnic->filter, filter,
1636                                                 bnxt_filter_info, next);
1637                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1638                                 bnxt_free_filter(bp, filter);
1639                         }
1640                         filter = temp_filter;
1641                 }
1642         }
1643 }
1644
1645 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1646                                struct rte_ether_addr *mac_addr, uint32_t index,
1647                                uint32_t pool)
1648 {
1649         struct bnxt_filter_info *filter;
1650         int rc = 0;
1651
1652         /* Attach requested MAC address to the new l2_filter */
1653         STAILQ_FOREACH(filter, &vnic->filter, next) {
1654                 if (filter->mac_index == index) {
1655                         PMD_DRV_LOG(DEBUG,
1656                                     "MAC addr already existed for pool %d\n",
1657                                     pool);
1658                         return 0;
1659                 }
1660         }
1661
1662         filter = bnxt_alloc_filter(bp);
1663         if (!filter) {
1664                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1665                 return -ENODEV;
1666         }
1667
1668         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1669          * if the MAC that's been programmed now is a different one, then,
1670          * copy that addr to filter->l2_addr
1671          */
1672         if (mac_addr)
1673                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1674         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1675
1676         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1677         if (!rc) {
1678                 filter->mac_index = index;
1679                 if (filter->mac_index == 0)
1680                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1681                 else
1682                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1683         } else {
1684                 bnxt_free_filter(bp, filter);
1685         }
1686
1687         return rc;
1688 }
1689
1690 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1691                                 struct rte_ether_addr *mac_addr,
1692                                 uint32_t index, uint32_t pool)
1693 {
1694         struct bnxt *bp = eth_dev->data->dev_private;
1695         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1696         int rc = 0;
1697
1698         rc = is_bnxt_in_error(bp);
1699         if (rc)
1700                 return rc;
1701
1702         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1703                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1704                 return -ENOTSUP;
1705         }
1706
1707         if (!vnic) {
1708                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1709                 return -EINVAL;
1710         }
1711
1712         /* Filter settings will get applied when port is started */
1713         if (!eth_dev->data->dev_started)
1714                 return 0;
1715
1716         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1717
1718         return rc;
1719 }
1720
1721 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1722 {
1723         int rc = 0;
1724         struct bnxt *bp = eth_dev->data->dev_private;
1725         struct rte_eth_link new;
1726         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1727                         BNXT_MIN_LINK_WAIT_CNT;
1728
1729         rc = is_bnxt_in_error(bp);
1730         if (rc)
1731                 return rc;
1732
1733         memset(&new, 0, sizeof(new));
1734
1735         if (bp->link_info == NULL)
1736                 goto out;
1737
1738         do {
1739                 /* Retrieve link info from hardware */
1740                 rc = bnxt_get_hwrm_link_config(bp, &new);
1741                 if (rc) {
1742                         new.link_speed = ETH_LINK_SPEED_100M;
1743                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1744                         PMD_DRV_LOG(ERR,
1745                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1746                         goto out;
1747                 }
1748
1749                 if (!wait_to_complete || new.link_status)
1750                         break;
1751
1752                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1753         } while (cnt--);
1754
1755         /* Only single function PF can bring phy down.
1756          * When port is stopped, report link down for VF/MH/NPAR functions.
1757          */
1758         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1759                 memset(&new, 0, sizeof(new));
1760
1761 out:
1762         /* Timed out or success */
1763         if (new.link_status != eth_dev->data->dev_link.link_status ||
1764             new.link_speed != eth_dev->data->dev_link.link_speed) {
1765                 rte_eth_linkstatus_set(eth_dev, &new);
1766
1767                 rte_eth_dev_callback_process(eth_dev,
1768                                              RTE_ETH_EVENT_INTR_LSC,
1769                                              NULL);
1770
1771                 bnxt_print_link_info(eth_dev);
1772         }
1773
1774         return rc;
1775 }
1776
1777 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1778 {
1779         struct bnxt *bp = eth_dev->data->dev_private;
1780         struct bnxt_vnic_info *vnic;
1781         uint32_t old_flags;
1782         int rc;
1783
1784         rc = is_bnxt_in_error(bp);
1785         if (rc)
1786                 return rc;
1787
1788         /* Filter settings will get applied when port is started */
1789         if (!eth_dev->data->dev_started)
1790                 return 0;
1791
1792         if (bp->vnic_info == NULL)
1793                 return 0;
1794
1795         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1796
1797         old_flags = vnic->flags;
1798         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1799         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1800         if (rc != 0)
1801                 vnic->flags = old_flags;
1802
1803         return rc;
1804 }
1805
1806 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1807 {
1808         struct bnxt *bp = eth_dev->data->dev_private;
1809         struct bnxt_vnic_info *vnic;
1810         uint32_t old_flags;
1811         int rc;
1812
1813         rc = is_bnxt_in_error(bp);
1814         if (rc)
1815                 return rc;
1816
1817         /* Filter settings will get applied when port is started */
1818         if (!eth_dev->data->dev_started)
1819                 return 0;
1820
1821         if (bp->vnic_info == NULL)
1822                 return 0;
1823
1824         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1825
1826         old_flags = vnic->flags;
1827         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1828         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1829         if (rc != 0)
1830                 vnic->flags = old_flags;
1831
1832         return rc;
1833 }
1834
1835 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1836 {
1837         struct bnxt *bp = eth_dev->data->dev_private;
1838         struct bnxt_vnic_info *vnic;
1839         uint32_t old_flags;
1840         int rc;
1841
1842         rc = is_bnxt_in_error(bp);
1843         if (rc)
1844                 return rc;
1845
1846         /* Filter settings will get applied when port is started */
1847         if (!eth_dev->data->dev_started)
1848                 return 0;
1849
1850         if (bp->vnic_info == NULL)
1851                 return 0;
1852
1853         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1854
1855         old_flags = vnic->flags;
1856         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1857         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1858         if (rc != 0)
1859                 vnic->flags = old_flags;
1860
1861         return rc;
1862 }
1863
1864 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1865 {
1866         struct bnxt *bp = eth_dev->data->dev_private;
1867         struct bnxt_vnic_info *vnic;
1868         uint32_t old_flags;
1869         int rc;
1870
1871         rc = is_bnxt_in_error(bp);
1872         if (rc)
1873                 return rc;
1874
1875         /* Filter settings will get applied when port is started */
1876         if (!eth_dev->data->dev_started)
1877                 return 0;
1878
1879         if (bp->vnic_info == NULL)
1880                 return 0;
1881
1882         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1883
1884         old_flags = vnic->flags;
1885         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1886         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1887         if (rc != 0)
1888                 vnic->flags = old_flags;
1889
1890         return rc;
1891 }
1892
1893 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1894 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1895 {
1896         if (qid >= bp->rx_nr_rings)
1897                 return NULL;
1898
1899         return bp->eth_dev->data->rx_queues[qid];
1900 }
1901
1902 /* Return rxq corresponding to a given rss table ring/group ID. */
1903 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1904 {
1905         struct bnxt_rx_queue *rxq;
1906         unsigned int i;
1907
1908         if (!BNXT_HAS_RING_GRPS(bp)) {
1909                 for (i = 0; i < bp->rx_nr_rings; i++) {
1910                         rxq = bp->eth_dev->data->rx_queues[i];
1911                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1912                                 return rxq->index;
1913                 }
1914         } else {
1915                 for (i = 0; i < bp->rx_nr_rings; i++) {
1916                         if (bp->grp_info[i].fw_grp_id == fwr)
1917                                 return i;
1918                 }
1919         }
1920
1921         return INVALID_HW_RING_ID;
1922 }
1923
1924 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1925                             struct rte_eth_rss_reta_entry64 *reta_conf,
1926                             uint16_t reta_size)
1927 {
1928         struct bnxt *bp = eth_dev->data->dev_private;
1929         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1930         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1931         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1932         uint16_t idx, sft;
1933         int i, rc;
1934
1935         rc = is_bnxt_in_error(bp);
1936         if (rc)
1937                 return rc;
1938
1939         if (!vnic->rss_table)
1940                 return -EINVAL;
1941
1942         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1943                 return -EINVAL;
1944
1945         if (reta_size != tbl_size) {
1946                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1947                         "(%d) must equal the size supported by the hardware "
1948                         "(%d)\n", reta_size, tbl_size);
1949                 return -EINVAL;
1950         }
1951
1952         for (i = 0; i < reta_size; i++) {
1953                 struct bnxt_rx_queue *rxq;
1954
1955                 idx = i / RTE_RETA_GROUP_SIZE;
1956                 sft = i % RTE_RETA_GROUP_SIZE;
1957
1958                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1959                         continue;
1960
1961                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1962                 if (!rxq) {
1963                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1964                         return -EINVAL;
1965                 }
1966
1967                 if (BNXT_CHIP_P5(bp)) {
1968                         vnic->rss_table[i * 2] =
1969                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1970                         vnic->rss_table[i * 2 + 1] =
1971                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1972                 } else {
1973                         vnic->rss_table[i] =
1974                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1975                 }
1976         }
1977
1978         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1979         return rc;
1980 }
1981
1982 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1983                               struct rte_eth_rss_reta_entry64 *reta_conf,
1984                               uint16_t reta_size)
1985 {
1986         struct bnxt *bp = eth_dev->data->dev_private;
1987         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1988         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1989         uint16_t idx, sft, i;
1990         int rc;
1991
1992         rc = is_bnxt_in_error(bp);
1993         if (rc)
1994                 return rc;
1995
1996         /* Retrieve from the default VNIC */
1997         if (!vnic)
1998                 return -EINVAL;
1999         if (!vnic->rss_table)
2000                 return -EINVAL;
2001
2002         if (reta_size != tbl_size) {
2003                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2004                         "(%d) must equal the size supported by the hardware "
2005                         "(%d)\n", reta_size, tbl_size);
2006                 return -EINVAL;
2007         }
2008
2009         for (idx = 0, i = 0; i < reta_size; i++) {
2010                 idx = i / RTE_RETA_GROUP_SIZE;
2011                 sft = i % RTE_RETA_GROUP_SIZE;
2012
2013                 if (reta_conf[idx].mask & (1ULL << sft)) {
2014                         uint16_t qid;
2015
2016                         if (BNXT_CHIP_P5(bp))
2017                                 qid = bnxt_rss_to_qid(bp,
2018                                                       vnic->rss_table[i * 2]);
2019                         else
2020                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2021
2022                         if (qid == INVALID_HW_RING_ID) {
2023                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2024                                 return -EINVAL;
2025                         }
2026                         reta_conf[idx].reta[sft] = qid;
2027                 }
2028         }
2029
2030         return 0;
2031 }
2032
2033 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2034                                    struct rte_eth_rss_conf *rss_conf)
2035 {
2036         struct bnxt *bp = eth_dev->data->dev_private;
2037         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2038         struct bnxt_vnic_info *vnic;
2039         int rc;
2040
2041         rc = is_bnxt_in_error(bp);
2042         if (rc)
2043                 return rc;
2044
2045         /*
2046          * If RSS enablement were different than dev_configure,
2047          * then return -EINVAL
2048          */
2049         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2050                 if (!rss_conf->rss_hf)
2051                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2052         } else {
2053                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2054                         return -EINVAL;
2055         }
2056
2057         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2058         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2059                rss_conf,
2060                sizeof(*rss_conf));
2061
2062         /* Update the default RSS VNIC(s) */
2063         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2064         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2065         vnic->hash_mode =
2066                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2067                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2068
2069         /*
2070          * If hashkey is not specified, use the previously configured
2071          * hashkey
2072          */
2073         if (!rss_conf->rss_key)
2074                 goto rss_config;
2075
2076         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2077                 PMD_DRV_LOG(ERR,
2078                             "Invalid hashkey length, should be 16 bytes\n");
2079                 return -EINVAL;
2080         }
2081         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2082
2083 rss_config:
2084         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2085         return rc;
2086 }
2087
2088 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2089                                      struct rte_eth_rss_conf *rss_conf)
2090 {
2091         struct bnxt *bp = eth_dev->data->dev_private;
2092         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2093         int len, rc;
2094         uint32_t hash_types;
2095
2096         rc = is_bnxt_in_error(bp);
2097         if (rc)
2098                 return rc;
2099
2100         /* RSS configuration is the same for all VNICs */
2101         if (vnic && vnic->rss_hash_key) {
2102                 if (rss_conf->rss_key) {
2103                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2104                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2105                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2106                 }
2107
2108                 hash_types = vnic->hash_type;
2109                 rss_conf->rss_hf = 0;
2110                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2111                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2112                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2113                 }
2114                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2115                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2116                         hash_types &=
2117                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2118                 }
2119                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2120                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2121                         hash_types &=
2122                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2123                 }
2124                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2125                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2126                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2127                 }
2128                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2129                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2130                         hash_types &=
2131                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2132                 }
2133                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2134                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2135                         hash_types &=
2136                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2137                 }
2138
2139                 rss_conf->rss_hf |=
2140                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2141
2142                 if (hash_types) {
2143                         PMD_DRV_LOG(ERR,
2144                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2145                                 vnic->hash_type);
2146                         return -ENOTSUP;
2147                 }
2148         } else {
2149                 rss_conf->rss_hf = 0;
2150         }
2151         return 0;
2152 }
2153
2154 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2155                                struct rte_eth_fc_conf *fc_conf)
2156 {
2157         struct bnxt *bp = dev->data->dev_private;
2158         struct rte_eth_link link_info;
2159         int rc;
2160
2161         rc = is_bnxt_in_error(bp);
2162         if (rc)
2163                 return rc;
2164
2165         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2166         if (rc)
2167                 return rc;
2168
2169         memset(fc_conf, 0, sizeof(*fc_conf));
2170         if (bp->link_info->auto_pause)
2171                 fc_conf->autoneg = 1;
2172         switch (bp->link_info->pause) {
2173         case 0:
2174                 fc_conf->mode = RTE_FC_NONE;
2175                 break;
2176         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2177                 fc_conf->mode = RTE_FC_TX_PAUSE;
2178                 break;
2179         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2180                 fc_conf->mode = RTE_FC_RX_PAUSE;
2181                 break;
2182         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2183                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2184                 fc_conf->mode = RTE_FC_FULL;
2185                 break;
2186         }
2187         return 0;
2188 }
2189
2190 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2191                                struct rte_eth_fc_conf *fc_conf)
2192 {
2193         struct bnxt *bp = dev->data->dev_private;
2194         int rc;
2195
2196         rc = is_bnxt_in_error(bp);
2197         if (rc)
2198                 return rc;
2199
2200         if (!BNXT_SINGLE_PF(bp)) {
2201                 PMD_DRV_LOG(ERR,
2202                             "Flow Control Settings cannot be modified on VF or on shared PF\n");
2203                 return -ENOTSUP;
2204         }
2205
2206         switch (fc_conf->mode) {
2207         case RTE_FC_NONE:
2208                 bp->link_info->auto_pause = 0;
2209                 bp->link_info->force_pause = 0;
2210                 break;
2211         case RTE_FC_RX_PAUSE:
2212                 if (fc_conf->autoneg) {
2213                         bp->link_info->auto_pause =
2214                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2215                         bp->link_info->force_pause = 0;
2216                 } else {
2217                         bp->link_info->auto_pause = 0;
2218                         bp->link_info->force_pause =
2219                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2220                 }
2221                 break;
2222         case RTE_FC_TX_PAUSE:
2223                 if (fc_conf->autoneg) {
2224                         bp->link_info->auto_pause =
2225                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2226                         bp->link_info->force_pause = 0;
2227                 } else {
2228                         bp->link_info->auto_pause = 0;
2229                         bp->link_info->force_pause =
2230                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2231                 }
2232                 break;
2233         case RTE_FC_FULL:
2234                 if (fc_conf->autoneg) {
2235                         bp->link_info->auto_pause =
2236                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2237                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2238                         bp->link_info->force_pause = 0;
2239                 } else {
2240                         bp->link_info->auto_pause = 0;
2241                         bp->link_info->force_pause =
2242                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2243                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2244                 }
2245                 break;
2246         }
2247         return bnxt_set_hwrm_link_config(bp, true);
2248 }
2249
2250 /* Add UDP tunneling port */
2251 static int
2252 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2253                          struct rte_eth_udp_tunnel *udp_tunnel)
2254 {
2255         struct bnxt *bp = eth_dev->data->dev_private;
2256         uint16_t tunnel_type = 0;
2257         int rc = 0;
2258
2259         rc = is_bnxt_in_error(bp);
2260         if (rc)
2261                 return rc;
2262
2263         switch (udp_tunnel->prot_type) {
2264         case RTE_TUNNEL_TYPE_VXLAN:
2265                 if (bp->vxlan_port_cnt) {
2266                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2267                                 udp_tunnel->udp_port);
2268                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2269                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2270                                 return -ENOSPC;
2271                         }
2272                         bp->vxlan_port_cnt++;
2273                         return 0;
2274                 }
2275                 tunnel_type =
2276                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2277                 bp->vxlan_port_cnt++;
2278                 break;
2279         case RTE_TUNNEL_TYPE_GENEVE:
2280                 if (bp->geneve_port_cnt) {
2281                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2282                                 udp_tunnel->udp_port);
2283                         if (bp->geneve_port != udp_tunnel->udp_port) {
2284                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2285                                 return -ENOSPC;
2286                         }
2287                         bp->geneve_port_cnt++;
2288                         return 0;
2289                 }
2290                 tunnel_type =
2291                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2292                 bp->geneve_port_cnt++;
2293                 break;
2294         default:
2295                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2296                 return -ENOTSUP;
2297         }
2298         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2299                                              tunnel_type);
2300         return rc;
2301 }
2302
2303 static int
2304 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2305                          struct rte_eth_udp_tunnel *udp_tunnel)
2306 {
2307         struct bnxt *bp = eth_dev->data->dev_private;
2308         uint16_t tunnel_type = 0;
2309         uint16_t port = 0;
2310         int rc = 0;
2311
2312         rc = is_bnxt_in_error(bp);
2313         if (rc)
2314                 return rc;
2315
2316         switch (udp_tunnel->prot_type) {
2317         case RTE_TUNNEL_TYPE_VXLAN:
2318                 if (!bp->vxlan_port_cnt) {
2319                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2320                         return -EINVAL;
2321                 }
2322                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2323                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2324                                 udp_tunnel->udp_port, bp->vxlan_port);
2325                         return -EINVAL;
2326                 }
2327                 if (--bp->vxlan_port_cnt)
2328                         return 0;
2329
2330                 tunnel_type =
2331                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2332                 port = bp->vxlan_fw_dst_port_id;
2333                 break;
2334         case RTE_TUNNEL_TYPE_GENEVE:
2335                 if (!bp->geneve_port_cnt) {
2336                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2337                         return -EINVAL;
2338                 }
2339                 if (bp->geneve_port != udp_tunnel->udp_port) {
2340                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2341                                 udp_tunnel->udp_port, bp->geneve_port);
2342                         return -EINVAL;
2343                 }
2344                 if (--bp->geneve_port_cnt)
2345                         return 0;
2346
2347                 tunnel_type =
2348                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2349                 port = bp->geneve_fw_dst_port_id;
2350                 break;
2351         default:
2352                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2353                 return -ENOTSUP;
2354         }
2355
2356         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2357         return rc;
2358 }
2359
2360 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2361 {
2362         struct bnxt_filter_info *filter;
2363         struct bnxt_vnic_info *vnic;
2364         int rc = 0;
2365         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2366
2367         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2368         filter = STAILQ_FIRST(&vnic->filter);
2369         while (filter) {
2370                 /* Search for this matching MAC+VLAN filter */
2371                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2372                         /* Delete the filter */
2373                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2374                         if (rc)
2375                                 return rc;
2376                         STAILQ_REMOVE(&vnic->filter, filter,
2377                                       bnxt_filter_info, next);
2378                         bnxt_free_filter(bp, filter);
2379                         PMD_DRV_LOG(INFO,
2380                                     "Deleted vlan filter for %d\n",
2381                                     vlan_id);
2382                         return 0;
2383                 }
2384                 filter = STAILQ_NEXT(filter, next);
2385         }
2386         return -ENOENT;
2387 }
2388
2389 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2390 {
2391         struct bnxt_filter_info *filter;
2392         struct bnxt_vnic_info *vnic;
2393         int rc = 0;
2394         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2395                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2396         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2397
2398         /* Implementation notes on the use of VNIC in this command:
2399          *
2400          * By default, these filters belong to default vnic for the function.
2401          * Once these filters are set up, only destination VNIC can be modified.
2402          * If the destination VNIC is not specified in this command,
2403          * then the HWRM shall only create an l2 context id.
2404          */
2405
2406         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2407         filter = STAILQ_FIRST(&vnic->filter);
2408         /* Check if the VLAN has already been added */
2409         while (filter) {
2410                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2411                         return -EEXIST;
2412
2413                 filter = STAILQ_NEXT(filter, next);
2414         }
2415
2416         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2417          * command to create MAC+VLAN filter with the right flags, enables set.
2418          */
2419         filter = bnxt_alloc_filter(bp);
2420         if (!filter) {
2421                 PMD_DRV_LOG(ERR,
2422                             "MAC/VLAN filter alloc failed\n");
2423                 return -ENOMEM;
2424         }
2425         /* MAC + VLAN ID filter */
2426         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2427          * untagged packets are received
2428          *
2429          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2430          * packets and only the programmed vlan's packets are received
2431          */
2432         filter->l2_ivlan = vlan_id;
2433         filter->l2_ivlan_mask = 0x0FFF;
2434         filter->enables |= en;
2435         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2436
2437         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2438         if (rc) {
2439                 /* Free the newly allocated filter as we were
2440                  * not able to create the filter in hardware.
2441                  */
2442                 bnxt_free_filter(bp, filter);
2443                 return rc;
2444         }
2445
2446         filter->mac_index = 0;
2447         /* Add this new filter to the list */
2448         if (vlan_id == 0)
2449                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2450         else
2451                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2452
2453         PMD_DRV_LOG(INFO,
2454                     "Added Vlan filter for %d\n", vlan_id);
2455         return rc;
2456 }
2457
2458 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2459                 uint16_t vlan_id, int on)
2460 {
2461         struct bnxt *bp = eth_dev->data->dev_private;
2462         int rc;
2463
2464         rc = is_bnxt_in_error(bp);
2465         if (rc)
2466                 return rc;
2467
2468         if (!eth_dev->data->dev_started) {
2469                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2470                 return -EINVAL;
2471         }
2472
2473         /* These operations apply to ALL existing MAC/VLAN filters */
2474         if (on)
2475                 return bnxt_add_vlan_filter(bp, vlan_id);
2476         else
2477                 return bnxt_del_vlan_filter(bp, vlan_id);
2478 }
2479
2480 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2481                                     struct bnxt_vnic_info *vnic)
2482 {
2483         struct bnxt_filter_info *filter;
2484         int rc;
2485
2486         filter = STAILQ_FIRST(&vnic->filter);
2487         while (filter) {
2488                 if (filter->mac_index == 0 &&
2489                     !memcmp(filter->l2_addr, bp->mac_addr,
2490                             RTE_ETHER_ADDR_LEN)) {
2491                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2492                         if (!rc) {
2493                                 STAILQ_REMOVE(&vnic->filter, filter,
2494                                               bnxt_filter_info, next);
2495                                 bnxt_free_filter(bp, filter);
2496                         }
2497                         return rc;
2498                 }
2499                 filter = STAILQ_NEXT(filter, next);
2500         }
2501         return 0;
2502 }
2503
2504 static int
2505 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2506 {
2507         struct bnxt_vnic_info *vnic;
2508         unsigned int i;
2509         int rc;
2510
2511         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2512         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2513                 /* Remove any VLAN filters programmed */
2514                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2515                         bnxt_del_vlan_filter(bp, i);
2516
2517                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2518                 if (rc)
2519                         return rc;
2520         } else {
2521                 /* Default filter will allow packets that match the
2522                  * dest mac. So, it has to be deleted, otherwise, we
2523                  * will endup receiving vlan packets for which the
2524                  * filter is not programmed, when hw-vlan-filter
2525                  * configuration is ON
2526                  */
2527                 bnxt_del_dflt_mac_filter(bp, vnic);
2528                 /* This filter will allow only untagged packets */
2529                 bnxt_add_vlan_filter(bp, 0);
2530         }
2531         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2532                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2533
2534         return 0;
2535 }
2536
2537 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2538 {
2539         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2540         unsigned int i;
2541         int rc;
2542
2543         /* Destroy vnic filters and vnic */
2544         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2545             DEV_RX_OFFLOAD_VLAN_FILTER) {
2546                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2547                         bnxt_del_vlan_filter(bp, i);
2548         }
2549         bnxt_del_dflt_mac_filter(bp, vnic);
2550
2551         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2552         if (rc)
2553                 return rc;
2554
2555         rc = bnxt_hwrm_vnic_free(bp, vnic);
2556         if (rc)
2557                 return rc;
2558
2559         rte_free(vnic->fw_grp_ids);
2560         vnic->fw_grp_ids = NULL;
2561
2562         vnic->rx_queue_cnt = 0;
2563
2564         return 0;
2565 }
2566
2567 static int
2568 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2569 {
2570         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2571         int rc;
2572
2573         /* Destroy, recreate and reconfigure the default vnic */
2574         rc = bnxt_free_one_vnic(bp, 0);
2575         if (rc)
2576                 return rc;
2577
2578         /* default vnic 0 */
2579         rc = bnxt_setup_one_vnic(bp, 0);
2580         if (rc)
2581                 return rc;
2582
2583         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2584             DEV_RX_OFFLOAD_VLAN_FILTER) {
2585                 rc = bnxt_add_vlan_filter(bp, 0);
2586                 if (rc)
2587                         return rc;
2588                 rc = bnxt_restore_vlan_filters(bp);
2589                 if (rc)
2590                         return rc;
2591         } else {
2592                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2593                 if (rc)
2594                         return rc;
2595         }
2596
2597         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2598         if (rc)
2599                 return rc;
2600
2601         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2602                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2603
2604         return rc;
2605 }
2606
2607 static int
2608 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2609 {
2610         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2611         struct bnxt *bp = dev->data->dev_private;
2612         int rc;
2613
2614         rc = is_bnxt_in_error(bp);
2615         if (rc)
2616                 return rc;
2617
2618         /* Filter settings will get applied when port is started */
2619         if (!dev->data->dev_started)
2620                 return 0;
2621
2622         if (mask & ETH_VLAN_FILTER_MASK) {
2623                 /* Enable or disable VLAN filtering */
2624                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2625                 if (rc)
2626                         return rc;
2627         }
2628
2629         if (mask & ETH_VLAN_STRIP_MASK) {
2630                 /* Enable or disable VLAN stripping */
2631                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2632                 if (rc)
2633                         return rc;
2634         }
2635
2636         if (mask & ETH_VLAN_EXTEND_MASK) {
2637                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2638                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2639                 else
2640                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2641         }
2642
2643         return 0;
2644 }
2645
2646 static int
2647 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2648                       uint16_t tpid)
2649 {
2650         struct bnxt *bp = dev->data->dev_private;
2651         int qinq = dev->data->dev_conf.rxmode.offloads &
2652                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2653
2654         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2655             vlan_type != ETH_VLAN_TYPE_OUTER) {
2656                 PMD_DRV_LOG(ERR,
2657                             "Unsupported vlan type.");
2658                 return -EINVAL;
2659         }
2660         if (!qinq) {
2661                 PMD_DRV_LOG(ERR,
2662                             "QinQ not enabled. Needs to be ON as we can "
2663                             "accelerate only outer vlan\n");
2664                 return -EINVAL;
2665         }
2666
2667         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2668                 switch (tpid) {
2669                 case RTE_ETHER_TYPE_QINQ:
2670                         bp->outer_tpid_bd =
2671                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2672                                 break;
2673                 case RTE_ETHER_TYPE_VLAN:
2674                         bp->outer_tpid_bd =
2675                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2676                                 break;
2677                 case RTE_ETHER_TYPE_QINQ1:
2678                         bp->outer_tpid_bd =
2679                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2680                                 break;
2681                 case RTE_ETHER_TYPE_QINQ2:
2682                         bp->outer_tpid_bd =
2683                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2684                                 break;
2685                 case RTE_ETHER_TYPE_QINQ3:
2686                         bp->outer_tpid_bd =
2687                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2688                                 break;
2689                 default:
2690                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2691                         return -EINVAL;
2692                 }
2693                 bp->outer_tpid_bd |= tpid;
2694                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2695         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2696                 PMD_DRV_LOG(ERR,
2697                             "Can accelerate only outer vlan in QinQ\n");
2698                 return -EINVAL;
2699         }
2700
2701         return 0;
2702 }
2703
2704 static int
2705 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2706                              struct rte_ether_addr *addr)
2707 {
2708         struct bnxt *bp = dev->data->dev_private;
2709         /* Default Filter is tied to VNIC 0 */
2710         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2711         int rc;
2712
2713         rc = is_bnxt_in_error(bp);
2714         if (rc)
2715                 return rc;
2716
2717         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2718                 return -EPERM;
2719
2720         if (rte_is_zero_ether_addr(addr))
2721                 return -EINVAL;
2722
2723         /* Filter settings will get applied when port is started */
2724         if (!dev->data->dev_started)
2725                 return 0;
2726
2727         /* Check if the requested MAC is already added */
2728         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2729                 return 0;
2730
2731         /* Destroy filter and re-create it */
2732         bnxt_del_dflt_mac_filter(bp, vnic);
2733
2734         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2735         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2736                 /* This filter will allow only untagged packets */
2737                 rc = bnxt_add_vlan_filter(bp, 0);
2738         } else {
2739                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2740         }
2741
2742         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2743         return rc;
2744 }
2745
2746 static int
2747 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2748                           struct rte_ether_addr *mc_addr_set,
2749                           uint32_t nb_mc_addr)
2750 {
2751         struct bnxt *bp = eth_dev->data->dev_private;
2752         char *mc_addr_list = (char *)mc_addr_set;
2753         struct bnxt_vnic_info *vnic;
2754         uint32_t off = 0, i = 0;
2755         int rc;
2756
2757         rc = is_bnxt_in_error(bp);
2758         if (rc)
2759                 return rc;
2760
2761         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2762
2763         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2764                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2765                 goto allmulti;
2766         }
2767
2768         /* TODO Check for Duplicate mcast addresses */
2769         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2770         for (i = 0; i < nb_mc_addr; i++) {
2771                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2772                         RTE_ETHER_ADDR_LEN);
2773                 off += RTE_ETHER_ADDR_LEN;
2774         }
2775
2776         vnic->mc_addr_cnt = i;
2777         if (vnic->mc_addr_cnt)
2778                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2779         else
2780                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2781
2782 allmulti:
2783         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2784 }
2785
2786 static int
2787 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2788 {
2789         struct bnxt *bp = dev->data->dev_private;
2790         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2791         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2792         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2793         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2794         int ret;
2795
2796         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2797                         fw_major, fw_minor, fw_updt, fw_rsvd);
2798         if (ret < 0)
2799                 return -EINVAL;
2800
2801         ret += 1; /* add the size of '\0' */
2802         if (fw_size < (size_t)ret)
2803                 return ret;
2804         else
2805                 return 0;
2806 }
2807
2808 static void
2809 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2810         struct rte_eth_rxq_info *qinfo)
2811 {
2812         struct bnxt *bp = dev->data->dev_private;
2813         struct bnxt_rx_queue *rxq;
2814
2815         if (is_bnxt_in_error(bp))
2816                 return;
2817
2818         rxq = dev->data->rx_queues[queue_id];
2819
2820         qinfo->mp = rxq->mb_pool;
2821         qinfo->scattered_rx = dev->data->scattered_rx;
2822         qinfo->nb_desc = rxq->nb_rx_desc;
2823
2824         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2825         qinfo->conf.rx_drop_en = rxq->drop_en;
2826         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2827         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2828 }
2829
2830 static void
2831 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2832         struct rte_eth_txq_info *qinfo)
2833 {
2834         struct bnxt *bp = dev->data->dev_private;
2835         struct bnxt_tx_queue *txq;
2836
2837         if (is_bnxt_in_error(bp))
2838                 return;
2839
2840         txq = dev->data->tx_queues[queue_id];
2841
2842         qinfo->nb_desc = txq->nb_tx_desc;
2843
2844         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2845         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2846         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2847
2848         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2849         qinfo->conf.tx_rs_thresh = 0;
2850         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2851         qinfo->conf.offloads = txq->offloads;
2852 }
2853
2854 static const struct {
2855         eth_rx_burst_t pkt_burst;
2856         const char *info;
2857 } bnxt_rx_burst_info[] = {
2858         {bnxt_recv_pkts,        "Scalar"},
2859 #if defined(RTE_ARCH_X86)
2860         {bnxt_recv_pkts_vec,    "Vector SSE"},
2861 #elif defined(RTE_ARCH_ARM64)
2862         {bnxt_recv_pkts_vec,    "Vector Neon"},
2863 #endif
2864 };
2865
2866 static int
2867 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2868                        struct rte_eth_burst_mode *mode)
2869 {
2870         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2871         size_t i;
2872
2873         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2874                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2875                         snprintf(mode->info, sizeof(mode->info), "%s",
2876                                  bnxt_rx_burst_info[i].info);
2877                         return 0;
2878                 }
2879         }
2880
2881         return -EINVAL;
2882 }
2883
2884 static const struct {
2885         eth_tx_burst_t pkt_burst;
2886         const char *info;
2887 } bnxt_tx_burst_info[] = {
2888         {bnxt_xmit_pkts,        "Scalar"},
2889 #if defined(RTE_ARCH_X86)
2890         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2891 #elif defined(RTE_ARCH_ARM64)
2892         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2893 #endif
2894 };
2895
2896 static int
2897 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2898                        struct rte_eth_burst_mode *mode)
2899 {
2900         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2901         size_t i;
2902
2903         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2904                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2905                         snprintf(mode->info, sizeof(mode->info), "%s",
2906                                  bnxt_tx_burst_info[i].info);
2907                         return 0;
2908                 }
2909         }
2910
2911         return -EINVAL;
2912 }
2913
2914 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2915 {
2916         struct bnxt *bp = eth_dev->data->dev_private;
2917         uint32_t new_pkt_size;
2918         uint32_t rc = 0;
2919         uint32_t i;
2920
2921         rc = is_bnxt_in_error(bp);
2922         if (rc)
2923                 return rc;
2924
2925         /* Exit if receive queues are not configured yet */
2926         if (!eth_dev->data->nb_rx_queues)
2927                 return rc;
2928
2929         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2930                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2931
2932         /*
2933          * Disallow any MTU change that would require scattered receive support
2934          * if it is not already enabled.
2935          */
2936         if (eth_dev->data->dev_started &&
2937             !eth_dev->data->scattered_rx &&
2938             (new_pkt_size >
2939              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2940                 PMD_DRV_LOG(ERR,
2941                             "MTU change would require scattered rx support. ");
2942                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2943                 return -EINVAL;
2944         }
2945
2946         if (new_mtu > RTE_ETHER_MTU) {
2947                 bp->flags |= BNXT_FLAG_JUMBO;
2948                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2949                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2950         } else {
2951                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2952                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2953                 bp->flags &= ~BNXT_FLAG_JUMBO;
2954         }
2955
2956         /* Is there a change in mtu setting? */
2957         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2958                 return rc;
2959
2960         for (i = 0; i < bp->nr_vnics; i++) {
2961                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2962                 uint16_t size = 0;
2963
2964                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2965                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2966                 if (rc)
2967                         break;
2968
2969                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2970                 size -= RTE_PKTMBUF_HEADROOM;
2971
2972                 if (size < new_mtu) {
2973                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2974                         if (rc)
2975                                 return rc;
2976                 }
2977         }
2978
2979         if (!rc)
2980                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2981
2982         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2983
2984         return rc;
2985 }
2986
2987 static int
2988 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2989 {
2990         struct bnxt *bp = dev->data->dev_private;
2991         uint16_t vlan = bp->vlan;
2992         int rc;
2993
2994         rc = is_bnxt_in_error(bp);
2995         if (rc)
2996                 return rc;
2997
2998         if (!BNXT_SINGLE_PF(bp)) {
2999                 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3000                 return -ENOTSUP;
3001         }
3002         bp->vlan = on ? pvid : 0;
3003
3004         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3005         if (rc)
3006                 bp->vlan = vlan;
3007         return rc;
3008 }
3009
3010 static int
3011 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3012 {
3013         struct bnxt *bp = dev->data->dev_private;
3014         int rc;
3015
3016         rc = is_bnxt_in_error(bp);
3017         if (rc)
3018                 return rc;
3019
3020         return bnxt_hwrm_port_led_cfg(bp, true);
3021 }
3022
3023 static int
3024 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3025 {
3026         struct bnxt *bp = dev->data->dev_private;
3027         int rc;
3028
3029         rc = is_bnxt_in_error(bp);
3030         if (rc)
3031                 return rc;
3032
3033         return bnxt_hwrm_port_led_cfg(bp, false);
3034 }
3035
3036 static uint32_t
3037 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3038 {
3039         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3040         struct bnxt_cp_ring_info *cpr;
3041         uint32_t desc = 0, raw_cons;
3042         struct bnxt_rx_queue *rxq;
3043         struct rx_pkt_cmpl *rxcmp;
3044         int rc;
3045
3046         rc = is_bnxt_in_error(bp);
3047         if (rc)
3048                 return rc;
3049
3050         rxq = dev->data->rx_queues[rx_queue_id];
3051         cpr = rxq->cp_ring;
3052         raw_cons = cpr->cp_raw_cons;
3053
3054         while (1) {
3055                 uint32_t agg_cnt, cons, cmpl_type;
3056
3057                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3058                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3059
3060                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3061                         break;
3062
3063                 cmpl_type = CMP_TYPE(rxcmp);
3064
3065                 switch (cmpl_type) {
3066                 case CMPL_BASE_TYPE_RX_L2:
3067                 case CMPL_BASE_TYPE_RX_L2_V2:
3068                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3069                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3070                         desc++;
3071                         break;
3072
3073                 case CMPL_BASE_TYPE_RX_TPA_END:
3074                         if (BNXT_CHIP_P5(rxq->bp)) {
3075                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3076
3077                                 p5_tpa_end = (void *)rxcmp;
3078                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3079                         } else {
3080                                 struct rx_tpa_end_cmpl *tpa_end;
3081
3082                                 tpa_end = (void *)rxcmp;
3083                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3084                         }
3085
3086                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3087                         desc++;
3088                         break;
3089
3090                 default:
3091                         raw_cons += CMP_LEN(cmpl_type);
3092                 }
3093         }
3094
3095         return desc;
3096 }
3097
3098 static int
3099 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3100 {
3101         struct bnxt_rx_queue *rxq = rx_queue;
3102         struct bnxt_cp_ring_info *cpr;
3103         struct bnxt_rx_ring_info *rxr;
3104         uint32_t desc, raw_cons;
3105         struct bnxt *bp = rxq->bp;
3106         struct rx_pkt_cmpl *rxcmp;
3107         int rc;
3108
3109         rc = is_bnxt_in_error(bp);
3110         if (rc)
3111                 return rc;
3112
3113         if (offset >= rxq->nb_rx_desc)
3114                 return -EINVAL;
3115
3116         rxr = rxq->rx_ring;
3117         cpr = rxq->cp_ring;
3118
3119         /*
3120          * For the vector receive case, the completion at the requested
3121          * offset can be indexed directly.
3122          */
3123 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3124         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3125                 struct rx_pkt_cmpl *rxcmp;
3126                 uint32_t cons;
3127
3128                 /* Check status of completion descriptor. */
3129                 raw_cons = cpr->cp_raw_cons +
3130                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3131                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3132                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3133
3134                 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3135                         return RTE_ETH_RX_DESC_DONE;
3136
3137                 /* Check whether rx desc has an mbuf attached. */
3138                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3139                 if (cons >= rxq->rxrearm_start &&
3140                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3141                         return RTE_ETH_RX_DESC_UNAVAIL;
3142                 }
3143
3144                 return RTE_ETH_RX_DESC_AVAIL;
3145         }
3146 #endif
3147
3148         /*
3149          * For the non-vector receive case, scan the completion ring to
3150          * locate the completion descriptor for the requested offset.
3151          */
3152         raw_cons = cpr->cp_raw_cons;
3153         desc = 0;
3154         while (1) {
3155                 uint32_t agg_cnt, cons, cmpl_type;
3156
3157                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3158                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3159
3160                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3161                         break;
3162
3163                 cmpl_type = CMP_TYPE(rxcmp);
3164
3165                 switch (cmpl_type) {
3166                 case CMPL_BASE_TYPE_RX_L2:
3167                 case CMPL_BASE_TYPE_RX_L2_V2:
3168                         if (desc == offset) {
3169                                 cons = rxcmp->opaque;
3170                                 if (rxr->rx_buf_ring[cons])
3171                                         return RTE_ETH_RX_DESC_DONE;
3172                                 else
3173                                         return RTE_ETH_RX_DESC_UNAVAIL;
3174                         }
3175                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3176                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3177                         desc++;
3178                         break;
3179
3180                 case CMPL_BASE_TYPE_RX_TPA_END:
3181                         if (desc == offset)
3182                                 return RTE_ETH_RX_DESC_DONE;
3183
3184                         if (BNXT_CHIP_P5(rxq->bp)) {
3185                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3186
3187                                 p5_tpa_end = (void *)rxcmp;
3188                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3189                         } else {
3190                                 struct rx_tpa_end_cmpl *tpa_end;
3191
3192                                 tpa_end = (void *)rxcmp;
3193                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3194                         }
3195
3196                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3197                         desc++;
3198                         break;
3199
3200                 default:
3201                         raw_cons += CMP_LEN(cmpl_type);
3202                 }
3203         }
3204
3205         return RTE_ETH_RX_DESC_AVAIL;
3206 }
3207
3208 static int
3209 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3210 {
3211         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3212         struct bnxt_tx_ring_info *txr;
3213         struct bnxt_cp_ring_info *cpr;
3214         struct rte_mbuf **tx_buf;
3215         struct tx_pkt_cmpl *txcmp;
3216         uint32_t cons, cp_cons;
3217         int rc;
3218
3219         if (!txq)
3220                 return -EINVAL;
3221
3222         rc = is_bnxt_in_error(txq->bp);
3223         if (rc)
3224                 return rc;
3225
3226         cpr = txq->cp_ring;
3227         txr = txq->tx_ring;
3228
3229         if (offset >= txq->nb_tx_desc)
3230                 return -EINVAL;
3231
3232         cons = RING_CMP(cpr->cp_ring_struct, offset);
3233         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3234         cp_cons = cpr->cp_raw_cons;
3235
3236         if (cons > cp_cons) {
3237                 if (CMPL_VALID(txcmp, cpr->valid))
3238                         return RTE_ETH_TX_DESC_UNAVAIL;
3239         } else {
3240                 if (CMPL_VALID(txcmp, !cpr->valid))
3241                         return RTE_ETH_TX_DESC_UNAVAIL;
3242         }
3243         tx_buf = &txr->tx_buf_ring[cons];
3244         if (*tx_buf == NULL)
3245                 return RTE_ETH_TX_DESC_DONE;
3246
3247         return RTE_ETH_TX_DESC_FULL;
3248 }
3249
3250 int
3251 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3252                      const struct rte_flow_ops **ops)
3253 {
3254         struct bnxt *bp = dev->data->dev_private;
3255         int ret = 0;
3256
3257         if (!bp)
3258                 return -EIO;
3259
3260         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3261                 struct bnxt_representor *vfr = dev->data->dev_private;
3262                 bp = vfr->parent_dev->data->dev_private;
3263                 /* parent is deleted while children are still valid */
3264                 if (!bp) {
3265                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3266                                     dev->data->port_id);
3267                         return -EIO;
3268                 }
3269         }
3270
3271         ret = is_bnxt_in_error(bp);
3272         if (ret)
3273                 return ret;
3274
3275         /* PMD supports thread-safe flow operations.  rte_flow API
3276          * functions can avoid mutex for multi-thread safety.
3277          */
3278         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3279
3280         if (BNXT_TRUFLOW_EN(bp))
3281                 *ops = &bnxt_ulp_rte_flow_ops;
3282         else
3283                 *ops = &bnxt_flow_ops;
3284
3285         return ret;
3286 }
3287
3288 static const uint32_t *
3289 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3290 {
3291         static const uint32_t ptypes[] = {
3292                 RTE_PTYPE_L2_ETHER_VLAN,
3293                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3294                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3295                 RTE_PTYPE_L4_ICMP,
3296                 RTE_PTYPE_L4_TCP,
3297                 RTE_PTYPE_L4_UDP,
3298                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3299                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3300                 RTE_PTYPE_INNER_L4_ICMP,
3301                 RTE_PTYPE_INNER_L4_TCP,
3302                 RTE_PTYPE_INNER_L4_UDP,
3303                 RTE_PTYPE_UNKNOWN
3304         };
3305
3306         if (!dev->rx_pkt_burst)
3307                 return NULL;
3308
3309         return ptypes;
3310 }
3311
3312 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3313                          int reg_win)
3314 {
3315         uint32_t reg_base = *reg_arr & 0xfffff000;
3316         uint32_t win_off;
3317         int i;
3318
3319         for (i = 0; i < count; i++) {
3320                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3321                         return -ERANGE;
3322         }
3323         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3324         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3325         return 0;
3326 }
3327
3328 static int bnxt_map_ptp_regs(struct bnxt *bp)
3329 {
3330         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3331         uint32_t *reg_arr;
3332         int rc, i;
3333
3334         reg_arr = ptp->rx_regs;
3335         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3336         if (rc)
3337                 return rc;
3338
3339         reg_arr = ptp->tx_regs;
3340         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3341         if (rc)
3342                 return rc;
3343
3344         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3345                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3346
3347         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3348                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3349
3350         return 0;
3351 }
3352
3353 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3354 {
3355         rte_write32(0, (uint8_t *)bp->bar0 +
3356                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3357         rte_write32(0, (uint8_t *)bp->bar0 +
3358                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3359 }
3360
3361 static uint64_t bnxt_cc_read(struct bnxt *bp)
3362 {
3363         uint64_t ns;
3364
3365         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3366                               BNXT_GRCPF_REG_SYNC_TIME));
3367         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3368                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3369         return ns;
3370 }
3371
3372 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3373 {
3374         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3375         uint32_t fifo;
3376
3377         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3378                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3379         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3380                 return -EAGAIN;
3381
3382         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3383                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3384         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3385                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3386         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3387                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3388         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3389
3390         return 0;
3391 }
3392
3393 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3394 {
3395         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3396         struct bnxt_pf_info *pf = bp->pf;
3397         uint16_t port_id;
3398         int i = 0;
3399         uint32_t fifo;
3400
3401         if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3402                 return -EINVAL;
3403
3404         port_id = pf->port_id;
3405         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3406                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3407         while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3408                 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3409                             ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3410                 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3411                                         ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3412                 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3413                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3414                 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3415                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3416                 i++;
3417         }
3418
3419         if (i >= BNXT_PTP_RX_PND_CNT)
3420                 return -EBUSY;
3421
3422         return 0;
3423 }
3424
3425 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3426 {
3427         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3428         struct bnxt_pf_info *pf = bp->pf;
3429         uint16_t port_id;
3430         uint32_t fifo;
3431
3432         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3433                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3434         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3435                 return -EAGAIN;
3436
3437         port_id = pf->port_id;
3438         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3439                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3440
3441         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3442                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3443         if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3444                 return bnxt_clr_rx_ts(bp, ts);
3445
3446         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3447                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3448         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3449                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3450
3451         return 0;
3452 }
3453
3454 static int
3455 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3456 {
3457         uint64_t ns;
3458         struct bnxt *bp = dev->data->dev_private;
3459         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3460
3461         if (!ptp)
3462                 return -ENOTSUP;
3463
3464         ns = rte_timespec_to_ns(ts);
3465         /* Set the timecounters to a new value. */
3466         ptp->tc.nsec = ns;
3467         ptp->tx_tstamp_tc.nsec = ns;
3468         ptp->rx_tstamp_tc.nsec = ns;
3469
3470         return 0;
3471 }
3472
3473 static int
3474 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3475 {
3476         struct bnxt *bp = dev->data->dev_private;
3477         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3478         uint64_t ns, systime_cycles = 0;
3479         int rc = 0;
3480
3481         if (!ptp)
3482                 return -ENOTSUP;
3483
3484         if (BNXT_CHIP_P5(bp))
3485                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3486                                              &systime_cycles);
3487         else
3488                 systime_cycles = bnxt_cc_read(bp);
3489
3490         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3491         *ts = rte_ns_to_timespec(ns);
3492
3493         return rc;
3494 }
3495 static int
3496 bnxt_timesync_enable(struct rte_eth_dev *dev)
3497 {
3498         struct bnxt *bp = dev->data->dev_private;
3499         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3500         uint32_t shift = 0;
3501         int rc;
3502
3503         if (!ptp)
3504                 return -ENOTSUP;
3505
3506         ptp->rx_filter = 1;
3507         ptp->tx_tstamp_en = 1;
3508         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3509
3510         rc = bnxt_hwrm_ptp_cfg(bp);
3511         if (rc)
3512                 return rc;
3513
3514         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3515         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3516         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3517
3518         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3519         ptp->tc.cc_shift = shift;
3520         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3521
3522         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3523         ptp->rx_tstamp_tc.cc_shift = shift;
3524         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3525
3526         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3527         ptp->tx_tstamp_tc.cc_shift = shift;
3528         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3529
3530         if (!BNXT_CHIP_P5(bp))
3531                 bnxt_map_ptp_regs(bp);
3532         else
3533                 rc = bnxt_ptp_start(bp);
3534
3535         return rc;
3536 }
3537
3538 static int
3539 bnxt_timesync_disable(struct rte_eth_dev *dev)
3540 {
3541         struct bnxt *bp = dev->data->dev_private;
3542         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3543
3544         if (!ptp)
3545                 return -ENOTSUP;
3546
3547         ptp->rx_filter = 0;
3548         ptp->tx_tstamp_en = 0;
3549         ptp->rxctl = 0;
3550
3551         bnxt_hwrm_ptp_cfg(bp);
3552
3553         if (!BNXT_CHIP_P5(bp))
3554                 bnxt_unmap_ptp_regs(bp);
3555         else
3556                 bnxt_ptp_stop(bp);
3557
3558         return 0;
3559 }
3560
3561 static int
3562 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3563                                  struct timespec *timestamp,
3564                                  uint32_t flags __rte_unused)
3565 {
3566         struct bnxt *bp = dev->data->dev_private;
3567         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3568         uint64_t rx_tstamp_cycles = 0;
3569         uint64_t ns;
3570
3571         if (!ptp)
3572                 return -ENOTSUP;
3573
3574         if (BNXT_CHIP_P5(bp))
3575                 rx_tstamp_cycles = ptp->rx_timestamp;
3576         else
3577                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3578
3579         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3580         *timestamp = rte_ns_to_timespec(ns);
3581         return  0;
3582 }
3583
3584 static int
3585 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3586                                  struct timespec *timestamp)
3587 {
3588         struct bnxt *bp = dev->data->dev_private;
3589         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3590         uint64_t tx_tstamp_cycles = 0;
3591         uint64_t ns;
3592         int rc = 0;
3593
3594         if (!ptp)
3595                 return -ENOTSUP;
3596
3597         if (BNXT_CHIP_P5(bp))
3598                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3599                                              &tx_tstamp_cycles);
3600         else
3601                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3602
3603         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3604         *timestamp = rte_ns_to_timespec(ns);
3605
3606         return rc;
3607 }
3608
3609 static int
3610 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3611 {
3612         struct bnxt *bp = dev->data->dev_private;
3613         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3614
3615         if (!ptp)
3616                 return -ENOTSUP;
3617
3618         ptp->tc.nsec += delta;
3619         ptp->tx_tstamp_tc.nsec += delta;
3620         ptp->rx_tstamp_tc.nsec += delta;
3621
3622         return 0;
3623 }
3624
3625 static int
3626 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3627 {
3628         struct bnxt *bp = dev->data->dev_private;
3629         int rc;
3630         uint32_t dir_entries;
3631         uint32_t entry_length;
3632
3633         rc = is_bnxt_in_error(bp);
3634         if (rc)
3635                 return rc;
3636
3637         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3638                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3639                     bp->pdev->addr.devid, bp->pdev->addr.function);
3640
3641         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3642         if (rc != 0)
3643                 return rc;
3644
3645         return dir_entries * entry_length;
3646 }
3647
3648 static int
3649 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3650                 struct rte_dev_eeprom_info *in_eeprom)
3651 {
3652         struct bnxt *bp = dev->data->dev_private;
3653         uint32_t index;
3654         uint32_t offset;
3655         int rc;
3656
3657         rc = is_bnxt_in_error(bp);
3658         if (rc)
3659                 return rc;
3660
3661         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3662                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3663                     bp->pdev->addr.devid, bp->pdev->addr.function,
3664                     in_eeprom->offset, in_eeprom->length);
3665
3666         if (in_eeprom->offset == 0) /* special offset value to get directory */
3667                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3668                                                 in_eeprom->data);
3669
3670         index = in_eeprom->offset >> 24;
3671         offset = in_eeprom->offset & 0xffffff;
3672
3673         if (index != 0)
3674                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3675                                            in_eeprom->length, in_eeprom->data);
3676
3677         return 0;
3678 }
3679
3680 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3681 {
3682         switch (dir_type) {
3683         case BNX_DIR_TYPE_CHIMP_PATCH:
3684         case BNX_DIR_TYPE_BOOTCODE:
3685         case BNX_DIR_TYPE_BOOTCODE_2:
3686         case BNX_DIR_TYPE_APE_FW:
3687         case BNX_DIR_TYPE_APE_PATCH:
3688         case BNX_DIR_TYPE_KONG_FW:
3689         case BNX_DIR_TYPE_KONG_PATCH:
3690         case BNX_DIR_TYPE_BONO_FW:
3691         case BNX_DIR_TYPE_BONO_PATCH:
3692                 /* FALLTHROUGH */
3693                 return true;
3694         }
3695
3696         return false;
3697 }
3698
3699 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3700 {
3701         switch (dir_type) {
3702         case BNX_DIR_TYPE_AVS:
3703         case BNX_DIR_TYPE_EXP_ROM_MBA:
3704         case BNX_DIR_TYPE_PCIE:
3705         case BNX_DIR_TYPE_TSCF_UCODE:
3706         case BNX_DIR_TYPE_EXT_PHY:
3707         case BNX_DIR_TYPE_CCM:
3708         case BNX_DIR_TYPE_ISCSI_BOOT:
3709         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3710         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3711                 /* FALLTHROUGH */
3712                 return true;
3713         }
3714
3715         return false;
3716 }
3717
3718 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3719 {
3720         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3721                 bnxt_dir_type_is_other_exec_format(dir_type);
3722 }
3723
3724 static int
3725 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3726                 struct rte_dev_eeprom_info *in_eeprom)
3727 {
3728         struct bnxt *bp = dev->data->dev_private;
3729         uint8_t index, dir_op;
3730         uint16_t type, ext, ordinal, attr;
3731         int rc;
3732
3733         rc = is_bnxt_in_error(bp);
3734         if (rc)
3735                 return rc;
3736
3737         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3738                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3739                     bp->pdev->addr.devid, bp->pdev->addr.function,
3740                     in_eeprom->offset, in_eeprom->length);
3741
3742         if (!BNXT_PF(bp)) {
3743                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3744                 return -EINVAL;
3745         }
3746
3747         type = in_eeprom->magic >> 16;
3748
3749         if (type == 0xffff) { /* special value for directory operations */
3750                 index = in_eeprom->magic & 0xff;
3751                 dir_op = in_eeprom->magic >> 8;
3752                 if (index == 0)
3753                         return -EINVAL;
3754                 switch (dir_op) {
3755                 case 0x0e: /* erase */
3756                         if (in_eeprom->offset != ~in_eeprom->magic)
3757                                 return -EINVAL;
3758                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3759                 default:
3760                         return -EINVAL;
3761                 }
3762         }
3763
3764         /* Create or re-write an NVM item: */
3765         if (bnxt_dir_type_is_executable(type) == true)
3766                 return -EOPNOTSUPP;
3767         ext = in_eeprom->magic & 0xffff;
3768         ordinal = in_eeprom->offset >> 16;
3769         attr = in_eeprom->offset & 0xffff;
3770
3771         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3772                                      in_eeprom->data, in_eeprom->length);
3773 }
3774
3775 /*
3776  * Initialization
3777  */
3778
3779 static const struct eth_dev_ops bnxt_dev_ops = {
3780         .dev_infos_get = bnxt_dev_info_get_op,
3781         .dev_close = bnxt_dev_close_op,
3782         .dev_configure = bnxt_dev_configure_op,
3783         .dev_start = bnxt_dev_start_op,
3784         .dev_stop = bnxt_dev_stop_op,
3785         .dev_set_link_up = bnxt_dev_set_link_up_op,
3786         .dev_set_link_down = bnxt_dev_set_link_down_op,
3787         .stats_get = bnxt_stats_get_op,
3788         .stats_reset = bnxt_stats_reset_op,
3789         .rx_queue_setup = bnxt_rx_queue_setup_op,
3790         .rx_queue_release = bnxt_rx_queue_release_op,
3791         .tx_queue_setup = bnxt_tx_queue_setup_op,
3792         .tx_queue_release = bnxt_tx_queue_release_op,
3793         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3794         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3795         .reta_update = bnxt_reta_update_op,
3796         .reta_query = bnxt_reta_query_op,
3797         .rss_hash_update = bnxt_rss_hash_update_op,
3798         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3799         .link_update = bnxt_link_update_op,
3800         .promiscuous_enable = bnxt_promiscuous_enable_op,
3801         .promiscuous_disable = bnxt_promiscuous_disable_op,
3802         .allmulticast_enable = bnxt_allmulticast_enable_op,
3803         .allmulticast_disable = bnxt_allmulticast_disable_op,
3804         .mac_addr_add = bnxt_mac_addr_add_op,
3805         .mac_addr_remove = bnxt_mac_addr_remove_op,
3806         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3807         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3808         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3809         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3810         .vlan_filter_set = bnxt_vlan_filter_set_op,
3811         .vlan_offload_set = bnxt_vlan_offload_set_op,
3812         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3813         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3814         .mtu_set = bnxt_mtu_set_op,
3815         .mac_addr_set = bnxt_set_default_mac_addr_op,
3816         .xstats_get = bnxt_dev_xstats_get_op,
3817         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3818         .xstats_reset = bnxt_dev_xstats_reset_op,
3819         .fw_version_get = bnxt_fw_version_get,
3820         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3821         .rxq_info_get = bnxt_rxq_info_get_op,
3822         .txq_info_get = bnxt_txq_info_get_op,
3823         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3824         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3825         .dev_led_on = bnxt_dev_led_on_op,
3826         .dev_led_off = bnxt_dev_led_off_op,
3827         .rx_queue_start = bnxt_rx_queue_start,
3828         .rx_queue_stop = bnxt_rx_queue_stop,
3829         .tx_queue_start = bnxt_tx_queue_start,
3830         .tx_queue_stop = bnxt_tx_queue_stop,
3831         .flow_ops_get = bnxt_flow_ops_get_op,
3832         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3833         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3834         .get_eeprom           = bnxt_get_eeprom_op,
3835         .set_eeprom           = bnxt_set_eeprom_op,
3836         .timesync_enable      = bnxt_timesync_enable,
3837         .timesync_disable     = bnxt_timesync_disable,
3838         .timesync_read_time   = bnxt_timesync_read_time,
3839         .timesync_write_time   = bnxt_timesync_write_time,
3840         .timesync_adjust_time = bnxt_timesync_adjust_time,
3841         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3842         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3843 };
3844
3845 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3846 {
3847         uint32_t offset;
3848
3849         /* Only pre-map the reset GRC registers using window 3 */
3850         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3851                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3852
3853         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3854
3855         return offset;
3856 }
3857
3858 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3859 {
3860         struct bnxt_error_recovery_info *info = bp->recovery_info;
3861         uint32_t reg_base = 0xffffffff;
3862         int i;
3863
3864         /* Only pre-map the monitoring GRC registers using window 2 */
3865         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3866                 uint32_t reg = info->status_regs[i];
3867
3868                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3869                         continue;
3870
3871                 if (reg_base == 0xffffffff)
3872                         reg_base = reg & 0xfffff000;
3873                 if ((reg & 0xfffff000) != reg_base)
3874                         return -ERANGE;
3875
3876                 /* Use mask 0xffc as the Lower 2 bits indicates
3877                  * address space location
3878                  */
3879                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3880                                                 (reg & 0xffc);
3881         }
3882
3883         if (reg_base == 0xffffffff)
3884                 return 0;
3885
3886         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3887                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3888
3889         return 0;
3890 }
3891
3892 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3893 {
3894         struct bnxt_error_recovery_info *info = bp->recovery_info;
3895         uint32_t delay = info->delay_after_reset[index];
3896         uint32_t val = info->reset_reg_val[index];
3897         uint32_t reg = info->reset_reg[index];
3898         uint32_t type, offset;
3899         int ret;
3900
3901         type = BNXT_FW_STATUS_REG_TYPE(reg);
3902         offset = BNXT_FW_STATUS_REG_OFF(reg);
3903
3904         switch (type) {
3905         case BNXT_FW_STATUS_REG_TYPE_CFG:
3906                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3907                 if (ret < 0) {
3908                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
3909                                     val, offset);
3910                         return;
3911                 }
3912                 break;
3913         case BNXT_FW_STATUS_REG_TYPE_GRC:
3914                 offset = bnxt_map_reset_regs(bp, offset);
3915                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3916                 break;
3917         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3918                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3919                 break;
3920         }
3921         /* wait on a specific interval of time until core reset is complete */
3922         if (delay)
3923                 rte_delay_ms(delay);
3924 }
3925
3926 static void bnxt_dev_cleanup(struct bnxt *bp)
3927 {
3928         bp->eth_dev->data->dev_link.link_status = 0;
3929         bp->link_info->link_up = 0;
3930         if (bp->eth_dev->data->dev_started)
3931                 bnxt_dev_stop(bp->eth_dev);
3932
3933         bnxt_uninit_resources(bp, true);
3934 }
3935
3936 static int
3937 bnxt_check_fw_reset_done(struct bnxt *bp)
3938 {
3939         int timeout = bp->fw_reset_max_msecs;
3940         uint16_t val = 0;
3941         int rc;
3942
3943         do {
3944                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
3945                 if (rc < 0) {
3946                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
3947                         return rc;
3948                 }
3949                 if (val != 0xffff)
3950                         break;
3951                 rte_delay_ms(1);
3952         } while (timeout--);
3953
3954         if (val == 0xffff) {
3955                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
3956                 return -1;
3957         }
3958
3959         return 0;
3960 }
3961
3962 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3963 {
3964         struct rte_eth_dev *dev = bp->eth_dev;
3965         struct rte_vlan_filter_conf *vfc;
3966         int vidx, vbit, rc;
3967         uint16_t vlan_id;
3968
3969         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3970                 vfc = &dev->data->vlan_filter_conf;
3971                 vidx = vlan_id / 64;
3972                 vbit = vlan_id % 64;
3973
3974                 /* Each bit corresponds to a VLAN id */
3975                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3976                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3977                         if (rc)
3978                                 return rc;
3979                 }
3980         }
3981
3982         return 0;
3983 }
3984
3985 static int bnxt_restore_mac_filters(struct bnxt *bp)
3986 {
3987         struct rte_eth_dev *dev = bp->eth_dev;
3988         struct rte_eth_dev_info dev_info;
3989         struct rte_ether_addr *addr;
3990         uint64_t pool_mask;
3991         uint32_t pool = 0;
3992         uint32_t i;
3993         int rc;
3994
3995         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3996                 return 0;
3997
3998         rc = bnxt_dev_info_get_op(dev, &dev_info);
3999         if (rc)
4000                 return rc;
4001
4002         /* replay MAC address configuration */
4003         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4004                 addr = &dev->data->mac_addrs[i];
4005
4006                 /* skip zero address */
4007                 if (rte_is_zero_ether_addr(addr))
4008                         continue;
4009
4010                 pool = 0;
4011                 pool_mask = dev->data->mac_pool_sel[i];
4012
4013                 do {
4014                         if (pool_mask & 1ULL) {
4015                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4016                                 if (rc)
4017                                         return rc;
4018                         }
4019                         pool_mask >>= 1;
4020                         pool++;
4021                 } while (pool_mask);
4022         }
4023
4024         return 0;
4025 }
4026
4027 static int bnxt_restore_filters(struct bnxt *bp)
4028 {
4029         struct rte_eth_dev *dev = bp->eth_dev;
4030         int ret = 0;
4031
4032         if (dev->data->all_multicast) {
4033                 ret = bnxt_allmulticast_enable_op(dev);
4034                 if (ret)
4035                         return ret;
4036         }
4037         if (dev->data->promiscuous) {
4038                 ret = bnxt_promiscuous_enable_op(dev);
4039                 if (ret)
4040                         return ret;
4041         }
4042
4043         ret = bnxt_restore_mac_filters(bp);
4044         if (ret)
4045                 return ret;
4046
4047         ret = bnxt_restore_vlan_filters(bp);
4048         /* TODO restore other filters as well */
4049         return ret;
4050 }
4051
4052 static int bnxt_check_fw_ready(struct bnxt *bp)
4053 {
4054         int timeout = bp->fw_reset_max_msecs;
4055         int rc = 0;
4056
4057         do {
4058                 rc = bnxt_hwrm_poll_ver_get(bp);
4059                 if (rc == 0)
4060                         break;
4061                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4062                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4063         } while (rc && timeout > 0);
4064
4065         if (rc)
4066                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4067
4068         return rc;
4069 }
4070
4071 static void bnxt_dev_recover(void *arg)
4072 {
4073         struct bnxt *bp = arg;
4074         int rc = 0;
4075
4076         pthread_mutex_lock(&bp->err_recovery_lock);
4077
4078         if (!bp->fw_reset_min_msecs) {
4079                 rc = bnxt_check_fw_reset_done(bp);
4080                 if (rc)
4081                         goto err;
4082         }
4083
4084         /* Clear Error flag so that device re-init should happen */
4085         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4086
4087         rc = bnxt_check_fw_ready(bp);
4088         if (rc)
4089                 goto err;
4090
4091         rc = bnxt_init_resources(bp, true);
4092         if (rc) {
4093                 PMD_DRV_LOG(ERR,
4094                             "Failed to initialize resources after reset\n");
4095                 goto err;
4096         }
4097         /* clear reset flag as the device is initialized now */
4098         bp->flags &= ~BNXT_FLAG_FW_RESET;
4099
4100         rc = bnxt_dev_start_op(bp->eth_dev);
4101         if (rc) {
4102                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4103                 goto err_start;
4104         }
4105
4106         rc = bnxt_restore_filters(bp);
4107         if (rc)
4108                 goto err_start;
4109
4110         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4111         pthread_mutex_unlock(&bp->err_recovery_lock);
4112
4113         return;
4114 err_start:
4115         bnxt_dev_stop(bp->eth_dev);
4116 err:
4117         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4118         bnxt_uninit_resources(bp, false);
4119         pthread_mutex_unlock(&bp->err_recovery_lock);
4120         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4121 }
4122
4123 void bnxt_dev_reset_and_resume(void *arg)
4124 {
4125         struct bnxt *bp = arg;
4126         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4127         uint16_t val = 0;
4128         int rc;
4129
4130         bnxt_dev_cleanup(bp);
4131
4132         bnxt_wait_for_device_shutdown(bp);
4133
4134         /* During some fatal firmware error conditions, the PCI config space
4135          * register 0x2e which normally contains the subsystem ID will become
4136          * 0xffff. This register will revert back to the normal value after
4137          * the chip has completed core reset. If we detect this condition,
4138          * we can poll this config register immediately for the value to revert.
4139          */
4140         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4141                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4142                 if (rc < 0) {
4143                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4144                         return;
4145                 }
4146                 if (val == 0xffff) {
4147                         bp->fw_reset_min_msecs = 0;
4148                         us = 1;
4149                 }
4150         }
4151
4152         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4153         if (rc)
4154                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4155 }
4156
4157 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4158 {
4159         struct bnxt_error_recovery_info *info = bp->recovery_info;
4160         uint32_t reg = info->status_regs[index];
4161         uint32_t type, offset, val = 0;
4162         int ret = 0;
4163
4164         type = BNXT_FW_STATUS_REG_TYPE(reg);
4165         offset = BNXT_FW_STATUS_REG_OFF(reg);
4166
4167         switch (type) {
4168         case BNXT_FW_STATUS_REG_TYPE_CFG:
4169                 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4170                 if (ret < 0)
4171                         PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4172                                     offset);
4173                 break;
4174         case BNXT_FW_STATUS_REG_TYPE_GRC:
4175                 offset = info->mapped_status_regs[index];
4176                 /* FALLTHROUGH */
4177         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4178                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4179                                        offset));
4180                 break;
4181         }
4182
4183         return val;
4184 }
4185
4186 static int bnxt_fw_reset_all(struct bnxt *bp)
4187 {
4188         struct bnxt_error_recovery_info *info = bp->recovery_info;
4189         uint32_t i;
4190         int rc = 0;
4191
4192         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4193                 /* Reset through master function driver */
4194                 for (i = 0; i < info->reg_array_cnt; i++)
4195                         bnxt_write_fw_reset_reg(bp, i);
4196                 /* Wait for time specified by FW after triggering reset */
4197                 rte_delay_ms(info->master_func_wait_period_after_reset);
4198         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4199                 /* Reset with the help of Kong processor */
4200                 rc = bnxt_hwrm_fw_reset(bp);
4201                 if (rc)
4202                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4203         }
4204
4205         return rc;
4206 }
4207
4208 static void bnxt_fw_reset_cb(void *arg)
4209 {
4210         struct bnxt *bp = arg;
4211         struct bnxt_error_recovery_info *info = bp->recovery_info;
4212         int rc = 0;
4213
4214         /* Only Master function can do FW reset */
4215         if (bnxt_is_master_func(bp) &&
4216             bnxt_is_recovery_enabled(bp)) {
4217                 rc = bnxt_fw_reset_all(bp);
4218                 if (rc) {
4219                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4220                         return;
4221                 }
4222         }
4223
4224         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4225          * EXCEPTION_FATAL_ASYNC event to all the functions
4226          * (including MASTER FUNC). After receiving this Async, all the active
4227          * drivers should treat this case as FW initiated recovery
4228          */
4229         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4230                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4231                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4232
4233                 /* To recover from error */
4234                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4235                                   (void *)bp);
4236         }
4237 }
4238
4239 /* Driver should poll FW heartbeat, reset_counter with the frequency
4240  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4241  * When the driver detects heartbeat stop or change in reset_counter,
4242  * it has to trigger a reset to recover from the error condition.
4243  * A “master PF” is the function who will have the privilege to
4244  * initiate the chimp reset. The master PF will be elected by the
4245  * firmware and will be notified through async message.
4246  */
4247 static void bnxt_check_fw_health(void *arg)
4248 {
4249         struct bnxt *bp = arg;
4250         struct bnxt_error_recovery_info *info = bp->recovery_info;
4251         uint32_t val = 0, wait_msec;
4252
4253         if (!info || !bnxt_is_recovery_enabled(bp) ||
4254             is_bnxt_in_error(bp))
4255                 return;
4256
4257         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4258         if (val == info->last_heart_beat)
4259                 goto reset;
4260
4261         info->last_heart_beat = val;
4262
4263         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4264         if (val != info->last_reset_counter)
4265                 goto reset;
4266
4267         info->last_reset_counter = val;
4268
4269         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4270                           bnxt_check_fw_health, (void *)bp);
4271
4272         return;
4273 reset:
4274         /* Stop DMA to/from device */
4275         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4276         bp->flags |= BNXT_FLAG_FW_RESET;
4277
4278         bnxt_stop_rxtx(bp);
4279
4280         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4281
4282         if (bnxt_is_master_func(bp))
4283                 wait_msec = info->master_func_wait_period;
4284         else
4285                 wait_msec = info->normal_func_wait_period;
4286
4287         rte_eal_alarm_set(US_PER_MS * wait_msec,
4288                           bnxt_fw_reset_cb, (void *)bp);
4289 }
4290
4291 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4292 {
4293         uint32_t polling_freq;
4294
4295         pthread_mutex_lock(&bp->health_check_lock);
4296
4297         if (!bnxt_is_recovery_enabled(bp))
4298                 goto done;
4299
4300         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4301                 goto done;
4302
4303         polling_freq = bp->recovery_info->driver_polling_freq;
4304
4305         rte_eal_alarm_set(US_PER_MS * polling_freq,
4306                           bnxt_check_fw_health, (void *)bp);
4307         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4308
4309 done:
4310         pthread_mutex_unlock(&bp->health_check_lock);
4311 }
4312
4313 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4314 {
4315         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4316         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4317 }
4318
4319 static bool bnxt_vf_pciid(uint16_t device_id)
4320 {
4321         switch (device_id) {
4322         case BROADCOM_DEV_ID_57304_VF:
4323         case BROADCOM_DEV_ID_57406_VF:
4324         case BROADCOM_DEV_ID_5731X_VF:
4325         case BROADCOM_DEV_ID_5741X_VF:
4326         case BROADCOM_DEV_ID_57414_VF:
4327         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4328         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4329         case BROADCOM_DEV_ID_58802_VF:
4330         case BROADCOM_DEV_ID_57500_VF1:
4331         case BROADCOM_DEV_ID_57500_VF2:
4332         case BROADCOM_DEV_ID_58818_VF:
4333                 /* FALLTHROUGH */
4334                 return true;
4335         default:
4336                 return false;
4337         }
4338 }
4339
4340 /* Phase 5 device */
4341 static bool bnxt_p5_device(uint16_t device_id)
4342 {
4343         switch (device_id) {
4344         case BROADCOM_DEV_ID_57508:
4345         case BROADCOM_DEV_ID_57504:
4346         case BROADCOM_DEV_ID_57502:
4347         case BROADCOM_DEV_ID_57508_MF1:
4348         case BROADCOM_DEV_ID_57504_MF1:
4349         case BROADCOM_DEV_ID_57502_MF1:
4350         case BROADCOM_DEV_ID_57508_MF2:
4351         case BROADCOM_DEV_ID_57504_MF2:
4352         case BROADCOM_DEV_ID_57502_MF2:
4353         case BROADCOM_DEV_ID_57500_VF1:
4354         case BROADCOM_DEV_ID_57500_VF2:
4355         case BROADCOM_DEV_ID_58812:
4356         case BROADCOM_DEV_ID_58814:
4357         case BROADCOM_DEV_ID_58818:
4358         case BROADCOM_DEV_ID_58818_VF:
4359                 /* FALLTHROUGH */
4360                 return true;
4361         default:
4362                 return false;
4363         }
4364 }
4365
4366 bool bnxt_stratus_device(struct bnxt *bp)
4367 {
4368         uint16_t device_id = bp->pdev->id.device_id;
4369
4370         switch (device_id) {
4371         case BROADCOM_DEV_ID_STRATUS_NIC:
4372         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4373         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4374                 /* FALLTHROUGH */
4375                 return true;
4376         default:
4377                 return false;
4378         }
4379 }
4380
4381 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4382 {
4383         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4384         struct bnxt *bp = eth_dev->data->dev_private;
4385
4386         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4387         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4388         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4389         if (!bp->bar0 || !bp->doorbell_base) {
4390                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4391                 return -ENODEV;
4392         }
4393
4394         bp->eth_dev = eth_dev;
4395         bp->pdev = pci_dev;
4396
4397         return 0;
4398 }
4399
4400 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4401                                   struct bnxt_ctx_pg_info *ctx_pg,
4402                                   uint32_t mem_size,
4403                                   const char *suffix,
4404                                   uint16_t idx)
4405 {
4406         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4407         const struct rte_memzone *mz = NULL;
4408         char mz_name[RTE_MEMZONE_NAMESIZE];
4409         rte_iova_t mz_phys_addr;
4410         uint64_t valid_bits = 0;
4411         uint32_t sz;
4412         int i;
4413
4414         if (!mem_size)
4415                 return 0;
4416
4417         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4418                          BNXT_PAGE_SIZE;
4419         rmem->page_size = BNXT_PAGE_SIZE;
4420         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4421         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4422         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4423
4424         valid_bits = PTU_PTE_VALID;
4425
4426         if (rmem->nr_pages > 1) {
4427                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4428                          "bnxt_ctx_pg_tbl%s_%x_%d",
4429                          suffix, idx, bp->eth_dev->data->port_id);
4430                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4431                 mz = rte_memzone_lookup(mz_name);
4432                 if (!mz) {
4433                         mz = rte_memzone_reserve_aligned(mz_name,
4434                                                 rmem->nr_pages * 8,
4435                                                 SOCKET_ID_ANY,
4436                                                 RTE_MEMZONE_2MB |
4437                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4438                                                 RTE_MEMZONE_IOVA_CONTIG,
4439                                                 BNXT_PAGE_SIZE);
4440                         if (mz == NULL)
4441                                 return -ENOMEM;
4442                 }
4443
4444                 memset(mz->addr, 0, mz->len);
4445                 mz_phys_addr = mz->iova;
4446
4447                 rmem->pg_tbl = mz->addr;
4448                 rmem->pg_tbl_map = mz_phys_addr;
4449                 rmem->pg_tbl_mz = mz;
4450         }
4451
4452         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4453                  suffix, idx, bp->eth_dev->data->port_id);
4454         mz = rte_memzone_lookup(mz_name);
4455         if (!mz) {
4456                 mz = rte_memzone_reserve_aligned(mz_name,
4457                                                  mem_size,
4458                                                  SOCKET_ID_ANY,
4459                                                  RTE_MEMZONE_1GB |
4460                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4461                                                  RTE_MEMZONE_IOVA_CONTIG,
4462                                                  BNXT_PAGE_SIZE);
4463                 if (mz == NULL)
4464                         return -ENOMEM;
4465         }
4466
4467         memset(mz->addr, 0, mz->len);
4468         mz_phys_addr = mz->iova;
4469
4470         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4471                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4472                 rmem->dma_arr[i] = mz_phys_addr + sz;
4473
4474                 if (rmem->nr_pages > 1) {
4475                         if (i == rmem->nr_pages - 2 &&
4476                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4477                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4478                         else if (i == rmem->nr_pages - 1 &&
4479                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4480                                 valid_bits |= PTU_PTE_LAST;
4481
4482                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4483                                                            valid_bits);
4484                 }
4485         }
4486
4487         rmem->mz = mz;
4488         if (rmem->vmem_size)
4489                 rmem->vmem = (void **)mz->addr;
4490         rmem->dma_arr[0] = mz_phys_addr;
4491         return 0;
4492 }
4493
4494 static void bnxt_free_ctx_mem(struct bnxt *bp)
4495 {
4496         int i;
4497
4498         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4499                 return;
4500
4501         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4502         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4503         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4504         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4505         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4506         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4507         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4508         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4509         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4510         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4511         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4512
4513         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4514                 if (bp->ctx->tqm_mem[i])
4515                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4516         }
4517
4518         rte_free(bp->ctx);
4519         bp->ctx = NULL;
4520 }
4521
4522 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4523
4524 #define min_t(type, x, y) ({                    \
4525         type __min1 = (x);                      \
4526         type __min2 = (y);                      \
4527         __min1 < __min2 ? __min1 : __min2; })
4528
4529 #define max_t(type, x, y) ({                    \
4530         type __max1 = (x);                      \
4531         type __max2 = (y);                      \
4532         __max1 > __max2 ? __max1 : __max2; })
4533
4534 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4535
4536 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4537 {
4538         struct bnxt_ctx_pg_info *ctx_pg;
4539         struct bnxt_ctx_mem_info *ctx;
4540         uint32_t mem_size, ena, entries;
4541         uint32_t entries_sp, min;
4542         int i, rc;
4543
4544         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4545         if (rc) {
4546                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4547                 return rc;
4548         }
4549         ctx = bp->ctx;
4550         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4551                 return 0;
4552
4553         ctx_pg = &ctx->qp_mem;
4554         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4555         if (ctx->qp_entry_size) {
4556                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4557                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4558                 if (rc)
4559                         return rc;
4560         }
4561
4562         ctx_pg = &ctx->srq_mem;
4563         ctx_pg->entries = ctx->srq_max_l2_entries;
4564         if (ctx->srq_entry_size) {
4565                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4566                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4567                 if (rc)
4568                         return rc;
4569         }
4570
4571         ctx_pg = &ctx->cq_mem;
4572         ctx_pg->entries = ctx->cq_max_l2_entries;
4573         if (ctx->cq_entry_size) {
4574                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4575                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4576                 if (rc)
4577                         return rc;
4578         }
4579
4580         ctx_pg = &ctx->vnic_mem;
4581         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4582                 ctx->vnic_max_ring_table_entries;
4583         if (ctx->vnic_entry_size) {
4584                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4585                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4586                 if (rc)
4587                         return rc;
4588         }
4589
4590         ctx_pg = &ctx->stat_mem;
4591         ctx_pg->entries = ctx->stat_max_entries;
4592         if (ctx->stat_entry_size) {
4593                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4594                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4595                 if (rc)
4596                         return rc;
4597         }
4598
4599         min = ctx->tqm_min_entries_per_ring;
4600
4601         entries_sp = ctx->qp_max_l2_entries +
4602                      ctx->vnic_max_vnic_entries +
4603                      2 * ctx->qp_min_qp1_entries + min;
4604         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4605
4606         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4607         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4608         entries = clamp_t(uint32_t, entries, min,
4609                           ctx->tqm_max_entries_per_ring);
4610         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4611                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4612                  * i > 8 is other ext rings.
4613                  */
4614                 ctx_pg = ctx->tqm_mem[i];
4615                 ctx_pg->entries = i ? entries : entries_sp;
4616                 if (ctx->tqm_entry_size) {
4617                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4618                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4619                                                     "tqm_mem", i);
4620                         if (rc)
4621                                 return rc;
4622                 }
4623                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4624                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4625                 else
4626                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4627         }
4628
4629         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4630         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4631         if (rc)
4632                 PMD_DRV_LOG(ERR,
4633                             "Failed to configure context mem: rc = %d\n", rc);
4634         else
4635                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4636
4637         return rc;
4638 }
4639
4640 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4641 {
4642         struct rte_pci_device *pci_dev = bp->pdev;
4643         char mz_name[RTE_MEMZONE_NAMESIZE];
4644         const struct rte_memzone *mz = NULL;
4645         uint32_t total_alloc_len;
4646         rte_iova_t mz_phys_addr;
4647
4648         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4649                 return 0;
4650
4651         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4652                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4653                  pci_dev->addr.bus, pci_dev->addr.devid,
4654                  pci_dev->addr.function, "rx_port_stats");
4655         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4656         mz = rte_memzone_lookup(mz_name);
4657         total_alloc_len =
4658                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4659                                        sizeof(struct rx_port_stats_ext) + 512);
4660         if (!mz) {
4661                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4662                                          SOCKET_ID_ANY,
4663                                          RTE_MEMZONE_2MB |
4664                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4665                                          RTE_MEMZONE_IOVA_CONTIG);
4666                 if (mz == NULL)
4667                         return -ENOMEM;
4668         }
4669         memset(mz->addr, 0, mz->len);
4670         mz_phys_addr = mz->iova;
4671
4672         bp->rx_mem_zone = (const void *)mz;
4673         bp->hw_rx_port_stats = mz->addr;
4674         bp->hw_rx_port_stats_map = mz_phys_addr;
4675
4676         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4677                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4678                  pci_dev->addr.bus, pci_dev->addr.devid,
4679                  pci_dev->addr.function, "tx_port_stats");
4680         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4681         mz = rte_memzone_lookup(mz_name);
4682         total_alloc_len =
4683                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4684                                        sizeof(struct tx_port_stats_ext) + 512);
4685         if (!mz) {
4686                 mz = rte_memzone_reserve(mz_name,
4687                                          total_alloc_len,
4688                                          SOCKET_ID_ANY,
4689                                          RTE_MEMZONE_2MB |
4690                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4691                                          RTE_MEMZONE_IOVA_CONTIG);
4692                 if (mz == NULL)
4693                         return -ENOMEM;
4694         }
4695         memset(mz->addr, 0, mz->len);
4696         mz_phys_addr = mz->iova;
4697
4698         bp->tx_mem_zone = (const void *)mz;
4699         bp->hw_tx_port_stats = mz->addr;
4700         bp->hw_tx_port_stats_map = mz_phys_addr;
4701         bp->flags |= BNXT_FLAG_PORT_STATS;
4702
4703         /* Display extended statistics if FW supports it */
4704         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4705             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4706             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4707                 return 0;
4708
4709         bp->hw_rx_port_stats_ext = (void *)
4710                 ((uint8_t *)bp->hw_rx_port_stats +
4711                  sizeof(struct rx_port_stats));
4712         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4713                 sizeof(struct rx_port_stats);
4714         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4715
4716         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4717             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4718                 bp->hw_tx_port_stats_ext = (void *)
4719                         ((uint8_t *)bp->hw_tx_port_stats +
4720                          sizeof(struct tx_port_stats));
4721                 bp->hw_tx_port_stats_ext_map =
4722                         bp->hw_tx_port_stats_map +
4723                         sizeof(struct tx_port_stats);
4724                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4725         }
4726
4727         return 0;
4728 }
4729
4730 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4731 {
4732         struct bnxt *bp = eth_dev->data->dev_private;
4733         int rc = 0;
4734
4735         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4736                                                RTE_ETHER_ADDR_LEN *
4737                                                bp->max_l2_ctx,
4738                                                0);
4739         if (eth_dev->data->mac_addrs == NULL) {
4740                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4741                 return -ENOMEM;
4742         }
4743
4744         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4745                 if (BNXT_PF(bp))
4746                         return -EINVAL;
4747
4748                 /* Generate a random MAC address, if none was assigned by PF */
4749                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4750                 bnxt_eth_hw_addr_random(bp->mac_addr);
4751                 PMD_DRV_LOG(INFO,
4752                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4753                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4754                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4755
4756                 rc = bnxt_hwrm_set_mac(bp);
4757                 if (rc)
4758                         return rc;
4759         }
4760
4761         /* Copy the permanent MAC from the FUNC_QCAPS response */
4762         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4763
4764         return rc;
4765 }
4766
4767 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4768 {
4769         int rc = 0;
4770
4771         /* MAC is already configured in FW */
4772         if (BNXT_HAS_DFLT_MAC_SET(bp))
4773                 return 0;
4774
4775         /* Restore the old MAC configured */
4776         rc = bnxt_hwrm_set_mac(bp);
4777         if (rc)
4778                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4779
4780         return rc;
4781 }
4782
4783 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4784 {
4785         if (!BNXT_PF(bp))
4786                 return;
4787
4788         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4789
4790         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4791                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4792         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4793         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4794         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4795         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4796 }
4797
4798 uint16_t
4799 bnxt_get_svif(uint16_t port_id, bool func_svif,
4800               enum bnxt_ulp_intf_type type)
4801 {
4802         struct rte_eth_dev *eth_dev;
4803         struct bnxt *bp;
4804
4805         eth_dev = &rte_eth_devices[port_id];
4806         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4807                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4808                 if (!vfr)
4809                         return 0;
4810
4811                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4812                         return vfr->svif;
4813
4814                 eth_dev = vfr->parent_dev;
4815         }
4816
4817         bp = eth_dev->data->dev_private;
4818
4819         return func_svif ? bp->func_svif : bp->port_svif;
4820 }
4821
4822 uint16_t
4823 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4824 {
4825         struct rte_eth_dev *eth_dev;
4826         struct bnxt_vnic_info *vnic;
4827         struct bnxt *bp;
4828
4829         eth_dev = &rte_eth_devices[port];
4830         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4831                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4832                 if (!vfr)
4833                         return 0;
4834
4835                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4836                         return vfr->dflt_vnic_id;
4837
4838                 eth_dev = vfr->parent_dev;
4839         }
4840
4841         bp = eth_dev->data->dev_private;
4842
4843         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4844
4845         return vnic->fw_vnic_id;
4846 }
4847
4848 uint16_t
4849 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4850 {
4851         struct rte_eth_dev *eth_dev;
4852         struct bnxt *bp;
4853
4854         eth_dev = &rte_eth_devices[port];
4855         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4856                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4857                 if (!vfr)
4858                         return 0;
4859
4860                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4861                         return vfr->fw_fid;
4862
4863                 eth_dev = vfr->parent_dev;
4864         }
4865
4866         bp = eth_dev->data->dev_private;
4867
4868         return bp->fw_fid;
4869 }
4870
4871 enum bnxt_ulp_intf_type
4872 bnxt_get_interface_type(uint16_t port)
4873 {
4874         struct rte_eth_dev *eth_dev;
4875         struct bnxt *bp;
4876
4877         eth_dev = &rte_eth_devices[port];
4878         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4879                 return BNXT_ULP_INTF_TYPE_VF_REP;
4880
4881         bp = eth_dev->data->dev_private;
4882         if (BNXT_PF(bp))
4883                 return BNXT_ULP_INTF_TYPE_PF;
4884         else if (BNXT_VF_IS_TRUSTED(bp))
4885                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4886         else if (BNXT_VF(bp))
4887                 return BNXT_ULP_INTF_TYPE_VF;
4888
4889         return BNXT_ULP_INTF_TYPE_INVALID;
4890 }
4891
4892 uint16_t
4893 bnxt_get_phy_port_id(uint16_t port_id)
4894 {
4895         struct bnxt_representor *vfr;
4896         struct rte_eth_dev *eth_dev;
4897         struct bnxt *bp;
4898
4899         eth_dev = &rte_eth_devices[port_id];
4900         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4901                 vfr = eth_dev->data->dev_private;
4902                 if (!vfr)
4903                         return 0;
4904
4905                 eth_dev = vfr->parent_dev;
4906         }
4907
4908         bp = eth_dev->data->dev_private;
4909
4910         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4911 }
4912
4913 uint16_t
4914 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4915 {
4916         struct rte_eth_dev *eth_dev;
4917         struct bnxt *bp;
4918
4919         eth_dev = &rte_eth_devices[port_id];
4920         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4921                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4922                 if (!vfr)
4923                         return 0;
4924
4925                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4926                         return vfr->fw_fid - 1;
4927
4928                 eth_dev = vfr->parent_dev;
4929         }
4930
4931         bp = eth_dev->data->dev_private;
4932
4933         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4934 }
4935
4936 uint16_t
4937 bnxt_get_vport(uint16_t port_id)
4938 {
4939         return (1 << bnxt_get_phy_port_id(port_id));
4940 }
4941
4942 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4943 {
4944         struct bnxt_error_recovery_info *info = bp->recovery_info;
4945
4946         if (info) {
4947                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4948                         memset(info, 0, sizeof(*info));
4949                 return;
4950         }
4951
4952         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4953                 return;
4954
4955         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4956                            sizeof(*info), 0);
4957         if (!info)
4958                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4959
4960         bp->recovery_info = info;
4961 }
4962
4963 static void bnxt_check_fw_status(struct bnxt *bp)
4964 {
4965         uint32_t fw_status;
4966
4967         if (!(bp->recovery_info &&
4968               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4969                 return;
4970
4971         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4972         if (fw_status != BNXT_FW_STATUS_HEALTHY)
4973                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4974                             fw_status);
4975 }
4976
4977 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4978 {
4979         struct bnxt_error_recovery_info *info = bp->recovery_info;
4980         uint32_t status_loc;
4981         uint32_t sig_ver;
4982
4983         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4984                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4985         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4986                                    BNXT_GRCP_WINDOW_2_BASE +
4987                                    offsetof(struct hcomm_status,
4988                                             sig_ver)));
4989         /* If the signature is absent, then FW does not support this feature */
4990         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4991             HCOMM_STATUS_SIGNATURE_VAL)
4992                 return 0;
4993
4994         if (!info) {
4995                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4996                                    sizeof(*info), 0);
4997                 if (!info)
4998                         return -ENOMEM;
4999                 bp->recovery_info = info;
5000         } else {
5001                 memset(info, 0, sizeof(*info));
5002         }
5003
5004         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5005                                       BNXT_GRCP_WINDOW_2_BASE +
5006                                       offsetof(struct hcomm_status,
5007                                                fw_status_loc)));
5008
5009         /* Only pre-map the FW health status GRC register */
5010         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5011                 return 0;
5012
5013         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5014         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5015                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5016
5017         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5018                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5019
5020         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5021
5022         return 0;
5023 }
5024
5025 /* This function gets the FW version along with the
5026  * capabilities(MAX and current) of the function, vnic,
5027  * error recovery, phy and other chip related info
5028  */
5029 static int bnxt_get_config(struct bnxt *bp)
5030 {
5031         uint16_t mtu;
5032         int rc = 0;
5033
5034         bp->fw_cap = 0;
5035
5036         rc = bnxt_map_hcomm_fw_status_reg(bp);
5037         if (rc)
5038                 return rc;
5039
5040         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5041         if (rc) {
5042                 bnxt_check_fw_status(bp);
5043                 return rc;
5044         }
5045
5046         rc = bnxt_hwrm_func_reset(bp);
5047         if (rc)
5048                 return -EIO;
5049
5050         rc = bnxt_hwrm_vnic_qcaps(bp);
5051         if (rc)
5052                 return rc;
5053
5054         rc = bnxt_hwrm_queue_qportcfg(bp);
5055         if (rc)
5056                 return rc;
5057
5058         /* Get the MAX capabilities for this function.
5059          * This function also allocates context memory for TQM rings and
5060          * informs the firmware about this allocated backing store memory.
5061          */
5062         rc = bnxt_hwrm_func_qcaps(bp);
5063         if (rc)
5064                 return rc;
5065
5066         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5067         if (rc)
5068                 return rc;
5069
5070         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5071         if (rc)
5072                 return rc;
5073
5074         bnxt_hwrm_port_mac_qcfg(bp);
5075
5076         bnxt_hwrm_parent_pf_qcfg(bp);
5077
5078         bnxt_hwrm_port_phy_qcaps(bp);
5079
5080         bnxt_alloc_error_recovery_info(bp);
5081         /* Get the adapter error recovery support info */
5082         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5083         if (rc)
5084                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5085
5086         bnxt_hwrm_port_led_qcaps(bp);
5087
5088         return 0;
5089 }
5090
5091 static int
5092 bnxt_init_locks(struct bnxt *bp)
5093 {
5094         int err;
5095
5096         err = pthread_mutex_init(&bp->flow_lock, NULL);
5097         if (err) {
5098                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5099                 return err;
5100         }
5101
5102         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5103         if (err) {
5104                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5105                 return err;
5106         }
5107
5108         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5109         if (err) {
5110                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5111                 return err;
5112         }
5113
5114         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5115         if (err)
5116                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5117
5118         return err;
5119 }
5120
5121 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5122 {
5123         int rc = 0;
5124
5125         rc = bnxt_get_config(bp);
5126         if (rc)
5127                 return rc;
5128
5129         if (!reconfig_dev) {
5130                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5131                 if (rc)
5132                         return rc;
5133         } else {
5134                 rc = bnxt_restore_dflt_mac(bp);
5135                 if (rc)
5136                         return rc;
5137         }
5138
5139         bnxt_config_vf_req_fwd(bp);
5140
5141         rc = bnxt_hwrm_func_driver_register(bp);
5142         if (rc) {
5143                 PMD_DRV_LOG(ERR, "Failed to register driver");
5144                 return -EBUSY;
5145         }
5146
5147         if (BNXT_PF(bp)) {
5148                 if (bp->pdev->max_vfs) {
5149                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5150                         if (rc) {
5151                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5152                                 return rc;
5153                         }
5154                 } else {
5155                         rc = bnxt_hwrm_allocate_pf_only(bp);
5156                         if (rc) {
5157                                 PMD_DRV_LOG(ERR,
5158                                             "Failed to allocate PF resources");
5159                                 return rc;
5160                         }
5161                 }
5162         }
5163
5164         rc = bnxt_alloc_mem(bp, reconfig_dev);
5165         if (rc)
5166                 return rc;
5167
5168         rc = bnxt_setup_int(bp);
5169         if (rc)
5170                 return rc;
5171
5172         rc = bnxt_request_int(bp);
5173         if (rc)
5174                 return rc;
5175
5176         rc = bnxt_init_ctx_mem(bp);
5177         if (rc) {
5178                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5179                 return rc;
5180         }
5181
5182         return 0;
5183 }
5184
5185 static int
5186 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5187                           const char *value, void *opaque_arg)
5188 {
5189         struct bnxt *bp = opaque_arg;
5190         unsigned long truflow;
5191         char *end = NULL;
5192
5193         if (!value || !opaque_arg) {
5194                 PMD_DRV_LOG(ERR,
5195                             "Invalid parameter passed to truflow devargs.\n");
5196                 return -EINVAL;
5197         }
5198
5199         truflow = strtoul(value, &end, 10);
5200         if (end == NULL || *end != '\0' ||
5201             (truflow == ULONG_MAX && errno == ERANGE)) {
5202                 PMD_DRV_LOG(ERR,
5203                             "Invalid parameter passed to truflow devargs.\n");
5204                 return -EINVAL;
5205         }
5206
5207         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5208                 PMD_DRV_LOG(ERR,
5209                             "Invalid value passed to truflow devargs.\n");
5210                 return -EINVAL;
5211         }
5212
5213         if (truflow) {
5214                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5215                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5216         } else {
5217                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5218                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5219         }
5220
5221         return 0;
5222 }
5223
5224 static int
5225 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5226                              const char *value, void *opaque_arg)
5227 {
5228         struct bnxt *bp = opaque_arg;
5229         unsigned long flow_xstat;
5230         char *end = NULL;
5231
5232         if (!value || !opaque_arg) {
5233                 PMD_DRV_LOG(ERR,
5234                             "Invalid parameter passed to flow_xstat devarg.\n");
5235                 return -EINVAL;
5236         }
5237
5238         flow_xstat = strtoul(value, &end, 10);
5239         if (end == NULL || *end != '\0' ||
5240             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5241                 PMD_DRV_LOG(ERR,
5242                             "Invalid parameter passed to flow_xstat devarg.\n");
5243                 return -EINVAL;
5244         }
5245
5246         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5247                 PMD_DRV_LOG(ERR,
5248                             "Invalid value passed to flow_xstat devarg.\n");
5249                 return -EINVAL;
5250         }
5251
5252         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5253         if (BNXT_FLOW_XSTATS_EN(bp))
5254                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5255
5256         return 0;
5257 }
5258
5259 static int
5260 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5261                                         const char *value, void *opaque_arg)
5262 {
5263         struct bnxt *bp = opaque_arg;
5264         unsigned long max_num_kflows;
5265         char *end = NULL;
5266
5267         if (!value || !opaque_arg) {
5268                 PMD_DRV_LOG(ERR,
5269                         "Invalid parameter passed to max_num_kflows devarg.\n");
5270                 return -EINVAL;
5271         }
5272
5273         max_num_kflows = strtoul(value, &end, 10);
5274         if (end == NULL || *end != '\0' ||
5275                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5276                 PMD_DRV_LOG(ERR,
5277                         "Invalid parameter passed to max_num_kflows devarg.\n");
5278                 return -EINVAL;
5279         }
5280
5281         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5282                 PMD_DRV_LOG(ERR,
5283                         "Invalid value passed to max_num_kflows devarg.\n");
5284                 return -EINVAL;
5285         }
5286
5287         bp->max_num_kflows = max_num_kflows;
5288         if (bp->max_num_kflows)
5289                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5290                                 max_num_kflows);
5291
5292         return 0;
5293 }
5294
5295 static int
5296 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5297                             const char *value, void *opaque_arg)
5298 {
5299         struct bnxt_representor *vfr_bp = opaque_arg;
5300         unsigned long rep_is_pf;
5301         char *end = NULL;
5302
5303         if (!value || !opaque_arg) {
5304                 PMD_DRV_LOG(ERR,
5305                             "Invalid parameter passed to rep_is_pf devargs.\n");
5306                 return -EINVAL;
5307         }
5308
5309         rep_is_pf = strtoul(value, &end, 10);
5310         if (end == NULL || *end != '\0' ||
5311             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5312                 PMD_DRV_LOG(ERR,
5313                             "Invalid parameter passed to rep_is_pf devargs.\n");
5314                 return -EINVAL;
5315         }
5316
5317         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5318                 PMD_DRV_LOG(ERR,
5319                             "Invalid value passed to rep_is_pf devargs.\n");
5320                 return -EINVAL;
5321         }
5322
5323         vfr_bp->flags |= rep_is_pf;
5324         if (BNXT_REP_PF(vfr_bp))
5325                 PMD_DRV_LOG(INFO, "PF representor\n");
5326         else
5327                 PMD_DRV_LOG(INFO, "VF representor\n");
5328
5329         return 0;
5330 }
5331
5332 static int
5333 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5334                                const char *value, void *opaque_arg)
5335 {
5336         struct bnxt_representor *vfr_bp = opaque_arg;
5337         unsigned long rep_based_pf;
5338         char *end = NULL;
5339
5340         if (!value || !opaque_arg) {
5341                 PMD_DRV_LOG(ERR,
5342                             "Invalid parameter passed to rep_based_pf "
5343                             "devargs.\n");
5344                 return -EINVAL;
5345         }
5346
5347         rep_based_pf = strtoul(value, &end, 10);
5348         if (end == NULL || *end != '\0' ||
5349             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5350                 PMD_DRV_LOG(ERR,
5351                             "Invalid parameter passed to rep_based_pf "
5352                             "devargs.\n");
5353                 return -EINVAL;
5354         }
5355
5356         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5357                 PMD_DRV_LOG(ERR,
5358                             "Invalid value passed to rep_based_pf devargs.\n");
5359                 return -EINVAL;
5360         }
5361
5362         vfr_bp->rep_based_pf = rep_based_pf;
5363         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5364
5365         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5366
5367         return 0;
5368 }
5369
5370 static int
5371 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5372                             const char *value, void *opaque_arg)
5373 {
5374         struct bnxt_representor *vfr_bp = opaque_arg;
5375         unsigned long rep_q_r2f;
5376         char *end = NULL;
5377
5378         if (!value || !opaque_arg) {
5379                 PMD_DRV_LOG(ERR,
5380                             "Invalid parameter passed to rep_q_r2f "
5381                             "devargs.\n");
5382                 return -EINVAL;
5383         }
5384
5385         rep_q_r2f = strtoul(value, &end, 10);
5386         if (end == NULL || *end != '\0' ||
5387             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5388                 PMD_DRV_LOG(ERR,
5389                             "Invalid parameter passed to rep_q_r2f "
5390                             "devargs.\n");
5391                 return -EINVAL;
5392         }
5393
5394         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5395                 PMD_DRV_LOG(ERR,
5396                             "Invalid value passed to rep_q_r2f devargs.\n");
5397                 return -EINVAL;
5398         }
5399
5400         vfr_bp->rep_q_r2f = rep_q_r2f;
5401         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5402         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5403
5404         return 0;
5405 }
5406
5407 static int
5408 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5409                             const char *value, void *opaque_arg)
5410 {
5411         struct bnxt_representor *vfr_bp = opaque_arg;
5412         unsigned long rep_q_f2r;
5413         char *end = NULL;
5414
5415         if (!value || !opaque_arg) {
5416                 PMD_DRV_LOG(ERR,
5417                             "Invalid parameter passed to rep_q_f2r "
5418                             "devargs.\n");
5419                 return -EINVAL;
5420         }
5421
5422         rep_q_f2r = strtoul(value, &end, 10);
5423         if (end == NULL || *end != '\0' ||
5424             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5425                 PMD_DRV_LOG(ERR,
5426                             "Invalid parameter passed to rep_q_f2r "
5427                             "devargs.\n");
5428                 return -EINVAL;
5429         }
5430
5431         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5432                 PMD_DRV_LOG(ERR,
5433                             "Invalid value passed to rep_q_f2r devargs.\n");
5434                 return -EINVAL;
5435         }
5436
5437         vfr_bp->rep_q_f2r = rep_q_f2r;
5438         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5439         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5440
5441         return 0;
5442 }
5443
5444 static int
5445 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5446                              const char *value, void *opaque_arg)
5447 {
5448         struct bnxt_representor *vfr_bp = opaque_arg;
5449         unsigned long rep_fc_r2f;
5450         char *end = NULL;
5451
5452         if (!value || !opaque_arg) {
5453                 PMD_DRV_LOG(ERR,
5454                             "Invalid parameter passed to rep_fc_r2f "
5455                             "devargs.\n");
5456                 return -EINVAL;
5457         }
5458
5459         rep_fc_r2f = strtoul(value, &end, 10);
5460         if (end == NULL || *end != '\0' ||
5461             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5462                 PMD_DRV_LOG(ERR,
5463                             "Invalid parameter passed to rep_fc_r2f "
5464                             "devargs.\n");
5465                 return -EINVAL;
5466         }
5467
5468         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5469                 PMD_DRV_LOG(ERR,
5470                             "Invalid value passed to rep_fc_r2f devargs.\n");
5471                 return -EINVAL;
5472         }
5473
5474         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5475         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5476         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5477
5478         return 0;
5479 }
5480
5481 static int
5482 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5483                              const char *value, void *opaque_arg)
5484 {
5485         struct bnxt_representor *vfr_bp = opaque_arg;
5486         unsigned long rep_fc_f2r;
5487         char *end = NULL;
5488
5489         if (!value || !opaque_arg) {
5490                 PMD_DRV_LOG(ERR,
5491                             "Invalid parameter passed to rep_fc_f2r "
5492                             "devargs.\n");
5493                 return -EINVAL;
5494         }
5495
5496         rep_fc_f2r = strtoul(value, &end, 10);
5497         if (end == NULL || *end != '\0' ||
5498             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5499                 PMD_DRV_LOG(ERR,
5500                             "Invalid parameter passed to rep_fc_f2r "
5501                             "devargs.\n");
5502                 return -EINVAL;
5503         }
5504
5505         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5506                 PMD_DRV_LOG(ERR,
5507                             "Invalid value passed to rep_fc_f2r devargs.\n");
5508                 return -EINVAL;
5509         }
5510
5511         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5512         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5513         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5514
5515         return 0;
5516 }
5517
5518 static int
5519 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5520 {
5521         struct rte_kvargs *kvlist;
5522         int ret;
5523
5524         if (devargs == NULL)
5525                 return 0;
5526
5527         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5528         if (kvlist == NULL)
5529                 return -EINVAL;
5530
5531         /*
5532          * Handler for "truflow" devarg.
5533          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5534          */
5535         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5536                                  bnxt_parse_devarg_truflow, bp);
5537         if (ret)
5538                 goto err;
5539
5540         /*
5541          * Handler for "flow_xstat" devarg.
5542          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5543          */
5544         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5545                                  bnxt_parse_devarg_flow_xstat, bp);
5546         if (ret)
5547                 goto err;
5548
5549         /*
5550          * Handler for "max_num_kflows" devarg.
5551          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5552          */
5553         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5554                                  bnxt_parse_devarg_max_num_kflows, bp);
5555         if (ret)
5556                 goto err;
5557
5558 err:
5559         rte_kvargs_free(kvlist);
5560         return ret;
5561 }
5562
5563 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5564 {
5565         int rc = 0;
5566
5567         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5568                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5569                 if (rc)
5570                         PMD_DRV_LOG(ERR,
5571                                     "Failed to alloc switch domain: %d\n", rc);
5572                 else
5573                         PMD_DRV_LOG(INFO,
5574                                     "Switch domain allocated %d\n",
5575                                     bp->switch_domain_id);
5576         }
5577
5578         return rc;
5579 }
5580
5581 /* Allocate and initialize various fields in bnxt struct that
5582  * need to be allocated/destroyed only once in the lifetime of the driver
5583  */
5584 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5585 {
5586         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5587         struct bnxt *bp = eth_dev->data->dev_private;
5588         int rc = 0;
5589
5590         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5591
5592         if (bnxt_vf_pciid(pci_dev->id.device_id))
5593                 bp->flags |= BNXT_FLAG_VF;
5594
5595         if (bnxt_p5_device(pci_dev->id.device_id))
5596                 bp->flags |= BNXT_FLAG_CHIP_P5;
5597
5598         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5599             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5600             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5601             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5602                 bp->flags |= BNXT_FLAG_STINGRAY;
5603
5604         if (BNXT_TRUFLOW_EN(bp)) {
5605                 /* extra mbuf field is required to store CFA code from mark */
5606                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5607                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5608                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5609                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5610                 };
5611                 bnxt_cfa_code_dynfield_offset =
5612                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5613                 if (bnxt_cfa_code_dynfield_offset < 0) {
5614                         PMD_DRV_LOG(ERR,
5615                             "Failed to register mbuf field for TruFlow mark\n");
5616                         return -rte_errno;
5617                 }
5618         }
5619
5620         rc = bnxt_map_pci_bars(eth_dev);
5621         if (rc) {
5622                 PMD_DRV_LOG(ERR,
5623                             "Failed to initialize board rc: %x\n", rc);
5624                 return rc;
5625         }
5626
5627         rc = bnxt_alloc_pf_info(bp);
5628         if (rc)
5629                 return rc;
5630
5631         rc = bnxt_alloc_link_info(bp);
5632         if (rc)
5633                 return rc;
5634
5635         rc = bnxt_alloc_parent_info(bp);
5636         if (rc)
5637                 return rc;
5638
5639         rc = bnxt_alloc_hwrm_resources(bp);
5640         if (rc) {
5641                 PMD_DRV_LOG(ERR,
5642                             "Failed to allocate response buffer rc: %x\n", rc);
5643                 return rc;
5644         }
5645         rc = bnxt_alloc_leds_info(bp);
5646         if (rc)
5647                 return rc;
5648
5649         rc = bnxt_alloc_cos_queues(bp);
5650         if (rc)
5651                 return rc;
5652
5653         rc = bnxt_init_locks(bp);
5654         if (rc)
5655                 return rc;
5656
5657         rc = bnxt_alloc_switch_domain(bp);
5658         if (rc)
5659                 return rc;
5660
5661         return rc;
5662 }
5663
5664 static int
5665 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5666 {
5667         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5668         static int version_printed;
5669         struct bnxt *bp;
5670         int rc;
5671
5672         if (version_printed++ == 0)
5673                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5674
5675         eth_dev->dev_ops = &bnxt_dev_ops;
5676         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5677         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5678         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5679         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5680         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5681
5682         /*
5683          * For secondary processes, we don't initialise any further
5684          * as primary has already done this work.
5685          */
5686         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5687                 return 0;
5688
5689         rte_eth_copy_pci_info(eth_dev, pci_dev);
5690         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5691
5692         bp = eth_dev->data->dev_private;
5693
5694         /* Parse dev arguments passed on when starting the DPDK application. */
5695         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5696         if (rc)
5697                 goto error_free;
5698
5699         rc = bnxt_drv_init(eth_dev);
5700         if (rc)
5701                 goto error_free;
5702
5703         rc = bnxt_init_resources(bp, false);
5704         if (rc)
5705                 goto error_free;
5706
5707         rc = bnxt_alloc_stats_mem(bp);
5708         if (rc)
5709                 goto error_free;
5710
5711         PMD_DRV_LOG(INFO,
5712                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5713                     pci_dev->mem_resource[0].phys_addr,
5714                     pci_dev->mem_resource[0].addr);
5715
5716         return 0;
5717
5718 error_free:
5719         bnxt_dev_uninit(eth_dev);
5720         return rc;
5721 }
5722
5723
5724 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5725 {
5726         if (!ctx)
5727                 return;
5728
5729         if (ctx->va)
5730                 rte_free(ctx->va);
5731
5732         ctx->va = NULL;
5733         ctx->dma = RTE_BAD_IOVA;
5734         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5735 }
5736
5737 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5738 {
5739         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5740                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5741                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5742                                   bp->flow_stat->max_fc,
5743                                   false);
5744
5745         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5746                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5747                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5748                                   bp->flow_stat->max_fc,
5749                                   false);
5750
5751         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5752                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5753         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5754
5755         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5756                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5757         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5758
5759         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5760                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5761         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5762
5763         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5764                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5765         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5766 }
5767
5768 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5769 {
5770         bnxt_unregister_fc_ctx_mem(bp);
5771
5772         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5773         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5774         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5775         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5776 }
5777
5778 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5779 {
5780         if (BNXT_FLOW_XSTATS_EN(bp))
5781                 bnxt_uninit_fc_ctx_mem(bp);
5782 }
5783
5784 static void
5785 bnxt_free_error_recovery_info(struct bnxt *bp)
5786 {
5787         rte_free(bp->recovery_info);
5788         bp->recovery_info = NULL;
5789         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5790 }
5791
5792 static int
5793 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5794 {
5795         int rc;
5796
5797         bnxt_free_int(bp);
5798         bnxt_free_mem(bp, reconfig_dev);
5799
5800         bnxt_hwrm_func_buf_unrgtr(bp);
5801         if (bp->pf != NULL) {
5802                 rte_free(bp->pf->vf_req_buf);
5803                 bp->pf->vf_req_buf = NULL;
5804         }
5805
5806         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5807         bp->flags &= ~BNXT_FLAG_REGISTERED;
5808         bnxt_free_ctx_mem(bp);
5809         if (!reconfig_dev) {
5810                 bnxt_free_hwrm_resources(bp);
5811                 bnxt_free_error_recovery_info(bp);
5812         }
5813
5814         bnxt_uninit_ctx_mem(bp);
5815
5816         bnxt_free_flow_stats_info(bp);
5817         if (bp->rep_info != NULL)
5818                 bnxt_free_switch_domain(bp);
5819         bnxt_free_rep_info(bp);
5820         rte_free(bp->ptp_cfg);
5821         bp->ptp_cfg = NULL;
5822         return rc;
5823 }
5824
5825 static int
5826 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5827 {
5828         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5829                 return -EPERM;
5830
5831         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5832
5833         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5834                 bnxt_dev_close_op(eth_dev);
5835
5836         return 0;
5837 }
5838
5839 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5840 {
5841         struct bnxt *bp = eth_dev->data->dev_private;
5842         struct rte_eth_dev *vf_rep_eth_dev;
5843         int ret = 0, i;
5844
5845         if (!bp)
5846                 return -EINVAL;
5847
5848         for (i = 0; i < bp->num_reps; i++) {
5849                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5850                 if (!vf_rep_eth_dev)
5851                         continue;
5852                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5853                             vf_rep_eth_dev->data->port_id);
5854                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5855         }
5856         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5857                     eth_dev->data->port_id);
5858         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5859
5860         return ret;
5861 }
5862
5863 static void bnxt_free_rep_info(struct bnxt *bp)
5864 {
5865         rte_free(bp->rep_info);
5866         bp->rep_info = NULL;
5867         rte_free(bp->cfa_code_map);
5868         bp->cfa_code_map = NULL;
5869 }
5870
5871 static int bnxt_init_rep_info(struct bnxt *bp)
5872 {
5873         int i = 0, rc;
5874
5875         if (bp->rep_info)
5876                 return 0;
5877
5878         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5879                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5880                                    0);
5881         if (!bp->rep_info) {
5882                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5883                 return -ENOMEM;
5884         }
5885         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5886                                        sizeof(*bp->cfa_code_map) *
5887                                        BNXT_MAX_CFA_CODE, 0);
5888         if (!bp->cfa_code_map) {
5889                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5890                 bnxt_free_rep_info(bp);
5891                 return -ENOMEM;
5892         }
5893
5894         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5895                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5896
5897         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5898         if (rc) {
5899                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5900                 bnxt_free_rep_info(bp);
5901                 return rc;
5902         }
5903
5904         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5905         if (rc) {
5906                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5907                 bnxt_free_rep_info(bp);
5908                 return rc;
5909         }
5910
5911         return rc;
5912 }
5913
5914 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5915                                struct rte_eth_devargs *eth_da,
5916                                struct rte_eth_dev *backing_eth_dev,
5917                                const char *dev_args)
5918 {
5919         struct rte_eth_dev *vf_rep_eth_dev;
5920         char name[RTE_ETH_NAME_MAX_LEN];
5921         struct bnxt *backing_bp;
5922         uint16_t num_rep;
5923         int i, ret = 0;
5924         struct rte_kvargs *kvlist = NULL;
5925
5926         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
5927                 return 0;
5928         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
5929                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
5930                             eth_da->type);
5931                 return -ENOTSUP;
5932         }
5933         num_rep = eth_da->nb_representor_ports;
5934         if (num_rep > BNXT_MAX_VF_REPS) {
5935                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5936                             num_rep, BNXT_MAX_VF_REPS);
5937                 return -EINVAL;
5938         }
5939
5940         if (num_rep >= RTE_MAX_ETHPORTS) {
5941                 PMD_DRV_LOG(ERR,
5942                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5943                             num_rep, RTE_MAX_ETHPORTS);
5944                 return -EINVAL;
5945         }
5946
5947         backing_bp = backing_eth_dev->data->dev_private;
5948
5949         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5950                 PMD_DRV_LOG(ERR,
5951                             "Not a PF or trusted VF. No Representor support\n");
5952                 /* Returning an error is not an option.
5953                  * Applications are not handling this correctly
5954                  */
5955                 return 0;
5956         }
5957
5958         if (bnxt_init_rep_info(backing_bp))
5959                 return 0;
5960
5961         for (i = 0; i < num_rep; i++) {
5962                 struct bnxt_representor representor = {
5963                         .vf_id = eth_da->representor_ports[i],
5964                         .switch_domain_id = backing_bp->switch_domain_id,
5965                         .parent_dev = backing_eth_dev
5966                 };
5967
5968                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5969                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5970                                     representor.vf_id, BNXT_MAX_VF_REPS);
5971                         continue;
5972                 }
5973
5974                 /* representor port net_bdf_port */
5975                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5976                          pci_dev->device.name, eth_da->representor_ports[i]);
5977
5978                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5979                 if (kvlist) {
5980                         /*
5981                          * Handler for "rep_is_pf" devarg.
5982                          * Invoked as for ex: "-a 000:00:0d.0,
5983                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5984                          */
5985                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5986                                                  bnxt_parse_devarg_rep_is_pf,
5987                                                  (void *)&representor);
5988                         if (ret) {
5989                                 ret = -EINVAL;
5990                                 goto err;
5991                         }
5992                         /*
5993                          * Handler for "rep_based_pf" devarg.
5994                          * Invoked as for ex: "-a 000:00:0d.0,
5995                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5996                          */
5997                         ret = rte_kvargs_process(kvlist,
5998                                                  BNXT_DEVARG_REP_BASED_PF,
5999                                                  bnxt_parse_devarg_rep_based_pf,
6000                                                  (void *)&representor);
6001                         if (ret) {
6002                                 ret = -EINVAL;
6003                                 goto err;
6004                         }
6005                         /*
6006                          * Handler for "rep_based_pf" devarg.
6007                          * Invoked as for ex: "-a 000:00:0d.0,
6008                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6009                          */
6010                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6011                                                  bnxt_parse_devarg_rep_q_r2f,
6012                                                  (void *)&representor);
6013                         if (ret) {
6014                                 ret = -EINVAL;
6015                                 goto err;
6016                         }
6017                         /*
6018                          * Handler for "rep_based_pf" devarg.
6019                          * Invoked as for ex: "-a 000:00:0d.0,
6020                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6021                          */
6022                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6023                                                  bnxt_parse_devarg_rep_q_f2r,
6024                                                  (void *)&representor);
6025                         if (ret) {
6026                                 ret = -EINVAL;
6027                                 goto err;
6028                         }
6029                         /*
6030                          * Handler for "rep_based_pf" devarg.
6031                          * Invoked as for ex: "-a 000:00:0d.0,
6032                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6033                          */
6034                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6035                                                  bnxt_parse_devarg_rep_fc_r2f,
6036                                                  (void *)&representor);
6037                         if (ret) {
6038                                 ret = -EINVAL;
6039                                 goto err;
6040                         }
6041                         /*
6042                          * Handler for "rep_based_pf" devarg.
6043                          * Invoked as for ex: "-a 000:00:0d.0,
6044                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6045                          */
6046                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6047                                                  bnxt_parse_devarg_rep_fc_f2r,
6048                                                  (void *)&representor);
6049                         if (ret) {
6050                                 ret = -EINVAL;
6051                                 goto err;
6052                         }
6053                 }
6054
6055                 ret = rte_eth_dev_create(&pci_dev->device, name,
6056                                          sizeof(struct bnxt_representor),
6057                                          NULL, NULL,
6058                                          bnxt_representor_init,
6059                                          &representor);
6060                 if (ret) {
6061                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6062                                     "representor %s.", name);
6063                         goto err;
6064                 }
6065
6066                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6067                 if (!vf_rep_eth_dev) {
6068                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6069                                     " for VF-Rep: %s.", name);
6070                         ret = -ENODEV;
6071                         goto err;
6072                 }
6073
6074                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6075                             backing_eth_dev->data->port_id);
6076                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6077                                                          vf_rep_eth_dev;
6078                 backing_bp->num_reps++;
6079
6080         }
6081
6082         rte_kvargs_free(kvlist);
6083         return 0;
6084
6085 err:
6086         /* If num_rep > 1, then rollback already created
6087          * ports, since we'll be failing the probe anyway
6088          */
6089         if (num_rep > 1)
6090                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6091         rte_errno = -ret;
6092         rte_kvargs_free(kvlist);
6093
6094         return ret;
6095 }
6096
6097 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6098                           struct rte_pci_device *pci_dev)
6099 {
6100         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6101         struct rte_eth_dev *backing_eth_dev;
6102         uint16_t num_rep;
6103         int ret = 0;
6104
6105         if (pci_dev->device.devargs) {
6106                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6107                                             &eth_da);
6108                 if (ret)
6109                         return ret;
6110         }
6111
6112         num_rep = eth_da.nb_representor_ports;
6113         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6114                     num_rep);
6115
6116         /* We could come here after first level of probe is already invoked
6117          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6118          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6119          */
6120         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6121         if (backing_eth_dev == NULL) {
6122                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6123                                          sizeof(struct bnxt),
6124                                          eth_dev_pci_specific_init, pci_dev,
6125                                          bnxt_dev_init, NULL);
6126
6127                 if (ret || !num_rep)
6128                         return ret;
6129
6130                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6131         }
6132         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6133                     backing_eth_dev->data->port_id);
6134
6135         if (!num_rep)
6136                 return ret;
6137
6138         /* probe representor ports now */
6139         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6140                                   pci_dev->device.devargs->args);
6141
6142         return ret;
6143 }
6144
6145 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6146 {
6147         struct rte_eth_dev *eth_dev;
6148
6149         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6150         if (!eth_dev)
6151                 return 0; /* Invoked typically only by OVS-DPDK, by the
6152                            * time it comes here the eth_dev is already
6153                            * deleted by rte_eth_dev_close(), so returning
6154                            * +ve value will at least help in proper cleanup
6155                            */
6156
6157         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6158         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6159                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6160                         return rte_eth_dev_destroy(eth_dev,
6161                                                    bnxt_representor_uninit);
6162                 else
6163                         return rte_eth_dev_destroy(eth_dev,
6164                                                    bnxt_dev_uninit);
6165         } else {
6166                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6167         }
6168 }
6169
6170 static struct rte_pci_driver bnxt_rte_pmd = {
6171         .id_table = bnxt_pci_id_map,
6172         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6173                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6174                                                   * and OVS-DPDK
6175                                                   */
6176         .probe = bnxt_pci_probe,
6177         .remove = bnxt_pci_remove,
6178 };
6179
6180 static bool
6181 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6182 {
6183         if (strcmp(dev->device->driver->name, drv->driver.name))
6184                 return false;
6185
6186         return true;
6187 }
6188
6189 bool is_bnxt_supported(struct rte_eth_dev *dev)
6190 {
6191         return is_device_supported(dev, &bnxt_rte_pmd);
6192 }
6193
6194 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6195 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6196 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6197 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");