1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
30 #include "bnxt_util.h"
32 #define DRV_MODULE_NAME "bnxt"
33 static const char bnxt_version[] =
34 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
35 int bnxt_logtype_driver;
37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
43 #define BROADCOM_DEV_ID_57301 0x16c8
44 #define BROADCOM_DEV_ID_57302 0x16c9
45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
48 #define BROADCOM_DEV_ID_NS2 0x16cd
49 #define BROADCOM_DEV_ID_57311 0x16ce
50 #define BROADCOM_DEV_ID_57312 0x16cf
51 #define BROADCOM_DEV_ID_57402 0x16d0
52 #define BROADCOM_DEV_ID_57404 0x16d1
53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
57 #define BROADCOM_DEV_ID_57412 0x16d6
58 #define BROADCOM_DEV_ID_57414 0x16d7
59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
62 #define BROADCOM_DEV_ID_57412_MF 0x16de
63 #define BROADCOM_DEV_ID_57314 0x16df
64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
75 #define BROADCOM_DEV_ID_57508 0x1750
76 #define BROADCOM_DEV_ID_57504 0x1751
77 #define BROADCOM_DEV_ID_57502 0x1752
78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
80 #define BROADCOM_DEV_ID_58802 0xd802
81 #define BROADCOM_DEV_ID_58804 0xd804
82 #define BROADCOM_DEV_ID_58808 0x16f0
83 #define BROADCOM_DEV_ID_58802_VF 0xd800
85 static const struct rte_pci_id bnxt_pci_id_map[] = {
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
89 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
145 DEV_TX_OFFLOAD_IPV4_CKSUM | \
146 DEV_TX_OFFLOAD_TCP_CKSUM | \
147 DEV_TX_OFFLOAD_UDP_CKSUM | \
148 DEV_TX_OFFLOAD_TCP_TSO | \
149 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
151 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
152 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
153 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
154 DEV_TX_OFFLOAD_MULTI_SEGS)
156 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
157 DEV_RX_OFFLOAD_VLAN_STRIP | \
158 DEV_RX_OFFLOAD_IPV4_CKSUM | \
159 DEV_RX_OFFLOAD_UDP_CKSUM | \
160 DEV_RX_OFFLOAD_TCP_CKSUM | \
161 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
162 DEV_RX_OFFLOAD_JUMBO_FRAME | \
163 DEV_RX_OFFLOAD_KEEP_CRC | \
164 DEV_RX_OFFLOAD_TCP_LRO)
166 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
167 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
168 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
169 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
170 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
171 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
172 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
174 int is_bnxt_in_error(struct bnxt *bp)
176 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
178 if (bp->flags & BNXT_FLAG_FW_RESET)
184 /***********************/
187 * High level utility functions
190 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
192 if (!BNXT_CHIP_THOR(bp))
195 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
196 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
197 BNXT_RSS_ENTRIES_PER_CTX_THOR;
200 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
202 if (!BNXT_CHIP_THOR(bp))
203 return HW_HASH_INDEX_SIZE;
205 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
208 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
210 bnxt_free_filter_mem(bp);
211 bnxt_free_vnic_attributes(bp);
212 bnxt_free_vnic_mem(bp);
214 /* tx/rx rings are configured as part of *_queue_setup callbacks.
215 * If the number of rings change across fw update,
216 * we don't have much choice except to warn the user.
220 bnxt_free_tx_rings(bp);
221 bnxt_free_rx_rings(bp);
223 bnxt_free_async_cp_ring(bp);
226 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
230 rc = bnxt_alloc_ring_grps(bp);
234 rc = bnxt_alloc_async_ring_struct(bp);
238 rc = bnxt_alloc_vnic_mem(bp);
242 rc = bnxt_alloc_vnic_attributes(bp);
246 rc = bnxt_alloc_filter_mem(bp);
250 rc = bnxt_alloc_async_cp_ring(bp);
257 bnxt_free_mem(bp, reconfig);
261 static int bnxt_init_chip(struct bnxt *bp)
263 struct bnxt_rx_queue *rxq;
264 struct rte_eth_link new;
265 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
266 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
267 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
268 uint64_t rx_offloads = dev_conf->rxmode.offloads;
269 uint32_t intr_vector = 0;
270 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
271 uint32_t vec = BNXT_MISC_VEC_ID;
275 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
276 bp->eth_dev->data->dev_conf.rxmode.offloads |=
277 DEV_RX_OFFLOAD_JUMBO_FRAME;
278 bp->flags |= BNXT_FLAG_JUMBO;
280 bp->eth_dev->data->dev_conf.rxmode.offloads &=
281 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
282 bp->flags &= ~BNXT_FLAG_JUMBO;
285 /* THOR does not support ring groups.
286 * But we will use the array to save RSS context IDs.
288 if (BNXT_CHIP_THOR(bp))
289 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
291 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
293 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
297 rc = bnxt_alloc_hwrm_rings(bp);
299 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
303 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
305 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
309 rc = bnxt_mq_rx_configure(bp);
311 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
315 /* VNIC configuration */
316 for (i = 0; i < bp->nr_vnics; i++) {
317 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
318 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
319 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
321 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
322 if (!vnic->fw_grp_ids) {
324 "Failed to alloc %d bytes for group ids\n",
329 memset(vnic->fw_grp_ids, -1, size);
331 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
332 i, vnic, vnic->fw_grp_ids);
334 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
336 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
341 /* Alloc RSS context only if RSS mode is enabled */
342 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
343 int j, nr_ctxs = bnxt_rss_ctxts(bp);
346 for (j = 0; j < nr_ctxs; j++) {
347 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
353 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
357 vnic->num_lb_ctxts = nr_ctxs;
361 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
362 * setting is not available at this time, it will not be
363 * configured correctly in the CFA.
365 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
366 vnic->vlan_strip = true;
368 vnic->vlan_strip = false;
370 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
372 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
377 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
380 "HWRM vnic %d filter failure rc: %x\n",
385 for (j = 0; j < bp->rx_nr_rings; j++) {
386 rxq = bp->eth_dev->data->rx_queues[j];
389 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
390 j, rxq->vnic, rxq->vnic->fw_grp_ids);
392 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
393 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
396 rc = bnxt_vnic_rss_configure(bp, vnic);
399 "HWRM vnic set RSS failure rc: %x\n", rc);
403 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
405 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
406 DEV_RX_OFFLOAD_TCP_LRO)
407 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
409 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
411 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
414 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
418 /* check and configure queue intr-vector mapping */
419 if ((rte_intr_cap_multiple(intr_handle) ||
420 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
421 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
422 intr_vector = bp->eth_dev->data->nb_rx_queues;
423 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
424 if (intr_vector > bp->rx_cp_nr_rings) {
425 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
429 rc = rte_intr_efd_enable(intr_handle, intr_vector);
434 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
435 intr_handle->intr_vec =
436 rte_zmalloc("intr_vec",
437 bp->eth_dev->data->nb_rx_queues *
439 if (intr_handle->intr_vec == NULL) {
440 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
441 " intr_vec", bp->eth_dev->data->nb_rx_queues);
445 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
446 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
447 intr_handle->intr_vec, intr_handle->nb_efd,
448 intr_handle->max_intr);
449 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
451 intr_handle->intr_vec[queue_id] =
452 vec + BNXT_RX_VEC_START;
453 if (vec < base + intr_handle->nb_efd - 1)
458 /* enable uio/vfio intr/eventfd mapping */
459 rc = rte_intr_enable(intr_handle);
463 rc = bnxt_get_hwrm_link_config(bp, &new);
465 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
469 if (!bp->link_info.link_up) {
470 rc = bnxt_set_hwrm_link_config(bp, true);
473 "HWRM link config failure rc: %x\n", rc);
477 bnxt_print_link_info(bp->eth_dev);
482 rte_free(intr_handle->intr_vec);
484 rte_intr_efd_disable(intr_handle);
486 /* Some of the error status returned by FW may not be from errno.h */
493 static int bnxt_shutdown_nic(struct bnxt *bp)
495 bnxt_free_all_hwrm_resources(bp);
496 bnxt_free_all_filters(bp);
497 bnxt_free_all_vnics(bp);
501 static int bnxt_init_nic(struct bnxt *bp)
505 if (BNXT_HAS_RING_GRPS(bp)) {
506 rc = bnxt_init_ring_grps(bp);
512 bnxt_init_filters(bp);
518 * Device configuration and status function
521 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
522 struct rte_eth_dev_info *dev_info)
524 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
525 struct bnxt *bp = eth_dev->data->dev_private;
526 uint16_t max_vnics, i, j, vpool, vrxq;
527 unsigned int max_rx_rings;
530 rc = is_bnxt_in_error(bp);
535 dev_info->max_mac_addrs = bp->max_l2_ctx;
536 dev_info->max_hash_mac_addrs = 0;
538 /* PF/VF specifics */
540 dev_info->max_vfs = pdev->max_vfs;
542 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
543 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
544 dev_info->max_rx_queues = max_rx_rings;
545 dev_info->max_tx_queues = max_rx_rings;
546 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
547 dev_info->hash_key_size = 40;
548 max_vnics = bp->max_vnics;
551 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
552 dev_info->max_mtu = BNXT_MAX_MTU;
554 /* Fast path specifics */
555 dev_info->min_rx_bufsize = 1;
556 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
558 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
559 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
560 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
561 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
562 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
565 dev_info->default_rxconf = (struct rte_eth_rxconf) {
571 .rx_free_thresh = 32,
572 /* If no descriptors available, pkts are dropped by default */
576 dev_info->default_txconf = (struct rte_eth_txconf) {
582 .tx_free_thresh = 32,
585 eth_dev->data->dev_conf.intr_conf.lsc = 1;
587 eth_dev->data->dev_conf.intr_conf.rxq = 1;
588 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
589 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
590 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
591 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
596 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
597 * need further investigation.
601 vpool = 64; /* ETH_64_POOLS */
602 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
603 for (i = 0; i < 4; vpool >>= 1, i++) {
604 if (max_vnics > vpool) {
605 for (j = 0; j < 5; vrxq >>= 1, j++) {
606 if (dev_info->max_rx_queues > vrxq) {
612 /* Not enough resources to support VMDq */
616 /* Not enough resources to support VMDq */
620 dev_info->max_vmdq_pools = vpool;
621 dev_info->vmdq_queue_num = vrxq;
623 dev_info->vmdq_pool_base = 0;
624 dev_info->vmdq_queue_base = 0;
629 /* Configure the device based on the configuration provided */
630 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
632 struct bnxt *bp = eth_dev->data->dev_private;
633 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
636 bp->rx_queues = (void *)eth_dev->data->rx_queues;
637 bp->tx_queues = (void *)eth_dev->data->tx_queues;
638 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
639 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
641 rc = is_bnxt_in_error(bp);
645 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
646 rc = bnxt_hwrm_check_vf_rings(bp);
648 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
652 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
654 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
658 /* legacy driver needs to get updated values */
659 rc = bnxt_hwrm_func_qcaps(bp);
661 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
666 /* Inherit new configurations */
667 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
668 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
669 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
670 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
671 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
675 if (BNXT_HAS_RING_GRPS(bp) &&
676 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
679 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
680 bp->max_vnics < eth_dev->data->nb_rx_queues)
683 bp->rx_cp_nr_rings = bp->rx_nr_rings;
684 bp->tx_cp_nr_rings = bp->tx_nr_rings;
686 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
688 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
689 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
691 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
697 "Insufficient resources to support requested config\n");
699 "Num Queues Requested: Tx %d, Rx %d\n",
700 eth_dev->data->nb_tx_queues,
701 eth_dev->data->nb_rx_queues);
703 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
704 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
705 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
709 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
711 struct rte_eth_link *link = ð_dev->data->dev_link;
713 if (link->link_status)
714 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
715 eth_dev->data->port_id,
716 (uint32_t)link->link_speed,
717 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
718 ("full-duplex") : ("half-duplex\n"));
720 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
721 eth_dev->data->port_id);
725 * Determine whether the current configuration requires support for scattered
726 * receive; return 1 if scattered receive is required and 0 if not.
728 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
733 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
734 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
736 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
737 RTE_PKTMBUF_HEADROOM);
738 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
744 static eth_rx_burst_t
745 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
748 #ifndef RTE_LIBRTE_IEEE1588
750 * Vector mode receive can be enabled only if scatter rx is not
751 * in use and rx offloads are limited to VLAN stripping and
754 if (!eth_dev->data->scattered_rx &&
755 !(eth_dev->data->dev_conf.rxmode.offloads &
756 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
757 DEV_RX_OFFLOAD_KEEP_CRC |
758 DEV_RX_OFFLOAD_JUMBO_FRAME |
759 DEV_RX_OFFLOAD_IPV4_CKSUM |
760 DEV_RX_OFFLOAD_UDP_CKSUM |
761 DEV_RX_OFFLOAD_TCP_CKSUM |
762 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
763 DEV_RX_OFFLOAD_VLAN_FILTER))) {
764 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
765 eth_dev->data->port_id);
766 return bnxt_recv_pkts_vec;
768 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
769 eth_dev->data->port_id);
771 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
772 eth_dev->data->port_id,
773 eth_dev->data->scattered_rx,
774 eth_dev->data->dev_conf.rxmode.offloads);
777 return bnxt_recv_pkts;
780 static eth_tx_burst_t
781 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
784 #ifndef RTE_LIBRTE_IEEE1588
786 * Vector mode transmit can be enabled only if not using scatter rx
789 if (!eth_dev->data->scattered_rx &&
790 !eth_dev->data->dev_conf.txmode.offloads) {
791 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
792 eth_dev->data->port_id);
793 return bnxt_xmit_pkts_vec;
795 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
796 eth_dev->data->port_id);
798 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
799 eth_dev->data->port_id,
800 eth_dev->data->scattered_rx,
801 eth_dev->data->dev_conf.txmode.offloads);
804 return bnxt_xmit_pkts;
807 static int bnxt_handle_if_change_status(struct bnxt *bp)
811 /* Since fw has undergone a reset and lost all contexts,
812 * set fatal flag to not issue hwrm during cleanup
814 bp->flags |= BNXT_FLAG_FATAL_ERROR;
815 bnxt_uninit_resources(bp, true);
817 /* clear fatal flag so that re-init happens */
818 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
819 rc = bnxt_init_resources(bp, true);
821 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
826 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
828 struct bnxt *bp = eth_dev->data->dev_private;
829 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
833 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
835 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
836 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
840 rc = bnxt_hwrm_if_change(bp, 1);
842 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
843 rc = bnxt_handle_if_change_status(bp);
849 rc = bnxt_init_chip(bp);
853 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
855 bnxt_link_update_op(eth_dev, 1);
857 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
858 vlan_mask |= ETH_VLAN_FILTER_MASK;
859 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
860 vlan_mask |= ETH_VLAN_STRIP_MASK;
861 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
865 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
866 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
868 bp->flags |= BNXT_FLAG_INIT_DONE;
869 eth_dev->data->dev_started = 1;
871 bnxt_schedule_fw_health_check(bp);
875 bnxt_hwrm_if_change(bp, 0);
876 bnxt_shutdown_nic(bp);
877 bnxt_free_tx_mbufs(bp);
878 bnxt_free_rx_mbufs(bp);
882 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
884 struct bnxt *bp = eth_dev->data->dev_private;
887 if (!bp->link_info.link_up)
888 rc = bnxt_set_hwrm_link_config(bp, true);
890 eth_dev->data->dev_link.link_status = 1;
892 bnxt_print_link_info(eth_dev);
896 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
898 struct bnxt *bp = eth_dev->data->dev_private;
900 eth_dev->data->dev_link.link_status = 0;
901 bnxt_set_hwrm_link_config(bp, false);
902 bp->link_info.link_up = 0;
907 /* Unload the driver, release resources */
908 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
910 struct bnxt *bp = eth_dev->data->dev_private;
911 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
912 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
914 eth_dev->data->dev_started = 0;
915 /* Prevent crashes when queues are still in use */
916 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
917 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
919 bnxt_disable_int(bp);
921 /* disable uio/vfio intr/eventfd mapping */
922 rte_intr_disable(intr_handle);
924 bnxt_cancel_fw_health_check(bp);
926 bp->flags &= ~BNXT_FLAG_INIT_DONE;
927 if (bp->eth_dev->data->dev_started) {
928 /* TBD: STOP HW queues DMA */
929 eth_dev->data->dev_link.link_status = 0;
931 bnxt_dev_set_link_down_op(eth_dev);
932 /* Wait for link to be reset and the async notification to process. */
933 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
935 /* Clean queue intr-vector mapping */
936 rte_intr_efd_disable(intr_handle);
937 if (intr_handle->intr_vec != NULL) {
938 rte_free(intr_handle->intr_vec);
939 intr_handle->intr_vec = NULL;
942 bnxt_hwrm_port_clr_stats(bp);
943 bnxt_free_tx_mbufs(bp);
944 bnxt_free_rx_mbufs(bp);
945 /* Process any remaining notifications in default completion queue */
946 bnxt_int_handler(eth_dev);
947 bnxt_shutdown_nic(bp);
948 bnxt_hwrm_if_change(bp, 0);
952 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
954 struct bnxt *bp = eth_dev->data->dev_private;
956 if (bp->dev_stopped == 0)
957 bnxt_dev_stop_op(eth_dev);
959 if (eth_dev->data->mac_addrs != NULL) {
960 rte_free(eth_dev->data->mac_addrs);
961 eth_dev->data->mac_addrs = NULL;
963 if (bp->grp_info != NULL) {
964 rte_free(bp->grp_info);
968 bnxt_dev_uninit(eth_dev);
971 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
974 struct bnxt *bp = eth_dev->data->dev_private;
975 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
976 struct bnxt_vnic_info *vnic;
977 struct bnxt_filter_info *filter, *temp_filter;
980 if (is_bnxt_in_error(bp))
984 * Loop through all VNICs from the specified filter flow pools to
985 * remove the corresponding MAC addr filter
987 for (i = 0; i < bp->nr_vnics; i++) {
988 if (!(pool_mask & (1ULL << i)))
991 vnic = &bp->vnic_info[i];
992 filter = STAILQ_FIRST(&vnic->filter);
994 temp_filter = STAILQ_NEXT(filter, next);
995 if (filter->mac_index == index) {
996 STAILQ_REMOVE(&vnic->filter, filter,
997 bnxt_filter_info, next);
998 bnxt_hwrm_clear_l2_filter(bp, filter);
999 filter->mac_index = INVALID_MAC_INDEX;
1000 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1001 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1004 filter = temp_filter;
1009 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1010 struct rte_ether_addr *mac_addr,
1011 uint32_t index, uint32_t pool)
1013 struct bnxt *bp = eth_dev->data->dev_private;
1014 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1015 struct bnxt_filter_info *filter;
1018 rc = is_bnxt_in_error(bp);
1022 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1023 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1028 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1031 /* Attach requested MAC address to the new l2_filter */
1032 STAILQ_FOREACH(filter, &vnic->filter, next) {
1033 if (filter->mac_index == index) {
1035 "MAC addr already existed for pool %d\n", pool);
1039 filter = bnxt_alloc_filter(bp);
1041 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1045 filter->mac_index = index;
1046 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1048 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1050 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1052 filter->mac_index = INVALID_MAC_INDEX;
1053 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1054 bnxt_free_filter(bp, filter);
1060 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1063 struct bnxt *bp = eth_dev->data->dev_private;
1064 struct rte_eth_link new;
1065 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1067 rc = is_bnxt_in_error(bp);
1071 memset(&new, 0, sizeof(new));
1073 /* Retrieve link info from hardware */
1074 rc = bnxt_get_hwrm_link_config(bp, &new);
1076 new.link_speed = ETH_LINK_SPEED_100M;
1077 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1079 "Failed to retrieve link rc = 0x%x!\n", rc);
1083 if (!wait_to_complete || new.link_status)
1086 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1090 /* Timed out or success */
1091 if (new.link_status != eth_dev->data->dev_link.link_status ||
1092 new.link_speed != eth_dev->data->dev_link.link_speed) {
1093 rte_eth_linkstatus_set(eth_dev, &new);
1095 _rte_eth_dev_callback_process(eth_dev,
1096 RTE_ETH_EVENT_INTR_LSC,
1099 bnxt_print_link_info(eth_dev);
1105 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1107 struct bnxt *bp = eth_dev->data->dev_private;
1108 struct bnxt_vnic_info *vnic;
1112 rc = is_bnxt_in_error(bp);
1116 if (bp->vnic_info == NULL)
1119 vnic = &bp->vnic_info[0];
1121 old_flags = vnic->flags;
1122 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1123 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1125 vnic->flags = old_flags;
1130 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1132 struct bnxt *bp = eth_dev->data->dev_private;
1133 struct bnxt_vnic_info *vnic;
1137 rc = is_bnxt_in_error(bp);
1141 if (bp->vnic_info == NULL)
1144 vnic = &bp->vnic_info[0];
1146 old_flags = vnic->flags;
1147 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1148 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1150 vnic->flags = old_flags;
1155 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1157 struct bnxt *bp = eth_dev->data->dev_private;
1158 struct bnxt_vnic_info *vnic;
1162 rc = is_bnxt_in_error(bp);
1166 if (bp->vnic_info == NULL)
1169 vnic = &bp->vnic_info[0];
1171 old_flags = vnic->flags;
1172 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1173 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1175 vnic->flags = old_flags;
1180 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1182 struct bnxt *bp = eth_dev->data->dev_private;
1183 struct bnxt_vnic_info *vnic;
1187 rc = is_bnxt_in_error(bp);
1191 if (bp->vnic_info == NULL)
1194 vnic = &bp->vnic_info[0];
1196 old_flags = vnic->flags;
1197 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1198 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1200 vnic->flags = old_flags;
1205 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1206 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1208 if (qid >= bp->rx_nr_rings)
1211 return bp->eth_dev->data->rx_queues[qid];
1214 /* Return rxq corresponding to a given rss table ring/group ID. */
1215 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1217 struct bnxt_rx_queue *rxq;
1220 if (!BNXT_HAS_RING_GRPS(bp)) {
1221 for (i = 0; i < bp->rx_nr_rings; i++) {
1222 rxq = bp->eth_dev->data->rx_queues[i];
1223 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1227 for (i = 0; i < bp->rx_nr_rings; i++) {
1228 if (bp->grp_info[i].fw_grp_id == fwr)
1233 return INVALID_HW_RING_ID;
1236 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1237 struct rte_eth_rss_reta_entry64 *reta_conf,
1240 struct bnxt *bp = eth_dev->data->dev_private;
1241 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1242 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1243 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1247 rc = is_bnxt_in_error(bp);
1251 if (!vnic->rss_table)
1254 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1257 if (reta_size != tbl_size) {
1258 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1259 "(%d) must equal the size supported by the hardware "
1260 "(%d)\n", reta_size, tbl_size);
1264 for (i = 0; i < reta_size; i++) {
1265 struct bnxt_rx_queue *rxq;
1267 idx = i / RTE_RETA_GROUP_SIZE;
1268 sft = i % RTE_RETA_GROUP_SIZE;
1270 if (!(reta_conf[idx].mask & (1ULL << sft)))
1273 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1275 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1279 if (BNXT_CHIP_THOR(bp)) {
1280 vnic->rss_table[i * 2] =
1281 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1282 vnic->rss_table[i * 2 + 1] =
1283 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1285 vnic->rss_table[i] =
1286 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1289 vnic->rss_table[i] =
1290 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1293 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1297 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1298 struct rte_eth_rss_reta_entry64 *reta_conf,
1301 struct bnxt *bp = eth_dev->data->dev_private;
1302 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1303 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1304 uint16_t idx, sft, i;
1307 rc = is_bnxt_in_error(bp);
1311 /* Retrieve from the default VNIC */
1314 if (!vnic->rss_table)
1317 if (reta_size != tbl_size) {
1318 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1319 "(%d) must equal the size supported by the hardware "
1320 "(%d)\n", reta_size, tbl_size);
1324 for (idx = 0, i = 0; i < reta_size; i++) {
1325 idx = i / RTE_RETA_GROUP_SIZE;
1326 sft = i % RTE_RETA_GROUP_SIZE;
1328 if (reta_conf[idx].mask & (1ULL << sft)) {
1331 if (BNXT_CHIP_THOR(bp))
1332 qid = bnxt_rss_to_qid(bp,
1333 vnic->rss_table[i * 2]);
1335 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1337 if (qid == INVALID_HW_RING_ID) {
1338 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1341 reta_conf[idx].reta[sft] = qid;
1348 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1349 struct rte_eth_rss_conf *rss_conf)
1351 struct bnxt *bp = eth_dev->data->dev_private;
1352 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1353 struct bnxt_vnic_info *vnic;
1354 uint16_t hash_type = 0;
1358 rc = is_bnxt_in_error(bp);
1363 * If RSS enablement were different than dev_configure,
1364 * then return -EINVAL
1366 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1367 if (!rss_conf->rss_hf)
1368 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1370 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1374 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1375 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1377 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1378 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1379 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1380 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1381 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1382 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1383 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1384 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1385 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1386 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1387 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1388 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1390 /* Update the RSS VNIC(s) */
1391 for (i = 0; i < bp->nr_vnics; i++) {
1392 vnic = &bp->vnic_info[i];
1393 vnic->hash_type = hash_type;
1396 * Use the supplied key if the key length is
1397 * acceptable and the rss_key is not NULL
1399 if (rss_conf->rss_key &&
1400 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1401 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1402 rss_conf->rss_key_len);
1404 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1409 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1410 struct rte_eth_rss_conf *rss_conf)
1412 struct bnxt *bp = eth_dev->data->dev_private;
1413 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1415 uint32_t hash_types;
1417 rc = is_bnxt_in_error(bp);
1421 /* RSS configuration is the same for all VNICs */
1422 if (vnic && vnic->rss_hash_key) {
1423 if (rss_conf->rss_key) {
1424 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1425 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1426 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1429 hash_types = vnic->hash_type;
1430 rss_conf->rss_hf = 0;
1431 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1432 rss_conf->rss_hf |= ETH_RSS_IPV4;
1433 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1435 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1436 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1438 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1440 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1441 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1443 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1445 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1446 rss_conf->rss_hf |= ETH_RSS_IPV6;
1447 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1449 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1450 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1452 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1454 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1455 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1457 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1461 "Unknwon RSS config from firmware (%08x), RSS disabled",
1466 rss_conf->rss_hf = 0;
1471 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1472 struct rte_eth_fc_conf *fc_conf)
1474 struct bnxt *bp = dev->data->dev_private;
1475 struct rte_eth_link link_info;
1478 rc = is_bnxt_in_error(bp);
1482 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1486 memset(fc_conf, 0, sizeof(*fc_conf));
1487 if (bp->link_info.auto_pause)
1488 fc_conf->autoneg = 1;
1489 switch (bp->link_info.pause) {
1491 fc_conf->mode = RTE_FC_NONE;
1493 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1494 fc_conf->mode = RTE_FC_TX_PAUSE;
1496 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1497 fc_conf->mode = RTE_FC_RX_PAUSE;
1499 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1500 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1501 fc_conf->mode = RTE_FC_FULL;
1507 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1508 struct rte_eth_fc_conf *fc_conf)
1510 struct bnxt *bp = dev->data->dev_private;
1513 rc = is_bnxt_in_error(bp);
1517 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1518 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1522 switch (fc_conf->mode) {
1524 bp->link_info.auto_pause = 0;
1525 bp->link_info.force_pause = 0;
1527 case RTE_FC_RX_PAUSE:
1528 if (fc_conf->autoneg) {
1529 bp->link_info.auto_pause =
1530 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1531 bp->link_info.force_pause = 0;
1533 bp->link_info.auto_pause = 0;
1534 bp->link_info.force_pause =
1535 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1538 case RTE_FC_TX_PAUSE:
1539 if (fc_conf->autoneg) {
1540 bp->link_info.auto_pause =
1541 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1542 bp->link_info.force_pause = 0;
1544 bp->link_info.auto_pause = 0;
1545 bp->link_info.force_pause =
1546 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1550 if (fc_conf->autoneg) {
1551 bp->link_info.auto_pause =
1552 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1553 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1554 bp->link_info.force_pause = 0;
1556 bp->link_info.auto_pause = 0;
1557 bp->link_info.force_pause =
1558 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1559 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1563 return bnxt_set_hwrm_link_config(bp, true);
1566 /* Add UDP tunneling port */
1568 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1569 struct rte_eth_udp_tunnel *udp_tunnel)
1571 struct bnxt *bp = eth_dev->data->dev_private;
1572 uint16_t tunnel_type = 0;
1575 rc = is_bnxt_in_error(bp);
1579 switch (udp_tunnel->prot_type) {
1580 case RTE_TUNNEL_TYPE_VXLAN:
1581 if (bp->vxlan_port_cnt) {
1582 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1583 udp_tunnel->udp_port);
1584 if (bp->vxlan_port != udp_tunnel->udp_port) {
1585 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1588 bp->vxlan_port_cnt++;
1592 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1593 bp->vxlan_port_cnt++;
1595 case RTE_TUNNEL_TYPE_GENEVE:
1596 if (bp->geneve_port_cnt) {
1597 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1598 udp_tunnel->udp_port);
1599 if (bp->geneve_port != udp_tunnel->udp_port) {
1600 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1603 bp->geneve_port_cnt++;
1607 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1608 bp->geneve_port_cnt++;
1611 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1614 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1620 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1621 struct rte_eth_udp_tunnel *udp_tunnel)
1623 struct bnxt *bp = eth_dev->data->dev_private;
1624 uint16_t tunnel_type = 0;
1628 rc = is_bnxt_in_error(bp);
1632 switch (udp_tunnel->prot_type) {
1633 case RTE_TUNNEL_TYPE_VXLAN:
1634 if (!bp->vxlan_port_cnt) {
1635 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1638 if (bp->vxlan_port != udp_tunnel->udp_port) {
1639 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1640 udp_tunnel->udp_port, bp->vxlan_port);
1643 if (--bp->vxlan_port_cnt)
1647 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1648 port = bp->vxlan_fw_dst_port_id;
1650 case RTE_TUNNEL_TYPE_GENEVE:
1651 if (!bp->geneve_port_cnt) {
1652 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1655 if (bp->geneve_port != udp_tunnel->udp_port) {
1656 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1657 udp_tunnel->udp_port, bp->geneve_port);
1660 if (--bp->geneve_port_cnt)
1664 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1665 port = bp->geneve_fw_dst_port_id;
1668 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1672 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1675 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1678 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1679 bp->geneve_port = 0;
1684 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1686 struct bnxt_filter_info *filter;
1687 struct bnxt_vnic_info *vnic;
1689 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1691 /* if VLAN exists && VLAN matches vlan_id
1692 * remove the MAC+VLAN filter
1693 * add a new MAC only filter
1695 * VLAN filter doesn't exist, just skip and continue
1697 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1698 filter = STAILQ_FIRST(&vnic->filter);
1700 /* Search for this matching MAC+VLAN filter */
1701 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1702 !memcmp(filter->l2_addr,
1704 RTE_ETHER_ADDR_LEN)) {
1705 /* Delete the filter */
1706 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1709 STAILQ_REMOVE(&vnic->filter, filter,
1710 bnxt_filter_info, next);
1711 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1714 "Del Vlan filter for %d\n",
1718 filter = STAILQ_NEXT(filter, next);
1723 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1725 struct bnxt_filter_info *filter;
1726 struct bnxt_vnic_info *vnic;
1728 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1729 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1730 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1732 /* Implementation notes on the use of VNIC in this command:
1734 * By default, these filters belong to default vnic for the function.
1735 * Once these filters are set up, only destination VNIC can be modified.
1736 * If the destination VNIC is not specified in this command,
1737 * then the HWRM shall only create an l2 context id.
1740 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1741 filter = STAILQ_FIRST(&vnic->filter);
1742 /* Check if the VLAN has already been added */
1744 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1745 !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1748 filter = STAILQ_NEXT(filter, next);
1751 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1752 * command to create MAC+VLAN filter with the right flags, enables set.
1754 filter = bnxt_alloc_filter(bp);
1757 "MAC/VLAN filter alloc failed\n");
1760 /* MAC + VLAN ID filter */
1761 filter->l2_ivlan = vlan_id;
1762 filter->l2_ivlan_mask = 0x0FFF;
1763 filter->enables |= en;
1764 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1766 /* Free the newly allocated filter as we were
1767 * not able to create the filter in hardware.
1769 filter->fw_l2_filter_id = UINT64_MAX;
1770 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1774 /* Add this new filter to the list */
1775 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1777 "Added Vlan filter for %d\n", vlan_id);
1781 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1782 uint16_t vlan_id, int on)
1784 struct bnxt *bp = eth_dev->data->dev_private;
1787 rc = is_bnxt_in_error(bp);
1791 /* These operations apply to ALL existing MAC/VLAN filters */
1793 return bnxt_add_vlan_filter(bp, vlan_id);
1795 return bnxt_del_vlan_filter(bp, vlan_id);
1799 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1801 struct bnxt *bp = dev->data->dev_private;
1802 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1806 rc = is_bnxt_in_error(bp);
1810 if (mask & ETH_VLAN_FILTER_MASK) {
1811 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1812 /* Remove any VLAN filters programmed */
1813 for (i = 0; i < 4095; i++)
1814 bnxt_del_vlan_filter(bp, i);
1816 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1817 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1820 if (mask & ETH_VLAN_STRIP_MASK) {
1821 /* Enable or disable VLAN stripping */
1822 for (i = 0; i < bp->nr_vnics; i++) {
1823 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1824 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1825 vnic->vlan_strip = true;
1827 vnic->vlan_strip = false;
1828 bnxt_hwrm_vnic_cfg(bp, vnic);
1830 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1831 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1834 if (mask & ETH_VLAN_EXTEND_MASK)
1835 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1841 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1842 struct rte_ether_addr *addr)
1844 struct bnxt *bp = dev->data->dev_private;
1845 /* Default Filter is tied to VNIC 0 */
1846 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1847 struct bnxt_filter_info *filter;
1850 rc = is_bnxt_in_error(bp);
1854 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1857 if (rte_is_zero_ether_addr(addr))
1860 STAILQ_FOREACH(filter, &vnic->filter, next) {
1861 /* Default Filter is at Index 0 */
1862 if (filter->mac_index != 0)
1865 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1866 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1867 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1869 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1870 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1872 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1876 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1877 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1885 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1886 struct rte_ether_addr *mc_addr_set,
1887 uint32_t nb_mc_addr)
1889 struct bnxt *bp = eth_dev->data->dev_private;
1890 char *mc_addr_list = (char *)mc_addr_set;
1891 struct bnxt_vnic_info *vnic;
1892 uint32_t off = 0, i = 0;
1895 rc = is_bnxt_in_error(bp);
1899 vnic = &bp->vnic_info[0];
1901 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1902 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1906 /* TODO Check for Duplicate mcast addresses */
1907 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1908 for (i = 0; i < nb_mc_addr; i++) {
1909 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1910 RTE_ETHER_ADDR_LEN);
1911 off += RTE_ETHER_ADDR_LEN;
1914 vnic->mc_addr_cnt = i;
1917 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1921 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1923 struct bnxt *bp = dev->data->dev_private;
1924 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1925 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1926 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1929 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1930 fw_major, fw_minor, fw_updt);
1932 ret += 1; /* add the size of '\0' */
1933 if (fw_size < (uint32_t)ret)
1940 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1941 struct rte_eth_rxq_info *qinfo)
1943 struct bnxt_rx_queue *rxq;
1945 rxq = dev->data->rx_queues[queue_id];
1947 qinfo->mp = rxq->mb_pool;
1948 qinfo->scattered_rx = dev->data->scattered_rx;
1949 qinfo->nb_desc = rxq->nb_rx_desc;
1951 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1952 qinfo->conf.rx_drop_en = 0;
1953 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1957 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1958 struct rte_eth_txq_info *qinfo)
1960 struct bnxt_tx_queue *txq;
1962 txq = dev->data->tx_queues[queue_id];
1964 qinfo->nb_desc = txq->nb_tx_desc;
1966 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1967 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1968 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1970 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1971 qinfo->conf.tx_rs_thresh = 0;
1972 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1975 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1977 struct bnxt *bp = eth_dev->data->dev_private;
1978 uint32_t new_pkt_size;
1982 rc = is_bnxt_in_error(bp);
1986 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1987 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1991 * If vector-mode tx/rx is active, disallow any MTU change that would
1992 * require scattered receive support.
1994 if (eth_dev->data->dev_started &&
1995 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1996 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1998 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2000 "MTU change would require scattered rx support. ");
2001 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2006 if (new_mtu > RTE_ETHER_MTU) {
2007 bp->flags |= BNXT_FLAG_JUMBO;
2008 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2009 DEV_RX_OFFLOAD_JUMBO_FRAME;
2011 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2012 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2013 bp->flags &= ~BNXT_FLAG_JUMBO;
2016 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2018 for (i = 0; i < bp->nr_vnics; i++) {
2019 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2022 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2023 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2024 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2028 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2029 size -= RTE_PKTMBUF_HEADROOM;
2031 if (size < new_mtu) {
2032 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2038 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2044 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2046 struct bnxt *bp = dev->data->dev_private;
2047 uint16_t vlan = bp->vlan;
2050 rc = is_bnxt_in_error(bp);
2054 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2056 "PVID cannot be modified for this function\n");
2059 bp->vlan = on ? pvid : 0;
2061 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2068 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2070 struct bnxt *bp = dev->data->dev_private;
2073 rc = is_bnxt_in_error(bp);
2077 return bnxt_hwrm_port_led_cfg(bp, true);
2081 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2083 struct bnxt *bp = dev->data->dev_private;
2086 rc = is_bnxt_in_error(bp);
2090 return bnxt_hwrm_port_led_cfg(bp, false);
2094 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2096 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2097 uint32_t desc = 0, raw_cons = 0, cons;
2098 struct bnxt_cp_ring_info *cpr;
2099 struct bnxt_rx_queue *rxq;
2100 struct rx_pkt_cmpl *rxcmp;
2103 rc = is_bnxt_in_error(bp);
2107 rxq = dev->data->rx_queues[rx_queue_id];
2109 raw_cons = cpr->cp_raw_cons;
2112 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2113 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2114 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2116 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2128 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2130 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2131 struct bnxt_rx_ring_info *rxr;
2132 struct bnxt_cp_ring_info *cpr;
2133 struct bnxt_sw_rx_bd *rx_buf;
2134 struct rx_pkt_cmpl *rxcmp;
2135 uint32_t cons, cp_cons;
2141 rc = is_bnxt_in_error(rxq->bp);
2148 if (offset >= rxq->nb_rx_desc)
2151 cons = RING_CMP(cpr->cp_ring_struct, offset);
2152 cp_cons = cpr->cp_raw_cons;
2153 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2155 if (cons > cp_cons) {
2156 if (CMPL_VALID(rxcmp, cpr->valid))
2157 return RTE_ETH_RX_DESC_DONE;
2159 if (CMPL_VALID(rxcmp, !cpr->valid))
2160 return RTE_ETH_RX_DESC_DONE;
2162 rx_buf = &rxr->rx_buf_ring[cons];
2163 if (rx_buf->mbuf == NULL)
2164 return RTE_ETH_RX_DESC_UNAVAIL;
2167 return RTE_ETH_RX_DESC_AVAIL;
2171 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2173 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2174 struct bnxt_tx_ring_info *txr;
2175 struct bnxt_cp_ring_info *cpr;
2176 struct bnxt_sw_tx_bd *tx_buf;
2177 struct tx_pkt_cmpl *txcmp;
2178 uint32_t cons, cp_cons;
2184 rc = is_bnxt_in_error(txq->bp);
2191 if (offset >= txq->nb_tx_desc)
2194 cons = RING_CMP(cpr->cp_ring_struct, offset);
2195 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2196 cp_cons = cpr->cp_raw_cons;
2198 if (cons > cp_cons) {
2199 if (CMPL_VALID(txcmp, cpr->valid))
2200 return RTE_ETH_TX_DESC_UNAVAIL;
2202 if (CMPL_VALID(txcmp, !cpr->valid))
2203 return RTE_ETH_TX_DESC_UNAVAIL;
2205 tx_buf = &txr->tx_buf_ring[cons];
2206 if (tx_buf->mbuf == NULL)
2207 return RTE_ETH_TX_DESC_DONE;
2209 return RTE_ETH_TX_DESC_FULL;
2212 static struct bnxt_filter_info *
2213 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2214 struct rte_eth_ethertype_filter *efilter,
2215 struct bnxt_vnic_info *vnic0,
2216 struct bnxt_vnic_info *vnic,
2219 struct bnxt_filter_info *mfilter = NULL;
2223 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2224 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2225 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2226 " ethertype filter.", efilter->ether_type);
2230 if (efilter->queue >= bp->rx_nr_rings) {
2231 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2236 vnic0 = &bp->vnic_info[0];
2237 vnic = &bp->vnic_info[efilter->queue];
2239 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2244 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2245 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2246 if ((!memcmp(efilter->mac_addr.addr_bytes,
2247 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2249 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2250 mfilter->ethertype == efilter->ether_type)) {
2256 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2257 if ((!memcmp(efilter->mac_addr.addr_bytes,
2258 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2259 mfilter->ethertype == efilter->ether_type &&
2261 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2275 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2276 enum rte_filter_op filter_op,
2279 struct bnxt *bp = dev->data->dev_private;
2280 struct rte_eth_ethertype_filter *efilter =
2281 (struct rte_eth_ethertype_filter *)arg;
2282 struct bnxt_filter_info *bfilter, *filter1;
2283 struct bnxt_vnic_info *vnic, *vnic0;
2286 if (filter_op == RTE_ETH_FILTER_NOP)
2290 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2295 vnic0 = &bp->vnic_info[0];
2296 vnic = &bp->vnic_info[efilter->queue];
2298 switch (filter_op) {
2299 case RTE_ETH_FILTER_ADD:
2300 bnxt_match_and_validate_ether_filter(bp, efilter,
2305 bfilter = bnxt_get_unused_filter(bp);
2306 if (bfilter == NULL) {
2308 "Not enough resources for a new filter.\n");
2311 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2312 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2313 RTE_ETHER_ADDR_LEN);
2314 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2315 RTE_ETHER_ADDR_LEN);
2316 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2317 bfilter->ethertype = efilter->ether_type;
2318 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2320 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2321 if (filter1 == NULL) {
2326 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2327 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2329 bfilter->dst_id = vnic->fw_vnic_id;
2331 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2333 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2336 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2339 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2341 case RTE_ETH_FILTER_DELETE:
2342 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2344 if (ret == -EEXIST) {
2345 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2347 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2349 bnxt_free_filter(bp, filter1);
2350 } else if (ret == 0) {
2351 PMD_DRV_LOG(ERR, "No matching filter found\n");
2355 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2361 bnxt_free_filter(bp, bfilter);
2367 parse_ntuple_filter(struct bnxt *bp,
2368 struct rte_eth_ntuple_filter *nfilter,
2369 struct bnxt_filter_info *bfilter)
2373 if (nfilter->queue >= bp->rx_nr_rings) {
2374 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2378 switch (nfilter->dst_port_mask) {
2380 bfilter->dst_port_mask = -1;
2381 bfilter->dst_port = nfilter->dst_port;
2382 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2383 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2386 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2390 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2391 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2393 switch (nfilter->proto_mask) {
2395 if (nfilter->proto == 17) /* IPPROTO_UDP */
2396 bfilter->ip_protocol = 17;
2397 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2398 bfilter->ip_protocol = 6;
2401 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2404 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2408 switch (nfilter->dst_ip_mask) {
2410 bfilter->dst_ipaddr_mask[0] = -1;
2411 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2412 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2413 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2416 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2420 switch (nfilter->src_ip_mask) {
2422 bfilter->src_ipaddr_mask[0] = -1;
2423 bfilter->src_ipaddr[0] = nfilter->src_ip;
2424 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2425 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2428 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2432 switch (nfilter->src_port_mask) {
2434 bfilter->src_port_mask = -1;
2435 bfilter->src_port = nfilter->src_port;
2436 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2437 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2440 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2445 //nfilter->priority = (uint8_t)filter->priority;
2447 bfilter->enables = en;
2451 static struct bnxt_filter_info*
2452 bnxt_match_ntuple_filter(struct bnxt *bp,
2453 struct bnxt_filter_info *bfilter,
2454 struct bnxt_vnic_info **mvnic)
2456 struct bnxt_filter_info *mfilter = NULL;
2459 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2460 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2461 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2462 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2463 bfilter->src_ipaddr_mask[0] ==
2464 mfilter->src_ipaddr_mask[0] &&
2465 bfilter->src_port == mfilter->src_port &&
2466 bfilter->src_port_mask == mfilter->src_port_mask &&
2467 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2468 bfilter->dst_ipaddr_mask[0] ==
2469 mfilter->dst_ipaddr_mask[0] &&
2470 bfilter->dst_port == mfilter->dst_port &&
2471 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2472 bfilter->flags == mfilter->flags &&
2473 bfilter->enables == mfilter->enables) {
2484 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2485 struct rte_eth_ntuple_filter *nfilter,
2486 enum rte_filter_op filter_op)
2488 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2489 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2492 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2493 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2497 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2498 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2502 bfilter = bnxt_get_unused_filter(bp);
2503 if (bfilter == NULL) {
2505 "Not enough resources for a new filter.\n");
2508 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2512 vnic = &bp->vnic_info[nfilter->queue];
2513 vnic0 = &bp->vnic_info[0];
2514 filter1 = STAILQ_FIRST(&vnic0->filter);
2515 if (filter1 == NULL) {
2520 bfilter->dst_id = vnic->fw_vnic_id;
2521 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2523 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2524 bfilter->ethertype = 0x800;
2525 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2527 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2529 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2530 bfilter->dst_id == mfilter->dst_id) {
2531 PMD_DRV_LOG(ERR, "filter exists.\n");
2534 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2535 bfilter->dst_id != mfilter->dst_id) {
2536 mfilter->dst_id = vnic->fw_vnic_id;
2537 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2538 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2539 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2540 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2541 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2544 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2545 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2550 if (filter_op == RTE_ETH_FILTER_ADD) {
2551 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2552 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2555 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2557 if (mfilter == NULL) {
2558 /* This should not happen. But for Coverity! */
2562 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2564 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2565 bnxt_free_filter(bp, mfilter);
2566 mfilter->fw_l2_filter_id = -1;
2567 bnxt_free_filter(bp, bfilter);
2568 bfilter->fw_l2_filter_id = -1;
2573 bfilter->fw_l2_filter_id = -1;
2574 bnxt_free_filter(bp, bfilter);
2579 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2580 enum rte_filter_op filter_op,
2583 struct bnxt *bp = dev->data->dev_private;
2586 if (filter_op == RTE_ETH_FILTER_NOP)
2590 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2595 switch (filter_op) {
2596 case RTE_ETH_FILTER_ADD:
2597 ret = bnxt_cfg_ntuple_filter(bp,
2598 (struct rte_eth_ntuple_filter *)arg,
2601 case RTE_ETH_FILTER_DELETE:
2602 ret = bnxt_cfg_ntuple_filter(bp,
2603 (struct rte_eth_ntuple_filter *)arg,
2607 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2615 bnxt_parse_fdir_filter(struct bnxt *bp,
2616 struct rte_eth_fdir_filter *fdir,
2617 struct bnxt_filter_info *filter)
2619 enum rte_fdir_mode fdir_mode =
2620 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2621 struct bnxt_vnic_info *vnic0, *vnic;
2622 struct bnxt_filter_info *filter1;
2626 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2629 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2630 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2632 switch (fdir->input.flow_type) {
2633 case RTE_ETH_FLOW_IPV4:
2634 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2636 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2637 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2638 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2639 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2640 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2641 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2642 filter->ip_addr_type =
2643 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2644 filter->src_ipaddr_mask[0] = 0xffffffff;
2645 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2646 filter->dst_ipaddr_mask[0] = 0xffffffff;
2647 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2648 filter->ethertype = 0x800;
2649 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2651 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2652 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2653 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2654 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2655 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2656 filter->dst_port_mask = 0xffff;
2657 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2658 filter->src_port_mask = 0xffff;
2659 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2660 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2661 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2662 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2663 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2664 filter->ip_protocol = 6;
2665 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2666 filter->ip_addr_type =
2667 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2668 filter->src_ipaddr_mask[0] = 0xffffffff;
2669 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2670 filter->dst_ipaddr_mask[0] = 0xffffffff;
2671 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2672 filter->ethertype = 0x800;
2673 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2675 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2676 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2677 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2678 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2679 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2680 filter->dst_port_mask = 0xffff;
2681 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2682 filter->src_port_mask = 0xffff;
2683 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2684 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2685 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2686 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2687 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2688 filter->ip_protocol = 17;
2689 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2690 filter->ip_addr_type =
2691 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2692 filter->src_ipaddr_mask[0] = 0xffffffff;
2693 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2694 filter->dst_ipaddr_mask[0] = 0xffffffff;
2695 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2696 filter->ethertype = 0x800;
2697 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2699 case RTE_ETH_FLOW_IPV6:
2700 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2702 filter->ip_addr_type =
2703 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2704 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2705 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2706 rte_memcpy(filter->src_ipaddr,
2707 fdir->input.flow.ipv6_flow.src_ip, 16);
2708 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2709 rte_memcpy(filter->dst_ipaddr,
2710 fdir->input.flow.ipv6_flow.dst_ip, 16);
2711 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2712 memset(filter->dst_ipaddr_mask, 0xff, 16);
2713 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2714 memset(filter->src_ipaddr_mask, 0xff, 16);
2715 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2716 filter->ethertype = 0x86dd;
2717 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2719 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2720 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2721 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2722 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2723 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2724 filter->dst_port_mask = 0xffff;
2725 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2726 filter->src_port_mask = 0xffff;
2727 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2728 filter->ip_addr_type =
2729 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2730 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2731 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2732 rte_memcpy(filter->src_ipaddr,
2733 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2734 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2735 rte_memcpy(filter->dst_ipaddr,
2736 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2737 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2738 memset(filter->dst_ipaddr_mask, 0xff, 16);
2739 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2740 memset(filter->src_ipaddr_mask, 0xff, 16);
2741 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2742 filter->ethertype = 0x86dd;
2743 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2745 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2746 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2747 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2748 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2749 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2750 filter->dst_port_mask = 0xffff;
2751 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2752 filter->src_port_mask = 0xffff;
2753 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2754 filter->ip_addr_type =
2755 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2756 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2757 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2758 rte_memcpy(filter->src_ipaddr,
2759 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2760 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2761 rte_memcpy(filter->dst_ipaddr,
2762 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2763 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2764 memset(filter->dst_ipaddr_mask, 0xff, 16);
2765 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2766 memset(filter->src_ipaddr_mask, 0xff, 16);
2767 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2768 filter->ethertype = 0x86dd;
2769 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2771 case RTE_ETH_FLOW_L2_PAYLOAD:
2772 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2773 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2775 case RTE_ETH_FLOW_VXLAN:
2776 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2778 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2779 filter->tunnel_type =
2780 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2781 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2783 case RTE_ETH_FLOW_NVGRE:
2784 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2786 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2787 filter->tunnel_type =
2788 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2789 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2791 case RTE_ETH_FLOW_UNKNOWN:
2792 case RTE_ETH_FLOW_RAW:
2793 case RTE_ETH_FLOW_FRAG_IPV4:
2794 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2795 case RTE_ETH_FLOW_FRAG_IPV6:
2796 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2797 case RTE_ETH_FLOW_IPV6_EX:
2798 case RTE_ETH_FLOW_IPV6_TCP_EX:
2799 case RTE_ETH_FLOW_IPV6_UDP_EX:
2800 case RTE_ETH_FLOW_GENEVE:
2806 vnic0 = &bp->vnic_info[0];
2807 vnic = &bp->vnic_info[fdir->action.rx_queue];
2809 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2814 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2815 rte_memcpy(filter->dst_macaddr,
2816 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2817 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2820 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2821 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2822 filter1 = STAILQ_FIRST(&vnic0->filter);
2823 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2825 filter->dst_id = vnic->fw_vnic_id;
2826 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2827 if (filter->dst_macaddr[i] == 0x00)
2828 filter1 = STAILQ_FIRST(&vnic0->filter);
2830 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2833 if (filter1 == NULL)
2836 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2837 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2839 filter->enables = en;
2844 static struct bnxt_filter_info *
2845 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2846 struct bnxt_vnic_info **mvnic)
2848 struct bnxt_filter_info *mf = NULL;
2851 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2852 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2854 STAILQ_FOREACH(mf, &vnic->filter, next) {
2855 if (mf->filter_type == nf->filter_type &&
2856 mf->flags == nf->flags &&
2857 mf->src_port == nf->src_port &&
2858 mf->src_port_mask == nf->src_port_mask &&
2859 mf->dst_port == nf->dst_port &&
2860 mf->dst_port_mask == nf->dst_port_mask &&
2861 mf->ip_protocol == nf->ip_protocol &&
2862 mf->ip_addr_type == nf->ip_addr_type &&
2863 mf->ethertype == nf->ethertype &&
2864 mf->vni == nf->vni &&
2865 mf->tunnel_type == nf->tunnel_type &&
2866 mf->l2_ovlan == nf->l2_ovlan &&
2867 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2868 mf->l2_ivlan == nf->l2_ivlan &&
2869 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2870 !memcmp(mf->l2_addr, nf->l2_addr,
2871 RTE_ETHER_ADDR_LEN) &&
2872 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2873 RTE_ETHER_ADDR_LEN) &&
2874 !memcmp(mf->src_macaddr, nf->src_macaddr,
2875 RTE_ETHER_ADDR_LEN) &&
2876 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2877 RTE_ETHER_ADDR_LEN) &&
2878 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2879 sizeof(nf->src_ipaddr)) &&
2880 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2881 sizeof(nf->src_ipaddr_mask)) &&
2882 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2883 sizeof(nf->dst_ipaddr)) &&
2884 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2885 sizeof(nf->dst_ipaddr_mask))) {
2896 bnxt_fdir_filter(struct rte_eth_dev *dev,
2897 enum rte_filter_op filter_op,
2900 struct bnxt *bp = dev->data->dev_private;
2901 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2902 struct bnxt_filter_info *filter, *match;
2903 struct bnxt_vnic_info *vnic, *mvnic;
2906 if (filter_op == RTE_ETH_FILTER_NOP)
2909 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2912 switch (filter_op) {
2913 case RTE_ETH_FILTER_ADD:
2914 case RTE_ETH_FILTER_DELETE:
2916 filter = bnxt_get_unused_filter(bp);
2917 if (filter == NULL) {
2919 "Not enough resources for a new flow.\n");
2923 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2926 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2928 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2929 vnic = &bp->vnic_info[0];
2931 vnic = &bp->vnic_info[fdir->action.rx_queue];
2933 match = bnxt_match_fdir(bp, filter, &mvnic);
2934 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2935 if (match->dst_id == vnic->fw_vnic_id) {
2936 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2940 match->dst_id = vnic->fw_vnic_id;
2941 ret = bnxt_hwrm_set_ntuple_filter(bp,
2944 STAILQ_REMOVE(&mvnic->filter, match,
2945 bnxt_filter_info, next);
2946 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2948 "Filter with matching pattern exist\n");
2950 "Updated it to new destination q\n");
2954 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2955 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2960 if (filter_op == RTE_ETH_FILTER_ADD) {
2961 ret = bnxt_hwrm_set_ntuple_filter(bp,
2966 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2968 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2969 STAILQ_REMOVE(&vnic->filter, match,
2970 bnxt_filter_info, next);
2971 bnxt_free_filter(bp, match);
2972 filter->fw_l2_filter_id = -1;
2973 bnxt_free_filter(bp, filter);
2976 case RTE_ETH_FILTER_FLUSH:
2977 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2978 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2980 STAILQ_FOREACH(filter, &vnic->filter, next) {
2981 if (filter->filter_type ==
2982 HWRM_CFA_NTUPLE_FILTER) {
2984 bnxt_hwrm_clear_ntuple_filter(bp,
2986 STAILQ_REMOVE(&vnic->filter, filter,
2987 bnxt_filter_info, next);
2992 case RTE_ETH_FILTER_UPDATE:
2993 case RTE_ETH_FILTER_STATS:
2994 case RTE_ETH_FILTER_INFO:
2995 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2998 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3005 filter->fw_l2_filter_id = -1;
3006 bnxt_free_filter(bp, filter);
3011 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3012 enum rte_filter_type filter_type,
3013 enum rte_filter_op filter_op, void *arg)
3017 ret = is_bnxt_in_error(dev->data->dev_private);
3021 switch (filter_type) {
3022 case RTE_ETH_FILTER_TUNNEL:
3024 "filter type: %d: To be implemented\n", filter_type);
3026 case RTE_ETH_FILTER_FDIR:
3027 ret = bnxt_fdir_filter(dev, filter_op, arg);
3029 case RTE_ETH_FILTER_NTUPLE:
3030 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3032 case RTE_ETH_FILTER_ETHERTYPE:
3033 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3035 case RTE_ETH_FILTER_GENERIC:
3036 if (filter_op != RTE_ETH_FILTER_GET)
3038 *(const void **)arg = &bnxt_flow_ops;
3042 "Filter type (%d) not supported", filter_type);
3049 static const uint32_t *
3050 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3052 static const uint32_t ptypes[] = {
3053 RTE_PTYPE_L2_ETHER_VLAN,
3054 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3055 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3059 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3060 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3061 RTE_PTYPE_INNER_L4_ICMP,
3062 RTE_PTYPE_INNER_L4_TCP,
3063 RTE_PTYPE_INNER_L4_UDP,
3067 if (!dev->rx_pkt_burst)
3073 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3076 uint32_t reg_base = *reg_arr & 0xfffff000;
3080 for (i = 0; i < count; i++) {
3081 if ((reg_arr[i] & 0xfffff000) != reg_base)
3084 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3085 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3089 static int bnxt_map_ptp_regs(struct bnxt *bp)
3091 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3095 reg_arr = ptp->rx_regs;
3096 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3100 reg_arr = ptp->tx_regs;
3101 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3105 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3106 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3108 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3109 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3114 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3116 rte_write32(0, (uint8_t *)bp->bar0 +
3117 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3118 rte_write32(0, (uint8_t *)bp->bar0 +
3119 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3122 static uint64_t bnxt_cc_read(struct bnxt *bp)
3126 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3127 BNXT_GRCPF_REG_SYNC_TIME));
3128 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3129 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3133 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3135 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3138 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3139 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3140 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3143 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3144 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3145 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3146 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3147 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3148 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3153 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3155 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3156 struct bnxt_pf_info *pf = &bp->pf;
3163 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3164 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3165 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3168 port_id = pf->port_id;
3169 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3170 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3172 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3173 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3174 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3175 /* bnxt_clr_rx_ts(bp); TBD */
3179 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3180 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3181 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3182 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3188 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3191 struct bnxt *bp = dev->data->dev_private;
3192 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3197 ns = rte_timespec_to_ns(ts);
3198 /* Set the timecounters to a new value. */
3205 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3207 struct bnxt *bp = dev->data->dev_private;
3208 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3209 uint64_t ns, systime_cycles = 0;
3215 if (BNXT_CHIP_THOR(bp))
3216 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3219 systime_cycles = bnxt_cc_read(bp);
3221 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3222 *ts = rte_ns_to_timespec(ns);
3227 bnxt_timesync_enable(struct rte_eth_dev *dev)
3229 struct bnxt *bp = dev->data->dev_private;
3230 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3238 ptp->tx_tstamp_en = 1;
3239 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3241 rc = bnxt_hwrm_ptp_cfg(bp);
3245 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3246 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3247 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3249 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3250 ptp->tc.cc_shift = shift;
3251 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3253 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3254 ptp->rx_tstamp_tc.cc_shift = shift;
3255 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3257 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3258 ptp->tx_tstamp_tc.cc_shift = shift;
3259 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3261 if (!BNXT_CHIP_THOR(bp))
3262 bnxt_map_ptp_regs(bp);
3268 bnxt_timesync_disable(struct rte_eth_dev *dev)
3270 struct bnxt *bp = dev->data->dev_private;
3271 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3277 ptp->tx_tstamp_en = 0;
3280 bnxt_hwrm_ptp_cfg(bp);
3282 if (!BNXT_CHIP_THOR(bp))
3283 bnxt_unmap_ptp_regs(bp);
3289 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3290 struct timespec *timestamp,
3291 uint32_t flags __rte_unused)
3293 struct bnxt *bp = dev->data->dev_private;
3294 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3295 uint64_t rx_tstamp_cycles = 0;
3301 if (BNXT_CHIP_THOR(bp))
3302 rx_tstamp_cycles = ptp->rx_timestamp;
3304 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3306 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3307 *timestamp = rte_ns_to_timespec(ns);
3312 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3313 struct timespec *timestamp)
3315 struct bnxt *bp = dev->data->dev_private;
3316 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3317 uint64_t tx_tstamp_cycles = 0;
3324 if (BNXT_CHIP_THOR(bp))
3325 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3328 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3330 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3331 *timestamp = rte_ns_to_timespec(ns);
3337 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3339 struct bnxt *bp = dev->data->dev_private;
3340 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3345 ptp->tc.nsec += delta;
3351 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3353 struct bnxt *bp = dev->data->dev_private;
3355 uint32_t dir_entries;
3356 uint32_t entry_length;
3358 rc = is_bnxt_in_error(bp);
3362 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3363 bp->pdev->addr.domain, bp->pdev->addr.bus,
3364 bp->pdev->addr.devid, bp->pdev->addr.function);
3366 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3370 return dir_entries * entry_length;
3374 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3375 struct rte_dev_eeprom_info *in_eeprom)
3377 struct bnxt *bp = dev->data->dev_private;
3382 rc = is_bnxt_in_error(bp);
3386 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3387 "len = %d\n", bp->pdev->addr.domain,
3388 bp->pdev->addr.bus, bp->pdev->addr.devid,
3389 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3391 if (in_eeprom->offset == 0) /* special offset value to get directory */
3392 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3395 index = in_eeprom->offset >> 24;
3396 offset = in_eeprom->offset & 0xffffff;
3399 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3400 in_eeprom->length, in_eeprom->data);
3405 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3408 case BNX_DIR_TYPE_CHIMP_PATCH:
3409 case BNX_DIR_TYPE_BOOTCODE:
3410 case BNX_DIR_TYPE_BOOTCODE_2:
3411 case BNX_DIR_TYPE_APE_FW:
3412 case BNX_DIR_TYPE_APE_PATCH:
3413 case BNX_DIR_TYPE_KONG_FW:
3414 case BNX_DIR_TYPE_KONG_PATCH:
3415 case BNX_DIR_TYPE_BONO_FW:
3416 case BNX_DIR_TYPE_BONO_PATCH:
3424 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3427 case BNX_DIR_TYPE_AVS:
3428 case BNX_DIR_TYPE_EXP_ROM_MBA:
3429 case BNX_DIR_TYPE_PCIE:
3430 case BNX_DIR_TYPE_TSCF_UCODE:
3431 case BNX_DIR_TYPE_EXT_PHY:
3432 case BNX_DIR_TYPE_CCM:
3433 case BNX_DIR_TYPE_ISCSI_BOOT:
3434 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3435 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3443 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3445 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3446 bnxt_dir_type_is_other_exec_format(dir_type);
3450 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3451 struct rte_dev_eeprom_info *in_eeprom)
3453 struct bnxt *bp = dev->data->dev_private;
3454 uint8_t index, dir_op;
3455 uint16_t type, ext, ordinal, attr;
3458 rc = is_bnxt_in_error(bp);
3462 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3463 "len = %d\n", bp->pdev->addr.domain,
3464 bp->pdev->addr.bus, bp->pdev->addr.devid,
3465 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3468 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3472 type = in_eeprom->magic >> 16;
3474 if (type == 0xffff) { /* special value for directory operations */
3475 index = in_eeprom->magic & 0xff;
3476 dir_op = in_eeprom->magic >> 8;
3480 case 0x0e: /* erase */
3481 if (in_eeprom->offset != ~in_eeprom->magic)
3483 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3489 /* Create or re-write an NVM item: */
3490 if (bnxt_dir_type_is_executable(type) == true)
3492 ext = in_eeprom->magic & 0xffff;
3493 ordinal = in_eeprom->offset >> 16;
3494 attr = in_eeprom->offset & 0xffff;
3496 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3497 in_eeprom->data, in_eeprom->length);
3504 static const struct eth_dev_ops bnxt_dev_ops = {
3505 .dev_infos_get = bnxt_dev_info_get_op,
3506 .dev_close = bnxt_dev_close_op,
3507 .dev_configure = bnxt_dev_configure_op,
3508 .dev_start = bnxt_dev_start_op,
3509 .dev_stop = bnxt_dev_stop_op,
3510 .dev_set_link_up = bnxt_dev_set_link_up_op,
3511 .dev_set_link_down = bnxt_dev_set_link_down_op,
3512 .stats_get = bnxt_stats_get_op,
3513 .stats_reset = bnxt_stats_reset_op,
3514 .rx_queue_setup = bnxt_rx_queue_setup_op,
3515 .rx_queue_release = bnxt_rx_queue_release_op,
3516 .tx_queue_setup = bnxt_tx_queue_setup_op,
3517 .tx_queue_release = bnxt_tx_queue_release_op,
3518 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3519 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3520 .reta_update = bnxt_reta_update_op,
3521 .reta_query = bnxt_reta_query_op,
3522 .rss_hash_update = bnxt_rss_hash_update_op,
3523 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3524 .link_update = bnxt_link_update_op,
3525 .promiscuous_enable = bnxt_promiscuous_enable_op,
3526 .promiscuous_disable = bnxt_promiscuous_disable_op,
3527 .allmulticast_enable = bnxt_allmulticast_enable_op,
3528 .allmulticast_disable = bnxt_allmulticast_disable_op,
3529 .mac_addr_add = bnxt_mac_addr_add_op,
3530 .mac_addr_remove = bnxt_mac_addr_remove_op,
3531 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3532 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3533 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3534 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3535 .vlan_filter_set = bnxt_vlan_filter_set_op,
3536 .vlan_offload_set = bnxt_vlan_offload_set_op,
3537 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3538 .mtu_set = bnxt_mtu_set_op,
3539 .mac_addr_set = bnxt_set_default_mac_addr_op,
3540 .xstats_get = bnxt_dev_xstats_get_op,
3541 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3542 .xstats_reset = bnxt_dev_xstats_reset_op,
3543 .fw_version_get = bnxt_fw_version_get,
3544 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3545 .rxq_info_get = bnxt_rxq_info_get_op,
3546 .txq_info_get = bnxt_txq_info_get_op,
3547 .dev_led_on = bnxt_dev_led_on_op,
3548 .dev_led_off = bnxt_dev_led_off_op,
3549 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3550 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3551 .rx_queue_count = bnxt_rx_queue_count_op,
3552 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3553 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3554 .rx_queue_start = bnxt_rx_queue_start,
3555 .rx_queue_stop = bnxt_rx_queue_stop,
3556 .tx_queue_start = bnxt_tx_queue_start,
3557 .tx_queue_stop = bnxt_tx_queue_stop,
3558 .filter_ctrl = bnxt_filter_ctrl_op,
3559 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3560 .get_eeprom_length = bnxt_get_eeprom_length_op,
3561 .get_eeprom = bnxt_get_eeprom_op,
3562 .set_eeprom = bnxt_set_eeprom_op,
3563 .timesync_enable = bnxt_timesync_enable,
3564 .timesync_disable = bnxt_timesync_disable,
3565 .timesync_read_time = bnxt_timesync_read_time,
3566 .timesync_write_time = bnxt_timesync_write_time,
3567 .timesync_adjust_time = bnxt_timesync_adjust_time,
3568 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3569 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3572 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3576 /* Only pre-map the reset GRC registers using window 3 */
3577 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3578 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3580 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3585 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3587 struct bnxt_error_recovery_info *info = bp->recovery_info;
3588 uint32_t reg_base = 0xffffffff;
3591 /* Only pre-map the monitoring GRC registers using window 2 */
3592 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3593 uint32_t reg = info->status_regs[i];
3595 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3598 if (reg_base == 0xffffffff)
3599 reg_base = reg & 0xfffff000;
3600 if ((reg & 0xfffff000) != reg_base)
3603 /* Use mask 0xffc as the Lower 2 bits indicates
3604 * address space location
3606 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3610 if (reg_base == 0xffffffff)
3613 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3614 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3619 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3621 struct bnxt_error_recovery_info *info = bp->recovery_info;
3622 uint32_t delay = info->delay_after_reset[index];
3623 uint32_t val = info->reset_reg_val[index];
3624 uint32_t reg = info->reset_reg[index];
3625 uint32_t type, offset;
3627 type = BNXT_FW_STATUS_REG_TYPE(reg);
3628 offset = BNXT_FW_STATUS_REG_OFF(reg);
3631 case BNXT_FW_STATUS_REG_TYPE_CFG:
3632 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3634 case BNXT_FW_STATUS_REG_TYPE_GRC:
3635 offset = bnxt_map_reset_regs(bp, offset);
3636 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3638 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3639 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3642 /* wait on a specific interval of time until core reset is complete */
3644 rte_delay_ms(delay);
3647 static void bnxt_dev_cleanup(struct bnxt *bp)
3649 bnxt_set_hwrm_link_config(bp, false);
3650 bp->link_info.link_up = 0;
3651 if (bp->dev_stopped == 0)
3652 bnxt_dev_stop_op(bp->eth_dev);
3654 bnxt_uninit_resources(bp, true);
3657 static int bnxt_restore_filters(struct bnxt *bp)
3659 struct rte_eth_dev *dev = bp->eth_dev;
3662 if (dev->data->all_multicast)
3663 ret = bnxt_allmulticast_enable_op(dev);
3664 if (dev->data->promiscuous)
3665 ret = bnxt_promiscuous_enable_op(dev);
3667 /* TODO restore other filters as well */
3671 static void bnxt_dev_recover(void *arg)
3673 struct bnxt *bp = arg;
3674 int timeout = bp->fw_reset_max_msecs;
3677 /* Clear Error flag so that device re-init should happen */
3678 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3681 rc = bnxt_hwrm_ver_get(bp);
3684 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3685 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3686 } while (rc && timeout);
3689 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3693 rc = bnxt_init_resources(bp, true);
3696 "Failed to initialize resources after reset\n");
3699 /* clear reset flag as the device is initialized now */
3700 bp->flags &= ~BNXT_FLAG_FW_RESET;
3702 rc = bnxt_dev_start_op(bp->eth_dev);
3704 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3708 rc = bnxt_restore_filters(bp);
3712 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3715 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3716 bnxt_uninit_resources(bp, false);
3717 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3720 void bnxt_dev_reset_and_resume(void *arg)
3722 struct bnxt *bp = arg;
3725 bnxt_dev_cleanup(bp);
3727 bnxt_wait_for_device_shutdown(bp);
3729 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3730 bnxt_dev_recover, (void *)bp);
3732 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3735 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3737 struct bnxt_error_recovery_info *info = bp->recovery_info;
3738 uint32_t reg = info->status_regs[index];
3739 uint32_t type, offset, val = 0;
3741 type = BNXT_FW_STATUS_REG_TYPE(reg);
3742 offset = BNXT_FW_STATUS_REG_OFF(reg);
3745 case BNXT_FW_STATUS_REG_TYPE_CFG:
3746 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3748 case BNXT_FW_STATUS_REG_TYPE_GRC:
3749 offset = info->mapped_status_regs[index];
3751 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3752 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3760 static int bnxt_fw_reset_all(struct bnxt *bp)
3762 struct bnxt_error_recovery_info *info = bp->recovery_info;
3766 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3767 /* Reset through master function driver */
3768 for (i = 0; i < info->reg_array_cnt; i++)
3769 bnxt_write_fw_reset_reg(bp, i);
3770 /* Wait for time specified by FW after triggering reset */
3771 rte_delay_ms(info->master_func_wait_period_after_reset);
3772 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3773 /* Reset with the help of Kong processor */
3774 rc = bnxt_hwrm_fw_reset(bp);
3776 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3782 static void bnxt_fw_reset_cb(void *arg)
3784 struct bnxt *bp = arg;
3785 struct bnxt_error_recovery_info *info = bp->recovery_info;
3788 /* Only Master function can do FW reset */
3789 if (bnxt_is_master_func(bp) &&
3790 bnxt_is_recovery_enabled(bp)) {
3791 rc = bnxt_fw_reset_all(bp);
3793 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3798 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3799 * EXCEPTION_FATAL_ASYNC event to all the functions
3800 * (including MASTER FUNC). After receiving this Async, all the active
3801 * drivers should treat this case as FW initiated recovery
3803 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3804 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3805 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3807 /* To recover from error */
3808 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3813 /* Driver should poll FW heartbeat, reset_counter with the frequency
3814 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3815 * When the driver detects heartbeat stop or change in reset_counter,
3816 * it has to trigger a reset to recover from the error condition.
3817 * A “master PF” is the function who will have the privilege to
3818 * initiate the chimp reset. The master PF will be elected by the
3819 * firmware and will be notified through async message.
3821 static void bnxt_check_fw_health(void *arg)
3823 struct bnxt *bp = arg;
3824 struct bnxt_error_recovery_info *info = bp->recovery_info;
3825 uint32_t val = 0, wait_msec;
3827 if (!info || !bnxt_is_recovery_enabled(bp) ||
3828 is_bnxt_in_error(bp))
3831 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3832 if (val == info->last_heart_beat)
3835 info->last_heart_beat = val;
3837 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3838 if (val != info->last_reset_counter)
3841 info->last_reset_counter = val;
3843 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3844 bnxt_check_fw_health, (void *)bp);
3848 /* Stop DMA to/from device */
3849 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3850 bp->flags |= BNXT_FLAG_FW_RESET;
3852 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3854 if (bnxt_is_master_func(bp))
3855 wait_msec = info->master_func_wait_period;
3857 wait_msec = info->normal_func_wait_period;
3859 rte_eal_alarm_set(US_PER_MS * wait_msec,
3860 bnxt_fw_reset_cb, (void *)bp);
3863 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3865 uint32_t polling_freq;
3867 if (!bnxt_is_recovery_enabled(bp))
3870 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3873 polling_freq = bp->recovery_info->driver_polling_freq;
3875 rte_eal_alarm_set(US_PER_MS * polling_freq,
3876 bnxt_check_fw_health, (void *)bp);
3877 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3880 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3882 if (!bnxt_is_recovery_enabled(bp))
3885 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3886 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3889 static bool bnxt_vf_pciid(uint16_t id)
3891 if (id == BROADCOM_DEV_ID_57304_VF ||
3892 id == BROADCOM_DEV_ID_57406_VF ||
3893 id == BROADCOM_DEV_ID_5731X_VF ||
3894 id == BROADCOM_DEV_ID_5741X_VF ||
3895 id == BROADCOM_DEV_ID_57414_VF ||
3896 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3897 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3898 id == BROADCOM_DEV_ID_58802_VF ||
3899 id == BROADCOM_DEV_ID_57500_VF1 ||
3900 id == BROADCOM_DEV_ID_57500_VF2)
3905 bool bnxt_stratus_device(struct bnxt *bp)
3907 uint16_t id = bp->pdev->id.device_id;
3909 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3910 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3911 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3916 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3918 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3919 struct bnxt *bp = eth_dev->data->dev_private;
3921 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3922 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3923 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3924 if (!bp->bar0 || !bp->doorbell_base) {
3925 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3929 bp->eth_dev = eth_dev;
3935 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3936 struct bnxt_ctx_pg_info *ctx_pg,
3941 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3942 const struct rte_memzone *mz = NULL;
3943 char mz_name[RTE_MEMZONE_NAMESIZE];
3944 rte_iova_t mz_phys_addr;
3945 uint64_t valid_bits = 0;
3952 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3954 rmem->page_size = BNXT_PAGE_SIZE;
3955 rmem->pg_arr = ctx_pg->ctx_pg_arr;
3956 rmem->dma_arr = ctx_pg->ctx_dma_arr;
3957 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3959 valid_bits = PTU_PTE_VALID;
3961 if (rmem->nr_pages > 1) {
3962 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3963 "bnxt_ctx_pg_tbl%s_%x_%d",
3964 suffix, idx, bp->eth_dev->data->port_id);
3965 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3966 mz = rte_memzone_lookup(mz_name);
3968 mz = rte_memzone_reserve_aligned(mz_name,
3972 RTE_MEMZONE_SIZE_HINT_ONLY |
3973 RTE_MEMZONE_IOVA_CONTIG,
3979 memset(mz->addr, 0, mz->len);
3980 mz_phys_addr = mz->iova;
3981 if ((unsigned long)mz->addr == mz_phys_addr) {
3983 "physical address same as virtual\n");
3984 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
3985 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3986 if (mz_phys_addr == RTE_BAD_IOVA) {
3988 "unable to map addr to phys memory\n");
3992 rte_mem_lock_page(((char *)mz->addr));
3994 rmem->pg_tbl = mz->addr;
3995 rmem->pg_tbl_map = mz_phys_addr;
3996 rmem->pg_tbl_mz = mz;
3999 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4000 suffix, idx, bp->eth_dev->data->port_id);
4001 mz = rte_memzone_lookup(mz_name);
4003 mz = rte_memzone_reserve_aligned(mz_name,
4007 RTE_MEMZONE_SIZE_HINT_ONLY |
4008 RTE_MEMZONE_IOVA_CONTIG,
4014 memset(mz->addr, 0, mz->len);
4015 mz_phys_addr = mz->iova;
4016 if ((unsigned long)mz->addr == mz_phys_addr) {
4018 "Memzone physical address same as virtual.\n");
4019 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4020 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4021 rte_mem_lock_page(((char *)mz->addr) + sz);
4022 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4023 if (mz_phys_addr == RTE_BAD_IOVA) {
4025 "unable to map addr to phys memory\n");
4030 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4031 rte_mem_lock_page(((char *)mz->addr) + sz);
4032 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4033 rmem->dma_arr[i] = mz_phys_addr + sz;
4035 if (rmem->nr_pages > 1) {
4036 if (i == rmem->nr_pages - 2 &&
4037 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4038 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4039 else if (i == rmem->nr_pages - 1 &&
4040 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4041 valid_bits |= PTU_PTE_LAST;
4043 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4049 if (rmem->vmem_size)
4050 rmem->vmem = (void **)mz->addr;
4051 rmem->dma_arr[0] = mz_phys_addr;
4055 static void bnxt_free_ctx_mem(struct bnxt *bp)
4059 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4062 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4063 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4064 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4065 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4066 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4067 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4068 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4069 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4070 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4071 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4072 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4074 for (i = 0; i < BNXT_MAX_Q; i++) {
4075 if (bp->ctx->tqm_mem[i])
4076 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4083 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4085 #define min_t(type, x, y) ({ \
4086 type __min1 = (x); \
4087 type __min2 = (y); \
4088 __min1 < __min2 ? __min1 : __min2; })
4090 #define max_t(type, x, y) ({ \
4091 type __max1 = (x); \
4092 type __max2 = (y); \
4093 __max1 > __max2 ? __max1 : __max2; })
4095 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4097 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4099 struct bnxt_ctx_pg_info *ctx_pg;
4100 struct bnxt_ctx_mem_info *ctx;
4101 uint32_t mem_size, ena, entries;
4104 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4106 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4110 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4113 ctx_pg = &ctx->qp_mem;
4114 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4115 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4116 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4120 ctx_pg = &ctx->srq_mem;
4121 ctx_pg->entries = ctx->srq_max_l2_entries;
4122 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4123 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4127 ctx_pg = &ctx->cq_mem;
4128 ctx_pg->entries = ctx->cq_max_l2_entries;
4129 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4130 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4134 ctx_pg = &ctx->vnic_mem;
4135 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4136 ctx->vnic_max_ring_table_entries;
4137 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4138 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4142 ctx_pg = &ctx->stat_mem;
4143 ctx_pg->entries = ctx->stat_max_entries;
4144 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4145 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4149 entries = ctx->qp_max_l2_entries;
4150 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4151 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4152 ctx->tqm_max_entries_per_ring);
4153 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4154 ctx_pg = ctx->tqm_mem[i];
4155 /* use min tqm entries for now. */
4156 ctx_pg->entries = entries;
4157 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4158 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4161 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4164 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4165 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4168 "Failed to configure context mem: rc = %d\n", rc);
4170 ctx->flags |= BNXT_CTX_FLAG_INITED;
4175 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4177 struct rte_pci_device *pci_dev = bp->pdev;
4178 char mz_name[RTE_MEMZONE_NAMESIZE];
4179 const struct rte_memzone *mz = NULL;
4180 uint32_t total_alloc_len;
4181 rte_iova_t mz_phys_addr;
4183 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4186 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4187 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4188 pci_dev->addr.bus, pci_dev->addr.devid,
4189 pci_dev->addr.function, "rx_port_stats");
4190 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4191 mz = rte_memzone_lookup(mz_name);
4193 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4194 sizeof(struct rx_port_stats_ext) + 512);
4196 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4199 RTE_MEMZONE_SIZE_HINT_ONLY |
4200 RTE_MEMZONE_IOVA_CONTIG);
4204 memset(mz->addr, 0, mz->len);
4205 mz_phys_addr = mz->iova;
4206 if ((unsigned long)mz->addr == mz_phys_addr) {
4208 "Memzone physical address same as virtual.\n");
4210 "Using rte_mem_virt2iova()\n");
4211 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4212 if (mz_phys_addr == RTE_BAD_IOVA) {
4214 "Can't map address to physical memory\n");
4219 bp->rx_mem_zone = (const void *)mz;
4220 bp->hw_rx_port_stats = mz->addr;
4221 bp->hw_rx_port_stats_map = mz_phys_addr;
4223 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4224 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4225 pci_dev->addr.bus, pci_dev->addr.devid,
4226 pci_dev->addr.function, "tx_port_stats");
4227 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4228 mz = rte_memzone_lookup(mz_name);
4230 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4231 sizeof(struct tx_port_stats_ext) + 512);
4233 mz = rte_memzone_reserve(mz_name,
4237 RTE_MEMZONE_SIZE_HINT_ONLY |
4238 RTE_MEMZONE_IOVA_CONTIG);
4242 memset(mz->addr, 0, mz->len);
4243 mz_phys_addr = mz->iova;
4244 if ((unsigned long)mz->addr == mz_phys_addr) {
4246 "Memzone physical address same as virtual\n");
4247 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4248 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4249 if (mz_phys_addr == RTE_BAD_IOVA) {
4251 "Can't map address to physical memory\n");
4256 bp->tx_mem_zone = (const void *)mz;
4257 bp->hw_tx_port_stats = mz->addr;
4258 bp->hw_tx_port_stats_map = mz_phys_addr;
4259 bp->flags |= BNXT_FLAG_PORT_STATS;
4261 /* Display extended statistics if FW supports it */
4262 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4263 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4264 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4267 bp->hw_rx_port_stats_ext = (void *)
4268 ((uint8_t *)bp->hw_rx_port_stats +
4269 sizeof(struct rx_port_stats));
4270 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4271 sizeof(struct rx_port_stats);
4272 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4274 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4275 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4276 bp->hw_tx_port_stats_ext = (void *)
4277 ((uint8_t *)bp->hw_tx_port_stats +
4278 sizeof(struct tx_port_stats));
4279 bp->hw_tx_port_stats_ext_map =
4280 bp->hw_tx_port_stats_map +
4281 sizeof(struct tx_port_stats);
4282 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4288 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4290 struct bnxt *bp = eth_dev->data->dev_private;
4293 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4294 RTE_ETHER_ADDR_LEN *
4297 if (eth_dev->data->mac_addrs == NULL) {
4298 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4302 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4306 /* Generate a random MAC address, if none was assigned by PF */
4307 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4308 bnxt_eth_hw_addr_random(bp->mac_addr);
4310 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4311 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4312 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4314 rc = bnxt_hwrm_set_mac(bp);
4316 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4317 RTE_ETHER_ADDR_LEN);
4321 /* Copy the permanent MAC from the FUNC_QCAPS response */
4322 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4323 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4328 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4332 /* MAC is already configured in FW */
4333 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4336 /* Restore the old MAC configured */
4337 rc = bnxt_hwrm_set_mac(bp);
4339 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4344 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4349 #define ALLOW_FUNC(x) \
4351 uint32_t arg = (x); \
4352 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4353 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4356 /* Forward all requests if firmware is new enough */
4357 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4358 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4359 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4360 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4362 PMD_DRV_LOG(WARNING,
4363 "Firmware too old for VF mailbox functionality\n");
4364 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4368 * The following are used for driver cleanup. If we disallow these,
4369 * VF drivers can't clean up cleanly.
4371 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4372 ALLOW_FUNC(HWRM_VNIC_FREE);
4373 ALLOW_FUNC(HWRM_RING_FREE);
4374 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4375 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4376 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4377 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4378 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4379 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4382 static int bnxt_init_fw(struct bnxt *bp)
4387 rc = bnxt_hwrm_ver_get(bp);
4391 rc = bnxt_hwrm_func_reset(bp);
4395 rc = bnxt_hwrm_queue_qportcfg(bp);
4399 /* Get the MAX capabilities for this function */
4400 rc = bnxt_hwrm_func_qcaps(bp);
4404 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4408 /* Get the adapter error recovery support info */
4409 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4411 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4413 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4414 mtu != bp->eth_dev->data->mtu)
4415 bp->eth_dev->data->mtu = mtu;
4417 bnxt_hwrm_port_led_qcaps(bp);
4422 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4426 rc = bnxt_init_fw(bp);
4430 if (!reconfig_dev) {
4431 rc = bnxt_setup_mac_addr(bp->eth_dev);
4435 rc = bnxt_restore_dflt_mac(bp);
4440 bnxt_config_vf_req_fwd(bp);
4442 rc = bnxt_hwrm_func_driver_register(bp);
4444 PMD_DRV_LOG(ERR, "Failed to register driver");
4449 if (bp->pdev->max_vfs) {
4450 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4452 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4456 rc = bnxt_hwrm_allocate_pf_only(bp);
4459 "Failed to allocate PF resources");
4465 rc = bnxt_alloc_mem(bp, reconfig_dev);
4469 rc = bnxt_setup_int(bp);
4475 rc = bnxt_request_int(bp);
4483 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4485 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4486 static int version_printed;
4490 if (version_printed++ == 0)
4491 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4493 eth_dev->dev_ops = &bnxt_dev_ops;
4494 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4495 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4498 * For secondary processes, we don't initialise any further
4499 * as primary has already done this work.
4501 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4504 rte_eth_copy_pci_info(eth_dev, pci_dev);
4506 bp = eth_dev->data->dev_private;
4508 bp->dev_stopped = 1;
4510 if (bnxt_vf_pciid(pci_dev->id.device_id))
4511 bp->flags |= BNXT_FLAG_VF;
4513 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4514 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4515 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4516 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4517 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4518 bp->flags |= BNXT_FLAG_THOR_CHIP;
4520 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4521 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4522 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4523 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4524 bp->flags |= BNXT_FLAG_STINGRAY;
4526 rc = bnxt_init_board(eth_dev);
4529 "Failed to initialize board rc: %x\n", rc);
4533 rc = bnxt_alloc_hwrm_resources(bp);
4536 "Failed to allocate hwrm resource rc: %x\n", rc);
4539 rc = bnxt_init_resources(bp, false);
4543 rc = bnxt_alloc_stats_mem(bp);
4548 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4549 pci_dev->mem_resource[0].phys_addr,
4550 pci_dev->mem_resource[0].addr);
4555 bnxt_dev_uninit(eth_dev);
4560 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4565 bnxt_free_mem(bp, reconfig_dev);
4566 bnxt_hwrm_func_buf_unrgtr(bp);
4567 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4568 bp->flags &= ~BNXT_FLAG_REGISTERED;
4569 bnxt_free_ctx_mem(bp);
4570 if (!reconfig_dev) {
4571 bnxt_free_hwrm_resources(bp);
4573 if (bp->recovery_info != NULL) {
4574 rte_free(bp->recovery_info);
4575 bp->recovery_info = NULL;
4579 rte_free(bp->ptp_cfg);
4585 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4587 struct bnxt *bp = eth_dev->data->dev_private;
4590 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4593 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4595 rc = bnxt_uninit_resources(bp, false);
4597 if (bp->grp_info != NULL) {
4598 rte_free(bp->grp_info);
4599 bp->grp_info = NULL;
4602 if (bp->tx_mem_zone) {
4603 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4604 bp->tx_mem_zone = NULL;
4607 if (bp->rx_mem_zone) {
4608 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4609 bp->rx_mem_zone = NULL;
4612 if (bp->dev_stopped == 0)
4613 bnxt_dev_close_op(eth_dev);
4615 rte_free(bp->pf.vf_info);
4616 eth_dev->dev_ops = NULL;
4617 eth_dev->rx_pkt_burst = NULL;
4618 eth_dev->tx_pkt_burst = NULL;
4623 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4624 struct rte_pci_device *pci_dev)
4626 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4630 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4632 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4633 return rte_eth_dev_pci_generic_remove(pci_dev,
4636 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4639 static struct rte_pci_driver bnxt_rte_pmd = {
4640 .id_table = bnxt_pci_id_map,
4641 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4642 .probe = bnxt_pci_probe,
4643 .remove = bnxt_pci_remove,
4647 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4649 if (strcmp(dev->device->driver->name, drv->driver.name))
4655 bool is_bnxt_supported(struct rte_eth_dev *dev)
4657 return is_device_supported(dev, &bnxt_rte_pmd);
4660 RTE_INIT(bnxt_init_log)
4662 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4663 if (bnxt_logtype_driver >= 0)
4664 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4667 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4668 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4669 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");