1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_reps.h"
22 #include "bnxt_ring.h"
25 #include "bnxt_stats.h"
28 #include "bnxt_vnic.h"
29 #include "hsi_struct_def_dpdk.h"
30 #include "bnxt_nvm_defs.h"
31 #include "bnxt_tf_common.h"
32 #include "ulp_flow_db.h"
34 #define DRV_MODULE_NAME "bnxt"
35 static const char bnxt_version[] =
36 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
39 * The set of PCI devices this driver supports
41 static const struct rte_pci_id bnxt_pci_id_map[] = {
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
95 { .vendor_id = 0, /* sentinel */ },
98 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
99 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
100 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
101 #define BNXT_DEVARG_REPRESENTOR "representor"
102 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
103 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
104 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
105 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
106 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
107 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
109 static const char *const bnxt_dev_args[] = {
110 BNXT_DEVARG_REPRESENTOR,
112 BNXT_DEVARG_FLOW_XSTAT,
113 BNXT_DEVARG_MAX_NUM_KFLOWS,
114 BNXT_DEVARG_REP_BASED_PF,
115 BNXT_DEVARG_REP_IS_PF,
116 BNXT_DEVARG_REP_Q_R2F,
117 BNXT_DEVARG_REP_Q_F2R,
118 BNXT_DEVARG_REP_FC_R2F,
119 BNXT_DEVARG_REP_FC_F2R,
124 * truflow == false to disable the feature
125 * truflow == true to enable the feature
127 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
130 * flow_xstat == false to disable the feature
131 * flow_xstat == true to enable the feature
133 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
136 * rep_is_pf == false to indicate VF representor
137 * rep_is_pf == true to indicate PF representor
139 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
142 * rep_based_pf == Physical index of the PF
144 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
146 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
148 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
151 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
153 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
156 * rep_fc_r2f == Flow control for the representor to endpoint direction
158 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
161 * rep_fc_f2r == Flow control for the endpoint to representor direction
163 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
166 * max_num_kflows must be >= 32
167 * and must be a power-of-2 supported value
168 * return: 1 -> invalid
171 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
173 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
178 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
179 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
180 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
181 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
182 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
183 static int bnxt_restore_vlan_filters(struct bnxt *bp);
184 static void bnxt_dev_recover(void *arg);
185 static void bnxt_free_error_recovery_info(struct bnxt *bp);
186 static void bnxt_free_rep_info(struct bnxt *bp);
188 int is_bnxt_in_error(struct bnxt *bp)
190 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
192 if (bp->flags & BNXT_FLAG_FW_RESET)
198 /***********************/
201 * High level utility functions
204 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
206 if (!BNXT_CHIP_THOR(bp))
209 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
210 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
211 BNXT_RSS_ENTRIES_PER_CTX_THOR;
214 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
216 if (!BNXT_CHIP_THOR(bp))
217 return HW_HASH_INDEX_SIZE;
219 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
222 static void bnxt_free_parent_info(struct bnxt *bp)
224 rte_free(bp->parent);
227 static void bnxt_free_pf_info(struct bnxt *bp)
232 static void bnxt_free_link_info(struct bnxt *bp)
234 rte_free(bp->link_info);
237 static void bnxt_free_leds_info(struct bnxt *bp)
246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
248 rte_free(bp->flow_stat);
249 bp->flow_stat = NULL;
252 static void bnxt_free_cos_queues(struct bnxt *bp)
254 rte_free(bp->rx_cos_queue);
255 rte_free(bp->tx_cos_queue);
258 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
260 bnxt_free_filter_mem(bp);
261 bnxt_free_vnic_attributes(bp);
262 bnxt_free_vnic_mem(bp);
264 /* tx/rx rings are configured as part of *_queue_setup callbacks.
265 * If the number of rings change across fw update,
266 * we don't have much choice except to warn the user.
270 bnxt_free_tx_rings(bp);
271 bnxt_free_rx_rings(bp);
273 bnxt_free_async_cp_ring(bp);
274 bnxt_free_rxtx_nq_ring(bp);
276 rte_free(bp->grp_info);
280 static int bnxt_alloc_parent_info(struct bnxt *bp)
282 bp->parent = rte_zmalloc("bnxt_parent_info",
283 sizeof(struct bnxt_parent_info), 0);
284 if (bp->parent == NULL)
290 static int bnxt_alloc_pf_info(struct bnxt *bp)
292 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
299 static int bnxt_alloc_link_info(struct bnxt *bp)
302 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
303 if (bp->link_info == NULL)
309 static int bnxt_alloc_leds_info(struct bnxt *bp)
314 bp->leds = rte_zmalloc("bnxt_leds",
315 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
317 if (bp->leds == NULL)
323 static int bnxt_alloc_cos_queues(struct bnxt *bp)
326 rte_zmalloc("bnxt_rx_cosq",
327 BNXT_COS_QUEUE_COUNT *
328 sizeof(struct bnxt_cos_queue_info),
330 if (bp->rx_cos_queue == NULL)
334 rte_zmalloc("bnxt_tx_cosq",
335 BNXT_COS_QUEUE_COUNT *
336 sizeof(struct bnxt_cos_queue_info),
338 if (bp->tx_cos_queue == NULL)
344 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
346 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
347 sizeof(struct bnxt_flow_stat_info), 0);
348 if (bp->flow_stat == NULL)
354 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
358 rc = bnxt_alloc_ring_grps(bp);
362 rc = bnxt_alloc_async_ring_struct(bp);
366 rc = bnxt_alloc_vnic_mem(bp);
370 rc = bnxt_alloc_vnic_attributes(bp);
374 rc = bnxt_alloc_filter_mem(bp);
378 rc = bnxt_alloc_async_cp_ring(bp);
382 rc = bnxt_alloc_rxtx_nq_ring(bp);
386 if (BNXT_FLOW_XSTATS_EN(bp)) {
387 rc = bnxt_alloc_flow_stats_info(bp);
395 bnxt_free_mem(bp, reconfig);
399 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
401 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
402 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
403 uint64_t rx_offloads = dev_conf->rxmode.offloads;
404 struct bnxt_rx_queue *rxq;
408 rc = bnxt_vnic_grp_alloc(bp, vnic);
412 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
413 vnic_id, vnic, vnic->fw_grp_ids);
415 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
419 /* Alloc RSS context only if RSS mode is enabled */
420 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
421 int j, nr_ctxs = bnxt_rss_ctxts(bp);
424 for (j = 0; j < nr_ctxs; j++) {
425 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
431 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
435 vnic->num_lb_ctxts = nr_ctxs;
439 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
440 * setting is not available at this time, it will not be
441 * configured correctly in the CFA.
443 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
444 vnic->vlan_strip = true;
446 vnic->vlan_strip = false;
448 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
452 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
456 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
457 rxq = bp->eth_dev->data->rx_queues[j];
460 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
461 j, rxq->vnic, rxq->vnic->fw_grp_ids);
463 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
464 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
466 vnic->rx_queue_cnt++;
469 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
471 rc = bnxt_vnic_rss_configure(bp, vnic);
475 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
477 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
478 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
480 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
484 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
489 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
493 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
494 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
499 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
500 " rx_fc_in_tbl.ctx_id = %d\n",
501 bp->flow_stat->rx_fc_in_tbl.va,
502 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
503 bp->flow_stat->rx_fc_in_tbl.ctx_id);
505 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
506 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
511 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
512 " rx_fc_out_tbl.ctx_id = %d\n",
513 bp->flow_stat->rx_fc_out_tbl.va,
514 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
515 bp->flow_stat->rx_fc_out_tbl.ctx_id);
517 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
518 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
523 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
524 " tx_fc_in_tbl.ctx_id = %d\n",
525 bp->flow_stat->tx_fc_in_tbl.va,
526 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
527 bp->flow_stat->tx_fc_in_tbl.ctx_id);
529 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
530 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
535 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
536 " tx_fc_out_tbl.ctx_id = %d\n",
537 bp->flow_stat->tx_fc_out_tbl.va,
538 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
539 bp->flow_stat->tx_fc_out_tbl.ctx_id);
541 memset(bp->flow_stat->rx_fc_out_tbl.va,
543 bp->flow_stat->rx_fc_out_tbl.size);
544 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
545 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
546 bp->flow_stat->rx_fc_out_tbl.ctx_id,
547 bp->flow_stat->max_fc,
552 memset(bp->flow_stat->tx_fc_out_tbl.va,
554 bp->flow_stat->tx_fc_out_tbl.size);
555 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
556 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
557 bp->flow_stat->tx_fc_out_tbl.ctx_id,
558 bp->flow_stat->max_fc,
564 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
565 struct bnxt_ctx_mem_buf_info *ctx)
570 ctx->va = rte_zmalloc(type, size, 0);
573 rte_mem_lock_page(ctx->va);
575 ctx->dma = rte_mem_virt2iova(ctx->va);
576 if (ctx->dma == RTE_BAD_IOVA)
582 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
584 struct rte_pci_device *pdev = bp->pdev;
585 char type[RTE_MEMZONE_NAMESIZE];
589 max_fc = bp->flow_stat->max_fc;
591 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
592 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
593 /* 4 bytes for each counter-id */
594 rc = bnxt_alloc_ctx_mem_buf(type,
596 &bp->flow_stat->rx_fc_in_tbl);
600 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
601 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
602 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
603 rc = bnxt_alloc_ctx_mem_buf(type,
605 &bp->flow_stat->rx_fc_out_tbl);
609 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
610 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
611 /* 4 bytes for each counter-id */
612 rc = bnxt_alloc_ctx_mem_buf(type,
614 &bp->flow_stat->tx_fc_in_tbl);
618 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
619 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
620 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
621 rc = bnxt_alloc_ctx_mem_buf(type,
623 &bp->flow_stat->tx_fc_out_tbl);
627 rc = bnxt_register_fc_ctx_mem(bp);
632 static int bnxt_init_ctx_mem(struct bnxt *bp)
636 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
637 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
638 !BNXT_FLOW_XSTATS_EN(bp))
641 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
645 rc = bnxt_init_fc_ctx_mem(bp);
650 static int bnxt_update_phy_setting(struct bnxt *bp)
652 struct rte_eth_link new;
655 rc = bnxt_get_hwrm_link_config(bp, &new);
657 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
662 * On BCM957508-N2100 adapters, FW will not allow any user other
663 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
664 * always returns link up. Force phy update always in that case.
666 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
667 rc = bnxt_set_hwrm_link_config(bp, true);
669 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
677 static int bnxt_init_chip(struct bnxt *bp)
679 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
680 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
681 uint32_t intr_vector = 0;
682 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
683 uint32_t vec = BNXT_MISC_VEC_ID;
687 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
688 bp->eth_dev->data->dev_conf.rxmode.offloads |=
689 DEV_RX_OFFLOAD_JUMBO_FRAME;
690 bp->flags |= BNXT_FLAG_JUMBO;
692 bp->eth_dev->data->dev_conf.rxmode.offloads &=
693 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
694 bp->flags &= ~BNXT_FLAG_JUMBO;
697 /* THOR does not support ring groups.
698 * But we will use the array to save RSS context IDs.
700 if (BNXT_CHIP_THOR(bp))
701 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
703 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
705 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
709 rc = bnxt_alloc_hwrm_rings(bp);
711 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
715 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
717 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
721 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
724 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
725 if (bp->rx_cos_queue[i].id != 0xff) {
726 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
730 "Num pools more than FW profile\n");
734 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
740 rc = bnxt_mq_rx_configure(bp);
742 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
746 /* VNIC configuration */
747 for (i = 0; i < bp->nr_vnics; i++) {
748 rc = bnxt_setup_one_vnic(bp, i);
753 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
756 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
760 /* check and configure queue intr-vector mapping */
761 if ((rte_intr_cap_multiple(intr_handle) ||
762 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
763 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
764 intr_vector = bp->eth_dev->data->nb_rx_queues;
765 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
766 if (intr_vector > bp->rx_cp_nr_rings) {
767 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
771 rc = rte_intr_efd_enable(intr_handle, intr_vector);
776 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
777 intr_handle->intr_vec =
778 rte_zmalloc("intr_vec",
779 bp->eth_dev->data->nb_rx_queues *
781 if (intr_handle->intr_vec == NULL) {
782 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
783 " intr_vec", bp->eth_dev->data->nb_rx_queues);
787 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
788 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
789 intr_handle->intr_vec, intr_handle->nb_efd,
790 intr_handle->max_intr);
791 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
793 intr_handle->intr_vec[queue_id] =
794 vec + BNXT_RX_VEC_START;
795 if (vec < base + intr_handle->nb_efd - 1)
800 /* enable uio/vfio intr/eventfd mapping */
801 rc = rte_intr_enable(intr_handle);
802 #ifndef RTE_EXEC_ENV_FREEBSD
803 /* In FreeBSD OS, nic_uio driver does not support interrupts */
808 rc = bnxt_update_phy_setting(bp);
812 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
814 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
819 rte_free(intr_handle->intr_vec);
821 rte_intr_efd_disable(intr_handle);
823 /* Some of the error status returned by FW may not be from errno.h */
830 static int bnxt_shutdown_nic(struct bnxt *bp)
832 bnxt_free_all_hwrm_resources(bp);
833 bnxt_free_all_filters(bp);
834 bnxt_free_all_vnics(bp);
839 * Device configuration and status function
842 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
844 uint32_t link_speed = bp->link_info->support_speeds;
845 uint32_t speed_capa = 0;
847 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
848 speed_capa |= ETH_LINK_SPEED_100M;
849 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
850 speed_capa |= ETH_LINK_SPEED_100M_HD;
851 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
852 speed_capa |= ETH_LINK_SPEED_1G;
853 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
854 speed_capa |= ETH_LINK_SPEED_2_5G;
855 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
856 speed_capa |= ETH_LINK_SPEED_10G;
857 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
858 speed_capa |= ETH_LINK_SPEED_20G;
859 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
860 speed_capa |= ETH_LINK_SPEED_25G;
861 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
862 speed_capa |= ETH_LINK_SPEED_40G;
863 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
864 speed_capa |= ETH_LINK_SPEED_50G;
865 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
866 speed_capa |= ETH_LINK_SPEED_100G;
867 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
868 speed_capa |= ETH_LINK_SPEED_50G;
869 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
870 speed_capa |= ETH_LINK_SPEED_100G;
871 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
872 speed_capa |= ETH_LINK_SPEED_200G;
874 if (bp->link_info->auto_mode ==
875 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
876 speed_capa |= ETH_LINK_SPEED_FIXED;
878 speed_capa |= ETH_LINK_SPEED_AUTONEG;
883 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
884 struct rte_eth_dev_info *dev_info)
886 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
887 struct bnxt *bp = eth_dev->data->dev_private;
888 uint16_t max_vnics, i, j, vpool, vrxq;
889 unsigned int max_rx_rings;
892 rc = is_bnxt_in_error(bp);
897 dev_info->max_mac_addrs = bp->max_l2_ctx;
898 dev_info->max_hash_mac_addrs = 0;
900 /* PF/VF specifics */
902 dev_info->max_vfs = pdev->max_vfs;
904 max_rx_rings = BNXT_MAX_RINGS(bp);
905 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
906 dev_info->max_rx_queues = max_rx_rings;
907 dev_info->max_tx_queues = max_rx_rings;
908 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
909 dev_info->hash_key_size = 40;
910 max_vnics = bp->max_vnics;
913 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
914 dev_info->max_mtu = BNXT_MAX_MTU;
916 /* Fast path specifics */
917 dev_info->min_rx_bufsize = 1;
918 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
920 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
921 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
922 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
923 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
924 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
926 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
929 dev_info->default_rxconf = (struct rte_eth_rxconf) {
935 .rx_free_thresh = 32,
936 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
939 dev_info->default_txconf = (struct rte_eth_txconf) {
945 .tx_free_thresh = 32,
948 eth_dev->data->dev_conf.intr_conf.lsc = 1;
950 eth_dev->data->dev_conf.intr_conf.rxq = 1;
951 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
952 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
953 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
954 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
956 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
957 dev_info->switch_info.name = eth_dev->device->name;
958 dev_info->switch_info.domain_id = bp->switch_domain_id;
959 dev_info->switch_info.port_id =
960 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
961 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
967 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
968 * need further investigation.
972 vpool = 64; /* ETH_64_POOLS */
973 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
974 for (i = 0; i < 4; vpool >>= 1, i++) {
975 if (max_vnics > vpool) {
976 for (j = 0; j < 5; vrxq >>= 1, j++) {
977 if (dev_info->max_rx_queues > vrxq) {
983 /* Not enough resources to support VMDq */
987 /* Not enough resources to support VMDq */
991 dev_info->max_vmdq_pools = vpool;
992 dev_info->vmdq_queue_num = vrxq;
994 dev_info->vmdq_pool_base = 0;
995 dev_info->vmdq_queue_base = 0;
1000 /* Configure the device based on the configuration provided */
1001 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1003 struct bnxt *bp = eth_dev->data->dev_private;
1004 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1007 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1008 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1009 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1010 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1012 rc = is_bnxt_in_error(bp);
1016 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1017 rc = bnxt_hwrm_check_vf_rings(bp);
1019 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1023 /* If a resource has already been allocated - in this case
1024 * it is the async completion ring, free it. Reallocate it after
1025 * resource reservation. This will ensure the resource counts
1026 * are calculated correctly.
1029 pthread_mutex_lock(&bp->def_cp_lock);
1031 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1032 bnxt_disable_int(bp);
1033 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1036 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1038 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1039 pthread_mutex_unlock(&bp->def_cp_lock);
1043 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1044 rc = bnxt_alloc_async_cp_ring(bp);
1046 pthread_mutex_unlock(&bp->def_cp_lock);
1049 bnxt_enable_int(bp);
1052 pthread_mutex_unlock(&bp->def_cp_lock);
1054 /* legacy driver needs to get updated values */
1055 rc = bnxt_hwrm_func_qcaps(bp);
1057 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1062 /* Inherit new configurations */
1063 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1064 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1065 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1066 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1067 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1069 goto resource_error;
1071 if (BNXT_HAS_RING_GRPS(bp) &&
1072 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1073 goto resource_error;
1075 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1076 bp->max_vnics < eth_dev->data->nb_rx_queues)
1077 goto resource_error;
1079 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1080 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1082 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1083 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1084 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1086 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1087 eth_dev->data->mtu =
1088 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1089 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1091 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1097 "Insufficient resources to support requested config\n");
1099 "Num Queues Requested: Tx %d, Rx %d\n",
1100 eth_dev->data->nb_tx_queues,
1101 eth_dev->data->nb_rx_queues);
1103 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1104 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1105 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1109 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1111 struct rte_eth_link *link = ð_dev->data->dev_link;
1113 if (link->link_status)
1114 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1115 eth_dev->data->port_id,
1116 (uint32_t)link->link_speed,
1117 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1118 ("full-duplex") : ("half-duplex\n"));
1120 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1121 eth_dev->data->port_id);
1125 * Determine whether the current configuration requires support for scattered
1126 * receive; return 1 if scattered receive is required and 0 if not.
1128 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1133 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1136 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1137 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1139 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1140 RTE_PKTMBUF_HEADROOM);
1141 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1147 static eth_rx_burst_t
1148 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1150 struct bnxt *bp = eth_dev->data->dev_private;
1152 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1153 #ifndef RTE_LIBRTE_IEEE1588
1155 * Vector mode receive can be enabled only if scatter rx is not
1156 * in use and rx offloads are limited to VLAN stripping and
1159 if (!eth_dev->data->scattered_rx &&
1160 !(eth_dev->data->dev_conf.rxmode.offloads &
1161 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1162 DEV_RX_OFFLOAD_KEEP_CRC |
1163 DEV_RX_OFFLOAD_JUMBO_FRAME |
1164 DEV_RX_OFFLOAD_IPV4_CKSUM |
1165 DEV_RX_OFFLOAD_UDP_CKSUM |
1166 DEV_RX_OFFLOAD_TCP_CKSUM |
1167 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1168 DEV_RX_OFFLOAD_RSS_HASH |
1169 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1170 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1171 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1172 eth_dev->data->port_id);
1173 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1174 return bnxt_recv_pkts_vec;
1176 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1177 eth_dev->data->port_id);
1179 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1180 eth_dev->data->port_id,
1181 eth_dev->data->scattered_rx,
1182 eth_dev->data->dev_conf.rxmode.offloads);
1185 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1186 return bnxt_recv_pkts;
1189 static eth_tx_burst_t
1190 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1192 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1193 #ifndef RTE_LIBRTE_IEEE1588
1194 struct bnxt *bp = eth_dev->data->dev_private;
1197 * Vector mode transmit can be enabled only if not using scatter rx
1200 if (!eth_dev->data->scattered_rx &&
1201 !eth_dev->data->dev_conf.txmode.offloads &&
1202 !BNXT_TRUFLOW_EN(bp)) {
1203 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1204 eth_dev->data->port_id);
1205 return bnxt_xmit_pkts_vec;
1207 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1208 eth_dev->data->port_id);
1210 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1211 eth_dev->data->port_id,
1212 eth_dev->data->scattered_rx,
1213 eth_dev->data->dev_conf.txmode.offloads);
1216 return bnxt_xmit_pkts;
1219 static int bnxt_handle_if_change_status(struct bnxt *bp)
1223 /* Since fw has undergone a reset and lost all contexts,
1224 * set fatal flag to not issue hwrm during cleanup
1226 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1227 bnxt_uninit_resources(bp, true);
1229 /* clear fatal flag so that re-init happens */
1230 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1231 rc = bnxt_init_resources(bp, true);
1233 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1238 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1240 struct bnxt *bp = eth_dev->data->dev_private;
1241 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1243 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1245 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1246 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1250 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1252 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1253 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1257 rc = bnxt_hwrm_if_change(bp, true);
1258 if (rc == 0 || rc != -EAGAIN)
1261 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1262 } while (retry_cnt--);
1267 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1268 rc = bnxt_handle_if_change_status(bp);
1273 bnxt_enable_int(bp);
1275 rc = bnxt_init_chip(bp);
1279 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1280 eth_dev->data->dev_started = 1;
1282 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1284 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1285 vlan_mask |= ETH_VLAN_FILTER_MASK;
1286 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1287 vlan_mask |= ETH_VLAN_STRIP_MASK;
1288 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1292 /* Initialize bnxt ULP port details */
1293 rc = bnxt_ulp_port_init(bp);
1297 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1298 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1300 bnxt_schedule_fw_health_check(bp);
1305 bnxt_shutdown_nic(bp);
1306 bnxt_free_tx_mbufs(bp);
1307 bnxt_free_rx_mbufs(bp);
1308 bnxt_hwrm_if_change(bp, false);
1309 eth_dev->data->dev_started = 0;
1313 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1315 struct bnxt *bp = eth_dev->data->dev_private;
1318 if (!bp->link_info->link_up)
1319 rc = bnxt_set_hwrm_link_config(bp, true);
1321 eth_dev->data->dev_link.link_status = 1;
1323 bnxt_print_link_info(eth_dev);
1327 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1329 struct bnxt *bp = eth_dev->data->dev_private;
1331 eth_dev->data->dev_link.link_status = 0;
1332 bnxt_set_hwrm_link_config(bp, false);
1333 bp->link_info->link_up = 0;
1338 static void bnxt_free_switch_domain(struct bnxt *bp)
1340 if (bp->switch_domain_id)
1341 rte_eth_switch_domain_free(bp->switch_domain_id);
1344 /* Unload the driver, release resources */
1345 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1347 struct bnxt *bp = eth_dev->data->dev_private;
1348 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1349 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1351 eth_dev->data->dev_started = 0;
1352 eth_dev->data->scattered_rx = 0;
1354 /* Prevent crashes when queues are still in use */
1355 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1356 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1358 bnxt_disable_int(bp);
1360 /* disable uio/vfio intr/eventfd mapping */
1361 rte_intr_disable(intr_handle);
1363 /* Stop the child representors for this device */
1364 bnxt_rep_stop_all(bp);
1366 /* delete the bnxt ULP port details */
1367 bnxt_ulp_port_deinit(bp);
1369 bnxt_cancel_fw_health_check(bp);
1371 /* Do not bring link down during reset recovery */
1372 if (!is_bnxt_in_error(bp))
1373 bnxt_dev_set_link_down_op(eth_dev);
1375 /* Wait for link to be reset and the async notification to process.
1376 * During reset recovery, there is no need to wait and
1377 * VF/NPAR functions do not have privilege to change PHY config.
1379 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1380 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1382 /* Clean queue intr-vector mapping */
1383 rte_intr_efd_disable(intr_handle);
1384 if (intr_handle->intr_vec != NULL) {
1385 rte_free(intr_handle->intr_vec);
1386 intr_handle->intr_vec = NULL;
1389 bnxt_hwrm_port_clr_stats(bp);
1390 bnxt_free_tx_mbufs(bp);
1391 bnxt_free_rx_mbufs(bp);
1392 /* Process any remaining notifications in default completion queue */
1393 bnxt_int_handler(eth_dev);
1394 bnxt_shutdown_nic(bp);
1395 bnxt_hwrm_if_change(bp, false);
1397 rte_free(bp->mark_table);
1398 bp->mark_table = NULL;
1400 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1401 bp->rx_cosq_cnt = 0;
1402 /* All filters are deleted on a port stop. */
1403 if (BNXT_FLOW_XSTATS_EN(bp))
1404 bp->flow_stat->flow_count = 0;
1407 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1409 struct bnxt *bp = eth_dev->data->dev_private;
1411 /* cancel the recovery handler before remove dev */
1412 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1413 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1414 bnxt_cancel_fc_thread(bp);
1416 if (eth_dev->data->dev_started)
1417 bnxt_dev_stop_op(eth_dev);
1419 bnxt_free_switch_domain(bp);
1421 bnxt_uninit_resources(bp, false);
1423 bnxt_free_leds_info(bp);
1424 bnxt_free_cos_queues(bp);
1425 bnxt_free_link_info(bp);
1426 bnxt_free_pf_info(bp);
1427 bnxt_free_parent_info(bp);
1429 eth_dev->dev_ops = NULL;
1430 eth_dev->rx_pkt_burst = NULL;
1431 eth_dev->tx_pkt_burst = NULL;
1433 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1434 bp->tx_mem_zone = NULL;
1435 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1436 bp->rx_mem_zone = NULL;
1438 bnxt_hwrm_free_vf_info(bp);
1440 rte_free(bp->grp_info);
1441 bp->grp_info = NULL;
1446 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1449 struct bnxt *bp = eth_dev->data->dev_private;
1450 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1451 struct bnxt_vnic_info *vnic;
1452 struct bnxt_filter_info *filter, *temp_filter;
1455 if (is_bnxt_in_error(bp))
1459 * Loop through all VNICs from the specified filter flow pools to
1460 * remove the corresponding MAC addr filter
1462 for (i = 0; i < bp->nr_vnics; i++) {
1463 if (!(pool_mask & (1ULL << i)))
1466 vnic = &bp->vnic_info[i];
1467 filter = STAILQ_FIRST(&vnic->filter);
1469 temp_filter = STAILQ_NEXT(filter, next);
1470 if (filter->mac_index == index) {
1471 STAILQ_REMOVE(&vnic->filter, filter,
1472 bnxt_filter_info, next);
1473 bnxt_hwrm_clear_l2_filter(bp, filter);
1474 bnxt_free_filter(bp, filter);
1476 filter = temp_filter;
1481 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1482 struct rte_ether_addr *mac_addr, uint32_t index,
1485 struct bnxt_filter_info *filter;
1488 /* Attach requested MAC address to the new l2_filter */
1489 STAILQ_FOREACH(filter, &vnic->filter, next) {
1490 if (filter->mac_index == index) {
1492 "MAC addr already existed for pool %d\n",
1498 filter = bnxt_alloc_filter(bp);
1500 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1504 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1505 * if the MAC that's been programmed now is a different one, then,
1506 * copy that addr to filter->l2_addr
1509 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1510 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1512 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1514 filter->mac_index = index;
1515 if (filter->mac_index == 0)
1516 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1518 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1520 bnxt_free_filter(bp, filter);
1526 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1527 struct rte_ether_addr *mac_addr,
1528 uint32_t index, uint32_t pool)
1530 struct bnxt *bp = eth_dev->data->dev_private;
1531 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1534 rc = is_bnxt_in_error(bp);
1538 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1539 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1544 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1548 /* Filter settings will get applied when port is started */
1549 if (!eth_dev->data->dev_started)
1552 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1557 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1558 bool exp_link_status)
1561 struct bnxt *bp = eth_dev->data->dev_private;
1562 struct rte_eth_link new;
1563 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1564 BNXT_LINK_DOWN_WAIT_CNT;
1566 rc = is_bnxt_in_error(bp);
1570 memset(&new, 0, sizeof(new));
1572 /* Retrieve link info from hardware */
1573 rc = bnxt_get_hwrm_link_config(bp, &new);
1575 new.link_speed = ETH_LINK_SPEED_100M;
1576 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1578 "Failed to retrieve link rc = 0x%x!\n", rc);
1582 if (!wait_to_complete || new.link_status == exp_link_status)
1585 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1589 /* Timed out or success */
1590 if (new.link_status != eth_dev->data->dev_link.link_status ||
1591 new.link_speed != eth_dev->data->dev_link.link_speed) {
1592 rte_eth_linkstatus_set(eth_dev, &new);
1594 rte_eth_dev_callback_process(eth_dev,
1595 RTE_ETH_EVENT_INTR_LSC,
1598 bnxt_print_link_info(eth_dev);
1604 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1605 int wait_to_complete)
1607 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1610 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1612 struct bnxt *bp = eth_dev->data->dev_private;
1613 struct bnxt_vnic_info *vnic;
1617 rc = is_bnxt_in_error(bp);
1621 /* Filter settings will get applied when port is started */
1622 if (!eth_dev->data->dev_started)
1625 if (bp->vnic_info == NULL)
1628 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1630 old_flags = vnic->flags;
1631 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1632 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1634 vnic->flags = old_flags;
1639 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1641 struct bnxt *bp = eth_dev->data->dev_private;
1642 struct bnxt_vnic_info *vnic;
1646 rc = is_bnxt_in_error(bp);
1650 /* Filter settings will get applied when port is started */
1651 if (!eth_dev->data->dev_started)
1654 if (bp->vnic_info == NULL)
1657 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1659 old_flags = vnic->flags;
1660 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1661 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1663 vnic->flags = old_flags;
1668 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1670 struct bnxt *bp = eth_dev->data->dev_private;
1671 struct bnxt_vnic_info *vnic;
1675 rc = is_bnxt_in_error(bp);
1679 /* Filter settings will get applied when port is started */
1680 if (!eth_dev->data->dev_started)
1683 if (bp->vnic_info == NULL)
1686 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1688 old_flags = vnic->flags;
1689 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1690 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1692 vnic->flags = old_flags;
1697 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1699 struct bnxt *bp = eth_dev->data->dev_private;
1700 struct bnxt_vnic_info *vnic;
1704 rc = is_bnxt_in_error(bp);
1708 /* Filter settings will get applied when port is started */
1709 if (!eth_dev->data->dev_started)
1712 if (bp->vnic_info == NULL)
1715 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1717 old_flags = vnic->flags;
1718 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1719 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1721 vnic->flags = old_flags;
1726 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1727 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1729 if (qid >= bp->rx_nr_rings)
1732 return bp->eth_dev->data->rx_queues[qid];
1735 /* Return rxq corresponding to a given rss table ring/group ID. */
1736 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1738 struct bnxt_rx_queue *rxq;
1741 if (!BNXT_HAS_RING_GRPS(bp)) {
1742 for (i = 0; i < bp->rx_nr_rings; i++) {
1743 rxq = bp->eth_dev->data->rx_queues[i];
1744 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1748 for (i = 0; i < bp->rx_nr_rings; i++) {
1749 if (bp->grp_info[i].fw_grp_id == fwr)
1754 return INVALID_HW_RING_ID;
1757 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1758 struct rte_eth_rss_reta_entry64 *reta_conf,
1761 struct bnxt *bp = eth_dev->data->dev_private;
1762 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1763 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1764 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1768 rc = is_bnxt_in_error(bp);
1772 if (!vnic->rss_table)
1775 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1778 if (reta_size != tbl_size) {
1779 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1780 "(%d) must equal the size supported by the hardware "
1781 "(%d)\n", reta_size, tbl_size);
1785 for (i = 0; i < reta_size; i++) {
1786 struct bnxt_rx_queue *rxq;
1788 idx = i / RTE_RETA_GROUP_SIZE;
1789 sft = i % RTE_RETA_GROUP_SIZE;
1791 if (!(reta_conf[idx].mask & (1ULL << sft)))
1794 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1796 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1800 if (BNXT_CHIP_THOR(bp)) {
1801 vnic->rss_table[i * 2] =
1802 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1803 vnic->rss_table[i * 2 + 1] =
1804 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1806 vnic->rss_table[i] =
1807 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1811 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1815 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1816 struct rte_eth_rss_reta_entry64 *reta_conf,
1819 struct bnxt *bp = eth_dev->data->dev_private;
1820 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1821 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1822 uint16_t idx, sft, i;
1825 rc = is_bnxt_in_error(bp);
1829 /* Retrieve from the default VNIC */
1832 if (!vnic->rss_table)
1835 if (reta_size != tbl_size) {
1836 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1837 "(%d) must equal the size supported by the hardware "
1838 "(%d)\n", reta_size, tbl_size);
1842 for (idx = 0, i = 0; i < reta_size; i++) {
1843 idx = i / RTE_RETA_GROUP_SIZE;
1844 sft = i % RTE_RETA_GROUP_SIZE;
1846 if (reta_conf[idx].mask & (1ULL << sft)) {
1849 if (BNXT_CHIP_THOR(bp))
1850 qid = bnxt_rss_to_qid(bp,
1851 vnic->rss_table[i * 2]);
1853 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1855 if (qid == INVALID_HW_RING_ID) {
1856 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1859 reta_conf[idx].reta[sft] = qid;
1866 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1867 struct rte_eth_rss_conf *rss_conf)
1869 struct bnxt *bp = eth_dev->data->dev_private;
1870 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1871 struct bnxt_vnic_info *vnic;
1874 rc = is_bnxt_in_error(bp);
1879 * If RSS enablement were different than dev_configure,
1880 * then return -EINVAL
1882 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1883 if (!rss_conf->rss_hf)
1884 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1886 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1890 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1891 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1895 /* Update the default RSS VNIC(s) */
1896 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1897 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1900 * If hashkey is not specified, use the previously configured
1903 if (!rss_conf->rss_key)
1906 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1908 "Invalid hashkey length, should be 16 bytes\n");
1911 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1914 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1918 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1919 struct rte_eth_rss_conf *rss_conf)
1921 struct bnxt *bp = eth_dev->data->dev_private;
1922 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1924 uint32_t hash_types;
1926 rc = is_bnxt_in_error(bp);
1930 /* RSS configuration is the same for all VNICs */
1931 if (vnic && vnic->rss_hash_key) {
1932 if (rss_conf->rss_key) {
1933 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1934 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1935 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1938 hash_types = vnic->hash_type;
1939 rss_conf->rss_hf = 0;
1940 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1941 rss_conf->rss_hf |= ETH_RSS_IPV4;
1942 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1944 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1945 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1947 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1949 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1950 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1952 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1954 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1955 rss_conf->rss_hf |= ETH_RSS_IPV6;
1956 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1958 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1959 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1961 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1963 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1964 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1966 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1970 "Unknown RSS config from firmware (%08x), RSS disabled",
1975 rss_conf->rss_hf = 0;
1980 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1981 struct rte_eth_fc_conf *fc_conf)
1983 struct bnxt *bp = dev->data->dev_private;
1984 struct rte_eth_link link_info;
1987 rc = is_bnxt_in_error(bp);
1991 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1995 memset(fc_conf, 0, sizeof(*fc_conf));
1996 if (bp->link_info->auto_pause)
1997 fc_conf->autoneg = 1;
1998 switch (bp->link_info->pause) {
2000 fc_conf->mode = RTE_FC_NONE;
2002 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2003 fc_conf->mode = RTE_FC_TX_PAUSE;
2005 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2006 fc_conf->mode = RTE_FC_RX_PAUSE;
2008 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2009 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2010 fc_conf->mode = RTE_FC_FULL;
2016 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2017 struct rte_eth_fc_conf *fc_conf)
2019 struct bnxt *bp = dev->data->dev_private;
2022 rc = is_bnxt_in_error(bp);
2026 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2027 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2031 switch (fc_conf->mode) {
2033 bp->link_info->auto_pause = 0;
2034 bp->link_info->force_pause = 0;
2036 case RTE_FC_RX_PAUSE:
2037 if (fc_conf->autoneg) {
2038 bp->link_info->auto_pause =
2039 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2040 bp->link_info->force_pause = 0;
2042 bp->link_info->auto_pause = 0;
2043 bp->link_info->force_pause =
2044 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2047 case RTE_FC_TX_PAUSE:
2048 if (fc_conf->autoneg) {
2049 bp->link_info->auto_pause =
2050 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2051 bp->link_info->force_pause = 0;
2053 bp->link_info->auto_pause = 0;
2054 bp->link_info->force_pause =
2055 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2059 if (fc_conf->autoneg) {
2060 bp->link_info->auto_pause =
2061 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2062 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2063 bp->link_info->force_pause = 0;
2065 bp->link_info->auto_pause = 0;
2066 bp->link_info->force_pause =
2067 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2068 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2072 return bnxt_set_hwrm_link_config(bp, true);
2075 /* Add UDP tunneling port */
2077 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2078 struct rte_eth_udp_tunnel *udp_tunnel)
2080 struct bnxt *bp = eth_dev->data->dev_private;
2081 uint16_t tunnel_type = 0;
2084 rc = is_bnxt_in_error(bp);
2088 switch (udp_tunnel->prot_type) {
2089 case RTE_TUNNEL_TYPE_VXLAN:
2090 if (bp->vxlan_port_cnt) {
2091 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2092 udp_tunnel->udp_port);
2093 if (bp->vxlan_port != udp_tunnel->udp_port) {
2094 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2097 bp->vxlan_port_cnt++;
2101 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2102 bp->vxlan_port_cnt++;
2104 case RTE_TUNNEL_TYPE_GENEVE:
2105 if (bp->geneve_port_cnt) {
2106 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2107 udp_tunnel->udp_port);
2108 if (bp->geneve_port != udp_tunnel->udp_port) {
2109 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2112 bp->geneve_port_cnt++;
2116 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2117 bp->geneve_port_cnt++;
2120 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2123 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2129 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2130 struct rte_eth_udp_tunnel *udp_tunnel)
2132 struct bnxt *bp = eth_dev->data->dev_private;
2133 uint16_t tunnel_type = 0;
2137 rc = is_bnxt_in_error(bp);
2141 switch (udp_tunnel->prot_type) {
2142 case RTE_TUNNEL_TYPE_VXLAN:
2143 if (!bp->vxlan_port_cnt) {
2144 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2147 if (bp->vxlan_port != udp_tunnel->udp_port) {
2148 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2149 udp_tunnel->udp_port, bp->vxlan_port);
2152 if (--bp->vxlan_port_cnt)
2156 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2157 port = bp->vxlan_fw_dst_port_id;
2159 case RTE_TUNNEL_TYPE_GENEVE:
2160 if (!bp->geneve_port_cnt) {
2161 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2164 if (bp->geneve_port != udp_tunnel->udp_port) {
2165 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2166 udp_tunnel->udp_port, bp->geneve_port);
2169 if (--bp->geneve_port_cnt)
2173 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2174 port = bp->geneve_fw_dst_port_id;
2177 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2181 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2184 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2187 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2188 bp->geneve_port = 0;
2193 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2195 struct bnxt_filter_info *filter;
2196 struct bnxt_vnic_info *vnic;
2198 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2200 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2201 filter = STAILQ_FIRST(&vnic->filter);
2203 /* Search for this matching MAC+VLAN filter */
2204 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2205 /* Delete the filter */
2206 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2209 STAILQ_REMOVE(&vnic->filter, filter,
2210 bnxt_filter_info, next);
2211 bnxt_free_filter(bp, filter);
2213 "Deleted vlan filter for %d\n",
2217 filter = STAILQ_NEXT(filter, next);
2222 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2224 struct bnxt_filter_info *filter;
2225 struct bnxt_vnic_info *vnic;
2227 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2228 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2229 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2231 /* Implementation notes on the use of VNIC in this command:
2233 * By default, these filters belong to default vnic for the function.
2234 * Once these filters are set up, only destination VNIC can be modified.
2235 * If the destination VNIC is not specified in this command,
2236 * then the HWRM shall only create an l2 context id.
2239 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2240 filter = STAILQ_FIRST(&vnic->filter);
2241 /* Check if the VLAN has already been added */
2243 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2246 filter = STAILQ_NEXT(filter, next);
2249 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2250 * command to create MAC+VLAN filter with the right flags, enables set.
2252 filter = bnxt_alloc_filter(bp);
2255 "MAC/VLAN filter alloc failed\n");
2258 /* MAC + VLAN ID filter */
2259 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2260 * untagged packets are received
2262 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2263 * packets and only the programmed vlan's packets are received
2265 filter->l2_ivlan = vlan_id;
2266 filter->l2_ivlan_mask = 0x0FFF;
2267 filter->enables |= en;
2268 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2270 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2272 /* Free the newly allocated filter as we were
2273 * not able to create the filter in hardware.
2275 bnxt_free_filter(bp, filter);
2279 filter->mac_index = 0;
2280 /* Add this new filter to the list */
2282 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2284 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2287 "Added Vlan filter for %d\n", vlan_id);
2291 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2292 uint16_t vlan_id, int on)
2294 struct bnxt *bp = eth_dev->data->dev_private;
2297 rc = is_bnxt_in_error(bp);
2301 if (!eth_dev->data->dev_started) {
2302 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2306 /* These operations apply to ALL existing MAC/VLAN filters */
2308 return bnxt_add_vlan_filter(bp, vlan_id);
2310 return bnxt_del_vlan_filter(bp, vlan_id);
2313 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2314 struct bnxt_vnic_info *vnic)
2316 struct bnxt_filter_info *filter;
2319 filter = STAILQ_FIRST(&vnic->filter);
2321 if (filter->mac_index == 0 &&
2322 !memcmp(filter->l2_addr, bp->mac_addr,
2323 RTE_ETHER_ADDR_LEN)) {
2324 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2326 STAILQ_REMOVE(&vnic->filter, filter,
2327 bnxt_filter_info, next);
2328 bnxt_free_filter(bp, filter);
2332 filter = STAILQ_NEXT(filter, next);
2338 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2340 struct bnxt_vnic_info *vnic;
2344 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2345 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2346 /* Remove any VLAN filters programmed */
2347 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2348 bnxt_del_vlan_filter(bp, i);
2350 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2354 /* Default filter will allow packets that match the
2355 * dest mac. So, it has to be deleted, otherwise, we
2356 * will endup receiving vlan packets for which the
2357 * filter is not programmed, when hw-vlan-filter
2358 * configuration is ON
2360 bnxt_del_dflt_mac_filter(bp, vnic);
2361 /* This filter will allow only untagged packets */
2362 bnxt_add_vlan_filter(bp, 0);
2364 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2365 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2370 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2372 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2376 /* Destroy vnic filters and vnic */
2377 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2378 DEV_RX_OFFLOAD_VLAN_FILTER) {
2379 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2380 bnxt_del_vlan_filter(bp, i);
2382 bnxt_del_dflt_mac_filter(bp, vnic);
2384 rc = bnxt_hwrm_vnic_free(bp, vnic);
2388 rte_free(vnic->fw_grp_ids);
2389 vnic->fw_grp_ids = NULL;
2391 vnic->rx_queue_cnt = 0;
2397 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2399 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2402 /* Destroy, recreate and reconfigure the default vnic */
2403 rc = bnxt_free_one_vnic(bp, 0);
2407 /* default vnic 0 */
2408 rc = bnxt_setup_one_vnic(bp, 0);
2412 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2413 DEV_RX_OFFLOAD_VLAN_FILTER) {
2414 rc = bnxt_add_vlan_filter(bp, 0);
2417 rc = bnxt_restore_vlan_filters(bp);
2421 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2426 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2430 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2431 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2437 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2439 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2440 struct bnxt *bp = dev->data->dev_private;
2443 rc = is_bnxt_in_error(bp);
2447 /* Filter settings will get applied when port is started */
2448 if (!dev->data->dev_started)
2451 if (mask & ETH_VLAN_FILTER_MASK) {
2452 /* Enable or disable VLAN filtering */
2453 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2458 if (mask & ETH_VLAN_STRIP_MASK) {
2459 /* Enable or disable VLAN stripping */
2460 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2465 if (mask & ETH_VLAN_EXTEND_MASK) {
2466 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2467 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2469 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2476 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2479 struct bnxt *bp = dev->data->dev_private;
2480 int qinq = dev->data->dev_conf.rxmode.offloads &
2481 DEV_RX_OFFLOAD_VLAN_EXTEND;
2483 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2484 vlan_type != ETH_VLAN_TYPE_OUTER) {
2486 "Unsupported vlan type.");
2491 "QinQ not enabled. Needs to be ON as we can "
2492 "accelerate only outer vlan\n");
2496 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2498 case RTE_ETHER_TYPE_QINQ:
2500 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2502 case RTE_ETHER_TYPE_VLAN:
2504 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2506 case RTE_ETHER_TYPE_QINQ1:
2508 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2510 case RTE_ETHER_TYPE_QINQ2:
2512 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2514 case RTE_ETHER_TYPE_QINQ3:
2516 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2519 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2522 bp->outer_tpid_bd |= tpid;
2523 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2524 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2526 "Can accelerate only outer vlan in QinQ\n");
2534 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2535 struct rte_ether_addr *addr)
2537 struct bnxt *bp = dev->data->dev_private;
2538 /* Default Filter is tied to VNIC 0 */
2539 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2542 rc = is_bnxt_in_error(bp);
2546 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2549 if (rte_is_zero_ether_addr(addr))
2552 /* Filter settings will get applied when port is started */
2553 if (!dev->data->dev_started)
2556 /* Check if the requested MAC is already added */
2557 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2560 /* Destroy filter and re-create it */
2561 bnxt_del_dflt_mac_filter(bp, vnic);
2563 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2564 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2565 /* This filter will allow only untagged packets */
2566 rc = bnxt_add_vlan_filter(bp, 0);
2568 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2571 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2576 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2577 struct rte_ether_addr *mc_addr_set,
2578 uint32_t nb_mc_addr)
2580 struct bnxt *bp = eth_dev->data->dev_private;
2581 char *mc_addr_list = (char *)mc_addr_set;
2582 struct bnxt_vnic_info *vnic;
2583 uint32_t off = 0, i = 0;
2586 rc = is_bnxt_in_error(bp);
2590 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2592 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2593 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2597 /* TODO Check for Duplicate mcast addresses */
2598 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2599 for (i = 0; i < nb_mc_addr; i++) {
2600 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2601 RTE_ETHER_ADDR_LEN);
2602 off += RTE_ETHER_ADDR_LEN;
2605 vnic->mc_addr_cnt = i;
2606 if (vnic->mc_addr_cnt)
2607 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2609 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2612 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2616 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2618 struct bnxt *bp = dev->data->dev_private;
2619 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2620 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2621 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2622 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2625 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2626 fw_major, fw_minor, fw_updt, fw_rsvd);
2628 ret += 1; /* add the size of '\0' */
2629 if (fw_size < (uint32_t)ret)
2636 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2637 struct rte_eth_rxq_info *qinfo)
2639 struct bnxt *bp = dev->data->dev_private;
2640 struct bnxt_rx_queue *rxq;
2642 if (is_bnxt_in_error(bp))
2645 rxq = dev->data->rx_queues[queue_id];
2647 qinfo->mp = rxq->mb_pool;
2648 qinfo->scattered_rx = dev->data->scattered_rx;
2649 qinfo->nb_desc = rxq->nb_rx_desc;
2651 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2652 qinfo->conf.rx_drop_en = rxq->drop_en;
2653 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2654 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2658 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2659 struct rte_eth_txq_info *qinfo)
2661 struct bnxt *bp = dev->data->dev_private;
2662 struct bnxt_tx_queue *txq;
2664 if (is_bnxt_in_error(bp))
2667 txq = dev->data->tx_queues[queue_id];
2669 qinfo->nb_desc = txq->nb_tx_desc;
2671 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2672 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2673 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2675 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2676 qinfo->conf.tx_rs_thresh = 0;
2677 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2678 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
2681 static const struct {
2682 eth_rx_burst_t pkt_burst;
2684 } bnxt_rx_burst_info[] = {
2685 {bnxt_recv_pkts, "Scalar"},
2686 #if defined(RTE_ARCH_X86)
2687 {bnxt_recv_pkts_vec, "Vector SSE"},
2688 #elif defined(RTE_ARCH_ARM64)
2689 {bnxt_recv_pkts_vec, "Vector Neon"},
2694 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2695 struct rte_eth_burst_mode *mode)
2697 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2700 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2701 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2702 snprintf(mode->info, sizeof(mode->info), "%s",
2703 bnxt_rx_burst_info[i].info);
2711 static const struct {
2712 eth_tx_burst_t pkt_burst;
2714 } bnxt_tx_burst_info[] = {
2715 {bnxt_xmit_pkts, "Scalar"},
2716 #if defined(RTE_ARCH_X86)
2717 {bnxt_xmit_pkts_vec, "Vector SSE"},
2718 #elif defined(RTE_ARCH_ARM64)
2719 {bnxt_xmit_pkts_vec, "Vector Neon"},
2724 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2725 struct rte_eth_burst_mode *mode)
2727 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2730 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2731 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2732 snprintf(mode->info, sizeof(mode->info), "%s",
2733 bnxt_tx_burst_info[i].info);
2741 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2743 struct bnxt *bp = eth_dev->data->dev_private;
2744 uint32_t new_pkt_size;
2748 rc = is_bnxt_in_error(bp);
2752 /* Exit if receive queues are not configured yet */
2753 if (!eth_dev->data->nb_rx_queues)
2756 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2757 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2760 * Disallow any MTU change that would require scattered receive support
2761 * if it is not already enabled.
2763 if (eth_dev->data->dev_started &&
2764 !eth_dev->data->scattered_rx &&
2766 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2768 "MTU change would require scattered rx support. ");
2769 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2773 if (new_mtu > RTE_ETHER_MTU) {
2774 bp->flags |= BNXT_FLAG_JUMBO;
2775 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2776 DEV_RX_OFFLOAD_JUMBO_FRAME;
2778 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2779 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2780 bp->flags &= ~BNXT_FLAG_JUMBO;
2783 /* Is there a change in mtu setting? */
2784 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2787 for (i = 0; i < bp->nr_vnics; i++) {
2788 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2791 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2792 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2796 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2797 size -= RTE_PKTMBUF_HEADROOM;
2799 if (size < new_mtu) {
2800 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2807 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2809 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2815 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2817 struct bnxt *bp = dev->data->dev_private;
2818 uint16_t vlan = bp->vlan;
2821 rc = is_bnxt_in_error(bp);
2825 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2827 "PVID cannot be modified for this function\n");
2830 bp->vlan = on ? pvid : 0;
2832 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2839 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2841 struct bnxt *bp = dev->data->dev_private;
2844 rc = is_bnxt_in_error(bp);
2848 return bnxt_hwrm_port_led_cfg(bp, true);
2852 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2854 struct bnxt *bp = dev->data->dev_private;
2857 rc = is_bnxt_in_error(bp);
2861 return bnxt_hwrm_port_led_cfg(bp, false);
2865 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2867 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2868 uint32_t desc = 0, raw_cons = 0, cons;
2869 struct bnxt_cp_ring_info *cpr;
2870 struct bnxt_rx_queue *rxq;
2871 struct rx_pkt_cmpl *rxcmp;
2874 rc = is_bnxt_in_error(bp);
2878 rxq = dev->data->rx_queues[rx_queue_id];
2880 raw_cons = cpr->cp_raw_cons;
2883 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2884 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2885 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2887 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2899 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2901 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2902 struct bnxt_rx_ring_info *rxr;
2903 struct bnxt_cp_ring_info *cpr;
2904 struct rte_mbuf *rx_buf;
2905 struct rx_pkt_cmpl *rxcmp;
2906 uint32_t cons, cp_cons;
2912 rc = is_bnxt_in_error(rxq->bp);
2919 if (offset >= rxq->nb_rx_desc)
2922 cons = RING_CMP(cpr->cp_ring_struct, offset);
2923 cp_cons = cpr->cp_raw_cons;
2924 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2926 if (cons > cp_cons) {
2927 if (CMPL_VALID(rxcmp, cpr->valid))
2928 return RTE_ETH_RX_DESC_DONE;
2930 if (CMPL_VALID(rxcmp, !cpr->valid))
2931 return RTE_ETH_RX_DESC_DONE;
2933 rx_buf = rxr->rx_buf_ring[cons];
2934 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2935 return RTE_ETH_RX_DESC_UNAVAIL;
2938 return RTE_ETH_RX_DESC_AVAIL;
2942 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2944 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2945 struct bnxt_tx_ring_info *txr;
2946 struct bnxt_cp_ring_info *cpr;
2947 struct bnxt_sw_tx_bd *tx_buf;
2948 struct tx_pkt_cmpl *txcmp;
2949 uint32_t cons, cp_cons;
2955 rc = is_bnxt_in_error(txq->bp);
2962 if (offset >= txq->nb_tx_desc)
2965 cons = RING_CMP(cpr->cp_ring_struct, offset);
2966 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2967 cp_cons = cpr->cp_raw_cons;
2969 if (cons > cp_cons) {
2970 if (CMPL_VALID(txcmp, cpr->valid))
2971 return RTE_ETH_TX_DESC_UNAVAIL;
2973 if (CMPL_VALID(txcmp, !cpr->valid))
2974 return RTE_ETH_TX_DESC_UNAVAIL;
2976 tx_buf = &txr->tx_buf_ring[cons];
2977 if (tx_buf->mbuf == NULL)
2978 return RTE_ETH_TX_DESC_DONE;
2980 return RTE_ETH_TX_DESC_FULL;
2983 static struct bnxt_filter_info *
2984 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2985 struct rte_eth_ethertype_filter *efilter,
2986 struct bnxt_vnic_info *vnic0,
2987 struct bnxt_vnic_info *vnic,
2990 struct bnxt_filter_info *mfilter = NULL;
2994 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2995 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2996 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2997 " ethertype filter.", efilter->ether_type);
3001 if (efilter->queue >= bp->rx_nr_rings) {
3002 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3007 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3008 vnic = &bp->vnic_info[efilter->queue];
3010 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3015 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3016 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
3017 if ((!memcmp(efilter->mac_addr.addr_bytes,
3018 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3020 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3021 mfilter->ethertype == efilter->ether_type)) {
3027 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3028 if ((!memcmp(efilter->mac_addr.addr_bytes,
3029 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3030 mfilter->ethertype == efilter->ether_type &&
3032 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3046 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3047 enum rte_filter_op filter_op,
3050 struct bnxt *bp = dev->data->dev_private;
3051 struct rte_eth_ethertype_filter *efilter =
3052 (struct rte_eth_ethertype_filter *)arg;
3053 struct bnxt_filter_info *bfilter, *filter1;
3054 struct bnxt_vnic_info *vnic, *vnic0;
3057 if (filter_op == RTE_ETH_FILTER_NOP)
3061 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3066 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3067 vnic = &bp->vnic_info[efilter->queue];
3069 switch (filter_op) {
3070 case RTE_ETH_FILTER_ADD:
3071 bnxt_match_and_validate_ether_filter(bp, efilter,
3076 bfilter = bnxt_get_unused_filter(bp);
3077 if (bfilter == NULL) {
3079 "Not enough resources for a new filter.\n");
3082 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3083 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3084 RTE_ETHER_ADDR_LEN);
3085 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3086 RTE_ETHER_ADDR_LEN);
3087 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3088 bfilter->ethertype = efilter->ether_type;
3089 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3091 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3092 if (filter1 == NULL) {
3097 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3098 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3100 bfilter->dst_id = vnic->fw_vnic_id;
3102 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3104 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3107 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3110 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3112 case RTE_ETH_FILTER_DELETE:
3113 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3115 if (ret == -EEXIST) {
3116 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3118 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3120 bnxt_free_filter(bp, filter1);
3121 } else if (ret == 0) {
3122 PMD_DRV_LOG(ERR, "No matching filter found\n");
3126 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3132 bnxt_free_filter(bp, bfilter);
3138 parse_ntuple_filter(struct bnxt *bp,
3139 struct rte_eth_ntuple_filter *nfilter,
3140 struct bnxt_filter_info *bfilter)
3144 if (nfilter->queue >= bp->rx_nr_rings) {
3145 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3149 switch (nfilter->dst_port_mask) {
3151 bfilter->dst_port_mask = -1;
3152 bfilter->dst_port = nfilter->dst_port;
3153 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3154 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3157 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3161 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3162 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3164 switch (nfilter->proto_mask) {
3166 if (nfilter->proto == 17) /* IPPROTO_UDP */
3167 bfilter->ip_protocol = 17;
3168 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3169 bfilter->ip_protocol = 6;
3172 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3175 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3179 switch (nfilter->dst_ip_mask) {
3181 bfilter->dst_ipaddr_mask[0] = -1;
3182 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3183 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3184 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3187 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3191 switch (nfilter->src_ip_mask) {
3193 bfilter->src_ipaddr_mask[0] = -1;
3194 bfilter->src_ipaddr[0] = nfilter->src_ip;
3195 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3196 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3199 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3203 switch (nfilter->src_port_mask) {
3205 bfilter->src_port_mask = -1;
3206 bfilter->src_port = nfilter->src_port;
3207 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3208 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3211 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3215 bfilter->enables = en;
3219 static struct bnxt_filter_info*
3220 bnxt_match_ntuple_filter(struct bnxt *bp,
3221 struct bnxt_filter_info *bfilter,
3222 struct bnxt_vnic_info **mvnic)
3224 struct bnxt_filter_info *mfilter = NULL;
3227 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3228 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3229 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3230 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3231 bfilter->src_ipaddr_mask[0] ==
3232 mfilter->src_ipaddr_mask[0] &&
3233 bfilter->src_port == mfilter->src_port &&
3234 bfilter->src_port_mask == mfilter->src_port_mask &&
3235 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3236 bfilter->dst_ipaddr_mask[0] ==
3237 mfilter->dst_ipaddr_mask[0] &&
3238 bfilter->dst_port == mfilter->dst_port &&
3239 bfilter->dst_port_mask == mfilter->dst_port_mask &&
3240 bfilter->flags == mfilter->flags &&
3241 bfilter->enables == mfilter->enables) {
3252 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3253 struct rte_eth_ntuple_filter *nfilter,
3254 enum rte_filter_op filter_op)
3256 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3257 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3260 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3261 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3265 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3266 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3270 bfilter = bnxt_get_unused_filter(bp);
3271 if (bfilter == NULL) {
3273 "Not enough resources for a new filter.\n");
3276 ret = parse_ntuple_filter(bp, nfilter, bfilter);
3280 vnic = &bp->vnic_info[nfilter->queue];
3281 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3282 filter1 = STAILQ_FIRST(&vnic0->filter);
3283 if (filter1 == NULL) {
3288 bfilter->dst_id = vnic->fw_vnic_id;
3289 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3291 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3292 bfilter->ethertype = 0x800;
3293 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3295 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3297 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3298 bfilter->dst_id == mfilter->dst_id) {
3299 PMD_DRV_LOG(ERR, "filter exists.\n");
3302 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3303 bfilter->dst_id != mfilter->dst_id) {
3304 mfilter->dst_id = vnic->fw_vnic_id;
3305 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3306 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3307 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3308 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3309 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3312 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3313 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3318 if (filter_op == RTE_ETH_FILTER_ADD) {
3319 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3320 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3323 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3325 if (mfilter == NULL) {
3326 /* This should not happen. But for Coverity! */
3330 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3332 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3333 bnxt_free_filter(bp, mfilter);
3334 bnxt_free_filter(bp, bfilter);
3339 bnxt_free_filter(bp, bfilter);
3344 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3345 enum rte_filter_op filter_op,
3348 struct bnxt *bp = dev->data->dev_private;
3351 if (filter_op == RTE_ETH_FILTER_NOP)
3355 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3360 switch (filter_op) {
3361 case RTE_ETH_FILTER_ADD:
3362 ret = bnxt_cfg_ntuple_filter(bp,
3363 (struct rte_eth_ntuple_filter *)arg,
3366 case RTE_ETH_FILTER_DELETE:
3367 ret = bnxt_cfg_ntuple_filter(bp,
3368 (struct rte_eth_ntuple_filter *)arg,
3372 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3380 bnxt_parse_fdir_filter(struct bnxt *bp,
3381 struct rte_eth_fdir_filter *fdir,
3382 struct bnxt_filter_info *filter)
3384 enum rte_fdir_mode fdir_mode =
3385 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3386 struct bnxt_vnic_info *vnic0, *vnic;
3387 struct bnxt_filter_info *filter1;
3391 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3394 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3395 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3397 switch (fdir->input.flow_type) {
3398 case RTE_ETH_FLOW_IPV4:
3399 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3401 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3402 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3403 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3404 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3405 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3406 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3407 filter->ip_addr_type =
3408 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3409 filter->src_ipaddr_mask[0] = 0xffffffff;
3410 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3411 filter->dst_ipaddr_mask[0] = 0xffffffff;
3412 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3413 filter->ethertype = 0x800;
3414 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3416 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3417 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3418 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3419 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3420 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3421 filter->dst_port_mask = 0xffff;
3422 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3423 filter->src_port_mask = 0xffff;
3424 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3425 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3426 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3427 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3428 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3429 filter->ip_protocol = 6;
3430 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3431 filter->ip_addr_type =
3432 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3433 filter->src_ipaddr_mask[0] = 0xffffffff;
3434 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3435 filter->dst_ipaddr_mask[0] = 0xffffffff;
3436 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3437 filter->ethertype = 0x800;
3438 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3440 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3441 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3442 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3443 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3444 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3445 filter->dst_port_mask = 0xffff;
3446 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3447 filter->src_port_mask = 0xffff;
3448 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3449 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3450 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3451 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3452 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3453 filter->ip_protocol = 17;
3454 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3455 filter->ip_addr_type =
3456 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3457 filter->src_ipaddr_mask[0] = 0xffffffff;
3458 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3459 filter->dst_ipaddr_mask[0] = 0xffffffff;
3460 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3461 filter->ethertype = 0x800;
3462 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3464 case RTE_ETH_FLOW_IPV6:
3465 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3467 filter->ip_addr_type =
3468 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3469 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3470 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3471 rte_memcpy(filter->src_ipaddr,
3472 fdir->input.flow.ipv6_flow.src_ip, 16);
3473 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3474 rte_memcpy(filter->dst_ipaddr,
3475 fdir->input.flow.ipv6_flow.dst_ip, 16);
3476 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3477 memset(filter->dst_ipaddr_mask, 0xff, 16);
3478 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3479 memset(filter->src_ipaddr_mask, 0xff, 16);
3480 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3481 filter->ethertype = 0x86dd;
3482 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3484 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3485 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3486 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3487 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3488 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3489 filter->dst_port_mask = 0xffff;
3490 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3491 filter->src_port_mask = 0xffff;
3492 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3493 filter->ip_addr_type =
3494 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3495 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3496 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3497 rte_memcpy(filter->src_ipaddr,
3498 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3499 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3500 rte_memcpy(filter->dst_ipaddr,
3501 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3502 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3503 memset(filter->dst_ipaddr_mask, 0xff, 16);
3504 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3505 memset(filter->src_ipaddr_mask, 0xff, 16);
3506 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3507 filter->ethertype = 0x86dd;
3508 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3510 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3511 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3512 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3513 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3514 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3515 filter->dst_port_mask = 0xffff;
3516 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3517 filter->src_port_mask = 0xffff;
3518 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3519 filter->ip_addr_type =
3520 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3521 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3522 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3523 rte_memcpy(filter->src_ipaddr,
3524 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3525 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3526 rte_memcpy(filter->dst_ipaddr,
3527 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3528 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3529 memset(filter->dst_ipaddr_mask, 0xff, 16);
3530 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3531 memset(filter->src_ipaddr_mask, 0xff, 16);
3532 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3533 filter->ethertype = 0x86dd;
3534 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3536 case RTE_ETH_FLOW_L2_PAYLOAD:
3537 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3538 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3540 case RTE_ETH_FLOW_VXLAN:
3541 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3543 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3544 filter->tunnel_type =
3545 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3546 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3548 case RTE_ETH_FLOW_NVGRE:
3549 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3551 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3552 filter->tunnel_type =
3553 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3554 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3556 case RTE_ETH_FLOW_UNKNOWN:
3557 case RTE_ETH_FLOW_RAW:
3558 case RTE_ETH_FLOW_FRAG_IPV4:
3559 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3560 case RTE_ETH_FLOW_FRAG_IPV6:
3561 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3562 case RTE_ETH_FLOW_IPV6_EX:
3563 case RTE_ETH_FLOW_IPV6_TCP_EX:
3564 case RTE_ETH_FLOW_IPV6_UDP_EX:
3565 case RTE_ETH_FLOW_GENEVE:
3571 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3572 vnic = &bp->vnic_info[fdir->action.rx_queue];
3574 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3578 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3579 rte_memcpy(filter->dst_macaddr,
3580 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3581 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3584 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3585 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3586 filter1 = STAILQ_FIRST(&vnic0->filter);
3587 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3589 filter->dst_id = vnic->fw_vnic_id;
3590 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3591 if (filter->dst_macaddr[i] == 0x00)
3592 filter1 = STAILQ_FIRST(&vnic0->filter);
3594 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3597 if (filter1 == NULL)
3600 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3601 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3603 filter->enables = en;
3608 static struct bnxt_filter_info *
3609 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3610 struct bnxt_vnic_info **mvnic)
3612 struct bnxt_filter_info *mf = NULL;
3615 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3616 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3618 STAILQ_FOREACH(mf, &vnic->filter, next) {
3619 if (mf->filter_type == nf->filter_type &&
3620 mf->flags == nf->flags &&
3621 mf->src_port == nf->src_port &&
3622 mf->src_port_mask == nf->src_port_mask &&
3623 mf->dst_port == nf->dst_port &&
3624 mf->dst_port_mask == nf->dst_port_mask &&
3625 mf->ip_protocol == nf->ip_protocol &&
3626 mf->ip_addr_type == nf->ip_addr_type &&
3627 mf->ethertype == nf->ethertype &&
3628 mf->vni == nf->vni &&
3629 mf->tunnel_type == nf->tunnel_type &&
3630 mf->l2_ovlan == nf->l2_ovlan &&
3631 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3632 mf->l2_ivlan == nf->l2_ivlan &&
3633 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3634 !memcmp(mf->l2_addr, nf->l2_addr,
3635 RTE_ETHER_ADDR_LEN) &&
3636 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3637 RTE_ETHER_ADDR_LEN) &&
3638 !memcmp(mf->src_macaddr, nf->src_macaddr,
3639 RTE_ETHER_ADDR_LEN) &&
3640 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3641 RTE_ETHER_ADDR_LEN) &&
3642 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3643 sizeof(nf->src_ipaddr)) &&
3644 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3645 sizeof(nf->src_ipaddr_mask)) &&
3646 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3647 sizeof(nf->dst_ipaddr)) &&
3648 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3649 sizeof(nf->dst_ipaddr_mask))) {
3660 bnxt_fdir_filter(struct rte_eth_dev *dev,
3661 enum rte_filter_op filter_op,
3664 struct bnxt *bp = dev->data->dev_private;
3665 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3666 struct bnxt_filter_info *filter, *match;
3667 struct bnxt_vnic_info *vnic, *mvnic;
3670 if (filter_op == RTE_ETH_FILTER_NOP)
3673 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3676 switch (filter_op) {
3677 case RTE_ETH_FILTER_ADD:
3678 case RTE_ETH_FILTER_DELETE:
3680 filter = bnxt_get_unused_filter(bp);
3681 if (filter == NULL) {
3683 "Not enough resources for a new flow.\n");
3687 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3690 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3692 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3693 vnic = &bp->vnic_info[0];
3695 vnic = &bp->vnic_info[fdir->action.rx_queue];
3697 match = bnxt_match_fdir(bp, filter, &mvnic);
3698 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3699 if (match->dst_id == vnic->fw_vnic_id) {
3700 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3704 match->dst_id = vnic->fw_vnic_id;
3705 ret = bnxt_hwrm_set_ntuple_filter(bp,
3708 STAILQ_REMOVE(&mvnic->filter, match,
3709 bnxt_filter_info, next);
3710 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3712 "Filter with matching pattern exist\n");
3714 "Updated it to new destination q\n");
3718 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3719 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3724 if (filter_op == RTE_ETH_FILTER_ADD) {
3725 ret = bnxt_hwrm_set_ntuple_filter(bp,
3730 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3732 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3733 STAILQ_REMOVE(&vnic->filter, match,
3734 bnxt_filter_info, next);
3735 bnxt_free_filter(bp, match);
3736 bnxt_free_filter(bp, filter);
3739 case RTE_ETH_FILTER_FLUSH:
3740 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3741 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3743 STAILQ_FOREACH(filter, &vnic->filter, next) {
3744 if (filter->filter_type ==
3745 HWRM_CFA_NTUPLE_FILTER) {
3747 bnxt_hwrm_clear_ntuple_filter(bp,
3749 STAILQ_REMOVE(&vnic->filter, filter,
3750 bnxt_filter_info, next);
3755 case RTE_ETH_FILTER_UPDATE:
3756 case RTE_ETH_FILTER_STATS:
3757 case RTE_ETH_FILTER_INFO:
3758 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3761 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3768 bnxt_free_filter(bp, filter);
3773 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3774 enum rte_filter_type filter_type,
3775 enum rte_filter_op filter_op, void *arg)
3777 struct bnxt *bp = dev->data->dev_private;
3783 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3784 struct bnxt_representor *vfr = dev->data->dev_private;
3785 bp = vfr->parent_dev->data->dev_private;
3786 /* parent is deleted while children are still valid */
3788 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3796 ret = is_bnxt_in_error(bp);
3800 switch (filter_type) {
3801 case RTE_ETH_FILTER_TUNNEL:
3803 "filter type: %d: To be implemented\n", filter_type);
3805 case RTE_ETH_FILTER_FDIR:
3806 ret = bnxt_fdir_filter(dev, filter_op, arg);
3808 case RTE_ETH_FILTER_NTUPLE:
3809 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3811 case RTE_ETH_FILTER_ETHERTYPE:
3812 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3814 case RTE_ETH_FILTER_GENERIC:
3815 if (filter_op != RTE_ETH_FILTER_GET)
3817 if (BNXT_TRUFLOW_EN(bp))
3818 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3820 *(const void **)arg = &bnxt_flow_ops;
3824 "Filter type (%d) not supported", filter_type);
3831 static const uint32_t *
3832 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3834 static const uint32_t ptypes[] = {
3835 RTE_PTYPE_L2_ETHER_VLAN,
3836 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3837 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3841 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3842 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3843 RTE_PTYPE_INNER_L4_ICMP,
3844 RTE_PTYPE_INNER_L4_TCP,
3845 RTE_PTYPE_INNER_L4_UDP,
3849 if (!dev->rx_pkt_burst)
3855 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3858 uint32_t reg_base = *reg_arr & 0xfffff000;
3862 for (i = 0; i < count; i++) {
3863 if ((reg_arr[i] & 0xfffff000) != reg_base)
3866 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3867 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3871 static int bnxt_map_ptp_regs(struct bnxt *bp)
3873 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3877 reg_arr = ptp->rx_regs;
3878 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3882 reg_arr = ptp->tx_regs;
3883 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3887 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3888 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3890 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3891 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3896 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3898 rte_write32(0, (uint8_t *)bp->bar0 +
3899 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3900 rte_write32(0, (uint8_t *)bp->bar0 +
3901 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3904 static uint64_t bnxt_cc_read(struct bnxt *bp)
3908 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3909 BNXT_GRCPF_REG_SYNC_TIME));
3910 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3911 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3915 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3917 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3920 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3921 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3922 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3925 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3926 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3927 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3928 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3929 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3930 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3935 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3937 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3938 struct bnxt_pf_info *pf = bp->pf;
3945 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3946 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3947 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3950 port_id = pf->port_id;
3951 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3952 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3954 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3955 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3956 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3957 /* bnxt_clr_rx_ts(bp); TBD */
3961 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3962 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3963 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3964 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3970 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3973 struct bnxt *bp = dev->data->dev_private;
3974 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3979 ns = rte_timespec_to_ns(ts);
3980 /* Set the timecounters to a new value. */
3987 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3989 struct bnxt *bp = dev->data->dev_private;
3990 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3991 uint64_t ns, systime_cycles = 0;
3997 if (BNXT_CHIP_THOR(bp))
3998 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
4001 systime_cycles = bnxt_cc_read(bp);
4003 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
4004 *ts = rte_ns_to_timespec(ns);
4009 bnxt_timesync_enable(struct rte_eth_dev *dev)
4011 struct bnxt *bp = dev->data->dev_private;
4012 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4020 ptp->tx_tstamp_en = 1;
4021 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
4023 rc = bnxt_hwrm_ptp_cfg(bp);
4027 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
4028 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4029 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4031 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4032 ptp->tc.cc_shift = shift;
4033 ptp->tc.nsec_mask = (1ULL << shift) - 1;
4035 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4036 ptp->rx_tstamp_tc.cc_shift = shift;
4037 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4039 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4040 ptp->tx_tstamp_tc.cc_shift = shift;
4041 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4043 if (!BNXT_CHIP_THOR(bp))
4044 bnxt_map_ptp_regs(bp);
4050 bnxt_timesync_disable(struct rte_eth_dev *dev)
4052 struct bnxt *bp = dev->data->dev_private;
4053 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4059 ptp->tx_tstamp_en = 0;
4062 bnxt_hwrm_ptp_cfg(bp);
4064 if (!BNXT_CHIP_THOR(bp))
4065 bnxt_unmap_ptp_regs(bp);
4071 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4072 struct timespec *timestamp,
4073 uint32_t flags __rte_unused)
4075 struct bnxt *bp = dev->data->dev_private;
4076 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4077 uint64_t rx_tstamp_cycles = 0;
4083 if (BNXT_CHIP_THOR(bp))
4084 rx_tstamp_cycles = ptp->rx_timestamp;
4086 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4088 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4089 *timestamp = rte_ns_to_timespec(ns);
4094 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4095 struct timespec *timestamp)
4097 struct bnxt *bp = dev->data->dev_private;
4098 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4099 uint64_t tx_tstamp_cycles = 0;
4106 if (BNXT_CHIP_THOR(bp))
4107 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4110 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4112 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4113 *timestamp = rte_ns_to_timespec(ns);
4119 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4121 struct bnxt *bp = dev->data->dev_private;
4122 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4127 ptp->tc.nsec += delta;
4133 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4135 struct bnxt *bp = dev->data->dev_private;
4137 uint32_t dir_entries;
4138 uint32_t entry_length;
4140 rc = is_bnxt_in_error(bp);
4144 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4145 bp->pdev->addr.domain, bp->pdev->addr.bus,
4146 bp->pdev->addr.devid, bp->pdev->addr.function);
4148 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4152 return dir_entries * entry_length;
4156 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4157 struct rte_dev_eeprom_info *in_eeprom)
4159 struct bnxt *bp = dev->data->dev_private;
4164 rc = is_bnxt_in_error(bp);
4168 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4169 bp->pdev->addr.domain, bp->pdev->addr.bus,
4170 bp->pdev->addr.devid, bp->pdev->addr.function,
4171 in_eeprom->offset, in_eeprom->length);
4173 if (in_eeprom->offset == 0) /* special offset value to get directory */
4174 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4177 index = in_eeprom->offset >> 24;
4178 offset = in_eeprom->offset & 0xffffff;
4181 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4182 in_eeprom->length, in_eeprom->data);
4187 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4190 case BNX_DIR_TYPE_CHIMP_PATCH:
4191 case BNX_DIR_TYPE_BOOTCODE:
4192 case BNX_DIR_TYPE_BOOTCODE_2:
4193 case BNX_DIR_TYPE_APE_FW:
4194 case BNX_DIR_TYPE_APE_PATCH:
4195 case BNX_DIR_TYPE_KONG_FW:
4196 case BNX_DIR_TYPE_KONG_PATCH:
4197 case BNX_DIR_TYPE_BONO_FW:
4198 case BNX_DIR_TYPE_BONO_PATCH:
4206 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4209 case BNX_DIR_TYPE_AVS:
4210 case BNX_DIR_TYPE_EXP_ROM_MBA:
4211 case BNX_DIR_TYPE_PCIE:
4212 case BNX_DIR_TYPE_TSCF_UCODE:
4213 case BNX_DIR_TYPE_EXT_PHY:
4214 case BNX_DIR_TYPE_CCM:
4215 case BNX_DIR_TYPE_ISCSI_BOOT:
4216 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4217 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4225 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4227 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4228 bnxt_dir_type_is_other_exec_format(dir_type);
4232 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4233 struct rte_dev_eeprom_info *in_eeprom)
4235 struct bnxt *bp = dev->data->dev_private;
4236 uint8_t index, dir_op;
4237 uint16_t type, ext, ordinal, attr;
4240 rc = is_bnxt_in_error(bp);
4244 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4245 bp->pdev->addr.domain, bp->pdev->addr.bus,
4246 bp->pdev->addr.devid, bp->pdev->addr.function,
4247 in_eeprom->offset, in_eeprom->length);
4250 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4254 type = in_eeprom->magic >> 16;
4256 if (type == 0xffff) { /* special value for directory operations */
4257 index = in_eeprom->magic & 0xff;
4258 dir_op = in_eeprom->magic >> 8;
4262 case 0x0e: /* erase */
4263 if (in_eeprom->offset != ~in_eeprom->magic)
4265 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4271 /* Create or re-write an NVM item: */
4272 if (bnxt_dir_type_is_executable(type) == true)
4274 ext = in_eeprom->magic & 0xffff;
4275 ordinal = in_eeprom->offset >> 16;
4276 attr = in_eeprom->offset & 0xffff;
4278 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4279 in_eeprom->data, in_eeprom->length);
4286 static const struct eth_dev_ops bnxt_dev_ops = {
4287 .dev_infos_get = bnxt_dev_info_get_op,
4288 .dev_close = bnxt_dev_close_op,
4289 .dev_configure = bnxt_dev_configure_op,
4290 .dev_start = bnxt_dev_start_op,
4291 .dev_stop = bnxt_dev_stop_op,
4292 .dev_set_link_up = bnxt_dev_set_link_up_op,
4293 .dev_set_link_down = bnxt_dev_set_link_down_op,
4294 .stats_get = bnxt_stats_get_op,
4295 .stats_reset = bnxt_stats_reset_op,
4296 .rx_queue_setup = bnxt_rx_queue_setup_op,
4297 .rx_queue_release = bnxt_rx_queue_release_op,
4298 .tx_queue_setup = bnxt_tx_queue_setup_op,
4299 .tx_queue_release = bnxt_tx_queue_release_op,
4300 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4301 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4302 .reta_update = bnxt_reta_update_op,
4303 .reta_query = bnxt_reta_query_op,
4304 .rss_hash_update = bnxt_rss_hash_update_op,
4305 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4306 .link_update = bnxt_link_update_op,
4307 .promiscuous_enable = bnxt_promiscuous_enable_op,
4308 .promiscuous_disable = bnxt_promiscuous_disable_op,
4309 .allmulticast_enable = bnxt_allmulticast_enable_op,
4310 .allmulticast_disable = bnxt_allmulticast_disable_op,
4311 .mac_addr_add = bnxt_mac_addr_add_op,
4312 .mac_addr_remove = bnxt_mac_addr_remove_op,
4313 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4314 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4315 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4316 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4317 .vlan_filter_set = bnxt_vlan_filter_set_op,
4318 .vlan_offload_set = bnxt_vlan_offload_set_op,
4319 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4320 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4321 .mtu_set = bnxt_mtu_set_op,
4322 .mac_addr_set = bnxt_set_default_mac_addr_op,
4323 .xstats_get = bnxt_dev_xstats_get_op,
4324 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4325 .xstats_reset = bnxt_dev_xstats_reset_op,
4326 .fw_version_get = bnxt_fw_version_get,
4327 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4328 .rxq_info_get = bnxt_rxq_info_get_op,
4329 .txq_info_get = bnxt_txq_info_get_op,
4330 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4331 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4332 .dev_led_on = bnxt_dev_led_on_op,
4333 .dev_led_off = bnxt_dev_led_off_op,
4334 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4335 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4336 .rx_queue_start = bnxt_rx_queue_start,
4337 .rx_queue_stop = bnxt_rx_queue_stop,
4338 .tx_queue_start = bnxt_tx_queue_start,
4339 .tx_queue_stop = bnxt_tx_queue_stop,
4340 .filter_ctrl = bnxt_filter_ctrl_op,
4341 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4342 .get_eeprom_length = bnxt_get_eeprom_length_op,
4343 .get_eeprom = bnxt_get_eeprom_op,
4344 .set_eeprom = bnxt_set_eeprom_op,
4345 .timesync_enable = bnxt_timesync_enable,
4346 .timesync_disable = bnxt_timesync_disable,
4347 .timesync_read_time = bnxt_timesync_read_time,
4348 .timesync_write_time = bnxt_timesync_write_time,
4349 .timesync_adjust_time = bnxt_timesync_adjust_time,
4350 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4351 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4354 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4358 /* Only pre-map the reset GRC registers using window 3 */
4359 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4360 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4362 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4367 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4369 struct bnxt_error_recovery_info *info = bp->recovery_info;
4370 uint32_t reg_base = 0xffffffff;
4373 /* Only pre-map the monitoring GRC registers using window 2 */
4374 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4375 uint32_t reg = info->status_regs[i];
4377 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4380 if (reg_base == 0xffffffff)
4381 reg_base = reg & 0xfffff000;
4382 if ((reg & 0xfffff000) != reg_base)
4385 /* Use mask 0xffc as the Lower 2 bits indicates
4386 * address space location
4388 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4392 if (reg_base == 0xffffffff)
4395 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4396 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4401 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4403 struct bnxt_error_recovery_info *info = bp->recovery_info;
4404 uint32_t delay = info->delay_after_reset[index];
4405 uint32_t val = info->reset_reg_val[index];
4406 uint32_t reg = info->reset_reg[index];
4407 uint32_t type, offset;
4409 type = BNXT_FW_STATUS_REG_TYPE(reg);
4410 offset = BNXT_FW_STATUS_REG_OFF(reg);
4413 case BNXT_FW_STATUS_REG_TYPE_CFG:
4414 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4416 case BNXT_FW_STATUS_REG_TYPE_GRC:
4417 offset = bnxt_map_reset_regs(bp, offset);
4418 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4420 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4421 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4424 /* wait on a specific interval of time until core reset is complete */
4426 rte_delay_ms(delay);
4429 static void bnxt_dev_cleanup(struct bnxt *bp)
4431 bp->eth_dev->data->dev_link.link_status = 0;
4432 bp->link_info->link_up = 0;
4433 if (bp->eth_dev->data->dev_started)
4434 bnxt_dev_stop_op(bp->eth_dev);
4436 bnxt_uninit_resources(bp, true);
4439 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4441 struct rte_eth_dev *dev = bp->eth_dev;
4442 struct rte_vlan_filter_conf *vfc;
4446 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4447 vfc = &dev->data->vlan_filter_conf;
4448 vidx = vlan_id / 64;
4449 vbit = vlan_id % 64;
4451 /* Each bit corresponds to a VLAN id */
4452 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4453 rc = bnxt_add_vlan_filter(bp, vlan_id);
4462 static int bnxt_restore_mac_filters(struct bnxt *bp)
4464 struct rte_eth_dev *dev = bp->eth_dev;
4465 struct rte_eth_dev_info dev_info;
4466 struct rte_ether_addr *addr;
4472 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4475 rc = bnxt_dev_info_get_op(dev, &dev_info);
4479 /* replay MAC address configuration */
4480 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4481 addr = &dev->data->mac_addrs[i];
4483 /* skip zero address */
4484 if (rte_is_zero_ether_addr(addr))
4488 pool_mask = dev->data->mac_pool_sel[i];
4491 if (pool_mask & 1ULL) {
4492 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4498 } while (pool_mask);
4504 static int bnxt_restore_filters(struct bnxt *bp)
4506 struct rte_eth_dev *dev = bp->eth_dev;
4509 if (dev->data->all_multicast) {
4510 ret = bnxt_allmulticast_enable_op(dev);
4514 if (dev->data->promiscuous) {
4515 ret = bnxt_promiscuous_enable_op(dev);
4520 ret = bnxt_restore_mac_filters(bp);
4524 ret = bnxt_restore_vlan_filters(bp);
4525 /* TODO restore other filters as well */
4529 static void bnxt_dev_recover(void *arg)
4531 struct bnxt *bp = arg;
4532 int timeout = bp->fw_reset_max_msecs;
4535 /* Clear Error flag so that device re-init should happen */
4536 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4539 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4542 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4543 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4544 } while (rc && timeout);
4547 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4551 rc = bnxt_init_resources(bp, true);
4554 "Failed to initialize resources after reset\n");
4557 /* clear reset flag as the device is initialized now */
4558 bp->flags &= ~BNXT_FLAG_FW_RESET;
4560 rc = bnxt_dev_start_op(bp->eth_dev);
4562 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4566 rc = bnxt_restore_filters(bp);
4570 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4573 bnxt_dev_stop_op(bp->eth_dev);
4575 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4576 bnxt_uninit_resources(bp, false);
4577 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4580 void bnxt_dev_reset_and_resume(void *arg)
4582 struct bnxt *bp = arg;
4585 bnxt_dev_cleanup(bp);
4587 bnxt_wait_for_device_shutdown(bp);
4589 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4590 bnxt_dev_recover, (void *)bp);
4592 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4595 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4597 struct bnxt_error_recovery_info *info = bp->recovery_info;
4598 uint32_t reg = info->status_regs[index];
4599 uint32_t type, offset, val = 0;
4601 type = BNXT_FW_STATUS_REG_TYPE(reg);
4602 offset = BNXT_FW_STATUS_REG_OFF(reg);
4605 case BNXT_FW_STATUS_REG_TYPE_CFG:
4606 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4608 case BNXT_FW_STATUS_REG_TYPE_GRC:
4609 offset = info->mapped_status_regs[index];
4611 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4612 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4620 static int bnxt_fw_reset_all(struct bnxt *bp)
4622 struct bnxt_error_recovery_info *info = bp->recovery_info;
4626 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4627 /* Reset through master function driver */
4628 for (i = 0; i < info->reg_array_cnt; i++)
4629 bnxt_write_fw_reset_reg(bp, i);
4630 /* Wait for time specified by FW after triggering reset */
4631 rte_delay_ms(info->master_func_wait_period_after_reset);
4632 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4633 /* Reset with the help of Kong processor */
4634 rc = bnxt_hwrm_fw_reset(bp);
4636 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4642 static void bnxt_fw_reset_cb(void *arg)
4644 struct bnxt *bp = arg;
4645 struct bnxt_error_recovery_info *info = bp->recovery_info;
4648 /* Only Master function can do FW reset */
4649 if (bnxt_is_master_func(bp) &&
4650 bnxt_is_recovery_enabled(bp)) {
4651 rc = bnxt_fw_reset_all(bp);
4653 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4658 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4659 * EXCEPTION_FATAL_ASYNC event to all the functions
4660 * (including MASTER FUNC). After receiving this Async, all the active
4661 * drivers should treat this case as FW initiated recovery
4663 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4664 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4665 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4667 /* To recover from error */
4668 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4673 /* Driver should poll FW heartbeat, reset_counter with the frequency
4674 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4675 * When the driver detects heartbeat stop or change in reset_counter,
4676 * it has to trigger a reset to recover from the error condition.
4677 * A “master PF” is the function who will have the privilege to
4678 * initiate the chimp reset. The master PF will be elected by the
4679 * firmware and will be notified through async message.
4681 static void bnxt_check_fw_health(void *arg)
4683 struct bnxt *bp = arg;
4684 struct bnxt_error_recovery_info *info = bp->recovery_info;
4685 uint32_t val = 0, wait_msec;
4687 if (!info || !bnxt_is_recovery_enabled(bp) ||
4688 is_bnxt_in_error(bp))
4691 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4692 if (val == info->last_heart_beat)
4695 info->last_heart_beat = val;
4697 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4698 if (val != info->last_reset_counter)
4701 info->last_reset_counter = val;
4703 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4704 bnxt_check_fw_health, (void *)bp);
4708 /* Stop DMA to/from device */
4709 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4710 bp->flags |= BNXT_FLAG_FW_RESET;
4712 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4714 if (bnxt_is_master_func(bp))
4715 wait_msec = info->master_func_wait_period;
4717 wait_msec = info->normal_func_wait_period;
4719 rte_eal_alarm_set(US_PER_MS * wait_msec,
4720 bnxt_fw_reset_cb, (void *)bp);
4723 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4725 uint32_t polling_freq;
4727 pthread_mutex_lock(&bp->health_check_lock);
4729 if (!bnxt_is_recovery_enabled(bp))
4732 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4735 polling_freq = bp->recovery_info->driver_polling_freq;
4737 rte_eal_alarm_set(US_PER_MS * polling_freq,
4738 bnxt_check_fw_health, (void *)bp);
4739 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4742 pthread_mutex_unlock(&bp->health_check_lock);
4745 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4747 if (!bnxt_is_recovery_enabled(bp))
4750 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4751 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4754 static bool bnxt_vf_pciid(uint16_t device_id)
4756 switch (device_id) {
4757 case BROADCOM_DEV_ID_57304_VF:
4758 case BROADCOM_DEV_ID_57406_VF:
4759 case BROADCOM_DEV_ID_5731X_VF:
4760 case BROADCOM_DEV_ID_5741X_VF:
4761 case BROADCOM_DEV_ID_57414_VF:
4762 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4763 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4764 case BROADCOM_DEV_ID_58802_VF:
4765 case BROADCOM_DEV_ID_57500_VF1:
4766 case BROADCOM_DEV_ID_57500_VF2:
4774 static bool bnxt_thor_device(uint16_t device_id)
4776 switch (device_id) {
4777 case BROADCOM_DEV_ID_57508:
4778 case BROADCOM_DEV_ID_57504:
4779 case BROADCOM_DEV_ID_57502:
4780 case BROADCOM_DEV_ID_57508_MF1:
4781 case BROADCOM_DEV_ID_57504_MF1:
4782 case BROADCOM_DEV_ID_57502_MF1:
4783 case BROADCOM_DEV_ID_57508_MF2:
4784 case BROADCOM_DEV_ID_57504_MF2:
4785 case BROADCOM_DEV_ID_57502_MF2:
4786 case BROADCOM_DEV_ID_57500_VF1:
4787 case BROADCOM_DEV_ID_57500_VF2:
4795 bool bnxt_stratus_device(struct bnxt *bp)
4797 uint16_t device_id = bp->pdev->id.device_id;
4799 switch (device_id) {
4800 case BROADCOM_DEV_ID_STRATUS_NIC:
4801 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4802 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4810 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4812 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4813 struct bnxt *bp = eth_dev->data->dev_private;
4815 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4816 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4817 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4818 if (!bp->bar0 || !bp->doorbell_base) {
4819 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4823 bp->eth_dev = eth_dev;
4829 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4830 struct bnxt_ctx_pg_info *ctx_pg,
4835 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4836 const struct rte_memzone *mz = NULL;
4837 char mz_name[RTE_MEMZONE_NAMESIZE];
4838 rte_iova_t mz_phys_addr;
4839 uint64_t valid_bits = 0;
4846 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4848 rmem->page_size = BNXT_PAGE_SIZE;
4849 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4850 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4851 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4853 valid_bits = PTU_PTE_VALID;
4855 if (rmem->nr_pages > 1) {
4856 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4857 "bnxt_ctx_pg_tbl%s_%x_%d",
4858 suffix, idx, bp->eth_dev->data->port_id);
4859 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4860 mz = rte_memzone_lookup(mz_name);
4862 mz = rte_memzone_reserve_aligned(mz_name,
4866 RTE_MEMZONE_SIZE_HINT_ONLY |
4867 RTE_MEMZONE_IOVA_CONTIG,
4873 memset(mz->addr, 0, mz->len);
4874 mz_phys_addr = mz->iova;
4876 rmem->pg_tbl = mz->addr;
4877 rmem->pg_tbl_map = mz_phys_addr;
4878 rmem->pg_tbl_mz = mz;
4881 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4882 suffix, idx, bp->eth_dev->data->port_id);
4883 mz = rte_memzone_lookup(mz_name);
4885 mz = rte_memzone_reserve_aligned(mz_name,
4889 RTE_MEMZONE_SIZE_HINT_ONLY |
4890 RTE_MEMZONE_IOVA_CONTIG,
4896 memset(mz->addr, 0, mz->len);
4897 mz_phys_addr = mz->iova;
4899 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4900 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4901 rmem->dma_arr[i] = mz_phys_addr + sz;
4903 if (rmem->nr_pages > 1) {
4904 if (i == rmem->nr_pages - 2 &&
4905 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4906 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4907 else if (i == rmem->nr_pages - 1 &&
4908 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4909 valid_bits |= PTU_PTE_LAST;
4911 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4917 if (rmem->vmem_size)
4918 rmem->vmem = (void **)mz->addr;
4919 rmem->dma_arr[0] = mz_phys_addr;
4923 static void bnxt_free_ctx_mem(struct bnxt *bp)
4927 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4930 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4931 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4932 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4933 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4934 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4935 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4936 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4937 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4938 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4939 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4940 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4942 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4943 if (bp->ctx->tqm_mem[i])
4944 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4951 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4953 #define min_t(type, x, y) ({ \
4954 type __min1 = (x); \
4955 type __min2 = (y); \
4956 __min1 < __min2 ? __min1 : __min2; })
4958 #define max_t(type, x, y) ({ \
4959 type __max1 = (x); \
4960 type __max2 = (y); \
4961 __max1 > __max2 ? __max1 : __max2; })
4963 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4965 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4967 struct bnxt_ctx_pg_info *ctx_pg;
4968 struct bnxt_ctx_mem_info *ctx;
4969 uint32_t mem_size, ena, entries;
4970 uint32_t entries_sp, min;
4973 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4975 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4979 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4982 ctx_pg = &ctx->qp_mem;
4983 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4984 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4985 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4989 ctx_pg = &ctx->srq_mem;
4990 ctx_pg->entries = ctx->srq_max_l2_entries;
4991 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4992 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4996 ctx_pg = &ctx->cq_mem;
4997 ctx_pg->entries = ctx->cq_max_l2_entries;
4998 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4999 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
5003 ctx_pg = &ctx->vnic_mem;
5004 ctx_pg->entries = ctx->vnic_max_vnic_entries +
5005 ctx->vnic_max_ring_table_entries;
5006 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
5007 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
5011 ctx_pg = &ctx->stat_mem;
5012 ctx_pg->entries = ctx->stat_max_entries;
5013 mem_size = ctx->stat_entry_size * ctx_pg->entries;
5014 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
5018 min = ctx->tqm_min_entries_per_ring;
5020 entries_sp = ctx->qp_max_l2_entries +
5021 ctx->vnic_max_vnic_entries +
5022 2 * ctx->qp_min_qp1_entries + min;
5023 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
5025 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
5026 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
5027 entries = clamp_t(uint32_t, entries, min,
5028 ctx->tqm_max_entries_per_ring);
5029 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
5030 ctx_pg = ctx->tqm_mem[i];
5031 ctx_pg->entries = i ? entries : entries_sp;
5032 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5033 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5036 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5039 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5040 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5043 "Failed to configure context mem: rc = %d\n", rc);
5045 ctx->flags |= BNXT_CTX_FLAG_INITED;
5050 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5052 struct rte_pci_device *pci_dev = bp->pdev;
5053 char mz_name[RTE_MEMZONE_NAMESIZE];
5054 const struct rte_memzone *mz = NULL;
5055 uint32_t total_alloc_len;
5056 rte_iova_t mz_phys_addr;
5058 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5061 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5062 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5063 pci_dev->addr.bus, pci_dev->addr.devid,
5064 pci_dev->addr.function, "rx_port_stats");
5065 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5066 mz = rte_memzone_lookup(mz_name);
5068 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5069 sizeof(struct rx_port_stats_ext) + 512);
5071 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5074 RTE_MEMZONE_SIZE_HINT_ONLY |
5075 RTE_MEMZONE_IOVA_CONTIG);
5079 memset(mz->addr, 0, mz->len);
5080 mz_phys_addr = mz->iova;
5082 bp->rx_mem_zone = (const void *)mz;
5083 bp->hw_rx_port_stats = mz->addr;
5084 bp->hw_rx_port_stats_map = mz_phys_addr;
5086 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5087 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5088 pci_dev->addr.bus, pci_dev->addr.devid,
5089 pci_dev->addr.function, "tx_port_stats");
5090 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5091 mz = rte_memzone_lookup(mz_name);
5093 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5094 sizeof(struct tx_port_stats_ext) + 512);
5096 mz = rte_memzone_reserve(mz_name,
5100 RTE_MEMZONE_SIZE_HINT_ONLY |
5101 RTE_MEMZONE_IOVA_CONTIG);
5105 memset(mz->addr, 0, mz->len);
5106 mz_phys_addr = mz->iova;
5108 bp->tx_mem_zone = (const void *)mz;
5109 bp->hw_tx_port_stats = mz->addr;
5110 bp->hw_tx_port_stats_map = mz_phys_addr;
5111 bp->flags |= BNXT_FLAG_PORT_STATS;
5113 /* Display extended statistics if FW supports it */
5114 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5115 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5116 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5119 bp->hw_rx_port_stats_ext = (void *)
5120 ((uint8_t *)bp->hw_rx_port_stats +
5121 sizeof(struct rx_port_stats));
5122 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5123 sizeof(struct rx_port_stats);
5124 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5126 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5127 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5128 bp->hw_tx_port_stats_ext = (void *)
5129 ((uint8_t *)bp->hw_tx_port_stats +
5130 sizeof(struct tx_port_stats));
5131 bp->hw_tx_port_stats_ext_map =
5132 bp->hw_tx_port_stats_map +
5133 sizeof(struct tx_port_stats);
5134 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5140 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5142 struct bnxt *bp = eth_dev->data->dev_private;
5145 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5146 RTE_ETHER_ADDR_LEN *
5149 if (eth_dev->data->mac_addrs == NULL) {
5150 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5154 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5158 /* Generate a random MAC address, if none was assigned by PF */
5159 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5160 bnxt_eth_hw_addr_random(bp->mac_addr);
5162 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5163 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5164 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5166 rc = bnxt_hwrm_set_mac(bp);
5171 /* Copy the permanent MAC from the FUNC_QCAPS response */
5172 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5177 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5181 /* MAC is already configured in FW */
5182 if (BNXT_HAS_DFLT_MAC_SET(bp))
5185 /* Restore the old MAC configured */
5186 rc = bnxt_hwrm_set_mac(bp);
5188 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5193 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5198 #define ALLOW_FUNC(x) \
5200 uint32_t arg = (x); \
5201 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5202 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5205 /* Forward all requests if firmware is new enough */
5206 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5207 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5208 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5209 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5211 PMD_DRV_LOG(WARNING,
5212 "Firmware too old for VF mailbox functionality\n");
5213 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5217 * The following are used for driver cleanup. If we disallow these,
5218 * VF drivers can't clean up cleanly.
5220 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5221 ALLOW_FUNC(HWRM_VNIC_FREE);
5222 ALLOW_FUNC(HWRM_RING_FREE);
5223 ALLOW_FUNC(HWRM_RING_GRP_FREE);
5224 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5225 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5226 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5227 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5228 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5232 bnxt_get_svif(uint16_t port_id, bool func_svif,
5233 enum bnxt_ulp_intf_type type)
5235 struct rte_eth_dev *eth_dev;
5238 eth_dev = &rte_eth_devices[port_id];
5239 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5240 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5244 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5247 eth_dev = vfr->parent_dev;
5250 bp = eth_dev->data->dev_private;
5252 return func_svif ? bp->func_svif : bp->port_svif;
5256 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5258 struct rte_eth_dev *eth_dev;
5259 struct bnxt_vnic_info *vnic;
5262 eth_dev = &rte_eth_devices[port];
5263 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5264 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5268 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5269 return vfr->dflt_vnic_id;
5271 eth_dev = vfr->parent_dev;
5274 bp = eth_dev->data->dev_private;
5276 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5278 return vnic->fw_vnic_id;
5282 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5284 struct rte_eth_dev *eth_dev;
5287 eth_dev = &rte_eth_devices[port];
5288 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5289 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5293 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5296 eth_dev = vfr->parent_dev;
5299 bp = eth_dev->data->dev_private;
5304 enum bnxt_ulp_intf_type
5305 bnxt_get_interface_type(uint16_t port)
5307 struct rte_eth_dev *eth_dev;
5310 eth_dev = &rte_eth_devices[port];
5311 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5312 return BNXT_ULP_INTF_TYPE_VF_REP;
5314 bp = eth_dev->data->dev_private;
5316 return BNXT_ULP_INTF_TYPE_PF;
5317 else if (BNXT_VF_IS_TRUSTED(bp))
5318 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5319 else if (BNXT_VF(bp))
5320 return BNXT_ULP_INTF_TYPE_VF;
5322 return BNXT_ULP_INTF_TYPE_INVALID;
5326 bnxt_get_phy_port_id(uint16_t port_id)
5328 struct bnxt_representor *vfr;
5329 struct rte_eth_dev *eth_dev;
5332 eth_dev = &rte_eth_devices[port_id];
5333 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5334 vfr = eth_dev->data->dev_private;
5338 eth_dev = vfr->parent_dev;
5341 bp = eth_dev->data->dev_private;
5343 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5347 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5349 struct rte_eth_dev *eth_dev;
5352 eth_dev = &rte_eth_devices[port_id];
5353 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5354 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5358 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5359 return vfr->fw_fid - 1;
5361 eth_dev = vfr->parent_dev;
5364 bp = eth_dev->data->dev_private;
5366 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5370 bnxt_get_vport(uint16_t port_id)
5372 return (1 << bnxt_get_phy_port_id(port_id));
5375 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5377 struct bnxt_error_recovery_info *info = bp->recovery_info;
5380 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5381 memset(info, 0, sizeof(*info));
5385 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5388 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5391 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5393 bp->recovery_info = info;
5396 static void bnxt_check_fw_status(struct bnxt *bp)
5400 if (!(bp->recovery_info &&
5401 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5404 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5405 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5406 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5410 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5412 struct bnxt_error_recovery_info *info = bp->recovery_info;
5413 uint32_t status_loc;
5416 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5417 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5418 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5419 BNXT_GRCP_WINDOW_2_BASE +
5420 offsetof(struct hcomm_status,
5422 /* If the signature is absent, then FW does not support this feature */
5423 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5424 HCOMM_STATUS_SIGNATURE_VAL)
5428 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5432 bp->recovery_info = info;
5434 memset(info, 0, sizeof(*info));
5437 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5438 BNXT_GRCP_WINDOW_2_BASE +
5439 offsetof(struct hcomm_status,
5442 /* Only pre-map the FW health status GRC register */
5443 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5446 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5447 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5448 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5450 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5451 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5453 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5458 static int bnxt_init_fw(struct bnxt *bp)
5465 rc = bnxt_map_hcomm_fw_status_reg(bp);
5469 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5471 bnxt_check_fw_status(bp);
5475 rc = bnxt_hwrm_func_reset(bp);
5479 rc = bnxt_hwrm_vnic_qcaps(bp);
5483 rc = bnxt_hwrm_queue_qportcfg(bp);
5487 /* Get the MAX capabilities for this function.
5488 * This function also allocates context memory for TQM rings and
5489 * informs the firmware about this allocated backing store memory.
5491 rc = bnxt_hwrm_func_qcaps(bp);
5495 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5499 bnxt_hwrm_port_mac_qcfg(bp);
5501 bnxt_hwrm_parent_pf_qcfg(bp);
5503 bnxt_hwrm_port_phy_qcaps(bp);
5505 bnxt_alloc_error_recovery_info(bp);
5506 /* Get the adapter error recovery support info */
5507 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5509 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5511 bnxt_hwrm_port_led_qcaps(bp);
5517 bnxt_init_locks(struct bnxt *bp)
5521 err = pthread_mutex_init(&bp->flow_lock, NULL);
5523 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5527 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5529 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5531 err = pthread_mutex_init(&bp->health_check_lock, NULL);
5533 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5537 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5541 rc = bnxt_init_fw(bp);
5545 if (!reconfig_dev) {
5546 rc = bnxt_setup_mac_addr(bp->eth_dev);
5550 rc = bnxt_restore_dflt_mac(bp);
5555 bnxt_config_vf_req_fwd(bp);
5557 rc = bnxt_hwrm_func_driver_register(bp);
5559 PMD_DRV_LOG(ERR, "Failed to register driver");
5564 if (bp->pdev->max_vfs) {
5565 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5567 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5571 rc = bnxt_hwrm_allocate_pf_only(bp);
5574 "Failed to allocate PF resources");
5580 rc = bnxt_alloc_mem(bp, reconfig_dev);
5584 rc = bnxt_setup_int(bp);
5588 rc = bnxt_request_int(bp);
5592 rc = bnxt_init_ctx_mem(bp);
5594 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5598 rc = bnxt_init_locks(bp);
5606 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5607 const char *value, void *opaque_arg)
5609 struct bnxt *bp = opaque_arg;
5610 unsigned long truflow;
5613 if (!value || !opaque_arg) {
5615 "Invalid parameter passed to truflow devargs.\n");
5619 truflow = strtoul(value, &end, 10);
5620 if (end == NULL || *end != '\0' ||
5621 (truflow == ULONG_MAX && errno == ERANGE)) {
5623 "Invalid parameter passed to truflow devargs.\n");
5627 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5629 "Invalid value passed to truflow devargs.\n");
5634 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5635 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5637 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5638 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5645 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5646 const char *value, void *opaque_arg)
5648 struct bnxt *bp = opaque_arg;
5649 unsigned long flow_xstat;
5652 if (!value || !opaque_arg) {
5654 "Invalid parameter passed to flow_xstat devarg.\n");
5658 flow_xstat = strtoul(value, &end, 10);
5659 if (end == NULL || *end != '\0' ||
5660 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5662 "Invalid parameter passed to flow_xstat devarg.\n");
5666 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5668 "Invalid value passed to flow_xstat devarg.\n");
5672 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5673 if (BNXT_FLOW_XSTATS_EN(bp))
5674 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5680 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5681 const char *value, void *opaque_arg)
5683 struct bnxt *bp = opaque_arg;
5684 unsigned long max_num_kflows;
5687 if (!value || !opaque_arg) {
5689 "Invalid parameter passed to max_num_kflows devarg.\n");
5693 max_num_kflows = strtoul(value, &end, 10);
5694 if (end == NULL || *end != '\0' ||
5695 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5697 "Invalid parameter passed to max_num_kflows devarg.\n");
5701 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5703 "Invalid value passed to max_num_kflows devarg.\n");
5707 bp->max_num_kflows = max_num_kflows;
5708 if (bp->max_num_kflows)
5709 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5716 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5717 const char *value, void *opaque_arg)
5719 struct bnxt_representor *vfr_bp = opaque_arg;
5720 unsigned long rep_is_pf;
5723 if (!value || !opaque_arg) {
5725 "Invalid parameter passed to rep_is_pf devargs.\n");
5729 rep_is_pf = strtoul(value, &end, 10);
5730 if (end == NULL || *end != '\0' ||
5731 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5733 "Invalid parameter passed to rep_is_pf devargs.\n");
5737 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5739 "Invalid value passed to rep_is_pf devargs.\n");
5743 vfr_bp->flags |= rep_is_pf;
5744 if (BNXT_REP_PF(vfr_bp))
5745 PMD_DRV_LOG(INFO, "PF representor\n");
5747 PMD_DRV_LOG(INFO, "VF representor\n");
5753 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5754 const char *value, void *opaque_arg)
5756 struct bnxt_representor *vfr_bp = opaque_arg;
5757 unsigned long rep_based_pf;
5760 if (!value || !opaque_arg) {
5762 "Invalid parameter passed to rep_based_pf "
5767 rep_based_pf = strtoul(value, &end, 10);
5768 if (end == NULL || *end != '\0' ||
5769 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5771 "Invalid parameter passed to rep_based_pf "
5776 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5778 "Invalid value passed to rep_based_pf devargs.\n");
5782 vfr_bp->rep_based_pf = rep_based_pf;
5783 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5789 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5790 const char *value, void *opaque_arg)
5792 struct bnxt_representor *vfr_bp = opaque_arg;
5793 unsigned long rep_q_r2f;
5796 if (!value || !opaque_arg) {
5798 "Invalid parameter passed to rep_q_r2f "
5803 rep_q_r2f = strtoul(value, &end, 10);
5804 if (end == NULL || *end != '\0' ||
5805 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5807 "Invalid parameter passed to rep_q_r2f "
5812 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5814 "Invalid value passed to rep_q_r2f devargs.\n");
5818 vfr_bp->rep_q_r2f = rep_q_r2f;
5819 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5820 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5826 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5827 const char *value, void *opaque_arg)
5829 struct bnxt_representor *vfr_bp = opaque_arg;
5830 unsigned long rep_q_f2r;
5833 if (!value || !opaque_arg) {
5835 "Invalid parameter passed to rep_q_f2r "
5840 rep_q_f2r = strtoul(value, &end, 10);
5841 if (end == NULL || *end != '\0' ||
5842 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5844 "Invalid parameter passed to rep_q_f2r "
5849 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5851 "Invalid value passed to rep_q_f2r devargs.\n");
5855 vfr_bp->rep_q_f2r = rep_q_f2r;
5856 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5857 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5863 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5864 const char *value, void *opaque_arg)
5866 struct bnxt_representor *vfr_bp = opaque_arg;
5867 unsigned long rep_fc_r2f;
5870 if (!value || !opaque_arg) {
5872 "Invalid parameter passed to rep_fc_r2f "
5877 rep_fc_r2f = strtoul(value, &end, 10);
5878 if (end == NULL || *end != '\0' ||
5879 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5881 "Invalid parameter passed to rep_fc_r2f "
5886 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5888 "Invalid value passed to rep_fc_r2f devargs.\n");
5892 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5893 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5894 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5900 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5901 const char *value, void *opaque_arg)
5903 struct bnxt_representor *vfr_bp = opaque_arg;
5904 unsigned long rep_fc_f2r;
5907 if (!value || !opaque_arg) {
5909 "Invalid parameter passed to rep_fc_f2r "
5914 rep_fc_f2r = strtoul(value, &end, 10);
5915 if (end == NULL || *end != '\0' ||
5916 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5918 "Invalid parameter passed to rep_fc_f2r "
5923 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5925 "Invalid value passed to rep_fc_f2r devargs.\n");
5929 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5930 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5931 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5937 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5939 struct rte_kvargs *kvlist;
5941 if (devargs == NULL)
5944 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5949 * Handler for "truflow" devarg.
5950 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5952 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5953 bnxt_parse_devarg_truflow, bp);
5956 * Handler for "flow_xstat" devarg.
5957 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5959 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5960 bnxt_parse_devarg_flow_xstat, bp);
5963 * Handler for "max_num_kflows" devarg.
5964 * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5966 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5967 bnxt_parse_devarg_max_num_kflows, bp);
5969 rte_kvargs_free(kvlist);
5972 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5976 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5977 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5980 "Failed to alloc switch domain: %d\n", rc);
5983 "Switch domain allocated %d\n",
5984 bp->switch_domain_id);
5991 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5993 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5994 static int version_printed;
5998 if (version_printed++ == 0)
5999 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6001 eth_dev->dev_ops = &bnxt_dev_ops;
6002 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6003 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6004 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6005 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6006 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6009 * For secondary processes, we don't initialise any further
6010 * as primary has already done this work.
6012 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6015 rte_eth_copy_pci_info(eth_dev, pci_dev);
6017 bp = eth_dev->data->dev_private;
6019 /* Parse dev arguments passed on when starting the DPDK application. */
6020 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6022 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
6024 if (bnxt_vf_pciid(pci_dev->id.device_id))
6025 bp->flags |= BNXT_FLAG_VF;
6027 if (bnxt_thor_device(pci_dev->id.device_id))
6028 bp->flags |= BNXT_FLAG_THOR_CHIP;
6030 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
6031 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
6032 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
6033 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
6034 bp->flags |= BNXT_FLAG_STINGRAY;
6036 rc = bnxt_init_board(eth_dev);
6039 "Failed to initialize board rc: %x\n", rc);
6043 rc = bnxt_alloc_pf_info(bp);
6047 rc = bnxt_alloc_link_info(bp);
6051 rc = bnxt_alloc_parent_info(bp);
6055 rc = bnxt_alloc_hwrm_resources(bp);
6058 "Failed to allocate hwrm resource rc: %x\n", rc);
6061 rc = bnxt_alloc_leds_info(bp);
6065 rc = bnxt_alloc_cos_queues(bp);
6069 rc = bnxt_init_resources(bp, false);
6073 rc = bnxt_alloc_stats_mem(bp);
6077 bnxt_alloc_switch_domain(bp);
6080 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
6081 pci_dev->mem_resource[0].phys_addr,
6082 pci_dev->mem_resource[0].addr);
6087 bnxt_dev_uninit(eth_dev);
6092 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6101 ctx->dma = RTE_BAD_IOVA;
6102 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6105 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6107 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6108 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6109 bp->flow_stat->rx_fc_out_tbl.ctx_id,
6110 bp->flow_stat->max_fc,
6113 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6114 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6115 bp->flow_stat->tx_fc_out_tbl.ctx_id,
6116 bp->flow_stat->max_fc,
6119 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6120 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6121 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6123 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6124 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6125 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6127 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6128 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6129 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6131 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6132 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6133 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6136 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6138 bnxt_unregister_fc_ctx_mem(bp);
6140 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6141 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6142 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6143 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6146 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6148 if (BNXT_FLOW_XSTATS_EN(bp))
6149 bnxt_uninit_fc_ctx_mem(bp);
6153 bnxt_free_error_recovery_info(struct bnxt *bp)
6155 rte_free(bp->recovery_info);
6156 bp->recovery_info = NULL;
6157 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6161 bnxt_uninit_locks(struct bnxt *bp)
6163 pthread_mutex_destroy(&bp->flow_lock);
6164 pthread_mutex_destroy(&bp->def_cp_lock);
6165 pthread_mutex_destroy(&bp->health_check_lock);
6167 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
6168 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
6173 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6178 bnxt_free_mem(bp, reconfig_dev);
6179 bnxt_hwrm_func_buf_unrgtr(bp);
6180 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6181 bp->flags &= ~BNXT_FLAG_REGISTERED;
6182 bnxt_free_ctx_mem(bp);
6183 if (!reconfig_dev) {
6184 bnxt_free_hwrm_resources(bp);
6185 bnxt_free_error_recovery_info(bp);
6188 bnxt_uninit_ctx_mem(bp);
6190 bnxt_uninit_locks(bp);
6191 bnxt_free_flow_stats_info(bp);
6192 bnxt_free_rep_info(bp);
6193 rte_free(bp->ptp_cfg);
6199 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6201 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6204 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6206 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6207 bnxt_dev_close_op(eth_dev);
6212 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6214 struct bnxt *bp = eth_dev->data->dev_private;
6215 struct rte_eth_dev *vf_rep_eth_dev;
6221 for (i = 0; i < bp->num_reps; i++) {
6222 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6223 if (!vf_rep_eth_dev)
6225 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6226 vf_rep_eth_dev->data->port_id);
6227 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6229 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6230 eth_dev->data->port_id);
6231 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6236 static void bnxt_free_rep_info(struct bnxt *bp)
6238 rte_free(bp->rep_info);
6239 bp->rep_info = NULL;
6240 rte_free(bp->cfa_code_map);
6241 bp->cfa_code_map = NULL;
6244 static int bnxt_init_rep_info(struct bnxt *bp)
6251 bp->rep_info = rte_zmalloc("bnxt_rep_info",
6252 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6254 if (!bp->rep_info) {
6255 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6258 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6259 sizeof(*bp->cfa_code_map) *
6260 BNXT_MAX_CFA_CODE, 0);
6261 if (!bp->cfa_code_map) {
6262 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6263 bnxt_free_rep_info(bp);
6267 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6268 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6270 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6272 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6273 bnxt_free_rep_info(bp);
6277 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6279 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6280 bnxt_free_rep_info(bp);
6287 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6288 struct rte_eth_devargs eth_da,
6289 struct rte_eth_dev *backing_eth_dev,
6290 const char *dev_args)
6292 struct rte_eth_dev *vf_rep_eth_dev;
6293 char name[RTE_ETH_NAME_MAX_LEN];
6294 struct bnxt *backing_bp;
6297 struct rte_kvargs *kvlist;
6299 num_rep = eth_da.nb_representor_ports;
6300 if (num_rep > BNXT_MAX_VF_REPS) {
6301 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6302 num_rep, BNXT_MAX_VF_REPS);
6306 if (num_rep >= RTE_MAX_ETHPORTS) {
6308 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6309 num_rep, RTE_MAX_ETHPORTS);
6313 backing_bp = backing_eth_dev->data->dev_private;
6315 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6317 "Not a PF or trusted VF. No Representor support\n");
6318 /* Returning an error is not an option.
6319 * Applications are not handling this correctly
6324 if (bnxt_init_rep_info(backing_bp))
6327 for (i = 0; i < num_rep; i++) {
6328 struct bnxt_representor representor = {
6329 .vf_id = eth_da.representor_ports[i],
6330 .switch_domain_id = backing_bp->switch_domain_id,
6331 .parent_dev = backing_eth_dev
6334 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6335 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6336 representor.vf_id, BNXT_MAX_VF_REPS);
6340 /* representor port net_bdf_port */
6341 snprintf(name, sizeof(name), "net_%s_representor_%d",
6342 pci_dev->device.name, eth_da.representor_ports[i]);
6344 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6347 * Handler for "rep_is_pf" devarg.
6348 * Invoked as for ex: "-w 000:00:0d.0,
6349 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6351 rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6352 bnxt_parse_devarg_rep_is_pf,
6353 (void *)&representor);
6355 * Handler for "rep_based_pf" devarg.
6356 * Invoked as for ex: "-w 000:00:0d.0,
6357 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6359 rte_kvargs_process(kvlist, BNXT_DEVARG_REP_BASED_PF,
6360 bnxt_parse_devarg_rep_based_pf,
6361 (void *)&representor);
6363 * Handler for "rep_based_pf" devarg.
6364 * Invoked as for ex: "-w 000:00:0d.0,
6365 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6367 rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6368 bnxt_parse_devarg_rep_q_r2f,
6369 (void *)&representor);
6371 * Handler for "rep_based_pf" devarg.
6372 * Invoked as for ex: "-w 000:00:0d.0,
6373 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6375 rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6376 bnxt_parse_devarg_rep_q_f2r,
6377 (void *)&representor);
6379 * Handler for "rep_based_pf" devarg.
6380 * Invoked as for ex: "-w 000:00:0d.0,
6381 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6383 rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6384 bnxt_parse_devarg_rep_fc_r2f,
6385 (void *)&representor);
6387 * Handler for "rep_based_pf" devarg.
6388 * Invoked as for ex: "-w 000:00:0d.0,
6389 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6391 rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6392 bnxt_parse_devarg_rep_fc_f2r,
6393 (void *)&representor);
6396 ret = rte_eth_dev_create(&pci_dev->device, name,
6397 sizeof(struct bnxt_representor),
6399 bnxt_representor_init,
6402 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6403 "representor %s.", name);
6407 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6408 if (!vf_rep_eth_dev) {
6409 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6410 " for VF-Rep: %s.", name);
6415 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6416 backing_eth_dev->data->port_id);
6417 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6419 backing_bp->num_reps++;
6426 /* If num_rep > 1, then rollback already created
6427 * ports, since we'll be failing the probe anyway
6430 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6435 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6436 struct rte_pci_device *pci_dev)
6438 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6439 struct rte_eth_dev *backing_eth_dev;
6443 if (pci_dev->device.devargs) {
6444 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6450 num_rep = eth_da.nb_representor_ports;
6451 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6454 /* We could come here after first level of probe is already invoked
6455 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6456 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6458 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6459 if (backing_eth_dev == NULL) {
6460 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6461 sizeof(struct bnxt),
6462 eth_dev_pci_specific_init, pci_dev,
6463 bnxt_dev_init, NULL);
6465 if (ret || !num_rep)
6468 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6470 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6471 backing_eth_dev->data->port_id);
6476 /* probe representor ports now */
6477 ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
6478 pci_dev->device.devargs->args);
6483 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6485 struct rte_eth_dev *eth_dev;
6487 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6489 return 0; /* Invoked typically only by OVS-DPDK, by the
6490 * time it comes here the eth_dev is already
6491 * deleted by rte_eth_dev_close(), so returning
6492 * +ve value will at least help in proper cleanup
6495 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6496 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6497 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6498 return rte_eth_dev_destroy(eth_dev,
6499 bnxt_representor_uninit);
6501 return rte_eth_dev_destroy(eth_dev,
6504 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6508 static struct rte_pci_driver bnxt_rte_pmd = {
6509 .id_table = bnxt_pci_id_map,
6510 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6511 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6514 .probe = bnxt_pci_probe,
6515 .remove = bnxt_pci_remove,
6519 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6521 if (strcmp(dev->device->driver->name, drv->driver.name))
6527 bool is_bnxt_supported(struct rte_eth_dev *dev)
6529 return is_device_supported(dev, &bnxt_rte_pmd);
6532 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6533 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6534 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6535 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");