1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
6 #ifndef _BNXT_FILTER_H_
7 #define _BNXT_FILTER_H_
13 #define BNXT_FLOW_L2_VALID_FLAG BIT(0)
14 #define BNXT_FLOW_L2_SRC_VALID_FLAG BIT(1)
15 #define BNXT_FLOW_L2_INNER_SRC_VALID_FLAG BIT(2)
16 #define BNXT_FLOW_L2_DST_VALID_FLAG BIT(3)
17 #define BNXT_FLOW_L2_INNER_DST_VALID_FLAG BIT(4)
19 struct bnxt_filter_info {
20 STAILQ_ENTRY(bnxt_filter_info) next;
21 uint64_t fw_l2_filter_id;
22 uint64_t fw_em_filter_id;
23 uint64_t fw_ntuple_filter_id;
24 #define INVALID_MAC_INDEX ((uint16_t)-1)
26 #define HWRM_CFA_L2_FILTER 0
27 #define HWRM_CFA_EM_FILTER 1
28 #define HWRM_CFA_NTUPLE_FILTER 2
29 #define HWRM_CFA_TUNNEL_REDIRECT_FILTER 3
33 /* Filter Characteristics */
36 uint8_t l2_addr[RTE_ETHER_ADDR_LEN];
37 uint8_t l2_addr_mask[RTE_ETHER_ADDR_LEN];
40 uint16_t l2_ovlan_mask;
42 uint16_t l2_ivlan_mask;
43 uint8_t t_l2_addr[RTE_ETHER_ADDR_LEN];
44 uint8_t t_l2_addr_mask[RTE_ETHER_ADDR_LEN];
46 uint16_t t_l2_ovlan_mask;
48 uint16_t t_l2_ivlan_mask;
50 uint16_t mirror_vnic_id;
53 uint64_t l2_filter_id_hint;
56 uint8_t src_macaddr[6];
57 uint8_t dst_macaddr[6];
58 uint32_t dst_ipaddr[4];
59 uint32_t dst_ipaddr_mask[4];
60 uint32_t src_ipaddr[4];
61 uint32_t src_ipaddr_mask[4];
63 uint16_t dst_port_mask;
65 uint16_t src_port_mask;
67 uint16_t ip_addr_type;
71 struct bnxt_filter_info *bnxt_alloc_filter(struct bnxt *bp);
72 struct bnxt_filter_info *bnxt_alloc_vf_filter(struct bnxt *bp, uint16_t vf);
73 void bnxt_init_filters(struct bnxt *bp);
74 void bnxt_free_all_filters(struct bnxt *bp);
75 void bnxt_free_filter_mem(struct bnxt *bp);
76 int bnxt_alloc_filter_mem(struct bnxt *bp);
77 struct bnxt_filter_info *bnxt_get_unused_filter(struct bnxt *bp);
78 void bnxt_free_filter(struct bnxt *bp, struct bnxt_filter_info *filter);
79 struct bnxt_filter_info *bnxt_get_l2_filter(struct bnxt *bp,
80 struct bnxt_filter_info *nf, struct bnxt_vnic_info *vnic);
82 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_MACADDR \
83 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR
84 #define EM_FLOW_ALLOC_INPUT_EN_SRC_MACADDR \
85 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR
86 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR \
87 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR
88 #define EM_FLOW_ALLOC_INPUT_EN_DST_MACADDR \
89 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR
90 #define NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE \
91 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE
92 #define EM_FLOW_ALLOC_INPUT_EN_ETHERTYPE \
93 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE
94 #define EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID \
95 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID
96 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR \
97 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR
98 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK \
99 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK
100 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR \
101 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR
102 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK \
103 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK
104 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT \
105 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT
106 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK \
107 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK
108 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT \
109 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT
110 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK \
111 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK
112 #define NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO \
113 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL
114 #define EM_FLOW_ALLOC_INPUT_EN_SRC_IPADDR \
115 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR
116 #define EM_FLOW_ALLOC_INPUT_EN_DST_IPADDR \
117 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR
118 #define EM_FLOW_ALLOC_INPUT_EN_SRC_PORT \
119 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT
120 #define EM_FLOW_ALLOC_INPUT_EN_DST_PORT \
121 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT
122 #define EM_FLOW_ALLOC_INPUT_EN_IP_PROTO \
123 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL
124 #define EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
125 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
126 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
127 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
128 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN \
129 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN
130 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE \
131 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE
132 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE \
133 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE
134 #define L2_FILTER_ALLOC_INPUT_EN_L2_ADDR_MASK \
135 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK
136 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UDP \
137 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
138 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_TCP \
139 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP
140 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
141 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN
142 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
143 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4
144 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID \
145 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
146 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID \
147 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID