1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SHORT_CMD_TIMEOUT 50000
31 #define HWRM_SPEC_CODE_1_8_3 0x10803
32 #define HWRM_VERSION_1_9_1 0x10901
33 #define HWRM_VERSION_1_9_2 0x10903
35 struct bnxt_plcmodes_cfg {
37 uint16_t jumbo_thresh;
39 uint16_t hds_threshold;
42 static int page_getenum(size_t size)
58 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
59 return sizeof(void *) * 8 - 1;
62 static int page_roundup(size_t size)
64 return 1 << page_getenum(size);
67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
71 if (rmem->nr_pages > 1) {
73 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
75 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
80 * HWRM Functions (sent to HWRM)
81 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
82 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
83 * command was failed by the ChiMP.
86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
87 uint32_t msg_len, bool use_kong_mb)
90 struct input *req = msg;
91 struct output *resp = bp->hwrm_cmd_resp_addr;
95 uint16_t max_req_len = bp->max_req_len;
96 struct hwrm_short_input short_input = { 0 };
97 uint16_t bar_offset = use_kong_mb ?
98 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
99 uint16_t mb_trigger_offset = use_kong_mb ?
100 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
103 /* Do not send HWRM commands to firmware in error state */
104 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
107 /* For VER_GET command, set timeout as 50ms */
108 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
109 timeout = HWRM_SHORT_CMD_TIMEOUT;
111 timeout = HWRM_CMD_TIMEOUT;
113 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
114 msg_len > bp->max_req_len) {
115 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
117 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
118 memcpy(short_cmd_req, req, msg_len);
120 short_input.req_type = rte_cpu_to_le_16(req->req_type);
121 short_input.signature = rte_cpu_to_le_16(
122 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
123 short_input.size = rte_cpu_to_le_16(msg_len);
124 short_input.req_addr =
125 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
127 data = (uint32_t *)&short_input;
128 msg_len = sizeof(short_input);
130 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
133 /* Write request msg to hwrm channel */
134 for (i = 0; i < msg_len; i += 4) {
135 bar = (uint8_t *)bp->bar0 + bar_offset + i;
136 rte_write32(*data, bar);
140 /* Zero the rest of the request space */
141 for (; i < max_req_len; i += 4) {
142 bar = (uint8_t *)bp->bar0 + bar_offset + i;
146 /* Ring channel doorbell */
147 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
150 * Make sure the channel doorbell ring command complete before
151 * reading the response to avoid getting stale or invalid
156 /* Poll for the valid bit */
157 for (i = 0; i < timeout; i++) {
158 /* Sanity check on the resp->resp_len */
160 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
161 /* Last byte of resp contains the valid key */
162 valid = (uint8_t *)resp + resp->resp_len - 1;
163 if (*valid == HWRM_RESP_VALID_KEY)
170 /* Suppress VER_GET timeout messages during reset recovery */
171 if (bp->flags & BNXT_FLAG_FW_RESET &&
172 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
175 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
183 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
184 * spinlock, and does initial processing.
186 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
187 * releases the spinlock only if it returns. If the regular int return codes
188 * are not used by the function, HWRM_CHECK_RESULT() should not be used
189 * directly, rather it should be copied and modified to suit the function.
191 * HWRM_UNLOCK() must be called after all response processing is completed.
193 #define HWRM_PREP(req, type, kong) do { \
194 rte_spinlock_lock(&bp->hwrm_lock); \
195 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
196 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
197 req.cmpl_ring = rte_cpu_to_le_16(-1); \
198 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
199 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
200 req.target_id = rte_cpu_to_le_16(0xffff); \
201 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
204 #define HWRM_CHECK_RESULT_SILENT() do {\
206 rte_spinlock_unlock(&bp->hwrm_lock); \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 rte_spinlock_unlock(&bp->hwrm_lock); \
216 #define HWRM_CHECK_RESULT() do {\
218 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
219 rte_spinlock_unlock(&bp->hwrm_lock); \
220 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
222 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
224 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
226 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
232 if (resp->error_code) { \
233 rc = rte_le_to_cpu_16(resp->error_code); \
234 if (resp->resp_len >= 16) { \
235 struct hwrm_err_output *tmp_hwrm_err_op = \
238 "error %d:%d:%08x:%04x\n", \
239 rc, tmp_hwrm_err_op->cmd_err, \
241 tmp_hwrm_err_op->opaque_0), \
243 tmp_hwrm_err_op->opaque_1)); \
245 PMD_DRV_LOG(ERR, "error %d\n", rc); \
247 rte_spinlock_unlock(&bp->hwrm_lock); \
248 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
250 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
252 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
254 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
262 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
264 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
267 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
268 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
270 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
271 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
274 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
282 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
283 struct bnxt_vnic_info *vnic,
285 struct bnxt_vlan_table_entry *vlan_table)
288 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
289 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
292 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
295 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
296 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
298 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
299 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
300 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
301 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
303 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
304 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
306 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
307 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
308 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
309 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
310 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
311 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
314 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
315 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
316 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
317 rte_mem_virt2iova(vlan_table));
318 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
320 req.mask = rte_cpu_to_le_32(mask);
322 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
330 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
332 struct bnxt_vlan_antispoof_table_entry *vlan_table)
335 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
336 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
337 bp->hwrm_cmd_resp_addr;
340 * Older HWRM versions did not support this command, and the set_rx_mask
341 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
342 * removed from set_rx_mask call, and this command was added.
344 * This command is also present from 1.7.8.11 and higher,
347 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
348 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
349 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
354 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
355 req.fid = rte_cpu_to_le_16(fid);
357 req.vlan_tag_mask_tbl_addr =
358 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
359 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
361 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
369 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
370 struct bnxt_filter_info *filter)
373 struct bnxt_filter_info *l2_filter = filter;
374 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
375 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
377 if (filter->fw_l2_filter_id == UINT64_MAX)
380 if (filter->matching_l2_fltr_ptr)
381 l2_filter = filter->matching_l2_fltr_ptr;
383 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
384 filter, l2_filter, l2_filter->l2_ref_cnt);
386 if (l2_filter->l2_ref_cnt > 0)
387 l2_filter->l2_ref_cnt--;
389 if (l2_filter->l2_ref_cnt > 0)
392 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
394 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
396 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
401 filter->fw_l2_filter_id = UINT64_MAX;
406 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
408 struct bnxt_filter_info *filter)
411 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
412 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
413 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
414 const struct rte_eth_vmdq_rx_conf *conf =
415 &dev_conf->rx_adv_conf.vmdq_rx_conf;
416 uint32_t enables = 0;
417 uint16_t j = dst_id - 1;
419 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
420 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
421 conf->pool_map[j].pools & (1UL << j)) {
423 "Add vlan %u to vmdq pool %u\n",
424 conf->pool_map[j].vlan_id, j);
426 filter->l2_ivlan = conf->pool_map[j].vlan_id;
428 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
429 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
432 if (filter->fw_l2_filter_id != UINT64_MAX)
433 bnxt_hwrm_clear_l2_filter(bp, filter);
435 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
437 req.flags = rte_cpu_to_le_32(filter->flags);
439 enables = filter->enables |
440 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
441 req.dst_id = rte_cpu_to_le_16(dst_id);
444 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
445 memcpy(req.l2_addr, filter->l2_addr,
448 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
449 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
452 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
453 req.l2_ovlan = filter->l2_ovlan;
455 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
456 req.l2_ivlan = filter->l2_ivlan;
458 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
459 req.l2_ovlan_mask = filter->l2_ovlan_mask;
461 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
462 req.l2_ivlan_mask = filter->l2_ivlan_mask;
463 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
464 req.src_id = rte_cpu_to_le_32(filter->src_id);
465 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
466 req.src_type = filter->src_type;
467 if (filter->pri_hint) {
468 req.pri_hint = filter->pri_hint;
469 req.l2_filter_id_hint =
470 rte_cpu_to_le_64(filter->l2_filter_id_hint);
473 req.enables = rte_cpu_to_le_32(enables);
475 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
479 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
485 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
487 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
488 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
495 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
498 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
501 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
502 if (ptp->tx_tstamp_en)
503 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
506 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
507 req.flags = rte_cpu_to_le_32(flags);
508 req.enables = rte_cpu_to_le_32
509 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
510 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
512 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
518 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
521 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
522 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
523 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
525 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
529 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
531 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
533 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
537 if (!BNXT_CHIP_THOR(bp) &&
538 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
541 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
542 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
544 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
548 if (!BNXT_CHIP_THOR(bp)) {
549 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
550 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
551 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
552 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
553 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
554 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
555 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
556 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
557 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
558 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
559 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
560 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
561 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
562 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
563 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
564 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
565 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
566 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
575 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
578 struct hwrm_func_qcaps_input req = {.req_type = 0 };
579 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
580 uint16_t new_max_vfs;
584 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
586 req.fid = rte_cpu_to_le_16(0xffff);
588 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
592 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
593 flags = rte_le_to_cpu_32(resp->flags);
595 bp->pf.port_id = resp->port_id;
596 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
597 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
598 new_max_vfs = bp->pdev->max_vfs;
599 if (new_max_vfs != bp->pf.max_vfs) {
601 rte_free(bp->pf.vf_info);
602 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
603 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
604 bp->pf.max_vfs = new_max_vfs;
605 for (i = 0; i < new_max_vfs; i++) {
606 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
607 bp->pf.vf_info[i].vlan_table =
608 rte_zmalloc("VF VLAN table",
611 if (bp->pf.vf_info[i].vlan_table == NULL)
613 "Fail to alloc VLAN table for VF %d\n",
617 bp->pf.vf_info[i].vlan_table);
618 bp->pf.vf_info[i].vlan_as_table =
619 rte_zmalloc("VF VLAN AS table",
622 if (bp->pf.vf_info[i].vlan_as_table == NULL)
624 "Alloc VLAN AS table for VF %d fail\n",
628 bp->pf.vf_info[i].vlan_as_table);
629 STAILQ_INIT(&bp->pf.vf_info[i].filter);
634 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
635 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
636 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
637 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
638 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
639 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
640 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
641 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
642 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
643 if (!BNXT_CHIP_THOR(bp))
644 bp->max_l2_ctx += bp->max_rx_em_flows;
645 /* TODO: For now, do not support VMDq/RFS on VFs. */
650 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
654 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
656 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
657 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
658 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
659 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
661 bnxt_hwrm_ptp_qcfg(bp);
665 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
666 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
668 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
669 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
670 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
672 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
675 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
676 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
678 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
685 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
689 rc = __bnxt_hwrm_func_qcaps(bp);
690 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
691 rc = bnxt_alloc_ctx_mem(bp);
695 rc = bnxt_hwrm_func_resc_qcaps(bp);
697 bp->flags |= BNXT_FLAG_NEW_RM;
703 int bnxt_hwrm_func_reset(struct bnxt *bp)
706 struct hwrm_func_reset_input req = {.req_type = 0 };
707 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
709 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
711 req.enables = rte_cpu_to_le_32(0);
713 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
721 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
725 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
726 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
728 if (bp->flags & BNXT_FLAG_REGISTERED)
731 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
732 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
733 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
735 /* PFs and trusted VFs should indicate the support of the
736 * Master capability on non Stingray platform
738 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
739 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
741 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
742 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
743 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
744 req.ver_maj = RTE_VER_YEAR;
745 req.ver_min = RTE_VER_MONTH;
746 req.ver_upd = RTE_VER_MINOR;
749 req.enables |= rte_cpu_to_le_32(
750 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
751 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
752 RTE_MIN(sizeof(req.vf_req_fwd),
753 sizeof(bp->pf.vf_req_fwd)));
756 * PF can sniff HWRM API issued by VF. This can be set up by
757 * linux driver and inherited by the DPDK PF driver. Clear
758 * this HWRM sniffer list in FW because DPDK PF driver does
761 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
764 req.flags = rte_cpu_to_le_32(flags);
766 req.async_event_fwd[0] |=
767 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
768 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
769 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
770 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
771 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
772 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
773 req.async_event_fwd[0] |=
774 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
775 req.async_event_fwd[1] |=
776 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
777 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
779 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
783 flags = rte_le_to_cpu_32(resp->flags);
784 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
785 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
789 bp->flags |= BNXT_FLAG_REGISTERED;
794 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
796 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
799 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
802 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
807 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
808 struct hwrm_func_vf_cfg_input req = {0};
810 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
812 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
813 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
814 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
815 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
816 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
818 if (BNXT_HAS_RING_GRPS(bp)) {
819 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
820 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
823 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
824 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
825 AGG_RING_MULTIPLIER);
826 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
828 BNXT_NUM_ASYNC_CPR(bp));
829 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
831 BNXT_NUM_ASYNC_CPR(bp));
832 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
833 if (bp->vf_resv_strategy ==
834 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
835 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
836 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
837 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
838 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
839 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
840 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
844 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
845 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
846 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
847 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
848 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
849 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
851 if (test && BNXT_HAS_RING_GRPS(bp))
852 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
854 req.flags = rte_cpu_to_le_32(flags);
855 req.enables |= rte_cpu_to_le_32(enables);
857 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
860 HWRM_CHECK_RESULT_SILENT();
868 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
871 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
872 struct hwrm_func_resource_qcaps_input req = {0};
874 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
875 req.fid = rte_cpu_to_le_16(0xffff);
877 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
882 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
883 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
884 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
885 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
886 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
887 /* func_resource_qcaps does not return max_rx_em_flows.
888 * So use the value provided by func_qcaps.
890 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
891 if (!BNXT_CHIP_THOR(bp))
892 bp->max_l2_ctx += bp->max_rx_em_flows;
893 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
894 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
896 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
897 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
898 if (bp->vf_resv_strategy >
899 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
900 bp->vf_resv_strategy =
901 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
907 int bnxt_hwrm_ver_get(struct bnxt *bp)
910 struct hwrm_ver_get_input req = {.req_type = 0 };
911 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
913 uint16_t max_resp_len;
914 char type[RTE_MEMZONE_NAMESIZE];
915 uint32_t dev_caps_cfg;
917 bp->max_req_len = HWRM_MAX_REQ_LEN;
918 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
920 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
921 req.hwrm_intf_min = HWRM_VERSION_MINOR;
922 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
924 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
926 if (bp->flags & BNXT_FLAG_FW_RESET)
927 HWRM_CHECK_RESULT_SILENT();
931 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
932 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
933 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
934 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
935 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
936 (resp->hwrm_fw_min_8b << 16) |
937 (resp->hwrm_fw_bld_8b << 8) |
938 resp->hwrm_fw_rsvd_8b;
939 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
940 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
942 fw_version = resp->hwrm_intf_maj_8b << 16;
943 fw_version |= resp->hwrm_intf_min_8b << 8;
944 fw_version |= resp->hwrm_intf_upd_8b;
945 bp->hwrm_spec_code = fw_version;
947 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
948 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
953 if (bp->max_req_len > resp->max_req_win_len) {
954 PMD_DRV_LOG(ERR, "Unsupported request length\n");
957 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
958 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
959 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
960 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
962 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
963 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
965 if (bp->max_resp_len != max_resp_len) {
966 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
967 bp->pdev->addr.domain, bp->pdev->addr.bus,
968 bp->pdev->addr.devid, bp->pdev->addr.function);
970 rte_free(bp->hwrm_cmd_resp_addr);
972 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
973 if (bp->hwrm_cmd_resp_addr == NULL) {
977 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
978 bp->hwrm_cmd_resp_dma_addr =
979 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
980 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
982 "Unable to map response buffer to physical memory.\n");
986 bp->max_resp_len = max_resp_len;
990 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
992 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
993 PMD_DRV_LOG(DEBUG, "Short command supported\n");
994 bp->flags |= BNXT_FLAG_SHORT_CMD;
998 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1000 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1001 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1002 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1003 bp->pdev->addr.domain, bp->pdev->addr.bus,
1004 bp->pdev->addr.devid, bp->pdev->addr.function);
1006 rte_free(bp->hwrm_short_cmd_req_addr);
1008 bp->hwrm_short_cmd_req_addr =
1009 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1010 if (bp->hwrm_short_cmd_req_addr == NULL) {
1014 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1015 bp->hwrm_short_cmd_req_dma_addr =
1016 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1017 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1018 rte_free(bp->hwrm_short_cmd_req_addr);
1020 "Unable to map buffer to physical memory.\n");
1026 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1027 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1028 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1031 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1032 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1034 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1035 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1036 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1044 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1047 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1048 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1050 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1053 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1056 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1058 HWRM_CHECK_RESULT();
1064 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1067 struct hwrm_port_phy_cfg_input req = {0};
1068 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1069 uint32_t enables = 0;
1071 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1073 if (conf->link_up) {
1074 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1075 if (bp->link_info.auto_mode && conf->link_speed) {
1076 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1077 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1080 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1081 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1082 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1084 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1085 * any auto mode, even "none".
1087 if (!conf->link_speed) {
1088 /* No speeds specified. Enable AutoNeg - all speeds */
1090 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1092 /* AutoNeg - Advertise speeds specified. */
1093 if (conf->auto_link_speed_mask &&
1094 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1096 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1097 req.auto_link_speed_mask =
1098 conf->auto_link_speed_mask;
1100 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1103 req.auto_duplex = conf->duplex;
1104 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1105 req.auto_pause = conf->auto_pause;
1106 req.force_pause = conf->force_pause;
1107 /* Set force_pause if there is no auto or if there is a force */
1108 if (req.auto_pause && !req.force_pause)
1109 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1111 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1113 req.enables = rte_cpu_to_le_32(enables);
1116 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1117 PMD_DRV_LOG(INFO, "Force Link Down\n");
1120 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1122 HWRM_CHECK_RESULT();
1128 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1129 struct bnxt_link_info *link_info)
1132 struct hwrm_port_phy_qcfg_input req = {0};
1133 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1135 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1137 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1139 HWRM_CHECK_RESULT();
1141 link_info->phy_link_status = resp->link;
1142 link_info->link_up =
1143 (link_info->phy_link_status ==
1144 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1145 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1146 link_info->duplex = resp->duplex_cfg;
1147 link_info->pause = resp->pause;
1148 link_info->auto_pause = resp->auto_pause;
1149 link_info->force_pause = resp->force_pause;
1150 link_info->auto_mode = resp->auto_mode;
1151 link_info->phy_type = resp->phy_type;
1152 link_info->media_type = resp->media_type;
1154 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1155 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1156 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1157 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1158 link_info->phy_ver[0] = resp->phy_maj;
1159 link_info->phy_ver[1] = resp->phy_min;
1160 link_info->phy_ver[2] = resp->phy_bld;
1164 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1165 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1166 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1167 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1168 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1169 link_info->auto_link_speed_mask);
1170 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1171 link_info->force_link_speed);
1176 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1179 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1180 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1183 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1185 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1186 /* HWRM Version >= 1.9.1 */
1187 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1189 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1190 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1192 HWRM_CHECK_RESULT();
1194 #define GET_QUEUE_INFO(x) \
1195 bp->cos_queue[x].id = resp->queue_id##x; \
1196 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1209 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1210 bp->tx_cosq_id = bp->cos_queue[0].id;
1212 /* iterate and find the COSq profile to use for Tx */
1213 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1214 if (bp->cos_queue[i].profile ==
1215 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1216 bp->tx_cosq_id = bp->cos_queue[i].id;
1222 bp->max_tc = resp->max_configurable_queues;
1223 bp->max_lltc = resp->max_configurable_lossless_queues;
1224 if (bp->max_tc > BNXT_MAX_QUEUE)
1225 bp->max_tc = BNXT_MAX_QUEUE;
1226 bp->max_q = bp->max_tc;
1228 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1233 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1234 struct bnxt_ring *ring,
1235 uint32_t ring_type, uint32_t map_index,
1236 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1239 uint32_t enables = 0;
1240 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1241 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1242 struct rte_mempool *mb_pool;
1243 uint16_t rx_buf_size;
1245 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1247 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1248 req.fbo = rte_cpu_to_le_32(0);
1249 /* Association of ring index with doorbell index */
1250 req.logical_id = rte_cpu_to_le_16(map_index);
1251 req.length = rte_cpu_to_le_32(ring->ring_size);
1253 switch (ring_type) {
1254 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1255 req.ring_type = ring_type;
1256 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1257 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1258 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1259 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1261 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1263 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1264 req.ring_type = ring_type;
1265 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1266 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1267 if (BNXT_CHIP_THOR(bp)) {
1268 mb_pool = bp->rx_queues[0]->mb_pool;
1269 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1270 RTE_PKTMBUF_HEADROOM;
1271 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1272 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1274 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1276 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1278 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1280 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1281 req.ring_type = ring_type;
1282 if (BNXT_HAS_NQ(bp)) {
1283 /* Association of cp ring with nq */
1284 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1286 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1288 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1290 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1291 req.ring_type = ring_type;
1292 req.page_size = BNXT_PAGE_SHFT;
1293 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1295 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1296 req.ring_type = ring_type;
1297 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1299 mb_pool = bp->rx_queues[0]->mb_pool;
1300 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1301 RTE_PKTMBUF_HEADROOM;
1302 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1303 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1305 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1306 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1307 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1308 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1311 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1316 req.enables = rte_cpu_to_le_32(enables);
1318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1320 if (rc || resp->error_code) {
1321 if (rc == 0 && resp->error_code)
1322 rc = rte_le_to_cpu_16(resp->error_code);
1323 switch (ring_type) {
1324 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1326 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1329 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1331 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1334 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1336 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1340 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1342 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1345 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1347 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1351 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1357 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1362 int bnxt_hwrm_ring_free(struct bnxt *bp,
1363 struct bnxt_ring *ring, uint32_t ring_type)
1366 struct hwrm_ring_free_input req = {.req_type = 0 };
1367 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1369 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1371 req.ring_type = ring_type;
1372 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1374 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1376 if (rc || resp->error_code) {
1377 if (rc == 0 && resp->error_code)
1378 rc = rte_le_to_cpu_16(resp->error_code);
1381 switch (ring_type) {
1382 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1383 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1386 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1387 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1390 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1391 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1394 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1396 "hwrm_ring_free nq failed. rc:%d\n", rc);
1398 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1400 "hwrm_ring_free agg failed. rc:%d\n", rc);
1403 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1411 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1414 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1415 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1417 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1419 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1420 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1421 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1422 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1424 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1426 HWRM_CHECK_RESULT();
1428 bp->grp_info[idx].fw_grp_id =
1429 rte_le_to_cpu_16(resp->ring_group_id);
1436 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1439 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1440 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1442 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1444 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1446 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1448 HWRM_CHECK_RESULT();
1451 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1455 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1458 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1459 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1461 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1464 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1466 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1468 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1470 HWRM_CHECK_RESULT();
1476 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1477 unsigned int idx __rte_unused)
1480 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1481 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1483 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1485 req.update_period_ms = rte_cpu_to_le_32(0);
1487 req.stats_dma_addr =
1488 rte_cpu_to_le_64(cpr->hw_stats_map);
1490 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1492 HWRM_CHECK_RESULT();
1494 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1501 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1502 unsigned int idx __rte_unused)
1505 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1506 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1508 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1510 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1512 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1514 HWRM_CHECK_RESULT();
1520 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1523 struct hwrm_vnic_alloc_input req = { 0 };
1524 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1526 if (!BNXT_HAS_RING_GRPS(bp))
1527 goto skip_ring_grps;
1529 /* map ring groups to this vnic */
1530 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1531 vnic->start_grp_id, vnic->end_grp_id);
1532 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1533 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1535 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1536 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1537 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1538 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1541 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1542 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1543 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1545 if (vnic->func_default)
1547 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1548 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1550 HWRM_CHECK_RESULT();
1552 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1554 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1558 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1559 struct bnxt_vnic_info *vnic,
1560 struct bnxt_plcmodes_cfg *pmode)
1563 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1564 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1566 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1568 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1570 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1572 HWRM_CHECK_RESULT();
1574 pmode->flags = rte_le_to_cpu_32(resp->flags);
1575 /* dflt_vnic bit doesn't exist in the _cfg command */
1576 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1577 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1578 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1579 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1586 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1587 struct bnxt_vnic_info *vnic,
1588 struct bnxt_plcmodes_cfg *pmode)
1591 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1592 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1594 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1595 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1599 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1601 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1602 req.flags = rte_cpu_to_le_32(pmode->flags);
1603 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1604 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1605 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1606 req.enables = rte_cpu_to_le_32(
1607 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1608 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1609 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1612 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1614 HWRM_CHECK_RESULT();
1620 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1623 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1624 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1625 struct bnxt_plcmodes_cfg pmodes = { 0 };
1626 uint32_t ctx_enable_flag = 0;
1627 uint32_t enables = 0;
1629 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1630 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1634 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1638 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1640 if (BNXT_CHIP_THOR(bp)) {
1641 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1642 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1643 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1645 req.default_rx_ring_id =
1646 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1647 req.default_cmpl_ring_id =
1648 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1649 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1650 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1654 /* Only RSS support for now TBD: COS & LB */
1655 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1656 if (vnic->lb_rule != 0xffff)
1657 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1658 if (vnic->cos_rule != 0xffff)
1659 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1660 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1661 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1662 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1664 enables |= ctx_enable_flag;
1665 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1666 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1667 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1668 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1671 req.enables = rte_cpu_to_le_32(enables);
1672 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1673 req.mru = rte_cpu_to_le_16(vnic->mru);
1674 /* Configure default VNIC only once. */
1675 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1677 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1678 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1680 if (vnic->vlan_strip)
1682 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1685 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1686 if (vnic->roce_dual)
1687 req.flags |= rte_cpu_to_le_32(
1688 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1689 if (vnic->roce_only)
1690 req.flags |= rte_cpu_to_le_32(
1691 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1692 if (vnic->rss_dflt_cr)
1693 req.flags |= rte_cpu_to_le_32(
1694 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1696 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1698 HWRM_CHECK_RESULT();
1701 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1706 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1710 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1711 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1713 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1714 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1717 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1720 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1721 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1722 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1724 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1726 HWRM_CHECK_RESULT();
1728 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1729 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1730 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1731 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1732 vnic->mru = rte_le_to_cpu_16(resp->mru);
1733 vnic->func_default = rte_le_to_cpu_32(
1734 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1735 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1736 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1737 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1738 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1739 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1740 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1741 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1742 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1743 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1744 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1751 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1752 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1756 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1757 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1758 bp->hwrm_cmd_resp_addr;
1760 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1762 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1763 HWRM_CHECK_RESULT();
1765 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1766 if (!BNXT_HAS_RING_GRPS(bp))
1767 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1768 else if (ctx_idx == 0)
1769 vnic->rss_rule = ctx_id;
1777 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1778 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1781 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1782 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1783 bp->hwrm_cmd_resp_addr;
1785 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1786 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1789 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1791 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1793 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1795 HWRM_CHECK_RESULT();
1801 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1805 if (BNXT_CHIP_THOR(bp)) {
1808 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1809 rc = _bnxt_hwrm_vnic_ctx_free(bp,
1811 vnic->fw_grp_ids[j]);
1812 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1814 vnic->num_lb_ctxts = 0;
1816 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1817 vnic->rss_rule = INVALID_HW_RING_ID;
1823 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1826 struct hwrm_vnic_free_input req = {.req_type = 0 };
1827 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1829 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1830 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1834 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1836 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1838 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1840 HWRM_CHECK_RESULT();
1843 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1844 /* Configure default VNIC again if necessary. */
1845 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1846 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1852 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1856 int nr_ctxs = vnic->num_lb_ctxts;
1857 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1858 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1860 for (i = 0; i < nr_ctxs; i++) {
1861 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1863 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1864 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1865 req.hash_mode_flags = vnic->hash_mode;
1867 req.hash_key_tbl_addr =
1868 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1870 req.ring_grp_tbl_addr =
1871 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1872 i * HW_HASH_INDEX_SIZE);
1873 req.ring_table_pair_index = i;
1874 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1876 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1879 HWRM_CHECK_RESULT();
1886 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1887 struct bnxt_vnic_info *vnic)
1890 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1891 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1893 if (!vnic->rss_table)
1896 if (BNXT_CHIP_THOR(bp))
1897 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1899 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1901 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1902 req.hash_mode_flags = vnic->hash_mode;
1904 req.ring_grp_tbl_addr =
1905 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1906 req.hash_key_tbl_addr =
1907 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1908 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1909 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1911 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1913 HWRM_CHECK_RESULT();
1919 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1920 struct bnxt_vnic_info *vnic)
1923 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1924 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1927 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1928 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1932 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1934 req.flags = rte_cpu_to_le_32(
1935 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1937 req.enables = rte_cpu_to_le_32(
1938 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1940 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1941 size -= RTE_PKTMBUF_HEADROOM;
1942 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1944 req.jumbo_thresh = rte_cpu_to_le_16(size);
1945 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1947 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1949 HWRM_CHECK_RESULT();
1955 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1956 struct bnxt_vnic_info *vnic, bool enable)
1959 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1960 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1962 if (BNXT_CHIP_THOR(bp))
1965 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1966 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
1970 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1973 req.enables = rte_cpu_to_le_32(
1974 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1975 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1976 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1977 req.flags = rte_cpu_to_le_32(
1978 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1979 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1980 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1981 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1982 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1983 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1984 req.max_agg_segs = rte_cpu_to_le_16(5);
1986 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1987 req.min_agg_len = rte_cpu_to_le_32(512);
1989 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1991 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1993 HWRM_CHECK_RESULT();
1999 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2001 struct hwrm_func_cfg_input req = {0};
2002 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2005 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2006 req.enables = rte_cpu_to_le_32(
2007 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2008 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2009 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2011 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2013 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2014 HWRM_CHECK_RESULT();
2017 bp->pf.vf_info[vf].random_mac = false;
2022 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2026 struct hwrm_func_qstats_input req = {.req_type = 0};
2027 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2029 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2031 req.fid = rte_cpu_to_le_16(fid);
2033 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2035 HWRM_CHECK_RESULT();
2038 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2045 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2046 struct rte_eth_stats *stats)
2049 struct hwrm_func_qstats_input req = {.req_type = 0};
2050 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2052 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2054 req.fid = rte_cpu_to_le_16(fid);
2056 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2058 HWRM_CHECK_RESULT();
2060 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2061 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2062 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2063 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2064 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2065 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2067 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2068 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2069 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2070 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2071 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2072 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2074 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2075 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2076 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2083 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2086 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2087 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2089 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2091 req.fid = rte_cpu_to_le_16(fid);
2093 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2095 HWRM_CHECK_RESULT();
2102 * HWRM utility functions
2105 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2110 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2111 struct bnxt_tx_queue *txq;
2112 struct bnxt_rx_queue *rxq;
2113 struct bnxt_cp_ring_info *cpr;
2115 if (i >= bp->rx_cp_nr_rings) {
2116 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2119 rxq = bp->rx_queues[i];
2123 rc = bnxt_hwrm_stat_clear(bp, cpr);
2130 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2134 struct bnxt_cp_ring_info *cpr;
2136 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2138 if (i >= bp->rx_cp_nr_rings) {
2139 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2141 cpr = bp->rx_queues[i]->cp_ring;
2142 if (BNXT_HAS_RING_GRPS(bp))
2143 bp->grp_info[i].fw_stats_ctx = -1;
2145 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2146 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2147 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2155 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2160 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2161 struct bnxt_tx_queue *txq;
2162 struct bnxt_rx_queue *rxq;
2163 struct bnxt_cp_ring_info *cpr;
2165 if (i >= bp->rx_cp_nr_rings) {
2166 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2169 rxq = bp->rx_queues[i];
2173 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2181 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2186 if (!BNXT_HAS_RING_GRPS(bp))
2189 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2191 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2194 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2202 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2204 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2206 bnxt_hwrm_ring_free(bp, cp_ring,
2207 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2208 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2209 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2210 sizeof(*cpr->cp_desc_ring));
2211 cpr->cp_raw_cons = 0;
2215 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2217 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2219 bnxt_hwrm_ring_free(bp, cp_ring,
2220 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2221 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2222 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2223 sizeof(*cpr->cp_desc_ring));
2224 cpr->cp_raw_cons = 0;
2228 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2230 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2231 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2232 struct bnxt_ring *ring = rxr->rx_ring_struct;
2233 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2235 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2236 bnxt_hwrm_ring_free(bp, ring,
2237 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2238 ring->fw_ring_id = INVALID_HW_RING_ID;
2239 if (BNXT_HAS_RING_GRPS(bp))
2240 bp->grp_info[queue_index].rx_fw_ring_id =
2242 memset(rxr->rx_desc_ring, 0,
2243 rxr->rx_ring_struct->ring_size *
2244 sizeof(*rxr->rx_desc_ring));
2245 memset(rxr->rx_buf_ring, 0,
2246 rxr->rx_ring_struct->ring_size *
2247 sizeof(*rxr->rx_buf_ring));
2250 ring = rxr->ag_ring_struct;
2251 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2252 bnxt_hwrm_ring_free(bp, ring,
2253 BNXT_CHIP_THOR(bp) ?
2254 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2255 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2256 ring->fw_ring_id = INVALID_HW_RING_ID;
2257 memset(rxr->ag_buf_ring, 0,
2258 rxr->ag_ring_struct->ring_size *
2259 sizeof(*rxr->ag_buf_ring));
2261 if (BNXT_HAS_RING_GRPS(bp))
2262 bp->grp_info[queue_index].ag_fw_ring_id =
2265 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2266 bnxt_free_cp_ring(bp, cpr);
2268 bnxt_free_nq_ring(bp, rxq->nq_ring);
2271 if (BNXT_HAS_RING_GRPS(bp))
2272 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2275 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2279 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2280 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2281 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2282 struct bnxt_ring *ring = txr->tx_ring_struct;
2283 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2285 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2286 bnxt_hwrm_ring_free(bp, ring,
2287 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2288 ring->fw_ring_id = INVALID_HW_RING_ID;
2289 memset(txr->tx_desc_ring, 0,
2290 txr->tx_ring_struct->ring_size *
2291 sizeof(*txr->tx_desc_ring));
2292 memset(txr->tx_buf_ring, 0,
2293 txr->tx_ring_struct->ring_size *
2294 sizeof(*txr->tx_buf_ring));
2298 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2299 bnxt_free_cp_ring(bp, cpr);
2300 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2302 bnxt_free_nq_ring(bp, txq->nq_ring);
2306 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2307 bnxt_free_hwrm_rx_ring(bp, i);
2312 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2317 if (!BNXT_HAS_RING_GRPS(bp))
2320 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2321 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2328 void bnxt_free_hwrm_resources(struct bnxt *bp)
2330 /* Release memzone */
2331 rte_free(bp->hwrm_cmd_resp_addr);
2332 rte_free(bp->hwrm_short_cmd_req_addr);
2333 bp->hwrm_cmd_resp_addr = NULL;
2334 bp->hwrm_short_cmd_req_addr = NULL;
2335 bp->hwrm_cmd_resp_dma_addr = 0;
2336 bp->hwrm_short_cmd_req_dma_addr = 0;
2339 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2341 struct rte_pci_device *pdev = bp->pdev;
2342 char type[RTE_MEMZONE_NAMESIZE];
2344 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2345 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2346 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2347 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2348 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2349 if (bp->hwrm_cmd_resp_addr == NULL)
2351 bp->hwrm_cmd_resp_dma_addr =
2352 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2353 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2355 "unable to map response address to physical memory\n");
2358 rte_spinlock_init(&bp->hwrm_lock);
2363 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2365 struct bnxt_filter_info *filter;
2368 STAILQ_FOREACH(filter, &vnic->filter, next) {
2369 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2370 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2371 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2372 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2374 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2375 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2376 bnxt_free_filter(bp, filter);
2384 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2386 struct bnxt_filter_info *filter;
2387 struct rte_flow *flow;
2390 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2391 flow = STAILQ_FIRST(&vnic->flow_list);
2392 filter = flow->filter;
2393 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2394 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2395 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2396 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2397 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2399 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2401 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2409 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2411 struct bnxt_filter_info *filter;
2414 STAILQ_FOREACH(filter, &vnic->filter, next) {
2415 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2416 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2418 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2419 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2422 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2433 void bnxt_free_tunnel_ports(struct bnxt *bp)
2435 if (bp->vxlan_port_cnt)
2436 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2437 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2439 if (bp->geneve_port_cnt)
2440 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2441 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2442 bp->geneve_port = 0;
2445 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2449 if (bp->vnic_info == NULL)
2453 * Cleanup VNICs in reverse order, to make sure the L2 filter
2454 * from vnic0 is last to be cleaned up.
2456 for (i = bp->max_vnics - 1; i >= 0; i--) {
2457 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2459 // If the VNIC ID is invalid we are not currently using the VNIC
2460 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2463 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2465 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2467 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2469 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2471 bnxt_hwrm_vnic_free(bp, vnic);
2473 rte_free(vnic->fw_grp_ids);
2475 /* Ring resources */
2476 bnxt_free_all_hwrm_rings(bp);
2477 bnxt_free_all_hwrm_ring_grps(bp);
2478 bnxt_free_all_hwrm_stat_ctxs(bp);
2479 bnxt_free_tunnel_ports(bp);
2482 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2484 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2486 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2487 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2489 switch (conf_link_speed) {
2490 case ETH_LINK_SPEED_10M_HD:
2491 case ETH_LINK_SPEED_100M_HD:
2493 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2495 return hw_link_duplex;
2498 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2500 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2503 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2505 uint16_t eth_link_speed = 0;
2507 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2508 return ETH_LINK_SPEED_AUTONEG;
2510 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2511 case ETH_LINK_SPEED_100M:
2512 case ETH_LINK_SPEED_100M_HD:
2515 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2517 case ETH_LINK_SPEED_1G:
2519 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2521 case ETH_LINK_SPEED_2_5G:
2523 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2525 case ETH_LINK_SPEED_10G:
2527 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2529 case ETH_LINK_SPEED_20G:
2531 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2533 case ETH_LINK_SPEED_25G:
2535 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2537 case ETH_LINK_SPEED_40G:
2539 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2541 case ETH_LINK_SPEED_50G:
2543 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2545 case ETH_LINK_SPEED_100G:
2547 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2551 "Unsupported link speed %d; default to AUTO\n",
2555 return eth_link_speed;
2558 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2559 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2560 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2561 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2563 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2567 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2570 if (link_speed & ETH_LINK_SPEED_FIXED) {
2571 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2573 if (one_speed & (one_speed - 1)) {
2575 "Invalid advertised speeds (%u) for port %u\n",
2576 link_speed, port_id);
2579 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2581 "Unsupported advertised speed (%u) for port %u\n",
2582 link_speed, port_id);
2586 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2588 "Unsupported advertised speeds (%u) for port %u\n",
2589 link_speed, port_id);
2597 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2601 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2602 if (bp->link_info.support_speeds)
2603 return bp->link_info.support_speeds;
2604 link_speed = BNXT_SUPPORTED_SPEEDS;
2607 if (link_speed & ETH_LINK_SPEED_100M)
2608 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2609 if (link_speed & ETH_LINK_SPEED_100M_HD)
2610 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2611 if (link_speed & ETH_LINK_SPEED_1G)
2612 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2613 if (link_speed & ETH_LINK_SPEED_2_5G)
2614 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2615 if (link_speed & ETH_LINK_SPEED_10G)
2616 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2617 if (link_speed & ETH_LINK_SPEED_20G)
2618 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2619 if (link_speed & ETH_LINK_SPEED_25G)
2620 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2621 if (link_speed & ETH_LINK_SPEED_40G)
2622 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2623 if (link_speed & ETH_LINK_SPEED_50G)
2624 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2625 if (link_speed & ETH_LINK_SPEED_100G)
2626 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2630 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2632 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2634 switch (hw_link_speed) {
2635 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2636 eth_link_speed = ETH_SPEED_NUM_100M;
2638 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2639 eth_link_speed = ETH_SPEED_NUM_1G;
2641 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2642 eth_link_speed = ETH_SPEED_NUM_2_5G;
2644 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2645 eth_link_speed = ETH_SPEED_NUM_10G;
2647 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2648 eth_link_speed = ETH_SPEED_NUM_20G;
2650 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2651 eth_link_speed = ETH_SPEED_NUM_25G;
2653 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2654 eth_link_speed = ETH_SPEED_NUM_40G;
2656 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2657 eth_link_speed = ETH_SPEED_NUM_50G;
2659 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2660 eth_link_speed = ETH_SPEED_NUM_100G;
2662 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2664 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2668 return eth_link_speed;
2671 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2673 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2675 switch (hw_link_duplex) {
2676 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2677 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2679 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2681 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2682 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2685 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2689 return eth_link_duplex;
2692 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2695 struct bnxt_link_info *link_info = &bp->link_info;
2697 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2700 "Get link config failed with rc %d\n", rc);
2703 if (link_info->link_speed)
2705 bnxt_parse_hw_link_speed(link_info->link_speed);
2707 link->link_speed = ETH_SPEED_NUM_NONE;
2708 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2709 link->link_status = link_info->link_up;
2710 link->link_autoneg = link_info->auto_mode ==
2711 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2712 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2717 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2720 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2721 struct bnxt_link_info link_req;
2722 uint16_t speed, autoneg;
2724 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2727 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2728 bp->eth_dev->data->port_id);
2732 memset(&link_req, 0, sizeof(link_req));
2733 link_req.link_up = link_up;
2737 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2738 if (BNXT_CHIP_THOR(bp) &&
2739 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2740 /* 40G is not supported as part of media auto detect.
2741 * The speed should be forced and autoneg disabled
2742 * to configure 40G speed.
2744 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2748 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2749 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2750 /* Autoneg can be done only when the FW allows.
2751 * When user configures fixed speed of 40G and later changes to
2752 * any other speed, auto_link_speed/force_link_speed is still set
2753 * to 40G until link comes up at new speed.
2756 !(!BNXT_CHIP_THOR(bp) &&
2757 (bp->link_info.auto_link_speed ||
2758 bp->link_info.force_link_speed))) {
2759 link_req.phy_flags |=
2760 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2761 link_req.auto_link_speed_mask =
2762 bnxt_parse_eth_link_speed_mask(bp,
2763 dev_conf->link_speeds);
2765 if (bp->link_info.phy_type ==
2766 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2767 bp->link_info.phy_type ==
2768 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2769 bp->link_info.media_type ==
2770 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2771 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2775 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2776 /* If user wants a particular speed try that first. */
2778 link_req.link_speed = speed;
2779 else if (bp->link_info.force_link_speed)
2780 link_req.link_speed = bp->link_info.force_link_speed;
2782 link_req.link_speed = bp->link_info.auto_link_speed;
2784 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2785 link_req.auto_pause = bp->link_info.auto_pause;
2786 link_req.force_pause = bp->link_info.force_pause;
2789 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2792 "Set link config failed with rc %d\n", rc);
2800 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2802 struct hwrm_func_qcfg_input req = {0};
2803 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2807 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2808 req.fid = rte_cpu_to_le_16(0xffff);
2810 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2812 HWRM_CHECK_RESULT();
2814 /* Hard Coded.. 0xfff VLAN ID mask */
2815 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2816 flags = rte_le_to_cpu_16(resp->flags);
2817 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2818 bp->flags |= BNXT_FLAG_MULTI_HOST;
2820 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2821 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2822 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2823 } else if (BNXT_VF(bp) &&
2824 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2825 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2826 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2832 switch (resp->port_partition_type) {
2833 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2834 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2835 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2837 bp->port_partition_type = resp->port_partition_type;
2840 bp->port_partition_type = 0;
2849 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2850 struct hwrm_func_qcaps_output *qcaps)
2852 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2853 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2854 sizeof(qcaps->mac_address));
2855 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2856 qcaps->max_rx_rings = fcfg->num_rx_rings;
2857 qcaps->max_tx_rings = fcfg->num_tx_rings;
2858 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2859 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2861 qcaps->first_vf_id = 0;
2862 qcaps->max_vnics = fcfg->num_vnics;
2863 qcaps->max_decap_records = 0;
2864 qcaps->max_encap_records = 0;
2865 qcaps->max_tx_wm_flows = 0;
2866 qcaps->max_tx_em_flows = 0;
2867 qcaps->max_rx_wm_flows = 0;
2868 qcaps->max_rx_em_flows = 0;
2869 qcaps->max_flow_id = 0;
2870 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2871 qcaps->max_sp_tx_rings = 0;
2872 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2875 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2877 struct hwrm_func_cfg_input req = {0};
2878 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2882 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2883 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2884 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2885 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2886 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2887 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2888 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2889 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2890 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2892 if (BNXT_HAS_RING_GRPS(bp)) {
2893 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2894 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2895 } else if (BNXT_HAS_NQ(bp)) {
2896 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2897 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2900 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2901 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2902 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2903 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2905 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2906 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2907 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2908 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2909 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2910 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2911 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2912 req.fid = rte_cpu_to_le_16(0xffff);
2913 req.enables = rte_cpu_to_le_32(enables);
2915 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2917 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2919 HWRM_CHECK_RESULT();
2925 static void populate_vf_func_cfg_req(struct bnxt *bp,
2926 struct hwrm_func_cfg_input *req,
2929 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2930 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2931 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2932 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2933 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2934 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2935 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2936 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2937 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2938 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2940 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2941 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2943 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2944 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2946 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2948 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2949 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2951 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2952 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2953 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2954 /* TODO: For now, do not support VMDq/RFS on VFs. */
2955 req->num_vnics = rte_cpu_to_le_16(1);
2956 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2960 static void add_random_mac_if_needed(struct bnxt *bp,
2961 struct hwrm_func_cfg_input *cfg_req,
2964 struct rte_ether_addr mac;
2966 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2969 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2971 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2972 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2973 bp->pf.vf_info[vf].random_mac = true;
2975 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2976 RTE_ETHER_ADDR_LEN);
2980 static void reserve_resources_from_vf(struct bnxt *bp,
2981 struct hwrm_func_cfg_input *cfg_req,
2984 struct hwrm_func_qcaps_input req = {0};
2985 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2988 /* Get the actual allocated values now */
2989 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2990 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2991 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2994 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2995 copy_func_cfg_to_qcaps(cfg_req, resp);
2996 } else if (resp->error_code) {
2997 rc = rte_le_to_cpu_16(resp->error_code);
2998 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2999 copy_func_cfg_to_qcaps(cfg_req, resp);
3002 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3003 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3004 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3005 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3006 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3007 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3009 * TODO: While not supporting VMDq with VFs, max_vnics is always
3010 * forced to 1 in this case
3012 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3013 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3018 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3020 struct hwrm_func_qcfg_input req = {0};
3021 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3024 /* Check for zero MAC address */
3025 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3026 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3027 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3028 HWRM_CHECK_RESULT();
3029 rc = rte_le_to_cpu_16(resp->vlan);
3036 static int update_pf_resource_max(struct bnxt *bp)
3038 struct hwrm_func_qcfg_input req = {0};
3039 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3042 /* And copy the allocated numbers into the pf struct */
3043 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3044 req.fid = rte_cpu_to_le_16(0xffff);
3045 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3046 HWRM_CHECK_RESULT();
3048 /* Only TX ring value reflects actual allocation? TODO */
3049 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3050 bp->pf.evb_mode = resp->evb_mode;
3057 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3062 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3066 rc = bnxt_hwrm_func_qcaps(bp);
3070 bp->pf.func_cfg_flags &=
3071 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3072 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3073 bp->pf.func_cfg_flags |=
3074 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3075 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3076 rc = __bnxt_hwrm_func_qcaps(bp);
3080 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3082 struct hwrm_func_cfg_input req = {0};
3083 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3090 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3094 rc = bnxt_hwrm_func_qcaps(bp);
3099 bp->pf.active_vfs = num_vfs;
3102 * First, configure the PF to only use one TX ring. This ensures that
3103 * there are enough rings for all VFs.
3105 * If we don't do this, when we call func_alloc() later, we will lock
3106 * extra rings to the PF that won't be available during func_cfg() of
3109 * This has been fixed with firmware versions above 20.6.54
3111 bp->pf.func_cfg_flags &=
3112 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3113 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3114 bp->pf.func_cfg_flags |=
3115 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3116 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3121 * Now, create and register a buffer to hold forwarded VF requests
3123 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3124 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3125 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3126 if (bp->pf.vf_req_buf == NULL) {
3130 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3131 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3132 for (i = 0; i < num_vfs; i++)
3133 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3134 (i * HWRM_MAX_REQ_LEN);
3136 rc = bnxt_hwrm_func_buf_rgtr(bp);
3140 populate_vf_func_cfg_req(bp, &req, num_vfs);
3142 bp->pf.active_vfs = 0;
3143 for (i = 0; i < num_vfs; i++) {
3144 add_random_mac_if_needed(bp, &req, i);
3146 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3147 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3148 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3149 rc = bnxt_hwrm_send_message(bp,
3154 /* Clear enable flag for next pass */
3155 req.enables &= ~rte_cpu_to_le_32(
3156 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3158 if (rc || resp->error_code) {
3160 "Failed to initizlie VF %d\n", i);
3162 "Not all VFs available. (%d, %d)\n",
3163 rc, resp->error_code);
3170 reserve_resources_from_vf(bp, &req, i);
3171 bp->pf.active_vfs++;
3172 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3176 * Now configure the PF to use "the rest" of the resources
3177 * We're using STD_TX_RING_MODE here though which will limit the TX
3178 * rings. This will allow QoS to function properly. Not setting this
3179 * will cause PF rings to break bandwidth settings.
3181 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3185 rc = update_pf_resource_max(bp);
3192 bnxt_hwrm_func_buf_unrgtr(bp);
3196 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3198 struct hwrm_func_cfg_input req = {0};
3199 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3202 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3204 req.fid = rte_cpu_to_le_16(0xffff);
3205 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3206 req.evb_mode = bp->pf.evb_mode;
3208 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3209 HWRM_CHECK_RESULT();
3215 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3216 uint8_t tunnel_type)
3218 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3219 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3222 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3223 req.tunnel_type = tunnel_type;
3224 req.tunnel_dst_port_val = port;
3225 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3226 HWRM_CHECK_RESULT();
3228 switch (tunnel_type) {
3229 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3230 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3231 bp->vxlan_port = port;
3233 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3234 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3235 bp->geneve_port = port;
3246 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3247 uint8_t tunnel_type)
3249 struct hwrm_tunnel_dst_port_free_input req = {0};
3250 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3253 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3255 req.tunnel_type = tunnel_type;
3256 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3257 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3259 HWRM_CHECK_RESULT();
3265 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3268 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3269 struct hwrm_func_cfg_input req = {0};
3272 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3274 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3275 req.flags = rte_cpu_to_le_32(flags);
3276 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3278 HWRM_CHECK_RESULT();
3284 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3286 uint32_t *flag = flagp;
3288 vnic->flags = *flag;
3291 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3293 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3296 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3299 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3300 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3302 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3304 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3305 req.req_buf_page_size = rte_cpu_to_le_16(
3306 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3307 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3308 req.req_buf_page_addr0 =
3309 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3310 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3312 "unable to map buffer address to physical memory\n");
3316 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3318 HWRM_CHECK_RESULT();
3324 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3327 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3328 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3330 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3333 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3337 HWRM_CHECK_RESULT();
3343 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3345 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3346 struct hwrm_func_cfg_input req = {0};
3349 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3351 req.fid = rte_cpu_to_le_16(0xffff);
3352 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3353 req.enables = rte_cpu_to_le_32(
3354 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3355 req.async_event_cr = rte_cpu_to_le_16(
3356 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3359 HWRM_CHECK_RESULT();
3365 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3367 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3368 struct hwrm_func_vf_cfg_input req = {0};
3371 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3373 req.enables = rte_cpu_to_le_32(
3374 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3375 req.async_event_cr = rte_cpu_to_le_16(
3376 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3377 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3379 HWRM_CHECK_RESULT();
3385 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3387 struct hwrm_func_cfg_input req = {0};
3388 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3389 uint16_t dflt_vlan, fid;
3390 uint32_t func_cfg_flags;
3393 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3396 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3397 fid = bp->pf.vf_info[vf].fid;
3398 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3400 fid = rte_cpu_to_le_16(0xffff);
3401 func_cfg_flags = bp->pf.func_cfg_flags;
3402 dflt_vlan = bp->vlan;
3405 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3406 req.fid = rte_cpu_to_le_16(fid);
3407 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3408 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3410 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3412 HWRM_CHECK_RESULT();
3418 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3419 uint16_t max_bw, uint16_t enables)
3421 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3422 struct hwrm_func_cfg_input req = {0};
3425 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3427 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3428 req.enables |= rte_cpu_to_le_32(enables);
3429 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3430 req.max_bw = rte_cpu_to_le_32(max_bw);
3431 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3433 HWRM_CHECK_RESULT();
3439 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3441 struct hwrm_func_cfg_input req = {0};
3442 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3445 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3447 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3448 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3449 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3450 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3452 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3454 HWRM_CHECK_RESULT();
3460 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3465 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3467 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3472 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3473 void *encaped, size_t ec_size)
3476 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3477 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3479 if (ec_size > sizeof(req.encap_request))
3482 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3484 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3485 memcpy(req.encap_request, encaped, ec_size);
3487 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3489 HWRM_CHECK_RESULT();
3495 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3496 struct rte_ether_addr *mac)
3498 struct hwrm_func_qcfg_input req = {0};
3499 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3502 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3504 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3507 HWRM_CHECK_RESULT();
3509 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3516 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3517 void *encaped, size_t ec_size)
3520 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3521 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3523 if (ec_size > sizeof(req.encap_request))
3526 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3528 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3529 memcpy(req.encap_request, encaped, ec_size);
3531 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3533 HWRM_CHECK_RESULT();
3539 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3540 struct rte_eth_stats *stats, uint8_t rx)
3543 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3544 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3546 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3548 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3550 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3552 HWRM_CHECK_RESULT();
3555 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3556 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3557 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3558 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3559 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3560 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3561 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3562 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3564 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3565 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3566 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3567 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3568 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3569 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3578 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3580 struct hwrm_port_qstats_input req = {0};
3581 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3582 struct bnxt_pf_info *pf = &bp->pf;
3585 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3587 req.port_id = rte_cpu_to_le_16(pf->port_id);
3588 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3589 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3590 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3592 HWRM_CHECK_RESULT();
3598 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3600 struct hwrm_port_clr_stats_input req = {0};
3601 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3602 struct bnxt_pf_info *pf = &bp->pf;
3605 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3606 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3607 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3610 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3612 req.port_id = rte_cpu_to_le_16(pf->port_id);
3613 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3615 HWRM_CHECK_RESULT();
3621 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3623 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3624 struct hwrm_port_led_qcaps_input req = {0};
3630 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3631 req.port_id = bp->pf.port_id;
3632 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3634 HWRM_CHECK_RESULT();
3636 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3639 bp->num_leds = resp->num_leds;
3640 memcpy(bp->leds, &resp->led0_id,
3641 sizeof(bp->leds[0]) * bp->num_leds);
3642 for (i = 0; i < bp->num_leds; i++) {
3643 struct bnxt_led_info *led = &bp->leds[i];
3645 uint16_t caps = led->led_state_caps;
3647 if (!led->led_group_id ||
3648 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3660 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3662 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3663 struct hwrm_port_led_cfg_input req = {0};
3664 struct bnxt_led_cfg *led_cfg;
3665 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3666 uint16_t duration = 0;
3669 if (!bp->num_leds || BNXT_VF(bp))
3672 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3675 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3676 duration = rte_cpu_to_le_16(500);
3678 req.port_id = bp->pf.port_id;
3679 req.num_leds = bp->num_leds;
3680 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3681 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3682 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3683 led_cfg->led_id = bp->leds[i].led_id;
3684 led_cfg->led_state = led_state;
3685 led_cfg->led_blink_on = duration;
3686 led_cfg->led_blink_off = duration;
3687 led_cfg->led_group_id = bp->leds[i].led_group_id;
3690 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3692 HWRM_CHECK_RESULT();
3698 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3702 struct hwrm_nvm_get_dir_info_input req = {0};
3703 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3705 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3707 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3709 HWRM_CHECK_RESULT();
3711 *entries = rte_le_to_cpu_32(resp->entries);
3712 *length = rte_le_to_cpu_32(resp->entry_length);
3718 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3721 uint32_t dir_entries;
3722 uint32_t entry_length;
3725 rte_iova_t dma_handle;
3726 struct hwrm_nvm_get_dir_entries_input req = {0};
3727 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3729 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3733 *data++ = dir_entries;
3734 *data++ = entry_length;
3736 memset(data, 0xff, len);
3738 buflen = dir_entries * entry_length;
3739 buf = rte_malloc("nvm_dir", buflen, 0);
3740 rte_mem_lock_page(buf);
3743 dma_handle = rte_mem_virt2iova(buf);
3744 if (dma_handle == RTE_BAD_IOVA) {
3746 "unable to map response address to physical memory\n");
3749 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3750 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3751 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3754 memcpy(data, buf, len > buflen ? buflen : len);
3757 HWRM_CHECK_RESULT();
3763 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3764 uint32_t offset, uint32_t length,
3769 rte_iova_t dma_handle;
3770 struct hwrm_nvm_read_input req = {0};
3771 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3773 buf = rte_malloc("nvm_item", length, 0);
3774 rte_mem_lock_page(buf);
3778 dma_handle = rte_mem_virt2iova(buf);
3779 if (dma_handle == RTE_BAD_IOVA) {
3781 "unable to map response address to physical memory\n");
3784 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3785 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3786 req.dir_idx = rte_cpu_to_le_16(index);
3787 req.offset = rte_cpu_to_le_32(offset);
3788 req.len = rte_cpu_to_le_32(length);
3789 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3791 memcpy(data, buf, length);
3794 HWRM_CHECK_RESULT();
3800 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3803 struct hwrm_nvm_erase_dir_entry_input req = {0};
3804 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3806 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3807 req.dir_idx = rte_cpu_to_le_16(index);
3808 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3809 HWRM_CHECK_RESULT();
3816 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3817 uint16_t dir_ordinal, uint16_t dir_ext,
3818 uint16_t dir_attr, const uint8_t *data,
3822 struct hwrm_nvm_write_input req = {0};
3823 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3824 rte_iova_t dma_handle;
3827 buf = rte_malloc("nvm_write", data_len, 0);
3828 rte_mem_lock_page(buf);
3832 dma_handle = rte_mem_virt2iova(buf);
3833 if (dma_handle == RTE_BAD_IOVA) {
3835 "unable to map response address to physical memory\n");
3838 memcpy(buf, data, data_len);
3840 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3842 req.dir_type = rte_cpu_to_le_16(dir_type);
3843 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3844 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3845 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3846 req.dir_data_length = rte_cpu_to_le_32(data_len);
3847 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3849 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3852 HWRM_CHECK_RESULT();
3859 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3861 uint32_t *count = cbdata;
3863 *count = *count + 1;
3866 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3867 struct bnxt_vnic_info *vnic __rte_unused)
3872 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3876 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3877 &count, bnxt_vnic_count_hwrm_stub);
3882 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3885 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3886 struct hwrm_func_vf_vnic_ids_query_output *resp =
3887 bp->hwrm_cmd_resp_addr;
3890 /* First query all VNIC ids */
3891 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3893 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3894 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3895 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3897 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3900 "unable to map VNIC ID table address to physical memory\n");
3903 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3904 HWRM_CHECK_RESULT();
3905 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3913 * This function queries the VNIC IDs for a specified VF. It then calls
3914 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3915 * Then it calls the hwrm_cb function to program this new vnic configuration.
3917 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3918 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3919 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3921 struct bnxt_vnic_info vnic;
3923 int i, num_vnic_ids;
3928 /* First query all VNIC ids */
3929 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3930 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3931 RTE_CACHE_LINE_SIZE);
3932 if (vnic_ids == NULL)
3935 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3936 rte_mem_lock_page(((char *)vnic_ids) + sz);
3938 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3940 if (num_vnic_ids < 0)
3941 return num_vnic_ids;
3943 /* Retrieve VNIC, update bd_stall then update */
3945 for (i = 0; i < num_vnic_ids; i++) {
3946 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3947 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3948 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3951 if (vnic.mru <= 4) /* Indicates unallocated */
3954 vnic_cb(&vnic, cbdata);
3956 rc = hwrm_cb(bp, &vnic);
3966 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3969 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3970 struct hwrm_func_cfg_input req = {0};
3973 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3975 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3976 req.enables |= rte_cpu_to_le_32(
3977 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3978 req.vlan_antispoof_mode = on ?
3979 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3980 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3981 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3983 HWRM_CHECK_RESULT();
3989 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3991 struct bnxt_vnic_info vnic;
3994 int num_vnic_ids, i;
3998 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3999 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4000 RTE_CACHE_LINE_SIZE);
4001 if (vnic_ids == NULL)
4004 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4005 rte_mem_lock_page(((char *)vnic_ids) + sz);
4007 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4013 * Loop through to find the default VNIC ID.
4014 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4015 * by sending the hwrm_func_qcfg command to the firmware.
4017 for (i = 0; i < num_vnic_ids; i++) {
4018 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4019 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4020 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4021 bp->pf.first_vf_id + vf);
4024 if (vnic.func_default) {
4026 return vnic.fw_vnic_id;
4029 /* Could not find a default VNIC. */
4030 PMD_DRV_LOG(ERR, "No default VNIC\n");
4036 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4038 struct bnxt_filter_info *filter)
4041 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4042 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4043 uint32_t enables = 0;
4045 if (filter->fw_em_filter_id != UINT64_MAX)
4046 bnxt_hwrm_clear_em_filter(bp, filter);
4048 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4050 req.flags = rte_cpu_to_le_32(filter->flags);
4052 enables = filter->enables |
4053 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4054 req.dst_id = rte_cpu_to_le_16(dst_id);
4056 if (filter->ip_addr_type) {
4057 req.ip_addr_type = filter->ip_addr_type;
4058 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4061 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4062 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4064 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4065 memcpy(req.src_macaddr, filter->src_macaddr,
4066 RTE_ETHER_ADDR_LEN);
4068 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4069 memcpy(req.dst_macaddr, filter->dst_macaddr,
4070 RTE_ETHER_ADDR_LEN);
4072 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4073 req.ovlan_vid = filter->l2_ovlan;
4075 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4076 req.ivlan_vid = filter->l2_ivlan;
4078 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4079 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4081 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4082 req.ip_protocol = filter->ip_protocol;
4084 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4085 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4087 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4088 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4090 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4091 req.src_port = rte_cpu_to_be_16(filter->src_port);
4093 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4094 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4096 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4097 req.mirror_vnic_id = filter->mirror_vnic_id;
4099 req.enables = rte_cpu_to_le_32(enables);
4101 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4103 HWRM_CHECK_RESULT();
4105 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4111 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4114 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4115 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4117 if (filter->fw_em_filter_id == UINT64_MAX)
4120 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4121 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4123 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4125 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4127 HWRM_CHECK_RESULT();
4130 filter->fw_em_filter_id = UINT64_MAX;
4131 filter->fw_l2_filter_id = UINT64_MAX;
4136 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4138 struct bnxt_filter_info *filter)
4141 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4142 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4143 bp->hwrm_cmd_resp_addr;
4144 uint32_t enables = 0;
4146 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4147 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4149 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4151 req.flags = rte_cpu_to_le_32(filter->flags);
4153 enables = filter->enables |
4154 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4155 req.dst_id = rte_cpu_to_le_16(dst_id);
4158 if (filter->ip_addr_type) {
4159 req.ip_addr_type = filter->ip_addr_type;
4161 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4164 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4165 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4167 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4168 memcpy(req.src_macaddr, filter->src_macaddr,
4169 RTE_ETHER_ADDR_LEN);
4171 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4172 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4173 //RTE_ETHER_ADDR_LEN);
4175 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4176 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4178 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4179 req.ip_protocol = filter->ip_protocol;
4181 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4182 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4184 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4185 req.src_ipaddr_mask[0] =
4186 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4188 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4189 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4191 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4192 req.dst_ipaddr_mask[0] =
4193 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4195 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4196 req.src_port = rte_cpu_to_le_16(filter->src_port);
4198 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4199 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4201 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4202 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4204 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4205 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4207 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4208 req.mirror_vnic_id = filter->mirror_vnic_id;
4210 req.enables = rte_cpu_to_le_32(enables);
4212 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4214 HWRM_CHECK_RESULT();
4216 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4222 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4223 struct bnxt_filter_info *filter)
4226 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4227 struct hwrm_cfa_ntuple_filter_free_output *resp =
4228 bp->hwrm_cmd_resp_addr;
4230 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4233 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4235 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4237 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4239 HWRM_CHECK_RESULT();
4242 filter->fw_ntuple_filter_id = UINT64_MAX;
4248 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4250 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4251 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4252 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4253 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4254 uint16_t *ring_tbl = vnic->rss_table;
4255 int nr_ctxs = vnic->num_lb_ctxts;
4256 int max_rings = bp->rx_nr_rings;
4260 for (i = 0, k = 0; i < nr_ctxs; i++) {
4261 struct bnxt_rx_ring_info *rxr;
4262 struct bnxt_cp_ring_info *cpr;
4264 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4266 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4267 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4268 req.hash_mode_flags = vnic->hash_mode;
4270 req.ring_grp_tbl_addr =
4271 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4272 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4273 2 * sizeof(*ring_tbl));
4274 req.hash_key_tbl_addr =
4275 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4277 req.ring_table_pair_index = i;
4278 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4280 for (j = 0; j < 64; j++) {
4283 /* Find next active ring. */
4284 for (cnt = 0; cnt < max_rings; cnt++) {
4285 if (rx_queue_state[k] !=
4286 RTE_ETH_QUEUE_STATE_STOPPED)
4288 if (++k == max_rings)
4292 /* Return if no rings are active. */
4293 if (cnt == max_rings)
4296 /* Add rx/cp ring pair to RSS table. */
4297 rxr = rxqs[k]->rx_ring;
4298 cpr = rxqs[k]->cp_ring;
4300 ring_id = rxr->rx_ring_struct->fw_ring_id;
4301 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4302 ring_id = cpr->cp_ring_struct->fw_ring_id;
4303 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4305 if (++k == max_rings)
4308 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4311 HWRM_CHECK_RESULT();
4318 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4320 unsigned int rss_idx, fw_idx, i;
4322 if (!(vnic->rss_table && vnic->hash_type))
4325 if (BNXT_CHIP_THOR(bp))
4326 return bnxt_vnic_rss_configure_thor(bp, vnic);
4328 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4331 if (vnic->rss_table && vnic->hash_type) {
4333 * Fill the RSS hash & redirection table with
4334 * ring group ids for all VNICs
4336 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4337 rss_idx++, fw_idx++) {
4338 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4339 fw_idx %= bp->rx_cp_nr_rings;
4340 if (vnic->fw_grp_ids[fw_idx] !=
4345 if (i == bp->rx_cp_nr_rings)
4347 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4349 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4355 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4356 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4360 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4362 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4363 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4365 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4366 req->num_cmpl_dma_aggr_during_int =
4367 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4369 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4371 /* min timer set to 1/2 of interrupt timer */
4372 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4374 /* buf timer set to 1/4 of interrupt timer */
4375 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4377 req->cmpl_aggr_dma_tmr_during_int =
4378 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4380 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4381 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4382 req->flags = rte_cpu_to_le_16(flags);
4385 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4386 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4388 struct hwrm_ring_aggint_qcaps_input req = {0};
4389 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4394 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4395 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4396 HWRM_CHECK_RESULT();
4398 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4399 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4401 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4402 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4403 agg_req->flags = rte_cpu_to_le_16(flags);
4405 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4406 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4407 agg_req->enables = rte_cpu_to_le_32(enables);
4413 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4414 struct bnxt_coal *coal, uint16_t ring_id)
4416 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4417 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4418 bp->hwrm_cmd_resp_addr;
4421 /* Set ring coalesce parameters only for 100G NICs */
4422 if (BNXT_CHIP_THOR(bp)) {
4423 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4425 } else if (bnxt_stratus_device(bp)) {
4426 bnxt_hwrm_set_coal_params(coal, &req);
4431 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4432 req.ring_id = rte_cpu_to_le_16(ring_id);
4433 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4434 HWRM_CHECK_RESULT();
4439 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4440 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4442 struct hwrm_func_backing_store_qcaps_input req = {0};
4443 struct hwrm_func_backing_store_qcaps_output *resp =
4444 bp->hwrm_cmd_resp_addr;
4445 struct bnxt_ctx_pg_info *ctx_pg;
4446 struct bnxt_ctx_mem_info *ctx;
4447 int total_alloc_len;
4450 if (!BNXT_CHIP_THOR(bp) ||
4451 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4456 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4457 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4458 HWRM_CHECK_RESULT_SILENT();
4460 total_alloc_len = sizeof(*ctx);
4461 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4462 RTE_CACHE_LINE_SIZE);
4468 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4469 sizeof(*ctx_pg) * BNXT_MAX_Q,
4470 RTE_CACHE_LINE_SIZE);
4475 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4476 ctx->tqm_mem[i] = ctx_pg;
4479 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4480 ctx->qp_min_qp1_entries =
4481 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4482 ctx->qp_max_l2_entries =
4483 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4484 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4485 ctx->srq_max_l2_entries =
4486 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4487 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4488 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4489 ctx->cq_max_l2_entries =
4490 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4491 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4492 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4493 ctx->vnic_max_vnic_entries =
4494 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4495 ctx->vnic_max_ring_table_entries =
4496 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4497 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4498 ctx->stat_max_entries =
4499 rte_le_to_cpu_32(resp->stat_max_entries);
4500 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4501 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4502 ctx->tqm_min_entries_per_ring =
4503 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4504 ctx->tqm_max_entries_per_ring =
4505 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4506 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4507 if (!ctx->tqm_entries_multiple)
4508 ctx->tqm_entries_multiple = 1;
4509 ctx->mrav_max_entries =
4510 rte_le_to_cpu_32(resp->mrav_max_entries);
4511 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4512 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4513 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4519 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4521 struct hwrm_func_backing_store_cfg_input req = {0};
4522 struct hwrm_func_backing_store_cfg_output *resp =
4523 bp->hwrm_cmd_resp_addr;
4524 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4525 struct bnxt_ctx_pg_info *ctx_pg;
4526 uint32_t *num_entries;
4535 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4536 req.enables = rte_cpu_to_le_32(enables);
4538 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4539 ctx_pg = &ctx->qp_mem;
4540 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4541 req.qp_num_qp1_entries =
4542 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4543 req.qp_num_l2_entries =
4544 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4545 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4546 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4547 &req.qpc_pg_size_qpc_lvl,
4551 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4552 ctx_pg = &ctx->srq_mem;
4553 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4554 req.srq_num_l2_entries =
4555 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4556 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4557 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4558 &req.srq_pg_size_srq_lvl,
4562 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4563 ctx_pg = &ctx->cq_mem;
4564 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4565 req.cq_num_l2_entries =
4566 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4567 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4568 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4569 &req.cq_pg_size_cq_lvl,
4573 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4574 ctx_pg = &ctx->vnic_mem;
4575 req.vnic_num_vnic_entries =
4576 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4577 req.vnic_num_ring_table_entries =
4578 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4579 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4580 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4581 &req.vnic_pg_size_vnic_lvl,
4582 &req.vnic_page_dir);
4585 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4586 ctx_pg = &ctx->stat_mem;
4587 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4588 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4589 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4590 &req.stat_pg_size_stat_lvl,
4591 &req.stat_page_dir);
4594 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4595 num_entries = &req.tqm_sp_num_entries;
4596 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4597 pg_dir = &req.tqm_sp_page_dir;
4598 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4599 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4600 if (!(enables & ena))
4603 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4605 ctx_pg = ctx->tqm_mem[i];
4606 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4607 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4610 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4611 HWRM_CHECK_RESULT();
4617 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4619 struct hwrm_port_qstats_ext_input req = {0};
4620 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4621 struct bnxt_pf_info *pf = &bp->pf;
4624 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4625 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4628 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4630 req.port_id = rte_cpu_to_le_16(pf->port_id);
4631 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4632 req.tx_stat_host_addr =
4633 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4635 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4637 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4638 req.rx_stat_host_addr =
4639 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4641 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4643 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4646 bp->fw_rx_port_stats_ext_size = 0;
4647 bp->fw_tx_port_stats_ext_size = 0;
4649 bp->fw_rx_port_stats_ext_size =
4650 rte_le_to_cpu_16(resp->rx_stat_size);
4651 bp->fw_tx_port_stats_ext_size =
4652 rte_le_to_cpu_16(resp->tx_stat_size);
4655 HWRM_CHECK_RESULT();
4662 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4664 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4665 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4666 bp->hwrm_cmd_resp_addr;
4669 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4670 req.tunnel_type = type;
4671 req.dest_fid = bp->fw_fid;
4672 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4673 HWRM_CHECK_RESULT();
4681 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4683 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4684 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4685 bp->hwrm_cmd_resp_addr;
4688 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4689 req.tunnel_type = type;
4690 req.dest_fid = bp->fw_fid;
4691 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4692 HWRM_CHECK_RESULT();
4699 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4701 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4702 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4703 bp->hwrm_cmd_resp_addr;
4706 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4707 req.src_fid = bp->fw_fid;
4708 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4709 HWRM_CHECK_RESULT();
4712 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4719 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4722 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4723 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4724 bp->hwrm_cmd_resp_addr;
4727 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4728 req.src_fid = bp->fw_fid;
4729 req.tunnel_type = tun_type;
4730 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4731 HWRM_CHECK_RESULT();
4734 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4736 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4743 int bnxt_hwrm_set_mac(struct bnxt *bp)
4745 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4746 struct hwrm_func_vf_cfg_input req = {0};
4752 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4755 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4756 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4758 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4760 HWRM_CHECK_RESULT();
4762 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4768 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4770 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4771 struct hwrm_func_drv_if_change_input req = {0};
4775 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4778 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4779 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4780 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4782 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4785 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4789 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4791 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4793 HWRM_CHECK_RESULT();
4794 flags = rte_le_to_cpu_32(resp->flags);
4797 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4798 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4799 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4805 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4807 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4808 struct bnxt_error_recovery_info *info = bp->recovery_info;
4809 struct hwrm_error_recovery_qcfg_input req = {0};
4814 /* Older FW does not have error recovery support */
4815 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4819 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4821 bp->recovery_info = info;
4825 memset(info, 0, sizeof(*info));
4828 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4830 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4832 HWRM_CHECK_RESULT();
4834 flags = rte_le_to_cpu_32(resp->flags);
4835 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4836 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4837 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4838 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4840 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4841 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4846 /* FW returned values are in units of 100msec */
4847 info->driver_polling_freq =
4848 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4849 info->master_func_wait_period =
4850 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4851 info->normal_func_wait_period =
4852 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4853 info->master_func_wait_period_after_reset =
4854 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4855 info->max_bailout_time_after_reset =
4856 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4857 info->status_regs[BNXT_FW_STATUS_REG] =
4858 rte_le_to_cpu_32(resp->fw_health_status_reg);
4859 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4860 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4861 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4862 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4863 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4864 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4865 info->reg_array_cnt =
4866 rte_le_to_cpu_32(resp->reg_array_cnt);
4868 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4873 for (i = 0; i < info->reg_array_cnt; i++) {
4874 info->reset_reg[i] =
4875 rte_le_to_cpu_32(resp->reset_reg[i]);
4876 info->reset_reg_val[i] =
4877 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4878 info->delay_after_reset[i] =
4879 resp->delay_after_reset[i];
4884 /* Map the FW status registers */
4886 rc = bnxt_map_fw_health_status_regs(bp);
4889 rte_free(bp->recovery_info);
4890 bp->recovery_info = NULL;
4895 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4897 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4898 struct hwrm_fw_reset_input req = {0};
4904 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4906 req.embedded_proc_type =
4907 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4908 req.selfrst_status =
4909 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4910 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4912 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4915 HWRM_CHECK_RESULT();
4921 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4923 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4924 struct hwrm_port_ts_query_input req = {0};
4925 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4932 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4935 case BNXT_PTP_FLAGS_PATH_TX:
4936 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4938 case BNXT_PTP_FLAGS_PATH_RX:
4939 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4941 case BNXT_PTP_FLAGS_CURRENT_TIME:
4942 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4946 req.flags = rte_cpu_to_le_32(flags);
4947 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4949 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4951 HWRM_CHECK_RESULT();
4954 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
4956 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
4963 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
4965 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
4966 bp->hwrm_cmd_resp_addr;
4967 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
4971 if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
4974 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
4976 "Not a PF or trusted VF. Command not supported\n");
4980 HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
4981 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4983 HWRM_CHECK_RESULT();
4984 flags = rte_le_to_cpu_32(resp->flags);
4987 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
4988 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
4989 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");