1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(void *) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages > 1) {
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
103 /* For VER_GET command, set timeout as 50ms */
104 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
105 timeout = HWRM_CMD_TIMEOUT;
107 timeout = bp->hwrm_cmd_timeout;
109 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
110 msg_len > bp->max_req_len) {
111 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
113 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
114 memcpy(short_cmd_req, req, msg_len);
116 short_input.req_type = rte_cpu_to_le_16(req->req_type);
117 short_input.signature = rte_cpu_to_le_16(
118 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
119 short_input.size = rte_cpu_to_le_16(msg_len);
120 short_input.req_addr =
121 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
123 data = (uint32_t *)&short_input;
124 msg_len = sizeof(short_input);
126 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
129 /* Write request msg to hwrm channel */
130 for (i = 0; i < msg_len; i += 4) {
131 bar = (uint8_t *)bp->bar0 + bar_offset + i;
132 rte_write32(*data, bar);
136 /* Zero the rest of the request space */
137 for (; i < max_req_len; i += 4) {
138 bar = (uint8_t *)bp->bar0 + bar_offset + i;
142 /* Ring channel doorbell */
143 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
146 * Make sure the channel doorbell ring command complete before
147 * reading the response to avoid getting stale or invalid
152 /* Poll for the valid bit */
153 for (i = 0; i < timeout; i++) {
154 /* Sanity check on the resp->resp_len */
156 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
157 /* Last byte of resp contains the valid key */
158 valid = (uint8_t *)resp + resp->resp_len - 1;
159 if (*valid == HWRM_RESP_VALID_KEY)
166 /* Suppress VER_GET timeout messages during reset recovery */
167 if (bp->flags & BNXT_FLAG_FW_RESET &&
168 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
171 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
179 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
180 * spinlock, and does initial processing.
182 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
183 * releases the spinlock only if it returns. If the regular int return codes
184 * are not used by the function, HWRM_CHECK_RESULT() should not be used
185 * directly, rather it should be copied and modified to suit the function.
187 * HWRM_UNLOCK() must be called after all response processing is completed.
189 #define HWRM_PREP(req, type, kong) do { \
190 rte_spinlock_lock(&bp->hwrm_lock); \
191 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
192 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
193 req.cmpl_ring = rte_cpu_to_le_16(-1); \
194 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
195 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
196 req.target_id = rte_cpu_to_le_16(0xffff); \
197 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
200 #define HWRM_CHECK_RESULT_SILENT() do {\
202 rte_spinlock_unlock(&bp->hwrm_lock); \
205 if (resp->error_code) { \
206 rc = rte_le_to_cpu_16(resp->error_code); \
207 rte_spinlock_unlock(&bp->hwrm_lock); \
212 #define HWRM_CHECK_RESULT() do {\
214 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
215 rte_spinlock_unlock(&bp->hwrm_lock); \
216 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
218 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
220 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
222 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
228 if (resp->error_code) { \
229 rc = rte_le_to_cpu_16(resp->error_code); \
230 if (resp->resp_len >= 16) { \
231 struct hwrm_err_output *tmp_hwrm_err_op = \
234 "error %d:%d:%08x:%04x\n", \
235 rc, tmp_hwrm_err_op->cmd_err, \
237 tmp_hwrm_err_op->opaque_0), \
239 tmp_hwrm_err_op->opaque_1)); \
241 PMD_DRV_LOG(ERR, "error %d\n", rc); \
243 rte_spinlock_unlock(&bp->hwrm_lock); \
244 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
246 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
248 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
250 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
258 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
263 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
264 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
270 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
279 struct bnxt_vnic_info *vnic,
281 struct bnxt_vlan_table_entry *vlan_table)
284 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
285 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
288 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
291 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
292 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
294 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
295 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
296 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
297 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
299 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
300 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
302 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
303 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
304 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
305 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
306 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
307 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
310 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
311 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
312 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
313 rte_mem_virt2iova(vlan_table));
314 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
316 req.mask = rte_cpu_to_le_32(mask);
318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
328 struct bnxt_vlan_antispoof_table_entry *vlan_table)
331 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
332 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
333 bp->hwrm_cmd_resp_addr;
336 * Older HWRM versions did not support this command, and the set_rx_mask
337 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
338 * removed from set_rx_mask call, and this command was added.
340 * This command is also present from 1.7.8.11 and higher,
343 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
344 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
345 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
350 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
351 req.fid = rte_cpu_to_le_16(fid);
353 req.vlan_tag_mask_tbl_addr =
354 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
355 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
366 struct bnxt_filter_info *filter)
369 struct bnxt_filter_info *l2_filter = filter;
370 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
371 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
373 if (filter->fw_l2_filter_id == UINT64_MAX)
376 if (filter->matching_l2_fltr_ptr)
377 l2_filter = filter->matching_l2_fltr_ptr;
379 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
380 filter, l2_filter, l2_filter->l2_ref_cnt);
382 if (l2_filter->l2_ref_cnt > 0)
383 l2_filter->l2_ref_cnt--;
385 if (l2_filter->l2_ref_cnt > 0)
388 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
390 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
392 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
397 filter->fw_l2_filter_id = UINT64_MAX;
402 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
404 struct bnxt_filter_info *filter)
407 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
408 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
409 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
410 const struct rte_eth_vmdq_rx_conf *conf =
411 &dev_conf->rx_adv_conf.vmdq_rx_conf;
412 uint32_t enables = 0;
413 uint16_t j = dst_id - 1;
415 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
416 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
417 conf->pool_map[j].pools & (1UL << j)) {
419 "Add vlan %u to vmdq pool %u\n",
420 conf->pool_map[j].vlan_id, j);
422 filter->l2_ivlan = conf->pool_map[j].vlan_id;
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
425 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
428 if (filter->fw_l2_filter_id != UINT64_MAX)
429 bnxt_hwrm_clear_l2_filter(bp, filter);
431 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
433 req.flags = rte_cpu_to_le_32(filter->flags);
435 enables = filter->enables |
436 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
437 req.dst_id = rte_cpu_to_le_16(dst_id);
440 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
441 memcpy(req.l2_addr, filter->l2_addr,
444 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
445 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
448 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
449 req.l2_ovlan = filter->l2_ovlan;
451 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
452 req.l2_ivlan = filter->l2_ivlan;
454 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
455 req.l2_ovlan_mask = filter->l2_ovlan_mask;
457 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
458 req.l2_ivlan_mask = filter->l2_ivlan_mask;
459 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
460 req.src_id = rte_cpu_to_le_32(filter->src_id);
461 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
462 req.src_type = filter->src_type;
463 if (filter->pri_hint) {
464 req.pri_hint = filter->pri_hint;
465 req.l2_filter_id_hint =
466 rte_cpu_to_le_64(filter->l2_filter_id_hint);
469 req.enables = rte_cpu_to_le_32(enables);
471 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
475 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
481 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
483 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
484 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
491 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
494 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
497 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
498 if (ptp->tx_tstamp_en)
499 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
502 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
503 req.flags = rte_cpu_to_le_32(flags);
504 req.enables = rte_cpu_to_le_32
505 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
506 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
508 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
514 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
517 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
518 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
519 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
524 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
526 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
528 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
532 if (!BNXT_CHIP_THOR(bp) &&
533 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
536 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
537 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
539 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
543 if (!BNXT_CHIP_THOR(bp)) {
544 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
545 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
546 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
547 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
548 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
549 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
550 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
551 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
552 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
553 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
554 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
555 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
556 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
557 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
558 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
559 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
560 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
561 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
570 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
573 struct hwrm_func_qcaps_input req = {.req_type = 0 };
574 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
575 uint16_t new_max_vfs;
579 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
581 req.fid = rte_cpu_to_le_16(0xffff);
583 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
587 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
588 flags = rte_le_to_cpu_32(resp->flags);
590 bp->pf.port_id = resp->port_id;
591 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
592 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
593 new_max_vfs = bp->pdev->max_vfs;
594 if (new_max_vfs != bp->pf.max_vfs) {
596 rte_free(bp->pf.vf_info);
597 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
598 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
599 bp->pf.max_vfs = new_max_vfs;
600 for (i = 0; i < new_max_vfs; i++) {
601 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
602 bp->pf.vf_info[i].vlan_table =
603 rte_zmalloc("VF VLAN table",
606 if (bp->pf.vf_info[i].vlan_table == NULL)
608 "Fail to alloc VLAN table for VF %d\n",
612 bp->pf.vf_info[i].vlan_table);
613 bp->pf.vf_info[i].vlan_as_table =
614 rte_zmalloc("VF VLAN AS table",
617 if (bp->pf.vf_info[i].vlan_as_table == NULL)
619 "Alloc VLAN AS table for VF %d fail\n",
623 bp->pf.vf_info[i].vlan_as_table);
624 STAILQ_INIT(&bp->pf.vf_info[i].filter);
629 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
630 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
631 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
632 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
633 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
634 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
635 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
636 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
637 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
638 if (!BNXT_CHIP_THOR(bp))
639 bp->max_l2_ctx += bp->max_rx_em_flows;
640 /* TODO: For now, do not support VMDq/RFS on VFs. */
645 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
649 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
651 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
652 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
653 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
654 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
656 bnxt_hwrm_ptp_qcfg(bp);
660 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
661 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
663 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
664 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
665 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
667 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
670 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
671 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
673 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
680 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
684 rc = __bnxt_hwrm_func_qcaps(bp);
685 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
686 rc = bnxt_alloc_ctx_mem(bp);
690 rc = bnxt_hwrm_func_resc_qcaps(bp);
692 bp->flags |= BNXT_FLAG_NEW_RM;
698 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
699 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
702 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
703 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
705 HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
707 req.target_id = rte_cpu_to_le_16(0xffff);
709 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
713 if (rte_le_to_cpu_32(resp->flags) &
714 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
715 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
716 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
719 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
726 int bnxt_hwrm_func_reset(struct bnxt *bp)
729 struct hwrm_func_reset_input req = {.req_type = 0 };
730 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
732 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
734 req.enables = rte_cpu_to_le_32(0);
736 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
744 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
748 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
749 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
751 if (bp->flags & BNXT_FLAG_REGISTERED)
754 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
755 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
756 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
758 /* PFs and trusted VFs should indicate the support of the
759 * Master capability on non Stingray platform
761 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
762 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
764 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
765 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
766 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
767 req.ver_maj = RTE_VER_YEAR;
768 req.ver_min = RTE_VER_MONTH;
769 req.ver_upd = RTE_VER_MINOR;
772 req.enables |= rte_cpu_to_le_32(
773 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
774 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
775 RTE_MIN(sizeof(req.vf_req_fwd),
776 sizeof(bp->pf.vf_req_fwd)));
779 * PF can sniff HWRM API issued by VF. This can be set up by
780 * linux driver and inherited by the DPDK PF driver. Clear
781 * this HWRM sniffer list in FW because DPDK PF driver does
784 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
787 req.flags = rte_cpu_to_le_32(flags);
789 req.async_event_fwd[0] |=
790 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
791 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
792 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
793 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
794 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
795 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
796 req.async_event_fwd[0] |=
797 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
798 req.async_event_fwd[1] |=
799 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
800 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
802 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
806 flags = rte_le_to_cpu_32(resp->flags);
807 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
808 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
812 bp->flags |= BNXT_FLAG_REGISTERED;
817 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
819 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
822 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
825 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
830 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
831 struct hwrm_func_vf_cfg_input req = {0};
833 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
835 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
836 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
837 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
838 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
839 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
841 if (BNXT_HAS_RING_GRPS(bp)) {
842 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
843 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
846 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
847 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
848 AGG_RING_MULTIPLIER);
849 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
850 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
852 BNXT_NUM_ASYNC_CPR(bp));
853 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
854 if (bp->vf_resv_strategy ==
855 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
856 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
857 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
858 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
859 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
860 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
861 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
865 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
866 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
867 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
868 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
869 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
870 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
872 if (test && BNXT_HAS_RING_GRPS(bp))
873 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
875 req.flags = rte_cpu_to_le_32(flags);
876 req.enables |= rte_cpu_to_le_32(enables);
878 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
881 HWRM_CHECK_RESULT_SILENT();
889 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
892 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
893 struct hwrm_func_resource_qcaps_input req = {0};
895 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
896 req.fid = rte_cpu_to_le_16(0xffff);
898 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
903 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
904 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
905 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
906 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
907 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
908 /* func_resource_qcaps does not return max_rx_em_flows.
909 * So use the value provided by func_qcaps.
911 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
912 if (!BNXT_CHIP_THOR(bp))
913 bp->max_l2_ctx += bp->max_rx_em_flows;
914 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
915 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
917 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
918 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
919 if (bp->vf_resv_strategy >
920 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
921 bp->vf_resv_strategy =
922 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
928 int bnxt_hwrm_ver_get(struct bnxt *bp)
931 struct hwrm_ver_get_input req = {.req_type = 0 };
932 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
934 uint16_t max_resp_len;
935 char type[RTE_MEMZONE_NAMESIZE];
936 uint32_t dev_caps_cfg;
938 bp->max_req_len = HWRM_MAX_REQ_LEN;
939 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
941 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
942 req.hwrm_intf_min = HWRM_VERSION_MINOR;
943 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
945 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
947 if (bp->flags & BNXT_FLAG_FW_RESET)
948 HWRM_CHECK_RESULT_SILENT();
952 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
953 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
954 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
955 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
956 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
957 (resp->hwrm_fw_min_8b << 16) |
958 (resp->hwrm_fw_bld_8b << 8) |
959 resp->hwrm_fw_rsvd_8b;
960 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
961 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
963 fw_version = resp->hwrm_intf_maj_8b << 16;
964 fw_version |= resp->hwrm_intf_min_8b << 8;
965 fw_version |= resp->hwrm_intf_upd_8b;
966 bp->hwrm_spec_code = fw_version;
968 /* def_req_timeout value is in milliseconds */
969 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
970 /* convert timeout to usec */
971 bp->hwrm_cmd_timeout *= 1000;
972 if (!bp->hwrm_cmd_timeout)
973 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
975 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
976 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
981 if (bp->max_req_len > resp->max_req_win_len) {
982 PMD_DRV_LOG(ERR, "Unsupported request length\n");
985 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
986 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
987 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
988 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
990 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
991 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
993 if (bp->max_resp_len != max_resp_len) {
994 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
995 bp->pdev->addr.domain, bp->pdev->addr.bus,
996 bp->pdev->addr.devid, bp->pdev->addr.function);
998 rte_free(bp->hwrm_cmd_resp_addr);
1000 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1001 if (bp->hwrm_cmd_resp_addr == NULL) {
1005 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1006 bp->hwrm_cmd_resp_dma_addr =
1007 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1008 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1010 "Unable to map response buffer to physical memory.\n");
1014 bp->max_resp_len = max_resp_len;
1018 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1020 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1021 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1022 bp->flags |= BNXT_FLAG_SHORT_CMD;
1025 if (((dev_caps_cfg &
1026 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1028 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1029 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1030 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1031 bp->pdev->addr.domain, bp->pdev->addr.bus,
1032 bp->pdev->addr.devid, bp->pdev->addr.function);
1034 rte_free(bp->hwrm_short_cmd_req_addr);
1036 bp->hwrm_short_cmd_req_addr =
1037 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1038 if (bp->hwrm_short_cmd_req_addr == NULL) {
1042 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1043 bp->hwrm_short_cmd_req_dma_addr =
1044 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1045 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1046 rte_free(bp->hwrm_short_cmd_req_addr);
1048 "Unable to map buffer to physical memory.\n");
1054 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1055 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1056 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1059 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1060 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1062 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1063 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1064 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1072 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1075 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1076 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1078 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1081 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1084 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1086 HWRM_CHECK_RESULT();
1092 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1095 struct hwrm_port_phy_cfg_input req = {0};
1096 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1097 uint32_t enables = 0;
1099 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1101 if (conf->link_up) {
1102 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1103 if (bp->link_info.auto_mode && conf->link_speed) {
1104 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1105 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1108 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1109 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1110 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1112 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1113 * any auto mode, even "none".
1115 if (!conf->link_speed) {
1116 /* No speeds specified. Enable AutoNeg - all speeds */
1118 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1120 /* AutoNeg - Advertise speeds specified. */
1121 if (conf->auto_link_speed_mask &&
1122 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1124 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1125 req.auto_link_speed_mask =
1126 conf->auto_link_speed_mask;
1128 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1131 req.auto_duplex = conf->duplex;
1132 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1133 req.auto_pause = conf->auto_pause;
1134 req.force_pause = conf->force_pause;
1135 /* Set force_pause if there is no auto or if there is a force */
1136 if (req.auto_pause && !req.force_pause)
1137 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1139 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1141 req.enables = rte_cpu_to_le_32(enables);
1144 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1145 PMD_DRV_LOG(INFO, "Force Link Down\n");
1148 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1150 HWRM_CHECK_RESULT();
1156 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1157 struct bnxt_link_info *link_info)
1160 struct hwrm_port_phy_qcfg_input req = {0};
1161 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1163 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1165 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1167 HWRM_CHECK_RESULT();
1169 link_info->phy_link_status = resp->link;
1170 link_info->link_up =
1171 (link_info->phy_link_status ==
1172 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1173 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1174 link_info->duplex = resp->duplex_cfg;
1175 link_info->pause = resp->pause;
1176 link_info->auto_pause = resp->auto_pause;
1177 link_info->force_pause = resp->force_pause;
1178 link_info->auto_mode = resp->auto_mode;
1179 link_info->phy_type = resp->phy_type;
1180 link_info->media_type = resp->media_type;
1182 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1183 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1184 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1185 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1186 link_info->phy_ver[0] = resp->phy_maj;
1187 link_info->phy_ver[1] = resp->phy_min;
1188 link_info->phy_ver[2] = resp->phy_bld;
1192 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1193 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1194 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1195 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1196 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1197 link_info->auto_link_speed_mask);
1198 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1199 link_info->force_link_speed);
1204 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1207 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1208 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1209 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1213 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1215 req.flags = rte_cpu_to_le_32(dir);
1216 /* HWRM Version >= 1.9.1 */
1217 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1219 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1220 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1222 HWRM_CHECK_RESULT();
1224 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1225 GET_TX_QUEUE_INFO(0);
1226 GET_TX_QUEUE_INFO(1);
1227 GET_TX_QUEUE_INFO(2);
1228 GET_TX_QUEUE_INFO(3);
1229 GET_TX_QUEUE_INFO(4);
1230 GET_TX_QUEUE_INFO(5);
1231 GET_TX_QUEUE_INFO(6);
1232 GET_TX_QUEUE_INFO(7);
1234 GET_RX_QUEUE_INFO(0);
1235 GET_RX_QUEUE_INFO(1);
1236 GET_RX_QUEUE_INFO(2);
1237 GET_RX_QUEUE_INFO(3);
1238 GET_RX_QUEUE_INFO(4);
1239 GET_RX_QUEUE_INFO(5);
1240 GET_RX_QUEUE_INFO(6);
1241 GET_RX_QUEUE_INFO(7);
1246 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1249 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1250 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1254 /* iterate and find the COSq profile to use for Tx */
1255 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1256 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1257 if (bp->tx_cos_queue[i].id != 0xff)
1258 bp->tx_cosq_id[j++] =
1259 bp->tx_cos_queue[i].id;
1262 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1263 if (bp->tx_cos_queue[i].profile ==
1264 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1266 bp->tx_cos_queue[i].id;
1273 bp->max_tc = resp->max_configurable_queues;
1274 bp->max_lltc = resp->max_configurable_lossless_queues;
1275 if (bp->max_tc > BNXT_MAX_QUEUE)
1276 bp->max_tc = BNXT_MAX_QUEUE;
1277 bp->max_q = bp->max_tc;
1279 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1280 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1288 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1289 struct bnxt_ring *ring,
1290 uint32_t ring_type, uint32_t map_index,
1291 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1292 uint16_t tx_cosq_id)
1295 uint32_t enables = 0;
1296 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1297 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1298 struct rte_mempool *mb_pool;
1299 uint16_t rx_buf_size;
1301 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1303 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1304 req.fbo = rte_cpu_to_le_32(0);
1305 /* Association of ring index with doorbell index */
1306 req.logical_id = rte_cpu_to_le_16(map_index);
1307 req.length = rte_cpu_to_le_32(ring->ring_size);
1309 switch (ring_type) {
1310 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1311 req.ring_type = ring_type;
1312 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1313 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1314 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1315 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1317 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1319 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1320 req.ring_type = ring_type;
1321 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1322 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1323 if (BNXT_CHIP_THOR(bp)) {
1324 mb_pool = bp->rx_queues[0]->mb_pool;
1325 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1326 RTE_PKTMBUF_HEADROOM;
1327 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1328 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1330 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1332 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1334 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1336 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1337 req.ring_type = ring_type;
1338 if (BNXT_HAS_NQ(bp)) {
1339 /* Association of cp ring with nq */
1340 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1342 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1344 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1346 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1347 req.ring_type = ring_type;
1348 req.page_size = BNXT_PAGE_SHFT;
1349 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1351 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1352 req.ring_type = ring_type;
1353 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1355 mb_pool = bp->rx_queues[0]->mb_pool;
1356 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1357 RTE_PKTMBUF_HEADROOM;
1358 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1359 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1361 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1362 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1363 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1364 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1367 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1372 req.enables = rte_cpu_to_le_32(enables);
1374 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1376 if (rc || resp->error_code) {
1377 if (rc == 0 && resp->error_code)
1378 rc = rte_le_to_cpu_16(resp->error_code);
1379 switch (ring_type) {
1380 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1382 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1385 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1387 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1390 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1392 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1396 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1398 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1401 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1403 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1407 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1413 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1418 int bnxt_hwrm_ring_free(struct bnxt *bp,
1419 struct bnxt_ring *ring, uint32_t ring_type)
1422 struct hwrm_ring_free_input req = {.req_type = 0 };
1423 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1425 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1427 req.ring_type = ring_type;
1428 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1430 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1432 if (rc || resp->error_code) {
1433 if (rc == 0 && resp->error_code)
1434 rc = rte_le_to_cpu_16(resp->error_code);
1437 switch (ring_type) {
1438 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1439 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1442 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1443 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1446 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1447 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1450 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1452 "hwrm_ring_free nq failed. rc:%d\n", rc);
1454 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1456 "hwrm_ring_free agg failed. rc:%d\n", rc);
1459 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1467 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1470 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1471 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1473 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1475 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1476 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1477 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1478 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1480 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1482 HWRM_CHECK_RESULT();
1484 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1491 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1494 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1495 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1497 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1499 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1501 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1503 HWRM_CHECK_RESULT();
1506 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1510 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1513 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1514 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1516 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1519 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1521 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1523 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1525 HWRM_CHECK_RESULT();
1531 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1532 unsigned int idx __rte_unused)
1535 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1536 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1538 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1540 req.update_period_ms = rte_cpu_to_le_32(0);
1542 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1544 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1546 HWRM_CHECK_RESULT();
1548 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1555 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1556 unsigned int idx __rte_unused)
1559 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1560 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1562 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1564 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1566 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1568 HWRM_CHECK_RESULT();
1574 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1577 struct hwrm_vnic_alloc_input req = { 0 };
1578 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1580 if (!BNXT_HAS_RING_GRPS(bp))
1581 goto skip_ring_grps;
1583 /* map ring groups to this vnic */
1584 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1585 vnic->start_grp_id, vnic->end_grp_id);
1586 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1587 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1589 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1590 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1591 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1592 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1595 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1596 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1598 if (vnic->func_default)
1600 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1601 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1603 HWRM_CHECK_RESULT();
1605 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1607 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1611 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1612 struct bnxt_vnic_info *vnic,
1613 struct bnxt_plcmodes_cfg *pmode)
1616 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1617 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1619 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1621 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1623 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1625 HWRM_CHECK_RESULT();
1627 pmode->flags = rte_le_to_cpu_32(resp->flags);
1628 /* dflt_vnic bit doesn't exist in the _cfg command */
1629 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1630 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1631 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1632 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1639 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1640 struct bnxt_vnic_info *vnic,
1641 struct bnxt_plcmodes_cfg *pmode)
1644 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1645 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1647 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1648 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1652 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1654 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1655 req.flags = rte_cpu_to_le_32(pmode->flags);
1656 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1657 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1658 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1659 req.enables = rte_cpu_to_le_32(
1660 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1661 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1662 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1665 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1667 HWRM_CHECK_RESULT();
1673 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1676 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1677 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1678 struct bnxt_plcmodes_cfg pmodes = { 0 };
1679 uint32_t ctx_enable_flag = 0;
1680 uint32_t enables = 0;
1682 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1683 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1687 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1691 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1693 if (BNXT_CHIP_THOR(bp)) {
1694 struct bnxt_rx_queue *rxq =
1695 bp->eth_dev->data->rx_queues[vnic->start_grp_id];
1696 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1697 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1699 req.default_rx_ring_id =
1700 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1701 req.default_cmpl_ring_id =
1702 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1703 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1704 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1708 /* Only RSS support for now TBD: COS & LB */
1709 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1710 if (vnic->lb_rule != 0xffff)
1711 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1712 if (vnic->cos_rule != 0xffff)
1713 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1714 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1715 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1716 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1718 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1719 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1720 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1723 enables |= ctx_enable_flag;
1724 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1725 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1726 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1727 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1730 req.enables = rte_cpu_to_le_32(enables);
1731 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1732 req.mru = rte_cpu_to_le_16(vnic->mru);
1733 /* Configure default VNIC only once. */
1734 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1736 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1737 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1739 if (vnic->vlan_strip)
1741 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1744 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1745 if (vnic->roce_dual)
1746 req.flags |= rte_cpu_to_le_32(
1747 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1748 if (vnic->roce_only)
1749 req.flags |= rte_cpu_to_le_32(
1750 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1751 if (vnic->rss_dflt_cr)
1752 req.flags |= rte_cpu_to_le_32(
1753 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1755 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1757 HWRM_CHECK_RESULT();
1760 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1765 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1769 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1770 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1772 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1773 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1776 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1779 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1780 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1781 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1783 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1785 HWRM_CHECK_RESULT();
1787 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1788 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1789 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1790 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1791 vnic->mru = rte_le_to_cpu_16(resp->mru);
1792 vnic->func_default = rte_le_to_cpu_32(
1793 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1794 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1795 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1796 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1797 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1798 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1799 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1800 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1801 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1802 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1803 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1810 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1811 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1815 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1816 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1817 bp->hwrm_cmd_resp_addr;
1819 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1821 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1822 HWRM_CHECK_RESULT();
1824 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1825 if (!BNXT_HAS_RING_GRPS(bp))
1826 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1827 else if (ctx_idx == 0)
1828 vnic->rss_rule = ctx_id;
1836 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1837 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1840 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1841 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1842 bp->hwrm_cmd_resp_addr;
1844 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1845 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1848 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1850 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1852 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1854 HWRM_CHECK_RESULT();
1860 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1864 if (BNXT_CHIP_THOR(bp)) {
1867 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1868 rc = _bnxt_hwrm_vnic_ctx_free(bp,
1870 vnic->fw_grp_ids[j]);
1871 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1873 vnic->num_lb_ctxts = 0;
1875 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1876 vnic->rss_rule = INVALID_HW_RING_ID;
1882 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1885 struct hwrm_vnic_free_input req = {.req_type = 0 };
1886 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1888 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1889 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1893 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1895 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1897 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1899 HWRM_CHECK_RESULT();
1902 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1903 /* Configure default VNIC again if necessary. */
1904 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1905 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1911 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1915 int nr_ctxs = vnic->num_lb_ctxts;
1916 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1917 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1919 for (i = 0; i < nr_ctxs; i++) {
1920 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1922 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1923 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1924 req.hash_mode_flags = vnic->hash_mode;
1926 req.hash_key_tbl_addr =
1927 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1929 req.ring_grp_tbl_addr =
1930 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1931 i * HW_HASH_INDEX_SIZE);
1932 req.ring_table_pair_index = i;
1933 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1935 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1938 HWRM_CHECK_RESULT();
1945 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1946 struct bnxt_vnic_info *vnic)
1949 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1950 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1952 if (!vnic->rss_table)
1955 if (BNXT_CHIP_THOR(bp))
1956 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1958 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1960 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1961 req.hash_mode_flags = vnic->hash_mode;
1963 req.ring_grp_tbl_addr =
1964 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1965 req.hash_key_tbl_addr =
1966 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1967 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1968 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1970 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1972 HWRM_CHECK_RESULT();
1978 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1979 struct bnxt_vnic_info *vnic)
1982 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1983 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1986 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1987 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1991 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1993 req.flags = rte_cpu_to_le_32(
1994 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1996 req.enables = rte_cpu_to_le_32(
1997 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1999 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2000 size -= RTE_PKTMBUF_HEADROOM;
2001 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2003 req.jumbo_thresh = rte_cpu_to_le_16(size);
2004 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2006 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2008 HWRM_CHECK_RESULT();
2014 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2015 struct bnxt_vnic_info *vnic, bool enable)
2018 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2019 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2021 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2023 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2027 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2028 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2032 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2035 req.enables = rte_cpu_to_le_32(
2036 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2037 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2038 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2039 req.flags = rte_cpu_to_le_32(
2040 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2041 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2042 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2043 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2044 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2045 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2046 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2047 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2048 req.min_agg_len = rte_cpu_to_le_32(512);
2050 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2052 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2054 HWRM_CHECK_RESULT();
2060 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2062 struct hwrm_func_cfg_input req = {0};
2063 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2066 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2067 req.enables = rte_cpu_to_le_32(
2068 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2069 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2070 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2072 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2074 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2075 HWRM_CHECK_RESULT();
2078 bp->pf.vf_info[vf].random_mac = false;
2083 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2087 struct hwrm_func_qstats_input req = {.req_type = 0};
2088 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2090 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2092 req.fid = rte_cpu_to_le_16(fid);
2094 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2096 HWRM_CHECK_RESULT();
2099 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2106 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2107 struct rte_eth_stats *stats)
2110 struct hwrm_func_qstats_input req = {.req_type = 0};
2111 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2113 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2115 req.fid = rte_cpu_to_le_16(fid);
2117 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2119 HWRM_CHECK_RESULT();
2121 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2122 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2123 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2124 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2125 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2126 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2128 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2129 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2130 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2131 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2132 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2133 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2135 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2136 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2137 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2144 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2147 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2148 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2150 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2152 req.fid = rte_cpu_to_le_16(fid);
2154 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2156 HWRM_CHECK_RESULT();
2162 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2167 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2168 struct bnxt_tx_queue *txq;
2169 struct bnxt_rx_queue *rxq;
2170 struct bnxt_cp_ring_info *cpr;
2172 if (i >= bp->rx_cp_nr_rings) {
2173 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2176 rxq = bp->rx_queues[i];
2180 rc = bnxt_hwrm_stat_clear(bp, cpr);
2187 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2191 struct bnxt_cp_ring_info *cpr;
2193 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2195 if (i >= bp->rx_cp_nr_rings) {
2196 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2198 cpr = bp->rx_queues[i]->cp_ring;
2199 if (BNXT_HAS_RING_GRPS(bp))
2200 bp->grp_info[i].fw_stats_ctx = -1;
2202 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2203 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2204 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2212 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2217 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2218 struct bnxt_tx_queue *txq;
2219 struct bnxt_rx_queue *rxq;
2220 struct bnxt_cp_ring_info *cpr;
2222 if (i >= bp->rx_cp_nr_rings) {
2223 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2226 rxq = bp->rx_queues[i];
2230 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2238 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2243 if (!BNXT_HAS_RING_GRPS(bp))
2246 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2248 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2251 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2259 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2261 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2263 bnxt_hwrm_ring_free(bp, cp_ring,
2264 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2265 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2266 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2267 sizeof(*cpr->cp_desc_ring));
2268 cpr->cp_raw_cons = 0;
2272 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2274 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2276 bnxt_hwrm_ring_free(bp, cp_ring,
2277 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2278 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2279 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2280 sizeof(*cpr->cp_desc_ring));
2281 cpr->cp_raw_cons = 0;
2285 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2287 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2288 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2289 struct bnxt_ring *ring = rxr->rx_ring_struct;
2290 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2292 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2293 bnxt_hwrm_ring_free(bp, ring,
2294 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2295 ring->fw_ring_id = INVALID_HW_RING_ID;
2296 if (BNXT_HAS_RING_GRPS(bp))
2297 bp->grp_info[queue_index].rx_fw_ring_id =
2299 memset(rxr->rx_desc_ring, 0,
2300 rxr->rx_ring_struct->ring_size *
2301 sizeof(*rxr->rx_desc_ring));
2302 memset(rxr->rx_buf_ring, 0,
2303 rxr->rx_ring_struct->ring_size *
2304 sizeof(*rxr->rx_buf_ring));
2307 ring = rxr->ag_ring_struct;
2308 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2309 bnxt_hwrm_ring_free(bp, ring,
2310 BNXT_CHIP_THOR(bp) ?
2311 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2312 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2313 ring->fw_ring_id = INVALID_HW_RING_ID;
2314 memset(rxr->ag_buf_ring, 0,
2315 rxr->ag_ring_struct->ring_size *
2316 sizeof(*rxr->ag_buf_ring));
2318 if (BNXT_HAS_RING_GRPS(bp))
2319 bp->grp_info[queue_index].ag_fw_ring_id =
2322 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2323 bnxt_free_cp_ring(bp, cpr);
2325 if (BNXT_HAS_RING_GRPS(bp))
2326 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2329 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2333 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2334 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2335 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2336 struct bnxt_ring *ring = txr->tx_ring_struct;
2337 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2339 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2340 bnxt_hwrm_ring_free(bp, ring,
2341 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2342 ring->fw_ring_id = INVALID_HW_RING_ID;
2343 memset(txr->tx_desc_ring, 0,
2344 txr->tx_ring_struct->ring_size *
2345 sizeof(*txr->tx_desc_ring));
2346 memset(txr->tx_buf_ring, 0,
2347 txr->tx_ring_struct->ring_size *
2348 sizeof(*txr->tx_buf_ring));
2352 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2353 bnxt_free_cp_ring(bp, cpr);
2354 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2358 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2359 bnxt_free_hwrm_rx_ring(bp, i);
2364 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2369 if (!BNXT_HAS_RING_GRPS(bp))
2372 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2373 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2381 * HWRM utility functions
2384 void bnxt_free_hwrm_resources(struct bnxt *bp)
2386 /* Release memzone */
2387 rte_free(bp->hwrm_cmd_resp_addr);
2388 rte_free(bp->hwrm_short_cmd_req_addr);
2389 bp->hwrm_cmd_resp_addr = NULL;
2390 bp->hwrm_short_cmd_req_addr = NULL;
2391 bp->hwrm_cmd_resp_dma_addr = 0;
2392 bp->hwrm_short_cmd_req_dma_addr = 0;
2395 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2397 struct rte_pci_device *pdev = bp->pdev;
2398 char type[RTE_MEMZONE_NAMESIZE];
2400 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2401 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2402 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2403 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2404 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2405 if (bp->hwrm_cmd_resp_addr == NULL)
2407 bp->hwrm_cmd_resp_dma_addr =
2408 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2409 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2411 "unable to map response address to physical memory\n");
2414 rte_spinlock_init(&bp->hwrm_lock);
2419 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2421 struct bnxt_filter_info *filter;
2424 STAILQ_FOREACH(filter, &vnic->filter, next) {
2425 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2426 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2427 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2428 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2430 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2431 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2432 bnxt_free_filter(bp, filter);
2438 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2440 struct bnxt_filter_info *filter;
2441 struct rte_flow *flow;
2444 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2445 flow = STAILQ_FIRST(&vnic->flow_list);
2446 filter = flow->filter;
2447 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2448 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2449 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2450 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2451 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2453 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2455 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2461 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2463 struct bnxt_filter_info *filter;
2466 STAILQ_FOREACH(filter, &vnic->filter, next) {
2467 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2468 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2470 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2471 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2474 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2485 void bnxt_free_tunnel_ports(struct bnxt *bp)
2487 if (bp->vxlan_port_cnt)
2488 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2489 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2491 if (bp->geneve_port_cnt)
2492 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2493 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2494 bp->geneve_port = 0;
2497 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2501 if (bp->vnic_info == NULL)
2505 * Cleanup VNICs in reverse order, to make sure the L2 filter
2506 * from vnic0 is last to be cleaned up.
2508 for (i = bp->max_vnics - 1; i >= 0; i--) {
2509 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2511 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2514 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2516 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2518 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2520 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2522 bnxt_hwrm_vnic_free(bp, vnic);
2524 rte_free(vnic->fw_grp_ids);
2526 /* Ring resources */
2527 bnxt_free_all_hwrm_rings(bp);
2528 bnxt_free_all_hwrm_ring_grps(bp);
2529 bnxt_free_all_hwrm_stat_ctxs(bp);
2530 bnxt_free_tunnel_ports(bp);
2533 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2535 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2537 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2538 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2540 switch (conf_link_speed) {
2541 case ETH_LINK_SPEED_10M_HD:
2542 case ETH_LINK_SPEED_100M_HD:
2544 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2546 return hw_link_duplex;
2549 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2551 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2554 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2556 uint16_t eth_link_speed = 0;
2558 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2559 return ETH_LINK_SPEED_AUTONEG;
2561 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2562 case ETH_LINK_SPEED_100M:
2563 case ETH_LINK_SPEED_100M_HD:
2566 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2568 case ETH_LINK_SPEED_1G:
2570 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2572 case ETH_LINK_SPEED_2_5G:
2574 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2576 case ETH_LINK_SPEED_10G:
2578 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2580 case ETH_LINK_SPEED_20G:
2582 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2584 case ETH_LINK_SPEED_25G:
2586 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2588 case ETH_LINK_SPEED_40G:
2590 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2592 case ETH_LINK_SPEED_50G:
2594 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2596 case ETH_LINK_SPEED_100G:
2598 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2602 "Unsupported link speed %d; default to AUTO\n",
2606 return eth_link_speed;
2609 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2610 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2611 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2612 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2614 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2618 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2621 if (link_speed & ETH_LINK_SPEED_FIXED) {
2622 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2624 if (one_speed & (one_speed - 1)) {
2626 "Invalid advertised speeds (%u) for port %u\n",
2627 link_speed, port_id);
2630 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2632 "Unsupported advertised speed (%u) for port %u\n",
2633 link_speed, port_id);
2637 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2639 "Unsupported advertised speeds (%u) for port %u\n",
2640 link_speed, port_id);
2648 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2652 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2653 if (bp->link_info.support_speeds)
2654 return bp->link_info.support_speeds;
2655 link_speed = BNXT_SUPPORTED_SPEEDS;
2658 if (link_speed & ETH_LINK_SPEED_100M)
2659 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2660 if (link_speed & ETH_LINK_SPEED_100M_HD)
2661 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2662 if (link_speed & ETH_LINK_SPEED_1G)
2663 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2664 if (link_speed & ETH_LINK_SPEED_2_5G)
2665 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2666 if (link_speed & ETH_LINK_SPEED_10G)
2667 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2668 if (link_speed & ETH_LINK_SPEED_20G)
2669 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2670 if (link_speed & ETH_LINK_SPEED_25G)
2671 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2672 if (link_speed & ETH_LINK_SPEED_40G)
2673 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2674 if (link_speed & ETH_LINK_SPEED_50G)
2675 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2676 if (link_speed & ETH_LINK_SPEED_100G)
2677 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2681 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2683 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2685 switch (hw_link_speed) {
2686 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2687 eth_link_speed = ETH_SPEED_NUM_100M;
2689 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2690 eth_link_speed = ETH_SPEED_NUM_1G;
2692 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2693 eth_link_speed = ETH_SPEED_NUM_2_5G;
2695 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2696 eth_link_speed = ETH_SPEED_NUM_10G;
2698 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2699 eth_link_speed = ETH_SPEED_NUM_20G;
2701 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2702 eth_link_speed = ETH_SPEED_NUM_25G;
2704 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2705 eth_link_speed = ETH_SPEED_NUM_40G;
2707 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2708 eth_link_speed = ETH_SPEED_NUM_50G;
2710 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2711 eth_link_speed = ETH_SPEED_NUM_100G;
2713 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2715 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2719 return eth_link_speed;
2722 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2724 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2726 switch (hw_link_duplex) {
2727 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2728 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2730 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2732 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2733 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2736 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2740 return eth_link_duplex;
2743 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2746 struct bnxt_link_info *link_info = &bp->link_info;
2748 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2751 "Get link config failed with rc %d\n", rc);
2754 if (link_info->link_speed)
2756 bnxt_parse_hw_link_speed(link_info->link_speed);
2758 link->link_speed = ETH_SPEED_NUM_NONE;
2759 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2760 link->link_status = link_info->link_up;
2761 link->link_autoneg = link_info->auto_mode ==
2762 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2763 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2768 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2771 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2772 struct bnxt_link_info link_req;
2773 uint16_t speed, autoneg;
2775 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2778 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2779 bp->eth_dev->data->port_id);
2783 memset(&link_req, 0, sizeof(link_req));
2784 link_req.link_up = link_up;
2788 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2789 if (BNXT_CHIP_THOR(bp) &&
2790 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2791 /* 40G is not supported as part of media auto detect.
2792 * The speed should be forced and autoneg disabled
2793 * to configure 40G speed.
2795 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2799 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2800 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2801 /* Autoneg can be done only when the FW allows.
2802 * When user configures fixed speed of 40G and later changes to
2803 * any other speed, auto_link_speed/force_link_speed is still set
2804 * to 40G until link comes up at new speed.
2807 !(!BNXT_CHIP_THOR(bp) &&
2808 (bp->link_info.auto_link_speed ||
2809 bp->link_info.force_link_speed))) {
2810 link_req.phy_flags |=
2811 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2812 link_req.auto_link_speed_mask =
2813 bnxt_parse_eth_link_speed_mask(bp,
2814 dev_conf->link_speeds);
2816 if (bp->link_info.phy_type ==
2817 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2818 bp->link_info.phy_type ==
2819 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2820 bp->link_info.media_type ==
2821 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2822 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2826 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2827 /* If user wants a particular speed try that first. */
2829 link_req.link_speed = speed;
2830 else if (bp->link_info.force_link_speed)
2831 link_req.link_speed = bp->link_info.force_link_speed;
2833 link_req.link_speed = bp->link_info.auto_link_speed;
2835 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2836 link_req.auto_pause = bp->link_info.auto_pause;
2837 link_req.force_pause = bp->link_info.force_pause;
2840 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2843 "Set link config failed with rc %d\n", rc);
2851 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2853 struct hwrm_func_qcfg_input req = {0};
2854 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2858 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2859 req.fid = rte_cpu_to_le_16(0xffff);
2861 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2863 HWRM_CHECK_RESULT();
2865 /* Hard Coded.. 0xfff VLAN ID mask */
2866 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2867 flags = rte_le_to_cpu_16(resp->flags);
2868 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2869 bp->flags |= BNXT_FLAG_MULTI_HOST;
2872 !BNXT_VF_IS_TRUSTED(bp) &&
2873 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2874 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2875 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2876 } else if (BNXT_VF(bp) &&
2877 BNXT_VF_IS_TRUSTED(bp) &&
2878 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2879 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2880 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2884 *mtu = rte_le_to_cpu_16(resp->mtu);
2886 switch (resp->port_partition_type) {
2887 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2888 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2889 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2891 bp->port_partition_type = resp->port_partition_type;
2894 bp->port_partition_type = 0;
2903 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2904 struct hwrm_func_qcaps_output *qcaps)
2906 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2907 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2908 sizeof(qcaps->mac_address));
2909 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2910 qcaps->max_rx_rings = fcfg->num_rx_rings;
2911 qcaps->max_tx_rings = fcfg->num_tx_rings;
2912 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2913 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2915 qcaps->first_vf_id = 0;
2916 qcaps->max_vnics = fcfg->num_vnics;
2917 qcaps->max_decap_records = 0;
2918 qcaps->max_encap_records = 0;
2919 qcaps->max_tx_wm_flows = 0;
2920 qcaps->max_tx_em_flows = 0;
2921 qcaps->max_rx_wm_flows = 0;
2922 qcaps->max_rx_em_flows = 0;
2923 qcaps->max_flow_id = 0;
2924 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2925 qcaps->max_sp_tx_rings = 0;
2926 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2929 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2931 struct hwrm_func_cfg_input req = {0};
2932 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2936 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2937 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2938 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2939 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2940 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2941 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2942 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2943 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2944 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2946 if (BNXT_HAS_RING_GRPS(bp)) {
2947 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2948 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2949 } else if (BNXT_HAS_NQ(bp)) {
2950 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2951 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2954 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2955 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2956 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
2957 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2958 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2959 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2960 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2961 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2962 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2963 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2964 req.fid = rte_cpu_to_le_16(0xffff);
2965 req.enables = rte_cpu_to_le_32(enables);
2967 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2969 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2971 HWRM_CHECK_RESULT();
2977 static void populate_vf_func_cfg_req(struct bnxt *bp,
2978 struct hwrm_func_cfg_input *req,
2981 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2982 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2983 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2984 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2985 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2986 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2987 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2988 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2989 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2990 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2992 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2993 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2995 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
2996 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2998 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2999 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3001 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3002 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3003 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3004 /* TODO: For now, do not support VMDq/RFS on VFs. */
3005 req->num_vnics = rte_cpu_to_le_16(1);
3006 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3010 static void add_random_mac_if_needed(struct bnxt *bp,
3011 struct hwrm_func_cfg_input *cfg_req,
3014 struct rte_ether_addr mac;
3016 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3019 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3021 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3022 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3023 bp->pf.vf_info[vf].random_mac = true;
3025 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3026 RTE_ETHER_ADDR_LEN);
3030 static void reserve_resources_from_vf(struct bnxt *bp,
3031 struct hwrm_func_cfg_input *cfg_req,
3034 struct hwrm_func_qcaps_input req = {0};
3035 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3038 /* Get the actual allocated values now */
3039 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3040 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3041 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3044 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3045 copy_func_cfg_to_qcaps(cfg_req, resp);
3046 } else if (resp->error_code) {
3047 rc = rte_le_to_cpu_16(resp->error_code);
3048 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3049 copy_func_cfg_to_qcaps(cfg_req, resp);
3052 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3053 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3054 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3055 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3056 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3057 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3059 * TODO: While not supporting VMDq with VFs, max_vnics is always
3060 * forced to 1 in this case
3062 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3063 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3068 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3070 struct hwrm_func_qcfg_input req = {0};
3071 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3074 /* Check for zero MAC address */
3075 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3076 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3077 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3078 HWRM_CHECK_RESULT();
3079 rc = rte_le_to_cpu_16(resp->vlan);
3086 static int update_pf_resource_max(struct bnxt *bp)
3088 struct hwrm_func_qcfg_input req = {0};
3089 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3092 /* And copy the allocated numbers into the pf struct */
3093 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3094 req.fid = rte_cpu_to_le_16(0xffff);
3095 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3096 HWRM_CHECK_RESULT();
3098 /* Only TX ring value reflects actual allocation? TODO */
3099 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3100 bp->pf.evb_mode = resp->evb_mode;
3107 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3112 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3116 rc = bnxt_hwrm_func_qcaps(bp);
3120 bp->pf.func_cfg_flags &=
3121 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3122 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3123 bp->pf.func_cfg_flags |=
3124 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3125 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3126 rc = __bnxt_hwrm_func_qcaps(bp);
3130 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3132 struct hwrm_func_cfg_input req = {0};
3133 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3140 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3144 rc = bnxt_hwrm_func_qcaps(bp);
3149 bp->pf.active_vfs = num_vfs;
3152 * First, configure the PF to only use one TX ring. This ensures that
3153 * there are enough rings for all VFs.
3155 * If we don't do this, when we call func_alloc() later, we will lock
3156 * extra rings to the PF that won't be available during func_cfg() of
3159 * This has been fixed with firmware versions above 20.6.54
3161 bp->pf.func_cfg_flags &=
3162 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3163 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3164 bp->pf.func_cfg_flags |=
3165 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3166 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3171 * Now, create and register a buffer to hold forwarded VF requests
3173 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3174 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3175 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3176 if (bp->pf.vf_req_buf == NULL) {
3180 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3181 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3182 for (i = 0; i < num_vfs; i++)
3183 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3184 (i * HWRM_MAX_REQ_LEN);
3186 rc = bnxt_hwrm_func_buf_rgtr(bp);
3190 populate_vf_func_cfg_req(bp, &req, num_vfs);
3192 bp->pf.active_vfs = 0;
3193 for (i = 0; i < num_vfs; i++) {
3194 add_random_mac_if_needed(bp, &req, i);
3196 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3197 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3198 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3199 rc = bnxt_hwrm_send_message(bp,
3204 /* Clear enable flag for next pass */
3205 req.enables &= ~rte_cpu_to_le_32(
3206 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3208 if (rc || resp->error_code) {
3210 "Failed to initizlie VF %d\n", i);
3212 "Not all VFs available. (%d, %d)\n",
3213 rc, resp->error_code);
3220 reserve_resources_from_vf(bp, &req, i);
3221 bp->pf.active_vfs++;
3222 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3226 * Now configure the PF to use "the rest" of the resources
3227 * We're using STD_TX_RING_MODE here though which will limit the TX
3228 * rings. This will allow QoS to function properly. Not setting this
3229 * will cause PF rings to break bandwidth settings.
3231 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3235 rc = update_pf_resource_max(bp);
3242 bnxt_hwrm_func_buf_unrgtr(bp);
3246 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3248 struct hwrm_func_cfg_input req = {0};
3249 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3252 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3254 req.fid = rte_cpu_to_le_16(0xffff);
3255 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3256 req.evb_mode = bp->pf.evb_mode;
3258 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3259 HWRM_CHECK_RESULT();
3265 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3266 uint8_t tunnel_type)
3268 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3269 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3272 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3273 req.tunnel_type = tunnel_type;
3274 req.tunnel_dst_port_val = port;
3275 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3276 HWRM_CHECK_RESULT();
3278 switch (tunnel_type) {
3279 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3280 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3281 bp->vxlan_port = port;
3283 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3284 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3285 bp->geneve_port = port;
3296 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3297 uint8_t tunnel_type)
3299 struct hwrm_tunnel_dst_port_free_input req = {0};
3300 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3303 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3305 req.tunnel_type = tunnel_type;
3306 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3307 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3309 HWRM_CHECK_RESULT();
3315 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3318 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3319 struct hwrm_func_cfg_input req = {0};
3322 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3324 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3325 req.flags = rte_cpu_to_le_32(flags);
3326 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3328 HWRM_CHECK_RESULT();
3334 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3336 uint32_t *flag = flagp;
3338 vnic->flags = *flag;
3341 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3343 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3346 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3349 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3350 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3352 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3354 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3355 req.req_buf_page_size = rte_cpu_to_le_16(
3356 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3357 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3358 req.req_buf_page_addr0 =
3359 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3360 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3362 "unable to map buffer address to physical memory\n");
3366 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3368 HWRM_CHECK_RESULT();
3374 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3377 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3378 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3380 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3383 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3385 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3387 HWRM_CHECK_RESULT();
3393 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3395 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3396 struct hwrm_func_cfg_input req = {0};
3399 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3401 req.fid = rte_cpu_to_le_16(0xffff);
3402 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3403 req.enables = rte_cpu_to_le_32(
3404 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3405 req.async_event_cr = rte_cpu_to_le_16(
3406 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3407 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3409 HWRM_CHECK_RESULT();
3415 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3417 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3418 struct hwrm_func_vf_cfg_input req = {0};
3421 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3423 req.enables = rte_cpu_to_le_32(
3424 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3425 req.async_event_cr = rte_cpu_to_le_16(
3426 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3427 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3429 HWRM_CHECK_RESULT();
3435 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3437 struct hwrm_func_cfg_input req = {0};
3438 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3439 uint16_t dflt_vlan, fid;
3440 uint32_t func_cfg_flags;
3443 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3446 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3447 fid = bp->pf.vf_info[vf].fid;
3448 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3450 fid = rte_cpu_to_le_16(0xffff);
3451 func_cfg_flags = bp->pf.func_cfg_flags;
3452 dflt_vlan = bp->vlan;
3455 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3456 req.fid = rte_cpu_to_le_16(fid);
3457 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3458 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3460 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3462 HWRM_CHECK_RESULT();
3468 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3469 uint16_t max_bw, uint16_t enables)
3471 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3472 struct hwrm_func_cfg_input req = {0};
3475 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3477 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3478 req.enables |= rte_cpu_to_le_32(enables);
3479 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3480 req.max_bw = rte_cpu_to_le_32(max_bw);
3481 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3483 HWRM_CHECK_RESULT();
3489 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3491 struct hwrm_func_cfg_input req = {0};
3492 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3495 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3497 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3498 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3499 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3500 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3502 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3504 HWRM_CHECK_RESULT();
3510 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3515 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3517 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3522 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3523 void *encaped, size_t ec_size)
3526 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3527 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3529 if (ec_size > sizeof(req.encap_request))
3532 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3534 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3535 memcpy(req.encap_request, encaped, ec_size);
3537 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3539 HWRM_CHECK_RESULT();
3545 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3546 struct rte_ether_addr *mac)
3548 struct hwrm_func_qcfg_input req = {0};
3549 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3552 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3554 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3555 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3557 HWRM_CHECK_RESULT();
3559 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3566 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3567 void *encaped, size_t ec_size)
3570 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3571 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3573 if (ec_size > sizeof(req.encap_request))
3576 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3578 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3579 memcpy(req.encap_request, encaped, ec_size);
3581 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3583 HWRM_CHECK_RESULT();
3589 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3590 struct rte_eth_stats *stats, uint8_t rx)
3593 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3594 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3596 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3598 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3600 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3602 HWRM_CHECK_RESULT();
3605 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3606 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3607 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3608 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3609 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3610 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3611 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3612 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3614 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3615 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3616 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3617 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3618 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3619 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3627 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3629 struct hwrm_port_qstats_input req = {0};
3630 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3631 struct bnxt_pf_info *pf = &bp->pf;
3634 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3636 req.port_id = rte_cpu_to_le_16(pf->port_id);
3637 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3638 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3639 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3641 HWRM_CHECK_RESULT();
3647 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3649 struct hwrm_port_clr_stats_input req = {0};
3650 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3651 struct bnxt_pf_info *pf = &bp->pf;
3654 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3655 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3656 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3659 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3661 req.port_id = rte_cpu_to_le_16(pf->port_id);
3662 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3664 HWRM_CHECK_RESULT();
3670 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3672 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3673 struct hwrm_port_led_qcaps_input req = {0};
3679 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3680 req.port_id = bp->pf.port_id;
3681 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3683 HWRM_CHECK_RESULT();
3685 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3688 bp->num_leds = resp->num_leds;
3689 memcpy(bp->leds, &resp->led0_id,
3690 sizeof(bp->leds[0]) * bp->num_leds);
3691 for (i = 0; i < bp->num_leds; i++) {
3692 struct bnxt_led_info *led = &bp->leds[i];
3694 uint16_t caps = led->led_state_caps;
3696 if (!led->led_group_id ||
3697 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3709 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3711 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3712 struct hwrm_port_led_cfg_input req = {0};
3713 struct bnxt_led_cfg *led_cfg;
3714 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3715 uint16_t duration = 0;
3718 if (!bp->num_leds || BNXT_VF(bp))
3721 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3724 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3725 duration = rte_cpu_to_le_16(500);
3727 req.port_id = bp->pf.port_id;
3728 req.num_leds = bp->num_leds;
3729 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3730 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3731 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3732 led_cfg->led_id = bp->leds[i].led_id;
3733 led_cfg->led_state = led_state;
3734 led_cfg->led_blink_on = duration;
3735 led_cfg->led_blink_off = duration;
3736 led_cfg->led_group_id = bp->leds[i].led_group_id;
3739 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3741 HWRM_CHECK_RESULT();
3747 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3751 struct hwrm_nvm_get_dir_info_input req = {0};
3752 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3754 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3756 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3758 HWRM_CHECK_RESULT();
3760 *entries = rte_le_to_cpu_32(resp->entries);
3761 *length = rte_le_to_cpu_32(resp->entry_length);
3767 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3770 uint32_t dir_entries;
3771 uint32_t entry_length;
3774 rte_iova_t dma_handle;
3775 struct hwrm_nvm_get_dir_entries_input req = {0};
3776 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3778 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3782 *data++ = dir_entries;
3783 *data++ = entry_length;
3785 memset(data, 0xff, len);
3787 buflen = dir_entries * entry_length;
3788 buf = rte_malloc("nvm_dir", buflen, 0);
3789 rte_mem_lock_page(buf);
3792 dma_handle = rte_mem_virt2iova(buf);
3793 if (dma_handle == RTE_BAD_IOVA) {
3795 "unable to map response address to physical memory\n");
3798 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3799 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3800 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3803 memcpy(data, buf, len > buflen ? buflen : len);
3806 HWRM_CHECK_RESULT();
3812 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3813 uint32_t offset, uint32_t length,
3818 rte_iova_t dma_handle;
3819 struct hwrm_nvm_read_input req = {0};
3820 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3822 buf = rte_malloc("nvm_item", length, 0);
3823 rte_mem_lock_page(buf);
3827 dma_handle = rte_mem_virt2iova(buf);
3828 if (dma_handle == RTE_BAD_IOVA) {
3830 "unable to map response address to physical memory\n");
3833 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3834 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3835 req.dir_idx = rte_cpu_to_le_16(index);
3836 req.offset = rte_cpu_to_le_32(offset);
3837 req.len = rte_cpu_to_le_32(length);
3838 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3840 memcpy(data, buf, length);
3843 HWRM_CHECK_RESULT();
3849 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3852 struct hwrm_nvm_erase_dir_entry_input req = {0};
3853 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3855 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3856 req.dir_idx = rte_cpu_to_le_16(index);
3857 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3858 HWRM_CHECK_RESULT();
3865 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3866 uint16_t dir_ordinal, uint16_t dir_ext,
3867 uint16_t dir_attr, const uint8_t *data,
3871 struct hwrm_nvm_write_input req = {0};
3872 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3873 rte_iova_t dma_handle;
3876 buf = rte_malloc("nvm_write", data_len, 0);
3877 rte_mem_lock_page(buf);
3881 dma_handle = rte_mem_virt2iova(buf);
3882 if (dma_handle == RTE_BAD_IOVA) {
3884 "unable to map response address to physical memory\n");
3887 memcpy(buf, data, data_len);
3889 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3891 req.dir_type = rte_cpu_to_le_16(dir_type);
3892 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3893 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3894 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3895 req.dir_data_length = rte_cpu_to_le_32(data_len);
3896 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3898 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3901 HWRM_CHECK_RESULT();
3908 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3910 uint32_t *count = cbdata;
3912 *count = *count + 1;
3915 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3916 struct bnxt_vnic_info *vnic __rte_unused)
3921 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3925 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3926 &count, bnxt_vnic_count_hwrm_stub);
3931 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3934 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3935 struct hwrm_func_vf_vnic_ids_query_output *resp =
3936 bp->hwrm_cmd_resp_addr;
3939 /* First query all VNIC ids */
3940 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3942 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3943 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3944 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3946 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3949 "unable to map VNIC ID table address to physical memory\n");
3952 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3953 HWRM_CHECK_RESULT();
3954 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3962 * This function queries the VNIC IDs for a specified VF. It then calls
3963 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3964 * Then it calls the hwrm_cb function to program this new vnic configuration.
3966 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3967 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3968 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3970 struct bnxt_vnic_info vnic;
3972 int i, num_vnic_ids;
3977 /* First query all VNIC ids */
3978 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3979 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3980 RTE_CACHE_LINE_SIZE);
3981 if (vnic_ids == NULL)
3984 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3985 rte_mem_lock_page(((char *)vnic_ids) + sz);
3987 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3989 if (num_vnic_ids < 0)
3990 return num_vnic_ids;
3992 /* Retrieve VNIC, update bd_stall then update */
3994 for (i = 0; i < num_vnic_ids; i++) {
3995 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3996 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3997 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4000 if (vnic.mru <= 4) /* Indicates unallocated */
4003 vnic_cb(&vnic, cbdata);
4005 rc = hwrm_cb(bp, &vnic);
4015 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4018 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4019 struct hwrm_func_cfg_input req = {0};
4022 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4024 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4025 req.enables |= rte_cpu_to_le_32(
4026 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4027 req.vlan_antispoof_mode = on ?
4028 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4029 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4030 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4032 HWRM_CHECK_RESULT();
4038 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4040 struct bnxt_vnic_info vnic;
4043 int num_vnic_ids, i;
4047 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4048 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4049 RTE_CACHE_LINE_SIZE);
4050 if (vnic_ids == NULL)
4053 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4054 rte_mem_lock_page(((char *)vnic_ids) + sz);
4056 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4062 * Loop through to find the default VNIC ID.
4063 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4064 * by sending the hwrm_func_qcfg command to the firmware.
4066 for (i = 0; i < num_vnic_ids; i++) {
4067 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4068 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4069 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4070 bp->pf.first_vf_id + vf);
4073 if (vnic.func_default) {
4075 return vnic.fw_vnic_id;
4078 /* Could not find a default VNIC. */
4079 PMD_DRV_LOG(ERR, "No default VNIC\n");
4085 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4087 struct bnxt_filter_info *filter)
4090 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4091 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4092 uint32_t enables = 0;
4094 if (filter->fw_em_filter_id != UINT64_MAX)
4095 bnxt_hwrm_clear_em_filter(bp, filter);
4097 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4099 req.flags = rte_cpu_to_le_32(filter->flags);
4101 enables = filter->enables |
4102 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4103 req.dst_id = rte_cpu_to_le_16(dst_id);
4105 if (filter->ip_addr_type) {
4106 req.ip_addr_type = filter->ip_addr_type;
4107 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4110 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4111 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4113 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4114 memcpy(req.src_macaddr, filter->src_macaddr,
4115 RTE_ETHER_ADDR_LEN);
4117 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4118 memcpy(req.dst_macaddr, filter->dst_macaddr,
4119 RTE_ETHER_ADDR_LEN);
4121 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4122 req.ovlan_vid = filter->l2_ovlan;
4124 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4125 req.ivlan_vid = filter->l2_ivlan;
4127 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4128 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4130 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4131 req.ip_protocol = filter->ip_protocol;
4133 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4134 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4136 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4137 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4139 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4140 req.src_port = rte_cpu_to_be_16(filter->src_port);
4142 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4143 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4145 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4146 req.mirror_vnic_id = filter->mirror_vnic_id;
4148 req.enables = rte_cpu_to_le_32(enables);
4150 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4152 HWRM_CHECK_RESULT();
4154 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4160 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4163 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4164 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4166 if (filter->fw_em_filter_id == UINT64_MAX)
4169 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4170 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4172 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4174 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4176 HWRM_CHECK_RESULT();
4179 filter->fw_em_filter_id = UINT64_MAX;
4180 filter->fw_l2_filter_id = UINT64_MAX;
4185 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4187 struct bnxt_filter_info *filter)
4190 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4191 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4192 bp->hwrm_cmd_resp_addr;
4193 uint32_t enables = 0;
4195 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4196 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4198 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4200 req.flags = rte_cpu_to_le_32(filter->flags);
4202 enables = filter->enables |
4203 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4204 req.dst_id = rte_cpu_to_le_16(dst_id);
4206 if (filter->ip_addr_type) {
4207 req.ip_addr_type = filter->ip_addr_type;
4209 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4212 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4213 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4215 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4216 memcpy(req.src_macaddr, filter->src_macaddr,
4217 RTE_ETHER_ADDR_LEN);
4219 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4220 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4222 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4223 req.ip_protocol = filter->ip_protocol;
4225 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4226 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4228 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4229 req.src_ipaddr_mask[0] =
4230 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4232 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4233 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4235 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4236 req.dst_ipaddr_mask[0] =
4237 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4239 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4240 req.src_port = rte_cpu_to_le_16(filter->src_port);
4242 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4243 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4245 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4246 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4248 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4249 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4251 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4252 req.mirror_vnic_id = filter->mirror_vnic_id;
4254 req.enables = rte_cpu_to_le_32(enables);
4256 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4258 HWRM_CHECK_RESULT();
4260 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4266 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4267 struct bnxt_filter_info *filter)
4270 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4271 struct hwrm_cfa_ntuple_filter_free_output *resp =
4272 bp->hwrm_cmd_resp_addr;
4274 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4277 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4279 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4281 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4283 HWRM_CHECK_RESULT();
4286 filter->fw_ntuple_filter_id = UINT64_MAX;
4292 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4294 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4295 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4296 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4297 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4298 uint16_t *ring_tbl = vnic->rss_table;
4299 int nr_ctxs = vnic->num_lb_ctxts;
4300 int max_rings = bp->rx_nr_rings;
4304 for (i = 0, k = 0; i < nr_ctxs; i++) {
4305 struct bnxt_rx_ring_info *rxr;
4306 struct bnxt_cp_ring_info *cpr;
4308 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4310 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4311 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4312 req.hash_mode_flags = vnic->hash_mode;
4314 req.ring_grp_tbl_addr =
4315 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4316 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4317 2 * sizeof(*ring_tbl));
4318 req.hash_key_tbl_addr =
4319 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4321 req.ring_table_pair_index = i;
4322 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4324 for (j = 0; j < 64; j++) {
4327 /* Find next active ring. */
4328 for (cnt = 0; cnt < max_rings; cnt++) {
4329 if (rx_queue_state[k] !=
4330 RTE_ETH_QUEUE_STATE_STOPPED)
4332 if (++k == max_rings)
4336 /* Return if no rings are active. */
4337 if (cnt == max_rings)
4340 /* Add rx/cp ring pair to RSS table. */
4341 rxr = rxqs[k]->rx_ring;
4342 cpr = rxqs[k]->cp_ring;
4344 ring_id = rxr->rx_ring_struct->fw_ring_id;
4345 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4346 ring_id = cpr->cp_ring_struct->fw_ring_id;
4347 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4349 if (++k == max_rings)
4352 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4355 HWRM_CHECK_RESULT();
4362 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4364 unsigned int rss_idx, fw_idx, i;
4366 if (!(vnic->rss_table && vnic->hash_type))
4369 if (BNXT_CHIP_THOR(bp))
4370 return bnxt_vnic_rss_configure_thor(bp, vnic);
4372 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4375 if (vnic->rss_table && vnic->hash_type) {
4377 * Fill the RSS hash & redirection table with
4378 * ring group ids for all VNICs
4380 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4381 rss_idx++, fw_idx++) {
4382 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4383 fw_idx %= bp->rx_cp_nr_rings;
4384 if (vnic->fw_grp_ids[fw_idx] !=
4389 if (i == bp->rx_cp_nr_rings)
4391 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4393 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4399 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4400 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4404 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4406 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4407 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4409 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4410 req->num_cmpl_dma_aggr_during_int =
4411 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4413 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4415 /* min timer set to 1/2 of interrupt timer */
4416 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4418 /* buf timer set to 1/4 of interrupt timer */
4419 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4421 req->cmpl_aggr_dma_tmr_during_int =
4422 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4424 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4425 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4426 req->flags = rte_cpu_to_le_16(flags);
4429 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4430 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4432 struct hwrm_ring_aggint_qcaps_input req = {0};
4433 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4438 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4439 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4440 HWRM_CHECK_RESULT();
4442 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4443 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4445 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4446 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4447 agg_req->flags = rte_cpu_to_le_16(flags);
4449 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4450 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4451 agg_req->enables = rte_cpu_to_le_32(enables);
4457 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4458 struct bnxt_coal *coal, uint16_t ring_id)
4460 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4461 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4462 bp->hwrm_cmd_resp_addr;
4465 /* Set ring coalesce parameters only for 100G NICs */
4466 if (BNXT_CHIP_THOR(bp)) {
4467 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4469 } else if (bnxt_stratus_device(bp)) {
4470 bnxt_hwrm_set_coal_params(coal, &req);
4475 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4476 req.ring_id = rte_cpu_to_le_16(ring_id);
4477 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4478 HWRM_CHECK_RESULT();
4483 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4484 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4486 struct hwrm_func_backing_store_qcaps_input req = {0};
4487 struct hwrm_func_backing_store_qcaps_output *resp =
4488 bp->hwrm_cmd_resp_addr;
4489 struct bnxt_ctx_pg_info *ctx_pg;
4490 struct bnxt_ctx_mem_info *ctx;
4491 int total_alloc_len;
4494 if (!BNXT_CHIP_THOR(bp) ||
4495 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4500 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4501 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4502 HWRM_CHECK_RESULT_SILENT();
4504 total_alloc_len = sizeof(*ctx);
4505 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4506 RTE_CACHE_LINE_SIZE);
4512 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4513 sizeof(*ctx_pg) * BNXT_MAX_Q,
4514 RTE_CACHE_LINE_SIZE);
4519 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4520 ctx->tqm_mem[i] = ctx_pg;
4523 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4524 ctx->qp_min_qp1_entries =
4525 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4526 ctx->qp_max_l2_entries =
4527 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4528 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4529 ctx->srq_max_l2_entries =
4530 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4531 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4532 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4533 ctx->cq_max_l2_entries =
4534 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4535 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4536 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4537 ctx->vnic_max_vnic_entries =
4538 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4539 ctx->vnic_max_ring_table_entries =
4540 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4541 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4542 ctx->stat_max_entries =
4543 rte_le_to_cpu_32(resp->stat_max_entries);
4544 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4545 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4546 ctx->tqm_min_entries_per_ring =
4547 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4548 ctx->tqm_max_entries_per_ring =
4549 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4550 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4551 if (!ctx->tqm_entries_multiple)
4552 ctx->tqm_entries_multiple = 1;
4553 ctx->mrav_max_entries =
4554 rte_le_to_cpu_32(resp->mrav_max_entries);
4555 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4556 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4557 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4563 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4565 struct hwrm_func_backing_store_cfg_input req = {0};
4566 struct hwrm_func_backing_store_cfg_output *resp =
4567 bp->hwrm_cmd_resp_addr;
4568 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4569 struct bnxt_ctx_pg_info *ctx_pg;
4570 uint32_t *num_entries;
4579 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4580 req.enables = rte_cpu_to_le_32(enables);
4582 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4583 ctx_pg = &ctx->qp_mem;
4584 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4585 req.qp_num_qp1_entries =
4586 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4587 req.qp_num_l2_entries =
4588 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4589 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4590 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4591 &req.qpc_pg_size_qpc_lvl,
4595 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4596 ctx_pg = &ctx->srq_mem;
4597 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4598 req.srq_num_l2_entries =
4599 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4600 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4601 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4602 &req.srq_pg_size_srq_lvl,
4606 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4607 ctx_pg = &ctx->cq_mem;
4608 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4609 req.cq_num_l2_entries =
4610 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4611 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4612 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4613 &req.cq_pg_size_cq_lvl,
4617 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4618 ctx_pg = &ctx->vnic_mem;
4619 req.vnic_num_vnic_entries =
4620 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4621 req.vnic_num_ring_table_entries =
4622 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4623 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4624 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4625 &req.vnic_pg_size_vnic_lvl,
4626 &req.vnic_page_dir);
4629 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4630 ctx_pg = &ctx->stat_mem;
4631 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4632 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4633 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4634 &req.stat_pg_size_stat_lvl,
4635 &req.stat_page_dir);
4638 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4639 num_entries = &req.tqm_sp_num_entries;
4640 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4641 pg_dir = &req.tqm_sp_page_dir;
4642 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4643 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4644 if (!(enables & ena))
4647 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4649 ctx_pg = ctx->tqm_mem[i];
4650 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4651 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4654 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4655 HWRM_CHECK_RESULT();
4661 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4663 struct hwrm_port_qstats_ext_input req = {0};
4664 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4665 struct bnxt_pf_info *pf = &bp->pf;
4668 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4669 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4672 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4674 req.port_id = rte_cpu_to_le_16(pf->port_id);
4675 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4676 req.tx_stat_host_addr =
4677 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4679 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4681 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4682 req.rx_stat_host_addr =
4683 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4685 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4687 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4690 bp->fw_rx_port_stats_ext_size = 0;
4691 bp->fw_tx_port_stats_ext_size = 0;
4693 bp->fw_rx_port_stats_ext_size =
4694 rte_le_to_cpu_16(resp->rx_stat_size);
4695 bp->fw_tx_port_stats_ext_size =
4696 rte_le_to_cpu_16(resp->tx_stat_size);
4699 HWRM_CHECK_RESULT();
4706 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4708 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4709 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4710 bp->hwrm_cmd_resp_addr;
4713 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4714 req.tunnel_type = type;
4715 req.dest_fid = bp->fw_fid;
4716 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4717 HWRM_CHECK_RESULT();
4725 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4727 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4728 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4729 bp->hwrm_cmd_resp_addr;
4732 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4733 req.tunnel_type = type;
4734 req.dest_fid = bp->fw_fid;
4735 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4736 HWRM_CHECK_RESULT();
4743 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4745 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4746 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4747 bp->hwrm_cmd_resp_addr;
4750 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4751 req.src_fid = bp->fw_fid;
4752 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4753 HWRM_CHECK_RESULT();
4756 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4763 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4766 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4767 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4768 bp->hwrm_cmd_resp_addr;
4771 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4772 req.src_fid = bp->fw_fid;
4773 req.tunnel_type = tun_type;
4774 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4775 HWRM_CHECK_RESULT();
4778 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4780 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4787 int bnxt_hwrm_set_mac(struct bnxt *bp)
4789 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4790 struct hwrm_func_vf_cfg_input req = {0};
4796 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4799 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4800 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4802 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4804 HWRM_CHECK_RESULT();
4806 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4812 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4814 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4815 struct hwrm_func_drv_if_change_input req = {0};
4819 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4822 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4823 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4824 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4826 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4829 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4833 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4835 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4837 HWRM_CHECK_RESULT();
4838 flags = rte_le_to_cpu_32(resp->flags);
4844 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4845 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4846 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4852 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4854 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4855 struct bnxt_error_recovery_info *info = bp->recovery_info;
4856 struct hwrm_error_recovery_qcfg_input req = {0};
4861 /* Older FW does not have error recovery support */
4862 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4866 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4868 bp->recovery_info = info;
4872 memset(info, 0, sizeof(*info));
4875 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4877 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4879 HWRM_CHECK_RESULT();
4881 flags = rte_le_to_cpu_32(resp->flags);
4882 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4883 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4884 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4885 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4887 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4888 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4893 /* FW returned values are in units of 100msec */
4894 info->driver_polling_freq =
4895 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4896 info->master_func_wait_period =
4897 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4898 info->normal_func_wait_period =
4899 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4900 info->master_func_wait_period_after_reset =
4901 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4902 info->max_bailout_time_after_reset =
4903 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4904 info->status_regs[BNXT_FW_STATUS_REG] =
4905 rte_le_to_cpu_32(resp->fw_health_status_reg);
4906 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4907 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4908 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4909 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4910 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4911 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4912 info->reg_array_cnt =
4913 rte_le_to_cpu_32(resp->reg_array_cnt);
4915 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4920 for (i = 0; i < info->reg_array_cnt; i++) {
4921 info->reset_reg[i] =
4922 rte_le_to_cpu_32(resp->reset_reg[i]);
4923 info->reset_reg_val[i] =
4924 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4925 info->delay_after_reset[i] =
4926 resp->delay_after_reset[i];
4931 /* Map the FW status registers */
4933 rc = bnxt_map_fw_health_status_regs(bp);
4936 rte_free(bp->recovery_info);
4937 bp->recovery_info = NULL;
4942 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4944 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4945 struct hwrm_fw_reset_input req = {0};
4951 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4953 req.embedded_proc_type =
4954 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4955 req.selfrst_status =
4956 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4957 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4959 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4962 HWRM_CHECK_RESULT();
4968 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4970 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4971 struct hwrm_port_ts_query_input req = {0};
4972 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4979 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4982 case BNXT_PTP_FLAGS_PATH_TX:
4983 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4985 case BNXT_PTP_FLAGS_PATH_RX:
4986 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4988 case BNXT_PTP_FLAGS_CURRENT_TIME:
4989 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4993 req.flags = rte_cpu_to_le_32(flags);
4994 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4996 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4998 HWRM_CHECK_RESULT();
5001 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5003 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5010 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5012 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5013 bp->hwrm_cmd_resp_addr;
5014 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5018 if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5021 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5023 "Not a PF or trusted VF. Command not supported\n");
5027 HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5028 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5030 HWRM_CHECK_RESULT();
5031 flags = rte_le_to_cpu_32(resp->flags);
5034 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5035 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5036 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");