1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SPEC_CODE_1_8_3 0x10803
31 #define HWRM_VERSION_1_9_1 0x10901
33 struct bnxt_plcmodes_cfg {
35 uint16_t jumbo_thresh;
37 uint16_t hds_threshold;
40 static int page_getenum(size_t size)
56 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
57 return sizeof(void *) * 8 - 1;
60 static int page_roundup(size_t size)
62 return 1 << page_getenum(size);
66 * HWRM Functions (sent to HWRM)
67 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
68 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
69 * command was failed by the ChiMP.
72 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
73 uint32_t msg_len, bool use_kong_mb)
76 struct input *req = msg;
77 struct output *resp = bp->hwrm_cmd_resp_addr;
81 uint16_t max_req_len = bp->max_req_len;
82 struct hwrm_short_input short_input = { 0 };
83 uint16_t bar_offset = use_kong_mb ?
84 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
85 uint16_t mb_trigger_offset = use_kong_mb ?
86 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
88 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
89 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
91 memset(short_cmd_req, 0, bp->max_req_len);
92 memcpy(short_cmd_req, req, msg_len);
94 short_input.req_type = rte_cpu_to_le_16(req->req_type);
95 short_input.signature = rte_cpu_to_le_16(
96 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
97 short_input.size = rte_cpu_to_le_16(msg_len);
98 short_input.req_addr =
99 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
101 data = (uint32_t *)&short_input;
102 msg_len = sizeof(short_input);
104 /* Sync memory write before updating doorbell */
107 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
110 /* Write request msg to hwrm channel */
111 for (i = 0; i < msg_len; i += 4) {
112 bar = (uint8_t *)bp->bar0 + bar_offset + i;
113 rte_write32(*data, bar);
117 /* Zero the rest of the request space */
118 for (; i < max_req_len; i += 4) {
119 bar = (uint8_t *)bp->bar0 + bar_offset + i;
123 /* Ring channel doorbell */
124 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
127 /* Poll for the valid bit */
128 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
129 /* Sanity check on the resp->resp_len */
131 if (resp->resp_len && resp->resp_len <=
133 /* Last byte of resp contains the valid key */
134 valid = (uint8_t *)resp + resp->resp_len - 1;
135 if (*valid == HWRM_RESP_VALID_KEY)
141 if (i >= HWRM_CMD_TIMEOUT) {
142 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
153 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
154 * spinlock, and does initial processing.
156 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
157 * releases the spinlock only if it returns. If the regular int return codes
158 * are not used by the function, HWRM_CHECK_RESULT() should not be used
159 * directly, rather it should be copied and modified to suit the function.
161 * HWRM_UNLOCK() must be called after all response processing is completed.
163 #define HWRM_PREP(req, type, kong) do { \
164 rte_spinlock_lock(&bp->hwrm_lock); \
165 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
166 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
167 req.cmpl_ring = rte_cpu_to_le_16(-1); \
168 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
169 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
170 req.target_id = rte_cpu_to_le_16(0xffff); \
171 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
174 #define HWRM_CHECK_RESULT_SILENT() do {\
176 rte_spinlock_unlock(&bp->hwrm_lock); \
179 if (resp->error_code) { \
180 rc = rte_le_to_cpu_16(resp->error_code); \
181 rte_spinlock_unlock(&bp->hwrm_lock); \
186 #define HWRM_CHECK_RESULT() do {\
188 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
189 rte_spinlock_unlock(&bp->hwrm_lock); \
190 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
196 if (resp->error_code) { \
197 rc = rte_le_to_cpu_16(resp->error_code); \
198 if (resp->resp_len >= 16) { \
199 struct hwrm_err_output *tmp_hwrm_err_op = \
202 "error %d:%d:%08x:%04x\n", \
203 rc, tmp_hwrm_err_op->cmd_err, \
205 tmp_hwrm_err_op->opaque_0), \
207 tmp_hwrm_err_op->opaque_1)); \
209 PMD_DRV_LOG(ERR, "error %d\n", rc); \
211 rte_spinlock_unlock(&bp->hwrm_lock); \
212 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
220 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
222 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
225 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
226 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
228 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
229 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
232 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
240 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
241 struct bnxt_vnic_info *vnic,
243 struct bnxt_vlan_table_entry *vlan_table)
246 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
247 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
250 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
253 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
254 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
256 /* FIXME add multicast flag, when multicast adding options is supported
259 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
260 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
261 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
262 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
263 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
264 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
265 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
266 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
267 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
268 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
269 if (vnic->mc_addr_cnt) {
270 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
271 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
272 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
275 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
276 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
277 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
278 rte_mem_virt2iova(vlan_table));
279 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
281 req.mask = rte_cpu_to_le_32(mask);
283 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
291 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
293 struct bnxt_vlan_antispoof_table_entry *vlan_table)
296 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
297 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
298 bp->hwrm_cmd_resp_addr;
301 * Older HWRM versions did not support this command, and the set_rx_mask
302 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
303 * removed from set_rx_mask call, and this command was added.
305 * This command is also present from 1.7.8.11 and higher,
308 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
309 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
310 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
315 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
316 req.fid = rte_cpu_to_le_16(fid);
318 req.vlan_tag_mask_tbl_addr =
319 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
320 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
322 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
330 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
331 struct bnxt_filter_info *filter)
334 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
335 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
337 if (filter->fw_l2_filter_id == UINT64_MAX)
340 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
342 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
344 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
349 filter->fw_l2_filter_id = UINT64_MAX;
354 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
356 struct bnxt_filter_info *filter)
359 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
360 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
361 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
362 const struct rte_eth_vmdq_rx_conf *conf =
363 &dev_conf->rx_adv_conf.vmdq_rx_conf;
364 uint32_t enables = 0;
365 uint16_t j = dst_id - 1;
367 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
368 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
369 conf->pool_map[j].pools & (1UL << j)) {
371 "Add vlan %u to vmdq pool %u\n",
372 conf->pool_map[j].vlan_id, j);
374 filter->l2_ivlan = conf->pool_map[j].vlan_id;
376 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
377 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
380 if (filter->fw_l2_filter_id != UINT64_MAX)
381 bnxt_hwrm_clear_l2_filter(bp, filter);
383 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
385 req.flags = rte_cpu_to_le_32(filter->flags);
387 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
389 enables = filter->enables |
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
391 req.dst_id = rte_cpu_to_le_16(dst_id);
394 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
395 memcpy(req.l2_addr, filter->l2_addr,
398 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
399 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
402 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
403 req.l2_ovlan = filter->l2_ovlan;
405 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
406 req.l2_ivlan = filter->l2_ivlan;
408 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
409 req.l2_ovlan_mask = filter->l2_ovlan_mask;
411 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
412 req.l2_ivlan_mask = filter->l2_ivlan_mask;
413 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
414 req.src_id = rte_cpu_to_le_32(filter->src_id);
415 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
416 req.src_type = filter->src_type;
418 req.enables = rte_cpu_to_le_32(enables);
420 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
424 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
430 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
432 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
433 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
440 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
443 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
446 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
447 if (ptp->tx_tstamp_en)
448 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
451 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
452 req.flags = rte_cpu_to_le_32(flags);
453 req.enables = rte_cpu_to_le_32
454 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
455 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
457 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
463 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
466 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
467 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
468 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
470 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
474 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
476 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
478 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
482 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
485 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
489 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
490 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
491 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
492 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
493 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
494 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
495 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
496 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
497 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
498 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
499 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
500 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
501 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
502 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
503 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
504 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
505 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
506 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
514 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
517 struct hwrm_func_qcaps_input req = {.req_type = 0 };
518 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
519 uint16_t new_max_vfs;
523 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
525 req.fid = rte_cpu_to_le_16(0xffff);
527 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
531 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
532 flags = rte_le_to_cpu_32(resp->flags);
534 bp->pf.port_id = resp->port_id;
535 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
536 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
537 new_max_vfs = bp->pdev->max_vfs;
538 if (new_max_vfs != bp->pf.max_vfs) {
540 rte_free(bp->pf.vf_info);
541 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
542 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
543 bp->pf.max_vfs = new_max_vfs;
544 for (i = 0; i < new_max_vfs; i++) {
545 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
546 bp->pf.vf_info[i].vlan_table =
547 rte_zmalloc("VF VLAN table",
550 if (bp->pf.vf_info[i].vlan_table == NULL)
552 "Fail to alloc VLAN table for VF %d\n",
556 bp->pf.vf_info[i].vlan_table);
557 bp->pf.vf_info[i].vlan_as_table =
558 rte_zmalloc("VF VLAN AS table",
561 if (bp->pf.vf_info[i].vlan_as_table == NULL)
563 "Alloc VLAN AS table for VF %d fail\n",
567 bp->pf.vf_info[i].vlan_as_table);
568 STAILQ_INIT(&bp->pf.vf_info[i].filter);
573 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
574 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
575 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
576 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
577 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
578 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
579 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
580 /* TODO: For now, do not support VMDq/RFS on VFs. */
585 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
589 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
591 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
592 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
593 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
594 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
596 bnxt_hwrm_ptp_qcfg(bp);
605 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
609 rc = __bnxt_hwrm_func_qcaps(bp);
610 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
611 rc = bnxt_hwrm_func_resc_qcaps(bp);
613 bp->flags |= BNXT_FLAG_NEW_RM;
619 int bnxt_hwrm_func_reset(struct bnxt *bp)
622 struct hwrm_func_reset_input req = {.req_type = 0 };
623 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
625 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
627 req.enables = rte_cpu_to_le_32(0);
629 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
637 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
640 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
641 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
643 if (bp->flags & BNXT_FLAG_REGISTERED)
646 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
647 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
648 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
649 req.ver_maj = RTE_VER_YEAR;
650 req.ver_min = RTE_VER_MONTH;
651 req.ver_upd = RTE_VER_MINOR;
654 req.enables |= rte_cpu_to_le_32(
655 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
656 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
657 RTE_MIN(sizeof(req.vf_req_fwd),
658 sizeof(bp->pf.vf_req_fwd)));
661 * PF can sniff HWRM API issued by VF. This can be set up by
662 * linux driver and inherited by the DPDK PF driver. Clear
663 * this HWRM sniffer list in FW because DPDK PF driver does
667 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
670 req.async_event_fwd[0] |=
671 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
672 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
673 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
674 req.async_event_fwd[1] |=
675 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
676 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
678 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
683 bp->flags |= BNXT_FLAG_REGISTERED;
688 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
690 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
693 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
696 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
701 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
702 struct hwrm_func_vf_cfg_input req = {0};
704 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
706 req.enables = rte_cpu_to_le_32
707 (HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
708 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
709 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
710 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
711 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS |
712 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS);
714 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
715 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
716 AGG_RING_MULTIPLIER);
717 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
718 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
720 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
721 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
722 if (bp->vf_resv_strategy ==
723 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
724 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
725 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
726 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
727 req.enables |= rte_cpu_to_le_32(enables);
728 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
729 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
730 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
734 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
735 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
736 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
737 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
738 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
739 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
741 req.flags = rte_cpu_to_le_32(flags);
743 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
746 HWRM_CHECK_RESULT_SILENT();
754 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
757 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
758 struct hwrm_func_resource_qcaps_input req = {0};
760 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
761 req.fid = rte_cpu_to_le_16(0xffff);
763 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
768 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
769 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
770 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
771 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
772 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
773 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
774 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
775 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
777 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
778 if (bp->vf_resv_strategy >
779 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
780 bp->vf_resv_strategy =
781 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
787 int bnxt_hwrm_ver_get(struct bnxt *bp)
790 struct hwrm_ver_get_input req = {.req_type = 0 };
791 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
793 uint16_t max_resp_len;
794 char type[RTE_MEMZONE_NAMESIZE];
795 uint32_t dev_caps_cfg;
797 bp->max_req_len = HWRM_MAX_REQ_LEN;
798 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
800 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
801 req.hwrm_intf_min = HWRM_VERSION_MINOR;
802 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
804 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
808 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
809 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
810 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
811 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
812 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
813 (resp->hwrm_fw_min_8b << 16) |
814 (resp->hwrm_fw_bld_8b << 8) |
815 resp->hwrm_fw_rsvd_8b;
816 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
817 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
819 fw_version = resp->hwrm_intf_maj_8b << 16;
820 fw_version |= resp->hwrm_intf_min_8b << 8;
821 fw_version |= resp->hwrm_intf_upd_8b;
822 bp->hwrm_spec_code = fw_version;
824 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
825 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
830 if (bp->max_req_len > resp->max_req_win_len) {
831 PMD_DRV_LOG(ERR, "Unsupported request length\n");
834 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
835 max_resp_len = resp->max_resp_len;
836 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
838 if (bp->max_resp_len != max_resp_len) {
839 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
840 bp->pdev->addr.domain, bp->pdev->addr.bus,
841 bp->pdev->addr.devid, bp->pdev->addr.function);
843 rte_free(bp->hwrm_cmd_resp_addr);
845 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
846 if (bp->hwrm_cmd_resp_addr == NULL) {
850 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
851 bp->hwrm_cmd_resp_dma_addr =
852 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
853 if (bp->hwrm_cmd_resp_dma_addr == 0) {
855 "Unable to map response buffer to physical memory.\n");
859 bp->max_resp_len = max_resp_len;
863 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
865 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
866 PMD_DRV_LOG(DEBUG, "Short command supported\n");
868 rte_free(bp->hwrm_short_cmd_req_addr);
870 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
872 if (bp->hwrm_short_cmd_req_addr == NULL) {
876 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
877 bp->hwrm_short_cmd_req_dma_addr =
878 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
879 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
880 rte_free(bp->hwrm_short_cmd_req_addr);
882 "Unable to map buffer to physical memory.\n");
887 bp->flags |= BNXT_FLAG_SHORT_CMD;
890 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
891 bp->flags |= BNXT_FLAG_KONG_MB_EN;
892 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
895 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
896 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
903 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
906 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
907 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
909 if (!(bp->flags & BNXT_FLAG_REGISTERED))
912 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
915 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
920 bp->flags &= ~BNXT_FLAG_REGISTERED;
925 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
928 struct hwrm_port_phy_cfg_input req = {0};
929 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
930 uint32_t enables = 0;
932 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
935 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
936 if (bp->link_info.auto_mode && conf->link_speed) {
937 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
938 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
941 req.flags = rte_cpu_to_le_32(conf->phy_flags);
942 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
943 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
945 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
946 * any auto mode, even "none".
948 if (!conf->link_speed) {
949 /* No speeds specified. Enable AutoNeg - all speeds */
951 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
953 /* AutoNeg - Advertise speeds specified. */
954 if (conf->auto_link_speed_mask &&
955 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
957 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
958 req.auto_link_speed_mask =
959 conf->auto_link_speed_mask;
961 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
964 req.auto_duplex = conf->duplex;
965 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
966 req.auto_pause = conf->auto_pause;
967 req.force_pause = conf->force_pause;
968 /* Set force_pause if there is no auto or if there is a force */
969 if (req.auto_pause && !req.force_pause)
970 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
972 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
974 req.enables = rte_cpu_to_le_32(enables);
977 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
978 PMD_DRV_LOG(INFO, "Force Link Down\n");
981 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
989 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
990 struct bnxt_link_info *link_info)
993 struct hwrm_port_phy_qcfg_input req = {0};
994 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
996 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
998 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1000 HWRM_CHECK_RESULT();
1002 link_info->phy_link_status = resp->link;
1003 link_info->link_up =
1004 (link_info->phy_link_status ==
1005 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1006 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1007 link_info->duplex = resp->duplex_cfg;
1008 link_info->pause = resp->pause;
1009 link_info->auto_pause = resp->auto_pause;
1010 link_info->force_pause = resp->force_pause;
1011 link_info->auto_mode = resp->auto_mode;
1012 link_info->phy_type = resp->phy_type;
1013 link_info->media_type = resp->media_type;
1015 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1016 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1017 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1018 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1019 link_info->phy_ver[0] = resp->phy_maj;
1020 link_info->phy_ver[1] = resp->phy_min;
1021 link_info->phy_ver[2] = resp->phy_bld;
1025 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1026 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1027 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1028 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1029 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1030 link_info->auto_link_speed_mask);
1031 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1032 link_info->force_link_speed);
1037 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1040 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1041 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1044 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1046 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1047 /* HWRM Version >= 1.9.1 */
1048 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1050 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1051 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1053 HWRM_CHECK_RESULT();
1055 #define GET_QUEUE_INFO(x) \
1056 bp->cos_queue[x].id = resp->queue_id##x; \
1057 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1070 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1071 bp->tx_cosq_id = bp->cos_queue[0].id;
1073 /* iterate and find the COSq profile to use for Tx */
1074 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1075 if (bp->cos_queue[i].profile ==
1076 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1077 bp->tx_cosq_id = bp->cos_queue[i].id;
1082 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1087 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1088 struct bnxt_ring *ring,
1089 uint32_t ring_type, uint32_t map_index,
1090 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1093 uint32_t enables = 0;
1094 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1095 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1097 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1099 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1100 req.fbo = rte_cpu_to_le_32(0);
1101 /* Association of ring index with doorbell index */
1102 req.logical_id = rte_cpu_to_le_16(map_index);
1103 req.length = rte_cpu_to_le_32(ring->ring_size);
1105 switch (ring_type) {
1106 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1107 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1109 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1110 req.ring_type = ring_type;
1111 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1112 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
1113 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1115 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1117 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1118 req.ring_type = ring_type;
1120 * TODO: Some HWRM versions crash with
1121 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
1123 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1126 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1131 req.enables = rte_cpu_to_le_32(enables);
1133 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1135 if (rc || resp->error_code) {
1136 if (rc == 0 && resp->error_code)
1137 rc = rte_le_to_cpu_16(resp->error_code);
1138 switch (ring_type) {
1139 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1141 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1144 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1146 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1149 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1151 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1155 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1161 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1166 int bnxt_hwrm_ring_free(struct bnxt *bp,
1167 struct bnxt_ring *ring, uint32_t ring_type)
1170 struct hwrm_ring_free_input req = {.req_type = 0 };
1171 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1173 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1175 req.ring_type = ring_type;
1176 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1178 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1180 if (rc || resp->error_code) {
1181 if (rc == 0 && resp->error_code)
1182 rc = rte_le_to_cpu_16(resp->error_code);
1185 switch (ring_type) {
1186 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1187 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1190 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1191 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1194 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1195 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1199 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1207 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1210 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1211 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1213 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1215 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1216 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1217 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1218 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1220 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1222 HWRM_CHECK_RESULT();
1224 bp->grp_info[idx].fw_grp_id =
1225 rte_le_to_cpu_16(resp->ring_group_id);
1232 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1235 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1236 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1238 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1240 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1242 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1244 HWRM_CHECK_RESULT();
1247 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1251 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1254 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1255 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1257 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1260 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1262 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1264 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1266 HWRM_CHECK_RESULT();
1272 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1273 unsigned int idx __rte_unused)
1276 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1277 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1279 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1281 req.update_period_ms = rte_cpu_to_le_32(0);
1283 req.stats_dma_addr =
1284 rte_cpu_to_le_64(cpr->hw_stats_map);
1286 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1288 HWRM_CHECK_RESULT();
1290 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1297 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1298 unsigned int idx __rte_unused)
1301 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1302 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1304 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1306 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1308 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1310 HWRM_CHECK_RESULT();
1316 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1319 struct hwrm_vnic_alloc_input req = { 0 };
1320 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1322 /* map ring groups to this vnic */
1323 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1324 vnic->start_grp_id, vnic->end_grp_id);
1325 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1326 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1328 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1329 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1330 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1331 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1332 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1333 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1334 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1336 if (vnic->func_default)
1338 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1339 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1341 HWRM_CHECK_RESULT();
1343 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1345 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1349 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1350 struct bnxt_vnic_info *vnic,
1351 struct bnxt_plcmodes_cfg *pmode)
1354 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1355 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1357 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1359 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1361 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1363 HWRM_CHECK_RESULT();
1365 pmode->flags = rte_le_to_cpu_32(resp->flags);
1366 /* dflt_vnic bit doesn't exist in the _cfg command */
1367 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1368 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1369 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1370 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1377 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1378 struct bnxt_vnic_info *vnic,
1379 struct bnxt_plcmodes_cfg *pmode)
1382 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1383 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1385 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1387 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1388 req.flags = rte_cpu_to_le_32(pmode->flags);
1389 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1390 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1391 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1392 req.enables = rte_cpu_to_le_32(
1393 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1394 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1395 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1398 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1400 HWRM_CHECK_RESULT();
1406 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1409 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1410 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1411 uint32_t ctx_enable_flag = 0;
1412 struct bnxt_plcmodes_cfg pmodes;
1414 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1415 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1419 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1423 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1425 /* Only RSS support for now TBD: COS & LB */
1427 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1428 if (vnic->lb_rule != 0xffff)
1429 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1430 if (vnic->cos_rule != 0xffff)
1431 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1432 if (vnic->rss_rule != 0xffff) {
1433 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1434 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1436 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1437 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1438 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1439 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1440 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1441 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1442 req.mru = rte_cpu_to_le_16(vnic->mru);
1443 /* Configure default VNIC only once. */
1444 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1446 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1447 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1449 if (vnic->vlan_strip)
1451 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1454 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1455 if (vnic->roce_dual)
1456 req.flags |= rte_cpu_to_le_32(
1457 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1458 if (vnic->roce_only)
1459 req.flags |= rte_cpu_to_le_32(
1460 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1461 if (vnic->rss_dflt_cr)
1462 req.flags |= rte_cpu_to_le_32(
1463 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1465 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1467 HWRM_CHECK_RESULT();
1470 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1475 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1479 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1480 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1482 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1483 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1486 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1489 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1490 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1491 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1493 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1495 HWRM_CHECK_RESULT();
1497 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1498 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1499 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1500 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1501 vnic->mru = rte_le_to_cpu_16(resp->mru);
1502 vnic->func_default = rte_le_to_cpu_32(
1503 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1504 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1505 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1506 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1507 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1508 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1509 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1510 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1511 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1512 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1513 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1520 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1523 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1524 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1525 bp->hwrm_cmd_resp_addr;
1527 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1529 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1531 HWRM_CHECK_RESULT();
1533 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1535 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1540 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1543 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1544 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1545 bp->hwrm_cmd_resp_addr;
1547 if (vnic->rss_rule == 0xffff) {
1548 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1551 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1553 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1555 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1557 HWRM_CHECK_RESULT();
1560 vnic->rss_rule = INVALID_HW_RING_ID;
1565 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1568 struct hwrm_vnic_free_input req = {.req_type = 0 };
1569 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1571 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1572 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1576 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1578 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1580 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1582 HWRM_CHECK_RESULT();
1585 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1586 /* Configure default VNIC again if necessary. */
1587 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1588 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1593 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1594 struct bnxt_vnic_info *vnic)
1597 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1598 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1600 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1602 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1603 req.hash_mode_flags = vnic->hash_mode;
1605 req.ring_grp_tbl_addr =
1606 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1607 req.hash_key_tbl_addr =
1608 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1609 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1610 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1612 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1614 HWRM_CHECK_RESULT();
1620 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1621 struct bnxt_vnic_info *vnic)
1624 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1625 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1628 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1629 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1633 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1635 req.flags = rte_cpu_to_le_32(
1636 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1638 req.enables = rte_cpu_to_le_32(
1639 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1641 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1642 size -= RTE_PKTMBUF_HEADROOM;
1644 req.jumbo_thresh = rte_cpu_to_le_16(size);
1645 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1647 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1649 HWRM_CHECK_RESULT();
1655 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1656 struct bnxt_vnic_info *vnic, bool enable)
1659 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1660 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1662 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1665 req.enables = rte_cpu_to_le_32(
1666 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1667 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1668 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1669 req.flags = rte_cpu_to_le_32(
1670 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1671 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1672 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1673 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1674 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1675 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1676 req.max_agg_segs = rte_cpu_to_le_16(5);
1678 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1679 req.min_agg_len = rte_cpu_to_le_32(512);
1681 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1683 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1685 HWRM_CHECK_RESULT();
1691 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1693 struct hwrm_func_cfg_input req = {0};
1694 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1697 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1698 req.enables = rte_cpu_to_le_32(
1699 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1700 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1701 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1703 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1705 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1706 HWRM_CHECK_RESULT();
1709 bp->pf.vf_info[vf].random_mac = false;
1714 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1718 struct hwrm_func_qstats_input req = {.req_type = 0};
1719 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1721 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1723 req.fid = rte_cpu_to_le_16(fid);
1725 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1727 HWRM_CHECK_RESULT();
1730 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1737 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1738 struct rte_eth_stats *stats)
1741 struct hwrm_func_qstats_input req = {.req_type = 0};
1742 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1744 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1746 req.fid = rte_cpu_to_le_16(fid);
1748 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1750 HWRM_CHECK_RESULT();
1752 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1753 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1754 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1755 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1756 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1757 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1759 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1760 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1761 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1762 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1763 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1764 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1766 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1767 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1768 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1775 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1778 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1779 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1781 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1783 req.fid = rte_cpu_to_le_16(fid);
1785 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1787 HWRM_CHECK_RESULT();
1794 * HWRM utility functions
1797 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1802 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1803 struct bnxt_tx_queue *txq;
1804 struct bnxt_rx_queue *rxq;
1805 struct bnxt_cp_ring_info *cpr;
1807 if (i >= bp->rx_cp_nr_rings) {
1808 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1811 rxq = bp->rx_queues[i];
1815 rc = bnxt_hwrm_stat_clear(bp, cpr);
1822 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1826 struct bnxt_cp_ring_info *cpr;
1828 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1830 if (i >= bp->rx_cp_nr_rings) {
1831 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1833 cpr = bp->rx_queues[i]->cp_ring;
1834 bp->grp_info[i].fw_stats_ctx = -1;
1836 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1837 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1838 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1846 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1851 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1852 struct bnxt_tx_queue *txq;
1853 struct bnxt_rx_queue *rxq;
1854 struct bnxt_cp_ring_info *cpr;
1856 if (i >= bp->rx_cp_nr_rings) {
1857 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1860 rxq = bp->rx_queues[i];
1864 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1872 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1877 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1879 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1882 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1890 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1892 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1894 bnxt_hwrm_ring_free(bp, cp_ring,
1895 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1896 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1897 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1898 sizeof(*cpr->cp_desc_ring));
1899 cpr->cp_raw_cons = 0;
1902 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
1904 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
1905 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1906 struct bnxt_ring *ring = rxr->rx_ring_struct;
1907 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1909 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1910 bnxt_hwrm_ring_free(bp, ring,
1911 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1912 ring->fw_ring_id = INVALID_HW_RING_ID;
1913 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
1914 memset(rxr->rx_desc_ring, 0,
1915 rxr->rx_ring_struct->ring_size *
1916 sizeof(*rxr->rx_desc_ring));
1917 memset(rxr->rx_buf_ring, 0,
1918 rxr->rx_ring_struct->ring_size *
1919 sizeof(*rxr->rx_buf_ring));
1922 ring = rxr->ag_ring_struct;
1923 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1924 bnxt_hwrm_ring_free(bp, ring,
1925 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1926 ring->fw_ring_id = INVALID_HW_RING_ID;
1927 memset(rxr->ag_buf_ring, 0,
1928 rxr->ag_ring_struct->ring_size *
1929 sizeof(*rxr->ag_buf_ring));
1931 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
1933 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1934 bnxt_free_cp_ring(bp, cpr);
1936 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
1939 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1943 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1944 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1945 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1946 struct bnxt_ring *ring = txr->tx_ring_struct;
1947 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1949 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1950 bnxt_hwrm_ring_free(bp, ring,
1951 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1952 ring->fw_ring_id = INVALID_HW_RING_ID;
1953 memset(txr->tx_desc_ring, 0,
1954 txr->tx_ring_struct->ring_size *
1955 sizeof(*txr->tx_desc_ring));
1956 memset(txr->tx_buf_ring, 0,
1957 txr->tx_ring_struct->ring_size *
1958 sizeof(*txr->tx_buf_ring));
1962 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1963 bnxt_free_cp_ring(bp, cpr);
1964 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1968 for (i = 0; i < bp->rx_cp_nr_rings; i++)
1969 bnxt_free_hwrm_rx_ring(bp, i);
1974 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1979 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1980 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1987 void bnxt_free_hwrm_resources(struct bnxt *bp)
1989 /* Release memzone */
1990 rte_free(bp->hwrm_cmd_resp_addr);
1991 rte_free(bp->hwrm_short_cmd_req_addr);
1992 bp->hwrm_cmd_resp_addr = NULL;
1993 bp->hwrm_short_cmd_req_addr = NULL;
1994 bp->hwrm_cmd_resp_dma_addr = 0;
1995 bp->hwrm_short_cmd_req_dma_addr = 0;
1998 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2000 struct rte_pci_device *pdev = bp->pdev;
2001 char type[RTE_MEMZONE_NAMESIZE];
2003 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2004 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2005 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2006 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2007 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2008 if (bp->hwrm_cmd_resp_addr == NULL)
2010 bp->hwrm_cmd_resp_dma_addr =
2011 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2012 if (bp->hwrm_cmd_resp_dma_addr == 0) {
2014 "unable to map response address to physical memory\n");
2017 rte_spinlock_init(&bp->hwrm_lock);
2022 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2024 struct bnxt_filter_info *filter;
2027 STAILQ_FOREACH(filter, &vnic->filter, next) {
2028 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2029 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2030 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2031 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2033 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2034 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2042 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2044 struct bnxt_filter_info *filter;
2045 struct rte_flow *flow;
2048 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2049 filter = flow->filter;
2050 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2051 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2052 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2053 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2054 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2056 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2058 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2066 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2068 struct bnxt_filter_info *filter;
2071 STAILQ_FOREACH(filter, &vnic->filter, next) {
2072 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2073 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2075 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2076 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2079 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2087 void bnxt_free_tunnel_ports(struct bnxt *bp)
2089 if (bp->vxlan_port_cnt)
2090 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2091 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2093 if (bp->geneve_port_cnt)
2094 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2095 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2096 bp->geneve_port = 0;
2099 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2103 if (bp->vnic_info == NULL)
2107 * Cleanup VNICs in reverse order, to make sure the L2 filter
2108 * from vnic0 is last to be cleaned up.
2110 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2111 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2113 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2115 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2117 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2119 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2121 bnxt_hwrm_vnic_free(bp, vnic);
2123 rte_free(vnic->fw_grp_ids);
2125 /* Ring resources */
2126 bnxt_free_all_hwrm_rings(bp);
2127 bnxt_free_all_hwrm_ring_grps(bp);
2128 bnxt_free_all_hwrm_stat_ctxs(bp);
2129 bnxt_free_tunnel_ports(bp);
2132 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2134 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2136 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2137 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2139 switch (conf_link_speed) {
2140 case ETH_LINK_SPEED_10M_HD:
2141 case ETH_LINK_SPEED_100M_HD:
2143 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2145 return hw_link_duplex;
2148 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2150 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2153 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2155 uint16_t eth_link_speed = 0;
2157 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2158 return ETH_LINK_SPEED_AUTONEG;
2160 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2161 case ETH_LINK_SPEED_100M:
2162 case ETH_LINK_SPEED_100M_HD:
2165 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2167 case ETH_LINK_SPEED_1G:
2169 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2171 case ETH_LINK_SPEED_2_5G:
2173 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2175 case ETH_LINK_SPEED_10G:
2177 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2179 case ETH_LINK_SPEED_20G:
2181 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2183 case ETH_LINK_SPEED_25G:
2185 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2187 case ETH_LINK_SPEED_40G:
2189 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2191 case ETH_LINK_SPEED_50G:
2193 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2195 case ETH_LINK_SPEED_100G:
2197 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2201 "Unsupported link speed %d; default to AUTO\n",
2205 return eth_link_speed;
2208 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2209 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2210 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2211 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2213 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2217 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2220 if (link_speed & ETH_LINK_SPEED_FIXED) {
2221 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2223 if (one_speed & (one_speed - 1)) {
2225 "Invalid advertised speeds (%u) for port %u\n",
2226 link_speed, port_id);
2229 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2231 "Unsupported advertised speed (%u) for port %u\n",
2232 link_speed, port_id);
2236 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2238 "Unsupported advertised speeds (%u) for port %u\n",
2239 link_speed, port_id);
2247 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2251 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2252 if (bp->link_info.support_speeds)
2253 return bp->link_info.support_speeds;
2254 link_speed = BNXT_SUPPORTED_SPEEDS;
2257 if (link_speed & ETH_LINK_SPEED_100M)
2258 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2259 if (link_speed & ETH_LINK_SPEED_100M_HD)
2260 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2261 if (link_speed & ETH_LINK_SPEED_1G)
2262 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2263 if (link_speed & ETH_LINK_SPEED_2_5G)
2264 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2265 if (link_speed & ETH_LINK_SPEED_10G)
2266 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2267 if (link_speed & ETH_LINK_SPEED_20G)
2268 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2269 if (link_speed & ETH_LINK_SPEED_25G)
2270 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2271 if (link_speed & ETH_LINK_SPEED_40G)
2272 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2273 if (link_speed & ETH_LINK_SPEED_50G)
2274 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2275 if (link_speed & ETH_LINK_SPEED_100G)
2276 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2280 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2282 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2284 switch (hw_link_speed) {
2285 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2286 eth_link_speed = ETH_SPEED_NUM_100M;
2288 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2289 eth_link_speed = ETH_SPEED_NUM_1G;
2291 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2292 eth_link_speed = ETH_SPEED_NUM_2_5G;
2294 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2295 eth_link_speed = ETH_SPEED_NUM_10G;
2297 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2298 eth_link_speed = ETH_SPEED_NUM_20G;
2300 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2301 eth_link_speed = ETH_SPEED_NUM_25G;
2303 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2304 eth_link_speed = ETH_SPEED_NUM_40G;
2306 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2307 eth_link_speed = ETH_SPEED_NUM_50G;
2309 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2310 eth_link_speed = ETH_SPEED_NUM_100G;
2312 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2314 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2318 return eth_link_speed;
2321 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2323 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2325 switch (hw_link_duplex) {
2326 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2327 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2329 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2331 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2332 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2335 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2339 return eth_link_duplex;
2342 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2345 struct bnxt_link_info *link_info = &bp->link_info;
2347 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2350 "Get link config failed with rc %d\n", rc);
2353 if (link_info->link_speed)
2355 bnxt_parse_hw_link_speed(link_info->link_speed);
2357 link->link_speed = ETH_SPEED_NUM_NONE;
2358 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2359 link->link_status = link_info->link_up;
2360 link->link_autoneg = link_info->auto_mode ==
2361 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2362 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2367 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2370 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2371 struct bnxt_link_info link_req;
2372 uint16_t speed, autoneg;
2374 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2377 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2378 bp->eth_dev->data->port_id);
2382 memset(&link_req, 0, sizeof(link_req));
2383 link_req.link_up = link_up;
2387 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2388 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2389 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2390 /* Autoneg can be done only when the FW allows */
2391 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2392 bp->link_info.force_link_speed)) {
2393 link_req.phy_flags |=
2394 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2395 link_req.auto_link_speed_mask =
2396 bnxt_parse_eth_link_speed_mask(bp,
2397 dev_conf->link_speeds);
2399 if (bp->link_info.phy_type ==
2400 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2401 bp->link_info.phy_type ==
2402 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2403 bp->link_info.media_type ==
2404 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2405 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2409 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2410 /* If user wants a particular speed try that first. */
2412 link_req.link_speed = speed;
2413 else if (bp->link_info.force_link_speed)
2414 link_req.link_speed = bp->link_info.force_link_speed;
2416 link_req.link_speed = bp->link_info.auto_link_speed;
2418 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2419 link_req.auto_pause = bp->link_info.auto_pause;
2420 link_req.force_pause = bp->link_info.force_pause;
2423 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2426 "Set link config failed with rc %d\n", rc);
2434 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2436 struct hwrm_func_qcfg_input req = {0};
2437 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2441 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2442 req.fid = rte_cpu_to_le_16(0xffff);
2444 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2446 HWRM_CHECK_RESULT();
2448 /* Hard Coded.. 0xfff VLAN ID mask */
2449 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2450 flags = rte_le_to_cpu_16(resp->flags);
2451 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2452 bp->flags |= BNXT_FLAG_MULTI_HOST;
2454 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2455 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2456 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2459 switch (resp->port_partition_type) {
2460 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2461 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2462 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2464 bp->port_partition_type = resp->port_partition_type;
2467 bp->port_partition_type = 0;
2476 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2477 struct hwrm_func_qcaps_output *qcaps)
2479 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2480 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2481 sizeof(qcaps->mac_address));
2482 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2483 qcaps->max_rx_rings = fcfg->num_rx_rings;
2484 qcaps->max_tx_rings = fcfg->num_tx_rings;
2485 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2486 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2488 qcaps->first_vf_id = 0;
2489 qcaps->max_vnics = fcfg->num_vnics;
2490 qcaps->max_decap_records = 0;
2491 qcaps->max_encap_records = 0;
2492 qcaps->max_tx_wm_flows = 0;
2493 qcaps->max_tx_em_flows = 0;
2494 qcaps->max_rx_wm_flows = 0;
2495 qcaps->max_rx_em_flows = 0;
2496 qcaps->max_flow_id = 0;
2497 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2498 qcaps->max_sp_tx_rings = 0;
2499 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2502 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2504 struct hwrm_func_cfg_input req = {0};
2505 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2508 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2509 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2510 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2511 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2512 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2513 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2514 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2515 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2516 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2517 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2518 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2519 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2520 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2521 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2523 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2524 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2525 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2526 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2527 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2528 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2529 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2530 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2531 req.fid = rte_cpu_to_le_16(0xffff);
2533 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2535 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2537 HWRM_CHECK_RESULT();
2543 static void populate_vf_func_cfg_req(struct bnxt *bp,
2544 struct hwrm_func_cfg_input *req,
2547 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2548 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2549 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2550 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2551 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2552 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2553 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2554 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2555 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2556 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2558 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2559 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2561 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2562 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2564 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2566 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2567 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2569 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2570 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2571 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2572 /* TODO: For now, do not support VMDq/RFS on VFs. */
2573 req->num_vnics = rte_cpu_to_le_16(1);
2574 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2578 static void add_random_mac_if_needed(struct bnxt *bp,
2579 struct hwrm_func_cfg_input *cfg_req,
2582 struct rte_ether_addr mac;
2584 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2587 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2589 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2590 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2591 bp->pf.vf_info[vf].random_mac = true;
2593 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2594 RTE_ETHER_ADDR_LEN);
2598 static void reserve_resources_from_vf(struct bnxt *bp,
2599 struct hwrm_func_cfg_input *cfg_req,
2602 struct hwrm_func_qcaps_input req = {0};
2603 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2606 /* Get the actual allocated values now */
2607 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2608 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2609 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2612 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2613 copy_func_cfg_to_qcaps(cfg_req, resp);
2614 } else if (resp->error_code) {
2615 rc = rte_le_to_cpu_16(resp->error_code);
2616 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2617 copy_func_cfg_to_qcaps(cfg_req, resp);
2620 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2621 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2622 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2623 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2624 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2625 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2627 * TODO: While not supporting VMDq with VFs, max_vnics is always
2628 * forced to 1 in this case
2630 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2631 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2636 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2638 struct hwrm_func_qcfg_input req = {0};
2639 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2642 /* Check for zero MAC address */
2643 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2644 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2645 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2647 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2649 } else if (resp->error_code) {
2650 rc = rte_le_to_cpu_16(resp->error_code);
2651 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2654 rc = rte_le_to_cpu_16(resp->vlan);
2661 static int update_pf_resource_max(struct bnxt *bp)
2663 struct hwrm_func_qcfg_input req = {0};
2664 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2667 /* And copy the allocated numbers into the pf struct */
2668 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2669 req.fid = rte_cpu_to_le_16(0xffff);
2670 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2671 HWRM_CHECK_RESULT();
2673 /* Only TX ring value reflects actual allocation? TODO */
2674 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2675 bp->pf.evb_mode = resp->evb_mode;
2682 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2687 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2691 rc = bnxt_hwrm_func_qcaps(bp);
2695 bp->pf.func_cfg_flags &=
2696 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2697 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2698 bp->pf.func_cfg_flags |=
2699 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2700 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2704 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2706 struct hwrm_func_cfg_input req = {0};
2707 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2714 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2718 rc = bnxt_hwrm_func_qcaps(bp);
2723 bp->pf.active_vfs = num_vfs;
2726 * First, configure the PF to only use one TX ring. This ensures that
2727 * there are enough rings for all VFs.
2729 * If we don't do this, when we call func_alloc() later, we will lock
2730 * extra rings to the PF that won't be available during func_cfg() of
2733 * This has been fixed with firmware versions above 20.6.54
2735 bp->pf.func_cfg_flags &=
2736 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2737 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2738 bp->pf.func_cfg_flags |=
2739 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2740 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2745 * Now, create and register a buffer to hold forwarded VF requests
2747 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2748 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2749 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2750 if (bp->pf.vf_req_buf == NULL) {
2754 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2755 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2756 for (i = 0; i < num_vfs; i++)
2757 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2758 (i * HWRM_MAX_REQ_LEN);
2760 rc = bnxt_hwrm_func_buf_rgtr(bp);
2764 populate_vf_func_cfg_req(bp, &req, num_vfs);
2766 bp->pf.active_vfs = 0;
2767 for (i = 0; i < num_vfs; i++) {
2768 add_random_mac_if_needed(bp, &req, i);
2770 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2771 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2772 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2773 rc = bnxt_hwrm_send_message(bp,
2778 /* Clear enable flag for next pass */
2779 req.enables &= ~rte_cpu_to_le_32(
2780 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2782 if (rc || resp->error_code) {
2784 "Failed to initizlie VF %d\n", i);
2786 "Not all VFs available. (%d, %d)\n",
2787 rc, resp->error_code);
2794 reserve_resources_from_vf(bp, &req, i);
2795 bp->pf.active_vfs++;
2796 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2800 * Now configure the PF to use "the rest" of the resources
2801 * We're using STD_TX_RING_MODE here though which will limit the TX
2802 * rings. This will allow QoS to function properly. Not setting this
2803 * will cause PF rings to break bandwidth settings.
2805 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2809 rc = update_pf_resource_max(bp);
2816 bnxt_hwrm_func_buf_unrgtr(bp);
2820 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2822 struct hwrm_func_cfg_input req = {0};
2823 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2826 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2828 req.fid = rte_cpu_to_le_16(0xffff);
2829 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2830 req.evb_mode = bp->pf.evb_mode;
2832 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2833 HWRM_CHECK_RESULT();
2839 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2840 uint8_t tunnel_type)
2842 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2843 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2846 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
2847 req.tunnel_type = tunnel_type;
2848 req.tunnel_dst_port_val = port;
2849 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2850 HWRM_CHECK_RESULT();
2852 switch (tunnel_type) {
2853 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2854 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2855 bp->vxlan_port = port;
2857 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2858 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2859 bp->geneve_port = port;
2870 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2871 uint8_t tunnel_type)
2873 struct hwrm_tunnel_dst_port_free_input req = {0};
2874 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2877 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
2879 req.tunnel_type = tunnel_type;
2880 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2881 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2883 HWRM_CHECK_RESULT();
2889 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2892 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2893 struct hwrm_func_cfg_input req = {0};
2896 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2898 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2899 req.flags = rte_cpu_to_le_32(flags);
2900 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2902 HWRM_CHECK_RESULT();
2908 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2910 uint32_t *flag = flagp;
2912 vnic->flags = *flag;
2915 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2917 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2920 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2923 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2924 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2926 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
2928 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2929 req.req_buf_page_size = rte_cpu_to_le_16(
2930 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2931 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2932 req.req_buf_page_addr0 =
2933 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2934 if (req.req_buf_page_addr0 == 0) {
2936 "unable to map buffer address to physical memory\n");
2940 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2942 HWRM_CHECK_RESULT();
2948 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2951 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2952 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2954 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
2956 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2958 HWRM_CHECK_RESULT();
2964 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2966 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2967 struct hwrm_func_cfg_input req = {0};
2970 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2972 req.fid = rte_cpu_to_le_16(0xffff);
2973 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2974 req.enables = rte_cpu_to_le_32(
2975 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2976 req.async_event_cr = rte_cpu_to_le_16(
2977 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2978 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2980 HWRM_CHECK_RESULT();
2986 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2988 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2989 struct hwrm_func_vf_cfg_input req = {0};
2992 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
2994 req.enables = rte_cpu_to_le_32(
2995 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2996 req.async_event_cr = rte_cpu_to_le_16(
2997 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2998 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3000 HWRM_CHECK_RESULT();
3006 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3008 struct hwrm_func_cfg_input req = {0};
3009 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3010 uint16_t dflt_vlan, fid;
3011 uint32_t func_cfg_flags;
3014 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3017 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3018 fid = bp->pf.vf_info[vf].fid;
3019 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3021 fid = rte_cpu_to_le_16(0xffff);
3022 func_cfg_flags = bp->pf.func_cfg_flags;
3023 dflt_vlan = bp->vlan;
3026 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3027 req.fid = rte_cpu_to_le_16(fid);
3028 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3029 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3031 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3033 HWRM_CHECK_RESULT();
3039 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3040 uint16_t max_bw, uint16_t enables)
3042 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3043 struct hwrm_func_cfg_input req = {0};
3046 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3048 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3049 req.enables |= rte_cpu_to_le_32(enables);
3050 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3051 req.max_bw = rte_cpu_to_le_32(max_bw);
3052 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3054 HWRM_CHECK_RESULT();
3060 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3062 struct hwrm_func_cfg_input req = {0};
3063 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3066 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3068 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3069 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3070 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3071 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3073 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3075 HWRM_CHECK_RESULT();
3081 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3086 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3088 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3093 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3094 void *encaped, size_t ec_size)
3097 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3098 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3100 if (ec_size > sizeof(req.encap_request))
3103 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3105 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3106 memcpy(req.encap_request, encaped, ec_size);
3108 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3110 HWRM_CHECK_RESULT();
3116 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3117 struct rte_ether_addr *mac)
3119 struct hwrm_func_qcfg_input req = {0};
3120 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3123 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3125 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3126 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3128 HWRM_CHECK_RESULT();
3130 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3137 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3138 void *encaped, size_t ec_size)
3141 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3142 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3144 if (ec_size > sizeof(req.encap_request))
3147 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3149 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3150 memcpy(req.encap_request, encaped, ec_size);
3152 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3154 HWRM_CHECK_RESULT();
3160 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3161 struct rte_eth_stats *stats, uint8_t rx)
3164 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3165 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3167 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3169 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3171 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3173 HWRM_CHECK_RESULT();
3176 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3177 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3178 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3179 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3180 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3181 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3182 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3183 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3185 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3186 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3187 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3188 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3189 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3190 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3199 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3201 struct hwrm_port_qstats_input req = {0};
3202 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3203 struct bnxt_pf_info *pf = &bp->pf;
3206 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3208 req.port_id = rte_cpu_to_le_16(pf->port_id);
3209 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3210 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3211 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3213 HWRM_CHECK_RESULT();
3219 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3221 struct hwrm_port_clr_stats_input req = {0};
3222 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3223 struct bnxt_pf_info *pf = &bp->pf;
3226 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3227 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3228 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3231 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3233 req.port_id = rte_cpu_to_le_16(pf->port_id);
3234 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3236 HWRM_CHECK_RESULT();
3242 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3244 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3245 struct hwrm_port_led_qcaps_input req = {0};
3251 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3252 req.port_id = bp->pf.port_id;
3253 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3255 HWRM_CHECK_RESULT();
3257 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3260 bp->num_leds = resp->num_leds;
3261 memcpy(bp->leds, &resp->led0_id,
3262 sizeof(bp->leds[0]) * bp->num_leds);
3263 for (i = 0; i < bp->num_leds; i++) {
3264 struct bnxt_led_info *led = &bp->leds[i];
3266 uint16_t caps = led->led_state_caps;
3268 if (!led->led_group_id ||
3269 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3281 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3283 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3284 struct hwrm_port_led_cfg_input req = {0};
3285 struct bnxt_led_cfg *led_cfg;
3286 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3287 uint16_t duration = 0;
3290 if (!bp->num_leds || BNXT_VF(bp))
3293 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3296 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3297 duration = rte_cpu_to_le_16(500);
3299 req.port_id = bp->pf.port_id;
3300 req.num_leds = bp->num_leds;
3301 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3302 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3303 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3304 led_cfg->led_id = bp->leds[i].led_id;
3305 led_cfg->led_state = led_state;
3306 led_cfg->led_blink_on = duration;
3307 led_cfg->led_blink_off = duration;
3308 led_cfg->led_group_id = bp->leds[i].led_group_id;
3311 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3313 HWRM_CHECK_RESULT();
3319 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3323 struct hwrm_nvm_get_dir_info_input req = {0};
3324 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3326 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3328 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3330 HWRM_CHECK_RESULT();
3334 *entries = rte_le_to_cpu_32(resp->entries);
3335 *length = rte_le_to_cpu_32(resp->entry_length);
3340 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3343 uint32_t dir_entries;
3344 uint32_t entry_length;
3347 rte_iova_t dma_handle;
3348 struct hwrm_nvm_get_dir_entries_input req = {0};
3349 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3351 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3355 *data++ = dir_entries;
3356 *data++ = entry_length;
3358 memset(data, 0xff, len);
3360 buflen = dir_entries * entry_length;
3361 buf = rte_malloc("nvm_dir", buflen, 0);
3362 rte_mem_lock_page(buf);
3365 dma_handle = rte_mem_virt2iova(buf);
3366 if (dma_handle == 0) {
3368 "unable to map response address to physical memory\n");
3371 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3372 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3373 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3376 memcpy(data, buf, len > buflen ? buflen : len);
3379 HWRM_CHECK_RESULT();
3385 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3386 uint32_t offset, uint32_t length,
3391 rte_iova_t dma_handle;
3392 struct hwrm_nvm_read_input req = {0};
3393 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3395 buf = rte_malloc("nvm_item", length, 0);
3396 rte_mem_lock_page(buf);
3400 dma_handle = rte_mem_virt2iova(buf);
3401 if (dma_handle == 0) {
3403 "unable to map response address to physical memory\n");
3406 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3407 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3408 req.dir_idx = rte_cpu_to_le_16(index);
3409 req.offset = rte_cpu_to_le_32(offset);
3410 req.len = rte_cpu_to_le_32(length);
3411 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3413 memcpy(data, buf, length);
3416 HWRM_CHECK_RESULT();
3422 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3425 struct hwrm_nvm_erase_dir_entry_input req = {0};
3426 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3428 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3429 req.dir_idx = rte_cpu_to_le_16(index);
3430 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3431 HWRM_CHECK_RESULT();
3438 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3439 uint16_t dir_ordinal, uint16_t dir_ext,
3440 uint16_t dir_attr, const uint8_t *data,
3444 struct hwrm_nvm_write_input req = {0};
3445 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3446 rte_iova_t dma_handle;
3449 buf = rte_malloc("nvm_write", data_len, 0);
3450 rte_mem_lock_page(buf);
3454 dma_handle = rte_mem_virt2iova(buf);
3455 if (dma_handle == 0) {
3457 "unable to map response address to physical memory\n");
3460 memcpy(buf, data, data_len);
3462 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3464 req.dir_type = rte_cpu_to_le_16(dir_type);
3465 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3466 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3467 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3468 req.dir_data_length = rte_cpu_to_le_32(data_len);
3469 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3471 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3474 HWRM_CHECK_RESULT();
3481 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3483 uint32_t *count = cbdata;
3485 *count = *count + 1;
3488 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3489 struct bnxt_vnic_info *vnic __rte_unused)
3494 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3498 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3499 &count, bnxt_vnic_count_hwrm_stub);
3504 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3507 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3508 struct hwrm_func_vf_vnic_ids_query_output *resp =
3509 bp->hwrm_cmd_resp_addr;
3512 /* First query all VNIC ids */
3513 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3515 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3516 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3517 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3519 if (req.vnic_id_tbl_addr == 0) {
3522 "unable to map VNIC ID table address to physical memory\n");
3525 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3528 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3530 } else if (resp->error_code) {
3531 rc = rte_le_to_cpu_16(resp->error_code);
3533 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3536 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3544 * This function queries the VNIC IDs for a specified VF. It then calls
3545 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3546 * Then it calls the hwrm_cb function to program this new vnic configuration.
3548 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3549 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3550 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3552 struct bnxt_vnic_info vnic;
3554 int i, num_vnic_ids;
3559 /* First query all VNIC ids */
3560 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3561 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3562 RTE_CACHE_LINE_SIZE);
3563 if (vnic_ids == NULL) {
3567 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3568 rte_mem_lock_page(((char *)vnic_ids) + sz);
3570 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3572 if (num_vnic_ids < 0)
3573 return num_vnic_ids;
3575 /* Retrieve VNIC, update bd_stall then update */
3577 for (i = 0; i < num_vnic_ids; i++) {
3578 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3579 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3580 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3583 if (vnic.mru <= 4) /* Indicates unallocated */
3586 vnic_cb(&vnic, cbdata);
3588 rc = hwrm_cb(bp, &vnic);
3598 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3601 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3602 struct hwrm_func_cfg_input req = {0};
3605 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3607 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3608 req.enables |= rte_cpu_to_le_32(
3609 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3610 req.vlan_antispoof_mode = on ?
3611 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3612 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3613 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3615 HWRM_CHECK_RESULT();
3621 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3623 struct bnxt_vnic_info vnic;
3626 int num_vnic_ids, i;
3630 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3631 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3632 RTE_CACHE_LINE_SIZE);
3633 if (vnic_ids == NULL) {
3638 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3639 rte_mem_lock_page(((char *)vnic_ids) + sz);
3641 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3647 * Loop through to find the default VNIC ID.
3648 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3649 * by sending the hwrm_func_qcfg command to the firmware.
3651 for (i = 0; i < num_vnic_ids; i++) {
3652 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3653 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3654 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3655 bp->pf.first_vf_id + vf);
3658 if (vnic.func_default) {
3660 return vnic.fw_vnic_id;
3663 /* Could not find a default VNIC. */
3664 PMD_DRV_LOG(ERR, "No default VNIC\n");
3670 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3672 struct bnxt_filter_info *filter)
3675 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3676 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3677 uint32_t enables = 0;
3679 if (filter->fw_em_filter_id != UINT64_MAX)
3680 bnxt_hwrm_clear_em_filter(bp, filter);
3682 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3684 req.flags = rte_cpu_to_le_32(filter->flags);
3686 enables = filter->enables |
3687 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3688 req.dst_id = rte_cpu_to_le_16(dst_id);
3690 if (filter->ip_addr_type) {
3691 req.ip_addr_type = filter->ip_addr_type;
3692 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3695 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3696 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3698 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3699 memcpy(req.src_macaddr, filter->src_macaddr,
3700 RTE_ETHER_ADDR_LEN);
3702 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3703 memcpy(req.dst_macaddr, filter->dst_macaddr,
3704 RTE_ETHER_ADDR_LEN);
3706 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3707 req.ovlan_vid = filter->l2_ovlan;
3709 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3710 req.ivlan_vid = filter->l2_ivlan;
3712 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3713 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3715 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3716 req.ip_protocol = filter->ip_protocol;
3718 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3719 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3721 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3722 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3724 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3725 req.src_port = rte_cpu_to_be_16(filter->src_port);
3727 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3728 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3730 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3731 req.mirror_vnic_id = filter->mirror_vnic_id;
3733 req.enables = rte_cpu_to_le_32(enables);
3735 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3737 HWRM_CHECK_RESULT();
3739 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3745 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3748 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3749 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3751 if (filter->fw_em_filter_id == UINT64_MAX)
3754 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3755 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3757 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3759 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3761 HWRM_CHECK_RESULT();
3764 filter->fw_em_filter_id = UINT64_MAX;
3765 filter->fw_l2_filter_id = UINT64_MAX;
3770 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3772 struct bnxt_filter_info *filter)
3775 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3776 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3777 bp->hwrm_cmd_resp_addr;
3778 uint32_t enables = 0;
3780 if (filter->fw_ntuple_filter_id != UINT64_MAX)
3781 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3783 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
3785 req.flags = rte_cpu_to_le_32(filter->flags);
3787 enables = filter->enables |
3788 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3789 req.dst_id = rte_cpu_to_le_16(dst_id);
3792 if (filter->ip_addr_type) {
3793 req.ip_addr_type = filter->ip_addr_type;
3795 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3798 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3799 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3801 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3802 memcpy(req.src_macaddr, filter->src_macaddr,
3803 RTE_ETHER_ADDR_LEN);
3805 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3806 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3807 //RTE_ETHER_ADDR_LEN);
3809 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3810 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3812 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3813 req.ip_protocol = filter->ip_protocol;
3815 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3816 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3818 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3819 req.src_ipaddr_mask[0] =
3820 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3822 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3823 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3825 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3826 req.dst_ipaddr_mask[0] =
3827 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3829 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3830 req.src_port = rte_cpu_to_le_16(filter->src_port);
3832 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3833 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3835 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3836 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3838 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3839 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3841 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3842 req.mirror_vnic_id = filter->mirror_vnic_id;
3844 req.enables = rte_cpu_to_le_32(enables);
3846 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3848 HWRM_CHECK_RESULT();
3850 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3856 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3857 struct bnxt_filter_info *filter)
3860 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3861 struct hwrm_cfa_ntuple_filter_free_output *resp =
3862 bp->hwrm_cmd_resp_addr;
3864 if (filter->fw_ntuple_filter_id == UINT64_MAX)
3867 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
3869 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3871 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3873 HWRM_CHECK_RESULT();
3876 filter->fw_ntuple_filter_id = UINT64_MAX;
3881 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3883 unsigned int rss_idx, fw_idx, i;
3885 if (vnic->rss_table && vnic->hash_type) {
3887 * Fill the RSS hash & redirection table with
3888 * ring group ids for all VNICs
3890 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
3891 rss_idx++, fw_idx++) {
3892 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
3893 fw_idx %= bp->rx_cp_nr_rings;
3894 if (vnic->fw_grp_ids[fw_idx] !=
3899 if (i == bp->rx_cp_nr_rings)
3901 vnic->rss_table[rss_idx] =
3902 vnic->fw_grp_ids[fw_idx];
3904 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
3909 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
3910 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3914 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
3916 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
3917 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
3919 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
3920 req->num_cmpl_dma_aggr_during_int =
3921 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
3923 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
3925 /* min timer set to 1/2 of interrupt timer */
3926 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
3928 /* buf timer set to 1/4 of interrupt timer */
3929 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
3931 req->cmpl_aggr_dma_tmr_during_int =
3932 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
3934 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
3935 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
3936 req->flags = rte_cpu_to_le_16(flags);
3939 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
3940 struct bnxt_coal *coal, uint16_t ring_id)
3942 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
3943 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
3944 bp->hwrm_cmd_resp_addr;
3947 /* Set ring coalesce parameters only for Stratus 100G NIC */
3948 if (!bnxt_stratus_device(bp))
3951 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
3952 bnxt_hwrm_set_coal_params(coal, &req);
3953 req.ring_id = rte_cpu_to_le_16(ring_id);
3954 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3955 HWRM_CHECK_RESULT();
3960 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
3962 struct hwrm_port_qstats_ext_input req = {0};
3963 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
3964 struct bnxt_pf_info *pf = &bp->pf;
3967 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
3968 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
3971 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
3973 req.port_id = rte_cpu_to_le_16(pf->port_id);
3974 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
3975 req.tx_stat_host_addr =
3976 rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3978 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
3980 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
3981 req.rx_stat_host_addr =
3982 rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3984 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
3986 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3989 bp->fw_rx_port_stats_ext_size = 0;
3990 bp->fw_tx_port_stats_ext_size = 0;
3992 bp->fw_rx_port_stats_ext_size =
3993 rte_le_to_cpu_16(resp->rx_stat_size);
3994 bp->fw_tx_port_stats_ext_size =
3995 rte_le_to_cpu_16(resp->tx_stat_size);
3998 HWRM_CHECK_RESULT();