1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SHORT_CMD_TIMEOUT 50000
31 #define HWRM_SPEC_CODE_1_8_3 0x10803
32 #define HWRM_VERSION_1_9_1 0x10901
33 #define HWRM_VERSION_1_9_2 0x10903
35 struct bnxt_plcmodes_cfg {
37 uint16_t jumbo_thresh;
39 uint16_t hds_threshold;
42 static int page_getenum(size_t size)
58 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
59 return sizeof(void *) * 8 - 1;
62 static int page_roundup(size_t size)
64 return 1 << page_getenum(size);
67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
71 if (rmem->nr_pages > 1) {
73 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
75 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
80 * HWRM Functions (sent to HWRM)
81 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
82 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
83 * command was failed by the ChiMP.
86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
87 uint32_t msg_len, bool use_kong_mb)
90 struct input *req = msg;
91 struct output *resp = bp->hwrm_cmd_resp_addr;
95 uint16_t max_req_len = bp->max_req_len;
96 struct hwrm_short_input short_input = { 0 };
97 uint16_t bar_offset = use_kong_mb ?
98 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
99 uint16_t mb_trigger_offset = use_kong_mb ?
100 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
103 /* Do not send HWRM commands to firmware in error state */
104 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
107 /* For VER_GET command, set timeout as 50ms */
108 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
109 timeout = HWRM_SHORT_CMD_TIMEOUT;
111 timeout = HWRM_CMD_TIMEOUT;
113 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
114 msg_len > bp->max_req_len) {
115 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
117 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
118 memcpy(short_cmd_req, req, msg_len);
120 short_input.req_type = rte_cpu_to_le_16(req->req_type);
121 short_input.signature = rte_cpu_to_le_16(
122 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
123 short_input.size = rte_cpu_to_le_16(msg_len);
124 short_input.req_addr =
125 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
127 data = (uint32_t *)&short_input;
128 msg_len = sizeof(short_input);
130 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
133 /* Write request msg to hwrm channel */
134 for (i = 0; i < msg_len; i += 4) {
135 bar = (uint8_t *)bp->bar0 + bar_offset + i;
136 rte_write32(*data, bar);
140 /* Zero the rest of the request space */
141 for (; i < max_req_len; i += 4) {
142 bar = (uint8_t *)bp->bar0 + bar_offset + i;
146 /* Ring channel doorbell */
147 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
150 * Make sure the channel doorbell ring command complete before
151 * reading the response to avoid getting stale or invalid
156 /* Poll for the valid bit */
157 for (i = 0; i < timeout; i++) {
158 /* Sanity check on the resp->resp_len */
160 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
161 /* Last byte of resp contains the valid key */
162 valid = (uint8_t *)resp + resp->resp_len - 1;
163 if (*valid == HWRM_RESP_VALID_KEY)
170 /* Suppress VER_GET timeout messages during reset recovery */
171 if (bp->flags & BNXT_FLAG_FW_RESET &&
172 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
175 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
183 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
184 * spinlock, and does initial processing.
186 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
187 * releases the spinlock only if it returns. If the regular int return codes
188 * are not used by the function, HWRM_CHECK_RESULT() should not be used
189 * directly, rather it should be copied and modified to suit the function.
191 * HWRM_UNLOCK() must be called after all response processing is completed.
193 #define HWRM_PREP(req, type, kong) do { \
194 rte_spinlock_lock(&bp->hwrm_lock); \
195 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
196 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
197 req.cmpl_ring = rte_cpu_to_le_16(-1); \
198 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
199 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
200 req.target_id = rte_cpu_to_le_16(0xffff); \
201 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
204 #define HWRM_CHECK_RESULT_SILENT() do {\
206 rte_spinlock_unlock(&bp->hwrm_lock); \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 rte_spinlock_unlock(&bp->hwrm_lock); \
216 #define HWRM_CHECK_RESULT() do {\
218 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
219 rte_spinlock_unlock(&bp->hwrm_lock); \
220 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
222 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
224 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
226 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
232 if (resp->error_code) { \
233 rc = rte_le_to_cpu_16(resp->error_code); \
234 if (resp->resp_len >= 16) { \
235 struct hwrm_err_output *tmp_hwrm_err_op = \
238 "error %d:%d:%08x:%04x\n", \
239 rc, tmp_hwrm_err_op->cmd_err, \
241 tmp_hwrm_err_op->opaque_0), \
243 tmp_hwrm_err_op->opaque_1)); \
245 PMD_DRV_LOG(ERR, "error %d\n", rc); \
247 rte_spinlock_unlock(&bp->hwrm_lock); \
248 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
250 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
252 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
254 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
262 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
264 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
267 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
268 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
270 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
271 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
274 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
282 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
283 struct bnxt_vnic_info *vnic,
285 struct bnxt_vlan_table_entry *vlan_table)
288 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
289 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
292 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
295 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
296 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
298 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
299 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
300 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
301 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
303 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
304 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
306 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
307 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
308 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
309 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
310 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
311 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
314 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
315 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
316 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
317 rte_mem_virt2iova(vlan_table));
318 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
320 req.mask = rte_cpu_to_le_32(mask);
322 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
330 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
332 struct bnxt_vlan_antispoof_table_entry *vlan_table)
335 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
336 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
337 bp->hwrm_cmd_resp_addr;
340 * Older HWRM versions did not support this command, and the set_rx_mask
341 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
342 * removed from set_rx_mask call, and this command was added.
344 * This command is also present from 1.7.8.11 and higher,
347 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
348 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
349 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
354 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
355 req.fid = rte_cpu_to_le_16(fid);
357 req.vlan_tag_mask_tbl_addr =
358 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
359 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
361 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
369 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
370 struct bnxt_filter_info *filter)
373 struct bnxt_filter_info *l2_filter = filter;
374 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
375 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
377 if (filter->fw_l2_filter_id == UINT64_MAX)
380 if (filter->matching_l2_fltr_ptr)
381 l2_filter = filter->matching_l2_fltr_ptr;
383 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
384 filter, l2_filter, l2_filter->l2_ref_cnt);
386 if (l2_filter->l2_ref_cnt > 0)
387 l2_filter->l2_ref_cnt--;
389 if (l2_filter->l2_ref_cnt > 0)
392 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
394 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
396 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
401 filter->fw_l2_filter_id = UINT64_MAX;
406 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
408 struct bnxt_filter_info *filter)
411 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
412 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
413 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
414 const struct rte_eth_vmdq_rx_conf *conf =
415 &dev_conf->rx_adv_conf.vmdq_rx_conf;
416 uint32_t enables = 0;
417 uint16_t j = dst_id - 1;
419 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
420 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
421 conf->pool_map[j].pools & (1UL << j)) {
423 "Add vlan %u to vmdq pool %u\n",
424 conf->pool_map[j].vlan_id, j);
426 filter->l2_ivlan = conf->pool_map[j].vlan_id;
428 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
429 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
432 if (filter->fw_l2_filter_id != UINT64_MAX)
433 bnxt_hwrm_clear_l2_filter(bp, filter);
435 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
437 req.flags = rte_cpu_to_le_32(filter->flags);
439 enables = filter->enables |
440 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
441 req.dst_id = rte_cpu_to_le_16(dst_id);
444 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
445 memcpy(req.l2_addr, filter->l2_addr,
448 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
449 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
452 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
453 req.l2_ovlan = filter->l2_ovlan;
455 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
456 req.l2_ivlan = filter->l2_ivlan;
458 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
459 req.l2_ovlan_mask = filter->l2_ovlan_mask;
461 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
462 req.l2_ivlan_mask = filter->l2_ivlan_mask;
463 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
464 req.src_id = rte_cpu_to_le_32(filter->src_id);
465 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
466 req.src_type = filter->src_type;
467 if (filter->pri_hint) {
468 req.pri_hint = filter->pri_hint;
469 req.l2_filter_id_hint =
470 rte_cpu_to_le_64(filter->l2_filter_id_hint);
473 req.enables = rte_cpu_to_le_32(enables);
475 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
479 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
485 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
487 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
488 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
495 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
498 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
501 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
502 if (ptp->tx_tstamp_en)
503 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
506 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
507 req.flags = rte_cpu_to_le_32(flags);
508 req.enables = rte_cpu_to_le_32
509 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
510 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
512 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
518 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
521 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
522 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
523 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
525 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
529 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
531 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
533 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
537 if (!BNXT_CHIP_THOR(bp) &&
538 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
541 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
542 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
544 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
548 if (!BNXT_CHIP_THOR(bp)) {
549 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
550 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
551 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
552 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
553 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
554 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
555 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
556 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
557 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
558 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
559 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
560 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
561 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
562 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
563 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
564 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
565 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
566 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
575 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
578 struct hwrm_func_qcaps_input req = {.req_type = 0 };
579 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
580 uint16_t new_max_vfs;
584 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
586 req.fid = rte_cpu_to_le_16(0xffff);
588 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
592 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
593 flags = rte_le_to_cpu_32(resp->flags);
595 bp->pf.port_id = resp->port_id;
596 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
597 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
598 new_max_vfs = bp->pdev->max_vfs;
599 if (new_max_vfs != bp->pf.max_vfs) {
601 rte_free(bp->pf.vf_info);
602 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
603 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
604 bp->pf.max_vfs = new_max_vfs;
605 for (i = 0; i < new_max_vfs; i++) {
606 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
607 bp->pf.vf_info[i].vlan_table =
608 rte_zmalloc("VF VLAN table",
611 if (bp->pf.vf_info[i].vlan_table == NULL)
613 "Fail to alloc VLAN table for VF %d\n",
617 bp->pf.vf_info[i].vlan_table);
618 bp->pf.vf_info[i].vlan_as_table =
619 rte_zmalloc("VF VLAN AS table",
622 if (bp->pf.vf_info[i].vlan_as_table == NULL)
624 "Alloc VLAN AS table for VF %d fail\n",
628 bp->pf.vf_info[i].vlan_as_table);
629 STAILQ_INIT(&bp->pf.vf_info[i].filter);
634 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
635 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
636 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
637 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
638 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
639 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
640 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
641 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
642 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
643 if (!BNXT_CHIP_THOR(bp))
644 bp->max_l2_ctx += bp->max_rx_em_flows;
645 /* TODO: For now, do not support VMDq/RFS on VFs. */
650 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
654 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
656 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
657 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
658 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
659 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
661 bnxt_hwrm_ptp_qcfg(bp);
665 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
666 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
668 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
669 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
670 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
672 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
675 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
676 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
678 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
685 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
689 rc = __bnxt_hwrm_func_qcaps(bp);
690 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
691 rc = bnxt_alloc_ctx_mem(bp);
695 rc = bnxt_hwrm_func_resc_qcaps(bp);
697 bp->flags |= BNXT_FLAG_NEW_RM;
703 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
704 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
707 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
708 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
710 HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
712 req.target_id = rte_cpu_to_le_16(0xffff);
714 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
718 if (rte_le_to_cpu_32(resp->flags) &
719 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
720 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
721 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
724 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
731 int bnxt_hwrm_func_reset(struct bnxt *bp)
734 struct hwrm_func_reset_input req = {.req_type = 0 };
735 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
737 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
739 req.enables = rte_cpu_to_le_32(0);
741 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
749 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
753 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
754 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
756 if (bp->flags & BNXT_FLAG_REGISTERED)
759 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
760 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
761 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
763 /* PFs and trusted VFs should indicate the support of the
764 * Master capability on non Stingray platform
766 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
767 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
769 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
770 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
771 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
772 req.ver_maj = RTE_VER_YEAR;
773 req.ver_min = RTE_VER_MONTH;
774 req.ver_upd = RTE_VER_MINOR;
777 req.enables |= rte_cpu_to_le_32(
778 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
779 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
780 RTE_MIN(sizeof(req.vf_req_fwd),
781 sizeof(bp->pf.vf_req_fwd)));
784 * PF can sniff HWRM API issued by VF. This can be set up by
785 * linux driver and inherited by the DPDK PF driver. Clear
786 * this HWRM sniffer list in FW because DPDK PF driver does
789 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
792 req.flags = rte_cpu_to_le_32(flags);
794 req.async_event_fwd[0] |=
795 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
796 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
797 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
798 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
799 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
800 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
801 req.async_event_fwd[0] |=
802 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
803 req.async_event_fwd[1] |=
804 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
805 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
807 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
811 flags = rte_le_to_cpu_32(resp->flags);
812 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
813 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
817 bp->flags |= BNXT_FLAG_REGISTERED;
822 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
824 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
827 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
830 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
835 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
836 struct hwrm_func_vf_cfg_input req = {0};
838 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
840 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
841 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
842 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
843 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
844 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
846 if (BNXT_HAS_RING_GRPS(bp)) {
847 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
848 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
851 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
852 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
853 AGG_RING_MULTIPLIER);
854 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
855 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
857 BNXT_NUM_ASYNC_CPR(bp));
858 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
859 if (bp->vf_resv_strategy ==
860 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
861 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
862 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
863 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
864 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
865 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
866 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
870 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
871 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
872 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
873 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
874 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
875 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
877 if (test && BNXT_HAS_RING_GRPS(bp))
878 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
880 req.flags = rte_cpu_to_le_32(flags);
881 req.enables |= rte_cpu_to_le_32(enables);
883 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
886 HWRM_CHECK_RESULT_SILENT();
894 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
897 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
898 struct hwrm_func_resource_qcaps_input req = {0};
900 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
901 req.fid = rte_cpu_to_le_16(0xffff);
903 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
908 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
909 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
910 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
911 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
912 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
913 /* func_resource_qcaps does not return max_rx_em_flows.
914 * So use the value provided by func_qcaps.
916 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
917 if (!BNXT_CHIP_THOR(bp))
918 bp->max_l2_ctx += bp->max_rx_em_flows;
919 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
920 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
922 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
923 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
924 if (bp->vf_resv_strategy >
925 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
926 bp->vf_resv_strategy =
927 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
933 int bnxt_hwrm_ver_get(struct bnxt *bp)
936 struct hwrm_ver_get_input req = {.req_type = 0 };
937 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
939 uint16_t max_resp_len;
940 char type[RTE_MEMZONE_NAMESIZE];
941 uint32_t dev_caps_cfg;
943 bp->max_req_len = HWRM_MAX_REQ_LEN;
944 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
946 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
947 req.hwrm_intf_min = HWRM_VERSION_MINOR;
948 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
950 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
952 if (bp->flags & BNXT_FLAG_FW_RESET)
953 HWRM_CHECK_RESULT_SILENT();
957 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
958 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
959 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
960 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
961 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
962 (resp->hwrm_fw_min_8b << 16) |
963 (resp->hwrm_fw_bld_8b << 8) |
964 resp->hwrm_fw_rsvd_8b;
965 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
966 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
968 fw_version = resp->hwrm_intf_maj_8b << 16;
969 fw_version |= resp->hwrm_intf_min_8b << 8;
970 fw_version |= resp->hwrm_intf_upd_8b;
971 bp->hwrm_spec_code = fw_version;
973 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
974 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
979 if (bp->max_req_len > resp->max_req_win_len) {
980 PMD_DRV_LOG(ERR, "Unsupported request length\n");
983 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
984 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
985 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
986 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
988 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
989 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
991 if (bp->max_resp_len != max_resp_len) {
992 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
993 bp->pdev->addr.domain, bp->pdev->addr.bus,
994 bp->pdev->addr.devid, bp->pdev->addr.function);
996 rte_free(bp->hwrm_cmd_resp_addr);
998 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
999 if (bp->hwrm_cmd_resp_addr == NULL) {
1003 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1004 bp->hwrm_cmd_resp_dma_addr =
1005 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1006 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1008 "Unable to map response buffer to physical memory.\n");
1012 bp->max_resp_len = max_resp_len;
1016 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1018 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1019 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1020 bp->flags |= BNXT_FLAG_SHORT_CMD;
1023 if (((dev_caps_cfg &
1024 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1026 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1027 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1028 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1029 bp->pdev->addr.domain, bp->pdev->addr.bus,
1030 bp->pdev->addr.devid, bp->pdev->addr.function);
1032 rte_free(bp->hwrm_short_cmd_req_addr);
1034 bp->hwrm_short_cmd_req_addr =
1035 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1036 if (bp->hwrm_short_cmd_req_addr == NULL) {
1040 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1041 bp->hwrm_short_cmd_req_dma_addr =
1042 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1043 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1044 rte_free(bp->hwrm_short_cmd_req_addr);
1046 "Unable to map buffer to physical memory.\n");
1052 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1053 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1054 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1057 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1058 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1060 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1061 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1062 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1070 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1073 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1074 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1076 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1079 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1082 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1084 HWRM_CHECK_RESULT();
1090 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1093 struct hwrm_port_phy_cfg_input req = {0};
1094 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1095 uint32_t enables = 0;
1097 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1099 if (conf->link_up) {
1100 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1101 if (bp->link_info.auto_mode && conf->link_speed) {
1102 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1103 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1106 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1107 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1108 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1110 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1111 * any auto mode, even "none".
1113 if (!conf->link_speed) {
1114 /* No speeds specified. Enable AutoNeg - all speeds */
1116 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1118 /* AutoNeg - Advertise speeds specified. */
1119 if (conf->auto_link_speed_mask &&
1120 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1122 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1123 req.auto_link_speed_mask =
1124 conf->auto_link_speed_mask;
1126 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1129 req.auto_duplex = conf->duplex;
1130 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1131 req.auto_pause = conf->auto_pause;
1132 req.force_pause = conf->force_pause;
1133 /* Set force_pause if there is no auto or if there is a force */
1134 if (req.auto_pause && !req.force_pause)
1135 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1137 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1139 req.enables = rte_cpu_to_le_32(enables);
1142 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1143 PMD_DRV_LOG(INFO, "Force Link Down\n");
1146 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1148 HWRM_CHECK_RESULT();
1154 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1155 struct bnxt_link_info *link_info)
1158 struct hwrm_port_phy_qcfg_input req = {0};
1159 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1161 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1163 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1165 HWRM_CHECK_RESULT();
1167 link_info->phy_link_status = resp->link;
1168 link_info->link_up =
1169 (link_info->phy_link_status ==
1170 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1171 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1172 link_info->duplex = resp->duplex_cfg;
1173 link_info->pause = resp->pause;
1174 link_info->auto_pause = resp->auto_pause;
1175 link_info->force_pause = resp->force_pause;
1176 link_info->auto_mode = resp->auto_mode;
1177 link_info->phy_type = resp->phy_type;
1178 link_info->media_type = resp->media_type;
1180 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1181 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1182 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1183 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1184 link_info->phy_ver[0] = resp->phy_maj;
1185 link_info->phy_ver[1] = resp->phy_min;
1186 link_info->phy_ver[2] = resp->phy_bld;
1190 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1191 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1192 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1193 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1194 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1195 link_info->auto_link_speed_mask);
1196 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1197 link_info->force_link_speed);
1202 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1205 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1206 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1207 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1211 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1213 req.flags = rte_cpu_to_le_32(dir);
1214 /* HWRM Version >= 1.9.1 */
1215 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1217 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1218 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1220 HWRM_CHECK_RESULT();
1222 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1223 GET_TX_QUEUE_INFO(0);
1224 GET_TX_QUEUE_INFO(1);
1225 GET_TX_QUEUE_INFO(2);
1226 GET_TX_QUEUE_INFO(3);
1227 GET_TX_QUEUE_INFO(4);
1228 GET_TX_QUEUE_INFO(5);
1229 GET_TX_QUEUE_INFO(6);
1230 GET_TX_QUEUE_INFO(7);
1232 GET_RX_QUEUE_INFO(0);
1233 GET_RX_QUEUE_INFO(1);
1234 GET_RX_QUEUE_INFO(2);
1235 GET_RX_QUEUE_INFO(3);
1236 GET_RX_QUEUE_INFO(4);
1237 GET_RX_QUEUE_INFO(5);
1238 GET_RX_QUEUE_INFO(6);
1239 GET_RX_QUEUE_INFO(7);
1244 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1247 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1248 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1252 /* iterate and find the COSq profile to use for Tx */
1253 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1254 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1255 if (bp->tx_cos_queue[i].id != 0xff)
1256 bp->tx_cosq_id[j++] =
1257 bp->tx_cos_queue[i].id;
1260 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1261 if (bp->tx_cos_queue[i].profile ==
1262 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1264 bp->tx_cos_queue[i].id;
1271 bp->max_tc = resp->max_configurable_queues;
1272 bp->max_lltc = resp->max_configurable_lossless_queues;
1273 if (bp->max_tc > BNXT_MAX_QUEUE)
1274 bp->max_tc = BNXT_MAX_QUEUE;
1275 bp->max_q = bp->max_tc;
1277 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1278 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1286 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1287 struct bnxt_ring *ring,
1288 uint32_t ring_type, uint32_t map_index,
1289 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1290 uint16_t tx_cosq_id)
1293 uint32_t enables = 0;
1294 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1295 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1296 struct rte_mempool *mb_pool;
1297 uint16_t rx_buf_size;
1299 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1301 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1302 req.fbo = rte_cpu_to_le_32(0);
1303 /* Association of ring index with doorbell index */
1304 req.logical_id = rte_cpu_to_le_16(map_index);
1305 req.length = rte_cpu_to_le_32(ring->ring_size);
1307 switch (ring_type) {
1308 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1309 req.ring_type = ring_type;
1310 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1311 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1312 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1313 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1315 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1317 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1318 req.ring_type = ring_type;
1319 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1320 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1321 if (BNXT_CHIP_THOR(bp)) {
1322 mb_pool = bp->rx_queues[0]->mb_pool;
1323 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1324 RTE_PKTMBUF_HEADROOM;
1325 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1326 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1328 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1330 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1332 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1334 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1335 req.ring_type = ring_type;
1336 if (BNXT_HAS_NQ(bp)) {
1337 /* Association of cp ring with nq */
1338 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1340 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1342 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1344 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1345 req.ring_type = ring_type;
1346 req.page_size = BNXT_PAGE_SHFT;
1347 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1349 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1350 req.ring_type = ring_type;
1351 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1353 mb_pool = bp->rx_queues[0]->mb_pool;
1354 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1355 RTE_PKTMBUF_HEADROOM;
1356 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1357 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1359 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1360 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1361 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1362 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1365 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1370 req.enables = rte_cpu_to_le_32(enables);
1372 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1374 if (rc || resp->error_code) {
1375 if (rc == 0 && resp->error_code)
1376 rc = rte_le_to_cpu_16(resp->error_code);
1377 switch (ring_type) {
1378 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1380 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1383 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1385 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1388 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1390 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1394 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1396 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1399 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1401 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1405 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1411 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1416 int bnxt_hwrm_ring_free(struct bnxt *bp,
1417 struct bnxt_ring *ring, uint32_t ring_type)
1420 struct hwrm_ring_free_input req = {.req_type = 0 };
1421 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1423 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1425 req.ring_type = ring_type;
1426 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1428 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1430 if (rc || resp->error_code) {
1431 if (rc == 0 && resp->error_code)
1432 rc = rte_le_to_cpu_16(resp->error_code);
1435 switch (ring_type) {
1436 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1437 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1440 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1441 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1444 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1445 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1448 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1450 "hwrm_ring_free nq failed. rc:%d\n", rc);
1452 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1454 "hwrm_ring_free agg failed. rc:%d\n", rc);
1457 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1465 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1468 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1469 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1471 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1473 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1474 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1475 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1476 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1478 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1480 HWRM_CHECK_RESULT();
1482 bp->grp_info[idx].fw_grp_id =
1483 rte_le_to_cpu_16(resp->ring_group_id);
1490 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1493 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1494 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1496 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1498 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1500 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1502 HWRM_CHECK_RESULT();
1505 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1509 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1512 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1513 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1515 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1518 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1520 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1522 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1524 HWRM_CHECK_RESULT();
1530 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1531 unsigned int idx __rte_unused)
1534 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1535 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1537 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1539 req.update_period_ms = rte_cpu_to_le_32(0);
1541 req.stats_dma_addr =
1542 rte_cpu_to_le_64(cpr->hw_stats_map);
1544 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1546 HWRM_CHECK_RESULT();
1548 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1555 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1556 unsigned int idx __rte_unused)
1559 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1560 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1562 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1564 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1566 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1568 HWRM_CHECK_RESULT();
1574 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1577 struct hwrm_vnic_alloc_input req = { 0 };
1578 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1580 if (!BNXT_HAS_RING_GRPS(bp))
1581 goto skip_ring_grps;
1583 /* map ring groups to this vnic */
1584 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1585 vnic->start_grp_id, vnic->end_grp_id);
1586 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1587 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1589 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1590 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1591 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1592 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1595 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1596 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1597 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1599 if (vnic->func_default)
1601 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1602 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1604 HWRM_CHECK_RESULT();
1606 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1608 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1612 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1613 struct bnxt_vnic_info *vnic,
1614 struct bnxt_plcmodes_cfg *pmode)
1617 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1618 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1620 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1622 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1624 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1626 HWRM_CHECK_RESULT();
1628 pmode->flags = rte_le_to_cpu_32(resp->flags);
1629 /* dflt_vnic bit doesn't exist in the _cfg command */
1630 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1631 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1632 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1633 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1640 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1641 struct bnxt_vnic_info *vnic,
1642 struct bnxt_plcmodes_cfg *pmode)
1645 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1646 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1648 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1649 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1653 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1655 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1656 req.flags = rte_cpu_to_le_32(pmode->flags);
1657 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1658 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1659 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1660 req.enables = rte_cpu_to_le_32(
1661 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1662 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1663 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1666 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1668 HWRM_CHECK_RESULT();
1674 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1677 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1678 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1679 struct bnxt_plcmodes_cfg pmodes = { 0 };
1680 uint32_t ctx_enable_flag = 0;
1681 uint32_t enables = 0;
1683 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1684 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1688 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1692 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1694 if (BNXT_CHIP_THOR(bp)) {
1695 struct bnxt_rx_queue *rxq =
1696 bp->eth_dev->data->rx_queues[vnic->start_grp_id];
1697 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1698 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1700 req.default_rx_ring_id =
1701 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1702 req.default_cmpl_ring_id =
1703 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1704 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1705 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1709 /* Only RSS support for now TBD: COS & LB */
1710 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1711 if (vnic->lb_rule != 0xffff)
1712 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1713 if (vnic->cos_rule != 0xffff)
1714 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1715 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1716 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1717 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1719 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1720 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1721 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1724 enables |= ctx_enable_flag;
1725 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1726 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1727 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1728 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1731 req.enables = rte_cpu_to_le_32(enables);
1732 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1733 req.mru = rte_cpu_to_le_16(vnic->mru);
1734 /* Configure default VNIC only once. */
1735 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1737 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1738 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1740 if (vnic->vlan_strip)
1742 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1745 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1746 if (vnic->roce_dual)
1747 req.flags |= rte_cpu_to_le_32(
1748 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1749 if (vnic->roce_only)
1750 req.flags |= rte_cpu_to_le_32(
1751 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1752 if (vnic->rss_dflt_cr)
1753 req.flags |= rte_cpu_to_le_32(
1754 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1756 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1758 HWRM_CHECK_RESULT();
1761 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1766 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1770 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1771 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1773 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1774 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1777 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1780 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1781 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1782 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1784 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1786 HWRM_CHECK_RESULT();
1788 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1789 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1790 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1791 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1792 vnic->mru = rte_le_to_cpu_16(resp->mru);
1793 vnic->func_default = rte_le_to_cpu_32(
1794 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1795 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1796 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1797 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1798 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1799 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1800 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1801 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1802 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1803 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1804 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1811 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1812 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1816 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1817 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1818 bp->hwrm_cmd_resp_addr;
1820 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1822 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1823 HWRM_CHECK_RESULT();
1825 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1826 if (!BNXT_HAS_RING_GRPS(bp))
1827 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1828 else if (ctx_idx == 0)
1829 vnic->rss_rule = ctx_id;
1837 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1838 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1841 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1842 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1843 bp->hwrm_cmd_resp_addr;
1845 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1846 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1849 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1851 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1853 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1855 HWRM_CHECK_RESULT();
1861 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1865 if (BNXT_CHIP_THOR(bp)) {
1868 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1869 rc = _bnxt_hwrm_vnic_ctx_free(bp,
1871 vnic->fw_grp_ids[j]);
1872 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1874 vnic->num_lb_ctxts = 0;
1876 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1877 vnic->rss_rule = INVALID_HW_RING_ID;
1883 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1886 struct hwrm_vnic_free_input req = {.req_type = 0 };
1887 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1889 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1890 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1894 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1896 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1898 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1900 HWRM_CHECK_RESULT();
1903 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1904 /* Configure default VNIC again if necessary. */
1905 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1906 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1912 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1916 int nr_ctxs = vnic->num_lb_ctxts;
1917 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1918 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1920 for (i = 0; i < nr_ctxs; i++) {
1921 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1923 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1924 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1925 req.hash_mode_flags = vnic->hash_mode;
1927 req.hash_key_tbl_addr =
1928 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1930 req.ring_grp_tbl_addr =
1931 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1932 i * HW_HASH_INDEX_SIZE);
1933 req.ring_table_pair_index = i;
1934 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1936 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1939 HWRM_CHECK_RESULT();
1946 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1947 struct bnxt_vnic_info *vnic)
1950 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1951 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1953 if (!vnic->rss_table)
1956 if (BNXT_CHIP_THOR(bp))
1957 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1959 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1961 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1962 req.hash_mode_flags = vnic->hash_mode;
1964 req.ring_grp_tbl_addr =
1965 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1966 req.hash_key_tbl_addr =
1967 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1968 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1969 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1971 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1973 HWRM_CHECK_RESULT();
1979 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1980 struct bnxt_vnic_info *vnic)
1983 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1984 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1987 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1988 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1992 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1994 req.flags = rte_cpu_to_le_32(
1995 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1997 req.enables = rte_cpu_to_le_32(
1998 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2000 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2001 size -= RTE_PKTMBUF_HEADROOM;
2002 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2004 req.jumbo_thresh = rte_cpu_to_le_16(size);
2005 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2007 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2009 HWRM_CHECK_RESULT();
2015 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2016 struct bnxt_vnic_info *vnic, bool enable)
2019 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2020 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2022 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2024 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2028 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2029 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2033 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2036 req.enables = rte_cpu_to_le_32(
2037 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2038 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2039 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2040 req.flags = rte_cpu_to_le_32(
2041 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2042 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2043 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2044 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2045 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2046 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2047 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2048 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2049 req.min_agg_len = rte_cpu_to_le_32(512);
2051 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2053 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2055 HWRM_CHECK_RESULT();
2061 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2063 struct hwrm_func_cfg_input req = {0};
2064 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2067 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2068 req.enables = rte_cpu_to_le_32(
2069 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2070 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2071 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2073 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2075 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2076 HWRM_CHECK_RESULT();
2079 bp->pf.vf_info[vf].random_mac = false;
2084 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2088 struct hwrm_func_qstats_input req = {.req_type = 0};
2089 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2091 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2093 req.fid = rte_cpu_to_le_16(fid);
2095 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2097 HWRM_CHECK_RESULT();
2100 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2107 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2108 struct rte_eth_stats *stats)
2111 struct hwrm_func_qstats_input req = {.req_type = 0};
2112 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2114 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2116 req.fid = rte_cpu_to_le_16(fid);
2118 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2120 HWRM_CHECK_RESULT();
2122 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2123 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2124 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2125 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2126 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2127 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2129 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2130 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2131 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2132 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2133 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2134 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2136 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2137 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2138 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2145 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2148 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2149 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2151 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2153 req.fid = rte_cpu_to_le_16(fid);
2155 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2157 HWRM_CHECK_RESULT();
2164 * HWRM utility functions
2167 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2172 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2173 struct bnxt_tx_queue *txq;
2174 struct bnxt_rx_queue *rxq;
2175 struct bnxt_cp_ring_info *cpr;
2177 if (i >= bp->rx_cp_nr_rings) {
2178 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2181 rxq = bp->rx_queues[i];
2185 rc = bnxt_hwrm_stat_clear(bp, cpr);
2192 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2196 struct bnxt_cp_ring_info *cpr;
2198 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2200 if (i >= bp->rx_cp_nr_rings) {
2201 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2203 cpr = bp->rx_queues[i]->cp_ring;
2204 if (BNXT_HAS_RING_GRPS(bp))
2205 bp->grp_info[i].fw_stats_ctx = -1;
2207 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2208 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2209 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2217 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2222 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2223 struct bnxt_tx_queue *txq;
2224 struct bnxt_rx_queue *rxq;
2225 struct bnxt_cp_ring_info *cpr;
2227 if (i >= bp->rx_cp_nr_rings) {
2228 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2231 rxq = bp->rx_queues[i];
2235 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2243 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2248 if (!BNXT_HAS_RING_GRPS(bp))
2251 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2253 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2256 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2264 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2266 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2268 bnxt_hwrm_ring_free(bp, cp_ring,
2269 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2270 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2271 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2272 sizeof(*cpr->cp_desc_ring));
2273 cpr->cp_raw_cons = 0;
2277 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2279 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2281 bnxt_hwrm_ring_free(bp, cp_ring,
2282 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2283 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2284 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2285 sizeof(*cpr->cp_desc_ring));
2286 cpr->cp_raw_cons = 0;
2290 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2292 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2293 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2294 struct bnxt_ring *ring = rxr->rx_ring_struct;
2295 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2297 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2298 bnxt_hwrm_ring_free(bp, ring,
2299 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2300 ring->fw_ring_id = INVALID_HW_RING_ID;
2301 if (BNXT_HAS_RING_GRPS(bp))
2302 bp->grp_info[queue_index].rx_fw_ring_id =
2304 memset(rxr->rx_desc_ring, 0,
2305 rxr->rx_ring_struct->ring_size *
2306 sizeof(*rxr->rx_desc_ring));
2307 memset(rxr->rx_buf_ring, 0,
2308 rxr->rx_ring_struct->ring_size *
2309 sizeof(*rxr->rx_buf_ring));
2312 ring = rxr->ag_ring_struct;
2313 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2314 bnxt_hwrm_ring_free(bp, ring,
2315 BNXT_CHIP_THOR(bp) ?
2316 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2317 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2318 ring->fw_ring_id = INVALID_HW_RING_ID;
2319 memset(rxr->ag_buf_ring, 0,
2320 rxr->ag_ring_struct->ring_size *
2321 sizeof(*rxr->ag_buf_ring));
2323 if (BNXT_HAS_RING_GRPS(bp))
2324 bp->grp_info[queue_index].ag_fw_ring_id =
2327 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2328 bnxt_free_cp_ring(bp, cpr);
2330 if (BNXT_HAS_RING_GRPS(bp))
2331 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2334 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2338 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2339 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2340 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2341 struct bnxt_ring *ring = txr->tx_ring_struct;
2342 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2344 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2345 bnxt_hwrm_ring_free(bp, ring,
2346 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2347 ring->fw_ring_id = INVALID_HW_RING_ID;
2348 memset(txr->tx_desc_ring, 0,
2349 txr->tx_ring_struct->ring_size *
2350 sizeof(*txr->tx_desc_ring));
2351 memset(txr->tx_buf_ring, 0,
2352 txr->tx_ring_struct->ring_size *
2353 sizeof(*txr->tx_buf_ring));
2357 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2358 bnxt_free_cp_ring(bp, cpr);
2359 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2363 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2364 bnxt_free_hwrm_rx_ring(bp, i);
2369 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2374 if (!BNXT_HAS_RING_GRPS(bp))
2377 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2378 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2385 void bnxt_free_hwrm_resources(struct bnxt *bp)
2387 /* Release memzone */
2388 rte_free(bp->hwrm_cmd_resp_addr);
2389 rte_free(bp->hwrm_short_cmd_req_addr);
2390 bp->hwrm_cmd_resp_addr = NULL;
2391 bp->hwrm_short_cmd_req_addr = NULL;
2392 bp->hwrm_cmd_resp_dma_addr = 0;
2393 bp->hwrm_short_cmd_req_dma_addr = 0;
2396 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2398 struct rte_pci_device *pdev = bp->pdev;
2399 char type[RTE_MEMZONE_NAMESIZE];
2401 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2402 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2403 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2404 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2405 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2406 if (bp->hwrm_cmd_resp_addr == NULL)
2408 bp->hwrm_cmd_resp_dma_addr =
2409 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2410 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2412 "unable to map response address to physical memory\n");
2415 rte_spinlock_init(&bp->hwrm_lock);
2420 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2422 struct bnxt_filter_info *filter;
2425 STAILQ_FOREACH(filter, &vnic->filter, next) {
2426 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2427 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2428 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2429 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2431 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2432 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2433 bnxt_free_filter(bp, filter);
2441 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2443 struct bnxt_filter_info *filter;
2444 struct rte_flow *flow;
2447 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2448 flow = STAILQ_FIRST(&vnic->flow_list);
2449 filter = flow->filter;
2450 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2451 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2452 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2453 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2454 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2456 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2458 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2466 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2468 struct bnxt_filter_info *filter;
2471 STAILQ_FOREACH(filter, &vnic->filter, next) {
2472 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2473 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2475 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2476 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2479 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2490 void bnxt_free_tunnel_ports(struct bnxt *bp)
2492 if (bp->vxlan_port_cnt)
2493 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2494 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2496 if (bp->geneve_port_cnt)
2497 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2498 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2499 bp->geneve_port = 0;
2502 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2506 if (bp->vnic_info == NULL)
2510 * Cleanup VNICs in reverse order, to make sure the L2 filter
2511 * from vnic0 is last to be cleaned up.
2513 for (i = bp->max_vnics - 1; i >= 0; i--) {
2514 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2516 // If the VNIC ID is invalid we are not currently using the VNIC
2517 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2520 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2522 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2524 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2526 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2528 bnxt_hwrm_vnic_free(bp, vnic);
2530 rte_free(vnic->fw_grp_ids);
2532 /* Ring resources */
2533 bnxt_free_all_hwrm_rings(bp);
2534 bnxt_free_all_hwrm_ring_grps(bp);
2535 bnxt_free_all_hwrm_stat_ctxs(bp);
2536 bnxt_free_tunnel_ports(bp);
2539 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2541 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2543 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2544 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2546 switch (conf_link_speed) {
2547 case ETH_LINK_SPEED_10M_HD:
2548 case ETH_LINK_SPEED_100M_HD:
2550 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2552 return hw_link_duplex;
2555 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2557 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2560 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2562 uint16_t eth_link_speed = 0;
2564 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2565 return ETH_LINK_SPEED_AUTONEG;
2567 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2568 case ETH_LINK_SPEED_100M:
2569 case ETH_LINK_SPEED_100M_HD:
2572 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2574 case ETH_LINK_SPEED_1G:
2576 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2578 case ETH_LINK_SPEED_2_5G:
2580 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2582 case ETH_LINK_SPEED_10G:
2584 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2586 case ETH_LINK_SPEED_20G:
2588 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2590 case ETH_LINK_SPEED_25G:
2592 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2594 case ETH_LINK_SPEED_40G:
2596 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2598 case ETH_LINK_SPEED_50G:
2600 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2602 case ETH_LINK_SPEED_100G:
2604 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2608 "Unsupported link speed %d; default to AUTO\n",
2612 return eth_link_speed;
2615 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2616 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2617 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2618 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2620 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2624 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2627 if (link_speed & ETH_LINK_SPEED_FIXED) {
2628 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2630 if (one_speed & (one_speed - 1)) {
2632 "Invalid advertised speeds (%u) for port %u\n",
2633 link_speed, port_id);
2636 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2638 "Unsupported advertised speed (%u) for port %u\n",
2639 link_speed, port_id);
2643 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2645 "Unsupported advertised speeds (%u) for port %u\n",
2646 link_speed, port_id);
2654 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2658 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2659 if (bp->link_info.support_speeds)
2660 return bp->link_info.support_speeds;
2661 link_speed = BNXT_SUPPORTED_SPEEDS;
2664 if (link_speed & ETH_LINK_SPEED_100M)
2665 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2666 if (link_speed & ETH_LINK_SPEED_100M_HD)
2667 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2668 if (link_speed & ETH_LINK_SPEED_1G)
2669 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2670 if (link_speed & ETH_LINK_SPEED_2_5G)
2671 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2672 if (link_speed & ETH_LINK_SPEED_10G)
2673 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2674 if (link_speed & ETH_LINK_SPEED_20G)
2675 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2676 if (link_speed & ETH_LINK_SPEED_25G)
2677 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2678 if (link_speed & ETH_LINK_SPEED_40G)
2679 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2680 if (link_speed & ETH_LINK_SPEED_50G)
2681 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2682 if (link_speed & ETH_LINK_SPEED_100G)
2683 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2687 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2689 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2691 switch (hw_link_speed) {
2692 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2693 eth_link_speed = ETH_SPEED_NUM_100M;
2695 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2696 eth_link_speed = ETH_SPEED_NUM_1G;
2698 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2699 eth_link_speed = ETH_SPEED_NUM_2_5G;
2701 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2702 eth_link_speed = ETH_SPEED_NUM_10G;
2704 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2705 eth_link_speed = ETH_SPEED_NUM_20G;
2707 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2708 eth_link_speed = ETH_SPEED_NUM_25G;
2710 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2711 eth_link_speed = ETH_SPEED_NUM_40G;
2713 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2714 eth_link_speed = ETH_SPEED_NUM_50G;
2716 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2717 eth_link_speed = ETH_SPEED_NUM_100G;
2719 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2721 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2725 return eth_link_speed;
2728 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2730 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2732 switch (hw_link_duplex) {
2733 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2734 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2736 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2738 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2739 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2742 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2746 return eth_link_duplex;
2749 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2752 struct bnxt_link_info *link_info = &bp->link_info;
2754 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2757 "Get link config failed with rc %d\n", rc);
2760 if (link_info->link_speed)
2762 bnxt_parse_hw_link_speed(link_info->link_speed);
2764 link->link_speed = ETH_SPEED_NUM_NONE;
2765 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2766 link->link_status = link_info->link_up;
2767 link->link_autoneg = link_info->auto_mode ==
2768 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2769 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2774 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2777 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2778 struct bnxt_link_info link_req;
2779 uint16_t speed, autoneg;
2781 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2784 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2785 bp->eth_dev->data->port_id);
2789 memset(&link_req, 0, sizeof(link_req));
2790 link_req.link_up = link_up;
2794 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2795 if (BNXT_CHIP_THOR(bp) &&
2796 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2797 /* 40G is not supported as part of media auto detect.
2798 * The speed should be forced and autoneg disabled
2799 * to configure 40G speed.
2801 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2805 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2806 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2807 /* Autoneg can be done only when the FW allows.
2808 * When user configures fixed speed of 40G and later changes to
2809 * any other speed, auto_link_speed/force_link_speed is still set
2810 * to 40G until link comes up at new speed.
2813 !(!BNXT_CHIP_THOR(bp) &&
2814 (bp->link_info.auto_link_speed ||
2815 bp->link_info.force_link_speed))) {
2816 link_req.phy_flags |=
2817 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2818 link_req.auto_link_speed_mask =
2819 bnxt_parse_eth_link_speed_mask(bp,
2820 dev_conf->link_speeds);
2822 if (bp->link_info.phy_type ==
2823 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2824 bp->link_info.phy_type ==
2825 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2826 bp->link_info.media_type ==
2827 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2828 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2832 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2833 /* If user wants a particular speed try that first. */
2835 link_req.link_speed = speed;
2836 else if (bp->link_info.force_link_speed)
2837 link_req.link_speed = bp->link_info.force_link_speed;
2839 link_req.link_speed = bp->link_info.auto_link_speed;
2841 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2842 link_req.auto_pause = bp->link_info.auto_pause;
2843 link_req.force_pause = bp->link_info.force_pause;
2846 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2849 "Set link config failed with rc %d\n", rc);
2857 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2859 struct hwrm_func_qcfg_input req = {0};
2860 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2864 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2865 req.fid = rte_cpu_to_le_16(0xffff);
2867 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2869 HWRM_CHECK_RESULT();
2871 /* Hard Coded.. 0xfff VLAN ID mask */
2872 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2873 flags = rte_le_to_cpu_16(resp->flags);
2874 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2875 bp->flags |= BNXT_FLAG_MULTI_HOST;
2877 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2878 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2879 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2880 } else if (BNXT_VF(bp) &&
2881 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2882 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2883 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2889 switch (resp->port_partition_type) {
2890 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2891 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2892 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2894 bp->port_partition_type = resp->port_partition_type;
2897 bp->port_partition_type = 0;
2906 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2907 struct hwrm_func_qcaps_output *qcaps)
2909 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2910 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2911 sizeof(qcaps->mac_address));
2912 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2913 qcaps->max_rx_rings = fcfg->num_rx_rings;
2914 qcaps->max_tx_rings = fcfg->num_tx_rings;
2915 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2916 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2918 qcaps->first_vf_id = 0;
2919 qcaps->max_vnics = fcfg->num_vnics;
2920 qcaps->max_decap_records = 0;
2921 qcaps->max_encap_records = 0;
2922 qcaps->max_tx_wm_flows = 0;
2923 qcaps->max_tx_em_flows = 0;
2924 qcaps->max_rx_wm_flows = 0;
2925 qcaps->max_rx_em_flows = 0;
2926 qcaps->max_flow_id = 0;
2927 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2928 qcaps->max_sp_tx_rings = 0;
2929 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2932 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2934 struct hwrm_func_cfg_input req = {0};
2935 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2939 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2940 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2941 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2942 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2943 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2944 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2945 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2946 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2947 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2949 if (BNXT_HAS_RING_GRPS(bp)) {
2950 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2951 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2952 } else if (BNXT_HAS_NQ(bp)) {
2953 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2954 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2957 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2958 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2959 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2960 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2962 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2963 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2964 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2965 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2966 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2967 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2968 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2969 req.fid = rte_cpu_to_le_16(0xffff);
2970 req.enables = rte_cpu_to_le_32(enables);
2972 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2974 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2976 HWRM_CHECK_RESULT();
2982 static void populate_vf_func_cfg_req(struct bnxt *bp,
2983 struct hwrm_func_cfg_input *req,
2986 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2987 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2988 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2989 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2990 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2991 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2992 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2993 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2994 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2995 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2997 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2998 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3000 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3001 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3003 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3005 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3006 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3008 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3009 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3010 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3011 /* TODO: For now, do not support VMDq/RFS on VFs. */
3012 req->num_vnics = rte_cpu_to_le_16(1);
3013 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3017 static void add_random_mac_if_needed(struct bnxt *bp,
3018 struct hwrm_func_cfg_input *cfg_req,
3021 struct rte_ether_addr mac;
3023 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3026 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3028 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3029 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3030 bp->pf.vf_info[vf].random_mac = true;
3032 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3033 RTE_ETHER_ADDR_LEN);
3037 static void reserve_resources_from_vf(struct bnxt *bp,
3038 struct hwrm_func_cfg_input *cfg_req,
3041 struct hwrm_func_qcaps_input req = {0};
3042 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3045 /* Get the actual allocated values now */
3046 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3047 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3048 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3051 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3052 copy_func_cfg_to_qcaps(cfg_req, resp);
3053 } else if (resp->error_code) {
3054 rc = rte_le_to_cpu_16(resp->error_code);
3055 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3056 copy_func_cfg_to_qcaps(cfg_req, resp);
3059 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3060 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3061 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3062 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3063 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3064 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3066 * TODO: While not supporting VMDq with VFs, max_vnics is always
3067 * forced to 1 in this case
3069 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3070 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3075 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3077 struct hwrm_func_qcfg_input req = {0};
3078 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3081 /* Check for zero MAC address */
3082 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3083 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3084 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3085 HWRM_CHECK_RESULT();
3086 rc = rte_le_to_cpu_16(resp->vlan);
3093 static int update_pf_resource_max(struct bnxt *bp)
3095 struct hwrm_func_qcfg_input req = {0};
3096 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3099 /* And copy the allocated numbers into the pf struct */
3100 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3101 req.fid = rte_cpu_to_le_16(0xffff);
3102 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3103 HWRM_CHECK_RESULT();
3105 /* Only TX ring value reflects actual allocation? TODO */
3106 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3107 bp->pf.evb_mode = resp->evb_mode;
3114 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3119 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3123 rc = bnxt_hwrm_func_qcaps(bp);
3127 bp->pf.func_cfg_flags &=
3128 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3129 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3130 bp->pf.func_cfg_flags |=
3131 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3132 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3133 rc = __bnxt_hwrm_func_qcaps(bp);
3137 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3139 struct hwrm_func_cfg_input req = {0};
3140 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3147 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3151 rc = bnxt_hwrm_func_qcaps(bp);
3156 bp->pf.active_vfs = num_vfs;
3159 * First, configure the PF to only use one TX ring. This ensures that
3160 * there are enough rings for all VFs.
3162 * If we don't do this, when we call func_alloc() later, we will lock
3163 * extra rings to the PF that won't be available during func_cfg() of
3166 * This has been fixed with firmware versions above 20.6.54
3168 bp->pf.func_cfg_flags &=
3169 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3170 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3171 bp->pf.func_cfg_flags |=
3172 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3173 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3178 * Now, create and register a buffer to hold forwarded VF requests
3180 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3181 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3182 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3183 if (bp->pf.vf_req_buf == NULL) {
3187 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3188 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3189 for (i = 0; i < num_vfs; i++)
3190 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3191 (i * HWRM_MAX_REQ_LEN);
3193 rc = bnxt_hwrm_func_buf_rgtr(bp);
3197 populate_vf_func_cfg_req(bp, &req, num_vfs);
3199 bp->pf.active_vfs = 0;
3200 for (i = 0; i < num_vfs; i++) {
3201 add_random_mac_if_needed(bp, &req, i);
3203 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3204 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3205 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3206 rc = bnxt_hwrm_send_message(bp,
3211 /* Clear enable flag for next pass */
3212 req.enables &= ~rte_cpu_to_le_32(
3213 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3215 if (rc || resp->error_code) {
3217 "Failed to initizlie VF %d\n", i);
3219 "Not all VFs available. (%d, %d)\n",
3220 rc, resp->error_code);
3227 reserve_resources_from_vf(bp, &req, i);
3228 bp->pf.active_vfs++;
3229 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3233 * Now configure the PF to use "the rest" of the resources
3234 * We're using STD_TX_RING_MODE here though which will limit the TX
3235 * rings. This will allow QoS to function properly. Not setting this
3236 * will cause PF rings to break bandwidth settings.
3238 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3242 rc = update_pf_resource_max(bp);
3249 bnxt_hwrm_func_buf_unrgtr(bp);
3253 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3255 struct hwrm_func_cfg_input req = {0};
3256 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3259 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3261 req.fid = rte_cpu_to_le_16(0xffff);
3262 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3263 req.evb_mode = bp->pf.evb_mode;
3265 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3266 HWRM_CHECK_RESULT();
3272 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3273 uint8_t tunnel_type)
3275 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3276 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3279 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3280 req.tunnel_type = tunnel_type;
3281 req.tunnel_dst_port_val = port;
3282 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3283 HWRM_CHECK_RESULT();
3285 switch (tunnel_type) {
3286 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3287 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3288 bp->vxlan_port = port;
3290 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3291 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3292 bp->geneve_port = port;
3303 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3304 uint8_t tunnel_type)
3306 struct hwrm_tunnel_dst_port_free_input req = {0};
3307 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3310 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3312 req.tunnel_type = tunnel_type;
3313 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3314 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3316 HWRM_CHECK_RESULT();
3322 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3325 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3326 struct hwrm_func_cfg_input req = {0};
3329 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3331 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3332 req.flags = rte_cpu_to_le_32(flags);
3333 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3335 HWRM_CHECK_RESULT();
3341 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3343 uint32_t *flag = flagp;
3345 vnic->flags = *flag;
3348 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3350 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3353 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3356 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3357 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3359 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3361 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3362 req.req_buf_page_size = rte_cpu_to_le_16(
3363 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3364 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3365 req.req_buf_page_addr0 =
3366 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3367 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3369 "unable to map buffer address to physical memory\n");
3373 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3375 HWRM_CHECK_RESULT();
3381 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3384 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3385 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3387 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3390 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3392 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3394 HWRM_CHECK_RESULT();
3400 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3402 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3403 struct hwrm_func_cfg_input req = {0};
3406 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3408 req.fid = rte_cpu_to_le_16(0xffff);
3409 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3410 req.enables = rte_cpu_to_le_32(
3411 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3412 req.async_event_cr = rte_cpu_to_le_16(
3413 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3414 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3416 HWRM_CHECK_RESULT();
3422 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3424 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3425 struct hwrm_func_vf_cfg_input req = {0};
3428 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3430 req.enables = rte_cpu_to_le_32(
3431 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3432 req.async_event_cr = rte_cpu_to_le_16(
3433 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3434 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3436 HWRM_CHECK_RESULT();
3442 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3444 struct hwrm_func_cfg_input req = {0};
3445 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3446 uint16_t dflt_vlan, fid;
3447 uint32_t func_cfg_flags;
3450 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3453 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3454 fid = bp->pf.vf_info[vf].fid;
3455 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3457 fid = rte_cpu_to_le_16(0xffff);
3458 func_cfg_flags = bp->pf.func_cfg_flags;
3459 dflt_vlan = bp->vlan;
3462 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3463 req.fid = rte_cpu_to_le_16(fid);
3464 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3465 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3467 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3469 HWRM_CHECK_RESULT();
3475 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3476 uint16_t max_bw, uint16_t enables)
3478 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3479 struct hwrm_func_cfg_input req = {0};
3482 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3484 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3485 req.enables |= rte_cpu_to_le_32(enables);
3486 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3487 req.max_bw = rte_cpu_to_le_32(max_bw);
3488 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3490 HWRM_CHECK_RESULT();
3496 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3498 struct hwrm_func_cfg_input req = {0};
3499 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3502 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3504 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3505 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3506 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3507 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3509 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3511 HWRM_CHECK_RESULT();
3517 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3522 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3524 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3529 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3530 void *encaped, size_t ec_size)
3533 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3534 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3536 if (ec_size > sizeof(req.encap_request))
3539 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3541 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3542 memcpy(req.encap_request, encaped, ec_size);
3544 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3546 HWRM_CHECK_RESULT();
3552 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3553 struct rte_ether_addr *mac)
3555 struct hwrm_func_qcfg_input req = {0};
3556 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3559 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3561 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3562 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3564 HWRM_CHECK_RESULT();
3566 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3573 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3574 void *encaped, size_t ec_size)
3577 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3578 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3580 if (ec_size > sizeof(req.encap_request))
3583 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3585 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3586 memcpy(req.encap_request, encaped, ec_size);
3588 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3590 HWRM_CHECK_RESULT();
3596 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3597 struct rte_eth_stats *stats, uint8_t rx)
3600 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3601 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3603 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3605 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3607 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3609 HWRM_CHECK_RESULT();
3612 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3613 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3614 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3615 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3616 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3617 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3618 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3619 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3621 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3622 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3623 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3624 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3625 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3626 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3635 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3637 struct hwrm_port_qstats_input req = {0};
3638 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3639 struct bnxt_pf_info *pf = &bp->pf;
3642 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3644 req.port_id = rte_cpu_to_le_16(pf->port_id);
3645 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3646 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3647 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3649 HWRM_CHECK_RESULT();
3655 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3657 struct hwrm_port_clr_stats_input req = {0};
3658 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3659 struct bnxt_pf_info *pf = &bp->pf;
3662 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3663 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3664 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3667 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3669 req.port_id = rte_cpu_to_le_16(pf->port_id);
3670 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3672 HWRM_CHECK_RESULT();
3678 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3680 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3681 struct hwrm_port_led_qcaps_input req = {0};
3687 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3688 req.port_id = bp->pf.port_id;
3689 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3691 HWRM_CHECK_RESULT();
3693 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3696 bp->num_leds = resp->num_leds;
3697 memcpy(bp->leds, &resp->led0_id,
3698 sizeof(bp->leds[0]) * bp->num_leds);
3699 for (i = 0; i < bp->num_leds; i++) {
3700 struct bnxt_led_info *led = &bp->leds[i];
3702 uint16_t caps = led->led_state_caps;
3704 if (!led->led_group_id ||
3705 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3717 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3719 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3720 struct hwrm_port_led_cfg_input req = {0};
3721 struct bnxt_led_cfg *led_cfg;
3722 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3723 uint16_t duration = 0;
3726 if (!bp->num_leds || BNXT_VF(bp))
3729 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3732 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3733 duration = rte_cpu_to_le_16(500);
3735 req.port_id = bp->pf.port_id;
3736 req.num_leds = bp->num_leds;
3737 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3738 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3739 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3740 led_cfg->led_id = bp->leds[i].led_id;
3741 led_cfg->led_state = led_state;
3742 led_cfg->led_blink_on = duration;
3743 led_cfg->led_blink_off = duration;
3744 led_cfg->led_group_id = bp->leds[i].led_group_id;
3747 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3749 HWRM_CHECK_RESULT();
3755 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3759 struct hwrm_nvm_get_dir_info_input req = {0};
3760 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3762 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3764 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3766 HWRM_CHECK_RESULT();
3768 *entries = rte_le_to_cpu_32(resp->entries);
3769 *length = rte_le_to_cpu_32(resp->entry_length);
3775 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3778 uint32_t dir_entries;
3779 uint32_t entry_length;
3782 rte_iova_t dma_handle;
3783 struct hwrm_nvm_get_dir_entries_input req = {0};
3784 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3786 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3790 *data++ = dir_entries;
3791 *data++ = entry_length;
3793 memset(data, 0xff, len);
3795 buflen = dir_entries * entry_length;
3796 buf = rte_malloc("nvm_dir", buflen, 0);
3797 rte_mem_lock_page(buf);
3800 dma_handle = rte_mem_virt2iova(buf);
3801 if (dma_handle == RTE_BAD_IOVA) {
3803 "unable to map response address to physical memory\n");
3806 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3807 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3808 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3811 memcpy(data, buf, len > buflen ? buflen : len);
3814 HWRM_CHECK_RESULT();
3820 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3821 uint32_t offset, uint32_t length,
3826 rte_iova_t dma_handle;
3827 struct hwrm_nvm_read_input req = {0};
3828 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3830 buf = rte_malloc("nvm_item", length, 0);
3831 rte_mem_lock_page(buf);
3835 dma_handle = rte_mem_virt2iova(buf);
3836 if (dma_handle == RTE_BAD_IOVA) {
3838 "unable to map response address to physical memory\n");
3841 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3842 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3843 req.dir_idx = rte_cpu_to_le_16(index);
3844 req.offset = rte_cpu_to_le_32(offset);
3845 req.len = rte_cpu_to_le_32(length);
3846 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3848 memcpy(data, buf, length);
3851 HWRM_CHECK_RESULT();
3857 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3860 struct hwrm_nvm_erase_dir_entry_input req = {0};
3861 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3863 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3864 req.dir_idx = rte_cpu_to_le_16(index);
3865 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3866 HWRM_CHECK_RESULT();
3873 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3874 uint16_t dir_ordinal, uint16_t dir_ext,
3875 uint16_t dir_attr, const uint8_t *data,
3879 struct hwrm_nvm_write_input req = {0};
3880 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3881 rte_iova_t dma_handle;
3884 buf = rte_malloc("nvm_write", data_len, 0);
3885 rte_mem_lock_page(buf);
3889 dma_handle = rte_mem_virt2iova(buf);
3890 if (dma_handle == RTE_BAD_IOVA) {
3892 "unable to map response address to physical memory\n");
3895 memcpy(buf, data, data_len);
3897 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3899 req.dir_type = rte_cpu_to_le_16(dir_type);
3900 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3901 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3902 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3903 req.dir_data_length = rte_cpu_to_le_32(data_len);
3904 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3906 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3909 HWRM_CHECK_RESULT();
3916 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3918 uint32_t *count = cbdata;
3920 *count = *count + 1;
3923 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3924 struct bnxt_vnic_info *vnic __rte_unused)
3929 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3933 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3934 &count, bnxt_vnic_count_hwrm_stub);
3939 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3942 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3943 struct hwrm_func_vf_vnic_ids_query_output *resp =
3944 bp->hwrm_cmd_resp_addr;
3947 /* First query all VNIC ids */
3948 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3950 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3951 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3952 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3954 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3957 "unable to map VNIC ID table address to physical memory\n");
3960 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3961 HWRM_CHECK_RESULT();
3962 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3970 * This function queries the VNIC IDs for a specified VF. It then calls
3971 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3972 * Then it calls the hwrm_cb function to program this new vnic configuration.
3974 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3975 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3976 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3978 struct bnxt_vnic_info vnic;
3980 int i, num_vnic_ids;
3985 /* First query all VNIC ids */
3986 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3987 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3988 RTE_CACHE_LINE_SIZE);
3989 if (vnic_ids == NULL)
3992 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3993 rte_mem_lock_page(((char *)vnic_ids) + sz);
3995 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3997 if (num_vnic_ids < 0)
3998 return num_vnic_ids;
4000 /* Retrieve VNIC, update bd_stall then update */
4002 for (i = 0; i < num_vnic_ids; i++) {
4003 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4004 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4005 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4008 if (vnic.mru <= 4) /* Indicates unallocated */
4011 vnic_cb(&vnic, cbdata);
4013 rc = hwrm_cb(bp, &vnic);
4023 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4026 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4027 struct hwrm_func_cfg_input req = {0};
4030 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4032 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4033 req.enables |= rte_cpu_to_le_32(
4034 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4035 req.vlan_antispoof_mode = on ?
4036 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4037 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4038 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4040 HWRM_CHECK_RESULT();
4046 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4048 struct bnxt_vnic_info vnic;
4051 int num_vnic_ids, i;
4055 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4056 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4057 RTE_CACHE_LINE_SIZE);
4058 if (vnic_ids == NULL)
4061 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4062 rte_mem_lock_page(((char *)vnic_ids) + sz);
4064 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4070 * Loop through to find the default VNIC ID.
4071 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4072 * by sending the hwrm_func_qcfg command to the firmware.
4074 for (i = 0; i < num_vnic_ids; i++) {
4075 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4076 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4077 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4078 bp->pf.first_vf_id + vf);
4081 if (vnic.func_default) {
4083 return vnic.fw_vnic_id;
4086 /* Could not find a default VNIC. */
4087 PMD_DRV_LOG(ERR, "No default VNIC\n");
4093 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4095 struct bnxt_filter_info *filter)
4098 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4099 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4100 uint32_t enables = 0;
4102 if (filter->fw_em_filter_id != UINT64_MAX)
4103 bnxt_hwrm_clear_em_filter(bp, filter);
4105 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4107 req.flags = rte_cpu_to_le_32(filter->flags);
4109 enables = filter->enables |
4110 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4111 req.dst_id = rte_cpu_to_le_16(dst_id);
4113 if (filter->ip_addr_type) {
4114 req.ip_addr_type = filter->ip_addr_type;
4115 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4118 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4119 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4121 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4122 memcpy(req.src_macaddr, filter->src_macaddr,
4123 RTE_ETHER_ADDR_LEN);
4125 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4126 memcpy(req.dst_macaddr, filter->dst_macaddr,
4127 RTE_ETHER_ADDR_LEN);
4129 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4130 req.ovlan_vid = filter->l2_ovlan;
4132 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4133 req.ivlan_vid = filter->l2_ivlan;
4135 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4136 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4138 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4139 req.ip_protocol = filter->ip_protocol;
4141 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4142 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4144 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4145 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4147 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4148 req.src_port = rte_cpu_to_be_16(filter->src_port);
4150 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4151 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4153 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4154 req.mirror_vnic_id = filter->mirror_vnic_id;
4156 req.enables = rte_cpu_to_le_32(enables);
4158 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4160 HWRM_CHECK_RESULT();
4162 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4168 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4171 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4172 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4174 if (filter->fw_em_filter_id == UINT64_MAX)
4177 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4178 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4180 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4182 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4184 HWRM_CHECK_RESULT();
4187 filter->fw_em_filter_id = UINT64_MAX;
4188 filter->fw_l2_filter_id = UINT64_MAX;
4193 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4195 struct bnxt_filter_info *filter)
4198 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4199 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4200 bp->hwrm_cmd_resp_addr;
4201 uint32_t enables = 0;
4203 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4204 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4206 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4208 req.flags = rte_cpu_to_le_32(filter->flags);
4210 enables = filter->enables |
4211 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4212 req.dst_id = rte_cpu_to_le_16(dst_id);
4215 if (filter->ip_addr_type) {
4216 req.ip_addr_type = filter->ip_addr_type;
4218 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4221 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4222 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4224 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4225 memcpy(req.src_macaddr, filter->src_macaddr,
4226 RTE_ETHER_ADDR_LEN);
4228 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4229 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4230 //RTE_ETHER_ADDR_LEN);
4232 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4233 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4235 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4236 req.ip_protocol = filter->ip_protocol;
4238 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4239 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4241 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4242 req.src_ipaddr_mask[0] =
4243 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4245 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4246 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4248 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4249 req.dst_ipaddr_mask[0] =
4250 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4252 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4253 req.src_port = rte_cpu_to_le_16(filter->src_port);
4255 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4256 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4258 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4259 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4261 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4262 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4264 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4265 req.mirror_vnic_id = filter->mirror_vnic_id;
4267 req.enables = rte_cpu_to_le_32(enables);
4269 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4271 HWRM_CHECK_RESULT();
4273 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4279 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4280 struct bnxt_filter_info *filter)
4283 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4284 struct hwrm_cfa_ntuple_filter_free_output *resp =
4285 bp->hwrm_cmd_resp_addr;
4287 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4290 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4292 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4294 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4296 HWRM_CHECK_RESULT();
4299 filter->fw_ntuple_filter_id = UINT64_MAX;
4305 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4307 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4308 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4309 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4310 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4311 uint16_t *ring_tbl = vnic->rss_table;
4312 int nr_ctxs = vnic->num_lb_ctxts;
4313 int max_rings = bp->rx_nr_rings;
4317 for (i = 0, k = 0; i < nr_ctxs; i++) {
4318 struct bnxt_rx_ring_info *rxr;
4319 struct bnxt_cp_ring_info *cpr;
4321 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4323 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4324 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4325 req.hash_mode_flags = vnic->hash_mode;
4327 req.ring_grp_tbl_addr =
4328 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4329 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4330 2 * sizeof(*ring_tbl));
4331 req.hash_key_tbl_addr =
4332 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4334 req.ring_table_pair_index = i;
4335 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4337 for (j = 0; j < 64; j++) {
4340 /* Find next active ring. */
4341 for (cnt = 0; cnt < max_rings; cnt++) {
4342 if (rx_queue_state[k] !=
4343 RTE_ETH_QUEUE_STATE_STOPPED)
4345 if (++k == max_rings)
4349 /* Return if no rings are active. */
4350 if (cnt == max_rings)
4353 /* Add rx/cp ring pair to RSS table. */
4354 rxr = rxqs[k]->rx_ring;
4355 cpr = rxqs[k]->cp_ring;
4357 ring_id = rxr->rx_ring_struct->fw_ring_id;
4358 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4359 ring_id = cpr->cp_ring_struct->fw_ring_id;
4360 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4362 if (++k == max_rings)
4365 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4368 HWRM_CHECK_RESULT();
4375 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4377 unsigned int rss_idx, fw_idx, i;
4379 if (!(vnic->rss_table && vnic->hash_type))
4382 if (BNXT_CHIP_THOR(bp))
4383 return bnxt_vnic_rss_configure_thor(bp, vnic);
4385 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4388 if (vnic->rss_table && vnic->hash_type) {
4390 * Fill the RSS hash & redirection table with
4391 * ring group ids for all VNICs
4393 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4394 rss_idx++, fw_idx++) {
4395 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4396 fw_idx %= bp->rx_cp_nr_rings;
4397 if (vnic->fw_grp_ids[fw_idx] !=
4402 if (i == bp->rx_cp_nr_rings)
4404 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4406 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4412 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4413 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4417 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4419 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4420 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4422 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4423 req->num_cmpl_dma_aggr_during_int =
4424 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4426 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4428 /* min timer set to 1/2 of interrupt timer */
4429 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4431 /* buf timer set to 1/4 of interrupt timer */
4432 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4434 req->cmpl_aggr_dma_tmr_during_int =
4435 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4437 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4438 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4439 req->flags = rte_cpu_to_le_16(flags);
4442 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4443 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4445 struct hwrm_ring_aggint_qcaps_input req = {0};
4446 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4451 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4452 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4453 HWRM_CHECK_RESULT();
4455 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4456 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4458 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4459 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4460 agg_req->flags = rte_cpu_to_le_16(flags);
4462 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4463 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4464 agg_req->enables = rte_cpu_to_le_32(enables);
4470 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4471 struct bnxt_coal *coal, uint16_t ring_id)
4473 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4474 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4475 bp->hwrm_cmd_resp_addr;
4478 /* Set ring coalesce parameters only for 100G NICs */
4479 if (BNXT_CHIP_THOR(bp)) {
4480 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4482 } else if (bnxt_stratus_device(bp)) {
4483 bnxt_hwrm_set_coal_params(coal, &req);
4488 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4489 req.ring_id = rte_cpu_to_le_16(ring_id);
4490 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4491 HWRM_CHECK_RESULT();
4496 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4497 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4499 struct hwrm_func_backing_store_qcaps_input req = {0};
4500 struct hwrm_func_backing_store_qcaps_output *resp =
4501 bp->hwrm_cmd_resp_addr;
4502 struct bnxt_ctx_pg_info *ctx_pg;
4503 struct bnxt_ctx_mem_info *ctx;
4504 int total_alloc_len;
4507 if (!BNXT_CHIP_THOR(bp) ||
4508 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4513 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4514 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4515 HWRM_CHECK_RESULT_SILENT();
4517 total_alloc_len = sizeof(*ctx);
4518 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4519 RTE_CACHE_LINE_SIZE);
4525 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4526 sizeof(*ctx_pg) * BNXT_MAX_Q,
4527 RTE_CACHE_LINE_SIZE);
4532 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4533 ctx->tqm_mem[i] = ctx_pg;
4536 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4537 ctx->qp_min_qp1_entries =
4538 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4539 ctx->qp_max_l2_entries =
4540 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4541 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4542 ctx->srq_max_l2_entries =
4543 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4544 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4545 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4546 ctx->cq_max_l2_entries =
4547 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4548 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4549 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4550 ctx->vnic_max_vnic_entries =
4551 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4552 ctx->vnic_max_ring_table_entries =
4553 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4554 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4555 ctx->stat_max_entries =
4556 rte_le_to_cpu_32(resp->stat_max_entries);
4557 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4558 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4559 ctx->tqm_min_entries_per_ring =
4560 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4561 ctx->tqm_max_entries_per_ring =
4562 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4563 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4564 if (!ctx->tqm_entries_multiple)
4565 ctx->tqm_entries_multiple = 1;
4566 ctx->mrav_max_entries =
4567 rte_le_to_cpu_32(resp->mrav_max_entries);
4568 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4569 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4570 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4576 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4578 struct hwrm_func_backing_store_cfg_input req = {0};
4579 struct hwrm_func_backing_store_cfg_output *resp =
4580 bp->hwrm_cmd_resp_addr;
4581 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4582 struct bnxt_ctx_pg_info *ctx_pg;
4583 uint32_t *num_entries;
4592 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4593 req.enables = rte_cpu_to_le_32(enables);
4595 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4596 ctx_pg = &ctx->qp_mem;
4597 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4598 req.qp_num_qp1_entries =
4599 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4600 req.qp_num_l2_entries =
4601 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4602 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4603 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4604 &req.qpc_pg_size_qpc_lvl,
4608 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4609 ctx_pg = &ctx->srq_mem;
4610 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4611 req.srq_num_l2_entries =
4612 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4613 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4614 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4615 &req.srq_pg_size_srq_lvl,
4619 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4620 ctx_pg = &ctx->cq_mem;
4621 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4622 req.cq_num_l2_entries =
4623 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4624 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4625 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4626 &req.cq_pg_size_cq_lvl,
4630 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4631 ctx_pg = &ctx->vnic_mem;
4632 req.vnic_num_vnic_entries =
4633 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4634 req.vnic_num_ring_table_entries =
4635 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4636 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4637 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4638 &req.vnic_pg_size_vnic_lvl,
4639 &req.vnic_page_dir);
4642 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4643 ctx_pg = &ctx->stat_mem;
4644 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4645 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4646 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4647 &req.stat_pg_size_stat_lvl,
4648 &req.stat_page_dir);
4651 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4652 num_entries = &req.tqm_sp_num_entries;
4653 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4654 pg_dir = &req.tqm_sp_page_dir;
4655 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4656 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4657 if (!(enables & ena))
4660 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4662 ctx_pg = ctx->tqm_mem[i];
4663 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4664 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4667 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4668 HWRM_CHECK_RESULT();
4674 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4676 struct hwrm_port_qstats_ext_input req = {0};
4677 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4678 struct bnxt_pf_info *pf = &bp->pf;
4681 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4682 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4685 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4687 req.port_id = rte_cpu_to_le_16(pf->port_id);
4688 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4689 req.tx_stat_host_addr =
4690 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4692 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4694 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4695 req.rx_stat_host_addr =
4696 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4698 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4700 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4703 bp->fw_rx_port_stats_ext_size = 0;
4704 bp->fw_tx_port_stats_ext_size = 0;
4706 bp->fw_rx_port_stats_ext_size =
4707 rte_le_to_cpu_16(resp->rx_stat_size);
4708 bp->fw_tx_port_stats_ext_size =
4709 rte_le_to_cpu_16(resp->tx_stat_size);
4712 HWRM_CHECK_RESULT();
4719 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4721 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4722 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4723 bp->hwrm_cmd_resp_addr;
4726 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4727 req.tunnel_type = type;
4728 req.dest_fid = bp->fw_fid;
4729 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4730 HWRM_CHECK_RESULT();
4738 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4740 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4741 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4742 bp->hwrm_cmd_resp_addr;
4745 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4746 req.tunnel_type = type;
4747 req.dest_fid = bp->fw_fid;
4748 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4749 HWRM_CHECK_RESULT();
4756 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4758 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4759 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4760 bp->hwrm_cmd_resp_addr;
4763 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4764 req.src_fid = bp->fw_fid;
4765 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4766 HWRM_CHECK_RESULT();
4769 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4776 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4779 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4780 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4781 bp->hwrm_cmd_resp_addr;
4784 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4785 req.src_fid = bp->fw_fid;
4786 req.tunnel_type = tun_type;
4787 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4788 HWRM_CHECK_RESULT();
4791 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4793 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4800 int bnxt_hwrm_set_mac(struct bnxt *bp)
4802 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4803 struct hwrm_func_vf_cfg_input req = {0};
4809 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4812 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4813 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4815 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4817 HWRM_CHECK_RESULT();
4819 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4825 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4827 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4828 struct hwrm_func_drv_if_change_input req = {0};
4832 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4835 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4836 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4837 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4839 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4842 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4846 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4848 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4850 HWRM_CHECK_RESULT();
4851 flags = rte_le_to_cpu_32(resp->flags);
4854 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4855 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4856 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4862 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4864 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4865 struct bnxt_error_recovery_info *info = bp->recovery_info;
4866 struct hwrm_error_recovery_qcfg_input req = {0};
4871 /* Older FW does not have error recovery support */
4872 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4876 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4878 bp->recovery_info = info;
4882 memset(info, 0, sizeof(*info));
4885 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4887 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4889 HWRM_CHECK_RESULT();
4891 flags = rte_le_to_cpu_32(resp->flags);
4892 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4893 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4894 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4895 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4897 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4898 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4903 /* FW returned values are in units of 100msec */
4904 info->driver_polling_freq =
4905 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4906 info->master_func_wait_period =
4907 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4908 info->normal_func_wait_period =
4909 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4910 info->master_func_wait_period_after_reset =
4911 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4912 info->max_bailout_time_after_reset =
4913 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4914 info->status_regs[BNXT_FW_STATUS_REG] =
4915 rte_le_to_cpu_32(resp->fw_health_status_reg);
4916 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4917 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4918 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4919 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4920 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4921 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4922 info->reg_array_cnt =
4923 rte_le_to_cpu_32(resp->reg_array_cnt);
4925 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4930 for (i = 0; i < info->reg_array_cnt; i++) {
4931 info->reset_reg[i] =
4932 rte_le_to_cpu_32(resp->reset_reg[i]);
4933 info->reset_reg_val[i] =
4934 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4935 info->delay_after_reset[i] =
4936 resp->delay_after_reset[i];
4941 /* Map the FW status registers */
4943 rc = bnxt_map_fw_health_status_regs(bp);
4946 rte_free(bp->recovery_info);
4947 bp->recovery_info = NULL;
4952 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4954 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4955 struct hwrm_fw_reset_input req = {0};
4961 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4963 req.embedded_proc_type =
4964 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4965 req.selfrst_status =
4966 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4967 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4969 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4972 HWRM_CHECK_RESULT();
4978 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4980 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4981 struct hwrm_port_ts_query_input req = {0};
4982 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4989 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4992 case BNXT_PTP_FLAGS_PATH_TX:
4993 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4995 case BNXT_PTP_FLAGS_PATH_RX:
4996 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4998 case BNXT_PTP_FLAGS_CURRENT_TIME:
4999 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5003 req.flags = rte_cpu_to_le_32(flags);
5004 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5006 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5008 HWRM_CHECK_RESULT();
5011 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5013 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5020 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5022 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5023 bp->hwrm_cmd_resp_addr;
5024 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5028 if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5031 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5033 "Not a PF or trusted VF. Command not supported\n");
5037 HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5038 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5040 HWRM_CHECK_RESULT();
5041 flags = rte_le_to_cpu_32(resp->flags);
5044 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5045 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5046 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");