4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <rte_byteorder.h>
37 #include <rte_common.h>
38 #include <rte_cycles.h>
39 #include <rte_malloc.h>
40 #include <rte_memzone.h>
41 #include <rte_version.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
49 #include "bnxt_ring.h"
52 #include "bnxt_vnic.h"
53 #include "hsi_struct_def_dpdk.h"
57 #define HWRM_CMD_TIMEOUT 10000
59 struct bnxt_plcmodes_cfg {
61 uint16_t jumbo_thresh;
63 uint16_t hds_threshold;
66 static int page_getenum(size_t size)
82 RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
83 return sizeof(void *) * 8 - 1;
86 static int page_roundup(size_t size)
88 return 1 << page_getenum(size);
92 * HWRM Functions (sent to HWRM)
93 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
94 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
95 * command was failed by the ChiMP.
98 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
102 struct input *req = msg;
103 struct output *resp = bp->hwrm_cmd_resp_addr;
104 uint32_t *data = msg;
107 uint16_t max_req_len = bp->max_req_len;
108 struct hwrm_short_input short_input = { 0 };
110 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
111 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
113 memset(short_cmd_req, 0, bp->max_req_len);
114 memcpy(short_cmd_req, req, msg_len);
116 short_input.req_type = rte_cpu_to_le_16(req->req_type);
117 short_input.signature = rte_cpu_to_le_16(
118 HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
119 short_input.size = rte_cpu_to_le_16(msg_len);
120 short_input.req_addr =
121 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
123 data = (uint32_t *)&short_input;
124 msg_len = sizeof(short_input);
126 /* Sync memory write before updating doorbell */
129 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
132 /* Write request msg to hwrm channel */
133 for (i = 0; i < msg_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + i;
135 rte_write32(*data, bar);
139 /* Zero the rest of the request space */
140 for (; i < max_req_len; i += 4) {
141 bar = (uint8_t *)bp->bar0 + i;
145 /* Ring channel doorbell */
146 bar = (uint8_t *)bp->bar0 + 0x100;
149 /* Poll for the valid bit */
150 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
151 /* Sanity check on the resp->resp_len */
153 if (resp->resp_len && resp->resp_len <=
155 /* Last byte of resp contains the valid key */
156 valid = (uint8_t *)resp + resp->resp_len - 1;
157 if (*valid == HWRM_RESP_VALID_KEY)
163 if (i >= HWRM_CMD_TIMEOUT) {
164 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
175 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
176 * spinlock, and does initial processing.
178 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
179 * releases the spinlock only if it returns. If the regular int return codes
180 * are not used by the function, HWRM_CHECK_RESULT() should not be used
181 * directly, rather it should be copied and modified to suit the function.
183 * HWRM_UNLOCK() must be called after all response processing is completed.
185 #define HWRM_PREP(req, type) do { \
186 rte_spinlock_lock(&bp->hwrm_lock); \
187 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
188 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
189 req.cmpl_ring = rte_cpu_to_le_16(-1); \
190 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
191 req.target_id = rte_cpu_to_le_16(0xffff); \
192 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
195 #define HWRM_CHECK_RESULT() do {\
197 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
199 rte_spinlock_unlock(&bp->hwrm_lock); \
202 if (resp->error_code) { \
203 rc = rte_le_to_cpu_16(resp->error_code); \
204 if (resp->resp_len >= 16) { \
205 struct hwrm_err_output *tmp_hwrm_err_op = \
208 "%s error %d:%d:%08x:%04x\n", \
210 rc, tmp_hwrm_err_op->cmd_err, \
212 tmp_hwrm_err_op->opaque_0), \
214 tmp_hwrm_err_op->opaque_1)); \
218 "%s error %d\n", __func__, rc); \
220 rte_spinlock_unlock(&bp->hwrm_lock); \
225 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
227 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
230 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
231 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
233 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
234 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
237 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
245 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
246 struct bnxt_vnic_info *vnic,
248 struct bnxt_vlan_table_entry *vlan_table)
251 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
252 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
255 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
256 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
258 /* FIXME add multicast flag, when multicast adding options is supported
261 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
262 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
263 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
264 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
265 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
266 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
267 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
268 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
269 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
270 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
271 if (vnic->mc_addr_cnt) {
272 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
273 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
274 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
277 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
278 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
279 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
280 rte_mem_virt2phy(vlan_table));
281 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
283 req.mask = rte_cpu_to_le_32(mask);
285 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
293 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
295 struct bnxt_vlan_antispoof_table_entry *vlan_table)
298 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
299 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
300 bp->hwrm_cmd_resp_addr;
303 * Older HWRM versions did not support this command, and the set_rx_mask
304 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
305 * removed from set_rx_mask call, and this command was added.
307 * This command is also present from 1.7.8.11 and higher,
310 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
311 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
312 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
317 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
318 req.fid = rte_cpu_to_le_16(fid);
320 req.vlan_tag_mask_tbl_addr =
321 rte_cpu_to_le_64(rte_mem_virt2phy(vlan_table));
322 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
324 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
332 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
333 struct bnxt_filter_info *filter)
336 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
337 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
339 if (filter->fw_l2_filter_id == UINT64_MAX)
342 HWRM_PREP(req, CFA_L2_FILTER_FREE);
344 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
346 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
351 filter->fw_l2_filter_id = -1;
356 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
358 struct bnxt_filter_info *filter)
361 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
362 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
363 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
364 const struct rte_eth_vmdq_rx_conf *conf =
365 &dev_conf->rx_adv_conf.vmdq_rx_conf;
366 uint32_t enables = 0;
367 uint16_t j = dst_id - 1;
369 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
370 if (conf->pool_map[j].pools & (1UL << j)) {
372 "Add vlan %u to vmdq pool %u\n",
373 conf->pool_map[j].vlan_id, j);
375 filter->l2_ivlan = conf->pool_map[j].vlan_id;
377 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
378 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
381 if (filter->fw_l2_filter_id != UINT64_MAX)
382 bnxt_hwrm_clear_l2_filter(bp, filter);
384 HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
386 req.flags = rte_cpu_to_le_32(filter->flags);
388 enables = filter->enables |
389 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
390 req.dst_id = rte_cpu_to_le_16(dst_id);
393 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
394 memcpy(req.l2_addr, filter->l2_addr,
397 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
398 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
401 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
402 req.l2_ovlan = filter->l2_ovlan;
404 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
405 req.l2_ovlan = filter->l2_ivlan;
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
408 req.l2_ovlan_mask = filter->l2_ovlan_mask;
410 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
411 req.l2_ovlan_mask = filter->l2_ivlan_mask;
412 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
413 req.src_id = rte_cpu_to_le_32(filter->src_id);
414 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
415 req.src_type = filter->src_type;
417 req.enables = rte_cpu_to_le_32(enables);
419 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
423 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
429 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
432 struct hwrm_func_qcaps_input req = {.req_type = 0 };
433 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
434 uint16_t new_max_vfs;
437 HWRM_PREP(req, FUNC_QCAPS);
439 req.fid = rte_cpu_to_le_16(0xffff);
441 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
445 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
447 bp->pf.port_id = resp->port_id;
448 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
449 new_max_vfs = bp->pdev->max_vfs;
450 if (new_max_vfs != bp->pf.max_vfs) {
452 rte_free(bp->pf.vf_info);
453 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
454 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
455 bp->pf.max_vfs = new_max_vfs;
456 for (i = 0; i < new_max_vfs; i++) {
457 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
458 bp->pf.vf_info[i].vlan_table =
459 rte_zmalloc("VF VLAN table",
462 if (bp->pf.vf_info[i].vlan_table == NULL)
464 "Fail to alloc VLAN table for VF %d\n",
468 bp->pf.vf_info[i].vlan_table);
469 bp->pf.vf_info[i].vlan_as_table =
470 rte_zmalloc("VF VLAN AS table",
473 if (bp->pf.vf_info[i].vlan_as_table == NULL)
475 "Alloc VLAN AS table for VF %d fail\n",
479 bp->pf.vf_info[i].vlan_as_table);
480 STAILQ_INIT(&bp->pf.vf_info[i].filter);
485 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
486 memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
487 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
488 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
489 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
490 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
491 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
492 /* TODO: For now, do not support VMDq/RFS on VFs. */
497 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
501 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
503 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
509 int bnxt_hwrm_func_reset(struct bnxt *bp)
512 struct hwrm_func_reset_input req = {.req_type = 0 };
513 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
515 HWRM_PREP(req, FUNC_RESET);
517 req.enables = rte_cpu_to_le_32(0);
519 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
527 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
530 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
531 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
533 if (bp->flags & BNXT_FLAG_REGISTERED)
536 HWRM_PREP(req, FUNC_DRV_RGTR);
537 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
538 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
539 req.ver_maj = RTE_VER_YEAR;
540 req.ver_min = RTE_VER_MONTH;
541 req.ver_upd = RTE_VER_MINOR;
544 req.enables |= rte_cpu_to_le_32(
545 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
546 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
547 RTE_MIN(sizeof(req.vf_req_fwd),
548 sizeof(bp->pf.vf_req_fwd)));
551 req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1); /* TODO: Use MACRO */
552 memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
554 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
559 bp->flags |= BNXT_FLAG_REGISTERED;
564 int bnxt_hwrm_ver_get(struct bnxt *bp)
567 struct hwrm_ver_get_input req = {.req_type = 0 };
568 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
571 uint16_t max_resp_len;
572 char type[RTE_MEMZONE_NAMESIZE];
573 uint32_t dev_caps_cfg;
575 bp->max_req_len = HWRM_MAX_REQ_LEN;
576 HWRM_PREP(req, VER_GET);
578 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
579 req.hwrm_intf_min = HWRM_VERSION_MINOR;
580 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
582 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
586 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
587 resp->hwrm_intf_maj, resp->hwrm_intf_min,
589 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
590 bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
591 (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
592 RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
593 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
595 my_version = HWRM_VERSION_MAJOR << 16;
596 my_version |= HWRM_VERSION_MINOR << 8;
597 my_version |= HWRM_VERSION_UPDATE;
599 fw_version = resp->hwrm_intf_maj << 16;
600 fw_version |= resp->hwrm_intf_min << 8;
601 fw_version |= resp->hwrm_intf_upd;
603 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
604 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
609 if (my_version != fw_version) {
610 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
611 if (my_version < fw_version) {
613 "Firmware API version is newer than driver.\n");
615 "The driver may be missing features.\n");
618 "Firmware API version is older than driver.\n");
620 "Not all driver features may be functional.\n");
624 if (bp->max_req_len > resp->max_req_win_len) {
625 RTE_LOG(ERR, PMD, "Unsupported request length\n");
628 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
629 max_resp_len = resp->max_resp_len;
630 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
632 if (bp->max_resp_len != max_resp_len) {
633 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
634 bp->pdev->addr.domain, bp->pdev->addr.bus,
635 bp->pdev->addr.devid, bp->pdev->addr.function);
637 rte_free(bp->hwrm_cmd_resp_addr);
639 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
640 if (bp->hwrm_cmd_resp_addr == NULL) {
644 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
645 bp->hwrm_cmd_resp_dma_addr =
646 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
647 if (bp->hwrm_cmd_resp_dma_addr == 0) {
649 "Unable to map response buffer to physical memory.\n");
653 bp->max_resp_len = max_resp_len;
657 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
659 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
660 RTE_LOG(DEBUG, PMD, "Short command supported\n");
662 rte_free(bp->hwrm_short_cmd_req_addr);
664 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
666 if (bp->hwrm_short_cmd_req_addr == NULL) {
670 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
671 bp->hwrm_short_cmd_req_dma_addr =
672 rte_mem_virt2phy(bp->hwrm_short_cmd_req_addr);
673 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
674 rte_free(bp->hwrm_short_cmd_req_addr);
676 "Unable to map buffer to physical memory.\n");
681 bp->flags |= BNXT_FLAG_SHORT_CMD;
689 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
692 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
693 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
695 if (!(bp->flags & BNXT_FLAG_REGISTERED))
698 HWRM_PREP(req, FUNC_DRV_UNRGTR);
701 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
706 bp->flags &= ~BNXT_FLAG_REGISTERED;
711 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
714 struct hwrm_port_phy_cfg_input req = {0};
715 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
716 uint32_t enables = 0;
717 uint32_t link_speed_mask =
718 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
720 HWRM_PREP(req, PORT_PHY_CFG);
723 req.flags = rte_cpu_to_le_32(conf->phy_flags);
724 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
726 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
727 * any auto mode, even "none".
729 if (!conf->link_speed) {
730 req.auto_mode = conf->auto_mode;
731 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
732 if (conf->auto_mode ==
733 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK) {
734 req.auto_link_speed_mask =
735 conf->auto_link_speed_mask;
736 enables |= link_speed_mask;
738 if (bp->link_info.auto_link_speed) {
739 req.auto_link_speed =
740 bp->link_info.auto_link_speed;
742 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
745 req.auto_duplex = conf->duplex;
746 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
747 req.auto_pause = conf->auto_pause;
748 req.force_pause = conf->force_pause;
749 /* Set force_pause if there is no auto or if there is a force */
750 if (req.auto_pause && !req.force_pause)
751 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
753 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
755 req.enables = rte_cpu_to_le_32(enables);
758 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
759 RTE_LOG(INFO, PMD, "Force Link Down\n");
762 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
770 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
771 struct bnxt_link_info *link_info)
774 struct hwrm_port_phy_qcfg_input req = {0};
775 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
777 HWRM_PREP(req, PORT_PHY_QCFG);
779 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
783 link_info->phy_link_status = resp->link;
785 (link_info->phy_link_status ==
786 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
787 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
788 link_info->duplex = resp->duplex;
789 link_info->pause = resp->pause;
790 link_info->auto_pause = resp->auto_pause;
791 link_info->force_pause = resp->force_pause;
792 link_info->auto_mode = resp->auto_mode;
794 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
795 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
796 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
797 link_info->phy_ver[0] = resp->phy_maj;
798 link_info->phy_ver[1] = resp->phy_min;
799 link_info->phy_ver[2] = resp->phy_bld;
806 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
809 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
810 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
812 HWRM_PREP(req, QUEUE_QPORTCFG);
814 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
818 #define GET_QUEUE_INFO(x) \
819 bp->cos_queue[x].id = resp->queue_id##x; \
820 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
836 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
837 struct bnxt_ring *ring,
838 uint32_t ring_type, uint32_t map_index,
839 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
842 uint32_t enables = 0;
843 struct hwrm_ring_alloc_input req = {.req_type = 0 };
844 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
846 HWRM_PREP(req, RING_ALLOC);
848 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
849 req.fbo = rte_cpu_to_le_32(0);
850 /* Association of ring index with doorbell index */
851 req.logical_id = rte_cpu_to_le_16(map_index);
852 req.length = rte_cpu_to_le_32(ring->ring_size);
855 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
856 req.queue_id = bp->cos_queue[0].id;
858 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
859 req.ring_type = ring_type;
860 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
861 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
862 if (stats_ctx_id != INVALID_STATS_CTX_ID)
864 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
866 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
867 req.ring_type = ring_type;
869 * TODO: Some HWRM versions crash with
870 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
872 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
875 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
880 req.enables = rte_cpu_to_le_32(enables);
882 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
884 if (rc || resp->error_code) {
885 if (rc == 0 && resp->error_code)
886 rc = rte_le_to_cpu_16(resp->error_code);
888 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
890 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
893 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
895 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
898 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
900 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
904 RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
910 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
915 int bnxt_hwrm_ring_free(struct bnxt *bp,
916 struct bnxt_ring *ring, uint32_t ring_type)
919 struct hwrm_ring_free_input req = {.req_type = 0 };
920 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
922 HWRM_PREP(req, RING_FREE);
924 req.ring_type = ring_type;
925 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
927 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
929 if (rc || resp->error_code) {
930 if (rc == 0 && resp->error_code)
931 rc = rte_le_to_cpu_16(resp->error_code);
935 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
936 RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
939 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
940 RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
943 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
944 RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
948 RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
956 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
959 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
960 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
962 HWRM_PREP(req, RING_GRP_ALLOC);
964 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
965 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
966 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
967 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
969 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
973 bp->grp_info[idx].fw_grp_id =
974 rte_le_to_cpu_16(resp->ring_group_id);
981 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
984 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
985 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
987 HWRM_PREP(req, RING_GRP_FREE);
989 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
991 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
996 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1000 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1003 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1004 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1006 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1009 HWRM_PREP(req, STAT_CTX_CLR_STATS);
1011 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1013 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1015 HWRM_CHECK_RESULT();
1021 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1022 unsigned int idx __rte_unused)
1025 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1026 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1028 HWRM_PREP(req, STAT_CTX_ALLOC);
1030 req.update_period_ms = rte_cpu_to_le_32(0);
1032 req.stats_dma_addr =
1033 rte_cpu_to_le_64(cpr->hw_stats_map);
1035 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1037 HWRM_CHECK_RESULT();
1039 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1042 bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
1047 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1048 unsigned int idx __rte_unused)
1051 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1052 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1054 HWRM_PREP(req, STAT_CTX_FREE);
1056 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1058 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1060 HWRM_CHECK_RESULT();
1066 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1069 struct hwrm_vnic_alloc_input req = { 0 };
1070 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1072 /* map ring groups to this vnic */
1073 RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
1074 vnic->start_grp_id, vnic->end_grp_id);
1075 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1076 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1077 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1078 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1079 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1080 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1081 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1082 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1083 HWRM_PREP(req, VNIC_ALLOC);
1085 if (vnic->func_default)
1086 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
1087 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1089 HWRM_CHECK_RESULT();
1091 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1093 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1097 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1098 struct bnxt_vnic_info *vnic,
1099 struct bnxt_plcmodes_cfg *pmode)
1102 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1103 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1105 HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1107 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1109 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1111 HWRM_CHECK_RESULT();
1113 pmode->flags = rte_le_to_cpu_32(resp->flags);
1114 /* dflt_vnic bit doesn't exist in the _cfg command */
1115 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1116 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1117 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1118 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1125 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1126 struct bnxt_vnic_info *vnic,
1127 struct bnxt_plcmodes_cfg *pmode)
1130 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1131 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1133 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1135 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1136 req.flags = rte_cpu_to_le_32(pmode->flags);
1137 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1138 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1139 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1140 req.enables = rte_cpu_to_le_32(
1141 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1142 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1143 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1146 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1148 HWRM_CHECK_RESULT();
1154 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1157 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1158 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1159 uint32_t ctx_enable_flag = 0;
1160 struct bnxt_plcmodes_cfg pmodes;
1162 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1163 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1167 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1171 HWRM_PREP(req, VNIC_CFG);
1173 /* Only RSS support for now TBD: COS & LB */
1175 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1176 if (vnic->lb_rule != 0xffff)
1177 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1178 if (vnic->cos_rule != 0xffff)
1179 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1180 if (vnic->rss_rule != 0xffff) {
1181 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1182 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1184 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1185 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1186 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1187 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1188 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1189 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1190 req.mru = rte_cpu_to_le_16(vnic->mru);
1191 if (vnic->func_default)
1193 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1194 if (vnic->vlan_strip)
1196 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1199 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1200 if (vnic->roce_dual)
1201 req.flags |= rte_cpu_to_le_32(
1202 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1203 if (vnic->roce_only)
1204 req.flags |= rte_cpu_to_le_32(
1205 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1206 if (vnic->rss_dflt_cr)
1207 req.flags |= rte_cpu_to_le_32(
1208 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1210 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1212 HWRM_CHECK_RESULT();
1215 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1220 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1224 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1225 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1227 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1228 RTE_LOG(DEBUG, PMD, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1231 HWRM_PREP(req, VNIC_QCFG);
1234 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1235 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1236 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1238 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1240 HWRM_CHECK_RESULT();
1242 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1243 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1244 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1245 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1246 vnic->mru = rte_le_to_cpu_16(resp->mru);
1247 vnic->func_default = rte_le_to_cpu_32(
1248 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1249 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1250 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1251 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1252 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1253 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1254 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1255 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1256 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1257 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1258 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1265 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1268 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1269 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1270 bp->hwrm_cmd_resp_addr;
1272 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1274 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1276 HWRM_CHECK_RESULT();
1278 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1280 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1285 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1288 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1289 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1290 bp->hwrm_cmd_resp_addr;
1292 if (vnic->rss_rule == 0xffff) {
1293 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1296 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1298 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1300 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1302 HWRM_CHECK_RESULT();
1305 vnic->rss_rule = INVALID_HW_RING_ID;
1310 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1313 struct hwrm_vnic_free_input req = {.req_type = 0 };
1314 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1316 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1317 RTE_LOG(DEBUG, PMD, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1321 HWRM_PREP(req, VNIC_FREE);
1323 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1325 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1327 HWRM_CHECK_RESULT();
1330 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1334 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1335 struct bnxt_vnic_info *vnic)
1338 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1339 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1341 HWRM_PREP(req, VNIC_RSS_CFG);
1343 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1345 req.ring_grp_tbl_addr =
1346 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1347 req.hash_key_tbl_addr =
1348 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1349 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1351 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1353 HWRM_CHECK_RESULT();
1359 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1360 struct bnxt_vnic_info *vnic)
1363 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1364 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1367 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1369 req.flags = rte_cpu_to_le_32(
1370 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1372 req.enables = rte_cpu_to_le_32(
1373 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1375 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1376 size -= RTE_PKTMBUF_HEADROOM;
1378 req.jumbo_thresh = rte_cpu_to_le_16(size);
1379 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1381 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1383 HWRM_CHECK_RESULT();
1389 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1390 struct bnxt_vnic_info *vnic, bool enable)
1393 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1394 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1396 HWRM_PREP(req, VNIC_TPA_CFG);
1399 req.enables = rte_cpu_to_le_32(
1400 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1401 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1402 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1403 req.flags = rte_cpu_to_le_32(
1404 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1405 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1406 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1407 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1408 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1409 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1410 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1411 req.max_agg_segs = rte_cpu_to_le_16(5);
1413 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1414 req.min_agg_len = rte_cpu_to_le_32(512);
1417 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1419 HWRM_CHECK_RESULT();
1425 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1427 struct hwrm_func_cfg_input req = {0};
1428 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1431 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1432 req.enables = rte_cpu_to_le_32(
1433 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1434 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1435 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1437 HWRM_PREP(req, FUNC_CFG);
1439 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1440 HWRM_CHECK_RESULT();
1443 bp->pf.vf_info[vf].random_mac = false;
1448 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1452 struct hwrm_func_qstats_input req = {.req_type = 0};
1453 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1455 HWRM_PREP(req, FUNC_QSTATS);
1457 req.fid = rte_cpu_to_le_16(fid);
1459 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1461 HWRM_CHECK_RESULT();
1464 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1471 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1472 struct rte_eth_stats *stats)
1475 struct hwrm_func_qstats_input req = {.req_type = 0};
1476 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1478 HWRM_PREP(req, FUNC_QSTATS);
1480 req.fid = rte_cpu_to_le_16(fid);
1482 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1484 HWRM_CHECK_RESULT();
1486 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1487 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1488 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1489 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1490 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1491 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1493 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1494 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1495 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1496 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1497 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1498 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1500 stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1501 stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1503 stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1510 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1513 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1514 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1516 HWRM_PREP(req, FUNC_CLR_STATS);
1518 req.fid = rte_cpu_to_le_16(fid);
1520 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1522 HWRM_CHECK_RESULT();
1529 * HWRM utility functions
1532 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1537 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1538 struct bnxt_tx_queue *txq;
1539 struct bnxt_rx_queue *rxq;
1540 struct bnxt_cp_ring_info *cpr;
1542 if (i >= bp->rx_cp_nr_rings) {
1543 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1546 rxq = bp->rx_queues[i];
1550 rc = bnxt_hwrm_stat_clear(bp, cpr);
1557 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1561 struct bnxt_cp_ring_info *cpr;
1563 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1565 if (i >= bp->rx_cp_nr_rings)
1566 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1568 cpr = bp->rx_queues[i]->cp_ring;
1569 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1570 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1571 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1573 * TODO. Need a better way to reset grp_info.stats_ctx
1574 * for Rx rings only. stats_ctx is not saved for Tx
1577 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1585 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1590 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1591 struct bnxt_tx_queue *txq;
1592 struct bnxt_rx_queue *rxq;
1593 struct bnxt_cp_ring_info *cpr;
1595 if (i >= bp->rx_cp_nr_rings) {
1596 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1599 rxq = bp->rx_queues[i];
1603 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1611 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1616 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1618 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1621 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1629 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1630 unsigned int idx __rte_unused)
1632 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1634 bnxt_hwrm_ring_free(bp, cp_ring,
1635 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1636 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1637 bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1638 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1639 sizeof(*cpr->cp_desc_ring));
1640 cpr->cp_raw_cons = 0;
1643 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1648 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1649 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1650 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1651 struct bnxt_ring *ring = txr->tx_ring_struct;
1652 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1653 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1655 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1656 bnxt_hwrm_ring_free(bp, ring,
1657 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1658 ring->fw_ring_id = INVALID_HW_RING_ID;
1659 memset(txr->tx_desc_ring, 0,
1660 txr->tx_ring_struct->ring_size *
1661 sizeof(*txr->tx_desc_ring));
1662 memset(txr->tx_buf_ring, 0,
1663 txr->tx_ring_struct->ring_size *
1664 sizeof(*txr->tx_buf_ring));
1668 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1669 bnxt_free_cp_ring(bp, cpr, idx);
1670 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1674 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1675 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1676 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1677 struct bnxt_ring *ring = rxr->rx_ring_struct;
1678 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1679 unsigned int idx = i + 1;
1681 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1682 bnxt_hwrm_ring_free(bp, ring,
1683 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1684 ring->fw_ring_id = INVALID_HW_RING_ID;
1685 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1686 memset(rxr->rx_desc_ring, 0,
1687 rxr->rx_ring_struct->ring_size *
1688 sizeof(*rxr->rx_desc_ring));
1689 memset(rxr->rx_buf_ring, 0,
1690 rxr->rx_ring_struct->ring_size *
1691 sizeof(*rxr->rx_buf_ring));
1693 memset(rxr->ag_buf_ring, 0,
1694 rxr->ag_ring_struct->ring_size *
1695 sizeof(*rxr->ag_buf_ring));
1698 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1699 bnxt_free_cp_ring(bp, cpr, idx);
1700 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1701 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1705 /* Default completion ring */
1707 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1709 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1710 bnxt_free_cp_ring(bp, cpr, 0);
1711 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1718 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1723 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1724 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1731 void bnxt_free_hwrm_resources(struct bnxt *bp)
1733 /* Release memzone */
1734 rte_free(bp->hwrm_cmd_resp_addr);
1735 rte_free(bp->hwrm_short_cmd_req_addr);
1736 bp->hwrm_cmd_resp_addr = NULL;
1737 bp->hwrm_short_cmd_req_addr = NULL;
1738 bp->hwrm_cmd_resp_dma_addr = 0;
1739 bp->hwrm_short_cmd_req_dma_addr = 0;
1742 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1744 struct rte_pci_device *pdev = bp->pdev;
1745 char type[RTE_MEMZONE_NAMESIZE];
1747 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1748 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1749 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1750 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1751 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1752 if (bp->hwrm_cmd_resp_addr == NULL)
1754 bp->hwrm_cmd_resp_dma_addr =
1755 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
1756 if (bp->hwrm_cmd_resp_dma_addr == 0) {
1758 "unable to map response address to physical memory\n");
1761 rte_spinlock_init(&bp->hwrm_lock);
1766 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1768 struct bnxt_filter_info *filter;
1771 STAILQ_FOREACH(filter, &vnic->filter, next) {
1772 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1773 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1774 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1775 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1777 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1785 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1787 struct bnxt_filter_info *filter;
1788 struct rte_flow *flow;
1791 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1792 filter = flow->filter;
1793 RTE_LOG(ERR, PMD, "filter type %d\n", filter->filter_type);
1794 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1795 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1796 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1797 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1799 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1801 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1809 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1811 struct bnxt_filter_info *filter;
1814 STAILQ_FOREACH(filter, &vnic->filter, next) {
1815 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1816 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1818 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1819 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1822 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1830 void bnxt_free_tunnel_ports(struct bnxt *bp)
1832 if (bp->vxlan_port_cnt)
1833 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1834 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1836 if (bp->geneve_port_cnt)
1837 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1838 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1839 bp->geneve_port = 0;
1842 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1846 if (bp->vnic_info == NULL)
1850 * Cleanup VNICs in reverse order, to make sure the L2 filter
1851 * from vnic0 is last to be cleaned up.
1853 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1854 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1856 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1858 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1860 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1862 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1864 bnxt_hwrm_vnic_free(bp, vnic);
1866 /* Ring resources */
1867 bnxt_free_all_hwrm_rings(bp);
1868 bnxt_free_all_hwrm_ring_grps(bp);
1869 bnxt_free_all_hwrm_stat_ctxs(bp);
1870 bnxt_free_tunnel_ports(bp);
1873 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1875 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1877 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1878 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1880 switch (conf_link_speed) {
1881 case ETH_LINK_SPEED_10M_HD:
1882 case ETH_LINK_SPEED_100M_HD:
1883 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1885 return hw_link_duplex;
1888 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1890 uint16_t eth_link_speed = 0;
1892 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1893 return ETH_LINK_SPEED_AUTONEG;
1895 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1896 case ETH_LINK_SPEED_100M:
1897 case ETH_LINK_SPEED_100M_HD:
1899 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1901 case ETH_LINK_SPEED_1G:
1903 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1905 case ETH_LINK_SPEED_2_5G:
1907 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1909 case ETH_LINK_SPEED_10G:
1911 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1913 case ETH_LINK_SPEED_20G:
1915 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1917 case ETH_LINK_SPEED_25G:
1919 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1921 case ETH_LINK_SPEED_40G:
1923 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1925 case ETH_LINK_SPEED_50G:
1927 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1931 "Unsupported link speed %d; default to AUTO\n",
1935 return eth_link_speed;
1938 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1939 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1940 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1941 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1943 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
1947 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1950 if (link_speed & ETH_LINK_SPEED_FIXED) {
1951 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1953 if (one_speed & (one_speed - 1)) {
1955 "Invalid advertised speeds (%u) for port %u\n",
1956 link_speed, port_id);
1959 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1961 "Unsupported advertised speed (%u) for port %u\n",
1962 link_speed, port_id);
1966 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1968 "Unsupported advertised speeds (%u) for port %u\n",
1969 link_speed, port_id);
1977 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
1981 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
1982 if (bp->link_info.support_speeds)
1983 return bp->link_info.support_speeds;
1984 link_speed = BNXT_SUPPORTED_SPEEDS;
1987 if (link_speed & ETH_LINK_SPEED_100M)
1988 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1989 if (link_speed & ETH_LINK_SPEED_100M_HD)
1990 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1991 if (link_speed & ETH_LINK_SPEED_1G)
1992 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1993 if (link_speed & ETH_LINK_SPEED_2_5G)
1994 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1995 if (link_speed & ETH_LINK_SPEED_10G)
1996 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1997 if (link_speed & ETH_LINK_SPEED_20G)
1998 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1999 if (link_speed & ETH_LINK_SPEED_25G)
2000 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2001 if (link_speed & ETH_LINK_SPEED_40G)
2002 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2003 if (link_speed & ETH_LINK_SPEED_50G)
2004 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2008 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2010 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2012 switch (hw_link_speed) {
2013 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2014 eth_link_speed = ETH_SPEED_NUM_100M;
2016 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2017 eth_link_speed = ETH_SPEED_NUM_1G;
2019 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2020 eth_link_speed = ETH_SPEED_NUM_2_5G;
2022 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2023 eth_link_speed = ETH_SPEED_NUM_10G;
2025 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2026 eth_link_speed = ETH_SPEED_NUM_20G;
2028 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2029 eth_link_speed = ETH_SPEED_NUM_25G;
2031 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2032 eth_link_speed = ETH_SPEED_NUM_40G;
2034 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2035 eth_link_speed = ETH_SPEED_NUM_50G;
2037 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2039 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
2043 return eth_link_speed;
2046 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2048 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2050 switch (hw_link_duplex) {
2051 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2052 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2053 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2055 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2056 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2059 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
2063 return eth_link_duplex;
2066 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2069 struct bnxt_link_info *link_info = &bp->link_info;
2071 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2074 "Get link config failed with rc %d\n", rc);
2077 if (link_info->link_speed)
2079 bnxt_parse_hw_link_speed(link_info->link_speed);
2081 link->link_speed = ETH_SPEED_NUM_NONE;
2082 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2083 link->link_status = link_info->link_up;
2084 link->link_autoneg = link_info->auto_mode ==
2085 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2086 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2091 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2094 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2095 struct bnxt_link_info link_req;
2098 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
2101 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2102 bp->eth_dev->data->port_id);
2106 memset(&link_req, 0, sizeof(link_req));
2107 link_req.link_up = link_up;
2111 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2112 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2114 link_req.phy_flags |=
2115 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2116 link_req.auto_mode =
2117 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
2118 link_req.auto_link_speed_mask =
2119 bnxt_parse_eth_link_speed_mask(bp,
2120 dev_conf->link_speeds);
2122 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2123 link_req.link_speed = speed;
2124 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
2126 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2127 link_req.auto_pause = bp->link_info.auto_pause;
2128 link_req.force_pause = bp->link_info.force_pause;
2131 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2134 "Set link config failed with rc %d\n", rc);
2142 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2144 struct hwrm_func_qcfg_input req = {0};
2145 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2148 HWRM_PREP(req, FUNC_QCFG);
2149 req.fid = rte_cpu_to_le_16(0xffff);
2151 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2153 HWRM_CHECK_RESULT();
2155 /* Hard Coded.. 0xfff VLAN ID mask */
2156 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2158 switch (resp->port_partition_type) {
2159 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2160 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2161 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2162 bp->port_partition_type = resp->port_partition_type;
2165 bp->port_partition_type = 0;
2174 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2175 struct hwrm_func_qcaps_output *qcaps)
2177 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2178 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2179 sizeof(qcaps->mac_address));
2180 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2181 qcaps->max_rx_rings = fcfg->num_rx_rings;
2182 qcaps->max_tx_rings = fcfg->num_tx_rings;
2183 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2184 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2186 qcaps->first_vf_id = 0;
2187 qcaps->max_vnics = fcfg->num_vnics;
2188 qcaps->max_decap_records = 0;
2189 qcaps->max_encap_records = 0;
2190 qcaps->max_tx_wm_flows = 0;
2191 qcaps->max_tx_em_flows = 0;
2192 qcaps->max_rx_wm_flows = 0;
2193 qcaps->max_rx_em_flows = 0;
2194 qcaps->max_flow_id = 0;
2195 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2196 qcaps->max_sp_tx_rings = 0;
2197 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2200 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2202 struct hwrm_func_cfg_input req = {0};
2203 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2206 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2207 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2208 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2209 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2210 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2211 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2212 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2213 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2214 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2215 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2216 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2217 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2218 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2219 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2220 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2221 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2222 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2223 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2224 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2225 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2226 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2227 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2228 req.fid = rte_cpu_to_le_16(0xffff);
2230 HWRM_PREP(req, FUNC_CFG);
2232 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2234 HWRM_CHECK_RESULT();
2240 static void populate_vf_func_cfg_req(struct bnxt *bp,
2241 struct hwrm_func_cfg_input *req,
2244 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2245 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2246 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2247 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2248 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2249 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2250 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2251 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2252 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2253 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2255 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2256 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2257 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2258 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2259 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2261 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2262 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2264 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2265 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2266 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2267 /* TODO: For now, do not support VMDq/RFS on VFs. */
2268 req->num_vnics = rte_cpu_to_le_16(1);
2269 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2273 static void add_random_mac_if_needed(struct bnxt *bp,
2274 struct hwrm_func_cfg_input *cfg_req,
2277 struct ether_addr mac;
2279 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2282 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2284 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2285 eth_random_addr(cfg_req->dflt_mac_addr);
2286 bp->pf.vf_info[vf].random_mac = true;
2288 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2292 static void reserve_resources_from_vf(struct bnxt *bp,
2293 struct hwrm_func_cfg_input *cfg_req,
2296 struct hwrm_func_qcaps_input req = {0};
2297 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2300 /* Get the actual allocated values now */
2301 HWRM_PREP(req, FUNC_QCAPS);
2302 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2303 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2306 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2307 copy_func_cfg_to_qcaps(cfg_req, resp);
2308 } else if (resp->error_code) {
2309 rc = rte_le_to_cpu_16(resp->error_code);
2310 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2311 copy_func_cfg_to_qcaps(cfg_req, resp);
2314 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2315 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2316 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2317 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2318 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2319 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2321 * TODO: While not supporting VMDq with VFs, max_vnics is always
2322 * forced to 1 in this case
2324 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2325 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2330 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2332 struct hwrm_func_qcfg_input req = {0};
2333 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2336 /* Check for zero MAC address */
2337 HWRM_PREP(req, FUNC_QCFG);
2338 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2339 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2341 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2343 } else if (resp->error_code) {
2344 rc = rte_le_to_cpu_16(resp->error_code);
2345 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2348 rc = rte_le_to_cpu_16(resp->vlan);
2355 static int update_pf_resource_max(struct bnxt *bp)
2357 struct hwrm_func_qcfg_input req = {0};
2358 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2361 /* And copy the allocated numbers into the pf struct */
2362 HWRM_PREP(req, FUNC_QCFG);
2363 req.fid = rte_cpu_to_le_16(0xffff);
2364 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2365 HWRM_CHECK_RESULT();
2367 /* Only TX ring value reflects actual allocation? TODO */
2368 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2369 bp->pf.evb_mode = resp->evb_mode;
2376 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2381 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2385 rc = bnxt_hwrm_func_qcaps(bp);
2389 bp->pf.func_cfg_flags &=
2390 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2391 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2392 bp->pf.func_cfg_flags |=
2393 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2394 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2398 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2400 struct hwrm_func_cfg_input req = {0};
2401 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2408 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2412 rc = bnxt_hwrm_func_qcaps(bp);
2417 bp->pf.active_vfs = num_vfs;
2420 * First, configure the PF to only use one TX ring. This ensures that
2421 * there are enough rings for all VFs.
2423 * If we don't do this, when we call func_alloc() later, we will lock
2424 * extra rings to the PF that won't be available during func_cfg() of
2427 * This has been fixed with firmware versions above 20.6.54
2429 bp->pf.func_cfg_flags &=
2430 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2431 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2432 bp->pf.func_cfg_flags |=
2433 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2434 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2439 * Now, create and register a buffer to hold forwarded VF requests
2441 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2442 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2443 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2444 if (bp->pf.vf_req_buf == NULL) {
2448 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2449 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2450 for (i = 0; i < num_vfs; i++)
2451 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2452 (i * HWRM_MAX_REQ_LEN);
2454 rc = bnxt_hwrm_func_buf_rgtr(bp);
2458 populate_vf_func_cfg_req(bp, &req, num_vfs);
2460 bp->pf.active_vfs = 0;
2461 for (i = 0; i < num_vfs; i++) {
2462 add_random_mac_if_needed(bp, &req, i);
2464 HWRM_PREP(req, FUNC_CFG);
2465 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2466 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2467 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2469 /* Clear enable flag for next pass */
2470 req.enables &= ~rte_cpu_to_le_32(
2471 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2473 if (rc || resp->error_code) {
2475 "Failed to initizlie VF %d\n", i);
2477 "Not all VFs available. (%d, %d)\n",
2478 rc, resp->error_code);
2485 reserve_resources_from_vf(bp, &req, i);
2486 bp->pf.active_vfs++;
2487 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2491 * Now configure the PF to use "the rest" of the resources
2492 * We're using STD_TX_RING_MODE here though which will limit the TX
2493 * rings. This will allow QoS to function properly. Not setting this
2494 * will cause PF rings to break bandwidth settings.
2496 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2500 rc = update_pf_resource_max(bp);
2507 bnxt_hwrm_func_buf_unrgtr(bp);
2511 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2513 struct hwrm_func_cfg_input req = {0};
2514 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2517 HWRM_PREP(req, FUNC_CFG);
2519 req.fid = rte_cpu_to_le_16(0xffff);
2520 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2521 req.evb_mode = bp->pf.evb_mode;
2523 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2524 HWRM_CHECK_RESULT();
2530 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2531 uint8_t tunnel_type)
2533 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2534 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2537 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2538 req.tunnel_type = tunnel_type;
2539 req.tunnel_dst_port_val = port;
2540 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2541 HWRM_CHECK_RESULT();
2543 switch (tunnel_type) {
2544 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2545 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2546 bp->vxlan_port = port;
2548 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2549 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2550 bp->geneve_port = port;
2561 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2562 uint8_t tunnel_type)
2564 struct hwrm_tunnel_dst_port_free_input req = {0};
2565 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2568 HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2570 req.tunnel_type = tunnel_type;
2571 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2572 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2574 HWRM_CHECK_RESULT();
2580 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2583 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2584 struct hwrm_func_cfg_input req = {0};
2587 HWRM_PREP(req, FUNC_CFG);
2589 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2590 req.flags = rte_cpu_to_le_32(flags);
2591 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2593 HWRM_CHECK_RESULT();
2599 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2601 uint32_t *flag = flagp;
2603 vnic->flags = *flag;
2606 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2608 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2611 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2614 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2615 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2617 HWRM_PREP(req, FUNC_BUF_RGTR);
2619 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2620 req.req_buf_page_size = rte_cpu_to_le_16(
2621 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2622 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2623 req.req_buf_page_addr[0] =
2624 rte_cpu_to_le_64(rte_mem_virt2phy(bp->pf.vf_req_buf));
2625 if (req.req_buf_page_addr[0] == 0) {
2627 "unable to map buffer address to physical memory\n");
2631 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2633 HWRM_CHECK_RESULT();
2639 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2642 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2643 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2645 HWRM_PREP(req, FUNC_BUF_UNRGTR);
2647 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2649 HWRM_CHECK_RESULT();
2655 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2657 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2658 struct hwrm_func_cfg_input req = {0};
2661 HWRM_PREP(req, FUNC_CFG);
2663 req.fid = rte_cpu_to_le_16(0xffff);
2664 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2665 req.enables = rte_cpu_to_le_32(
2666 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2667 req.async_event_cr = rte_cpu_to_le_16(
2668 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2669 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2671 HWRM_CHECK_RESULT();
2677 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2679 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2680 struct hwrm_func_vf_cfg_input req = {0};
2683 HWRM_PREP(req, FUNC_VF_CFG);
2685 req.enables = rte_cpu_to_le_32(
2686 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2687 req.async_event_cr = rte_cpu_to_le_16(
2688 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2689 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2691 HWRM_CHECK_RESULT();
2697 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2699 struct hwrm_func_cfg_input req = {0};
2700 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2701 uint16_t dflt_vlan, fid;
2702 uint32_t func_cfg_flags;
2705 HWRM_PREP(req, FUNC_CFG);
2708 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2709 fid = bp->pf.vf_info[vf].fid;
2710 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2712 fid = rte_cpu_to_le_16(0xffff);
2713 func_cfg_flags = bp->pf.func_cfg_flags;
2714 dflt_vlan = bp->vlan;
2717 req.flags = rte_cpu_to_le_32(func_cfg_flags);
2718 req.fid = rte_cpu_to_le_16(fid);
2719 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2720 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2722 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2724 HWRM_CHECK_RESULT();
2730 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2731 uint16_t max_bw, uint16_t enables)
2733 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2734 struct hwrm_func_cfg_input req = {0};
2737 HWRM_PREP(req, FUNC_CFG);
2739 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2740 req.enables |= rte_cpu_to_le_32(enables);
2741 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2742 req.max_bw = rte_cpu_to_le_32(max_bw);
2743 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2745 HWRM_CHECK_RESULT();
2751 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2753 struct hwrm_func_cfg_input req = {0};
2754 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2757 HWRM_PREP(req, FUNC_CFG);
2759 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2760 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2761 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2762 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2764 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2766 HWRM_CHECK_RESULT();
2772 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2773 void *encaped, size_t ec_size)
2776 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2777 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2779 if (ec_size > sizeof(req.encap_request))
2782 HWRM_PREP(req, REJECT_FWD_RESP);
2784 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2785 memcpy(req.encap_request, encaped, ec_size);
2787 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2789 HWRM_CHECK_RESULT();
2795 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2796 struct ether_addr *mac)
2798 struct hwrm_func_qcfg_input req = {0};
2799 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2802 HWRM_PREP(req, FUNC_QCFG);
2804 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2805 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2807 HWRM_CHECK_RESULT();
2809 memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2816 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2817 void *encaped, size_t ec_size)
2820 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2821 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2823 if (ec_size > sizeof(req.encap_request))
2826 HWRM_PREP(req, EXEC_FWD_RESP);
2828 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2829 memcpy(req.encap_request, encaped, ec_size);
2831 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2833 HWRM_CHECK_RESULT();
2839 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2840 struct rte_eth_stats *stats, uint8_t rx)
2843 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2844 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2846 HWRM_PREP(req, STAT_CTX_QUERY);
2848 req.stat_ctx_id = rte_cpu_to_le_32(cid);
2850 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2852 HWRM_CHECK_RESULT();
2855 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2856 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2857 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2858 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2859 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2860 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2861 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2862 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2864 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2865 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2866 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2867 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2868 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2869 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2870 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2879 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2881 struct hwrm_port_qstats_input req = {0};
2882 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2883 struct bnxt_pf_info *pf = &bp->pf;
2886 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2889 HWRM_PREP(req, PORT_QSTATS);
2891 req.port_id = rte_cpu_to_le_16(pf->port_id);
2892 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2893 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2894 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2896 HWRM_CHECK_RESULT();
2902 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2904 struct hwrm_port_clr_stats_input req = {0};
2905 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2906 struct bnxt_pf_info *pf = &bp->pf;
2909 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2912 HWRM_PREP(req, PORT_CLR_STATS);
2914 req.port_id = rte_cpu_to_le_16(pf->port_id);
2915 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2917 HWRM_CHECK_RESULT();
2923 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2925 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2926 struct hwrm_port_led_qcaps_input req = {0};
2932 HWRM_PREP(req, PORT_LED_QCAPS);
2933 req.port_id = bp->pf.port_id;
2934 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2936 HWRM_CHECK_RESULT();
2938 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2941 bp->num_leds = resp->num_leds;
2942 memcpy(bp->leds, &resp->led0_id,
2943 sizeof(bp->leds[0]) * bp->num_leds);
2944 for (i = 0; i < bp->num_leds; i++) {
2945 struct bnxt_led_info *led = &bp->leds[i];
2947 uint16_t caps = led->led_state_caps;
2949 if (!led->led_group_id ||
2950 !BNXT_LED_ALT_BLINK_CAP(caps)) {
2962 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
2964 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2965 struct hwrm_port_led_cfg_input req = {0};
2966 struct bnxt_led_cfg *led_cfg;
2967 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
2968 uint16_t duration = 0;
2971 if (!bp->num_leds || BNXT_VF(bp))
2974 HWRM_PREP(req, PORT_LED_CFG);
2977 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
2978 duration = rte_cpu_to_le_16(500);
2980 req.port_id = bp->pf.port_id;
2981 req.num_leds = bp->num_leds;
2982 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
2983 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
2984 req.enables |= BNXT_LED_DFLT_ENABLES(i);
2985 led_cfg->led_id = bp->leds[i].led_id;
2986 led_cfg->led_state = led_state;
2987 led_cfg->led_blink_on = duration;
2988 led_cfg->led_blink_off = duration;
2989 led_cfg->led_group_id = bp->leds[i].led_group_id;
2992 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2994 HWRM_CHECK_RESULT();
3000 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3004 struct hwrm_nvm_get_dir_info_input req = {0};
3005 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3007 HWRM_PREP(req, NVM_GET_DIR_INFO);
3009 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3011 HWRM_CHECK_RESULT();
3015 *entries = rte_le_to_cpu_32(resp->entries);
3016 *length = rte_le_to_cpu_32(resp->entry_length);
3021 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3024 uint32_t dir_entries;
3025 uint32_t entry_length;
3028 phys_addr_t dma_handle;
3029 struct hwrm_nvm_get_dir_entries_input req = {0};
3030 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3032 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3036 *data++ = dir_entries;
3037 *data++ = entry_length;
3039 memset(data, 0xff, len);
3041 buflen = dir_entries * entry_length;
3042 buf = rte_malloc("nvm_dir", buflen, 0);
3043 rte_mem_lock_page(buf);
3046 dma_handle = rte_mem_virt2phy(buf);
3047 if (dma_handle == 0) {
3049 "unable to map response address to physical memory\n");
3052 HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3053 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3054 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3056 HWRM_CHECK_RESULT();
3060 memcpy(data, buf, len > buflen ? buflen : len);
3067 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3068 uint32_t offset, uint32_t length,
3073 phys_addr_t dma_handle;
3074 struct hwrm_nvm_read_input req = {0};
3075 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3077 buf = rte_malloc("nvm_item", length, 0);
3078 rte_mem_lock_page(buf);
3082 dma_handle = rte_mem_virt2phy(buf);
3083 if (dma_handle == 0) {
3085 "unable to map response address to physical memory\n");
3088 HWRM_PREP(req, NVM_READ);
3089 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3090 req.dir_idx = rte_cpu_to_le_16(index);
3091 req.offset = rte_cpu_to_le_32(offset);
3092 req.len = rte_cpu_to_le_32(length);
3093 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3094 HWRM_CHECK_RESULT();
3097 memcpy(data, buf, length);
3103 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3106 struct hwrm_nvm_erase_dir_entry_input req = {0};
3107 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3109 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3110 req.dir_idx = rte_cpu_to_le_16(index);
3111 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3112 HWRM_CHECK_RESULT();
3119 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3120 uint16_t dir_ordinal, uint16_t dir_ext,
3121 uint16_t dir_attr, const uint8_t *data,
3125 struct hwrm_nvm_write_input req = {0};
3126 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3127 phys_addr_t dma_handle;
3130 HWRM_PREP(req, NVM_WRITE);
3132 req.dir_type = rte_cpu_to_le_16(dir_type);
3133 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3134 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3135 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3136 req.dir_data_length = rte_cpu_to_le_32(data_len);
3138 buf = rte_malloc("nvm_write", data_len, 0);
3139 rte_mem_lock_page(buf);
3143 dma_handle = rte_mem_virt2phy(buf);
3144 if (dma_handle == 0) {
3146 "unable to map response address to physical memory\n");
3149 memcpy(buf, data, data_len);
3150 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3152 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3154 HWRM_CHECK_RESULT();
3162 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3164 uint32_t *count = cbdata;
3166 *count = *count + 1;
3169 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3170 struct bnxt_vnic_info *vnic __rte_unused)
3175 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3179 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3180 &count, bnxt_vnic_count_hwrm_stub);
3185 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3188 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3189 struct hwrm_func_vf_vnic_ids_query_output *resp =
3190 bp->hwrm_cmd_resp_addr;
3193 /* First query all VNIC ids */
3194 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3196 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3197 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3198 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2phy(vnic_ids));
3200 if (req.vnic_id_tbl_addr == 0) {
3203 "unable to map VNIC ID table address to physical memory\n");
3206 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3209 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3211 } else if (resp->error_code) {
3212 rc = rte_le_to_cpu_16(resp->error_code);
3214 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
3217 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3225 * This function queries the VNIC IDs for a specified VF. It then calls
3226 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3227 * Then it calls the hwrm_cb function to program this new vnic configuration.
3229 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3230 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3231 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3233 struct bnxt_vnic_info vnic;
3235 int i, num_vnic_ids;
3240 /* First query all VNIC ids */
3241 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3242 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3243 RTE_CACHE_LINE_SIZE);
3244 if (vnic_ids == NULL) {
3248 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3249 rte_mem_lock_page(((char *)vnic_ids) + sz);
3251 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3253 if (num_vnic_ids < 0)
3254 return num_vnic_ids;
3256 /* Retrieve VNIC, update bd_stall then update */
3258 for (i = 0; i < num_vnic_ids; i++) {
3259 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3260 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3261 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3264 if (vnic.mru <= 4) /* Indicates unallocated */
3267 vnic_cb(&vnic, cbdata);
3269 rc = hwrm_cb(bp, &vnic);
3279 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3282 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3283 struct hwrm_func_cfg_input req = {0};
3286 HWRM_PREP(req, FUNC_CFG);
3288 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3289 req.enables |= rte_cpu_to_le_32(
3290 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3291 req.vlan_antispoof_mode = on ?
3292 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3293 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3294 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3296 HWRM_CHECK_RESULT();
3302 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3304 struct bnxt_vnic_info vnic;
3307 int num_vnic_ids, i;
3311 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3312 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3313 RTE_CACHE_LINE_SIZE);
3314 if (vnic_ids == NULL) {
3319 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3320 rte_mem_lock_page(((char *)vnic_ids) + sz);
3322 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3328 * Loop through to find the default VNIC ID.
3329 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3330 * by sending the hwrm_func_qcfg command to the firmware.
3332 for (i = 0; i < num_vnic_ids; i++) {
3333 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3334 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3335 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3336 bp->pf.first_vf_id + vf);
3339 if (vnic.func_default) {
3341 return vnic.fw_vnic_id;
3344 /* Could not find a default VNIC. */
3345 RTE_LOG(ERR, PMD, "No default VNIC\n");
3351 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3353 struct bnxt_filter_info *filter)
3356 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3357 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3358 uint32_t enables = 0;
3360 if (filter->fw_em_filter_id != UINT64_MAX)
3361 bnxt_hwrm_clear_em_filter(bp, filter);
3363 HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3365 req.flags = rte_cpu_to_le_32(filter->flags);
3367 enables = filter->enables |
3368 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3369 req.dst_id = rte_cpu_to_le_16(dst_id);
3371 if (filter->ip_addr_type) {
3372 req.ip_addr_type = filter->ip_addr_type;
3373 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3376 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3377 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3379 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3380 memcpy(req.src_macaddr, filter->src_macaddr,
3383 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3384 memcpy(req.dst_macaddr, filter->dst_macaddr,
3387 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3388 req.ovlan_vid = filter->l2_ovlan;
3390 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3391 req.ivlan_vid = filter->l2_ivlan;
3393 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3394 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3396 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3397 req.ip_protocol = filter->ip_protocol;
3399 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3400 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3402 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3403 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3405 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3406 req.src_port = rte_cpu_to_be_16(filter->src_port);
3408 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3409 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3411 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3412 req.mirror_vnic_id = filter->mirror_vnic_id;
3414 req.enables = rte_cpu_to_le_32(enables);
3416 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3418 HWRM_CHECK_RESULT();
3420 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3426 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3429 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3430 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3432 if (filter->fw_em_filter_id == UINT64_MAX)
3435 RTE_LOG(ERR, PMD, "Clear EM filter\n");
3436 HWRM_PREP(req, CFA_EM_FLOW_FREE);
3438 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3440 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3442 HWRM_CHECK_RESULT();
3445 filter->fw_em_filter_id = -1;
3446 filter->fw_l2_filter_id = -1;
3451 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3453 struct bnxt_filter_info *filter)
3456 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3457 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3458 bp->hwrm_cmd_resp_addr;
3459 uint32_t enables = 0;
3461 if (filter->fw_ntuple_filter_id != UINT64_MAX)
3462 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3464 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3466 req.flags = rte_cpu_to_le_32(filter->flags);
3468 enables = filter->enables |
3469 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3470 req.dst_id = rte_cpu_to_le_16(dst_id);
3473 if (filter->ip_addr_type) {
3474 req.ip_addr_type = filter->ip_addr_type;
3476 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3479 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3480 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3482 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3483 memcpy(req.src_macaddr, filter->src_macaddr,
3486 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3487 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3490 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3491 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3493 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3494 req.ip_protocol = filter->ip_protocol;
3496 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3497 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3499 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3500 req.src_ipaddr_mask[0] =
3501 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3503 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3504 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3506 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3507 req.dst_ipaddr_mask[0] =
3508 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3510 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3511 req.src_port = rte_cpu_to_le_16(filter->src_port);
3513 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3514 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3516 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3517 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3519 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3520 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3522 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3523 req.mirror_vnic_id = filter->mirror_vnic_id;
3525 req.enables = rte_cpu_to_le_32(enables);
3527 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3529 HWRM_CHECK_RESULT();
3531 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3537 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3538 struct bnxt_filter_info *filter)
3541 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3542 struct hwrm_cfa_ntuple_filter_free_output *resp =
3543 bp->hwrm_cmd_resp_addr;
3545 if (filter->fw_ntuple_filter_id == UINT64_MAX)
3548 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3550 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3552 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3554 HWRM_CHECK_RESULT();
3557 filter->fw_ntuple_filter_id = -1;
3558 filter->fw_l2_filter_id = -1;