1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 10000
30 #define HWRM_SPEC_CODE_1_8_3 0x10803
31 #define HWRM_VERSION_1_9_1 0x10901
33 struct bnxt_plcmodes_cfg {
35 uint16_t jumbo_thresh;
37 uint16_t hds_threshold;
40 static int page_getenum(size_t size)
56 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
57 return sizeof(void *) * 8 - 1;
60 static int page_roundup(size_t size)
62 return 1 << page_getenum(size);
66 * HWRM Functions (sent to HWRM)
67 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
68 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
69 * command was failed by the ChiMP.
72 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
73 uint32_t msg_len, bool use_kong_mb)
76 struct input *req = msg;
77 struct output *resp = bp->hwrm_cmd_resp_addr;
81 uint16_t max_req_len = bp->max_req_len;
82 struct hwrm_short_input short_input = { 0 };
83 uint16_t bar_offset = use_kong_mb ?
84 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
85 uint16_t mb_trigger_offset = use_kong_mb ?
86 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
88 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
89 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
91 memset(short_cmd_req, 0, bp->max_req_len);
92 memcpy(short_cmd_req, req, msg_len);
94 short_input.req_type = rte_cpu_to_le_16(req->req_type);
95 short_input.signature = rte_cpu_to_le_16(
96 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
97 short_input.size = rte_cpu_to_le_16(msg_len);
98 short_input.req_addr =
99 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
101 data = (uint32_t *)&short_input;
102 msg_len = sizeof(short_input);
104 /* Sync memory write before updating doorbell */
107 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
110 /* Write request msg to hwrm channel */
111 for (i = 0; i < msg_len; i += 4) {
112 bar = (uint8_t *)bp->bar0 + bar_offset + i;
113 rte_write32(*data, bar);
117 /* Zero the rest of the request space */
118 for (; i < max_req_len; i += 4) {
119 bar = (uint8_t *)bp->bar0 + bar_offset + i;
123 /* Ring channel doorbell */
124 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
127 /* Poll for the valid bit */
128 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
129 /* Sanity check on the resp->resp_len */
131 if (resp->resp_len && resp->resp_len <=
133 /* Last byte of resp contains the valid key */
134 valid = (uint8_t *)resp + resp->resp_len - 1;
135 if (*valid == HWRM_RESP_VALID_KEY)
141 if (i >= HWRM_CMD_TIMEOUT) {
142 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
153 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
154 * spinlock, and does initial processing.
156 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
157 * releases the spinlock only if it returns. If the regular int return codes
158 * are not used by the function, HWRM_CHECK_RESULT() should not be used
159 * directly, rather it should be copied and modified to suit the function.
161 * HWRM_UNLOCK() must be called after all response processing is completed.
163 #define HWRM_PREP(req, type, kong) do { \
164 rte_spinlock_lock(&bp->hwrm_lock); \
165 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
166 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
167 req.cmpl_ring = rte_cpu_to_le_16(-1); \
168 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
169 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
170 req.target_id = rte_cpu_to_le_16(0xffff); \
171 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
174 #define HWRM_CHECK_RESULT_SILENT() do {\
176 rte_spinlock_unlock(&bp->hwrm_lock); \
179 if (resp->error_code) { \
180 rc = rte_le_to_cpu_16(resp->error_code); \
181 rte_spinlock_unlock(&bp->hwrm_lock); \
186 #define HWRM_CHECK_RESULT() do {\
188 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
189 rte_spinlock_unlock(&bp->hwrm_lock); \
190 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
196 if (resp->error_code) { \
197 rc = rte_le_to_cpu_16(resp->error_code); \
198 if (resp->resp_len >= 16) { \
199 struct hwrm_err_output *tmp_hwrm_err_op = \
202 "error %d:%d:%08x:%04x\n", \
203 rc, tmp_hwrm_err_op->cmd_err, \
205 tmp_hwrm_err_op->opaque_0), \
207 tmp_hwrm_err_op->opaque_1)); \
209 PMD_DRV_LOG(ERR, "error %d\n", rc); \
211 rte_spinlock_unlock(&bp->hwrm_lock); \
212 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
220 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
222 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
225 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
226 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
228 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
229 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
232 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
240 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
241 struct bnxt_vnic_info *vnic,
243 struct bnxt_vlan_table_entry *vlan_table)
246 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
247 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
250 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
253 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
254 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
256 /* FIXME add multicast flag, when multicast adding options is supported
259 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
260 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
261 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
262 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
263 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
264 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
265 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
266 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
267 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
268 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
269 if (vnic->mc_addr_cnt) {
270 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
271 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
272 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
275 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
276 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
277 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
278 rte_mem_virt2iova(vlan_table));
279 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
281 req.mask = rte_cpu_to_le_32(mask);
283 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
291 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
293 struct bnxt_vlan_antispoof_table_entry *vlan_table)
296 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
297 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
298 bp->hwrm_cmd_resp_addr;
301 * Older HWRM versions did not support this command, and the set_rx_mask
302 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
303 * removed from set_rx_mask call, and this command was added.
305 * This command is also present from 1.7.8.11 and higher,
308 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
309 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
310 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
315 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
316 req.fid = rte_cpu_to_le_16(fid);
318 req.vlan_tag_mask_tbl_addr =
319 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
320 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
322 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
330 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
331 struct bnxt_filter_info *filter)
334 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
335 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
337 if (filter->fw_l2_filter_id == UINT64_MAX)
340 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
342 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
344 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
349 filter->fw_l2_filter_id = UINT64_MAX;
354 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
356 struct bnxt_filter_info *filter)
359 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
360 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
361 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
362 const struct rte_eth_vmdq_rx_conf *conf =
363 &dev_conf->rx_adv_conf.vmdq_rx_conf;
364 uint32_t enables = 0;
365 uint16_t j = dst_id - 1;
367 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
368 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
369 conf->pool_map[j].pools & (1UL << j)) {
371 "Add vlan %u to vmdq pool %u\n",
372 conf->pool_map[j].vlan_id, j);
374 filter->l2_ivlan = conf->pool_map[j].vlan_id;
376 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
377 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
380 if (filter->fw_l2_filter_id != UINT64_MAX)
381 bnxt_hwrm_clear_l2_filter(bp, filter);
383 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
385 req.flags = rte_cpu_to_le_32(filter->flags);
387 enables = filter->enables |
388 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
389 req.dst_id = rte_cpu_to_le_16(dst_id);
392 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
393 memcpy(req.l2_addr, filter->l2_addr,
396 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
397 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
400 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
401 req.l2_ovlan = filter->l2_ovlan;
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
404 req.l2_ivlan = filter->l2_ivlan;
406 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
407 req.l2_ovlan_mask = filter->l2_ovlan_mask;
409 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
410 req.l2_ivlan_mask = filter->l2_ivlan_mask;
411 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
412 req.src_id = rte_cpu_to_le_32(filter->src_id);
413 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
414 req.src_type = filter->src_type;
416 req.enables = rte_cpu_to_le_32(enables);
418 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
422 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
428 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
430 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
431 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
438 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
441 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
444 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
445 if (ptp->tx_tstamp_en)
446 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
449 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
450 req.flags = rte_cpu_to_le_32(flags);
451 req.enables = rte_cpu_to_le_32
452 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
453 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
455 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
461 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
464 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
465 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
466 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
468 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
472 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
474 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
476 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
480 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
483 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
487 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
488 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
489 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
490 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
491 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
492 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
493 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
494 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
495 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
496 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
497 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
498 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
499 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
500 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
501 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
502 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
503 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
504 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
512 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
515 struct hwrm_func_qcaps_input req = {.req_type = 0 };
516 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
517 uint16_t new_max_vfs;
521 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
523 req.fid = rte_cpu_to_le_16(0xffff);
525 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
529 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
530 flags = rte_le_to_cpu_32(resp->flags);
532 bp->pf.port_id = resp->port_id;
533 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
534 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
535 new_max_vfs = bp->pdev->max_vfs;
536 if (new_max_vfs != bp->pf.max_vfs) {
538 rte_free(bp->pf.vf_info);
539 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
540 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
541 bp->pf.max_vfs = new_max_vfs;
542 for (i = 0; i < new_max_vfs; i++) {
543 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
544 bp->pf.vf_info[i].vlan_table =
545 rte_zmalloc("VF VLAN table",
548 if (bp->pf.vf_info[i].vlan_table == NULL)
550 "Fail to alloc VLAN table for VF %d\n",
554 bp->pf.vf_info[i].vlan_table);
555 bp->pf.vf_info[i].vlan_as_table =
556 rte_zmalloc("VF VLAN AS table",
559 if (bp->pf.vf_info[i].vlan_as_table == NULL)
561 "Alloc VLAN AS table for VF %d fail\n",
565 bp->pf.vf_info[i].vlan_as_table);
566 STAILQ_INIT(&bp->pf.vf_info[i].filter);
571 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
572 memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
573 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
574 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
575 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
576 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
577 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
578 /* TODO: For now, do not support VMDq/RFS on VFs. */
583 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
587 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
589 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
590 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
591 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
592 PMD_DRV_LOG(INFO, "PTP SUPPORTED\n");
594 bnxt_hwrm_ptp_qcfg(bp);
603 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
607 rc = __bnxt_hwrm_func_qcaps(bp);
608 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
609 rc = bnxt_hwrm_func_resc_qcaps(bp);
611 bp->flags |= BNXT_FLAG_NEW_RM;
617 int bnxt_hwrm_func_reset(struct bnxt *bp)
620 struct hwrm_func_reset_input req = {.req_type = 0 };
621 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
623 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
625 req.enables = rte_cpu_to_le_32(0);
627 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
635 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
638 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
639 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
641 if (bp->flags & BNXT_FLAG_REGISTERED)
644 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
645 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
646 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
647 req.ver_maj = RTE_VER_YEAR;
648 req.ver_min = RTE_VER_MONTH;
649 req.ver_upd = RTE_VER_MINOR;
652 req.enables |= rte_cpu_to_le_32(
653 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
654 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
655 RTE_MIN(sizeof(req.vf_req_fwd),
656 sizeof(bp->pf.vf_req_fwd)));
659 * PF can sniff HWRM API issued by VF. This can be set up by
660 * linux driver and inherited by the DPDK PF driver. Clear
661 * this HWRM sniffer list in FW because DPDK PF driver does
665 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
668 req.async_event_fwd[0] |=
669 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
670 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
671 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
672 req.async_event_fwd[1] |=
673 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
674 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
676 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
681 bp->flags |= BNXT_FLAG_REGISTERED;
686 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
688 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
691 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
694 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
699 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
700 struct hwrm_func_vf_cfg_input req = {0};
702 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
704 req.enables = rte_cpu_to_le_32
705 (HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
706 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
707 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
708 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
709 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS |
710 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS);
712 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
713 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
714 AGG_RING_MULTIPLIER);
715 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
716 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
718 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
719 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
720 if (bp->vf_resv_strategy ==
721 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
722 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
723 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
724 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
725 req.enables |= rte_cpu_to_le_32(enables);
726 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
727 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
728 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
732 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
733 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
734 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
735 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
736 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
737 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
739 req.flags = rte_cpu_to_le_32(flags);
741 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
744 HWRM_CHECK_RESULT_SILENT();
752 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
755 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
756 struct hwrm_func_resource_qcaps_input req = {0};
758 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
759 req.fid = rte_cpu_to_le_16(0xffff);
761 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
766 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
767 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
768 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
769 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
770 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
771 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
772 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
773 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
775 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
776 if (bp->vf_resv_strategy >
777 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
778 bp->vf_resv_strategy =
779 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
785 int bnxt_hwrm_ver_get(struct bnxt *bp)
788 struct hwrm_ver_get_input req = {.req_type = 0 };
789 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
792 uint16_t max_resp_len;
793 char type[RTE_MEMZONE_NAMESIZE];
794 uint32_t dev_caps_cfg;
796 bp->max_req_len = HWRM_MAX_REQ_LEN;
797 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
799 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
800 req.hwrm_intf_min = HWRM_VERSION_MINOR;
801 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
803 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
807 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
808 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
809 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
810 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
811 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
812 (resp->hwrm_fw_min_8b << 16) |
813 (resp->hwrm_fw_bld_8b << 8) |
814 resp->hwrm_fw_rsvd_8b;
815 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
816 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
818 my_version = HWRM_VERSION_MAJOR << 16;
819 my_version |= HWRM_VERSION_MINOR << 8;
820 my_version |= HWRM_VERSION_UPDATE;
822 fw_version = resp->hwrm_intf_maj_8b << 16;
823 fw_version |= resp->hwrm_intf_min_8b << 8;
824 fw_version |= resp->hwrm_intf_upd_8b;
825 bp->hwrm_spec_code = fw_version;
827 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
828 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
833 if (my_version != fw_version) {
834 PMD_DRV_LOG(INFO, "BNXT Driver/HWRM API mismatch.\n");
835 if (my_version < fw_version) {
837 "Firmware API version is newer than driver.\n");
839 "The driver may be missing features.\n");
842 "Firmware API version is older than driver.\n");
844 "Not all driver features may be functional.\n");
848 if (bp->max_req_len > resp->max_req_win_len) {
849 PMD_DRV_LOG(ERR, "Unsupported request length\n");
852 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
853 max_resp_len = resp->max_resp_len;
854 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
856 if (bp->max_resp_len != max_resp_len) {
857 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
858 bp->pdev->addr.domain, bp->pdev->addr.bus,
859 bp->pdev->addr.devid, bp->pdev->addr.function);
861 rte_free(bp->hwrm_cmd_resp_addr);
863 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
864 if (bp->hwrm_cmd_resp_addr == NULL) {
868 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
869 bp->hwrm_cmd_resp_dma_addr =
870 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
871 if (bp->hwrm_cmd_resp_dma_addr == 0) {
873 "Unable to map response buffer to physical memory.\n");
877 bp->max_resp_len = max_resp_len;
881 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
883 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
884 PMD_DRV_LOG(DEBUG, "Short command supported\n");
886 rte_free(bp->hwrm_short_cmd_req_addr);
888 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
890 if (bp->hwrm_short_cmd_req_addr == NULL) {
894 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
895 bp->hwrm_short_cmd_req_dma_addr =
896 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
897 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
898 rte_free(bp->hwrm_short_cmd_req_addr);
900 "Unable to map buffer to physical memory.\n");
905 bp->flags |= BNXT_FLAG_SHORT_CMD;
908 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
909 bp->flags |= BNXT_FLAG_KONG_MB_EN;
910 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
918 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
921 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
922 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
924 if (!(bp->flags & BNXT_FLAG_REGISTERED))
927 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
930 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
935 bp->flags &= ~BNXT_FLAG_REGISTERED;
940 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
943 struct hwrm_port_phy_cfg_input req = {0};
944 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
945 uint32_t enables = 0;
947 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
950 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
951 if (bp->link_info.auto_mode && conf->link_speed) {
952 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
953 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
956 req.flags = rte_cpu_to_le_32(conf->phy_flags);
957 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
958 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
960 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
961 * any auto mode, even "none".
963 if (!conf->link_speed) {
964 /* No speeds specified. Enable AutoNeg - all speeds */
966 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
968 /* AutoNeg - Advertise speeds specified. */
969 if (conf->auto_link_speed_mask &&
970 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
972 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
973 req.auto_link_speed_mask =
974 conf->auto_link_speed_mask;
976 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
979 req.auto_duplex = conf->duplex;
980 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
981 req.auto_pause = conf->auto_pause;
982 req.force_pause = conf->force_pause;
983 /* Set force_pause if there is no auto or if there is a force */
984 if (req.auto_pause && !req.force_pause)
985 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
987 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
989 req.enables = rte_cpu_to_le_32(enables);
992 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
993 PMD_DRV_LOG(INFO, "Force Link Down\n");
996 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1004 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1005 struct bnxt_link_info *link_info)
1008 struct hwrm_port_phy_qcfg_input req = {0};
1009 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1011 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1013 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1015 HWRM_CHECK_RESULT();
1017 link_info->phy_link_status = resp->link;
1018 link_info->link_up =
1019 (link_info->phy_link_status ==
1020 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1021 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1022 link_info->duplex = resp->duplex_cfg;
1023 link_info->pause = resp->pause;
1024 link_info->auto_pause = resp->auto_pause;
1025 link_info->force_pause = resp->force_pause;
1026 link_info->auto_mode = resp->auto_mode;
1027 link_info->phy_type = resp->phy_type;
1028 link_info->media_type = resp->media_type;
1030 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1031 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1032 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1033 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1034 link_info->phy_ver[0] = resp->phy_maj;
1035 link_info->phy_ver[1] = resp->phy_min;
1036 link_info->phy_ver[2] = resp->phy_bld;
1040 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1041 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1042 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1043 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1044 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1045 link_info->auto_link_speed_mask);
1046 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1047 link_info->force_link_speed);
1052 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1055 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1056 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1059 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1061 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1062 /* HWRM Version >= 1.9.1 */
1063 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1065 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1066 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1068 HWRM_CHECK_RESULT();
1070 #define GET_QUEUE_INFO(x) \
1071 bp->cos_queue[x].id = resp->queue_id##x; \
1072 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1085 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1086 bp->tx_cosq_id = bp->cos_queue[0].id;
1088 /* iterate and find the COSq profile to use for Tx */
1089 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1090 if (bp->cos_queue[i].profile ==
1091 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1092 bp->tx_cosq_id = bp->cos_queue[i].id;
1097 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1102 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1103 struct bnxt_ring *ring,
1104 uint32_t ring_type, uint32_t map_index,
1105 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1108 uint32_t enables = 0;
1109 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1110 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1112 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1114 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1115 req.fbo = rte_cpu_to_le_32(0);
1116 /* Association of ring index with doorbell index */
1117 req.logical_id = rte_cpu_to_le_16(map_index);
1118 req.length = rte_cpu_to_le_32(ring->ring_size);
1120 switch (ring_type) {
1121 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1122 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1124 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1125 req.ring_type = ring_type;
1126 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1127 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
1128 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1130 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1132 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1133 req.ring_type = ring_type;
1135 * TODO: Some HWRM versions crash with
1136 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
1138 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1141 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1146 req.enables = rte_cpu_to_le_32(enables);
1148 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1150 if (rc || resp->error_code) {
1151 if (rc == 0 && resp->error_code)
1152 rc = rte_le_to_cpu_16(resp->error_code);
1153 switch (ring_type) {
1154 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1156 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1159 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1161 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1164 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1166 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1170 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1176 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1181 int bnxt_hwrm_ring_free(struct bnxt *bp,
1182 struct bnxt_ring *ring, uint32_t ring_type)
1185 struct hwrm_ring_free_input req = {.req_type = 0 };
1186 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1188 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1190 req.ring_type = ring_type;
1191 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1193 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1195 if (rc || resp->error_code) {
1196 if (rc == 0 && resp->error_code)
1197 rc = rte_le_to_cpu_16(resp->error_code);
1200 switch (ring_type) {
1201 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1202 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1205 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1206 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1209 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1210 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1214 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1222 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1225 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1226 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1228 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1230 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1231 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1232 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1233 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1235 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1237 HWRM_CHECK_RESULT();
1239 bp->grp_info[idx].fw_grp_id =
1240 rte_le_to_cpu_16(resp->ring_group_id);
1247 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1250 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1251 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1253 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1255 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1257 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1259 HWRM_CHECK_RESULT();
1262 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1266 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1269 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1270 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1272 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1275 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1277 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1279 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1281 HWRM_CHECK_RESULT();
1287 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1288 unsigned int idx __rte_unused)
1291 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1292 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1294 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1296 req.update_period_ms = rte_cpu_to_le_32(0);
1298 req.stats_dma_addr =
1299 rte_cpu_to_le_64(cpr->hw_stats_map);
1301 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1303 HWRM_CHECK_RESULT();
1305 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1312 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1313 unsigned int idx __rte_unused)
1316 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1317 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1319 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1321 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1323 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1325 HWRM_CHECK_RESULT();
1331 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1334 struct hwrm_vnic_alloc_input req = { 0 };
1335 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1337 /* map ring groups to this vnic */
1338 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1339 vnic->start_grp_id, vnic->end_grp_id);
1340 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1341 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1343 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1344 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1345 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1346 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1347 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1348 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1349 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1351 if (vnic->func_default)
1353 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1354 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1356 HWRM_CHECK_RESULT();
1358 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1360 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1364 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1365 struct bnxt_vnic_info *vnic,
1366 struct bnxt_plcmodes_cfg *pmode)
1369 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1370 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1372 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1374 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1376 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1378 HWRM_CHECK_RESULT();
1380 pmode->flags = rte_le_to_cpu_32(resp->flags);
1381 /* dflt_vnic bit doesn't exist in the _cfg command */
1382 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1383 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1384 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1385 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1392 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1393 struct bnxt_vnic_info *vnic,
1394 struct bnxt_plcmodes_cfg *pmode)
1397 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1398 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1400 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1402 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1403 req.flags = rte_cpu_to_le_32(pmode->flags);
1404 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1405 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1406 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1407 req.enables = rte_cpu_to_le_32(
1408 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1409 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1410 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1413 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1415 HWRM_CHECK_RESULT();
1421 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1424 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1425 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1426 uint32_t ctx_enable_flag = 0;
1427 struct bnxt_plcmodes_cfg pmodes;
1429 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1430 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1434 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1438 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1440 /* Only RSS support for now TBD: COS & LB */
1442 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1443 if (vnic->lb_rule != 0xffff)
1444 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1445 if (vnic->cos_rule != 0xffff)
1446 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1447 if (vnic->rss_rule != 0xffff) {
1448 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1449 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1451 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1452 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1453 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1454 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1455 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1456 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1457 req.mru = rte_cpu_to_le_16(vnic->mru);
1458 if (vnic->func_default)
1460 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1461 if (vnic->vlan_strip)
1463 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1466 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1467 if (vnic->roce_dual)
1468 req.flags |= rte_cpu_to_le_32(
1469 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1470 if (vnic->roce_only)
1471 req.flags |= rte_cpu_to_le_32(
1472 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1473 if (vnic->rss_dflt_cr)
1474 req.flags |= rte_cpu_to_le_32(
1475 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1477 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1479 HWRM_CHECK_RESULT();
1482 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1487 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1491 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1492 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1494 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1495 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1498 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1501 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1502 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1503 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1507 HWRM_CHECK_RESULT();
1509 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1510 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1511 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1512 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1513 vnic->mru = rte_le_to_cpu_16(resp->mru);
1514 vnic->func_default = rte_le_to_cpu_32(
1515 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1516 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1517 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1518 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1519 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1520 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1521 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1522 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1523 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1524 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1525 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1532 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1535 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1536 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1537 bp->hwrm_cmd_resp_addr;
1539 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1541 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1543 HWRM_CHECK_RESULT();
1545 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1547 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1552 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1555 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1556 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1557 bp->hwrm_cmd_resp_addr;
1559 if (vnic->rss_rule == 0xffff) {
1560 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1563 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1565 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1567 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1569 HWRM_CHECK_RESULT();
1572 vnic->rss_rule = INVALID_HW_RING_ID;
1577 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1580 struct hwrm_vnic_free_input req = {.req_type = 0 };
1581 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1583 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1584 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1588 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1590 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1592 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1594 HWRM_CHECK_RESULT();
1597 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1601 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1602 struct bnxt_vnic_info *vnic)
1605 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1606 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1608 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1610 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1611 req.hash_mode_flags = vnic->hash_mode;
1613 req.ring_grp_tbl_addr =
1614 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1615 req.hash_key_tbl_addr =
1616 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1617 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1619 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1621 HWRM_CHECK_RESULT();
1627 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1628 struct bnxt_vnic_info *vnic)
1631 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1632 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1635 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1636 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1640 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1642 req.flags = rte_cpu_to_le_32(
1643 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1645 req.enables = rte_cpu_to_le_32(
1646 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1648 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1649 size -= RTE_PKTMBUF_HEADROOM;
1651 req.jumbo_thresh = rte_cpu_to_le_16(size);
1652 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1654 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1656 HWRM_CHECK_RESULT();
1662 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1663 struct bnxt_vnic_info *vnic, bool enable)
1666 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1667 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1669 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1672 req.enables = rte_cpu_to_le_32(
1673 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1674 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1675 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1676 req.flags = rte_cpu_to_le_32(
1677 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1678 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1679 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1680 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1681 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1682 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1683 req.max_agg_segs = rte_cpu_to_le_16(5);
1685 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1686 req.min_agg_len = rte_cpu_to_le_32(512);
1688 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1690 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1692 HWRM_CHECK_RESULT();
1698 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1700 struct hwrm_func_cfg_input req = {0};
1701 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1704 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1705 req.enables = rte_cpu_to_le_32(
1706 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1707 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1708 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1710 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1712 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1713 HWRM_CHECK_RESULT();
1716 bp->pf.vf_info[vf].random_mac = false;
1721 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1725 struct hwrm_func_qstats_input req = {.req_type = 0};
1726 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1728 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1730 req.fid = rte_cpu_to_le_16(fid);
1732 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1734 HWRM_CHECK_RESULT();
1737 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1744 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1745 struct rte_eth_stats *stats)
1748 struct hwrm_func_qstats_input req = {.req_type = 0};
1749 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1751 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1753 req.fid = rte_cpu_to_le_16(fid);
1755 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1757 HWRM_CHECK_RESULT();
1759 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1760 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1761 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1762 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1763 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1764 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1766 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1767 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1768 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1769 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1770 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1771 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1773 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1774 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1775 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1782 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1785 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1786 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1788 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1790 req.fid = rte_cpu_to_le_16(fid);
1792 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1794 HWRM_CHECK_RESULT();
1801 * HWRM utility functions
1804 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1809 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1810 struct bnxt_tx_queue *txq;
1811 struct bnxt_rx_queue *rxq;
1812 struct bnxt_cp_ring_info *cpr;
1814 if (i >= bp->rx_cp_nr_rings) {
1815 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1818 rxq = bp->rx_queues[i];
1822 rc = bnxt_hwrm_stat_clear(bp, cpr);
1829 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1833 struct bnxt_cp_ring_info *cpr;
1835 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1837 if (i >= bp->rx_cp_nr_rings) {
1838 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1840 cpr = bp->rx_queues[i]->cp_ring;
1841 bp->grp_info[i].fw_stats_ctx = -1;
1843 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1844 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1845 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1853 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1858 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1859 struct bnxt_tx_queue *txq;
1860 struct bnxt_rx_queue *rxq;
1861 struct bnxt_cp_ring_info *cpr;
1863 if (i >= bp->rx_cp_nr_rings) {
1864 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1867 rxq = bp->rx_queues[i];
1871 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1879 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1884 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1886 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1889 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1897 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1899 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1901 bnxt_hwrm_ring_free(bp, cp_ring,
1902 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1903 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1904 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1905 sizeof(*cpr->cp_desc_ring));
1906 cpr->cp_raw_cons = 0;
1909 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
1911 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
1912 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1913 struct bnxt_ring *ring = rxr->rx_ring_struct;
1914 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1916 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1917 bnxt_hwrm_ring_free(bp, ring,
1918 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1919 ring->fw_ring_id = INVALID_HW_RING_ID;
1920 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
1921 memset(rxr->rx_desc_ring, 0,
1922 rxr->rx_ring_struct->ring_size *
1923 sizeof(*rxr->rx_desc_ring));
1924 memset(rxr->rx_buf_ring, 0,
1925 rxr->rx_ring_struct->ring_size *
1926 sizeof(*rxr->rx_buf_ring));
1929 ring = rxr->ag_ring_struct;
1930 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1931 bnxt_hwrm_ring_free(bp, ring,
1932 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1933 ring->fw_ring_id = INVALID_HW_RING_ID;
1934 memset(rxr->ag_buf_ring, 0,
1935 rxr->ag_ring_struct->ring_size *
1936 sizeof(*rxr->ag_buf_ring));
1938 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
1940 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1941 bnxt_free_cp_ring(bp, cpr);
1943 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
1946 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1950 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1951 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1952 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1953 struct bnxt_ring *ring = txr->tx_ring_struct;
1954 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1956 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1957 bnxt_hwrm_ring_free(bp, ring,
1958 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1959 ring->fw_ring_id = INVALID_HW_RING_ID;
1960 memset(txr->tx_desc_ring, 0,
1961 txr->tx_ring_struct->ring_size *
1962 sizeof(*txr->tx_desc_ring));
1963 memset(txr->tx_buf_ring, 0,
1964 txr->tx_ring_struct->ring_size *
1965 sizeof(*txr->tx_buf_ring));
1969 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1970 bnxt_free_cp_ring(bp, cpr);
1971 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1975 for (i = 0; i < bp->rx_cp_nr_rings; i++)
1976 bnxt_free_hwrm_rx_ring(bp, i);
1981 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1986 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1987 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1994 void bnxt_free_hwrm_resources(struct bnxt *bp)
1996 /* Release memzone */
1997 rte_free(bp->hwrm_cmd_resp_addr);
1998 rte_free(bp->hwrm_short_cmd_req_addr);
1999 bp->hwrm_cmd_resp_addr = NULL;
2000 bp->hwrm_short_cmd_req_addr = NULL;
2001 bp->hwrm_cmd_resp_dma_addr = 0;
2002 bp->hwrm_short_cmd_req_dma_addr = 0;
2005 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2007 struct rte_pci_device *pdev = bp->pdev;
2008 char type[RTE_MEMZONE_NAMESIZE];
2010 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2011 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2012 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2013 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2014 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2015 if (bp->hwrm_cmd_resp_addr == NULL)
2017 bp->hwrm_cmd_resp_dma_addr =
2018 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2019 if (bp->hwrm_cmd_resp_dma_addr == 0) {
2021 "unable to map response address to physical memory\n");
2024 rte_spinlock_init(&bp->hwrm_lock);
2029 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2031 struct bnxt_filter_info *filter;
2034 STAILQ_FOREACH(filter, &vnic->filter, next) {
2035 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2036 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2037 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2038 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2040 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2041 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2049 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2051 struct bnxt_filter_info *filter;
2052 struct rte_flow *flow;
2055 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2056 filter = flow->filter;
2057 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2058 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2059 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2060 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2061 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2063 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2065 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2073 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2075 struct bnxt_filter_info *filter;
2078 STAILQ_FOREACH(filter, &vnic->filter, next) {
2079 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2080 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2082 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2083 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2086 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2094 void bnxt_free_tunnel_ports(struct bnxt *bp)
2096 if (bp->vxlan_port_cnt)
2097 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2098 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2100 if (bp->geneve_port_cnt)
2101 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2102 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2103 bp->geneve_port = 0;
2106 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2110 if (bp->vnic_info == NULL)
2114 * Cleanup VNICs in reverse order, to make sure the L2 filter
2115 * from vnic0 is last to be cleaned up.
2117 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2118 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2120 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2122 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2124 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2126 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2128 bnxt_hwrm_vnic_free(bp, vnic);
2130 rte_free(vnic->fw_grp_ids);
2132 /* Ring resources */
2133 bnxt_free_all_hwrm_rings(bp);
2134 bnxt_free_all_hwrm_ring_grps(bp);
2135 bnxt_free_all_hwrm_stat_ctxs(bp);
2136 bnxt_free_tunnel_ports(bp);
2139 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2141 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2143 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2144 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2146 switch (conf_link_speed) {
2147 case ETH_LINK_SPEED_10M_HD:
2148 case ETH_LINK_SPEED_100M_HD:
2150 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2152 return hw_link_duplex;
2155 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2157 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2160 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2162 uint16_t eth_link_speed = 0;
2164 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2165 return ETH_LINK_SPEED_AUTONEG;
2167 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2168 case ETH_LINK_SPEED_100M:
2169 case ETH_LINK_SPEED_100M_HD:
2172 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2174 case ETH_LINK_SPEED_1G:
2176 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2178 case ETH_LINK_SPEED_2_5G:
2180 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2182 case ETH_LINK_SPEED_10G:
2184 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2186 case ETH_LINK_SPEED_20G:
2188 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2190 case ETH_LINK_SPEED_25G:
2192 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2194 case ETH_LINK_SPEED_40G:
2196 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2198 case ETH_LINK_SPEED_50G:
2200 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2202 case ETH_LINK_SPEED_100G:
2204 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2208 "Unsupported link speed %d; default to AUTO\n",
2212 return eth_link_speed;
2215 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2216 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2217 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2218 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2220 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2224 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2227 if (link_speed & ETH_LINK_SPEED_FIXED) {
2228 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2230 if (one_speed & (one_speed - 1)) {
2232 "Invalid advertised speeds (%u) for port %u\n",
2233 link_speed, port_id);
2236 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2238 "Unsupported advertised speed (%u) for port %u\n",
2239 link_speed, port_id);
2243 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2245 "Unsupported advertised speeds (%u) for port %u\n",
2246 link_speed, port_id);
2254 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2258 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2259 if (bp->link_info.support_speeds)
2260 return bp->link_info.support_speeds;
2261 link_speed = BNXT_SUPPORTED_SPEEDS;
2264 if (link_speed & ETH_LINK_SPEED_100M)
2265 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2266 if (link_speed & ETH_LINK_SPEED_100M_HD)
2267 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2268 if (link_speed & ETH_LINK_SPEED_1G)
2269 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2270 if (link_speed & ETH_LINK_SPEED_2_5G)
2271 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2272 if (link_speed & ETH_LINK_SPEED_10G)
2273 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2274 if (link_speed & ETH_LINK_SPEED_20G)
2275 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2276 if (link_speed & ETH_LINK_SPEED_25G)
2277 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2278 if (link_speed & ETH_LINK_SPEED_40G)
2279 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2280 if (link_speed & ETH_LINK_SPEED_50G)
2281 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2282 if (link_speed & ETH_LINK_SPEED_100G)
2283 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2287 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2289 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2291 switch (hw_link_speed) {
2292 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2293 eth_link_speed = ETH_SPEED_NUM_100M;
2295 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2296 eth_link_speed = ETH_SPEED_NUM_1G;
2298 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2299 eth_link_speed = ETH_SPEED_NUM_2_5G;
2301 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2302 eth_link_speed = ETH_SPEED_NUM_10G;
2304 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2305 eth_link_speed = ETH_SPEED_NUM_20G;
2307 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2308 eth_link_speed = ETH_SPEED_NUM_25G;
2310 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2311 eth_link_speed = ETH_SPEED_NUM_40G;
2313 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2314 eth_link_speed = ETH_SPEED_NUM_50G;
2316 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2317 eth_link_speed = ETH_SPEED_NUM_100G;
2319 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2321 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2325 return eth_link_speed;
2328 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2330 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2332 switch (hw_link_duplex) {
2333 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2334 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2336 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2338 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2339 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2342 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2346 return eth_link_duplex;
2349 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2352 struct bnxt_link_info *link_info = &bp->link_info;
2354 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2357 "Get link config failed with rc %d\n", rc);
2360 if (link_info->link_speed)
2362 bnxt_parse_hw_link_speed(link_info->link_speed);
2364 link->link_speed = ETH_SPEED_NUM_NONE;
2365 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2366 link->link_status = link_info->link_up;
2367 link->link_autoneg = link_info->auto_mode ==
2368 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2369 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2374 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2377 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2378 struct bnxt_link_info link_req;
2379 uint16_t speed, autoneg;
2381 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2384 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2385 bp->eth_dev->data->port_id);
2389 memset(&link_req, 0, sizeof(link_req));
2390 link_req.link_up = link_up;
2394 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2395 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2396 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2397 /* Autoneg can be done only when the FW allows */
2398 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2399 bp->link_info.force_link_speed)) {
2400 link_req.phy_flags |=
2401 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2402 link_req.auto_link_speed_mask =
2403 bnxt_parse_eth_link_speed_mask(bp,
2404 dev_conf->link_speeds);
2406 if (bp->link_info.phy_type ==
2407 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2408 bp->link_info.phy_type ==
2409 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2410 bp->link_info.media_type ==
2411 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2412 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2416 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2417 /* If user wants a particular speed try that first. */
2419 link_req.link_speed = speed;
2420 else if (bp->link_info.force_link_speed)
2421 link_req.link_speed = bp->link_info.force_link_speed;
2423 link_req.link_speed = bp->link_info.auto_link_speed;
2425 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2426 link_req.auto_pause = bp->link_info.auto_pause;
2427 link_req.force_pause = bp->link_info.force_pause;
2430 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2433 "Set link config failed with rc %d\n", rc);
2441 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2443 struct hwrm_func_qcfg_input req = {0};
2444 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2448 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2449 req.fid = rte_cpu_to_le_16(0xffff);
2451 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2453 HWRM_CHECK_RESULT();
2455 /* Hard Coded.. 0xfff VLAN ID mask */
2456 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2457 flags = rte_le_to_cpu_16(resp->flags);
2458 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2459 bp->flags |= BNXT_FLAG_MULTI_HOST;
2461 switch (resp->port_partition_type) {
2462 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2463 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2464 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2466 bp->port_partition_type = resp->port_partition_type;
2469 bp->port_partition_type = 0;
2478 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2479 struct hwrm_func_qcaps_output *qcaps)
2481 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2482 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2483 sizeof(qcaps->mac_address));
2484 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2485 qcaps->max_rx_rings = fcfg->num_rx_rings;
2486 qcaps->max_tx_rings = fcfg->num_tx_rings;
2487 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2488 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2490 qcaps->first_vf_id = 0;
2491 qcaps->max_vnics = fcfg->num_vnics;
2492 qcaps->max_decap_records = 0;
2493 qcaps->max_encap_records = 0;
2494 qcaps->max_tx_wm_flows = 0;
2495 qcaps->max_tx_em_flows = 0;
2496 qcaps->max_rx_wm_flows = 0;
2497 qcaps->max_rx_em_flows = 0;
2498 qcaps->max_flow_id = 0;
2499 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2500 qcaps->max_sp_tx_rings = 0;
2501 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2504 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2506 struct hwrm_func_cfg_input req = {0};
2507 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2510 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2511 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2512 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2513 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2514 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2515 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2516 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2517 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2518 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2519 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2520 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2521 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2522 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2523 ETHER_CRC_LEN + VLAN_TAG_SIZE *
2525 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2526 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2527 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2528 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2529 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2530 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2531 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2532 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2533 req.fid = rte_cpu_to_le_16(0xffff);
2535 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2537 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2539 HWRM_CHECK_RESULT();
2545 static void populate_vf_func_cfg_req(struct bnxt *bp,
2546 struct hwrm_func_cfg_input *req,
2549 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2550 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2551 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2552 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2553 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2554 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2555 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2556 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2557 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2558 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2560 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2561 ETHER_CRC_LEN + VLAN_TAG_SIZE *
2563 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2564 ETHER_CRC_LEN + VLAN_TAG_SIZE *
2566 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2568 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2569 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2571 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2572 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2573 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2574 /* TODO: For now, do not support VMDq/RFS on VFs. */
2575 req->num_vnics = rte_cpu_to_le_16(1);
2576 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2580 static void add_random_mac_if_needed(struct bnxt *bp,
2581 struct hwrm_func_cfg_input *cfg_req,
2584 struct ether_addr mac;
2586 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2589 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2591 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2592 eth_random_addr(cfg_req->dflt_mac_addr);
2593 bp->pf.vf_info[vf].random_mac = true;
2595 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2599 static void reserve_resources_from_vf(struct bnxt *bp,
2600 struct hwrm_func_cfg_input *cfg_req,
2603 struct hwrm_func_qcaps_input req = {0};
2604 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2607 /* Get the actual allocated values now */
2608 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2609 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2610 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2613 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2614 copy_func_cfg_to_qcaps(cfg_req, resp);
2615 } else if (resp->error_code) {
2616 rc = rte_le_to_cpu_16(resp->error_code);
2617 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2618 copy_func_cfg_to_qcaps(cfg_req, resp);
2621 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2622 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2623 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2624 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2625 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2626 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2628 * TODO: While not supporting VMDq with VFs, max_vnics is always
2629 * forced to 1 in this case
2631 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2632 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2637 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2639 struct hwrm_func_qcfg_input req = {0};
2640 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2643 /* Check for zero MAC address */
2644 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2645 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2646 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2648 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2650 } else if (resp->error_code) {
2651 rc = rte_le_to_cpu_16(resp->error_code);
2652 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2655 rc = rte_le_to_cpu_16(resp->vlan);
2662 static int update_pf_resource_max(struct bnxt *bp)
2664 struct hwrm_func_qcfg_input req = {0};
2665 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2668 /* And copy the allocated numbers into the pf struct */
2669 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2670 req.fid = rte_cpu_to_le_16(0xffff);
2671 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2672 HWRM_CHECK_RESULT();
2674 /* Only TX ring value reflects actual allocation? TODO */
2675 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2676 bp->pf.evb_mode = resp->evb_mode;
2683 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2688 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2692 rc = bnxt_hwrm_func_qcaps(bp);
2696 bp->pf.func_cfg_flags &=
2697 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2698 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2699 bp->pf.func_cfg_flags |=
2700 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2701 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2705 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2707 struct hwrm_func_cfg_input req = {0};
2708 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2715 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2719 rc = bnxt_hwrm_func_qcaps(bp);
2724 bp->pf.active_vfs = num_vfs;
2727 * First, configure the PF to only use one TX ring. This ensures that
2728 * there are enough rings for all VFs.
2730 * If we don't do this, when we call func_alloc() later, we will lock
2731 * extra rings to the PF that won't be available during func_cfg() of
2734 * This has been fixed with firmware versions above 20.6.54
2736 bp->pf.func_cfg_flags &=
2737 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2738 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2739 bp->pf.func_cfg_flags |=
2740 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2741 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2746 * Now, create and register a buffer to hold forwarded VF requests
2748 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2749 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2750 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2751 if (bp->pf.vf_req_buf == NULL) {
2755 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2756 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2757 for (i = 0; i < num_vfs; i++)
2758 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2759 (i * HWRM_MAX_REQ_LEN);
2761 rc = bnxt_hwrm_func_buf_rgtr(bp);
2765 populate_vf_func_cfg_req(bp, &req, num_vfs);
2767 bp->pf.active_vfs = 0;
2768 for (i = 0; i < num_vfs; i++) {
2769 add_random_mac_if_needed(bp, &req, i);
2771 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2772 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2773 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2774 rc = bnxt_hwrm_send_message(bp,
2779 /* Clear enable flag for next pass */
2780 req.enables &= ~rte_cpu_to_le_32(
2781 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2783 if (rc || resp->error_code) {
2785 "Failed to initizlie VF %d\n", i);
2787 "Not all VFs available. (%d, %d)\n",
2788 rc, resp->error_code);
2795 reserve_resources_from_vf(bp, &req, i);
2796 bp->pf.active_vfs++;
2797 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2801 * Now configure the PF to use "the rest" of the resources
2802 * We're using STD_TX_RING_MODE here though which will limit the TX
2803 * rings. This will allow QoS to function properly. Not setting this
2804 * will cause PF rings to break bandwidth settings.
2806 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2810 rc = update_pf_resource_max(bp);
2817 bnxt_hwrm_func_buf_unrgtr(bp);
2821 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2823 struct hwrm_func_cfg_input req = {0};
2824 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2827 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2829 req.fid = rte_cpu_to_le_16(0xffff);
2830 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2831 req.evb_mode = bp->pf.evb_mode;
2833 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2834 HWRM_CHECK_RESULT();
2840 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2841 uint8_t tunnel_type)
2843 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2844 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2847 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
2848 req.tunnel_type = tunnel_type;
2849 req.tunnel_dst_port_val = port;
2850 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2851 HWRM_CHECK_RESULT();
2853 switch (tunnel_type) {
2854 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2855 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2856 bp->vxlan_port = port;
2858 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2859 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2860 bp->geneve_port = port;
2871 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2872 uint8_t tunnel_type)
2874 struct hwrm_tunnel_dst_port_free_input req = {0};
2875 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2878 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
2880 req.tunnel_type = tunnel_type;
2881 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2882 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2884 HWRM_CHECK_RESULT();
2890 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2893 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2894 struct hwrm_func_cfg_input req = {0};
2897 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2899 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2900 req.flags = rte_cpu_to_le_32(flags);
2901 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2903 HWRM_CHECK_RESULT();
2909 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2911 uint32_t *flag = flagp;
2913 vnic->flags = *flag;
2916 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2918 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2921 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2924 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2925 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2927 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
2929 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2930 req.req_buf_page_size = rte_cpu_to_le_16(
2931 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2932 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2933 req.req_buf_page_addr0 =
2934 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2935 if (req.req_buf_page_addr0 == 0) {
2937 "unable to map buffer address to physical memory\n");
2941 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2943 HWRM_CHECK_RESULT();
2949 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2952 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2953 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2955 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
2957 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2959 HWRM_CHECK_RESULT();
2965 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2967 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2968 struct hwrm_func_cfg_input req = {0};
2971 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2973 req.fid = rte_cpu_to_le_16(0xffff);
2974 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2975 req.enables = rte_cpu_to_le_32(
2976 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2977 req.async_event_cr = rte_cpu_to_le_16(
2978 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2979 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2981 HWRM_CHECK_RESULT();
2987 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2989 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2990 struct hwrm_func_vf_cfg_input req = {0};
2993 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
2995 req.enables = rte_cpu_to_le_32(
2996 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2997 req.async_event_cr = rte_cpu_to_le_16(
2998 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2999 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3001 HWRM_CHECK_RESULT();
3007 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3009 struct hwrm_func_cfg_input req = {0};
3010 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3011 uint16_t dflt_vlan, fid;
3012 uint32_t func_cfg_flags;
3015 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3018 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3019 fid = bp->pf.vf_info[vf].fid;
3020 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3022 fid = rte_cpu_to_le_16(0xffff);
3023 func_cfg_flags = bp->pf.func_cfg_flags;
3024 dflt_vlan = bp->vlan;
3027 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3028 req.fid = rte_cpu_to_le_16(fid);
3029 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3030 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3032 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3034 HWRM_CHECK_RESULT();
3040 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3041 uint16_t max_bw, uint16_t enables)
3043 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3044 struct hwrm_func_cfg_input req = {0};
3047 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3049 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3050 req.enables |= rte_cpu_to_le_32(enables);
3051 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3052 req.max_bw = rte_cpu_to_le_32(max_bw);
3053 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3055 HWRM_CHECK_RESULT();
3061 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3063 struct hwrm_func_cfg_input req = {0};
3064 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3067 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3069 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3070 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3071 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3072 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3074 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3076 HWRM_CHECK_RESULT();
3082 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3087 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3089 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3094 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3095 void *encaped, size_t ec_size)
3098 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3099 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3101 if (ec_size > sizeof(req.encap_request))
3104 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3106 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3107 memcpy(req.encap_request, encaped, ec_size);
3109 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3111 HWRM_CHECK_RESULT();
3117 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3118 struct ether_addr *mac)
3120 struct hwrm_func_qcfg_input req = {0};
3121 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3124 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3126 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3127 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3129 HWRM_CHECK_RESULT();
3131 memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
3138 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3139 void *encaped, size_t ec_size)
3142 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3143 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3145 if (ec_size > sizeof(req.encap_request))
3148 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3150 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3151 memcpy(req.encap_request, encaped, ec_size);
3153 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3155 HWRM_CHECK_RESULT();
3161 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3162 struct rte_eth_stats *stats, uint8_t rx)
3165 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3166 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3168 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3170 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3172 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3174 HWRM_CHECK_RESULT();
3177 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3178 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3179 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3180 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3181 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3182 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3183 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3184 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3186 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3187 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3188 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3189 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3190 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3191 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3192 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
3201 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3203 struct hwrm_port_qstats_input req = {0};
3204 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3205 struct bnxt_pf_info *pf = &bp->pf;
3208 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3210 req.port_id = rte_cpu_to_le_16(pf->port_id);
3211 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3212 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3213 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3215 HWRM_CHECK_RESULT();
3221 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3223 struct hwrm_port_clr_stats_input req = {0};
3224 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3225 struct bnxt_pf_info *pf = &bp->pf;
3228 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3229 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3230 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3233 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3235 req.port_id = rte_cpu_to_le_16(pf->port_id);
3236 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3238 HWRM_CHECK_RESULT();
3244 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3246 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3247 struct hwrm_port_led_qcaps_input req = {0};
3253 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3254 req.port_id = bp->pf.port_id;
3255 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3257 HWRM_CHECK_RESULT();
3259 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3262 bp->num_leds = resp->num_leds;
3263 memcpy(bp->leds, &resp->led0_id,
3264 sizeof(bp->leds[0]) * bp->num_leds);
3265 for (i = 0; i < bp->num_leds; i++) {
3266 struct bnxt_led_info *led = &bp->leds[i];
3268 uint16_t caps = led->led_state_caps;
3270 if (!led->led_group_id ||
3271 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3283 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3285 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3286 struct hwrm_port_led_cfg_input req = {0};
3287 struct bnxt_led_cfg *led_cfg;
3288 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3289 uint16_t duration = 0;
3292 if (!bp->num_leds || BNXT_VF(bp))
3295 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3298 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3299 duration = rte_cpu_to_le_16(500);
3301 req.port_id = bp->pf.port_id;
3302 req.num_leds = bp->num_leds;
3303 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3304 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3305 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3306 led_cfg->led_id = bp->leds[i].led_id;
3307 led_cfg->led_state = led_state;
3308 led_cfg->led_blink_on = duration;
3309 led_cfg->led_blink_off = duration;
3310 led_cfg->led_group_id = bp->leds[i].led_group_id;
3313 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3315 HWRM_CHECK_RESULT();
3321 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3325 struct hwrm_nvm_get_dir_info_input req = {0};
3326 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3328 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3330 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3332 HWRM_CHECK_RESULT();
3336 *entries = rte_le_to_cpu_32(resp->entries);
3337 *length = rte_le_to_cpu_32(resp->entry_length);
3342 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3345 uint32_t dir_entries;
3346 uint32_t entry_length;
3349 rte_iova_t dma_handle;
3350 struct hwrm_nvm_get_dir_entries_input req = {0};
3351 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3353 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3357 *data++ = dir_entries;
3358 *data++ = entry_length;
3360 memset(data, 0xff, len);
3362 buflen = dir_entries * entry_length;
3363 buf = rte_malloc("nvm_dir", buflen, 0);
3364 rte_mem_lock_page(buf);
3367 dma_handle = rte_mem_virt2iova(buf);
3368 if (dma_handle == 0) {
3370 "unable to map response address to physical memory\n");
3373 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3374 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3375 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3378 memcpy(data, buf, len > buflen ? buflen : len);
3381 HWRM_CHECK_RESULT();
3387 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3388 uint32_t offset, uint32_t length,
3393 rte_iova_t dma_handle;
3394 struct hwrm_nvm_read_input req = {0};
3395 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3397 buf = rte_malloc("nvm_item", length, 0);
3398 rte_mem_lock_page(buf);
3402 dma_handle = rte_mem_virt2iova(buf);
3403 if (dma_handle == 0) {
3405 "unable to map response address to physical memory\n");
3408 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3409 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3410 req.dir_idx = rte_cpu_to_le_16(index);
3411 req.offset = rte_cpu_to_le_32(offset);
3412 req.len = rte_cpu_to_le_32(length);
3413 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3415 memcpy(data, buf, length);
3418 HWRM_CHECK_RESULT();
3424 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3427 struct hwrm_nvm_erase_dir_entry_input req = {0};
3428 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3430 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3431 req.dir_idx = rte_cpu_to_le_16(index);
3432 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3433 HWRM_CHECK_RESULT();
3440 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3441 uint16_t dir_ordinal, uint16_t dir_ext,
3442 uint16_t dir_attr, const uint8_t *data,
3446 struct hwrm_nvm_write_input req = {0};
3447 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3448 rte_iova_t dma_handle;
3451 buf = rte_malloc("nvm_write", data_len, 0);
3452 rte_mem_lock_page(buf);
3456 dma_handle = rte_mem_virt2iova(buf);
3457 if (dma_handle == 0) {
3459 "unable to map response address to physical memory\n");
3462 memcpy(buf, data, data_len);
3464 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3466 req.dir_type = rte_cpu_to_le_16(dir_type);
3467 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3468 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3469 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3470 req.dir_data_length = rte_cpu_to_le_32(data_len);
3471 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3473 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3476 HWRM_CHECK_RESULT();
3483 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3485 uint32_t *count = cbdata;
3487 *count = *count + 1;
3490 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3491 struct bnxt_vnic_info *vnic __rte_unused)
3496 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3500 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3501 &count, bnxt_vnic_count_hwrm_stub);
3506 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3509 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3510 struct hwrm_func_vf_vnic_ids_query_output *resp =
3511 bp->hwrm_cmd_resp_addr;
3514 /* First query all VNIC ids */
3515 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3517 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3518 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3519 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3521 if (req.vnic_id_tbl_addr == 0) {
3524 "unable to map VNIC ID table address to physical memory\n");
3527 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3530 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3532 } else if (resp->error_code) {
3533 rc = rte_le_to_cpu_16(resp->error_code);
3535 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3538 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3546 * This function queries the VNIC IDs for a specified VF. It then calls
3547 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3548 * Then it calls the hwrm_cb function to program this new vnic configuration.
3550 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3551 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3552 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3554 struct bnxt_vnic_info vnic;
3556 int i, num_vnic_ids;
3561 /* First query all VNIC ids */
3562 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3563 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3564 RTE_CACHE_LINE_SIZE);
3565 if (vnic_ids == NULL) {
3569 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3570 rte_mem_lock_page(((char *)vnic_ids) + sz);
3572 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3574 if (num_vnic_ids < 0)
3575 return num_vnic_ids;
3577 /* Retrieve VNIC, update bd_stall then update */
3579 for (i = 0; i < num_vnic_ids; i++) {
3580 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3581 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3582 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3585 if (vnic.mru <= 4) /* Indicates unallocated */
3588 vnic_cb(&vnic, cbdata);
3590 rc = hwrm_cb(bp, &vnic);
3600 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3603 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3604 struct hwrm_func_cfg_input req = {0};
3607 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3609 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3610 req.enables |= rte_cpu_to_le_32(
3611 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3612 req.vlan_antispoof_mode = on ?
3613 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3614 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3615 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3617 HWRM_CHECK_RESULT();
3623 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3625 struct bnxt_vnic_info vnic;
3628 int num_vnic_ids, i;
3632 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3633 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3634 RTE_CACHE_LINE_SIZE);
3635 if (vnic_ids == NULL) {
3640 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3641 rte_mem_lock_page(((char *)vnic_ids) + sz);
3643 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3649 * Loop through to find the default VNIC ID.
3650 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3651 * by sending the hwrm_func_qcfg command to the firmware.
3653 for (i = 0; i < num_vnic_ids; i++) {
3654 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3655 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3656 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3657 bp->pf.first_vf_id + vf);
3660 if (vnic.func_default) {
3662 return vnic.fw_vnic_id;
3665 /* Could not find a default VNIC. */
3666 PMD_DRV_LOG(ERR, "No default VNIC\n");
3672 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3674 struct bnxt_filter_info *filter)
3677 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3678 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3679 uint32_t enables = 0;
3681 if (filter->fw_em_filter_id != UINT64_MAX)
3682 bnxt_hwrm_clear_em_filter(bp, filter);
3684 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3686 req.flags = rte_cpu_to_le_32(filter->flags);
3688 enables = filter->enables |
3689 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3690 req.dst_id = rte_cpu_to_le_16(dst_id);
3692 if (filter->ip_addr_type) {
3693 req.ip_addr_type = filter->ip_addr_type;
3694 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3697 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3698 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3700 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3701 memcpy(req.src_macaddr, filter->src_macaddr,
3704 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3705 memcpy(req.dst_macaddr, filter->dst_macaddr,
3708 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3709 req.ovlan_vid = filter->l2_ovlan;
3711 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3712 req.ivlan_vid = filter->l2_ivlan;
3714 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3715 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3717 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3718 req.ip_protocol = filter->ip_protocol;
3720 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3721 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3723 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3724 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3726 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3727 req.src_port = rte_cpu_to_be_16(filter->src_port);
3729 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3730 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3732 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3733 req.mirror_vnic_id = filter->mirror_vnic_id;
3735 req.enables = rte_cpu_to_le_32(enables);
3737 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3739 HWRM_CHECK_RESULT();
3741 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3747 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3750 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3751 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3753 if (filter->fw_em_filter_id == UINT64_MAX)
3756 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3757 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3759 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3761 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3763 HWRM_CHECK_RESULT();
3766 filter->fw_em_filter_id = UINT64_MAX;
3767 filter->fw_l2_filter_id = UINT64_MAX;
3772 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3774 struct bnxt_filter_info *filter)
3777 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3778 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3779 bp->hwrm_cmd_resp_addr;
3780 uint32_t enables = 0;
3782 if (filter->fw_ntuple_filter_id != UINT64_MAX)
3783 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3785 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
3787 req.flags = rte_cpu_to_le_32(filter->flags);
3789 enables = filter->enables |
3790 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3791 req.dst_id = rte_cpu_to_le_16(dst_id);
3794 if (filter->ip_addr_type) {
3795 req.ip_addr_type = filter->ip_addr_type;
3797 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3800 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3801 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3803 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3804 memcpy(req.src_macaddr, filter->src_macaddr,
3807 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3808 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3811 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3812 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3814 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3815 req.ip_protocol = filter->ip_protocol;
3817 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3818 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3820 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3821 req.src_ipaddr_mask[0] =
3822 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3824 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3825 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3827 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3828 req.dst_ipaddr_mask[0] =
3829 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3831 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3832 req.src_port = rte_cpu_to_le_16(filter->src_port);
3834 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3835 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3837 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3838 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3840 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3841 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3843 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3844 req.mirror_vnic_id = filter->mirror_vnic_id;
3846 req.enables = rte_cpu_to_le_32(enables);
3848 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3850 HWRM_CHECK_RESULT();
3852 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3858 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3859 struct bnxt_filter_info *filter)
3862 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3863 struct hwrm_cfa_ntuple_filter_free_output *resp =
3864 bp->hwrm_cmd_resp_addr;
3866 if (filter->fw_ntuple_filter_id == UINT64_MAX)
3869 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
3871 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3873 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3875 HWRM_CHECK_RESULT();
3878 filter->fw_ntuple_filter_id = UINT64_MAX;
3883 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3885 unsigned int rss_idx, fw_idx, i;
3887 if (vnic->rss_table && vnic->hash_type) {
3889 * Fill the RSS hash & redirection table with
3890 * ring group ids for all VNICs
3892 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
3893 rss_idx++, fw_idx++) {
3894 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
3895 fw_idx %= bp->rx_cp_nr_rings;
3896 if (vnic->fw_grp_ids[fw_idx] !=
3901 if (i == bp->rx_cp_nr_rings)
3903 vnic->rss_table[rss_idx] =
3904 vnic->fw_grp_ids[fw_idx];
3906 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
3911 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
3912 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3916 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
3918 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
3919 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
3921 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
3922 req->num_cmpl_dma_aggr_during_int =
3923 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
3925 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
3927 /* min timer set to 1/2 of interrupt timer */
3928 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
3930 /* buf timer set to 1/4 of interrupt timer */
3931 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
3933 req->cmpl_aggr_dma_tmr_during_int =
3934 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
3936 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
3937 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
3938 req->flags = rte_cpu_to_le_16(flags);
3941 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
3942 struct bnxt_coal *coal, uint16_t ring_id)
3944 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
3945 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
3946 bp->hwrm_cmd_resp_addr;
3949 /* Set ring coalesce parameters only for Stratus 100G NIC */
3950 if (!bnxt_stratus_device(bp))
3953 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
3954 bnxt_hwrm_set_coal_params(coal, &req);
3955 req.ring_id = rte_cpu_to_le_16(ring_id);
3956 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3957 HWRM_CHECK_RESULT();
3962 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
3964 struct hwrm_port_qstats_ext_input req = {0};
3965 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
3966 struct bnxt_pf_info *pf = &bp->pf;
3969 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
3970 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
3973 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
3975 req.port_id = rte_cpu_to_le_16(pf->port_id);
3976 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
3977 req.tx_stat_host_addr =
3978 rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3980 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
3982 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
3983 req.rx_stat_host_addr =
3984 rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3986 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
3988 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3991 bp->fw_rx_port_stats_ext_size = 0;
3992 bp->fw_tx_port_stats_ext_size = 0;
3994 bp->fw_rx_port_stats_ext_size =
3995 rte_le_to_cpu_16(resp->rx_stat_size);
3996 bp->fw_tx_port_stats_ext_size =
3997 rte_le_to_cpu_16(resp->tx_stat_size);
4000 HWRM_CHECK_RESULT();