drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (BNXT_CHIP_P5(bp)) {
 754                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
 755                         return 0;
 756         } else {
 757                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 758                         return 0;
 759         }
 760
 761         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 762                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 763
 764         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 765         if (!ptp)
 766                 return -ENOMEM;
 767
 768         if (!BNXT_CHIP_P5(bp)) {
 769                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 771                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 773                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 775                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 776                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 777                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 778                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 779                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 781                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 783                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 784                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 785                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 786                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 787         }
 788
 789         ptp->bp = bp;
 790         bp->ptp_cfg = ptp;
 791
 792         return 0;
 793 }
 794
 795 void bnxt_free_vf_info(struct bnxt *bp)
 796 {
 797         int i;
 798
 799         if (bp->pf == NULL)
 800                 return;
 801
 802         if (bp->pf->vf_info == NULL)
 803                 return;
 804
 805         for (i = 0; i < bp->pf->max_vfs; i++) {
 806                 rte_free(bp->pf->vf_info[i].vlan_table);
 807                 bp->pf->vf_info[i].vlan_table = NULL;
 808                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 809                 bp->pf->vf_info[i].vlan_as_table = NULL;
 810         }
 811         rte_free(bp->pf->vf_info);
 812         bp->pf->vf_info = NULL;
 813 }
 814
 815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 816 {
 817         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 818         int i;
 819
 820         if (vf_info)
 821                 bnxt_free_vf_info(bp);
 822
 823         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 824         if (vf_info == NULL) {
 825                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 826                 return -ENOMEM;
 827         }
 828
 829         bp->pf->max_vfs = max_vfs;
 830         for (i = 0; i < max_vfs; i++) {
 831                 vf_info[i].fid = bp->pf->first_vf_id + i;
 832                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 833                                                     getpagesize(), getpagesize());
 834                 if (vf_info[i].vlan_table == NULL) {
 835                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 836                         goto err;
 837                 }
 838                 rte_mem_lock_page(vf_info[i].vlan_table);
 839
 840                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 841                                                        getpagesize(), getpagesize());
 842                 if (vf_info[i].vlan_as_table == NULL) {
 843                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 844                         goto err;
 845                 }
 846                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 847
 848                 STAILQ_INIT(&vf_info[i].filter);
 849         }
 850
 851         bp->pf->vf_info = vf_info;
 852
 853         return 0;
 854 err:
 855         bnxt_free_vf_info(bp);
 856         return -ENOMEM;
 857 }
 858
 859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 860 {
 861         int rc = 0;
 862         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 863         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 864         uint16_t new_max_vfs;
 865         uint32_t flags;
 866
 867         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 868
 869         req.fid = rte_cpu_to_le_16(0xffff);
 870
 871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 872
 873         HWRM_CHECK_RESULT();
 874
 875         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 876         flags = rte_le_to_cpu_32(resp->flags);
 877         if (BNXT_PF(bp)) {
 878                 bp->pf->port_id = resp->port_id;
 879                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 880                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 881                 new_max_vfs = bp->pdev->max_vfs;
 882                 if (new_max_vfs != bp->pf->max_vfs) {
 883                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 884                         if (rc)
 885                                 goto unlock;
 886                 }
 887         }
 888
 889         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 890         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 891                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 892                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 893         } else {
 894                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 895         }
 896         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 897         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 898         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 899         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 900         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 901         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 902         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 903         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 904                 bp->max_l2_ctx += bp->max_rx_em_flows;
 905         /* TODO: For now, do not support VMDq/RFS on VFs. */
 906         if (BNXT_PF(bp)) {
 907                 if (bp->pf->max_vfs)
 908                         bp->max_vnics = 1;
 909                 else
 910                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 911         } else {
 912                 bp->max_vnics = 1;
 913         }
 914         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 915                     bp->max_l2_ctx, bp->max_vnics);
 916         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 917         if (BNXT_PF(bp)) {
 918                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 919                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 920                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 921                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 922                         HWRM_UNLOCK();
 923                         bnxt_hwrm_ptp_qcfg(bp);
 924                 }
 925         }
 926
 927         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 928                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 929
 930         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 931                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 932                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 933         }
 934
 935         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 936                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 937
 938         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 939                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 940
 941         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 942                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 943
 944 unlock:
 945         HWRM_UNLOCK();
 946
 947         return rc;
 948 }
 949
 950 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 951 {
 952         int rc;
 953
 954         rc = __bnxt_hwrm_func_qcaps(bp);
 955         if (rc == -ENOMEM)
 956                 return rc;
 957
 958         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 959                 rc = bnxt_alloc_ctx_mem(bp);
 960                 if (rc)
 961                         return rc;
 962
 963                 /* On older FW,
 964                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 965                  * But the error can be ignored. Return success.
 966                  */
 967                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 968                 if (!rc)
 969                         bp->flags |= BNXT_FLAG_NEW_RM;
 970         }
 971
 972         return 0;
 973 }
 974
 975 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 976 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 977 {
 978         int rc = 0;
 979         uint32_t flags;
 980         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 981         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 982
 983         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 984
 985         req.target_id = rte_cpu_to_le_16(0xffff);
 986
 987         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 988
 989         HWRM_CHECK_RESULT();
 990
 991         flags = rte_le_to_cpu_32(resp->flags);
 992
 993         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 994                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 995                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 996         }
 997
 998         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 999                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1000
1001         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1002                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1003
1004         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1005
1006         HWRM_UNLOCK();
1007
1008         return rc;
1009 }
1010
1011 int bnxt_hwrm_func_reset(struct bnxt *bp)
1012 {
1013         int rc = 0;
1014         struct hwrm_func_reset_input req = {.req_type = 0 };
1015         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1016
1017         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1018
1019         req.enables = rte_cpu_to_le_32(0);
1020
1021         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1022
1023         HWRM_CHECK_RESULT();
1024         HWRM_UNLOCK();
1025
1026         return rc;
1027 }
1028
1029 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1030 {
1031         int rc;
1032         uint32_t flags = 0;
1033         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1034         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1035
1036         if (bp->flags & BNXT_FLAG_REGISTERED)
1037                 return 0;
1038
1039         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1040                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1041         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1042                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1043
1044         /* PFs and trusted VFs should indicate the support of the
1045          * Master capability on non Stingray platform
1046          */
1047         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1048                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1049
1050         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1051         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1052                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1053         req.ver_maj = RTE_VER_YEAR;
1054         req.ver_min = RTE_VER_MONTH;
1055         req.ver_upd = RTE_VER_MINOR;
1056
1057         if (BNXT_PF(bp)) {
1058                 req.enables |= rte_cpu_to_le_32(
1059                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1060                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1061                        RTE_MIN(sizeof(req.vf_req_fwd),
1062                                sizeof(bp->pf->vf_req_fwd)));
1063         }
1064
1065         req.flags = rte_cpu_to_le_32(flags);
1066
1067         req.async_event_fwd[0] |=
1068                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1069                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1070                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1071                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1072                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1073         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1074                 req.async_event_fwd[0] |=
1075                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1076         req.async_event_fwd[1] |=
1077                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1078                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1079         if (BNXT_PF(bp))
1080                 req.async_event_fwd[1] |=
1081                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1082
1083         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1084                 req.async_event_fwd[1] |=
1085                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1086
1087         req.async_event_fwd[2] |=
1088                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
1089
1090         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1091
1092         HWRM_CHECK_RESULT();
1093
1094         flags = rte_le_to_cpu_32(resp->flags);
1095         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1096                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1097
1098         HWRM_UNLOCK();
1099
1100         bp->flags |= BNXT_FLAG_REGISTERED;
1101
1102         return rc;
1103 }
1104
1105 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1106 {
1107         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1108                 return 0;
1109
1110         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1111 }
1112
1113 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1114 {
1115         int rc;
1116         uint32_t flags = 0;
1117         uint32_t enables;
1118         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1119         struct hwrm_func_vf_cfg_input req = {0};
1120
1121         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1122
1123         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1124                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1125                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1126                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1127                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1128
1129         if (BNXT_HAS_RING_GRPS(bp)) {
1130                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1131                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1132         }
1133
1134         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1135         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1136                                             AGG_RING_MULTIPLIER);
1137         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1138         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1139                                               bp->tx_nr_rings +
1140                                               BNXT_NUM_ASYNC_CPR(bp));
1141         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1142         if (bp->vf_resv_strategy ==
1143             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1144                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1145                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1146                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1147                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1148                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1149                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1150         } else if (bp->vf_resv_strategy ==
1151                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1152                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1153                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1154         }
1155
1156         if (test)
1157                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1158                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1159                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1160                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1161                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1162                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1163
1164         if (test && BNXT_HAS_RING_GRPS(bp))
1165                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1166
1167         req.flags = rte_cpu_to_le_32(flags);
1168         req.enables |= rte_cpu_to_le_32(enables);
1169
1170         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1171
1172         if (test)
1173                 HWRM_CHECK_RESULT_SILENT();
1174         else
1175                 HWRM_CHECK_RESULT();
1176
1177         HWRM_UNLOCK();
1178         return rc;
1179 }
1180
1181 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1182 {
1183         int rc;
1184         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1185         struct hwrm_func_resource_qcaps_input req = {0};
1186
1187         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1188         req.fid = rte_cpu_to_le_16(0xffff);
1189
1190         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1191
1192         HWRM_CHECK_RESULT_SILENT();
1193
1194         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1195         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1196         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1197         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1198         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1199         /* func_resource_qcaps does not return max_rx_em_flows.
1200          * So use the value provided by func_qcaps.
1201          */
1202         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1203         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1204                 bp->max_l2_ctx += bp->max_rx_em_flows;
1205         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1206         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1207         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1208         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1209         if (bp->vf_resv_strategy >
1210             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1211                 bp->vf_resv_strategy =
1212                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1213
1214         HWRM_UNLOCK();
1215         return rc;
1216 }
1217
1218 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1219 {
1220         int rc = 0;
1221         struct hwrm_ver_get_input req = {.req_type = 0 };
1222         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1223         uint32_t fw_version;
1224         uint16_t max_resp_len;
1225         char type[RTE_MEMZONE_NAMESIZE];
1226         uint32_t dev_caps_cfg;
1227
1228         bp->max_req_len = HWRM_MAX_REQ_LEN;
1229         bp->hwrm_cmd_timeout = timeout;
1230         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1231
1232         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1233         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1234         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1235
1236         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1237
1238         if (bp->flags & BNXT_FLAG_FW_RESET)
1239                 HWRM_CHECK_RESULT_SILENT();
1240         else
1241                 HWRM_CHECK_RESULT();
1242
1243         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1244                 rc = -EAGAIN;
1245                 goto error;
1246         }
1247
1248         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1249                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1250                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1251                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1252                 resp->hwrm_fw_rsvd_8b);
1253         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1254                      (resp->hwrm_fw_min_8b << 16) |
1255                      (resp->hwrm_fw_bld_8b << 8) |
1256                      resp->hwrm_fw_rsvd_8b;
1257         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1258                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1259
1260         fw_version = resp->hwrm_intf_maj_8b << 16;
1261         fw_version |= resp->hwrm_intf_min_8b << 8;
1262         fw_version |= resp->hwrm_intf_upd_8b;
1263         bp->hwrm_spec_code = fw_version;
1264
1265         /* def_req_timeout value is in milliseconds */
1266         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1267         /* convert timeout to usec */
1268         bp->hwrm_cmd_timeout *= 1000;
1269         if (!bp->hwrm_cmd_timeout)
1270                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1271
1272         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1273                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1274                 rc = -EINVAL;
1275                 goto error;
1276         }
1277
1278         if (bp->max_req_len > resp->max_req_win_len) {
1279                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1280                 rc = -EINVAL;
1281                 goto error;
1282         }
1283
1284         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1285
1286         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1287         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1288         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1289                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1290
1291         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1292         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1293
1294         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1295         bp->max_resp_len = max_resp_len;
1296
1297         if ((dev_caps_cfg &
1298                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1299             (dev_caps_cfg &
1300              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1301                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1302                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1303         }
1304
1305         if (((dev_caps_cfg &
1306               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1307              (dev_caps_cfg &
1308               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1309             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1310                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1311                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1312                         bp->pdev->addr.devid, bp->pdev->addr.function);
1313
1314                 rte_free(bp->hwrm_short_cmd_req_addr);
1315
1316                 bp->hwrm_short_cmd_req_addr =
1317                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1318                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1319                         rc = -ENOMEM;
1320                         goto error;
1321                 }
1322                 bp->hwrm_short_cmd_req_dma_addr =
1323                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1324                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1325                         rte_free(bp->hwrm_short_cmd_req_addr);
1326                         PMD_DRV_LOG(ERR,
1327                                 "Unable to map buffer to physical memory.\n");
1328                         rc = -ENOMEM;
1329                         goto error;
1330                 }
1331         }
1332         if (dev_caps_cfg &
1333             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1334                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1335                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1336         }
1337         if (dev_caps_cfg &
1338             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1339                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1340         if (dev_caps_cfg &
1341             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1342                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1343                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1344         }
1345
1346         if (dev_caps_cfg &
1347             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1348                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1349                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1350         }
1351
1352         if (dev_caps_cfg &
1353             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
1354                 PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
1355                 bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
1356         }
1357
1358 error:
1359         HWRM_UNLOCK();
1360         return rc;
1361 }
1362
1363 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1364 {
1365         int rc;
1366         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1367         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1368
1369         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1370                 return 0;
1371
1372         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1373         req.flags = flags;
1374
1375         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1376
1377         HWRM_CHECK_RESULT();
1378         HWRM_UNLOCK();
1379
1380         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1381                     bp->eth_dev->data->port_id);
1382
1383         return rc;
1384 }
1385
1386 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1387 {
1388         int rc = 0;
1389         struct hwrm_port_phy_cfg_input req = {0};
1390         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1391         uint32_t enables = 0;
1392
1393         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1394
1395         if (conf->link_up) {
1396                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1397                 if (bp->link_info->auto_mode && conf->link_speed) {
1398                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1399                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1400                 }
1401
1402                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1403                 /*
1404                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1405                  * any auto mode, even "none".
1406                  */
1407                 if (!conf->link_speed) {
1408                         /* No speeds specified. Enable AutoNeg - all speeds */
1409                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1410                         req.auto_mode =
1411                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1412                 } else {
1413                         if (bp->link_info->link_signal_mode) {
1414                                 enables |=
1415                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1416                                 req.force_pam4_link_speed =
1417                                         rte_cpu_to_le_16(conf->link_speed);
1418                         } else {
1419                                 req.force_link_speed =
1420                                         rte_cpu_to_le_16(conf->link_speed);
1421                         }
1422                 }
1423                 /* AutoNeg - Advertise speeds specified. */
1424                 if (conf->auto_link_speed_mask &&
1425                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1426                         req.auto_mode =
1427                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1428                         req.auto_link_speed_mask =
1429                                 conf->auto_link_speed_mask;
1430                         if (conf->auto_pam4_link_speeds) {
1431                                 enables |=
1432                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1433                                 req.auto_link_pam4_speed_mask =
1434                                         conf->auto_pam4_link_speeds;
1435                         } else {
1436                                 enables |=
1437                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1438                         }
1439                 }
1440                 if (conf->auto_link_speed &&
1441                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1442                         enables |=
1443                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1444
1445                 req.auto_duplex = conf->duplex;
1446                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1447                 req.auto_pause = conf->auto_pause;
1448                 req.force_pause = conf->force_pause;
1449                 /* Set force_pause if there is no auto or if there is a force */
1450                 if (req.auto_pause && !req.force_pause)
1451                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1452                 else
1453                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1454
1455                 req.enables = rte_cpu_to_le_32(enables);
1456         } else {
1457                 req.flags =
1458                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1459                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1460         }
1461
1462         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1463
1464         HWRM_CHECK_RESULT();
1465         HWRM_UNLOCK();
1466
1467         return rc;
1468 }
1469
1470 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1471                                    struct bnxt_link_info *link_info)
1472 {
1473         int rc = 0;
1474         struct hwrm_port_phy_qcfg_input req = {0};
1475         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1476
1477         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1478
1479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1480
1481         HWRM_CHECK_RESULT();
1482
1483         link_info->phy_link_status = resp->link;
1484         link_info->link_up =
1485                 (link_info->phy_link_status ==
1486                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1487         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1488         link_info->duplex = resp->duplex_cfg;
1489         link_info->pause = resp->pause;
1490         link_info->auto_pause = resp->auto_pause;
1491         link_info->force_pause = resp->force_pause;
1492         link_info->auto_mode = resp->auto_mode;
1493         link_info->phy_type = resp->phy_type;
1494         link_info->media_type = resp->media_type;
1495
1496         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1497         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1498         link_info->auto_link_speed_mask = rte_le_to_cpu_16(resp->auto_link_speed_mask);
1499         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1500         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1501         link_info->phy_ver[0] = resp->phy_maj;
1502         link_info->phy_ver[1] = resp->phy_min;
1503         link_info->phy_ver[2] = resp->phy_bld;
1504         link_info->link_signal_mode =
1505                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1506         link_info->force_pam4_link_speed =
1507                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1508         link_info->support_pam4_speeds =
1509                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1510         link_info->auto_pam4_link_speeds =
1511                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1512         link_info->module_status = resp->module_status;
1513         HWRM_UNLOCK();
1514
1515         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1516                     link_info->link_speed, link_info->auto_mode,
1517                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1518                     link_info->support_speeds, link_info->force_link_speed);
1519         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1520                     link_info->link_signal_mode,
1521                     link_info->auto_pam4_link_speeds,
1522                     link_info->support_pam4_speeds,
1523                     link_info->force_pam4_link_speed);
1524         return rc;
1525 }
1526
1527 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1528 {
1529         int rc = 0;
1530         struct hwrm_port_phy_qcaps_input req = {0};
1531         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1532         struct bnxt_link_info *link_info = bp->link_info;
1533
1534         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1535                 return 0;
1536
1537         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1538
1539         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1540
1541         HWRM_CHECK_RESULT_SILENT();
1542
1543         bp->port_cnt = resp->port_cnt;
1544         if (resp->supported_speeds_auto_mode)
1545                 link_info->support_auto_speeds =
1546                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1547         if (resp->supported_pam4_speeds_auto_mode)
1548                 link_info->support_pam4_auto_speeds =
1549                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1550
1551         HWRM_UNLOCK();
1552
1553         /* Older firmware does not have supported_auto_speeds, so assume
1554          * that all supported speeds can be autonegotiated.
1555          */
1556         if (link_info->auto_link_speed_mask && !link_info->support_auto_speeds)
1557                 link_info->support_auto_speeds = link_info->support_speeds;
1558
1559         return 0;
1560 }
1561
1562 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1563 {
1564         int i = 0;
1565
1566         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1567                 if (bp->tx_cos_queue[i].profile ==
1568                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1569                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1570                         return true;
1571                 }
1572         }
1573         return false;
1574 }
1575
1576 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1577 {
1578         int i = 0;
1579
1580         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1581                 if (bp->tx_cos_queue[i].profile !=
1582                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1583                     bp->tx_cos_queue[i].id !=
1584                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1585                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1586                         break;
1587                 }
1588         }
1589 }
1590
1591 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1592 {
1593         int rc = 0;
1594         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1595         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1596         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1597         int i;
1598
1599 get_rx_info:
1600         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1601
1602         req.flags = rte_cpu_to_le_32(dir);
1603         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1604         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1605             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1606                 req.drv_qmap_cap =
1607                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1608         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1609
1610         HWRM_CHECK_RESULT();
1611
1612         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1613                 GET_TX_QUEUE_INFO(0);
1614                 GET_TX_QUEUE_INFO(1);
1615                 GET_TX_QUEUE_INFO(2);
1616                 GET_TX_QUEUE_INFO(3);
1617                 GET_TX_QUEUE_INFO(4);
1618                 GET_TX_QUEUE_INFO(5);
1619                 GET_TX_QUEUE_INFO(6);
1620                 GET_TX_QUEUE_INFO(7);
1621         } else  {
1622                 GET_RX_QUEUE_INFO(0);
1623                 GET_RX_QUEUE_INFO(1);
1624                 GET_RX_QUEUE_INFO(2);
1625                 GET_RX_QUEUE_INFO(3);
1626                 GET_RX_QUEUE_INFO(4);
1627                 GET_RX_QUEUE_INFO(5);
1628                 GET_RX_QUEUE_INFO(6);
1629                 GET_RX_QUEUE_INFO(7);
1630         }
1631
1632         HWRM_UNLOCK();
1633
1634         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1635                 goto done;
1636
1637         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1638                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1639         } else {
1640                 int j;
1641
1642                 /* iterate and find the COSq profile to use for Tx */
1643                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1644                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1645                                 if (bp->tx_cos_queue[i].id != 0xff)
1646                                         bp->tx_cosq_id[j++] =
1647                                                 bp->tx_cos_queue[i].id;
1648                         }
1649                 } else {
1650                         /* When CoS classification is disabled, for normal NIC
1651                          * operations, ideally we should look to use LOSSY.
1652                          * If not found, fallback to the first valid profile
1653                          */
1654                         if (!bnxt_find_lossy_profile(bp))
1655                                 bnxt_find_first_valid_profile(bp);
1656
1657                 }
1658         }
1659
1660         bp->max_tc = resp->max_configurable_queues;
1661         bp->max_lltc = resp->max_configurable_lossless_queues;
1662         if (bp->max_tc > BNXT_MAX_QUEUE)
1663                 bp->max_tc = BNXT_MAX_QUEUE;
1664         bp->max_q = bp->max_tc;
1665
1666         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1667                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1668                 goto get_rx_info;
1669         }
1670
1671 done:
1672         return rc;
1673 }
1674
1675 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1676                          struct bnxt_ring *ring,
1677                          uint32_t ring_type, uint32_t map_index,
1678                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1679                          uint16_t tx_cosq_id)
1680 {
1681         int rc = 0;
1682         uint32_t enables = 0;
1683         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1684         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1685         struct rte_mempool *mb_pool;
1686         uint16_t rx_buf_size;
1687
1688         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1689
1690         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1691         req.fbo = rte_cpu_to_le_32(0);
1692         /* Association of ring index with doorbell index */
1693         req.logical_id = rte_cpu_to_le_16(map_index);
1694         req.length = rte_cpu_to_le_32(ring->ring_size);
1695
1696         switch (ring_type) {
1697         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1698                 req.ring_type = ring_type;
1699                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1700                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1701                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1702                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1703                         enables |=
1704                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1705                 break;
1706         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1707                 req.ring_type = ring_type;
1708                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1709                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1710                 if (BNXT_CHIP_P5(bp)) {
1711                         mb_pool = bp->rx_queues[0]->mb_pool;
1712                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1713                                       RTE_PKTMBUF_HEADROOM;
1714                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1715                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1716                         enables |=
1717                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1718                 }
1719                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1720                         enables |=
1721                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1722                 break;
1723         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1724                 req.ring_type = ring_type;
1725                 if (BNXT_HAS_NQ(bp)) {
1726                         /* Association of cp ring with nq */
1727                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1728                         enables |=
1729                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1730                 }
1731                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1732                 break;
1733         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1734                 req.ring_type = ring_type;
1735                 req.page_size = BNXT_PAGE_SHFT;
1736                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1737                 break;
1738         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1739                 req.ring_type = ring_type;
1740                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1741
1742                 mb_pool = bp->rx_queues[0]->mb_pool;
1743                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1744                               RTE_PKTMBUF_HEADROOM;
1745                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1746                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1747
1748                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1749                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1750                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1751                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1752                 break;
1753         default:
1754                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1755                         ring_type);
1756                 HWRM_UNLOCK();
1757                 return -EINVAL;
1758         }
1759         req.enables = rte_cpu_to_le_32(enables);
1760
1761         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1762
1763         if (rc || resp->error_code) {
1764                 if (rc == 0 && resp->error_code)
1765                         rc = rte_le_to_cpu_16(resp->error_code);
1766                 switch (ring_type) {
1767                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1768                         PMD_DRV_LOG(ERR,
1769                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1770                         HWRM_UNLOCK();
1771                         return rc;
1772                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1773                         PMD_DRV_LOG(ERR,
1774                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1775                         HWRM_UNLOCK();
1776                         return rc;
1777                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1778                         PMD_DRV_LOG(ERR,
1779                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1780                                     rc);
1781                         HWRM_UNLOCK();
1782                         return rc;
1783                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1784                         PMD_DRV_LOG(ERR,
1785                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1786                         HWRM_UNLOCK();
1787                         return rc;
1788                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1789                         PMD_DRV_LOG(ERR,
1790                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1791                         HWRM_UNLOCK();
1792                         return rc;
1793                 default:
1794                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1795                         HWRM_UNLOCK();
1796                         return rc;
1797                 }
1798         }
1799
1800         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1801         HWRM_UNLOCK();
1802         return rc;
1803 }
1804
1805 int bnxt_hwrm_ring_free(struct bnxt *bp,
1806                         struct bnxt_ring *ring, uint32_t ring_type,
1807                         uint16_t cp_ring_id)
1808 {
1809         int rc;
1810         struct hwrm_ring_free_input req = {.req_type = 0 };
1811         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1812
1813         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1814
1815         req.ring_type = ring_type;
1816         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1817         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1818
1819         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1820
1821         if (rc || resp->error_code) {
1822                 if (rc == 0 && resp->error_code)
1823                         rc = rte_le_to_cpu_16(resp->error_code);
1824                 HWRM_UNLOCK();
1825
1826                 switch (ring_type) {
1827                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1828                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1829                                 rc);
1830                         return rc;
1831                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1832                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1833                                 rc);
1834                         return rc;
1835                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1836                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1837                                 rc);
1838                         return rc;
1839                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1840                         PMD_DRV_LOG(ERR,
1841                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1842                         return rc;
1843                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1844                         PMD_DRV_LOG(ERR,
1845                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1846                         return rc;
1847                 default:
1848                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1849                         return rc;
1850                 }
1851         }
1852         HWRM_UNLOCK();
1853         return 0;
1854 }
1855
1856 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1857 {
1858         int rc = 0;
1859         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1860         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1861
1862         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1863
1864         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1865         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1866         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1867         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1868
1869         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1870
1871         HWRM_CHECK_RESULT();
1872
1873         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1874
1875         HWRM_UNLOCK();
1876
1877         return rc;
1878 }
1879
1880 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1881 {
1882         int rc;
1883         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1884         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1885
1886         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1887
1888         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1889
1890         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1891
1892         HWRM_CHECK_RESULT();
1893         HWRM_UNLOCK();
1894
1895         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1896         return rc;
1897 }
1898
1899 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1900 {
1901         int rc = 0;
1902         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1903         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1904
1905         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1906                 return rc;
1907
1908         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1909
1910         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1911
1912         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1913
1914         HWRM_CHECK_RESULT();
1915         HWRM_UNLOCK();
1916
1917         return rc;
1918 }
1919
1920 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1921 {
1922         int rc;
1923         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1924         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1925
1926         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1927
1928         req.update_period_ms = rte_cpu_to_le_32(0);
1929
1930         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1931
1932         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933
1934         HWRM_CHECK_RESULT();
1935
1936         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1937
1938         HWRM_UNLOCK();
1939
1940         return rc;
1941 }
1942
1943 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1944 {
1945         int rc;
1946         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1947         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1948
1949         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1950
1951         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1952
1953         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1954
1955         HWRM_CHECK_RESULT();
1956         HWRM_UNLOCK();
1957
1958         return rc;
1959 }
1960
1961 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1962 {
1963         int rc = 0, i, j;
1964         struct hwrm_vnic_alloc_input req = { 0 };
1965         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1966
1967         if (!BNXT_HAS_RING_GRPS(bp))
1968                 goto skip_ring_grps;
1969
1970         /* map ring groups to this vnic */
1971         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1972                 vnic->start_grp_id, vnic->end_grp_id);
1973         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1974                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1975
1976         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1977         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1978         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1979         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1980
1981 skip_ring_grps:
1982         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1983         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1984
1985         if (vnic->func_default)
1986                 req.flags =
1987                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1988         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1989
1990         HWRM_CHECK_RESULT();
1991
1992         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1993         HWRM_UNLOCK();
1994         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1995         return rc;
1996 }
1997
1998 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1999                                         struct bnxt_vnic_info *vnic,
2000                                         struct bnxt_plcmodes_cfg *pmode)
2001 {
2002         int rc = 0;
2003         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2004         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2005
2006         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2007
2008         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2009
2010         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2011
2012         HWRM_CHECK_RESULT();
2013
2014         pmode->flags = rte_le_to_cpu_32(resp->flags);
2015         /* dflt_vnic bit doesn't exist in the _cfg command */
2016         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2017         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2018         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2019         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2020
2021         HWRM_UNLOCK();
2022
2023         return rc;
2024 }
2025
2026 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2027                                        struct bnxt_vnic_info *vnic,
2028                                        struct bnxt_plcmodes_cfg *pmode)
2029 {
2030         int rc = 0;
2031         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2032         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2033
2034         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2035                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2036                 return rc;
2037         }
2038
2039         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2040
2041         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2042         req.flags = rte_cpu_to_le_32(pmode->flags);
2043         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2044         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2045         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2046         req.enables = rte_cpu_to_le_32(
2047             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2048             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2049             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2050         );
2051
2052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2053
2054         HWRM_CHECK_RESULT();
2055         HWRM_UNLOCK();
2056
2057         return rc;
2058 }
2059
2060 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2061 {
2062         int rc = 0;
2063         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2064         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2065         struct bnxt_plcmodes_cfg pmodes = { 0 };
2066         uint32_t ctx_enable_flag = 0;
2067         uint32_t enables = 0;
2068
2069         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2070                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2071                 return rc;
2072         }
2073
2074         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2075         if (rc)
2076                 return rc;
2077
2078         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2079
2080         if (BNXT_CHIP_P5(bp)) {
2081                 int dflt_rxq = vnic->start_grp_id;
2082                 struct bnxt_rx_ring_info *rxr;
2083                 struct bnxt_cp_ring_info *cpr;
2084                 struct bnxt_rx_queue *rxq;
2085                 int i;
2086
2087                 /*
2088                  * The first active receive ring is used as the VNIC
2089                  * default receive ring. If there are no active receive
2090                  * rings (all corresponding receive queues are stopped),
2091                  * the first receive ring is used.
2092                  */
2093                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2094                         rxq = bp->eth_dev->data->rx_queues[i];
2095                         if (rxq->rx_started) {
2096                                 dflt_rxq = i;
2097                                 break;
2098                         }
2099                 }
2100
2101                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2102                 rxr = rxq->rx_ring;
2103                 cpr = rxq->cp_ring;
2104
2105                 req.default_rx_ring_id =
2106                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2107                 req.default_cmpl_ring_id =
2108                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2109                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2110                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2111                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2112                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2113                         req.rx_csum_v2_mode =
2114                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2115                 }
2116                 goto config_mru;
2117         }
2118
2119         /* Only RSS support for now TBD: COS & LB */
2120         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2121         if (vnic->lb_rule != 0xffff)
2122                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2123         if (vnic->cos_rule != 0xffff)
2124                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2125         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2126                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2127                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2128         }
2129         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2130                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2131                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2132         }
2133
2134         enables |= ctx_enable_flag;
2135         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2136         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2137         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2138         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2139
2140 config_mru:
2141         req.enables = rte_cpu_to_le_32(enables);
2142         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2143         req.mru = rte_cpu_to_le_16(vnic->mru);
2144         /* Configure default VNIC only once. */
2145         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2146                 req.flags |=
2147                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2148                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2149         }
2150         if (vnic->vlan_strip)
2151                 req.flags |=
2152                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2153         if (vnic->bd_stall)
2154                 req.flags |=
2155                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2156         if (vnic->rss_dflt_cr)
2157                 req.flags |= rte_cpu_to_le_32(
2158                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2159
2160         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2161
2162         HWRM_CHECK_RESULT();
2163         HWRM_UNLOCK();
2164
2165         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2166
2167         return rc;
2168 }
2169
2170 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2171                 int16_t fw_vf_id)
2172 {
2173         int rc = 0;
2174         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2175         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2176
2177         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2178                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2179                 return rc;
2180         }
2181         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2182
2183         req.enables =
2184                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2185         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2186         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2187
2188         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2189
2190         HWRM_CHECK_RESULT();
2191
2192         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2193         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2194         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2195         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2196         vnic->mru = rte_le_to_cpu_16(resp->mru);
2197         vnic->func_default = rte_le_to_cpu_32(
2198                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2199         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2200                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2201         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2202                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2203         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2204                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2205
2206         HWRM_UNLOCK();
2207
2208         return rc;
2209 }
2210
2211 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2212                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2213 {
2214         int rc = 0;
2215         uint16_t ctx_id;
2216         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2217         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2218                                                 bp->hwrm_cmd_resp_addr;
2219
2220         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2221
2222         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2223         HWRM_CHECK_RESULT();
2224
2225         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2226         if (!BNXT_HAS_RING_GRPS(bp))
2227                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2228         else if (ctx_idx == 0)
2229                 vnic->rss_rule = ctx_id;
2230
2231         HWRM_UNLOCK();
2232
2233         return rc;
2234 }
2235
2236 static
2237 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2238                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2239 {
2240         int rc = 0;
2241         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2242         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2243                                                 bp->hwrm_cmd_resp_addr;
2244
2245         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2246                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2247                 return rc;
2248         }
2249         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2250
2251         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2252
2253         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2254
2255         HWRM_CHECK_RESULT();
2256         HWRM_UNLOCK();
2257
2258         return rc;
2259 }
2260
2261 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2262 {
2263         int rc = 0;
2264
2265         if (BNXT_CHIP_P5(bp)) {
2266                 int j;
2267
2268                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2269                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2270                                                       vnic,
2271                                                       vnic->fw_grp_ids[j]);
2272                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2273                 }
2274                 vnic->num_lb_ctxts = 0;
2275         } else {
2276                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2277                 vnic->rss_rule = INVALID_HW_RING_ID;
2278         }
2279
2280         return rc;
2281 }
2282
2283 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2284 {
2285         int rc = 0;
2286         struct hwrm_vnic_free_input req = {.req_type = 0 };
2287         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2288
2289         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2290                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2291                 return rc;
2292         }
2293
2294         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2295
2296         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2297
2298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2299
2300         HWRM_CHECK_RESULT();
2301         HWRM_UNLOCK();
2302
2303         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2304         /* Configure default VNIC again if necessary. */
2305         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2306                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2307
2308         return rc;
2309 }
2310
2311 static int
2312 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2313 {
2314         int i;
2315         int rc = 0;
2316         int nr_ctxs = vnic->num_lb_ctxts;
2317         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2318         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2319
2320         for (i = 0; i < nr_ctxs; i++) {
2321                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2322
2323                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2324                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2325                 req.hash_mode_flags = vnic->hash_mode;
2326
2327                 req.hash_key_tbl_addr =
2328                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2329
2330                 req.ring_grp_tbl_addr =
2331                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2332                                          i * HW_HASH_INDEX_SIZE);
2333                 req.ring_table_pair_index = i;
2334                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2335
2336                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2337                                             BNXT_USE_CHIMP_MB);
2338
2339                 HWRM_CHECK_RESULT();
2340                 HWRM_UNLOCK();
2341         }
2342
2343         return rc;
2344 }
2345
2346 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2347                            struct bnxt_vnic_info *vnic)
2348 {
2349         int rc = 0;
2350         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2351         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2352
2353         if (!vnic->rss_table)
2354                 return 0;
2355
2356         if (BNXT_CHIP_P5(bp))
2357                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2358
2359         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2360
2361         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2362         req.hash_mode_flags = vnic->hash_mode;
2363
2364         req.ring_grp_tbl_addr =
2365             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2366         req.hash_key_tbl_addr =
2367             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2368         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2369         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2370
2371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2372
2373         HWRM_CHECK_RESULT();
2374         HWRM_UNLOCK();
2375
2376         return rc;
2377 }
2378
2379 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2380                         struct bnxt_vnic_info *vnic)
2381 {
2382         int rc = 0;
2383         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2384         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2385         uint16_t size;
2386
2387         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2388                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2389                 return rc;
2390         }
2391
2392         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2393
2394         req.flags = rte_cpu_to_le_32(
2395                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2396
2397         req.enables = rte_cpu_to_le_32(
2398                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2399
2400         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2401         size -= RTE_PKTMBUF_HEADROOM;
2402         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2403
2404         req.jumbo_thresh = rte_cpu_to_le_16(size);
2405         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2406
2407         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2408
2409         HWRM_CHECK_RESULT();
2410         HWRM_UNLOCK();
2411
2412         return rc;
2413 }
2414
2415 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2416                         struct bnxt_vnic_info *vnic, bool enable)
2417 {
2418         int rc = 0;
2419         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2420         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2421
2422         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2423                 if (enable)
2424                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2425                 return -ENOTSUP;
2426         }
2427
2428         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2429                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2430                 return 0;
2431         }
2432
2433         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2434
2435         if (enable) {
2436                 req.enables = rte_cpu_to_le_32(
2437                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2438                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2439                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2440                 req.flags = rte_cpu_to_le_32(
2441                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2442                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2443                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2444                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2445                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2446                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2447                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2448                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2449                 req.min_agg_len = rte_cpu_to_le_32(512);
2450         }
2451         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2452
2453         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2454
2455         HWRM_CHECK_RESULT();
2456         HWRM_UNLOCK();
2457
2458         return rc;
2459 }
2460
2461 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2462 {
2463         struct hwrm_func_cfg_input req = {0};
2464         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2465         int rc;
2466
2467         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2468         req.enables = rte_cpu_to_le_32(
2469                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2470         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2471         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2472
2473         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2474
2475         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2476         HWRM_CHECK_RESULT();
2477         HWRM_UNLOCK();
2478
2479         bp->pf->vf_info[vf].random_mac = false;
2480
2481         return rc;
2482 }
2483
2484 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2485                                   uint64_t *dropped)
2486 {
2487         int rc = 0;
2488         struct hwrm_func_qstats_input req = {.req_type = 0};
2489         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2490
2491         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2492
2493         req.fid = rte_cpu_to_le_16(fid);
2494
2495         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2496
2497         HWRM_CHECK_RESULT();
2498
2499         if (dropped)
2500                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2501
2502         HWRM_UNLOCK();
2503
2504         return rc;
2505 }
2506
2507 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2508                           struct rte_eth_stats *stats,
2509                           struct hwrm_func_qstats_output *func_qstats)
2510 {
2511         int rc = 0;
2512         struct hwrm_func_qstats_input req = {.req_type = 0};
2513         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2514
2515         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2516
2517         req.fid = rte_cpu_to_le_16(fid);
2518
2519         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2520
2521         HWRM_CHECK_RESULT();
2522         if (func_qstats)
2523                 memcpy(func_qstats, resp,
2524                        sizeof(struct hwrm_func_qstats_output));
2525
2526         if (!stats)
2527                 goto exit;
2528
2529         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2530         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2531         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2532         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2533         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2534         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2535
2536         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2537         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2538         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2539         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2540         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2541         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2542
2543         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2544         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2545         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2546
2547 exit:
2548         HWRM_UNLOCK();
2549
2550         return rc;
2551 }
2552
2553 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2554 {
2555         int rc = 0;
2556         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2557         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2558
2559         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2560
2561         req.fid = rte_cpu_to_le_16(fid);
2562
2563         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2564
2565         HWRM_CHECK_RESULT();
2566         HWRM_UNLOCK();
2567
2568         return rc;
2569 }
2570
2571 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2572 {
2573         unsigned int i;
2574         int rc = 0;
2575
2576         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2577                 struct bnxt_tx_queue *txq;
2578                 struct bnxt_rx_queue *rxq;
2579                 struct bnxt_cp_ring_info *cpr;
2580
2581                 if (i >= bp->rx_cp_nr_rings) {
2582                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2583                         cpr = txq->cp_ring;
2584                 } else {
2585                         rxq = bp->rx_queues[i];
2586                         cpr = rxq->cp_ring;
2587                 }
2588
2589                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2590                 if (rc)
2591                         return rc;
2592         }
2593         return 0;
2594 }
2595
2596 static int
2597 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2598 {
2599         int rc;
2600         unsigned int i;
2601         struct bnxt_cp_ring_info *cpr;
2602
2603         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2604
2605                 if (i >= bp->rx_cp_nr_rings) {
2606                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2607                 } else {
2608                         cpr = bp->rx_queues[i]->cp_ring;
2609                         if (BNXT_HAS_RING_GRPS(bp))
2610                                 bp->grp_info[i].fw_stats_ctx = -1;
2611                 }
2612                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2613                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2614                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2615                         if (rc)
2616                                 return rc;
2617                 }
2618         }
2619         return 0;
2620 }
2621
2622 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2623 {
2624         unsigned int i;
2625         int rc = 0;
2626
2627         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2628                 struct bnxt_tx_queue *txq;
2629                 struct bnxt_rx_queue *rxq;
2630                 struct bnxt_cp_ring_info *cpr;
2631
2632                 if (i >= bp->rx_cp_nr_rings) {
2633                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2634                         cpr = txq->cp_ring;
2635                 } else {
2636                         rxq = bp->rx_queues[i];
2637                         cpr = rxq->cp_ring;
2638                 }
2639
2640                 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
2641                         rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2642                         if (rc)
2643                                 return rc;
2644                 }
2645         }
2646         return rc;
2647 }
2648
2649 static int
2650 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2651 {
2652         uint16_t idx;
2653         uint32_t rc = 0;
2654
2655         if (!BNXT_HAS_RING_GRPS(bp))
2656                 return 0;
2657
2658         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2659
2660                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2661                         continue;
2662
2663                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2664
2665                 if (rc)
2666                         return rc;
2667         }
2668         return rc;
2669 }
2670
2671 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2672 {
2673         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2674
2675         bnxt_hwrm_ring_free(bp, cp_ring,
2676                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2677                             INVALID_HW_RING_ID);
2678         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2679         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2680                                      sizeof(*cpr->cp_desc_ring));
2681         cpr->cp_raw_cons = 0;
2682 }
2683
2684 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2685 {
2686         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2687
2688         bnxt_hwrm_ring_free(bp, cp_ring,
2689                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2690                         INVALID_HW_RING_ID);
2691         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2692         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2693                         sizeof(*cpr->cp_desc_ring));
2694         cpr->cp_raw_cons = 0;
2695 }
2696
2697 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2698 {
2699         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2700         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2701         struct bnxt_ring *ring = rxr->rx_ring_struct;
2702         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2703
2704         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2705                 bnxt_hwrm_ring_free(bp, ring,
2706                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2707                                     cpr->cp_ring_struct->fw_ring_id);
2708                 ring->fw_ring_id = INVALID_HW_RING_ID;
2709                 if (BNXT_HAS_RING_GRPS(bp))
2710                         bp->grp_info[queue_index].rx_fw_ring_id =
2711                                                         INVALID_HW_RING_ID;
2712         }
2713         ring = rxr->ag_ring_struct;
2714         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2715                 bnxt_hwrm_ring_free(bp, ring,
2716                                     BNXT_CHIP_P5(bp) ?
2717                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2718                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2719                                     cpr->cp_ring_struct->fw_ring_id);
2720                 if (BNXT_HAS_RING_GRPS(bp))
2721                         bp->grp_info[queue_index].ag_fw_ring_id =
2722                                                         INVALID_HW_RING_ID;
2723         }
2724
2725         if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2726                 bnxt_hwrm_stat_ctx_free(bp, cpr);
2727                 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2728         }
2729
2730         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2731                 bnxt_free_cp_ring(bp, cpr);
2732
2733         if (BNXT_HAS_RING_GRPS(bp))
2734                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2735 }
2736
2737 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2738 {
2739         int rc;
2740         struct hwrm_ring_reset_input req = {.req_type = 0 };
2741         struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2742
2743         HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2744
2745         req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2746         req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2747         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2748
2749         HWRM_CHECK_RESULT();
2750
2751         HWRM_UNLOCK();
2752
2753         return rc;
2754 }
2755
2756 static int
2757 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2758 {
2759         unsigned int i;
2760
2761         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2762                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2763                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2764                 struct bnxt_ring *ring = txr->tx_ring_struct;
2765                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2766
2767                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2768                         bnxt_hwrm_ring_free(bp, ring,
2769                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX,
2770                                         cpr->cp_ring_struct->fw_ring_id);
2771                         ring->fw_ring_id = INVALID_HW_RING_ID;
2772                         memset(txr->tx_desc_ring, 0,
2773                                         txr->tx_ring_struct->ring_size *
2774                                         sizeof(*txr->tx_desc_ring));
2775                         memset(txr->tx_buf_ring, 0,
2776                                         txr->tx_ring_struct->ring_size *
2777                                         sizeof(*txr->tx_buf_ring));
2778                         txr->tx_raw_prod = 0;
2779                         txr->tx_raw_cons = 0;
2780                 }
2781                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2782                         bnxt_free_cp_ring(bp, cpr);
2783                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2784                 }
2785         }
2786
2787         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2788                 bnxt_free_hwrm_rx_ring(bp, i);
2789
2790         return 0;
2791 }
2792
2793 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2794 {
2795         uint16_t i;
2796         uint32_t rc = 0;
2797
2798         if (!BNXT_HAS_RING_GRPS(bp))
2799                 return 0;
2800
2801         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2802                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2803                 if (rc)
2804                         return rc;
2805         }
2806         return rc;
2807 }
2808
2809 /*
2810  * HWRM utility functions
2811  */
2812
2813 void bnxt_free_hwrm_resources(struct bnxt *bp)
2814 {
2815         /* Release memzone */
2816         rte_free(bp->hwrm_cmd_resp_addr);
2817         rte_free(bp->hwrm_short_cmd_req_addr);
2818         bp->hwrm_cmd_resp_addr = NULL;
2819         bp->hwrm_short_cmd_req_addr = NULL;
2820         bp->hwrm_cmd_resp_dma_addr = 0;
2821         bp->hwrm_short_cmd_req_dma_addr = 0;
2822 }
2823
2824 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2825 {
2826         struct rte_pci_device *pdev = bp->pdev;
2827         char type[RTE_MEMZONE_NAMESIZE];
2828
2829         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2830                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2831         bp->max_resp_len = BNXT_PAGE_SIZE;
2832         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2833         if (bp->hwrm_cmd_resp_addr == NULL)
2834                 return -ENOMEM;
2835         bp->hwrm_cmd_resp_dma_addr =
2836                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2837         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2838                 PMD_DRV_LOG(ERR,
2839                         "unable to map response address to physical memory\n");
2840                 return -ENOMEM;
2841         }
2842         rte_spinlock_init(&bp->hwrm_lock);
2843
2844         return 0;
2845 }
2846
2847 int
2848 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2849 {
2850         int rc = 0;
2851
2852         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2853                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2854                 if (rc)
2855                         return rc;
2856         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2857                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2858                 if (rc)
2859                         return rc;
2860         }
2861
2862         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2863         return rc;
2864 }
2865
2866 static int
2867 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2868 {
2869         struct bnxt_filter_info *filter;
2870         int rc = 0;
2871
2872         STAILQ_FOREACH(filter, &vnic->filter, next) {
2873                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2874                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2875                 bnxt_free_filter(bp, filter);
2876         }
2877         return rc;
2878 }
2879
2880 static int
2881 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2882 {
2883         struct bnxt_filter_info *filter;
2884         struct rte_flow *flow;
2885         int rc = 0;
2886
2887         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2888                 flow = STAILQ_FIRST(&vnic->flow_list);
2889                 filter = flow->filter;
2890                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2891                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2892
2893                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2894                 rte_free(flow);
2895         }
2896         return rc;
2897 }
2898
2899 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2900 {
2901         struct bnxt_filter_info *filter;
2902         int rc = 0;
2903
2904         STAILQ_FOREACH(filter, &vnic->filter, next) {
2905                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2906                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2907                                                      filter);
2908                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2909                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2910                                                          filter);
2911                 else
2912                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2913                                                      filter);
2914                 if (rc)
2915                         break;
2916         }
2917         return rc;
2918 }
2919
2920 static void
2921 bnxt_free_tunnel_ports(struct bnxt *bp)
2922 {
2923         if (bp->vxlan_port_cnt)
2924                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2925                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2926
2927         if (bp->geneve_port_cnt)
2928                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2929                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2930 }
2931
2932 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2933 {
2934         int i;
2935
2936         if (bp->vnic_info == NULL)
2937                 return;
2938
2939         /*
2940          * Cleanup VNICs in reverse order, to make sure the L2 filter
2941          * from vnic0 is last to be cleaned up.
2942          */
2943         for (i = bp->max_vnics - 1; i >= 0; i--) {
2944                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2945
2946                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2947                         continue;
2948
2949                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2950
2951                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2952
2953                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2954
2955                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2956
2957                 bnxt_hwrm_vnic_free(bp, vnic);
2958
2959                 rte_free(vnic->fw_grp_ids);
2960         }
2961         /* Ring resources */
2962         bnxt_free_all_hwrm_rings(bp);
2963         bnxt_free_all_hwrm_ring_grps(bp);
2964         bnxt_free_all_hwrm_stat_ctxs(bp);
2965         bnxt_free_tunnel_ports(bp);
2966 }
2967
2968 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2969 {
2970         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2971
2972         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2973                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2974
2975         switch (conf_link_speed) {
2976         case ETH_LINK_SPEED_10M_HD:
2977         case ETH_LINK_SPEED_100M_HD:
2978                 /* FALLTHROUGH */
2979                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2980         }
2981         return hw_link_duplex;
2982 }
2983
2984 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2985 {
2986         return !conf_link;
2987 }
2988
2989 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2990                                           uint16_t pam4_link)
2991 {
2992         uint16_t eth_link_speed = 0;
2993
2994         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2995                 return ETH_LINK_SPEED_AUTONEG;
2996
2997         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2998         case ETH_LINK_SPEED_100M:
2999         case ETH_LINK_SPEED_100M_HD:
3000                 /* FALLTHROUGH */
3001                 eth_link_speed =
3002                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
3003                 break;
3004         case ETH_LINK_SPEED_1G:
3005                 eth_link_speed =
3006                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
3007                 break;
3008         case ETH_LINK_SPEED_2_5G:
3009                 eth_link_speed =
3010                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
3011                 break;
3012         case ETH_LINK_SPEED_10G:
3013                 eth_link_speed =
3014                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
3015                 break;
3016         case ETH_LINK_SPEED_20G:
3017                 eth_link_speed =
3018                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3019                 break;
3020         case ETH_LINK_SPEED_25G:
3021                 eth_link_speed =
3022                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3023                 break;
3024         case ETH_LINK_SPEED_40G:
3025                 eth_link_speed =
3026                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3027                 break;
3028         case ETH_LINK_SPEED_50G:
3029                 eth_link_speed = pam4_link ?
3030                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3031                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3032                 break;
3033         case ETH_LINK_SPEED_100G:
3034                 eth_link_speed = pam4_link ?
3035                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3036                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3037                 break;
3038         case ETH_LINK_SPEED_200G:
3039                 eth_link_speed =
3040                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3041                 break;
3042         default:
3043                 PMD_DRV_LOG(ERR,
3044                         "Unsupported link speed %d; default to AUTO\n",
3045                         conf_link_speed);
3046                 break;
3047         }
3048         return eth_link_speed;
3049 }
3050
3051 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3052                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3053                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3054                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3055                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3056
3057 static int bnxt_validate_link_speed(struct bnxt *bp)
3058 {
3059         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3060         uint16_t port_id = bp->eth_dev->data->port_id;
3061         uint32_t link_speed_capa;
3062         uint32_t one_speed;
3063
3064         if (link_speed == ETH_LINK_SPEED_AUTONEG)
3065                 return 0;
3066
3067         link_speed_capa = bnxt_get_speed_capabilities(bp);
3068
3069         if (link_speed & ETH_LINK_SPEED_FIXED) {
3070                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3071
3072                 if (one_speed & (one_speed - 1)) {
3073                         PMD_DRV_LOG(ERR,
3074                                 "Invalid advertised speeds (%u) for port %u\n",
3075                                 link_speed, port_id);
3076                         return -EINVAL;
3077                 }
3078                 if ((one_speed & link_speed_capa) != one_speed) {
3079                         PMD_DRV_LOG(ERR,
3080                                 "Unsupported advertised speed (%u) for port %u\n",
3081                                 link_speed, port_id);
3082                         return -EINVAL;
3083                 }
3084         } else {
3085                 if (!(link_speed & link_speed_capa)) {
3086                         PMD_DRV_LOG(ERR,
3087                                 "Unsupported advertised speeds (%u) for port %u\n",
3088                                 link_speed, port_id);
3089                         return -EINVAL;
3090                 }
3091         }
3092         return 0;
3093 }
3094
3095 static uint16_t
3096 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3097 {
3098         uint16_t ret = 0;
3099
3100         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3101                 if (bp->link_info->support_speeds)
3102                         return bp->link_info->support_speeds;
3103                 link_speed = BNXT_SUPPORTED_SPEEDS;
3104         }
3105
3106         if (link_speed & ETH_LINK_SPEED_100M)
3107                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3108         if (link_speed & ETH_LINK_SPEED_100M_HD)
3109                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3110         if (link_speed & ETH_LINK_SPEED_1G)
3111                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3112         if (link_speed & ETH_LINK_SPEED_2_5G)
3113                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3114         if (link_speed & ETH_LINK_SPEED_10G)
3115                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3116         if (link_speed & ETH_LINK_SPEED_20G)
3117                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3118         if (link_speed & ETH_LINK_SPEED_25G)
3119                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3120         if (link_speed & ETH_LINK_SPEED_40G)
3121                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3122         if (link_speed & ETH_LINK_SPEED_50G)
3123                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3124         if (link_speed & ETH_LINK_SPEED_100G)
3125                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3126         if (link_speed & ETH_LINK_SPEED_200G)
3127                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3128         return ret;
3129 }
3130
3131 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3132 {
3133         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3134
3135         switch (hw_link_speed) {
3136         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3137                 eth_link_speed = ETH_SPEED_NUM_100M;
3138                 break;
3139         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3140                 eth_link_speed = ETH_SPEED_NUM_1G;
3141                 break;
3142         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3143                 eth_link_speed = ETH_SPEED_NUM_2_5G;
3144                 break;
3145         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3146                 eth_link_speed = ETH_SPEED_NUM_10G;
3147                 break;
3148         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3149                 eth_link_speed = ETH_SPEED_NUM_20G;
3150                 break;
3151         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3152                 eth_link_speed = ETH_SPEED_NUM_25G;
3153                 break;
3154         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3155                 eth_link_speed = ETH_SPEED_NUM_40G;
3156                 break;
3157         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3158                 eth_link_speed = ETH_SPEED_NUM_50G;
3159                 break;
3160         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3161                 eth_link_speed = ETH_SPEED_NUM_100G;
3162                 break;
3163         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3164                 eth_link_speed = ETH_SPEED_NUM_200G;
3165                 break;
3166         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3167         default:
3168                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3169                         hw_link_speed);
3170                 break;
3171         }
3172         return eth_link_speed;
3173 }
3174
3175 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3176 {
3177         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3178
3179         switch (hw_link_duplex) {
3180         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3181         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3182                 /* FALLTHROUGH */
3183                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3184                 break;
3185         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3186                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3187                 break;
3188         default:
3189                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3190                         hw_link_duplex);
3191                 break;
3192         }
3193         return eth_link_duplex;
3194 }
3195
3196 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3197 {
3198         int rc = 0;
3199         struct bnxt_link_info *link_info = bp->link_info;
3200
3201         rc = bnxt_hwrm_port_phy_qcaps(bp);
3202         if (rc)
3203                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3204
3205         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3206         if (rc) {
3207                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3208                 goto exit;
3209         }
3210
3211         if (link_info->link_speed)
3212                 link->link_speed =
3213                         bnxt_parse_hw_link_speed(link_info->link_speed);
3214         else
3215                 link->link_speed = ETH_SPEED_NUM_NONE;
3216         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3217         link->link_status = link_info->link_up;
3218         link->link_autoneg = link_info->auto_mode ==
3219                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3220                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3221 exit:
3222         return rc;
3223 }
3224
3225 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3226 {
3227         int rc = 0;
3228         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3229         struct bnxt_link_info link_req;
3230         uint16_t speed, autoneg;
3231
3232         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3233                 return 0;
3234
3235         rc = bnxt_validate_link_speed(bp);
3236         if (rc)
3237                 goto error;
3238
3239         memset(&link_req, 0, sizeof(link_req));
3240         link_req.link_up = link_up;
3241         if (!link_up)
3242                 goto port_phy_cfg;
3243
3244         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3245         if (BNXT_CHIP_P5(bp) &&
3246             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3247                 /* 40G is not supported as part of media auto detect.
3248                  * The speed should be forced and autoneg disabled
3249                  * to configure 40G speed.
3250                  */
3251                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3252                 autoneg = 0;
3253         }
3254
3255         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3256         if (bp->link_info->auto_link_speed == 0 &&
3257             bp->link_info->link_signal_mode &&
3258             bp->link_info->auto_pam4_link_speeds == 0)
3259                 autoneg = 0;
3260
3261         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3262                                           bp->link_info->link_signal_mode);
3263         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3264         /* Autoneg can be done only when the FW allows. */
3265         if (autoneg == 1 && bp->link_info->support_auto_speeds) {
3266                 link_req.phy_flags |=
3267                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3268                 link_req.auto_link_speed_mask =
3269                         bnxt_parse_eth_link_speed_mask(bp,
3270                                                        dev_conf->link_speeds);
3271         } else {
3272                 if (bp->link_info->phy_type ==
3273                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3274                     bp->link_info->phy_type ==
3275                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3276                     bp->link_info->media_type ==
3277                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3278                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3279                         return -EINVAL;
3280                 }
3281
3282                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3283                 /* If user wants a particular speed try that first. */
3284                 if (speed)
3285                         link_req.link_speed = speed;
3286                 else if (bp->link_info->force_pam4_link_speed)
3287                         link_req.link_speed =
3288                                 bp->link_info->force_pam4_link_speed;
3289                 else if (bp->link_info->auto_pam4_link_speeds)
3290                         link_req.link_speed =
3291                                 bp->link_info->auto_pam4_link_speeds;
3292                 else if (bp->link_info->support_pam4_speeds)
3293                         link_req.link_speed =
3294                                 bp->link_info->support_pam4_speeds;
3295                 else if (bp->link_info->force_link_speed)
3296                         link_req.link_speed = bp->link_info->force_link_speed;
3297                 else
3298                         link_req.link_speed = bp->link_info->auto_link_speed;
3299                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3300                  * zero. Use the auto_link_speed.
3301                  */
3302                 if (bp->link_info->auto_link_speed != 0 &&
3303                     bp->link_info->auto_pam4_link_speeds == 0)
3304                         link_req.link_speed = bp->link_info->auto_link_speed;
3305         }
3306         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3307         link_req.auto_pause = bp->link_info->auto_pause;
3308         link_req.force_pause = bp->link_info->force_pause;
3309
3310 port_phy_cfg:
3311         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3312         if (rc) {
3313                 PMD_DRV_LOG(ERR,
3314                         "Set link config failed with rc %d\n", rc);
3315         }
3316
3317 error:
3318         return rc;
3319 }
3320
3321 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3322 {
3323         struct hwrm_func_qcfg_input req = {0};
3324         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3325         uint16_t flags;
3326         int rc = 0;
3327         bp->func_svif = BNXT_SVIF_INVALID;
3328         uint16_t svif_info;
3329
3330         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3331         req.fid = rte_cpu_to_le_16(0xffff);
3332
3333         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3334
3335         HWRM_CHECK_RESULT();
3336
3337         bp->vlan = rte_le_to_cpu_16(resp->vlan) & ETH_VLAN_ID_MAX;
3338
3339         svif_info = rte_le_to_cpu_16(resp->svif_info);
3340         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3341                 bp->func_svif = svif_info &
3342                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3343
3344         flags = rte_le_to_cpu_16(resp->flags);
3345         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3346                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3347
3348         if (BNXT_VF(bp) &&
3349             !BNXT_VF_IS_TRUSTED(bp) &&
3350             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3351                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3352                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3353         } else if (BNXT_VF(bp) &&
3354                    BNXT_VF_IS_TRUSTED(bp) &&
3355                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3356                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3357                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3358         }
3359
3360         if (mtu)
3361                 *mtu = rte_le_to_cpu_16(resp->mtu);
3362
3363         switch (resp->port_partition_type) {
3364         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3365         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3366         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3367                 /* FALLTHROUGH */
3368                 bp->flags |= BNXT_FLAG_NPAR_PF;
3369                 break;
3370         default:
3371                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3372                 break;
3373         }
3374
3375         bp->legacy_db_size =
3376                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3377
3378         HWRM_UNLOCK();
3379
3380         return rc;
3381 }
3382
3383 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3384 {
3385         struct hwrm_func_qcfg_input req = {0};
3386         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3387         int rc;
3388
3389         if (!BNXT_VF_IS_TRUSTED(bp))
3390                 return 0;
3391
3392         if (!bp->parent)
3393                 return -EINVAL;
3394
3395         bp->parent->fid = BNXT_PF_FID_INVALID;
3396
3397         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3398
3399         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3400
3401         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3402
3403         HWRM_CHECK_RESULT_SILENT();
3404
3405         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3406         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3407         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3408         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3409
3410         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3411         if (bp->parent->vnic == 0) {
3412                 PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
3413                 /* Use hard-coded values appropriate for current Wh+ fw. */
3414                 if (bp->parent->fid == 2)
3415                         bp->parent->vnic = 0x100;
3416                 else
3417                         bp->parent->vnic = 1;
3418         }
3419
3420         HWRM_UNLOCK();
3421
3422         return 0;
3423 }
3424
3425 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3426                                  uint16_t *vnic_id, uint16_t *svif)
3427 {
3428         struct hwrm_func_qcfg_input req = {0};
3429         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3430         uint16_t svif_info;
3431         int rc = 0;
3432
3433         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3434         req.fid = rte_cpu_to_le_16(fid);
3435
3436         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3437
3438         HWRM_CHECK_RESULT();
3439
3440         if (vnic_id)
3441                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3442
3443         svif_info = rte_le_to_cpu_16(resp->svif_info);
3444         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3445                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3446
3447         HWRM_UNLOCK();
3448
3449         return rc;
3450 }
3451
3452 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3453 {
3454         struct hwrm_port_mac_qcfg_input req = {0};
3455         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3456         uint16_t port_svif_info;
3457         int rc;
3458
3459         bp->port_svif = BNXT_SVIF_INVALID;
3460
3461         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3462                 return 0;
3463
3464         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3465
3466         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3467
3468         HWRM_CHECK_RESULT_SILENT();
3469
3470         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3471         if (port_svif_info &
3472             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3473                 bp->port_svif = port_svif_info &
3474                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3475
3476         HWRM_UNLOCK();
3477
3478         return 0;
3479 }
3480
3481 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3482                                  struct bnxt_pf_resource_info *pf_resc)
3483 {
3484         struct hwrm_func_cfg_input req = {0};
3485         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3486         uint32_t enables;
3487         int rc;
3488
3489         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3490                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3491                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3492                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3493                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3494                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3495                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3496                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3497                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3498
3499         if (BNXT_HAS_RING_GRPS(bp)) {
3500                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3501                 req.num_hw_ring_grps =
3502                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3503         } else if (BNXT_HAS_NQ(bp)) {
3504                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3505                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3506         }
3507
3508         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3509         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3510         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3511         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3512         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3513         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3514         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3515         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3516         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3517         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3518         req.fid = rte_cpu_to_le_16(0xffff);
3519         req.enables = rte_cpu_to_le_32(enables);
3520
3521         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3522
3523         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3524
3525         HWRM_CHECK_RESULT();
3526         HWRM_UNLOCK();
3527
3528         return rc;
3529 }
3530
3531 /* min values are the guaranteed resources and max values are subject
3532  * to availability. The strategy for now is to keep both min & max
3533  * values the same.
3534  */
3535 static void
3536 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3537                               struct hwrm_func_vf_resource_cfg_input *req,
3538                               int num_vfs)
3539 {
3540         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3541                                                (num_vfs + 1));
3542         req->min_rsscos_ctx = req->max_rsscos_ctx;
3543         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3544         req->min_stat_ctx = req->max_stat_ctx;
3545         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3546                                                (num_vfs + 1));
3547         req->min_cmpl_rings = req->max_cmpl_rings;
3548         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3549         req->min_tx_rings = req->max_tx_rings;
3550         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3551         req->min_rx_rings = req->max_rx_rings;
3552         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3553         req->min_l2_ctxs = req->max_l2_ctxs;
3554         /* TODO: For now, do not support VMDq/RFS on VFs. */
3555         req->max_vnics = rte_cpu_to_le_16(1);
3556         req->min_vnics = req->max_vnics;
3557         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3558                                                  (num_vfs + 1));
3559         req->min_hw_ring_grps = req->max_hw_ring_grps;
3560         req->flags =
3561          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3562 }
3563
3564 static void
3565 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3566                               struct hwrm_func_cfg_input *req,
3567                               int num_vfs)
3568 {
3569         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3570                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3571                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3572                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3573                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3574                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3575                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3576                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3577                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3578                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3579
3580         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3581                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3582                                     BNXT_NUM_VLANS);
3583         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3584         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3585                                                 (num_vfs + 1));
3586         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3587         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3588                                                (num_vfs + 1));
3589         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3590         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3591         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3592         /* TODO: For now, do not support VMDq/RFS on VFs. */
3593         req->num_vnics = rte_cpu_to_le_16(1);
3594         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3595                                                  (num_vfs + 1));
3596 }
3597
3598 /* Update the port wide resource values based on how many resources
3599  * got allocated to the VF.
3600  */
3601 static int bnxt_update_max_resources(struct bnxt *bp,
3602                                      int vf)
3603 {
3604         struct hwrm_func_qcfg_input req = {0};
3605         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3606         int rc;
3607
3608         /* Get the actual allocated values now */
3609         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3610         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3612         HWRM_CHECK_RESULT();
3613
3614         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3615         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3616         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3617         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3618         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3619         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3620         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3621
3622         HWRM_UNLOCK();
3623
3624         return 0;
3625 }
3626
3627 /* Update the PF resource values based on how many resources
3628  * got allocated to it.
3629  */
3630 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3631 {
3632         struct hwrm_func_qcfg_input req = {0};
3633         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3634         int rc;
3635
3636         /* Get the actual allocated values now */
3637         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3638         req.fid = rte_cpu_to_le_16(0xffff);
3639         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3640         HWRM_CHECK_RESULT();
3641
3642         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3643         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3644         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3645         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3646         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3647         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3648         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3649         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3650
3651         HWRM_UNLOCK();
3652
3653         return 0;
3654 }
3655
3656 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3657 {
3658         struct hwrm_func_qcfg_input req = {0};
3659         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3660         int rc;
3661
3662         /* Check for zero MAC address */
3663         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3664         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3665         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3666         HWRM_CHECK_RESULT();
3667         rc = rte_le_to_cpu_16(resp->vlan);
3668
3669         HWRM_UNLOCK();
3670
3671         return rc;
3672 }
3673
3674 static int bnxt_query_pf_resources(struct bnxt *bp,
3675                                    struct bnxt_pf_resource_info *pf_resc)
3676 {
3677         struct hwrm_func_qcfg_input req = {0};
3678         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3679         int rc;
3680
3681         /* And copy the allocated numbers into the pf struct */
3682         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3683         req.fid = rte_cpu_to_le_16(0xffff);
3684         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3685         HWRM_CHECK_RESULT();
3686
3687         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3688         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3689         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3690         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3691         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3692         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3693         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3694         bp->pf->evb_mode = resp->evb_mode;
3695
3696         HWRM_UNLOCK();
3697
3698         return rc;
3699 }
3700
3701 static void
3702 bnxt_calculate_pf_resources(struct bnxt *bp,
3703                             struct bnxt_pf_resource_info *pf_resc,
3704                             int num_vfs)
3705 {
3706         if (!num_vfs) {
3707                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3708                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3709                 pf_resc->num_cp_rings = bp->max_cp_rings;
3710                 pf_resc->num_tx_rings = bp->max_tx_rings;
3711                 pf_resc->num_rx_rings = bp->max_rx_rings;
3712                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3713                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3714
3715                 return;
3716         }
3717
3718         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3719                                    bp->max_rsscos_ctx % (num_vfs + 1);
3720         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3721                                  bp->max_stat_ctx % (num_vfs + 1);
3722         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3723                                 bp->max_cp_rings % (num_vfs + 1);
3724         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3725                                 bp->max_tx_rings % (num_vfs + 1);
3726         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3727                                 bp->max_rx_rings % (num_vfs + 1);
3728         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3729                                bp->max_l2_ctx % (num_vfs + 1);
3730         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3731                                     bp->max_ring_grps % (num_vfs + 1);
3732 }
3733
3734 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3735 {
3736         struct bnxt_pf_resource_info pf_resc = { 0 };
3737         int rc;
3738
3739         if (!BNXT_PF(bp)) {
3740                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3741                 return -EINVAL;
3742         }
3743
3744         rc = bnxt_hwrm_func_qcaps(bp);
3745         if (rc)
3746                 return rc;
3747
3748         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3749
3750         bp->pf->func_cfg_flags &=
3751                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3752                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3753         bp->pf->func_cfg_flags |=
3754                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3755
3756         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3757         if (rc)
3758                 return rc;
3759
3760         rc = bnxt_update_max_resources_pf_only(bp);
3761
3762         return rc;
3763 }
3764
3765 static int
3766 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3767 {
3768         size_t req_buf_sz, sz;
3769         int i, rc;
3770
3771         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3772         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3773                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3774         if (bp->pf->vf_req_buf == NULL) {
3775                 return -ENOMEM;
3776         }
3777
3778         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3779                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3780
3781         for (i = 0; i < num_vfs; i++)
3782                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3783                                              (i * HWRM_MAX_REQ_LEN);
3784
3785         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3786         if (rc)
3787                 rte_free(bp->pf->vf_req_buf);
3788
3789         return rc;
3790 }
3791
3792 static int
3793 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3794 {
3795         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3796         struct hwrm_func_vf_resource_cfg_input req = {0};
3797         int i, rc = 0;
3798
3799         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3800         bp->pf->active_vfs = 0;
3801         for (i = 0; i < num_vfs; i++) {
3802                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3803                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3804                 rc = bnxt_hwrm_send_message(bp,
3805                                             &req,
3806                                             sizeof(req),
3807                                             BNXT_USE_CHIMP_MB);
3808                 if (rc || resp->error_code) {
3809                         PMD_DRV_LOG(ERR,
3810                                 "Failed to initialize VF %d\n", i);
3811                         PMD_DRV_LOG(ERR,
3812                                 "Not all VFs available. (%d, %d)\n",
3813                                 rc, resp->error_code);
3814                         HWRM_UNLOCK();
3815
3816                         /* If the first VF configuration itself fails,
3817                          * unregister the vf_fwd_request buffer.
3818                          */
3819                         if (i == 0)
3820                                 bnxt_hwrm_func_buf_unrgtr(bp);
3821                         break;
3822                 }
3823                 HWRM_UNLOCK();
3824
3825                 /* Update the max resource values based on the resource values
3826                  * allocated to the VF.
3827                  */
3828                 bnxt_update_max_resources(bp, i);
3829                 bp->pf->active_vfs++;
3830                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3831         }
3832
3833         return 0;
3834 }
3835
3836 static int
3837 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3838 {
3839         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3840         struct hwrm_func_cfg_input req = {0};
3841         int i, rc;
3842
3843         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3844
3845         bp->pf->active_vfs = 0;
3846         for (i = 0; i < num_vfs; i++) {
3847                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3848                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3849                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3850                 rc = bnxt_hwrm_send_message(bp,
3851                                             &req,
3852                                             sizeof(req),
3853                                             BNXT_USE_CHIMP_MB);
3854
3855                 /* Clear enable flag for next pass */
3856                 req.enables &= ~rte_cpu_to_le_32(
3857                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3858
3859                 if (rc || resp->error_code) {
3860                         PMD_DRV_LOG(ERR,
3861                                 "Failed to initialize VF %d\n", i);
3862                         PMD_DRV_LOG(ERR,
3863                                 "Not all VFs available. (%d, %d)\n",
3864                                 rc, resp->error_code);
3865                         HWRM_UNLOCK();
3866
3867                         /* If the first VF configuration itself fails,
3868                          * unregister the vf_fwd_request buffer.
3869                          */
3870                         if (i == 0)
3871                                 bnxt_hwrm_func_buf_unrgtr(bp);
3872                         break;
3873                 }
3874
3875                 HWRM_UNLOCK();
3876
3877                 /* Update the max resource values based on the resource values
3878                  * allocated to the VF.
3879                  */
3880                 bnxt_update_max_resources(bp, i);
3881                 bp->pf->active_vfs++;
3882                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3883         }
3884
3885         return 0;
3886 }
3887
3888 static void
3889 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3890 {
3891         if (bp->flags & BNXT_FLAG_NEW_RM)
3892                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3893         else
3894                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3895 }
3896
3897 static void
3898 bnxt_update_pf_resources(struct bnxt *bp,
3899                          struct bnxt_pf_resource_info *pf_resc)
3900 {
3901         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3902         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3903         bp->max_cp_rings = pf_resc->num_cp_rings;
3904         bp->max_tx_rings = pf_resc->num_tx_rings;
3905         bp->max_rx_rings = pf_resc->num_rx_rings;
3906         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3907 }
3908
3909 static int32_t
3910 bnxt_configure_pf_resources(struct bnxt *bp,
3911                             struct bnxt_pf_resource_info *pf_resc)
3912 {
3913         /*
3914          * We're using STD_TX_RING_MODE here which will limit the TX
3915          * rings. This will allow QoS to function properly. Not setting this
3916          * will cause PF rings to break bandwidth settings.
3917          */
3918         bp->pf->func_cfg_flags &=
3919                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3920                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3921         bp->pf->func_cfg_flags |=
3922                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3923         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3924 }
3925
3926 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3927 {
3928         struct bnxt_pf_resource_info pf_resc = { 0 };
3929         int rc;
3930
3931         if (!BNXT_PF(bp)) {
3932                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3933                 return -EINVAL;
3934         }
3935
3936         rc = bnxt_hwrm_func_qcaps(bp);
3937         if (rc)
3938                 return rc;
3939
3940         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3941
3942         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3943         if (rc)
3944                 return rc;
3945
3946         rc = bnxt_query_pf_resources(bp, &pf_resc);
3947         if (rc)
3948                 return rc;
3949
3950         /*
3951          * Now, create and register a buffer to hold forwarded VF requests
3952          */
3953         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3954         if (rc)
3955                 return rc;
3956
3957         bnxt_configure_vf_resources(bp, num_vfs);
3958
3959         bnxt_update_pf_resources(bp, &pf_resc);
3960
3961         return 0;
3962 }
3963
3964 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3965 {
3966         struct hwrm_func_cfg_input req = {0};
3967         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3968         int rc;
3969
3970         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3971
3972         req.fid = rte_cpu_to_le_16(0xffff);
3973         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3974         req.evb_mode = bp->pf->evb_mode;
3975
3976         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3977         HWRM_CHECK_RESULT();
3978         HWRM_UNLOCK();
3979
3980         return rc;
3981 }
3982
3983 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3984                                 uint8_t tunnel_type)
3985 {
3986         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3987         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3988         int rc = 0;
3989
3990         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3991         req.tunnel_type = tunnel_type;
3992         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3993         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3994         HWRM_CHECK_RESULT();
3995
3996         switch (tunnel_type) {
3997         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3998                 bp->vxlan_fw_dst_port_id =
3999                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
4000                 bp->vxlan_port = port;
4001                 break;
4002         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
4003                 bp->geneve_fw_dst_port_id =
4004                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
4005                 bp->geneve_port = port;
4006                 break;
4007         default:
4008                 break;
4009         }
4010
4011         HWRM_UNLOCK();
4012
4013         return rc;
4014 }
4015
4016 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4017                                 uint8_t tunnel_type)
4018 {
4019         struct hwrm_tunnel_dst_port_free_input req = {0};
4020         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4021         int rc = 0;
4022
4023         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4024
4025         req.tunnel_type = tunnel_type;
4026         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4027         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4028
4029         HWRM_CHECK_RESULT();
4030         HWRM_UNLOCK();
4031
4032         if (tunnel_type ==
4033             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4034                 bp->vxlan_port = 0;
4035                 bp->vxlan_port_cnt = 0;
4036         }
4037
4038         if (tunnel_type ==
4039             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4040                 bp->geneve_port = 0;
4041                 bp->geneve_port_cnt = 0;
4042         }
4043
4044         return rc;
4045 }
4046
4047 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4048                                         uint32_t flags)
4049 {
4050         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4051         struct hwrm_func_cfg_input req = {0};
4052         int rc;
4053
4054         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4055
4056         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4057         req.flags = rte_cpu_to_le_32(flags);
4058         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4059
4060         HWRM_CHECK_RESULT();
4061         HWRM_UNLOCK();
4062
4063         return rc;
4064 }
4065
4066 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4067 {
4068         uint32_t *flag = flagp;
4069
4070         vnic->flags = *flag;
4071 }
4072
4073 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4074 {
4075         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4076 }
4077
4078 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4079 {
4080         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4081         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4082         int rc;
4083
4084         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4085
4086         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4087         req.req_buf_page_size =
4088                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4089         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4090         req.req_buf_page_addr0 =
4091                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4092         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4093                 PMD_DRV_LOG(ERR,
4094                         "unable to map buffer address to physical memory\n");
4095                 HWRM_UNLOCK();
4096                 return -ENOMEM;
4097         }
4098
4099         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4100
4101         HWRM_CHECK_RESULT();
4102         HWRM_UNLOCK();
4103
4104         return rc;
4105 }
4106
4107 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4108 {
4109         int rc = 0;
4110         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4111         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4112
4113         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4114                 return 0;
4115
4116         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4117
4118         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4119
4120         HWRM_CHECK_RESULT();
4121         HWRM_UNLOCK();
4122
4123         return rc;
4124 }
4125
4126 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4127 {
4128         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4129         struct hwrm_func_cfg_input req = {0};
4130         int rc;
4131
4132         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4133
4134         req.fid = rte_cpu_to_le_16(0xffff);
4135         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4136         req.enables = rte_cpu_to_le_32(
4137                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4138         req.async_event_cr = rte_cpu_to_le_16(
4139                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4140         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4141
4142         HWRM_CHECK_RESULT();
4143         HWRM_UNLOCK();
4144
4145         return rc;
4146 }
4147
4148 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4149 {
4150         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4151         struct hwrm_func_vf_cfg_input req = {0};
4152         int rc;
4153
4154         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4155
4156         req.enables = rte_cpu_to_le_32(
4157                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4158         req.async_event_cr = rte_cpu_to_le_16(
4159                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4160         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4161
4162         HWRM_CHECK_RESULT();
4163         HWRM_UNLOCK();
4164
4165         return rc;
4166 }
4167
4168 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4169 {
4170         struct hwrm_func_cfg_input req = {0};
4171         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4172         uint16_t dflt_vlan, fid;
4173         uint32_t func_cfg_flags;
4174         int rc = 0;
4175
4176         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4177
4178         if (is_vf) {
4179                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4180                 fid = bp->pf->vf_info[vf].fid;
4181                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4182         } else {
4183                 fid = rte_cpu_to_le_16(0xffff);
4184                 func_cfg_flags = bp->pf->func_cfg_flags;
4185                 dflt_vlan = bp->vlan;
4186         }
4187
4188         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4189         req.fid = rte_cpu_to_le_16(fid);
4190         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4191         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4192
4193         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4194
4195         HWRM_CHECK_RESULT();
4196         HWRM_UNLOCK();
4197
4198         return rc;
4199 }
4200
4201 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4202                         uint16_t max_bw, uint16_t enables)
4203 {
4204         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4205         struct hwrm_func_cfg_input req = {0};
4206         int rc;
4207
4208         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4209
4210         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4211         req.enables |= rte_cpu_to_le_32(enables);
4212         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4213         req.max_bw = rte_cpu_to_le_32(max_bw);
4214         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4215
4216         HWRM_CHECK_RESULT();
4217         HWRM_UNLOCK();
4218
4219         return rc;
4220 }
4221
4222 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4223 {
4224         struct hwrm_func_cfg_input req = {0};
4225         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4226         int rc = 0;
4227
4228         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4229
4230         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4231         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4232         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4233         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4234
4235         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4236
4237         HWRM_CHECK_RESULT();
4238         HWRM_UNLOCK();
4239
4240         return rc;
4241 }
4242
4243 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4244 {
4245         int rc;
4246
4247         if (BNXT_PF(bp))
4248                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4249         else
4250                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4251
4252         return rc;
4253 }
4254
4255 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4256                               void *encaped, size_t ec_size)
4257 {
4258         int rc = 0;
4259         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4260         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4261
4262         if (ec_size > sizeof(req.encap_request))
4263                 return -1;
4264
4265         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4266
4267         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4268         memcpy(req.encap_request, encaped, ec_size);
4269
4270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4271
4272         HWRM_CHECK_RESULT();
4273         HWRM_UNLOCK();
4274
4275         return rc;
4276 }
4277
4278 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4279                                        struct rte_ether_addr *mac)
4280 {
4281         struct hwrm_func_qcfg_input req = {0};
4282         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4283         int rc;
4284
4285         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4286
4287         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4288         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4289
4290         HWRM_CHECK_RESULT();
4291
4292         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4293
4294         HWRM_UNLOCK();
4295
4296         return rc;
4297 }
4298
4299 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4300                             void *encaped, size_t ec_size)
4301 {
4302         int rc = 0;
4303         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4304         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4305
4306         if (ec_size > sizeof(req.encap_request))
4307                 return -1;
4308
4309         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4310
4311         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4312         memcpy(req.encap_request, encaped, ec_size);
4313
4314         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4315
4316         HWRM_CHECK_RESULT();
4317         HWRM_UNLOCK();
4318
4319         return rc;
4320 }
4321
4322 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4323 {
4324         /* One of the HW stat values that make up this counter was zero as
4325          * returned by HW in this iteration, so use the previous
4326          * iteration's counter value
4327          */
4328         if (*prev_cntr && *cntr == 0)
4329                 *cntr = *prev_cntr;
4330         else
4331                 *prev_cntr = *cntr;
4332 }
4333
4334 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4335                          struct bnxt_ring_stats *ring_stats, bool rx)
4336 {
4337         int rc = 0;
4338         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4339         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4340
4341         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4342
4343         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4344
4345         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4346
4347         HWRM_CHECK_RESULT();
4348
4349         if (rx) {
4350                 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4351
4352                 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4353                 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4354                                       &prev_stats->rx_ucast_pkts);
4355
4356                 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4357                 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4358                                       &prev_stats->rx_mcast_pkts);
4359
4360                 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4361                 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4362                                       &prev_stats->rx_bcast_pkts);
4363
4364                 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4365                 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4366                                       &prev_stats->rx_ucast_bytes);
4367
4368                 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4369                 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4370                                       &prev_stats->rx_mcast_bytes);
4371
4372                 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4373                 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4374                                       &prev_stats->rx_bcast_bytes);
4375
4376                 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4377                 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4378                                       &prev_stats->rx_discard_pkts);
4379
4380                 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4381                 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4382                                       &prev_stats->rx_error_pkts);
4383
4384                 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4385                 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4386                                       &prev_stats->rx_agg_pkts);
4387
4388                 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4389                 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4390                                       &prev_stats->rx_agg_bytes);
4391
4392                 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4393                 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4394                                       &prev_stats->rx_agg_events);
4395
4396                 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4397                 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4398                                       &prev_stats->rx_agg_aborts);
4399         } else {
4400                 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4401
4402                 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4403                 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4404                                       &prev_stats->tx_ucast_pkts);
4405
4406                 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4407                 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4408                                       &prev_stats->tx_mcast_pkts);
4409
4410                 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4411                 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4412                                       &prev_stats->tx_bcast_pkts);
4413
4414                 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4415                 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4416                                       &prev_stats->tx_ucast_bytes);
4417
4418                 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4419                 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4420                                       &prev_stats->tx_mcast_bytes);
4421
4422                 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4423                 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4424                                       &prev_stats->tx_bcast_bytes);
4425
4426                 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4427                 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4428                                       &prev_stats->tx_discard_pkts);
4429         }
4430
4431         HWRM_UNLOCK();
4432
4433         return rc;
4434 }
4435
4436 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4437 {
4438         struct hwrm_port_qstats_input req = {0};
4439         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4440         struct bnxt_pf_info *pf = bp->pf;
4441         int rc;
4442
4443         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4444
4445         req.port_id = rte_cpu_to_le_16(pf->port_id);
4446         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4447         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4448         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4449
4450         HWRM_CHECK_RESULT();
4451         HWRM_UNLOCK();
4452
4453         return rc;
4454 }
4455
4456 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4457 {
4458         struct hwrm_port_clr_stats_input req = {0};
4459         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4460         struct bnxt_pf_info *pf = bp->pf;
4461         int rc;
4462
4463         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4464         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4465             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4466                 return 0;
4467
4468         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4469
4470         req.port_id = rte_cpu_to_le_16(pf->port_id);
4471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4472
4473         HWRM_CHECK_RESULT();
4474         HWRM_UNLOCK();
4475
4476         return rc;
4477 }
4478
4479 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4480 {
4481         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4482         struct hwrm_port_led_qcaps_input req = {0};
4483         int rc;
4484
4485         if (BNXT_VF(bp))
4486                 return 0;
4487
4488         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4489         req.port_id = bp->pf->port_id;
4490         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4491
4492         HWRM_CHECK_RESULT_SILENT();
4493
4494         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4495                 unsigned int i;
4496
4497                 bp->leds->num_leds = resp->num_leds;
4498                 memcpy(bp->leds, &resp->led0_id,
4499                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4500                 for (i = 0; i < bp->leds->num_leds; i++) {
4501                         struct bnxt_led_info *led = &bp->leds[i];
4502
4503                         uint16_t caps = led->led_state_caps;
4504
4505                         if (!led->led_group_id ||
4506                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4507                                 bp->leds->num_leds = 0;
4508                                 break;
4509                         }
4510                 }
4511         }
4512
4513         HWRM_UNLOCK();
4514
4515         return rc;
4516 }
4517
4518 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4519 {
4520         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4521         struct hwrm_port_led_cfg_input req = {0};
4522         struct bnxt_led_cfg *led_cfg;
4523         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4524         uint16_t duration = 0;
4525         int rc, i;
4526
4527         if (!bp->leds->num_leds || BNXT_VF(bp))
4528                 return -EOPNOTSUPP;
4529
4530         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4531
4532         if (led_on) {
4533                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4534                 duration = rte_cpu_to_le_16(500);
4535         }
4536         req.port_id = bp->pf->port_id;
4537         req.num_leds = bp->leds->num_leds;
4538         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4539         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4540                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4541                 led_cfg->led_id = bp->leds[i].led_id;
4542                 led_cfg->led_state = led_state;
4543                 led_cfg->led_blink_on = duration;
4544                 led_cfg->led_blink_off = duration;
4545                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4546         }
4547
4548         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4549
4550         HWRM_CHECK_RESULT();
4551         HWRM_UNLOCK();
4552
4553         return rc;
4554 }
4555
4556 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4557                                uint32_t *length)
4558 {
4559         int rc;
4560         struct hwrm_nvm_get_dir_info_input req = {0};
4561         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4562
4563         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4564
4565         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4566
4567         HWRM_CHECK_RESULT();
4568
4569         *entries = rte_le_to_cpu_32(resp->entries);
4570         *length = rte_le_to_cpu_32(resp->entry_length);
4571
4572         HWRM_UNLOCK();
4573         return rc;
4574 }
4575
4576 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4577 {
4578         int rc;
4579         uint32_t dir_entries;
4580         uint32_t entry_length;
4581         uint8_t *buf;
4582         size_t buflen;
4583         rte_iova_t dma_handle;
4584         struct hwrm_nvm_get_dir_entries_input req = {0};
4585         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4586
4587         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4588         if (rc != 0)
4589                 return rc;
4590
4591         *data++ = dir_entries;
4592         *data++ = entry_length;
4593         len -= 2;
4594         memset(data, 0xff, len);
4595
4596         buflen = dir_entries * entry_length;
4597         buf = rte_malloc("nvm_dir", buflen, 0);
4598         if (buf == NULL)
4599                 return -ENOMEM;
4600         dma_handle = rte_malloc_virt2iova(buf);
4601         if (dma_handle == RTE_BAD_IOVA) {
4602                 rte_free(buf);
4603                 PMD_DRV_LOG(ERR,
4604                         "unable to map response address to physical memory\n");
4605                 return -ENOMEM;
4606         }
4607         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4608         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4609         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4610
4611         if (rc == 0)
4612                 memcpy(data, buf, len > buflen ? buflen : len);
4613
4614         rte_free(buf);
4615         HWRM_CHECK_RESULT();
4616         HWRM_UNLOCK();
4617
4618         return rc;
4619 }
4620
4621 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4622                              uint32_t offset, uint32_t length,
4623                              uint8_t *data)
4624 {
4625         int rc;
4626         uint8_t *buf;
4627         rte_iova_t dma_handle;
4628         struct hwrm_nvm_read_input req = {0};
4629         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4630
4631         buf = rte_malloc("nvm_item", length, 0);
4632         if (!buf)
4633                 return -ENOMEM;
4634
4635         dma_handle = rte_malloc_virt2iova(buf);
4636         if (dma_handle == RTE_BAD_IOVA) {
4637                 rte_free(buf);
4638                 PMD_DRV_LOG(ERR,
4639                         "unable to map response address to physical memory\n");
4640                 return -ENOMEM;
4641         }
4642         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4643         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4644         req.dir_idx = rte_cpu_to_le_16(index);
4645         req.offset = rte_cpu_to_le_32(offset);
4646         req.len = rte_cpu_to_le_32(length);
4647         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4648         if (rc == 0)
4649                 memcpy(data, buf, length);
4650
4651         rte_free(buf);
4652         HWRM_CHECK_RESULT();
4653         HWRM_UNLOCK();
4654
4655         return rc;
4656 }
4657
4658 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4659 {
4660         int rc;
4661         struct hwrm_nvm_erase_dir_entry_input req = {0};
4662         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4663
4664         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4665         req.dir_idx = rte_cpu_to_le_16(index);
4666         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4667         HWRM_CHECK_RESULT();
4668         HWRM_UNLOCK();
4669
4670         return rc;
4671 }
4672
4673 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4674                           uint16_t dir_ordinal, uint16_t dir_ext,
4675                           uint16_t dir_attr, const uint8_t *data,
4676                           size_t data_len)
4677 {
4678         int rc;
4679         struct hwrm_nvm_write_input req = {0};
4680         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4681         rte_iova_t dma_handle;
4682         uint8_t *buf;
4683
4684         buf = rte_malloc("nvm_write", data_len, 0);
4685         if (!buf)
4686                 return -ENOMEM;
4687
4688         dma_handle = rte_malloc_virt2iova(buf);
4689         if (dma_handle == RTE_BAD_IOVA) {
4690                 rte_free(buf);
4691                 PMD_DRV_LOG(ERR,
4692                         "unable to map response address to physical memory\n");
4693                 return -ENOMEM;
4694         }
4695         memcpy(buf, data, data_len);
4696
4697         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4698
4699         req.dir_type = rte_cpu_to_le_16(dir_type);
4700         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4701         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4702         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4703         req.dir_data_length = rte_cpu_to_le_32(data_len);
4704         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4705
4706         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4707
4708         rte_free(buf);
4709         HWRM_CHECK_RESULT();
4710         HWRM_UNLOCK();
4711
4712         return rc;
4713 }
4714
4715 static void
4716 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4717 {
4718         uint32_t *count = cbdata;
4719
4720         *count = *count + 1;
4721 }
4722
4723 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4724                                      struct bnxt_vnic_info *vnic __rte_unused)
4725 {
4726         return 0;
4727 }
4728
4729 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4730 {
4731         uint32_t count = 0;
4732
4733         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4734             &count, bnxt_vnic_count_hwrm_stub);
4735
4736         return count;
4737 }
4738
4739 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4740                                         uint16_t *vnic_ids)
4741 {
4742         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4743         struct hwrm_func_vf_vnic_ids_query_output *resp =
4744                                                 bp->hwrm_cmd_resp_addr;
4745         int rc;
4746
4747         /* First query all VNIC ids */
4748         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4749
4750         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4751         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4752         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4753
4754         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4755                 HWRM_UNLOCK();
4756                 PMD_DRV_LOG(ERR,
4757                 "unable to map VNIC ID table address to physical memory\n");
4758                 return -ENOMEM;
4759         }
4760         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4761         HWRM_CHECK_RESULT();
4762         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4763
4764         HWRM_UNLOCK();
4765
4766         return rc;
4767 }
4768
4769 /*
4770  * This function queries the VNIC IDs  for a specified VF. It then calls
4771  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4772  * Then it calls the hwrm_cb function to program this new vnic configuration.
4773  */
4774 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4775         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4776         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4777 {
4778         struct bnxt_vnic_info vnic;
4779         int rc = 0;
4780         int i, num_vnic_ids;
4781         uint16_t *vnic_ids;
4782         size_t vnic_id_sz;
4783         size_t sz;
4784
4785         /* First query all VNIC ids */
4786         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4787         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4788                         RTE_CACHE_LINE_SIZE);
4789         if (vnic_ids == NULL)
4790                 return -ENOMEM;
4791
4792         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4793                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4794
4795         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4796
4797         if (num_vnic_ids < 0)
4798                 return num_vnic_ids;
4799
4800         /* Retrieve VNIC, update bd_stall then update */
4801
4802         for (i = 0; i < num_vnic_ids; i++) {
4803                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4804                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4805                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4806                 if (rc)
4807                         break;
4808                 if (vnic.mru <= 4)      /* Indicates unallocated */
4809                         continue;
4810
4811                 vnic_cb(&vnic, cbdata);
4812
4813                 rc = hwrm_cb(bp, &vnic);
4814                 if (rc)
4815                         break;
4816         }
4817
4818         rte_free(vnic_ids);
4819
4820         return rc;
4821 }
4822
4823 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4824                                               bool on)
4825 {
4826         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4827         struct hwrm_func_cfg_input req = {0};
4828         int rc;
4829
4830         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4831
4832         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4833         req.enables |= rte_cpu_to_le_32(
4834                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4835         req.vlan_antispoof_mode = on ?
4836                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4837                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4838         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4839
4840         HWRM_CHECK_RESULT();
4841         HWRM_UNLOCK();
4842
4843         return rc;
4844 }
4845
4846 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4847 {
4848         struct bnxt_vnic_info vnic;
4849         uint16_t *vnic_ids;
4850         size_t vnic_id_sz;
4851         int num_vnic_ids, i;
4852         size_t sz;
4853         int rc;
4854
4855         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4856         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4857                         RTE_CACHE_LINE_SIZE);
4858         if (vnic_ids == NULL)
4859                 return -ENOMEM;
4860
4861         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4862                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4863
4864         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4865         if (rc <= 0)
4866                 goto exit;
4867         num_vnic_ids = rc;
4868
4869         /*
4870          * Loop through to find the default VNIC ID.
4871          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4872          * by sending the hwrm_func_qcfg command to the firmware.
4873          */
4874         for (i = 0; i < num_vnic_ids; i++) {
4875                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4876                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4877                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4878                                         bp->pf->first_vf_id + vf);
4879                 if (rc)
4880                         goto exit;
4881                 if (vnic.func_default) {
4882                         rte_free(vnic_ids);
4883                         return vnic.fw_vnic_id;
4884                 }
4885         }
4886         /* Could not find a default VNIC. */
4887         PMD_DRV_LOG(ERR, "No default VNIC\n");
4888 exit:
4889         rte_free(vnic_ids);
4890         return rc;
4891 }
4892
4893 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4894                          uint16_t dst_id,
4895                          struct bnxt_filter_info *filter)
4896 {
4897         int rc = 0;
4898         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4899         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4900         uint32_t enables = 0;
4901
4902         if (filter->fw_em_filter_id != UINT64_MAX)
4903                 bnxt_hwrm_clear_em_filter(bp, filter);
4904
4905         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4906
4907         req.flags = rte_cpu_to_le_32(filter->flags);
4908
4909         enables = filter->enables |
4910               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4911         req.dst_id = rte_cpu_to_le_16(dst_id);
4912
4913         if (filter->ip_addr_type) {
4914                 req.ip_addr_type = filter->ip_addr_type;
4915                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4916         }
4917         if (enables &
4918             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4919                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4920         if (enables &
4921             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4922                 memcpy(req.src_macaddr, filter->src_macaddr,
4923                        RTE_ETHER_ADDR_LEN);
4924         if (enables &
4925             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4926                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4927                        RTE_ETHER_ADDR_LEN);
4928         if (enables &
4929             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4930                 req.ovlan_vid = filter->l2_ovlan;
4931         if (enables &
4932             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4933                 req.ivlan_vid = filter->l2_ivlan;
4934         if (enables &
4935             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4936                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4937         if (enables &
4938             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4939                 req.ip_protocol = filter->ip_protocol;
4940         if (enables &
4941             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4942                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4943         if (enables &
4944             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4945                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4946         if (enables &
4947             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4948                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4949         if (enables &
4950             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4951                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4952         if (enables &
4953             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4954                 req.mirror_vnic_id = filter->mirror_vnic_id;
4955
4956         req.enables = rte_cpu_to_le_32(enables);
4957
4958         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4959
4960         HWRM_CHECK_RESULT();
4961
4962         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4963         HWRM_UNLOCK();
4964
4965         return rc;
4966 }
4967
4968 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4969 {
4970         int rc = 0;
4971         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4972         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4973
4974         if (filter->fw_em_filter_id == UINT64_MAX)
4975                 return 0;
4976
4977         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4978
4979         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4980
4981         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4982
4983         HWRM_CHECK_RESULT();
4984         HWRM_UNLOCK();
4985
4986         filter->fw_em_filter_id = UINT64_MAX;
4987         filter->fw_l2_filter_id = UINT64_MAX;
4988
4989         return 0;
4990 }
4991
4992 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4993                          uint16_t dst_id,
4994                          struct bnxt_filter_info *filter)
4995 {
4996         int rc = 0;
4997         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4998         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4999                                                 bp->hwrm_cmd_resp_addr;
5000         uint32_t enables = 0;
5001
5002         if (filter->fw_ntuple_filter_id != UINT64_MAX)
5003                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
5004
5005         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
5006
5007         req.flags = rte_cpu_to_le_32(filter->flags);
5008
5009         enables = filter->enables |
5010               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
5011         req.dst_id = rte_cpu_to_le_16(dst_id);
5012
5013         if (filter->ip_addr_type) {
5014                 req.ip_addr_type = filter->ip_addr_type;
5015                 enables |=
5016                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
5017         }
5018         if (enables &
5019             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5020                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5021         if (enables &
5022             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5023                 memcpy(req.src_macaddr, filter->src_macaddr,
5024                        RTE_ETHER_ADDR_LEN);
5025         if (enables &
5026             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5027                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5028         if (enables &
5029             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5030                 req.ip_protocol = filter->ip_protocol;
5031         if (enables &
5032             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5033                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5034         if (enables &
5035             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5036                 req.src_ipaddr_mask[0] =
5037                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5038         if (enables &
5039             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5040                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5041         if (enables &
5042             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5043                 req.dst_ipaddr_mask[0] =
5044                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5045         if (enables &
5046             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5047                 req.src_port = rte_cpu_to_le_16(filter->src_port);
5048         if (enables &
5049             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5050                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5051         if (enables &
5052             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5053                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5054         if (enables &
5055             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5056                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5057         if (enables &
5058             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5059                 req.mirror_vnic_id = filter->mirror_vnic_id;
5060
5061         req.enables = rte_cpu_to_le_32(enables);
5062
5063         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5064
5065         HWRM_CHECK_RESULT();
5066
5067         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5068         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5069         HWRM_UNLOCK();
5070
5071         return rc;
5072 }
5073
5074 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5075                                 struct bnxt_filter_info *filter)
5076 {
5077         int rc = 0;
5078         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5079         struct hwrm_cfa_ntuple_filter_free_output *resp =
5080                                                 bp->hwrm_cmd_resp_addr;
5081
5082         if (filter->fw_ntuple_filter_id == UINT64_MAX)
5083                 return 0;
5084
5085         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5086
5087         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5088
5089         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5090
5091         HWRM_CHECK_RESULT();
5092         HWRM_UNLOCK();
5093
5094         filter->fw_ntuple_filter_id = UINT64_MAX;
5095
5096         return 0;
5097 }
5098
5099 static int
5100 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5101 {
5102         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5103         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5104         struct bnxt_rx_queue **rxqs = bp->rx_queues;
5105         uint16_t *ring_tbl = vnic->rss_table;
5106         int nr_ctxs = vnic->num_lb_ctxts;
5107         int max_rings = bp->rx_nr_rings;
5108         int i, j, k, cnt;
5109         int rc = 0;
5110
5111         for (i = 0, k = 0; i < nr_ctxs; i++) {
5112                 struct bnxt_rx_ring_info *rxr;
5113                 struct bnxt_cp_ring_info *cpr;
5114
5115                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5116
5117                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5118                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5119                 req.hash_mode_flags = vnic->hash_mode;
5120
5121                 req.ring_grp_tbl_addr =
5122                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5123                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5124                                      2 * sizeof(*ring_tbl));
5125                 req.hash_key_tbl_addr =
5126                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5127
5128                 req.ring_table_pair_index = i;
5129                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5130
5131                 for (j = 0; j < 64; j++) {
5132                         uint16_t ring_id;
5133
5134                         /* Find next active ring. */
5135                         for (cnt = 0; cnt < max_rings; cnt++) {
5136                                 if (rxqs[k]->rx_started)
5137                                         break;
5138                                 if (++k == max_rings)
5139                                         k = 0;
5140                         }
5141
5142                         /* Return if no rings are active. */
5143                         if (cnt == max_rings) {
5144                                 HWRM_UNLOCK();
5145                                 return 0;
5146                         }
5147
5148                         /* Add rx/cp ring pair to RSS table. */
5149                         rxr = rxqs[k]->rx_ring;
5150                         cpr = rxqs[k]->cp_ring;
5151
5152                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5153                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5154                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5155                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5156
5157                         if (++k == max_rings)
5158                                 k = 0;
5159                 }
5160                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5161                                             BNXT_USE_CHIMP_MB);
5162
5163                 HWRM_CHECK_RESULT();
5164                 HWRM_UNLOCK();
5165         }
5166
5167         return rc;
5168 }
5169
5170 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5171 {
5172         unsigned int rss_idx, fw_idx, i;
5173
5174         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5175                 return 0;
5176
5177         if (!(vnic->rss_table && vnic->hash_type))
5178                 return 0;
5179
5180         if (BNXT_CHIP_P5(bp))
5181                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5182
5183         /*
5184          * Fill the RSS hash & redirection table with
5185          * ring group ids for all VNICs
5186          */
5187         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5188              rss_idx++, fw_idx++) {
5189                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5190                         fw_idx %= bp->rx_cp_nr_rings;
5191                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5192                                 break;
5193                         fw_idx++;
5194                 }
5195
5196                 if (i == bp->rx_cp_nr_rings)
5197                         return 0;
5198
5199                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5200         }
5201
5202         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5203 }
5204
5205 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5206         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5207 {
5208         uint16_t flags;
5209
5210         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5211
5212         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5213         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5214
5215         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5216         req->num_cmpl_dma_aggr_during_int =
5217                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5218
5219         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5220
5221         /* min timer set to 1/2 of interrupt timer */
5222         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5223
5224         /* buf timer set to 1/4 of interrupt timer */
5225         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5226
5227         req->cmpl_aggr_dma_tmr_during_int =
5228                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5229
5230         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5231                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5232         req->flags = rte_cpu_to_le_16(flags);
5233 }
5234
5235 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5236                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5237 {
5238         struct hwrm_ring_aggint_qcaps_input req = {0};
5239         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5240         uint32_t enables;
5241         uint16_t flags;
5242         int rc;
5243
5244         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5246         HWRM_CHECK_RESULT();
5247
5248         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5249         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5250
5251         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5252                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5253         agg_req->flags = rte_cpu_to_le_16(flags);
5254         enables =
5255          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5256          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5257         agg_req->enables = rte_cpu_to_le_32(enables);
5258
5259         HWRM_UNLOCK();
5260         return rc;
5261 }
5262
5263 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5264                         struct bnxt_coal *coal, uint16_t ring_id)
5265 {
5266         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5267         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5268                                                 bp->hwrm_cmd_resp_addr;
5269         int rc;
5270
5271         /* Set ring coalesce parameters only for 100G NICs */
5272         if (BNXT_CHIP_P5(bp)) {
5273                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5274                         return -1;
5275         } else if (bnxt_stratus_device(bp)) {
5276                 bnxt_hwrm_set_coal_params(coal, &req);
5277         } else {
5278                 return 0;
5279         }
5280
5281         HWRM_PREP(&req,
5282                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5283                   BNXT_USE_CHIMP_MB);
5284         req.ring_id = rte_cpu_to_le_16(ring_id);
5285         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5286         HWRM_CHECK_RESULT();
5287         HWRM_UNLOCK();
5288         return 0;
5289 }
5290
5291 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5292 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5293 {
5294         struct hwrm_func_backing_store_qcaps_input req = {0};
5295         struct hwrm_func_backing_store_qcaps_output *resp =
5296                 bp->hwrm_cmd_resp_addr;
5297         struct bnxt_ctx_pg_info *ctx_pg;
5298         struct bnxt_ctx_mem_info *ctx;
5299         int total_alloc_len;
5300         int rc, i, tqm_rings;
5301
5302         if (!BNXT_CHIP_P5(bp) ||
5303             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5304             BNXT_VF(bp) ||
5305             bp->ctx)
5306                 return 0;
5307
5308         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5309         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5310         HWRM_CHECK_RESULT_SILENT();
5311
5312         total_alloc_len = sizeof(*ctx);
5313         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5314                           RTE_CACHE_LINE_SIZE);
5315         if (!ctx) {
5316                 rc = -ENOMEM;
5317                 goto ctx_err;
5318         }
5319
5320         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5321         ctx->qp_min_qp1_entries =
5322                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5323         ctx->qp_max_l2_entries =
5324                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5325         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5326         ctx->srq_max_l2_entries =
5327                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5328         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5329         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5330         ctx->cq_max_l2_entries =
5331                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5332         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5333         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5334         ctx->vnic_max_vnic_entries =
5335                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5336         ctx->vnic_max_ring_table_entries =
5337                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5338         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5339         ctx->stat_max_entries =
5340                 rte_le_to_cpu_32(resp->stat_max_entries);
5341         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5342         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5343         ctx->tqm_min_entries_per_ring =
5344                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5345         ctx->tqm_max_entries_per_ring =
5346                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5347         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5348         if (!ctx->tqm_entries_multiple)
5349                 ctx->tqm_entries_multiple = 1;
5350         ctx->mrav_max_entries =
5351                 rte_le_to_cpu_32(resp->mrav_max_entries);
5352         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5353         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5354         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5355         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5356
5357         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5358                                   RTE_MIN(ctx->tqm_fp_rings_count,
5359                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5360                                   bp->max_q;
5361
5362         /* Check if the ext ring count needs to be counted.
5363          * Ext ring count is available only with new FW so we should not
5364          * look at the field on older FW.
5365          */
5366         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5367             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5368                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5369                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5370                                                   ctx->tqm_fp_rings_count);
5371         }
5372
5373         tqm_rings = ctx->tqm_fp_rings_count + 1;
5374
5375         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5376                             sizeof(*ctx_pg) * tqm_rings,
5377                             RTE_CACHE_LINE_SIZE);
5378         if (!ctx_pg) {
5379                 rc = -ENOMEM;
5380                 goto ctx_err;
5381         }
5382         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5383                 ctx->tqm_mem[i] = ctx_pg;
5384
5385         bp->ctx = ctx;
5386 ctx_err:
5387         HWRM_UNLOCK();
5388         return rc;
5389 }
5390
5391 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5392 {
5393         struct hwrm_func_backing_store_cfg_input req = {0};
5394         struct hwrm_func_backing_store_cfg_output *resp =
5395                 bp->hwrm_cmd_resp_addr;
5396         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5397         struct bnxt_ctx_pg_info *ctx_pg;
5398         uint32_t *num_entries;
5399         uint64_t *pg_dir;
5400         uint8_t *pg_attr;
5401         uint32_t ena;
5402         int i, rc;
5403
5404         if (!ctx)
5405                 return 0;
5406
5407         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5408         req.enables = rte_cpu_to_le_32(enables);
5409
5410         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5411                 ctx_pg = &ctx->qp_mem;
5412                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5413                 req.qp_num_qp1_entries =
5414                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5415                 req.qp_num_l2_entries =
5416                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5417                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5418                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5419                                       &req.qpc_pg_size_qpc_lvl,
5420                                       &req.qpc_page_dir);
5421         }
5422
5423         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5424                 ctx_pg = &ctx->srq_mem;
5425                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5426                 req.srq_num_l2_entries =
5427                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5428                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5429                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5430                                       &req.srq_pg_size_srq_lvl,
5431                                       &req.srq_page_dir);
5432         }
5433
5434         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5435                 ctx_pg = &ctx->cq_mem;
5436                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5437                 req.cq_num_l2_entries =
5438                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5439                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5440                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5441                                       &req.cq_pg_size_cq_lvl,
5442                                       &req.cq_page_dir);
5443         }
5444
5445         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5446                 ctx_pg = &ctx->vnic_mem;
5447                 req.vnic_num_vnic_entries =
5448                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5449                 req.vnic_num_ring_table_entries =
5450                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5451                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5452                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5453                                       &req.vnic_pg_size_vnic_lvl,
5454                                       &req.vnic_page_dir);
5455         }
5456
5457         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5458                 ctx_pg = &ctx->stat_mem;
5459                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5460                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5461                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5462                                       &req.stat_pg_size_stat_lvl,
5463                                       &req.stat_page_dir);
5464         }
5465
5466         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5467         num_entries = &req.tqm_sp_num_entries;
5468         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5469         pg_dir = &req.tqm_sp_page_dir;
5470         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5471         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5472                 if (!(enables & ena))
5473                         continue;
5474
5475                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5476
5477                 ctx_pg = ctx->tqm_mem[i];
5478                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5479                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5480         }
5481
5482         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5483                 /* DPDK does not need to configure MRAV and TIM type.
5484                  * So we are skipping over MRAV and TIM. Skip to configure
5485                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5486                  */
5487                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5488                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5489                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5490                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5491                                       &req.tqm_ring8_page_dir);
5492         }
5493
5494         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5495         HWRM_CHECK_RESULT();
5496         HWRM_UNLOCK();
5497
5498         return rc;
5499 }
5500
5501 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5502 {
5503         struct hwrm_port_qstats_ext_input req = {0};
5504         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5505         struct bnxt_pf_info *pf = bp->pf;
5506         int rc;
5507
5508         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5509               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5510                 return 0;
5511
5512         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5513
5514         req.port_id = rte_cpu_to_le_16(pf->port_id);
5515         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5516                 req.tx_stat_host_addr =
5517                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5518                 req.tx_stat_size =
5519                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5520         }
5521         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5522                 req.rx_stat_host_addr =
5523                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5524                 req.rx_stat_size =
5525                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5526         }
5527         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5528
5529         if (rc) {
5530                 bp->fw_rx_port_stats_ext_size = 0;
5531                 bp->fw_tx_port_stats_ext_size = 0;
5532         } else {
5533                 bp->fw_rx_port_stats_ext_size =
5534                         rte_le_to_cpu_16(resp->rx_stat_size);
5535                 bp->fw_tx_port_stats_ext_size =
5536                         rte_le_to_cpu_16(resp->tx_stat_size);
5537         }
5538
5539         HWRM_CHECK_RESULT();
5540         HWRM_UNLOCK();
5541
5542         return rc;
5543 }
5544
5545 int
5546 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5547 {
5548         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5549         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5550                 bp->hwrm_cmd_resp_addr;
5551         int rc = 0;
5552
5553         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5554         req.tunnel_type = type;
5555         req.dest_fid = bp->fw_fid;
5556         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5557         HWRM_CHECK_RESULT();
5558
5559         HWRM_UNLOCK();
5560
5561         return rc;
5562 }
5563
5564 int
5565 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5566 {
5567         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5568         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5569                 bp->hwrm_cmd_resp_addr;
5570         int rc = 0;
5571
5572         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5573         req.tunnel_type = type;
5574         req.dest_fid = bp->fw_fid;
5575         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5576         HWRM_CHECK_RESULT();
5577
5578         HWRM_UNLOCK();
5579
5580         return rc;
5581 }
5582
5583 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5584 {
5585         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5586         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5587                 bp->hwrm_cmd_resp_addr;
5588         int rc = 0;
5589
5590         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5591         req.src_fid = bp->fw_fid;
5592         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5593         HWRM_CHECK_RESULT();
5594
5595         if (type)
5596                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5597
5598         HWRM_UNLOCK();
5599
5600         return rc;
5601 }
5602
5603 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5604                                    uint16_t *dst_fid)
5605 {
5606         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5607         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5608                 bp->hwrm_cmd_resp_addr;
5609         int rc = 0;
5610
5611         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5612         req.src_fid = bp->fw_fid;
5613         req.tunnel_type = tun_type;
5614         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5615         HWRM_CHECK_RESULT();
5616
5617         if (dst_fid)
5618                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5619
5620         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5621
5622         HWRM_UNLOCK();
5623
5624         return rc;
5625 }
5626
5627 int bnxt_hwrm_set_mac(struct bnxt *bp)
5628 {
5629         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5630         struct hwrm_func_vf_cfg_input req = {0};
5631         int rc = 0;
5632
5633         if (!BNXT_VF(bp))
5634                 return 0;
5635
5636         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5637
5638         req.enables =
5639                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5640         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5641
5642         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5643
5644         HWRM_CHECK_RESULT();
5645
5646         HWRM_UNLOCK();
5647
5648         return rc;
5649 }
5650
5651 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5652 {
5653         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5654         struct hwrm_func_drv_if_change_input req = {0};
5655         uint32_t flags;
5656         int rc;
5657
5658         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5659                 return 0;
5660
5661         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5662          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5663          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5664          */
5665         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5666                 return 0;
5667
5668         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5669
5670         if (up)
5671                 req.flags =
5672                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5673
5674         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5675
5676         HWRM_CHECK_RESULT();
5677         flags = rte_le_to_cpu_32(resp->flags);
5678         HWRM_UNLOCK();
5679
5680         if (!up)
5681                 return 0;
5682
5683         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5684                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5685                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5686         }
5687
5688         return 0;
5689 }
5690
5691 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5692 {
5693         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5694         struct bnxt_error_recovery_info *info = bp->recovery_info;
5695         struct hwrm_error_recovery_qcfg_input req = {0};
5696         uint32_t flags = 0;
5697         unsigned int i;
5698         int rc;
5699
5700         /* Older FW does not have error recovery support */
5701         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5702                 return 0;
5703
5704         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5705
5706         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5707
5708         HWRM_CHECK_RESULT();
5709
5710         flags = rte_le_to_cpu_32(resp->flags);
5711         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5712                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5713         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5714                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5715
5716         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5717             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5718                 rc = -EINVAL;
5719                 goto err;
5720         }
5721
5722         /* FW returned values are in units of 100msec */
5723         info->driver_polling_freq =
5724                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5725         info->master_func_wait_period =
5726                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5727         info->normal_func_wait_period =
5728                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5729         info->master_func_wait_period_after_reset =
5730                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5731         info->max_bailout_time_after_reset =
5732                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5733         info->status_regs[BNXT_FW_STATUS_REG] =
5734                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5735         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5736                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5737         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5738                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5739         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5740                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5741         info->reg_array_cnt =
5742                 rte_le_to_cpu_32(resp->reg_array_cnt);
5743
5744         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5745                 rc = -EINVAL;
5746                 goto err;
5747         }
5748
5749         for (i = 0; i < info->reg_array_cnt; i++) {
5750                 info->reset_reg[i] =
5751                         rte_le_to_cpu_32(resp->reset_reg[i]);
5752                 info->reset_reg_val[i] =
5753                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5754                 info->delay_after_reset[i] =
5755                         resp->delay_after_reset[i];
5756         }
5757 err:
5758         HWRM_UNLOCK();
5759
5760         /* Map the FW status registers */
5761         if (!rc)
5762                 rc = bnxt_map_fw_health_status_regs(bp);
5763
5764         if (rc) {
5765                 rte_free(bp->recovery_info);
5766                 bp->recovery_info = NULL;
5767         }
5768         return rc;
5769 }
5770
5771 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5772 {
5773         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5774         struct hwrm_fw_reset_input req = {0};
5775         int rc;
5776
5777         if (!BNXT_PF(bp))
5778                 return -EOPNOTSUPP;
5779
5780         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5781
5782         req.embedded_proc_type =
5783                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5784         req.selfrst_status =
5785                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5786         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5787
5788         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5789                                     BNXT_USE_KONG(bp));
5790
5791         HWRM_CHECK_RESULT();
5792         HWRM_UNLOCK();
5793
5794         return rc;
5795 }
5796
5797 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5798 {
5799         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5800         struct hwrm_port_ts_query_input req = {0};
5801         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5802         uint32_t flags = 0;
5803         int rc;
5804
5805         if (!ptp)
5806                 return 0;
5807
5808         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5809
5810         switch (path) {
5811         case BNXT_PTP_FLAGS_PATH_TX:
5812                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5813                 break;
5814         case BNXT_PTP_FLAGS_PATH_RX:
5815                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5816                 break;
5817         case BNXT_PTP_FLAGS_CURRENT_TIME:
5818                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5819                 break;
5820         }
5821
5822         req.flags = rte_cpu_to_le_32(flags);
5823         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5824
5825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5826
5827         HWRM_CHECK_RESULT();
5828
5829         if (timestamp) {
5830                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5831                 *timestamp |=
5832                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5833         }
5834         HWRM_UNLOCK();
5835
5836         return rc;
5837 }
5838
5839 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5840 {
5841         int rc = 0;
5842
5843         struct hwrm_cfa_counter_qcaps_input req = {0};
5844         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5845
5846         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5847                 PMD_DRV_LOG(DEBUG,
5848                             "Not a PF or trusted VF. Command not supported\n");
5849                 return 0;
5850         }
5851
5852         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5853         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5854         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5855
5856         HWRM_CHECK_RESULT();
5857         if (max_fc)
5858                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5859         HWRM_UNLOCK();
5860
5861         return 0;
5862 }
5863
5864 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5865 {
5866         int rc = 0;
5867         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5868         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5869
5870         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5871                 PMD_DRV_LOG(DEBUG,
5872                             "Not a PF or trusted VF. Command not supported\n");
5873                 return 0;
5874         }
5875
5876         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5877
5878         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5879         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5880         req.page_dir = rte_cpu_to_le_64(dma_addr);
5881
5882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5883
5884         HWRM_CHECK_RESULT();
5885         if (ctx_id) {
5886                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5887                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5888         }
5889         HWRM_UNLOCK();
5890
5891         return 0;
5892 }
5893
5894 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5895 {
5896         int rc = 0;
5897         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5898         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5899
5900         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5901                 PMD_DRV_LOG(DEBUG,
5902                             "Not a PF or trusted VF. Command not supported\n");
5903                 return 0;
5904         }
5905
5906         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5907
5908         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5909
5910         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5911
5912         HWRM_CHECK_RESULT();
5913         HWRM_UNLOCK();
5914
5915         return rc;
5916 }
5917
5918 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5919                               uint16_t cntr, uint16_t ctx_id,
5920                               uint32_t num_entries, bool enable)
5921 {
5922         struct hwrm_cfa_counter_cfg_input req = {0};
5923         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5924         uint16_t flags = 0;
5925         int rc;
5926
5927         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5928                 PMD_DRV_LOG(DEBUG,
5929                             "Not a PF or trusted VF. Command not supported\n");
5930                 return 0;
5931         }
5932
5933         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5934
5935         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5936         req.counter_type = rte_cpu_to_le_16(cntr);
5937         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5938                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5939         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5940         if (dir == BNXT_DIR_RX)
5941                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5942         else if (dir == BNXT_DIR_TX)
5943                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5944         req.flags = rte_cpu_to_le_16(flags);
5945         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5946         req.num_entries = rte_cpu_to_le_32(num_entries);
5947
5948         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5949         HWRM_CHECK_RESULT();
5950         HWRM_UNLOCK();
5951
5952         return 0;
5953 }
5954
5955 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5956                                  enum bnxt_flow_dir dir,
5957                                  uint16_t cntr,
5958                                  uint16_t num_entries)
5959 {
5960         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5961         struct hwrm_cfa_counter_qstats_input req = {0};
5962         uint16_t flow_ctx_id = 0;
5963         uint16_t flags = 0;
5964         int rc = 0;
5965
5966         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5967                 PMD_DRV_LOG(DEBUG,
5968                             "Not a PF or trusted VF. Command not supported\n");
5969                 return 0;
5970         }
5971
5972         if (dir == BNXT_DIR_RX) {
5973                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5974                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5975         } else if (dir == BNXT_DIR_TX) {
5976                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5977                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5978         }
5979
5980         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5981         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5982         req.counter_type = rte_cpu_to_le_16(cntr);
5983         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5984         req.num_entries = rte_cpu_to_le_16(num_entries);
5985         req.flags = rte_cpu_to_le_16(flags);
5986         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5987
5988         HWRM_CHECK_RESULT();
5989         HWRM_UNLOCK();
5990
5991         return 0;
5992 }
5993
5994 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5995                                 uint16_t *first_vf_id)
5996 {
5997         int rc = 0;
5998         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5999         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6000
6001         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
6002
6003         req.fid = rte_cpu_to_le_16(fid);
6004
6005         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6006
6007         HWRM_CHECK_RESULT();
6008
6009         if (first_vf_id)
6010                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
6011
6012         HWRM_UNLOCK();
6013
6014         return rc;
6015 }
6016
6017 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6018 {
6019         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6020         struct hwrm_cfa_pair_alloc_input req = {0};
6021         int rc;
6022
6023         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6024                 PMD_DRV_LOG(DEBUG,
6025                             "Not a PF or trusted VF. Command not supported\n");
6026                 return 0;
6027         }
6028
6029         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6030         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6031         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6032                  bp->eth_dev->data->name, rep_bp->vf_id);
6033
6034         req.pf_b_id = rep_bp->parent_pf_idx;
6035         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6036                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6037         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6038         req.host_b_id = 1; /* TBD - Confirm if this is OK */
6039
6040         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6041                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6042         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6043                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6044         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6045                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6046         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6047                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6048
6049         req.q_ab = rep_bp->rep_q_r2f;
6050         req.q_ba = rep_bp->rep_q_f2r;
6051         req.fc_ab = rep_bp->rep_fc_r2f;
6052         req.fc_ba = rep_bp->rep_fc_f2r;
6053
6054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6055         HWRM_CHECK_RESULT();
6056
6057         HWRM_UNLOCK();
6058         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6059                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6060         return rc;
6061 }
6062
6063 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6064 {
6065         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6066         struct hwrm_cfa_pair_free_input req = {0};
6067         int rc;
6068
6069         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6070                 PMD_DRV_LOG(DEBUG,
6071                             "Not a PF or trusted VF. Command not supported\n");
6072                 return 0;
6073         }
6074
6075         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6076         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6077                  bp->eth_dev->data->name, rep_bp->vf_id);
6078         req.pf_b_id = rep_bp->parent_pf_idx;
6079         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6080         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6081                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6082         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6083         HWRM_CHECK_RESULT();
6084         HWRM_UNLOCK();
6085         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6086                     rep_bp->vf_id);
6087         return rc;
6088 }
6089
6090 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6091 {
6092         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6093                                         bp->hwrm_cmd_resp_addr;
6094         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6095         uint32_t flags = 0;
6096         int rc = 0;
6097
6098         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6099                 return 0;
6100
6101         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6102                 PMD_DRV_LOG(DEBUG,
6103                             "Not a PF or trusted VF. Command not supported\n");
6104                 return 0;
6105         }
6106
6107         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6108         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6109
6110         HWRM_CHECK_RESULT();
6111         flags = rte_le_to_cpu_32(resp->flags);
6112         HWRM_UNLOCK();
6113
6114         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6115                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6116         else
6117                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6118
6119         return rc;
6120 }
6121
6122 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6123                             uint32_t echo_req_data2)
6124 {
6125         struct hwrm_func_echo_response_input req = {0};
6126         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6127         int rc;
6128
6129         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6130         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6131         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6132
6133         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6134
6135         HWRM_CHECK_RESULT();
6136         HWRM_UNLOCK();
6137
6138         return rc;
6139 }
6140
6141 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6142 {
6143         struct hwrm_ver_get_input req = {.req_type = 0 };
6144         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6145         int rc = 0;
6146
6147         bp->max_req_len = HWRM_MAX_REQ_LEN;
6148         bp->max_resp_len = BNXT_PAGE_SIZE;
6149         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6150
6151         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6152         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6153         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6154         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6155
6156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6157
6158         HWRM_CHECK_RESULT_SILENT();
6159
6160         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6161                 rc = -EAGAIN;
6162
6163         HWRM_UNLOCK();
6164
6165         return rc;
6166 }
6167
6168 int bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt *bp, uint16_t i2c_addr,
6169                                           uint16_t page_number, uint16_t start_addr,
6170                                           uint16_t data_length, uint8_t *buf)
6171 {
6172         struct hwrm_port_phy_i2c_read_output *resp = bp->hwrm_cmd_resp_addr;
6173         struct hwrm_port_phy_i2c_read_input req = {0};
6174         uint32_t enables = HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET;
6175         int rc, byte_offset = 0;
6176
6177         do {
6178                 uint16_t xfer_size;
6179
6180                 HWRM_PREP(&req, HWRM_PORT_PHY_I2C_READ, BNXT_USE_CHIMP_MB);
6181                 req.i2c_slave_addr = i2c_addr;
6182                 req.page_number = rte_cpu_to_le_16(page_number);
6183                 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
6184
6185                 xfer_size = RTE_MIN(data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
6186                 req.page_offset = rte_cpu_to_le_16(start_addr + byte_offset);
6187                 req.data_length = xfer_size;
6188                 req.enables = rte_cpu_to_le_32(start_addr + byte_offset ? enables : 0);
6189                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6190                 HWRM_CHECK_RESULT();
6191
6192                 memcpy(buf + byte_offset, resp->data, xfer_size);
6193
6194                 data_length -= xfer_size;
6195                 byte_offset += xfer_size;
6196
6197                 HWRM_UNLOCK();
6198         } while (data_length > 0);
6199
6200         return rc;
6201 }
6202
6203 void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index)
6204 {
6205         struct bnxt_tx_queue *txq = bp->tx_queues[queue_index];
6206         struct bnxt_tx_ring_info *txr = txq->tx_ring;
6207         struct bnxt_ring *ring = txr->tx_ring_struct;
6208         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
6209
6210         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6211                 bnxt_hwrm_ring_free(bp, ring,
6212                                     HWRM_RING_FREE_INPUT_RING_TYPE_TX,
6213                                     cpr->cp_ring_struct->fw_ring_id);
6214                 ring->fw_ring_id = INVALID_HW_RING_ID;
6215         }
6216
6217         if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
6218                 bnxt_hwrm_stat_ctx_free(bp, cpr);
6219                 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
6220         }
6221
6222         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
6223                 bnxt_free_cp_ring(bp, cpr);
6224                 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
6225         }
6226 }