1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SHORT_CMD_TIMEOUT 50000
31 #define HWRM_SPEC_CODE_1_8_3 0x10803
32 #define HWRM_VERSION_1_9_1 0x10901
33 #define HWRM_VERSION_1_9_2 0x10903
35 struct bnxt_plcmodes_cfg {
37 uint16_t jumbo_thresh;
39 uint16_t hds_threshold;
42 static int page_getenum(size_t size)
58 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
59 return sizeof(void *) * 8 - 1;
62 static int page_roundup(size_t size)
64 return 1 << page_getenum(size);
67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
71 if (rmem->nr_pages > 1) {
73 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
75 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
80 * HWRM Functions (sent to HWRM)
81 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
82 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
83 * command was failed by the ChiMP.
86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
87 uint32_t msg_len, bool use_kong_mb)
90 struct input *req = msg;
91 struct output *resp = bp->hwrm_cmd_resp_addr;
95 uint16_t max_req_len = bp->max_req_len;
96 struct hwrm_short_input short_input = { 0 };
97 uint16_t bar_offset = use_kong_mb ?
98 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
99 uint16_t mb_trigger_offset = use_kong_mb ?
100 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
103 /* Do not send HWRM commands to firmware in error state */
104 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
107 /* For VER_GET command, set timeout as 50ms */
108 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
109 timeout = HWRM_SHORT_CMD_TIMEOUT;
111 timeout = HWRM_CMD_TIMEOUT;
113 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
114 msg_len > bp->max_req_len) {
115 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
117 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
118 memcpy(short_cmd_req, req, msg_len);
120 short_input.req_type = rte_cpu_to_le_16(req->req_type);
121 short_input.signature = rte_cpu_to_le_16(
122 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
123 short_input.size = rte_cpu_to_le_16(msg_len);
124 short_input.req_addr =
125 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
127 data = (uint32_t *)&short_input;
128 msg_len = sizeof(short_input);
130 /* Sync memory write before updating doorbell */
133 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
136 /* Write request msg to hwrm channel */
137 for (i = 0; i < msg_len; i += 4) {
138 bar = (uint8_t *)bp->bar0 + bar_offset + i;
139 rte_write32(*data, bar);
143 /* Zero the rest of the request space */
144 for (; i < max_req_len; i += 4) {
145 bar = (uint8_t *)bp->bar0 + bar_offset + i;
149 /* Ring channel doorbell */
150 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
153 /* Poll for the valid bit */
154 for (i = 0; i < timeout; i++) {
155 /* Sanity check on the resp->resp_len */
157 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
158 /* Last byte of resp contains the valid key */
159 valid = (uint8_t *)resp + resp->resp_len - 1;
160 if (*valid == HWRM_RESP_VALID_KEY)
167 /* Suppress VER_GET timeout messages during reset recovery */
168 if (bp->flags & BNXT_FLAG_FW_RESET &&
169 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
172 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
180 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
181 * spinlock, and does initial processing.
183 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
184 * releases the spinlock only if it returns. If the regular int return codes
185 * are not used by the function, HWRM_CHECK_RESULT() should not be used
186 * directly, rather it should be copied and modified to suit the function.
188 * HWRM_UNLOCK() must be called after all response processing is completed.
190 #define HWRM_PREP(req, type, kong) do { \
191 rte_spinlock_lock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
194 req.cmpl_ring = rte_cpu_to_le_16(-1); \
195 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
197 req.target_id = rte_cpu_to_le_16(0xffff); \
198 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
223 if (resp->error_code) { \
224 rc = rte_le_to_cpu_16(resp->error_code); \
225 if (resp->resp_len >= 16) { \
226 struct hwrm_err_output *tmp_hwrm_err_op = \
229 "error %d:%d:%08x:%04x\n", \
230 rc, tmp_hwrm_err_op->cmd_err, \
232 tmp_hwrm_err_op->opaque_0), \
234 tmp_hwrm_err_op->opaque_1)); \
236 PMD_DRV_LOG(ERR, "error %d\n", rc); \
238 rte_spinlock_unlock(&bp->hwrm_lock); \
239 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
247 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
249 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
252 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
253 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
255 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
256 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
259 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
267 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
268 struct bnxt_vnic_info *vnic,
270 struct bnxt_vlan_table_entry *vlan_table)
273 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
274 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
277 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
280 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
281 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
283 /* FIXME add multicast flag, when multicast adding options is supported
286 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
287 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
288 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
290 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
291 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
292 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
293 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
294 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
295 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
296 if (vnic->mc_addr_cnt) {
297 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
298 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
299 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
302 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
303 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
304 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
305 rte_mem_virt2iova(vlan_table));
306 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
308 req.mask = rte_cpu_to_le_32(mask);
310 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
318 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
320 struct bnxt_vlan_antispoof_table_entry *vlan_table)
323 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
324 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
325 bp->hwrm_cmd_resp_addr;
328 * Older HWRM versions did not support this command, and the set_rx_mask
329 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
330 * removed from set_rx_mask call, and this command was added.
332 * This command is also present from 1.7.8.11 and higher,
335 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
336 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
337 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
342 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
343 req.fid = rte_cpu_to_le_16(fid);
345 req.vlan_tag_mask_tbl_addr =
346 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
347 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
349 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
357 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
358 struct bnxt_filter_info *filter)
361 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
362 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
364 if (filter->fw_l2_filter_id == UINT64_MAX)
367 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
369 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
371 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
376 filter->fw_l2_filter_id = UINT64_MAX;
381 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
383 struct bnxt_filter_info *filter)
386 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
387 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
388 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
389 const struct rte_eth_vmdq_rx_conf *conf =
390 &dev_conf->rx_adv_conf.vmdq_rx_conf;
391 uint32_t enables = 0;
392 uint16_t j = dst_id - 1;
394 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
395 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
396 conf->pool_map[j].pools & (1UL << j)) {
398 "Add vlan %u to vmdq pool %u\n",
399 conf->pool_map[j].vlan_id, j);
401 filter->l2_ivlan = conf->pool_map[j].vlan_id;
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
404 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
407 if (filter->fw_l2_filter_id != UINT64_MAX)
408 bnxt_hwrm_clear_l2_filter(bp, filter);
410 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
412 req.flags = rte_cpu_to_le_32(filter->flags);
414 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
416 enables = filter->enables |
417 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
418 req.dst_id = rte_cpu_to_le_16(dst_id);
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
422 memcpy(req.l2_addr, filter->l2_addr,
425 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
426 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
429 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
430 req.l2_ovlan = filter->l2_ovlan;
432 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
433 req.l2_ivlan = filter->l2_ivlan;
435 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
436 req.l2_ovlan_mask = filter->l2_ovlan_mask;
438 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
439 req.l2_ivlan_mask = filter->l2_ivlan_mask;
440 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
441 req.src_id = rte_cpu_to_le_32(filter->src_id);
442 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
443 req.src_type = filter->src_type;
445 req.enables = rte_cpu_to_le_32(enables);
447 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
451 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
457 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
459 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
460 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
467 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
470 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
473 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
474 if (ptp->tx_tstamp_en)
475 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
478 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
479 req.flags = rte_cpu_to_le_32(flags);
480 req.enables = rte_cpu_to_le_32
481 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
482 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
490 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
493 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
494 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
495 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
497 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
501 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
503 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
509 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
512 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
516 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
517 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
518 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
519 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
520 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
521 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
522 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
523 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
524 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
525 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
526 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
527 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
528 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
529 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
530 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
531 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
532 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
533 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
541 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
544 struct hwrm_func_qcaps_input req = {.req_type = 0 };
545 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
546 uint16_t new_max_vfs;
550 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
552 req.fid = rte_cpu_to_le_16(0xffff);
554 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
558 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
559 flags = rte_le_to_cpu_32(resp->flags);
561 bp->pf.port_id = resp->port_id;
562 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
563 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
564 new_max_vfs = bp->pdev->max_vfs;
565 if (new_max_vfs != bp->pf.max_vfs) {
567 rte_free(bp->pf.vf_info);
568 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
569 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
570 bp->pf.max_vfs = new_max_vfs;
571 for (i = 0; i < new_max_vfs; i++) {
572 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
573 bp->pf.vf_info[i].vlan_table =
574 rte_zmalloc("VF VLAN table",
577 if (bp->pf.vf_info[i].vlan_table == NULL)
579 "Fail to alloc VLAN table for VF %d\n",
583 bp->pf.vf_info[i].vlan_table);
584 bp->pf.vf_info[i].vlan_as_table =
585 rte_zmalloc("VF VLAN AS table",
588 if (bp->pf.vf_info[i].vlan_as_table == NULL)
590 "Alloc VLAN AS table for VF %d fail\n",
594 bp->pf.vf_info[i].vlan_as_table);
595 STAILQ_INIT(&bp->pf.vf_info[i].filter);
600 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
601 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
602 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
603 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
604 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
605 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
606 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
607 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
609 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
610 /* TODO: For now, do not support VMDq/RFS on VFs. */
615 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
619 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
621 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
622 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
623 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
624 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
626 bnxt_hwrm_ptp_qcfg(bp);
630 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
631 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
638 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
642 rc = __bnxt_hwrm_func_qcaps(bp);
643 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
644 rc = bnxt_alloc_ctx_mem(bp);
648 rc = bnxt_hwrm_func_resc_qcaps(bp);
650 bp->flags |= BNXT_FLAG_NEW_RM;
656 int bnxt_hwrm_func_reset(struct bnxt *bp)
659 struct hwrm_func_reset_input req = {.req_type = 0 };
660 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
662 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
664 req.enables = rte_cpu_to_le_32(0);
666 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
674 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
678 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
679 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
681 if (bp->flags & BNXT_FLAG_REGISTERED)
684 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
686 /* PFs and trusted VFs should indicate the support of the
687 * Master capability on non Stingray platform
689 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
690 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
692 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
693 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
694 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
695 req.ver_maj = RTE_VER_YEAR;
696 req.ver_min = RTE_VER_MONTH;
697 req.ver_upd = RTE_VER_MINOR;
700 req.enables |= rte_cpu_to_le_32(
701 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
702 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
703 RTE_MIN(sizeof(req.vf_req_fwd),
704 sizeof(bp->pf.vf_req_fwd)));
707 * PF can sniff HWRM API issued by VF. This can be set up by
708 * linux driver and inherited by the DPDK PF driver. Clear
709 * this HWRM sniffer list in FW because DPDK PF driver does
712 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
715 req.flags = rte_cpu_to_le_32(flags);
717 req.async_event_fwd[0] |=
718 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
719 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
720 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
721 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
722 req.async_event_fwd[1] |=
723 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
724 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
726 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
730 flags = rte_le_to_cpu_32(resp->flags);
731 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
732 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
736 bp->flags |= BNXT_FLAG_REGISTERED;
741 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
743 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
746 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
749 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
754 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
755 struct hwrm_func_vf_cfg_input req = {0};
757 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
759 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
760 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
761 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
762 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
763 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
765 if (BNXT_HAS_RING_GRPS(bp)) {
766 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
767 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
770 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
771 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
772 AGG_RING_MULTIPLIER);
773 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
775 BNXT_NUM_ASYNC_CPR(bp));
776 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
778 BNXT_NUM_ASYNC_CPR(bp));
779 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
780 if (bp->vf_resv_strategy ==
781 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
782 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
783 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
784 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
785 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
786 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
787 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
791 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
792 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
793 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
794 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
795 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
796 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
798 if (test && BNXT_HAS_RING_GRPS(bp))
799 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
801 req.flags = rte_cpu_to_le_32(flags);
802 req.enables |= rte_cpu_to_le_32(enables);
804 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
807 HWRM_CHECK_RESULT_SILENT();
815 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
818 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
819 struct hwrm_func_resource_qcaps_input req = {0};
821 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
822 req.fid = rte_cpu_to_le_16(0xffff);
824 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
829 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
830 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
831 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
832 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
833 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
834 /* func_resource_qcaps does not return max_rx_em_flows.
835 * So use the value provided by func_qcaps.
838 rte_le_to_cpu_16(resp->max_l2_ctxs) +
840 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
841 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
843 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
844 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
845 if (bp->vf_resv_strategy >
846 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
847 bp->vf_resv_strategy =
848 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
854 int bnxt_hwrm_ver_get(struct bnxt *bp)
857 struct hwrm_ver_get_input req = {.req_type = 0 };
858 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
860 uint16_t max_resp_len;
861 char type[RTE_MEMZONE_NAMESIZE];
862 uint32_t dev_caps_cfg;
864 bp->max_req_len = HWRM_MAX_REQ_LEN;
865 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
867 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
868 req.hwrm_intf_min = HWRM_VERSION_MINOR;
869 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
871 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
873 if (bp->flags & BNXT_FLAG_FW_RESET)
874 HWRM_CHECK_RESULT_SILENT();
878 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
879 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
880 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
881 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
882 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
883 (resp->hwrm_fw_min_8b << 16) |
884 (resp->hwrm_fw_bld_8b << 8) |
885 resp->hwrm_fw_rsvd_8b;
886 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
887 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
889 fw_version = resp->hwrm_intf_maj_8b << 16;
890 fw_version |= resp->hwrm_intf_min_8b << 8;
891 fw_version |= resp->hwrm_intf_upd_8b;
892 bp->hwrm_spec_code = fw_version;
894 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
895 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
900 if (bp->max_req_len > resp->max_req_win_len) {
901 PMD_DRV_LOG(ERR, "Unsupported request length\n");
904 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
905 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
906 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
907 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
909 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
910 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
912 if (bp->max_resp_len != max_resp_len) {
913 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
914 bp->pdev->addr.domain, bp->pdev->addr.bus,
915 bp->pdev->addr.devid, bp->pdev->addr.function);
917 rte_free(bp->hwrm_cmd_resp_addr);
919 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
920 if (bp->hwrm_cmd_resp_addr == NULL) {
924 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
925 bp->hwrm_cmd_resp_dma_addr =
926 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
927 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
929 "Unable to map response buffer to physical memory.\n");
933 bp->max_resp_len = max_resp_len;
937 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
939 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
940 PMD_DRV_LOG(DEBUG, "Short command supported\n");
941 bp->flags |= BNXT_FLAG_SHORT_CMD;
945 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
947 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
948 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
949 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
950 bp->pdev->addr.domain, bp->pdev->addr.bus,
951 bp->pdev->addr.devid, bp->pdev->addr.function);
953 rte_free(bp->hwrm_short_cmd_req_addr);
955 bp->hwrm_short_cmd_req_addr =
956 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
957 if (bp->hwrm_short_cmd_req_addr == NULL) {
961 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
962 bp->hwrm_short_cmd_req_dma_addr =
963 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
964 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
965 rte_free(bp->hwrm_short_cmd_req_addr);
967 "Unable to map buffer to physical memory.\n");
973 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
974 bp->flags |= BNXT_FLAG_KONG_MB_EN;
975 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
978 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
979 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
986 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
989 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
990 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
992 if (!(bp->flags & BNXT_FLAG_REGISTERED))
995 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
998 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1000 HWRM_CHECK_RESULT();
1006 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1009 struct hwrm_port_phy_cfg_input req = {0};
1010 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1011 uint32_t enables = 0;
1013 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1015 if (conf->link_up) {
1016 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1017 if (bp->link_info.auto_mode && conf->link_speed) {
1018 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1019 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1022 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1023 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1024 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1026 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1027 * any auto mode, even "none".
1029 if (!conf->link_speed) {
1030 /* No speeds specified. Enable AutoNeg - all speeds */
1032 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1034 /* AutoNeg - Advertise speeds specified. */
1035 if (conf->auto_link_speed_mask &&
1036 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1038 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1039 req.auto_link_speed_mask =
1040 conf->auto_link_speed_mask;
1042 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1045 req.auto_duplex = conf->duplex;
1046 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1047 req.auto_pause = conf->auto_pause;
1048 req.force_pause = conf->force_pause;
1049 /* Set force_pause if there is no auto or if there is a force */
1050 if (req.auto_pause && !req.force_pause)
1051 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1053 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1055 req.enables = rte_cpu_to_le_32(enables);
1058 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1059 PMD_DRV_LOG(INFO, "Force Link Down\n");
1062 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1064 HWRM_CHECK_RESULT();
1070 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1071 struct bnxt_link_info *link_info)
1074 struct hwrm_port_phy_qcfg_input req = {0};
1075 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1077 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1079 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1081 HWRM_CHECK_RESULT();
1083 link_info->phy_link_status = resp->link;
1084 link_info->link_up =
1085 (link_info->phy_link_status ==
1086 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1087 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1088 link_info->duplex = resp->duplex_cfg;
1089 link_info->pause = resp->pause;
1090 link_info->auto_pause = resp->auto_pause;
1091 link_info->force_pause = resp->force_pause;
1092 link_info->auto_mode = resp->auto_mode;
1093 link_info->phy_type = resp->phy_type;
1094 link_info->media_type = resp->media_type;
1096 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1097 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1098 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1099 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1100 link_info->phy_ver[0] = resp->phy_maj;
1101 link_info->phy_ver[1] = resp->phy_min;
1102 link_info->phy_ver[2] = resp->phy_bld;
1106 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1107 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1108 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1109 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1110 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1111 link_info->auto_link_speed_mask);
1112 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1113 link_info->force_link_speed);
1118 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1121 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1122 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1125 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1127 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1128 /* HWRM Version >= 1.9.1 */
1129 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1131 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1132 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1134 HWRM_CHECK_RESULT();
1136 #define GET_QUEUE_INFO(x) \
1137 bp->cos_queue[x].id = resp->queue_id##x; \
1138 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1151 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1152 bp->tx_cosq_id = bp->cos_queue[0].id;
1154 /* iterate and find the COSq profile to use for Tx */
1155 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1156 if (bp->cos_queue[i].profile ==
1157 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1158 bp->tx_cosq_id = bp->cos_queue[i].id;
1164 bp->max_tc = resp->max_configurable_queues;
1165 bp->max_lltc = resp->max_configurable_lossless_queues;
1166 if (bp->max_tc > BNXT_MAX_QUEUE)
1167 bp->max_tc = BNXT_MAX_QUEUE;
1168 bp->max_q = bp->max_tc;
1170 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1175 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1176 struct bnxt_ring *ring,
1177 uint32_t ring_type, uint32_t map_index,
1178 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1181 uint32_t enables = 0;
1182 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1183 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1184 struct rte_mempool *mb_pool;
1185 uint16_t rx_buf_size;
1187 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1189 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1190 req.fbo = rte_cpu_to_le_32(0);
1191 /* Association of ring index with doorbell index */
1192 req.logical_id = rte_cpu_to_le_16(map_index);
1193 req.length = rte_cpu_to_le_32(ring->ring_size);
1195 switch (ring_type) {
1196 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1197 req.ring_type = ring_type;
1198 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1199 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1200 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1201 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1203 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1205 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1206 req.ring_type = ring_type;
1207 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1208 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1209 if (BNXT_CHIP_THOR(bp)) {
1210 mb_pool = bp->rx_queues[0]->mb_pool;
1211 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1212 RTE_PKTMBUF_HEADROOM;
1213 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1215 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1217 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1219 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1221 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1222 req.ring_type = ring_type;
1223 if (BNXT_HAS_NQ(bp)) {
1224 /* Association of cp ring with nq */
1225 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1227 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1229 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1231 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1232 req.ring_type = ring_type;
1233 req.page_size = BNXT_PAGE_SHFT;
1234 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1236 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1237 req.ring_type = ring_type;
1238 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1240 mb_pool = bp->rx_queues[0]->mb_pool;
1241 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1242 RTE_PKTMBUF_HEADROOM;
1243 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1245 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1246 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1247 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1248 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1251 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1256 req.enables = rte_cpu_to_le_32(enables);
1258 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1260 if (rc || resp->error_code) {
1261 if (rc == 0 && resp->error_code)
1262 rc = rte_le_to_cpu_16(resp->error_code);
1263 switch (ring_type) {
1264 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1266 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1269 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1271 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1274 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1276 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1280 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1282 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1285 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1287 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1291 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1297 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1302 int bnxt_hwrm_ring_free(struct bnxt *bp,
1303 struct bnxt_ring *ring, uint32_t ring_type)
1306 struct hwrm_ring_free_input req = {.req_type = 0 };
1307 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1309 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1311 req.ring_type = ring_type;
1312 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1314 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1316 if (rc || resp->error_code) {
1317 if (rc == 0 && resp->error_code)
1318 rc = rte_le_to_cpu_16(resp->error_code);
1321 switch (ring_type) {
1322 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1323 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1326 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1327 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1330 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1331 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1334 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1336 "hwrm_ring_free nq failed. rc:%d\n", rc);
1338 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1340 "hwrm_ring_free agg failed. rc:%d\n", rc);
1343 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1351 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1354 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1355 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1357 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1359 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1360 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1361 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1362 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1364 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1366 HWRM_CHECK_RESULT();
1368 bp->grp_info[idx].fw_grp_id =
1369 rte_le_to_cpu_16(resp->ring_group_id);
1376 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1379 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1380 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1382 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1384 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1386 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1388 HWRM_CHECK_RESULT();
1391 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1395 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1398 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1399 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1401 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1404 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1406 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1408 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1410 HWRM_CHECK_RESULT();
1416 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1417 unsigned int idx __rte_unused)
1420 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1421 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1423 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1425 req.update_period_ms = rte_cpu_to_le_32(0);
1427 req.stats_dma_addr =
1428 rte_cpu_to_le_64(cpr->hw_stats_map);
1430 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1432 HWRM_CHECK_RESULT();
1434 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1441 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1442 unsigned int idx __rte_unused)
1445 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1446 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1448 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1450 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1452 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1454 HWRM_CHECK_RESULT();
1460 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1463 struct hwrm_vnic_alloc_input req = { 0 };
1464 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1466 if (!BNXT_HAS_RING_GRPS(bp))
1467 goto skip_ring_grps;
1469 /* map ring groups to this vnic */
1470 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1471 vnic->start_grp_id, vnic->end_grp_id);
1472 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1473 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1475 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1476 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1477 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1478 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1481 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1482 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1483 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1485 if (vnic->func_default)
1487 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1488 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1490 HWRM_CHECK_RESULT();
1492 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1494 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1498 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1499 struct bnxt_vnic_info *vnic,
1500 struct bnxt_plcmodes_cfg *pmode)
1503 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1504 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1506 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1508 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1510 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1512 HWRM_CHECK_RESULT();
1514 pmode->flags = rte_le_to_cpu_32(resp->flags);
1515 /* dflt_vnic bit doesn't exist in the _cfg command */
1516 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1517 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1518 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1519 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1526 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1527 struct bnxt_vnic_info *vnic,
1528 struct bnxt_plcmodes_cfg *pmode)
1531 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1532 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1534 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1535 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1539 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1541 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1542 req.flags = rte_cpu_to_le_32(pmode->flags);
1543 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1544 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1545 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1546 req.enables = rte_cpu_to_le_32(
1547 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1548 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1549 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1552 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1554 HWRM_CHECK_RESULT();
1560 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1563 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1564 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1565 struct bnxt_plcmodes_cfg pmodes = { 0 };
1566 uint32_t ctx_enable_flag = 0;
1567 uint32_t enables = 0;
1569 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1570 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1574 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1578 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1580 if (BNXT_CHIP_THOR(bp)) {
1581 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1582 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1583 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1585 req.default_rx_ring_id =
1586 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1587 req.default_cmpl_ring_id =
1588 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1589 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1590 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1594 /* Only RSS support for now TBD: COS & LB */
1595 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1596 if (vnic->lb_rule != 0xffff)
1597 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1598 if (vnic->cos_rule != 0xffff)
1599 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1600 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1601 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1602 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1604 enables |= ctx_enable_flag;
1605 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1606 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1607 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1608 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1611 req.enables = rte_cpu_to_le_32(enables);
1612 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1613 req.mru = rte_cpu_to_le_16(vnic->mru);
1614 /* Configure default VNIC only once. */
1615 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1617 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1618 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1620 if (vnic->vlan_strip)
1622 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1625 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1626 if (vnic->roce_dual)
1627 req.flags |= rte_cpu_to_le_32(
1628 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1629 if (vnic->roce_only)
1630 req.flags |= rte_cpu_to_le_32(
1631 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1632 if (vnic->rss_dflt_cr)
1633 req.flags |= rte_cpu_to_le_32(
1634 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1636 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1638 HWRM_CHECK_RESULT();
1641 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1646 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1650 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1651 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1653 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1654 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1657 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1660 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1661 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1662 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1664 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1666 HWRM_CHECK_RESULT();
1668 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1669 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1670 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1671 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1672 vnic->mru = rte_le_to_cpu_16(resp->mru);
1673 vnic->func_default = rte_le_to_cpu_32(
1674 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1675 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1676 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1677 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1678 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1679 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1680 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1681 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1682 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1683 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1684 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1691 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1692 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1696 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1697 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1698 bp->hwrm_cmd_resp_addr;
1700 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1702 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1703 HWRM_CHECK_RESULT();
1705 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1706 if (!BNXT_HAS_RING_GRPS(bp))
1707 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1708 else if (ctx_idx == 0)
1709 vnic->rss_rule = ctx_id;
1716 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1717 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1720 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1721 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1722 bp->hwrm_cmd_resp_addr;
1724 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1725 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1728 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1730 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1732 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1734 HWRM_CHECK_RESULT();
1740 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1743 struct hwrm_vnic_free_input req = {.req_type = 0 };
1744 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1746 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1747 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1751 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1753 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1755 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1757 HWRM_CHECK_RESULT();
1760 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1761 /* Configure default VNIC again if necessary. */
1762 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1763 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1769 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1773 int nr_ctxs = vnic->num_lb_ctxts;
1774 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1775 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1777 for (i = 0; i < nr_ctxs; i++) {
1778 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1780 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1781 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1782 req.hash_mode_flags = vnic->hash_mode;
1784 req.hash_key_tbl_addr =
1785 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1787 req.ring_grp_tbl_addr =
1788 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1789 i * HW_HASH_INDEX_SIZE);
1790 req.ring_table_pair_index = i;
1791 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1793 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1796 HWRM_CHECK_RESULT();
1803 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1804 struct bnxt_vnic_info *vnic)
1807 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1808 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1810 if (!vnic->rss_table)
1813 if (BNXT_CHIP_THOR(bp))
1814 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1816 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1818 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1819 req.hash_mode_flags = vnic->hash_mode;
1821 req.ring_grp_tbl_addr =
1822 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1823 req.hash_key_tbl_addr =
1824 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1825 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1826 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1828 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1830 HWRM_CHECK_RESULT();
1836 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1837 struct bnxt_vnic_info *vnic)
1840 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1841 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1844 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1845 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1849 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1851 req.flags = rte_cpu_to_le_32(
1852 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1854 req.enables = rte_cpu_to_le_32(
1855 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1857 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1858 size -= RTE_PKTMBUF_HEADROOM;
1860 req.jumbo_thresh = rte_cpu_to_le_16(size);
1861 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1863 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1865 HWRM_CHECK_RESULT();
1871 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1872 struct bnxt_vnic_info *vnic, bool enable)
1875 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1876 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1878 if (BNXT_CHIP_THOR(bp))
1881 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1884 req.enables = rte_cpu_to_le_32(
1885 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1886 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1887 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1888 req.flags = rte_cpu_to_le_32(
1889 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1890 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1891 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1892 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1893 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1894 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1895 req.max_agg_segs = rte_cpu_to_le_16(5);
1897 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1898 req.min_agg_len = rte_cpu_to_le_32(512);
1900 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1902 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1904 HWRM_CHECK_RESULT();
1910 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1912 struct hwrm_func_cfg_input req = {0};
1913 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1916 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1917 req.enables = rte_cpu_to_le_32(
1918 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1919 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1920 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1922 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1924 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1925 HWRM_CHECK_RESULT();
1928 bp->pf.vf_info[vf].random_mac = false;
1933 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1937 struct hwrm_func_qstats_input req = {.req_type = 0};
1938 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1940 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1942 req.fid = rte_cpu_to_le_16(fid);
1944 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1946 HWRM_CHECK_RESULT();
1949 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1956 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1957 struct rte_eth_stats *stats)
1960 struct hwrm_func_qstats_input req = {.req_type = 0};
1961 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1963 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1965 req.fid = rte_cpu_to_le_16(fid);
1967 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1969 HWRM_CHECK_RESULT();
1971 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1972 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1973 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1974 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1975 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1976 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1978 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1979 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1980 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1981 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1982 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1983 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1985 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1986 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1987 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1994 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1997 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1998 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2000 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2002 req.fid = rte_cpu_to_le_16(fid);
2004 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2006 HWRM_CHECK_RESULT();
2013 * HWRM utility functions
2016 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2021 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2022 struct bnxt_tx_queue *txq;
2023 struct bnxt_rx_queue *rxq;
2024 struct bnxt_cp_ring_info *cpr;
2026 if (i >= bp->rx_cp_nr_rings) {
2027 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2030 rxq = bp->rx_queues[i];
2034 rc = bnxt_hwrm_stat_clear(bp, cpr);
2041 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2045 struct bnxt_cp_ring_info *cpr;
2047 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2049 if (i >= bp->rx_cp_nr_rings) {
2050 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2052 cpr = bp->rx_queues[i]->cp_ring;
2053 if (BNXT_HAS_RING_GRPS(bp))
2054 bp->grp_info[i].fw_stats_ctx = -1;
2056 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2057 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2058 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2066 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2071 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2072 struct bnxt_tx_queue *txq;
2073 struct bnxt_rx_queue *rxq;
2074 struct bnxt_cp_ring_info *cpr;
2076 if (i >= bp->rx_cp_nr_rings) {
2077 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2080 rxq = bp->rx_queues[i];
2084 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2092 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2097 if (!BNXT_HAS_RING_GRPS(bp))
2100 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2102 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2105 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2113 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2115 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2117 bnxt_hwrm_ring_free(bp, cp_ring,
2118 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2119 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2120 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2121 sizeof(*cpr->cp_desc_ring));
2122 cpr->cp_raw_cons = 0;
2126 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2128 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2130 bnxt_hwrm_ring_free(bp, cp_ring,
2131 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2132 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2133 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2134 sizeof(*cpr->cp_desc_ring));
2135 cpr->cp_raw_cons = 0;
2139 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2141 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2142 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2143 struct bnxt_ring *ring = rxr->rx_ring_struct;
2144 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2146 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2147 bnxt_hwrm_ring_free(bp, ring,
2148 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2149 ring->fw_ring_id = INVALID_HW_RING_ID;
2150 if (BNXT_HAS_RING_GRPS(bp))
2151 bp->grp_info[queue_index].rx_fw_ring_id =
2153 memset(rxr->rx_desc_ring, 0,
2154 rxr->rx_ring_struct->ring_size *
2155 sizeof(*rxr->rx_desc_ring));
2156 memset(rxr->rx_buf_ring, 0,
2157 rxr->rx_ring_struct->ring_size *
2158 sizeof(*rxr->rx_buf_ring));
2161 ring = rxr->ag_ring_struct;
2162 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2163 bnxt_hwrm_ring_free(bp, ring,
2164 BNXT_CHIP_THOR(bp) ?
2165 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2166 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2167 ring->fw_ring_id = INVALID_HW_RING_ID;
2168 memset(rxr->ag_buf_ring, 0,
2169 rxr->ag_ring_struct->ring_size *
2170 sizeof(*rxr->ag_buf_ring));
2172 if (BNXT_HAS_RING_GRPS(bp))
2173 bp->grp_info[queue_index].ag_fw_ring_id =
2176 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2177 bnxt_free_cp_ring(bp, cpr);
2179 bnxt_free_nq_ring(bp, rxq->nq_ring);
2182 if (BNXT_HAS_RING_GRPS(bp))
2183 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2186 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2190 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2191 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2192 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2193 struct bnxt_ring *ring = txr->tx_ring_struct;
2194 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2196 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2197 bnxt_hwrm_ring_free(bp, ring,
2198 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2199 ring->fw_ring_id = INVALID_HW_RING_ID;
2200 memset(txr->tx_desc_ring, 0,
2201 txr->tx_ring_struct->ring_size *
2202 sizeof(*txr->tx_desc_ring));
2203 memset(txr->tx_buf_ring, 0,
2204 txr->tx_ring_struct->ring_size *
2205 sizeof(*txr->tx_buf_ring));
2209 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2210 bnxt_free_cp_ring(bp, cpr);
2211 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2213 bnxt_free_nq_ring(bp, txq->nq_ring);
2217 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2218 bnxt_free_hwrm_rx_ring(bp, i);
2223 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2228 if (!BNXT_HAS_RING_GRPS(bp))
2231 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2232 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2239 void bnxt_free_hwrm_resources(struct bnxt *bp)
2241 /* Release memzone */
2242 rte_free(bp->hwrm_cmd_resp_addr);
2243 rte_free(bp->hwrm_short_cmd_req_addr);
2244 bp->hwrm_cmd_resp_addr = NULL;
2245 bp->hwrm_short_cmd_req_addr = NULL;
2246 bp->hwrm_cmd_resp_dma_addr = 0;
2247 bp->hwrm_short_cmd_req_dma_addr = 0;
2250 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2252 struct rte_pci_device *pdev = bp->pdev;
2253 char type[RTE_MEMZONE_NAMESIZE];
2255 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2256 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2257 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2258 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2259 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2260 if (bp->hwrm_cmd_resp_addr == NULL)
2262 bp->hwrm_cmd_resp_dma_addr =
2263 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2264 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2266 "unable to map response address to physical memory\n");
2269 rte_spinlock_init(&bp->hwrm_lock);
2274 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2276 struct bnxt_filter_info *filter;
2279 STAILQ_FOREACH(filter, &vnic->filter, next) {
2280 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2281 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2282 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2283 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2285 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2286 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2294 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2296 struct bnxt_filter_info *filter;
2297 struct rte_flow *flow;
2300 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2301 filter = flow->filter;
2302 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2303 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2304 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2305 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2306 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2308 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2310 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2318 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2320 struct bnxt_filter_info *filter;
2323 STAILQ_FOREACH(filter, &vnic->filter, next) {
2324 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2325 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2327 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2328 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2331 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2339 void bnxt_free_tunnel_ports(struct bnxt *bp)
2341 if (bp->vxlan_port_cnt)
2342 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2343 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2345 if (bp->geneve_port_cnt)
2346 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2347 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2348 bp->geneve_port = 0;
2351 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2355 if (bp->vnic_info == NULL)
2359 * Cleanup VNICs in reverse order, to make sure the L2 filter
2360 * from vnic0 is last to be cleaned up.
2362 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2363 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2365 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2366 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2370 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2372 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2374 if (BNXT_CHIP_THOR(bp)) {
2375 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2376 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2377 vnic->fw_grp_ids[j]);
2378 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2380 vnic->num_lb_ctxts = 0;
2382 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2383 vnic->rss_rule = INVALID_HW_RING_ID;
2386 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2388 bnxt_hwrm_vnic_free(bp, vnic);
2390 rte_free(vnic->fw_grp_ids);
2392 /* Ring resources */
2393 bnxt_free_all_hwrm_rings(bp);
2394 bnxt_free_all_hwrm_ring_grps(bp);
2395 bnxt_free_all_hwrm_stat_ctxs(bp);
2396 bnxt_free_tunnel_ports(bp);
2399 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2401 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2403 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2404 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2406 switch (conf_link_speed) {
2407 case ETH_LINK_SPEED_10M_HD:
2408 case ETH_LINK_SPEED_100M_HD:
2410 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2412 return hw_link_duplex;
2415 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2417 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2420 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2422 uint16_t eth_link_speed = 0;
2424 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2425 return ETH_LINK_SPEED_AUTONEG;
2427 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2428 case ETH_LINK_SPEED_100M:
2429 case ETH_LINK_SPEED_100M_HD:
2432 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2434 case ETH_LINK_SPEED_1G:
2436 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2438 case ETH_LINK_SPEED_2_5G:
2440 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2442 case ETH_LINK_SPEED_10G:
2444 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2446 case ETH_LINK_SPEED_20G:
2448 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2450 case ETH_LINK_SPEED_25G:
2452 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2454 case ETH_LINK_SPEED_40G:
2456 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2458 case ETH_LINK_SPEED_50G:
2460 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2462 case ETH_LINK_SPEED_100G:
2464 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2468 "Unsupported link speed %d; default to AUTO\n",
2472 return eth_link_speed;
2475 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2476 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2477 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2478 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2480 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2484 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2487 if (link_speed & ETH_LINK_SPEED_FIXED) {
2488 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2490 if (one_speed & (one_speed - 1)) {
2492 "Invalid advertised speeds (%u) for port %u\n",
2493 link_speed, port_id);
2496 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2498 "Unsupported advertised speed (%u) for port %u\n",
2499 link_speed, port_id);
2503 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2505 "Unsupported advertised speeds (%u) for port %u\n",
2506 link_speed, port_id);
2514 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2518 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2519 if (bp->link_info.support_speeds)
2520 return bp->link_info.support_speeds;
2521 link_speed = BNXT_SUPPORTED_SPEEDS;
2524 if (link_speed & ETH_LINK_SPEED_100M)
2525 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2526 if (link_speed & ETH_LINK_SPEED_100M_HD)
2527 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2528 if (link_speed & ETH_LINK_SPEED_1G)
2529 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2530 if (link_speed & ETH_LINK_SPEED_2_5G)
2531 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2532 if (link_speed & ETH_LINK_SPEED_10G)
2533 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2534 if (link_speed & ETH_LINK_SPEED_20G)
2535 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2536 if (link_speed & ETH_LINK_SPEED_25G)
2537 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2538 if (link_speed & ETH_LINK_SPEED_40G)
2539 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2540 if (link_speed & ETH_LINK_SPEED_50G)
2541 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2542 if (link_speed & ETH_LINK_SPEED_100G)
2543 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2547 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2549 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2551 switch (hw_link_speed) {
2552 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2553 eth_link_speed = ETH_SPEED_NUM_100M;
2555 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2556 eth_link_speed = ETH_SPEED_NUM_1G;
2558 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2559 eth_link_speed = ETH_SPEED_NUM_2_5G;
2561 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2562 eth_link_speed = ETH_SPEED_NUM_10G;
2564 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2565 eth_link_speed = ETH_SPEED_NUM_20G;
2567 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2568 eth_link_speed = ETH_SPEED_NUM_25G;
2570 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2571 eth_link_speed = ETH_SPEED_NUM_40G;
2573 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2574 eth_link_speed = ETH_SPEED_NUM_50G;
2576 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2577 eth_link_speed = ETH_SPEED_NUM_100G;
2579 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2581 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2585 return eth_link_speed;
2588 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2590 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2592 switch (hw_link_duplex) {
2593 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2594 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2596 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2598 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2599 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2602 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2606 return eth_link_duplex;
2609 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2612 struct bnxt_link_info *link_info = &bp->link_info;
2614 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2617 "Get link config failed with rc %d\n", rc);
2620 if (link_info->link_speed)
2622 bnxt_parse_hw_link_speed(link_info->link_speed);
2624 link->link_speed = ETH_SPEED_NUM_NONE;
2625 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2626 link->link_status = link_info->link_up;
2627 link->link_autoneg = link_info->auto_mode ==
2628 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2629 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2634 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2637 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2638 struct bnxt_link_info link_req;
2639 uint16_t speed, autoneg;
2641 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2644 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2645 bp->eth_dev->data->port_id);
2649 memset(&link_req, 0, sizeof(link_req));
2650 link_req.link_up = link_up;
2654 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2655 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2656 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2657 /* Autoneg can be done only when the FW allows */
2658 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2659 bp->link_info.force_link_speed)) {
2660 link_req.phy_flags |=
2661 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2662 link_req.auto_link_speed_mask =
2663 bnxt_parse_eth_link_speed_mask(bp,
2664 dev_conf->link_speeds);
2666 if (bp->link_info.phy_type ==
2667 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2668 bp->link_info.phy_type ==
2669 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2670 bp->link_info.media_type ==
2671 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2672 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2676 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2677 /* If user wants a particular speed try that first. */
2679 link_req.link_speed = speed;
2680 else if (bp->link_info.force_link_speed)
2681 link_req.link_speed = bp->link_info.force_link_speed;
2683 link_req.link_speed = bp->link_info.auto_link_speed;
2685 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2686 link_req.auto_pause = bp->link_info.auto_pause;
2687 link_req.force_pause = bp->link_info.force_pause;
2690 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2693 "Set link config failed with rc %d\n", rc);
2701 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2703 struct hwrm_func_qcfg_input req = {0};
2704 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2708 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2709 req.fid = rte_cpu_to_le_16(0xffff);
2711 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2713 HWRM_CHECK_RESULT();
2715 /* Hard Coded.. 0xfff VLAN ID mask */
2716 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2717 flags = rte_le_to_cpu_16(resp->flags);
2718 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2719 bp->flags |= BNXT_FLAG_MULTI_HOST;
2721 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2722 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2723 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2724 } else if (BNXT_VF(bp) &&
2725 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2726 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2727 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2733 switch (resp->port_partition_type) {
2734 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2735 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2736 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2738 bp->port_partition_type = resp->port_partition_type;
2741 bp->port_partition_type = 0;
2750 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2751 struct hwrm_func_qcaps_output *qcaps)
2753 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2754 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2755 sizeof(qcaps->mac_address));
2756 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2757 qcaps->max_rx_rings = fcfg->num_rx_rings;
2758 qcaps->max_tx_rings = fcfg->num_tx_rings;
2759 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2760 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2762 qcaps->first_vf_id = 0;
2763 qcaps->max_vnics = fcfg->num_vnics;
2764 qcaps->max_decap_records = 0;
2765 qcaps->max_encap_records = 0;
2766 qcaps->max_tx_wm_flows = 0;
2767 qcaps->max_tx_em_flows = 0;
2768 qcaps->max_rx_wm_flows = 0;
2769 qcaps->max_rx_em_flows = 0;
2770 qcaps->max_flow_id = 0;
2771 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2772 qcaps->max_sp_tx_rings = 0;
2773 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2776 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2778 struct hwrm_func_cfg_input req = {0};
2779 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2783 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2784 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2785 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2786 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2787 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2788 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2789 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2790 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2791 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2793 if (BNXT_HAS_RING_GRPS(bp)) {
2794 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2795 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2796 } else if (BNXT_HAS_NQ(bp)) {
2797 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2798 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2801 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2802 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2803 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2804 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2806 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2807 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2808 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2809 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2810 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2811 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2812 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2813 req.fid = rte_cpu_to_le_16(0xffff);
2814 req.enables = rte_cpu_to_le_32(enables);
2816 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2818 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2820 HWRM_CHECK_RESULT();
2826 static void populate_vf_func_cfg_req(struct bnxt *bp,
2827 struct hwrm_func_cfg_input *req,
2830 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2831 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2832 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2833 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2834 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2835 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2836 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2837 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2838 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2839 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2841 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2842 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2844 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2845 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2847 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2849 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2850 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2852 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2853 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2854 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2855 /* TODO: For now, do not support VMDq/RFS on VFs. */
2856 req->num_vnics = rte_cpu_to_le_16(1);
2857 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2861 static void add_random_mac_if_needed(struct bnxt *bp,
2862 struct hwrm_func_cfg_input *cfg_req,
2865 struct rte_ether_addr mac;
2867 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2870 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2872 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2873 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2874 bp->pf.vf_info[vf].random_mac = true;
2876 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2877 RTE_ETHER_ADDR_LEN);
2881 static void reserve_resources_from_vf(struct bnxt *bp,
2882 struct hwrm_func_cfg_input *cfg_req,
2885 struct hwrm_func_qcaps_input req = {0};
2886 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2889 /* Get the actual allocated values now */
2890 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2891 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2892 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2895 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2896 copy_func_cfg_to_qcaps(cfg_req, resp);
2897 } else if (resp->error_code) {
2898 rc = rte_le_to_cpu_16(resp->error_code);
2899 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2900 copy_func_cfg_to_qcaps(cfg_req, resp);
2903 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2904 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2905 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2906 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2907 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2908 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2910 * TODO: While not supporting VMDq with VFs, max_vnics is always
2911 * forced to 1 in this case
2913 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2914 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2919 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2921 struct hwrm_func_qcfg_input req = {0};
2922 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2925 /* Check for zero MAC address */
2926 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2927 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2928 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2929 HWRM_CHECK_RESULT();
2930 rc = rte_le_to_cpu_16(resp->vlan);
2937 static int update_pf_resource_max(struct bnxt *bp)
2939 struct hwrm_func_qcfg_input req = {0};
2940 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2943 /* And copy the allocated numbers into the pf struct */
2944 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2945 req.fid = rte_cpu_to_le_16(0xffff);
2946 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2947 HWRM_CHECK_RESULT();
2949 /* Only TX ring value reflects actual allocation? TODO */
2950 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2951 bp->pf.evb_mode = resp->evb_mode;
2958 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2963 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2967 rc = bnxt_hwrm_func_qcaps(bp);
2971 bp->pf.func_cfg_flags &=
2972 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2973 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2974 bp->pf.func_cfg_flags |=
2975 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2976 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2977 rc = __bnxt_hwrm_func_qcaps(bp);
2981 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2983 struct hwrm_func_cfg_input req = {0};
2984 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2991 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2995 rc = bnxt_hwrm_func_qcaps(bp);
3000 bp->pf.active_vfs = num_vfs;
3003 * First, configure the PF to only use one TX ring. This ensures that
3004 * there are enough rings for all VFs.
3006 * If we don't do this, when we call func_alloc() later, we will lock
3007 * extra rings to the PF that won't be available during func_cfg() of
3010 * This has been fixed with firmware versions above 20.6.54
3012 bp->pf.func_cfg_flags &=
3013 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3014 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3015 bp->pf.func_cfg_flags |=
3016 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3017 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3022 * Now, create and register a buffer to hold forwarded VF requests
3024 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3025 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3026 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3027 if (bp->pf.vf_req_buf == NULL) {
3031 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3032 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3033 for (i = 0; i < num_vfs; i++)
3034 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3035 (i * HWRM_MAX_REQ_LEN);
3037 rc = bnxt_hwrm_func_buf_rgtr(bp);
3041 populate_vf_func_cfg_req(bp, &req, num_vfs);
3043 bp->pf.active_vfs = 0;
3044 for (i = 0; i < num_vfs; i++) {
3045 add_random_mac_if_needed(bp, &req, i);
3047 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3048 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3049 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3050 rc = bnxt_hwrm_send_message(bp,
3055 /* Clear enable flag for next pass */
3056 req.enables &= ~rte_cpu_to_le_32(
3057 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3059 if (rc || resp->error_code) {
3061 "Failed to initizlie VF %d\n", i);
3063 "Not all VFs available. (%d, %d)\n",
3064 rc, resp->error_code);
3071 reserve_resources_from_vf(bp, &req, i);
3072 bp->pf.active_vfs++;
3073 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3077 * Now configure the PF to use "the rest" of the resources
3078 * We're using STD_TX_RING_MODE here though which will limit the TX
3079 * rings. This will allow QoS to function properly. Not setting this
3080 * will cause PF rings to break bandwidth settings.
3082 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3086 rc = update_pf_resource_max(bp);
3093 bnxt_hwrm_func_buf_unrgtr(bp);
3097 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3099 struct hwrm_func_cfg_input req = {0};
3100 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3103 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3105 req.fid = rte_cpu_to_le_16(0xffff);
3106 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3107 req.evb_mode = bp->pf.evb_mode;
3109 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3110 HWRM_CHECK_RESULT();
3116 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3117 uint8_t tunnel_type)
3119 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3120 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3123 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3124 req.tunnel_type = tunnel_type;
3125 req.tunnel_dst_port_val = port;
3126 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3127 HWRM_CHECK_RESULT();
3129 switch (tunnel_type) {
3130 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3131 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3132 bp->vxlan_port = port;
3134 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3135 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3136 bp->geneve_port = port;
3147 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3148 uint8_t tunnel_type)
3150 struct hwrm_tunnel_dst_port_free_input req = {0};
3151 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3154 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3156 req.tunnel_type = tunnel_type;
3157 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3158 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3160 HWRM_CHECK_RESULT();
3166 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3169 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3170 struct hwrm_func_cfg_input req = {0};
3173 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3175 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3176 req.flags = rte_cpu_to_le_32(flags);
3177 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3179 HWRM_CHECK_RESULT();
3185 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3187 uint32_t *flag = flagp;
3189 vnic->flags = *flag;
3192 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3194 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3197 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3200 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3201 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3203 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3205 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3206 req.req_buf_page_size = rte_cpu_to_le_16(
3207 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3208 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3209 req.req_buf_page_addr0 =
3210 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3211 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3213 "unable to map buffer address to physical memory\n");
3217 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3219 HWRM_CHECK_RESULT();
3225 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3228 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3229 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3231 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3234 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3236 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3238 HWRM_CHECK_RESULT();
3244 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3246 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3247 struct hwrm_func_cfg_input req = {0};
3250 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3252 req.fid = rte_cpu_to_le_16(0xffff);
3253 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3254 req.enables = rte_cpu_to_le_32(
3255 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3256 req.async_event_cr = rte_cpu_to_le_16(
3257 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3258 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3260 HWRM_CHECK_RESULT();
3266 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3268 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3269 struct hwrm_func_vf_cfg_input req = {0};
3272 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3274 req.enables = rte_cpu_to_le_32(
3275 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3276 req.async_event_cr = rte_cpu_to_le_16(
3277 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3278 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3280 HWRM_CHECK_RESULT();
3286 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3288 struct hwrm_func_cfg_input req = {0};
3289 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3290 uint16_t dflt_vlan, fid;
3291 uint32_t func_cfg_flags;
3294 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3297 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3298 fid = bp->pf.vf_info[vf].fid;
3299 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3301 fid = rte_cpu_to_le_16(0xffff);
3302 func_cfg_flags = bp->pf.func_cfg_flags;
3303 dflt_vlan = bp->vlan;
3306 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3307 req.fid = rte_cpu_to_le_16(fid);
3308 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3309 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3311 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3313 HWRM_CHECK_RESULT();
3319 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3320 uint16_t max_bw, uint16_t enables)
3322 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3323 struct hwrm_func_cfg_input req = {0};
3326 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3328 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3329 req.enables |= rte_cpu_to_le_32(enables);
3330 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3331 req.max_bw = rte_cpu_to_le_32(max_bw);
3332 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3334 HWRM_CHECK_RESULT();
3340 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3342 struct hwrm_func_cfg_input req = {0};
3343 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3346 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3348 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3349 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3350 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3351 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3353 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3355 HWRM_CHECK_RESULT();
3361 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3366 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3368 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3373 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3374 void *encaped, size_t ec_size)
3377 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3378 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3380 if (ec_size > sizeof(req.encap_request))
3383 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3385 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3386 memcpy(req.encap_request, encaped, ec_size);
3388 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3390 HWRM_CHECK_RESULT();
3396 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3397 struct rte_ether_addr *mac)
3399 struct hwrm_func_qcfg_input req = {0};
3400 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3403 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3405 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3406 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3408 HWRM_CHECK_RESULT();
3410 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3417 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3418 void *encaped, size_t ec_size)
3421 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3422 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3424 if (ec_size > sizeof(req.encap_request))
3427 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3429 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3430 memcpy(req.encap_request, encaped, ec_size);
3432 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3434 HWRM_CHECK_RESULT();
3440 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3441 struct rte_eth_stats *stats, uint8_t rx)
3444 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3445 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3447 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3449 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3451 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3453 HWRM_CHECK_RESULT();
3456 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3457 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3458 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3459 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3460 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3461 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3462 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3463 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3465 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3466 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3467 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3468 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3469 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3470 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3479 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3481 struct hwrm_port_qstats_input req = {0};
3482 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3483 struct bnxt_pf_info *pf = &bp->pf;
3486 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3488 req.port_id = rte_cpu_to_le_16(pf->port_id);
3489 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3490 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3493 HWRM_CHECK_RESULT();
3499 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3501 struct hwrm_port_clr_stats_input req = {0};
3502 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3503 struct bnxt_pf_info *pf = &bp->pf;
3506 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3507 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3508 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3511 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3513 req.port_id = rte_cpu_to_le_16(pf->port_id);
3514 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3516 HWRM_CHECK_RESULT();
3522 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3524 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3525 struct hwrm_port_led_qcaps_input req = {0};
3531 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3532 req.port_id = bp->pf.port_id;
3533 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3535 HWRM_CHECK_RESULT();
3537 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3540 bp->num_leds = resp->num_leds;
3541 memcpy(bp->leds, &resp->led0_id,
3542 sizeof(bp->leds[0]) * bp->num_leds);
3543 for (i = 0; i < bp->num_leds; i++) {
3544 struct bnxt_led_info *led = &bp->leds[i];
3546 uint16_t caps = led->led_state_caps;
3548 if (!led->led_group_id ||
3549 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3561 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3563 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3564 struct hwrm_port_led_cfg_input req = {0};
3565 struct bnxt_led_cfg *led_cfg;
3566 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3567 uint16_t duration = 0;
3570 if (!bp->num_leds || BNXT_VF(bp))
3573 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3576 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3577 duration = rte_cpu_to_le_16(500);
3579 req.port_id = bp->pf.port_id;
3580 req.num_leds = bp->num_leds;
3581 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3582 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3583 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3584 led_cfg->led_id = bp->leds[i].led_id;
3585 led_cfg->led_state = led_state;
3586 led_cfg->led_blink_on = duration;
3587 led_cfg->led_blink_off = duration;
3588 led_cfg->led_group_id = bp->leds[i].led_group_id;
3591 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3593 HWRM_CHECK_RESULT();
3599 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3603 struct hwrm_nvm_get_dir_info_input req = {0};
3604 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3606 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3608 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3610 HWRM_CHECK_RESULT();
3612 *entries = rte_le_to_cpu_32(resp->entries);
3613 *length = rte_le_to_cpu_32(resp->entry_length);
3619 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3622 uint32_t dir_entries;
3623 uint32_t entry_length;
3626 rte_iova_t dma_handle;
3627 struct hwrm_nvm_get_dir_entries_input req = {0};
3628 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3630 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3634 *data++ = dir_entries;
3635 *data++ = entry_length;
3637 memset(data, 0xff, len);
3639 buflen = dir_entries * entry_length;
3640 buf = rte_malloc("nvm_dir", buflen, 0);
3641 rte_mem_lock_page(buf);
3644 dma_handle = rte_mem_virt2iova(buf);
3645 if (dma_handle == RTE_BAD_IOVA) {
3647 "unable to map response address to physical memory\n");
3650 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3651 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3652 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3655 memcpy(data, buf, len > buflen ? buflen : len);
3658 HWRM_CHECK_RESULT();
3664 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3665 uint32_t offset, uint32_t length,
3670 rte_iova_t dma_handle;
3671 struct hwrm_nvm_read_input req = {0};
3672 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3674 buf = rte_malloc("nvm_item", length, 0);
3675 rte_mem_lock_page(buf);
3679 dma_handle = rte_mem_virt2iova(buf);
3680 if (dma_handle == RTE_BAD_IOVA) {
3682 "unable to map response address to physical memory\n");
3685 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3686 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3687 req.dir_idx = rte_cpu_to_le_16(index);
3688 req.offset = rte_cpu_to_le_32(offset);
3689 req.len = rte_cpu_to_le_32(length);
3690 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3692 memcpy(data, buf, length);
3695 HWRM_CHECK_RESULT();
3701 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3704 struct hwrm_nvm_erase_dir_entry_input req = {0};
3705 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3707 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3708 req.dir_idx = rte_cpu_to_le_16(index);
3709 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3710 HWRM_CHECK_RESULT();
3717 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3718 uint16_t dir_ordinal, uint16_t dir_ext,
3719 uint16_t dir_attr, const uint8_t *data,
3723 struct hwrm_nvm_write_input req = {0};
3724 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3725 rte_iova_t dma_handle;
3728 buf = rte_malloc("nvm_write", data_len, 0);
3729 rte_mem_lock_page(buf);
3733 dma_handle = rte_mem_virt2iova(buf);
3734 if (dma_handle == RTE_BAD_IOVA) {
3736 "unable to map response address to physical memory\n");
3739 memcpy(buf, data, data_len);
3741 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3743 req.dir_type = rte_cpu_to_le_16(dir_type);
3744 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3745 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3746 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3747 req.dir_data_length = rte_cpu_to_le_32(data_len);
3748 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3750 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3753 HWRM_CHECK_RESULT();
3760 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3762 uint32_t *count = cbdata;
3764 *count = *count + 1;
3767 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3768 struct bnxt_vnic_info *vnic __rte_unused)
3773 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3777 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3778 &count, bnxt_vnic_count_hwrm_stub);
3783 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3786 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3787 struct hwrm_func_vf_vnic_ids_query_output *resp =
3788 bp->hwrm_cmd_resp_addr;
3791 /* First query all VNIC ids */
3792 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3794 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3795 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3796 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3798 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3801 "unable to map VNIC ID table address to physical memory\n");
3804 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3805 HWRM_CHECK_RESULT();
3806 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3814 * This function queries the VNIC IDs for a specified VF. It then calls
3815 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3816 * Then it calls the hwrm_cb function to program this new vnic configuration.
3818 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3819 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3820 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3822 struct bnxt_vnic_info vnic;
3824 int i, num_vnic_ids;
3829 /* First query all VNIC ids */
3830 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3831 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3832 RTE_CACHE_LINE_SIZE);
3833 if (vnic_ids == NULL)
3836 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3837 rte_mem_lock_page(((char *)vnic_ids) + sz);
3839 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3841 if (num_vnic_ids < 0)
3842 return num_vnic_ids;
3844 /* Retrieve VNIC, update bd_stall then update */
3846 for (i = 0; i < num_vnic_ids; i++) {
3847 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3848 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3849 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3852 if (vnic.mru <= 4) /* Indicates unallocated */
3855 vnic_cb(&vnic, cbdata);
3857 rc = hwrm_cb(bp, &vnic);
3867 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3870 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3871 struct hwrm_func_cfg_input req = {0};
3874 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3876 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3877 req.enables |= rte_cpu_to_le_32(
3878 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3879 req.vlan_antispoof_mode = on ?
3880 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3881 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3882 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3884 HWRM_CHECK_RESULT();
3890 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3892 struct bnxt_vnic_info vnic;
3895 int num_vnic_ids, i;
3899 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3900 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3901 RTE_CACHE_LINE_SIZE);
3902 if (vnic_ids == NULL)
3905 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3906 rte_mem_lock_page(((char *)vnic_ids) + sz);
3908 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3914 * Loop through to find the default VNIC ID.
3915 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3916 * by sending the hwrm_func_qcfg command to the firmware.
3918 for (i = 0; i < num_vnic_ids; i++) {
3919 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3920 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3921 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3922 bp->pf.first_vf_id + vf);
3925 if (vnic.func_default) {
3927 return vnic.fw_vnic_id;
3930 /* Could not find a default VNIC. */
3931 PMD_DRV_LOG(ERR, "No default VNIC\n");
3937 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3939 struct bnxt_filter_info *filter)
3942 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3943 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3944 uint32_t enables = 0;
3946 if (filter->fw_em_filter_id != UINT64_MAX)
3947 bnxt_hwrm_clear_em_filter(bp, filter);
3949 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3951 req.flags = rte_cpu_to_le_32(filter->flags);
3953 enables = filter->enables |
3954 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3955 req.dst_id = rte_cpu_to_le_16(dst_id);
3957 if (filter->ip_addr_type) {
3958 req.ip_addr_type = filter->ip_addr_type;
3959 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3962 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3963 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3965 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3966 memcpy(req.src_macaddr, filter->src_macaddr,
3967 RTE_ETHER_ADDR_LEN);
3969 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3970 memcpy(req.dst_macaddr, filter->dst_macaddr,
3971 RTE_ETHER_ADDR_LEN);
3973 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3974 req.ovlan_vid = filter->l2_ovlan;
3976 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3977 req.ivlan_vid = filter->l2_ivlan;
3979 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3980 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3982 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3983 req.ip_protocol = filter->ip_protocol;
3985 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3986 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3988 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3989 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3991 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3992 req.src_port = rte_cpu_to_be_16(filter->src_port);
3994 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3995 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3997 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3998 req.mirror_vnic_id = filter->mirror_vnic_id;
4000 req.enables = rte_cpu_to_le_32(enables);
4002 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4004 HWRM_CHECK_RESULT();
4006 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4012 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4015 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4016 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4018 if (filter->fw_em_filter_id == UINT64_MAX)
4021 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4022 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4024 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4026 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4028 HWRM_CHECK_RESULT();
4031 filter->fw_em_filter_id = UINT64_MAX;
4032 filter->fw_l2_filter_id = UINT64_MAX;
4037 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4039 struct bnxt_filter_info *filter)
4042 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4043 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4044 bp->hwrm_cmd_resp_addr;
4045 uint32_t enables = 0;
4047 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4048 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4050 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4052 req.flags = rte_cpu_to_le_32(filter->flags);
4054 enables = filter->enables |
4055 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4056 req.dst_id = rte_cpu_to_le_16(dst_id);
4059 if (filter->ip_addr_type) {
4060 req.ip_addr_type = filter->ip_addr_type;
4062 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4065 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4066 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4068 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4069 memcpy(req.src_macaddr, filter->src_macaddr,
4070 RTE_ETHER_ADDR_LEN);
4072 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4073 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4074 //RTE_ETHER_ADDR_LEN);
4076 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4077 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4079 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4080 req.ip_protocol = filter->ip_protocol;
4082 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4083 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4085 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4086 req.src_ipaddr_mask[0] =
4087 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4089 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4090 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4092 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4093 req.dst_ipaddr_mask[0] =
4094 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4096 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4097 req.src_port = rte_cpu_to_le_16(filter->src_port);
4099 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4100 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4102 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4103 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4105 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4106 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4108 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4109 req.mirror_vnic_id = filter->mirror_vnic_id;
4111 req.enables = rte_cpu_to_le_32(enables);
4113 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4115 HWRM_CHECK_RESULT();
4117 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4123 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4124 struct bnxt_filter_info *filter)
4127 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4128 struct hwrm_cfa_ntuple_filter_free_output *resp =
4129 bp->hwrm_cmd_resp_addr;
4131 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4134 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4136 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4138 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4140 HWRM_CHECK_RESULT();
4143 filter->fw_ntuple_filter_id = UINT64_MAX;
4149 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4151 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4152 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4153 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4154 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4155 uint16_t *ring_tbl = vnic->rss_table;
4156 int nr_ctxs = vnic->num_lb_ctxts;
4157 int max_rings = bp->rx_nr_rings;
4161 for (i = 0, k = 0; i < nr_ctxs; i++) {
4162 struct bnxt_rx_ring_info *rxr;
4163 struct bnxt_cp_ring_info *cpr;
4165 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4167 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4168 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4169 req.hash_mode_flags = vnic->hash_mode;
4171 req.ring_grp_tbl_addr =
4172 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4173 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4174 2 * sizeof(*ring_tbl));
4175 req.hash_key_tbl_addr =
4176 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4178 req.ring_table_pair_index = i;
4179 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4181 for (j = 0; j < 64; j++) {
4184 /* Find next active ring. */
4185 for (cnt = 0; cnt < max_rings; cnt++) {
4186 if (rx_queue_state[k] !=
4187 RTE_ETH_QUEUE_STATE_STOPPED)
4189 if (++k == max_rings)
4193 /* Return if no rings are active. */
4194 if (cnt == max_rings)
4197 /* Add rx/cp ring pair to RSS table. */
4198 rxr = rxqs[k]->rx_ring;
4199 cpr = rxqs[k]->cp_ring;
4201 ring_id = rxr->rx_ring_struct->fw_ring_id;
4202 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4203 ring_id = cpr->cp_ring_struct->fw_ring_id;
4204 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4206 if (++k == max_rings)
4209 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4212 HWRM_CHECK_RESULT();
4219 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4221 unsigned int rss_idx, fw_idx, i;
4223 if (!(vnic->rss_table && vnic->hash_type))
4226 if (BNXT_CHIP_THOR(bp))
4227 return bnxt_vnic_rss_configure_thor(bp, vnic);
4230 * Fill the RSS hash & redirection table with
4231 * ring group ids for all VNICs
4233 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4234 rss_idx++, fw_idx++) {
4235 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4236 fw_idx %= bp->rx_cp_nr_rings;
4237 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4241 if (i == bp->rx_cp_nr_rings)
4243 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4245 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4248 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4249 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4253 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4255 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4256 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4258 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4259 req->num_cmpl_dma_aggr_during_int =
4260 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4262 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4264 /* min timer set to 1/2 of interrupt timer */
4265 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4267 /* buf timer set to 1/4 of interrupt timer */
4268 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4270 req->cmpl_aggr_dma_tmr_during_int =
4271 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4273 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4274 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4275 req->flags = rte_cpu_to_le_16(flags);
4278 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4279 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4281 struct hwrm_ring_aggint_qcaps_input req = {0};
4282 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4287 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4288 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4289 HWRM_CHECK_RESULT();
4291 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4292 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4294 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4295 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4296 agg_req->flags = rte_cpu_to_le_16(flags);
4298 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4299 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4300 agg_req->enables = rte_cpu_to_le_32(enables);
4306 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4307 struct bnxt_coal *coal, uint16_t ring_id)
4309 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4310 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4311 bp->hwrm_cmd_resp_addr;
4314 /* Set ring coalesce parameters only for 100G NICs */
4315 if (BNXT_CHIP_THOR(bp)) {
4316 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4318 } else if (bnxt_stratus_device(bp)) {
4319 bnxt_hwrm_set_coal_params(coal, &req);
4324 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4325 req.ring_id = rte_cpu_to_le_16(ring_id);
4326 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4327 HWRM_CHECK_RESULT();
4332 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4333 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4335 struct hwrm_func_backing_store_qcaps_input req = {0};
4336 struct hwrm_func_backing_store_qcaps_output *resp =
4337 bp->hwrm_cmd_resp_addr;
4340 if (!BNXT_CHIP_THOR(bp) ||
4341 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4346 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4347 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4348 HWRM_CHECK_RESULT_SILENT();
4351 struct bnxt_ctx_pg_info *ctx_pg;
4352 struct bnxt_ctx_mem_info *ctx;
4353 int total_alloc_len;
4356 total_alloc_len = sizeof(*ctx);
4357 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4358 RTE_CACHE_LINE_SIZE);
4363 memset(ctx, 0, total_alloc_len);
4365 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4366 sizeof(*ctx_pg) * BNXT_MAX_Q,
4367 RTE_CACHE_LINE_SIZE);
4372 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4373 ctx->tqm_mem[i] = ctx_pg;
4376 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4377 ctx->qp_min_qp1_entries =
4378 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4379 ctx->qp_max_l2_entries =
4380 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4381 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4382 ctx->srq_max_l2_entries =
4383 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4384 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4385 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4386 ctx->cq_max_l2_entries =
4387 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4388 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4389 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4390 ctx->vnic_max_vnic_entries =
4391 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4392 ctx->vnic_max_ring_table_entries =
4393 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4394 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4395 ctx->stat_max_entries =
4396 rte_le_to_cpu_32(resp->stat_max_entries);
4397 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4398 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4399 ctx->tqm_min_entries_per_ring =
4400 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4401 ctx->tqm_max_entries_per_ring =
4402 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4403 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4404 if (!ctx->tqm_entries_multiple)
4405 ctx->tqm_entries_multiple = 1;
4406 ctx->mrav_max_entries =
4407 rte_le_to_cpu_32(resp->mrav_max_entries);
4408 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4409 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4410 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4419 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4421 struct hwrm_func_backing_store_cfg_input req = {0};
4422 struct hwrm_func_backing_store_cfg_output *resp =
4423 bp->hwrm_cmd_resp_addr;
4424 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4425 struct bnxt_ctx_pg_info *ctx_pg;
4426 uint32_t *num_entries;
4435 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4436 req.enables = rte_cpu_to_le_32(enables);
4438 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4439 ctx_pg = &ctx->qp_mem;
4440 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4441 req.qp_num_qp1_entries =
4442 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4443 req.qp_num_l2_entries =
4444 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4445 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4446 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4447 &req.qpc_pg_size_qpc_lvl,
4451 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4452 ctx_pg = &ctx->srq_mem;
4453 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4454 req.srq_num_l2_entries =
4455 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4456 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4457 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4458 &req.srq_pg_size_srq_lvl,
4462 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4463 ctx_pg = &ctx->cq_mem;
4464 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4465 req.cq_num_l2_entries =
4466 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4467 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4468 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4469 &req.cq_pg_size_cq_lvl,
4473 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4474 ctx_pg = &ctx->vnic_mem;
4475 req.vnic_num_vnic_entries =
4476 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4477 req.vnic_num_ring_table_entries =
4478 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4479 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4480 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4481 &req.vnic_pg_size_vnic_lvl,
4482 &req.vnic_page_dir);
4485 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4486 ctx_pg = &ctx->stat_mem;
4487 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4488 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4489 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4490 &req.stat_pg_size_stat_lvl,
4491 &req.stat_page_dir);
4494 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4495 num_entries = &req.tqm_sp_num_entries;
4496 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4497 pg_dir = &req.tqm_sp_page_dir;
4498 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4499 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4500 if (!(enables & ena))
4503 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4505 ctx_pg = ctx->tqm_mem[i];
4506 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4507 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4510 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4511 HWRM_CHECK_RESULT();
4517 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4519 struct hwrm_port_qstats_ext_input req = {0};
4520 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4521 struct bnxt_pf_info *pf = &bp->pf;
4524 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4525 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4528 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4530 req.port_id = rte_cpu_to_le_16(pf->port_id);
4531 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4532 req.tx_stat_host_addr =
4533 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4535 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4537 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4538 req.rx_stat_host_addr =
4539 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4541 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4543 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4546 bp->fw_rx_port_stats_ext_size = 0;
4547 bp->fw_tx_port_stats_ext_size = 0;
4549 bp->fw_rx_port_stats_ext_size =
4550 rte_le_to_cpu_16(resp->rx_stat_size);
4551 bp->fw_tx_port_stats_ext_size =
4552 rte_le_to_cpu_16(resp->tx_stat_size);
4555 HWRM_CHECK_RESULT();
4562 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4564 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4565 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4566 bp->hwrm_cmd_resp_addr;
4569 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4570 req.tunnel_type = type;
4571 req.dest_fid = bp->fw_fid;
4572 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4573 HWRM_CHECK_RESULT();
4581 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4583 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4584 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4585 bp->hwrm_cmd_resp_addr;
4588 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4589 req.tunnel_type = type;
4590 req.dest_fid = bp->fw_fid;
4591 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4592 HWRM_CHECK_RESULT();
4599 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4601 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4602 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4603 bp->hwrm_cmd_resp_addr;
4606 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4607 req.src_fid = bp->fw_fid;
4608 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4609 HWRM_CHECK_RESULT();
4612 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4619 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4622 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4623 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4624 bp->hwrm_cmd_resp_addr;
4627 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4628 req.src_fid = bp->fw_fid;
4629 req.tunnel_type = tun_type;
4630 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4631 HWRM_CHECK_RESULT();
4634 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4636 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4643 int bnxt_hwrm_set_mac(struct bnxt *bp)
4645 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4646 struct hwrm_func_vf_cfg_input req = {0};
4652 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4655 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4656 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4658 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4660 HWRM_CHECK_RESULT();
4662 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4668 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4670 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4671 struct hwrm_func_drv_if_change_input req = {0};
4675 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4678 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4679 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4680 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4682 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4685 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4689 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4691 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4693 HWRM_CHECK_RESULT();
4694 flags = rte_le_to_cpu_32(resp->flags);
4697 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4698 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4699 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;