1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(void *) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages > 1) {
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
103 /* For VER_GET command, set timeout as 50ms */
104 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
105 timeout = HWRM_CMD_TIMEOUT;
107 timeout = bp->hwrm_cmd_timeout;
109 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
110 msg_len > bp->max_req_len) {
111 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
113 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
114 memcpy(short_cmd_req, req, msg_len);
116 short_input.req_type = rte_cpu_to_le_16(req->req_type);
117 short_input.signature = rte_cpu_to_le_16(
118 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
119 short_input.size = rte_cpu_to_le_16(msg_len);
120 short_input.req_addr =
121 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
123 data = (uint32_t *)&short_input;
124 msg_len = sizeof(short_input);
126 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
129 /* Write request msg to hwrm channel */
130 for (i = 0; i < msg_len; i += 4) {
131 bar = (uint8_t *)bp->bar0 + bar_offset + i;
132 rte_write32(*data, bar);
136 /* Zero the rest of the request space */
137 for (; i < max_req_len; i += 4) {
138 bar = (uint8_t *)bp->bar0 + bar_offset + i;
142 /* Ring channel doorbell */
143 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
146 * Make sure the channel doorbell ring command complete before
147 * reading the response to avoid getting stale or invalid
152 /* Poll for the valid bit */
153 for (i = 0; i < timeout; i++) {
154 /* Sanity check on the resp->resp_len */
156 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
157 /* Last byte of resp contains the valid key */
158 valid = (uint8_t *)resp + resp->resp_len - 1;
159 if (*valid == HWRM_RESP_VALID_KEY)
166 /* Suppress VER_GET timeout messages during reset recovery */
167 if (bp->flags & BNXT_FLAG_FW_RESET &&
168 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
171 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
179 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
180 * spinlock, and does initial processing.
182 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
183 * releases the spinlock only if it returns. If the regular int return codes
184 * are not used by the function, HWRM_CHECK_RESULT() should not be used
185 * directly, rather it should be copied and modified to suit the function.
187 * HWRM_UNLOCK() must be called after all response processing is completed.
189 #define HWRM_PREP(req, type, kong) do { \
190 rte_spinlock_lock(&bp->hwrm_lock); \
191 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
192 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
193 req.cmpl_ring = rte_cpu_to_le_16(-1); \
194 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
195 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
196 req.target_id = rte_cpu_to_le_16(0xffff); \
197 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
200 #define HWRM_CHECK_RESULT_SILENT() do {\
202 rte_spinlock_unlock(&bp->hwrm_lock); \
205 if (resp->error_code) { \
206 rc = rte_le_to_cpu_16(resp->error_code); \
207 rte_spinlock_unlock(&bp->hwrm_lock); \
212 #define HWRM_CHECK_RESULT() do {\
214 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
215 rte_spinlock_unlock(&bp->hwrm_lock); \
216 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
218 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
220 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
222 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
228 if (resp->error_code) { \
229 rc = rte_le_to_cpu_16(resp->error_code); \
230 if (resp->resp_len >= 16) { \
231 struct hwrm_err_output *tmp_hwrm_err_op = \
234 "error %d:%d:%08x:%04x\n", \
235 rc, tmp_hwrm_err_op->cmd_err, \
237 tmp_hwrm_err_op->opaque_0), \
239 tmp_hwrm_err_op->opaque_1)); \
241 PMD_DRV_LOG(ERR, "error %d\n", rc); \
243 rte_spinlock_unlock(&bp->hwrm_lock); \
244 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
246 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
248 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
250 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
258 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
263 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
264 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
270 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
279 struct bnxt_vnic_info *vnic,
281 struct bnxt_vlan_table_entry *vlan_table)
284 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
285 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
288 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
291 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
292 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
294 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
295 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
296 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
297 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
299 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
300 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
302 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
303 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
304 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
305 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
306 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
307 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
310 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
311 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
312 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
313 rte_mem_virt2iova(vlan_table));
314 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
316 req.mask = rte_cpu_to_le_32(mask);
318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
328 struct bnxt_vlan_antispoof_table_entry *vlan_table)
331 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
332 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
333 bp->hwrm_cmd_resp_addr;
336 * Older HWRM versions did not support this command, and the set_rx_mask
337 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
338 * removed from set_rx_mask call, and this command was added.
340 * This command is also present from 1.7.8.11 and higher,
343 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
344 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
345 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
350 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
351 req.fid = rte_cpu_to_le_16(fid);
353 req.vlan_tag_mask_tbl_addr =
354 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
355 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
366 struct bnxt_filter_info *filter)
369 struct bnxt_filter_info *l2_filter = filter;
370 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
371 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
373 if (filter->fw_l2_filter_id == UINT64_MAX)
376 if (filter->matching_l2_fltr_ptr)
377 l2_filter = filter->matching_l2_fltr_ptr;
379 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
380 filter, l2_filter, l2_filter->l2_ref_cnt);
382 if (l2_filter->l2_ref_cnt > 0)
383 l2_filter->l2_ref_cnt--;
385 if (l2_filter->l2_ref_cnt > 0)
388 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
390 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
392 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
397 filter->fw_l2_filter_id = UINT64_MAX;
402 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
404 struct bnxt_filter_info *filter)
407 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
408 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
409 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
410 const struct rte_eth_vmdq_rx_conf *conf =
411 &dev_conf->rx_adv_conf.vmdq_rx_conf;
412 uint32_t enables = 0;
413 uint16_t j = dst_id - 1;
415 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
416 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
417 conf->pool_map[j].pools & (1UL << j)) {
419 "Add vlan %u to vmdq pool %u\n",
420 conf->pool_map[j].vlan_id, j);
422 filter->l2_ivlan = conf->pool_map[j].vlan_id;
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
425 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
428 if (filter->fw_l2_filter_id != UINT64_MAX)
429 bnxt_hwrm_clear_l2_filter(bp, filter);
431 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
433 req.flags = rte_cpu_to_le_32(filter->flags);
435 enables = filter->enables |
436 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
437 req.dst_id = rte_cpu_to_le_16(dst_id);
440 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
441 memcpy(req.l2_addr, filter->l2_addr,
444 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
445 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
448 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
449 req.l2_ovlan = filter->l2_ovlan;
451 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
452 req.l2_ivlan = filter->l2_ivlan;
454 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
455 req.l2_ovlan_mask = filter->l2_ovlan_mask;
457 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
458 req.l2_ivlan_mask = filter->l2_ivlan_mask;
459 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
460 req.src_id = rte_cpu_to_le_32(filter->src_id);
461 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
462 req.src_type = filter->src_type;
463 if (filter->pri_hint) {
464 req.pri_hint = filter->pri_hint;
465 req.l2_filter_id_hint =
466 rte_cpu_to_le_64(filter->l2_filter_id_hint);
469 req.enables = rte_cpu_to_le_32(enables);
471 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
475 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
481 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
483 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
484 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
491 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
494 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
497 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
498 if (ptp->tx_tstamp_en)
499 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
502 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
503 req.flags = rte_cpu_to_le_32(flags);
504 req.enables = rte_cpu_to_le_32
505 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
506 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
508 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
514 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
517 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
518 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
519 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
524 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
526 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
528 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
532 if (!BNXT_CHIP_THOR(bp) &&
533 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
536 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
537 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
539 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
543 if (!BNXT_CHIP_THOR(bp)) {
544 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
545 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
546 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
547 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
548 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
549 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
550 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
551 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
552 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
553 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
554 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
555 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
556 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
557 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
558 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
559 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
560 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
561 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
570 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
573 struct hwrm_func_qcaps_input req = {.req_type = 0 };
574 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
575 uint16_t new_max_vfs;
579 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
581 req.fid = rte_cpu_to_le_16(0xffff);
583 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
587 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
588 flags = rte_le_to_cpu_32(resp->flags);
590 bp->pf.port_id = resp->port_id;
591 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
592 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
593 new_max_vfs = bp->pdev->max_vfs;
594 if (new_max_vfs != bp->pf.max_vfs) {
596 rte_free(bp->pf.vf_info);
597 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
598 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
599 bp->pf.max_vfs = new_max_vfs;
600 for (i = 0; i < new_max_vfs; i++) {
601 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
602 bp->pf.vf_info[i].vlan_table =
603 rte_zmalloc("VF VLAN table",
606 if (bp->pf.vf_info[i].vlan_table == NULL)
608 "Fail to alloc VLAN table for VF %d\n",
612 bp->pf.vf_info[i].vlan_table);
613 bp->pf.vf_info[i].vlan_as_table =
614 rte_zmalloc("VF VLAN AS table",
617 if (bp->pf.vf_info[i].vlan_as_table == NULL)
619 "Alloc VLAN AS table for VF %d fail\n",
623 bp->pf.vf_info[i].vlan_as_table);
624 STAILQ_INIT(&bp->pf.vf_info[i].filter);
629 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
630 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
631 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
632 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
633 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
634 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
635 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
636 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
637 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
638 if (!BNXT_CHIP_THOR(bp))
639 bp->max_l2_ctx += bp->max_rx_em_flows;
640 /* TODO: For now, do not support VMDq/RFS on VFs. */
645 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
649 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
651 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
652 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
653 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
654 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
656 bnxt_hwrm_ptp_qcfg(bp);
660 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
661 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
663 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
664 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
665 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
667 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
670 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
671 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
673 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
680 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
684 rc = __bnxt_hwrm_func_qcaps(bp);
685 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
686 rc = bnxt_alloc_ctx_mem(bp);
690 rc = bnxt_hwrm_func_resc_qcaps(bp);
692 bp->flags |= BNXT_FLAG_NEW_RM;
696 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
697 * But the error can be ignored. Return success.
703 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
704 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
707 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
708 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
710 HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
712 req.target_id = rte_cpu_to_le_16(0xffff);
714 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
718 if (rte_le_to_cpu_32(resp->flags) &
719 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
720 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
721 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
724 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
731 int bnxt_hwrm_func_reset(struct bnxt *bp)
734 struct hwrm_func_reset_input req = {.req_type = 0 };
735 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
737 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
739 req.enables = rte_cpu_to_le_32(0);
741 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
749 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
753 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
754 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
756 if (bp->flags & BNXT_FLAG_REGISTERED)
759 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
760 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
761 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
763 /* PFs and trusted VFs should indicate the support of the
764 * Master capability on non Stingray platform
766 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
767 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
769 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
770 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
771 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
772 req.ver_maj = RTE_VER_YEAR;
773 req.ver_min = RTE_VER_MONTH;
774 req.ver_upd = RTE_VER_MINOR;
777 req.enables |= rte_cpu_to_le_32(
778 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
779 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
780 RTE_MIN(sizeof(req.vf_req_fwd),
781 sizeof(bp->pf.vf_req_fwd)));
784 * PF can sniff HWRM API issued by VF. This can be set up by
785 * linux driver and inherited by the DPDK PF driver. Clear
786 * this HWRM sniffer list in FW because DPDK PF driver does
789 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
792 req.flags = rte_cpu_to_le_32(flags);
794 req.async_event_fwd[0] |=
795 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
796 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
797 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
798 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
799 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
800 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
801 req.async_event_fwd[0] |=
802 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
803 req.async_event_fwd[1] |=
804 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
805 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
807 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
811 flags = rte_le_to_cpu_32(resp->flags);
812 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
813 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
817 bp->flags |= BNXT_FLAG_REGISTERED;
822 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
824 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
827 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
830 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
835 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
836 struct hwrm_func_vf_cfg_input req = {0};
838 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
840 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
841 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
842 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
843 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
844 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
846 if (BNXT_HAS_RING_GRPS(bp)) {
847 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
848 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
851 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
852 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
853 AGG_RING_MULTIPLIER);
854 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
855 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
857 BNXT_NUM_ASYNC_CPR(bp));
858 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
859 if (bp->vf_resv_strategy ==
860 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
861 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
862 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
863 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
864 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
865 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
866 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
867 } else if (bp->vf_resv_strategy ==
868 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
869 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
870 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
874 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
875 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
876 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
877 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
878 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
879 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
881 if (test && BNXT_HAS_RING_GRPS(bp))
882 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
884 req.flags = rte_cpu_to_le_32(flags);
885 req.enables |= rte_cpu_to_le_32(enables);
887 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
890 HWRM_CHECK_RESULT_SILENT();
898 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
901 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
902 struct hwrm_func_resource_qcaps_input req = {0};
904 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
905 req.fid = rte_cpu_to_le_16(0xffff);
907 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
909 HWRM_CHECK_RESULT_SILENT();
912 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
913 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
914 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
915 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
916 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
917 /* func_resource_qcaps does not return max_rx_em_flows.
918 * So use the value provided by func_qcaps.
920 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
921 if (!BNXT_CHIP_THOR(bp))
922 bp->max_l2_ctx += bp->max_rx_em_flows;
923 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
924 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
926 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
927 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
928 if (bp->vf_resv_strategy >
929 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
930 bp->vf_resv_strategy =
931 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
937 int bnxt_hwrm_ver_get(struct bnxt *bp)
940 struct hwrm_ver_get_input req = {.req_type = 0 };
941 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
943 uint16_t max_resp_len;
944 char type[RTE_MEMZONE_NAMESIZE];
945 uint32_t dev_caps_cfg;
947 bp->max_req_len = HWRM_MAX_REQ_LEN;
948 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
950 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
951 req.hwrm_intf_min = HWRM_VERSION_MINOR;
952 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
954 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
956 if (bp->flags & BNXT_FLAG_FW_RESET)
957 HWRM_CHECK_RESULT_SILENT();
961 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
962 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
963 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
964 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
965 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
966 (resp->hwrm_fw_min_8b << 16) |
967 (resp->hwrm_fw_bld_8b << 8) |
968 resp->hwrm_fw_rsvd_8b;
969 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
970 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
972 fw_version = resp->hwrm_intf_maj_8b << 16;
973 fw_version |= resp->hwrm_intf_min_8b << 8;
974 fw_version |= resp->hwrm_intf_upd_8b;
975 bp->hwrm_spec_code = fw_version;
977 /* def_req_timeout value is in milliseconds */
978 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
979 /* convert timeout to usec */
980 bp->hwrm_cmd_timeout *= 1000;
981 if (!bp->hwrm_cmd_timeout)
982 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
984 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
985 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
990 if (bp->max_req_len > resp->max_req_win_len) {
991 PMD_DRV_LOG(ERR, "Unsupported request length\n");
994 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
995 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
996 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
997 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
999 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1000 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1002 if (bp->max_resp_len != max_resp_len) {
1003 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1004 bp->pdev->addr.domain, bp->pdev->addr.bus,
1005 bp->pdev->addr.devid, bp->pdev->addr.function);
1007 rte_free(bp->hwrm_cmd_resp_addr);
1009 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1010 if (bp->hwrm_cmd_resp_addr == NULL) {
1014 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1015 bp->hwrm_cmd_resp_dma_addr =
1016 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1017 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1019 "Unable to map response buffer to physical memory.\n");
1023 bp->max_resp_len = max_resp_len;
1027 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1029 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1030 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1031 bp->flags |= BNXT_FLAG_SHORT_CMD;
1034 if (((dev_caps_cfg &
1035 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1037 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1038 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1039 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1040 bp->pdev->addr.domain, bp->pdev->addr.bus,
1041 bp->pdev->addr.devid, bp->pdev->addr.function);
1043 rte_free(bp->hwrm_short_cmd_req_addr);
1045 bp->hwrm_short_cmd_req_addr =
1046 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1047 if (bp->hwrm_short_cmd_req_addr == NULL) {
1051 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1052 bp->hwrm_short_cmd_req_dma_addr =
1053 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1054 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1055 rte_free(bp->hwrm_short_cmd_req_addr);
1057 "Unable to map buffer to physical memory.\n");
1063 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1064 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1065 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1068 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1069 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1071 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1072 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1073 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1081 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1084 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1085 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1087 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1090 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1093 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1095 HWRM_CHECK_RESULT();
1101 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1104 struct hwrm_port_phy_cfg_input req = {0};
1105 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1106 uint32_t enables = 0;
1108 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1110 if (conf->link_up) {
1111 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1112 if (bp->link_info.auto_mode && conf->link_speed) {
1113 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1114 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1117 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1118 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1119 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1121 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1122 * any auto mode, even "none".
1124 if (!conf->link_speed) {
1125 /* No speeds specified. Enable AutoNeg - all speeds */
1127 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1129 /* AutoNeg - Advertise speeds specified. */
1130 if (conf->auto_link_speed_mask &&
1131 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1133 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1134 req.auto_link_speed_mask =
1135 conf->auto_link_speed_mask;
1137 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1140 req.auto_duplex = conf->duplex;
1141 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1142 req.auto_pause = conf->auto_pause;
1143 req.force_pause = conf->force_pause;
1144 /* Set force_pause if there is no auto or if there is a force */
1145 if (req.auto_pause && !req.force_pause)
1146 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1148 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1150 req.enables = rte_cpu_to_le_32(enables);
1153 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1154 PMD_DRV_LOG(INFO, "Force Link Down\n");
1157 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1159 HWRM_CHECK_RESULT();
1165 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1166 struct bnxt_link_info *link_info)
1169 struct hwrm_port_phy_qcfg_input req = {0};
1170 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1172 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1174 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1176 HWRM_CHECK_RESULT();
1178 link_info->phy_link_status = resp->link;
1179 link_info->link_up =
1180 (link_info->phy_link_status ==
1181 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1182 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1183 link_info->duplex = resp->duplex_cfg;
1184 link_info->pause = resp->pause;
1185 link_info->auto_pause = resp->auto_pause;
1186 link_info->force_pause = resp->force_pause;
1187 link_info->auto_mode = resp->auto_mode;
1188 link_info->phy_type = resp->phy_type;
1189 link_info->media_type = resp->media_type;
1191 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1192 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1193 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1194 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1195 link_info->phy_ver[0] = resp->phy_maj;
1196 link_info->phy_ver[1] = resp->phy_min;
1197 link_info->phy_ver[2] = resp->phy_bld;
1201 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1202 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1203 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1204 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1205 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1206 link_info->auto_link_speed_mask);
1207 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1208 link_info->force_link_speed);
1213 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1216 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1217 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1218 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1222 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1224 req.flags = rte_cpu_to_le_32(dir);
1225 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1226 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1227 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1229 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1230 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1232 HWRM_CHECK_RESULT();
1234 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1235 GET_TX_QUEUE_INFO(0);
1236 GET_TX_QUEUE_INFO(1);
1237 GET_TX_QUEUE_INFO(2);
1238 GET_TX_QUEUE_INFO(3);
1239 GET_TX_QUEUE_INFO(4);
1240 GET_TX_QUEUE_INFO(5);
1241 GET_TX_QUEUE_INFO(6);
1242 GET_TX_QUEUE_INFO(7);
1244 GET_RX_QUEUE_INFO(0);
1245 GET_RX_QUEUE_INFO(1);
1246 GET_RX_QUEUE_INFO(2);
1247 GET_RX_QUEUE_INFO(3);
1248 GET_RX_QUEUE_INFO(4);
1249 GET_RX_QUEUE_INFO(5);
1250 GET_RX_QUEUE_INFO(6);
1251 GET_RX_QUEUE_INFO(7);
1256 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1259 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1260 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1264 /* iterate and find the COSq profile to use for Tx */
1265 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1266 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1267 if (bp->tx_cos_queue[i].id != 0xff)
1268 bp->tx_cosq_id[j++] =
1269 bp->tx_cos_queue[i].id;
1272 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1273 if (bp->tx_cos_queue[i].profile ==
1274 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1276 bp->tx_cos_queue[i].id;
1283 bp->max_tc = resp->max_configurable_queues;
1284 bp->max_lltc = resp->max_configurable_lossless_queues;
1285 if (bp->max_tc > BNXT_MAX_QUEUE)
1286 bp->max_tc = BNXT_MAX_QUEUE;
1287 bp->max_q = bp->max_tc;
1289 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1290 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1298 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1299 struct bnxt_ring *ring,
1300 uint32_t ring_type, uint32_t map_index,
1301 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1302 uint16_t tx_cosq_id)
1305 uint32_t enables = 0;
1306 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1307 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1308 struct rte_mempool *mb_pool;
1309 uint16_t rx_buf_size;
1311 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1313 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1314 req.fbo = rte_cpu_to_le_32(0);
1315 /* Association of ring index with doorbell index */
1316 req.logical_id = rte_cpu_to_le_16(map_index);
1317 req.length = rte_cpu_to_le_32(ring->ring_size);
1319 switch (ring_type) {
1320 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1321 req.ring_type = ring_type;
1322 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1323 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1324 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1325 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1327 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1329 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1330 req.ring_type = ring_type;
1331 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1332 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1333 if (BNXT_CHIP_THOR(bp)) {
1334 mb_pool = bp->rx_queues[0]->mb_pool;
1335 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1336 RTE_PKTMBUF_HEADROOM;
1337 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1338 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1340 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1342 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1344 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1346 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1347 req.ring_type = ring_type;
1348 if (BNXT_HAS_NQ(bp)) {
1349 /* Association of cp ring with nq */
1350 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1352 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1354 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1356 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1357 req.ring_type = ring_type;
1358 req.page_size = BNXT_PAGE_SHFT;
1359 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1361 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1362 req.ring_type = ring_type;
1363 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1365 mb_pool = bp->rx_queues[0]->mb_pool;
1366 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1367 RTE_PKTMBUF_HEADROOM;
1368 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1369 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1371 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1372 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1373 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1374 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1377 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1382 req.enables = rte_cpu_to_le_32(enables);
1384 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1386 if (rc || resp->error_code) {
1387 if (rc == 0 && resp->error_code)
1388 rc = rte_le_to_cpu_16(resp->error_code);
1389 switch (ring_type) {
1390 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1392 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1395 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1397 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1400 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1402 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1406 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1408 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1411 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1413 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1417 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1423 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1428 int bnxt_hwrm_ring_free(struct bnxt *bp,
1429 struct bnxt_ring *ring, uint32_t ring_type)
1432 struct hwrm_ring_free_input req = {.req_type = 0 };
1433 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1435 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1437 req.ring_type = ring_type;
1438 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1440 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1442 if (rc || resp->error_code) {
1443 if (rc == 0 && resp->error_code)
1444 rc = rte_le_to_cpu_16(resp->error_code);
1447 switch (ring_type) {
1448 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1449 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1452 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1453 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1456 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1457 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1460 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1462 "hwrm_ring_free nq failed. rc:%d\n", rc);
1464 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1466 "hwrm_ring_free agg failed. rc:%d\n", rc);
1469 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1477 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1480 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1481 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1483 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1485 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1486 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1487 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1488 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1490 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1492 HWRM_CHECK_RESULT();
1494 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1501 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1504 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1505 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1507 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1509 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1511 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1513 HWRM_CHECK_RESULT();
1516 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1520 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1523 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1524 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1526 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1529 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1531 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1533 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1535 HWRM_CHECK_RESULT();
1541 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1542 unsigned int idx __rte_unused)
1545 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1546 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1548 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1550 req.update_period_ms = rte_cpu_to_le_32(0);
1552 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1554 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1556 HWRM_CHECK_RESULT();
1558 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1565 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1566 unsigned int idx __rte_unused)
1569 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1570 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1572 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1574 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1576 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1578 HWRM_CHECK_RESULT();
1584 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1587 struct hwrm_vnic_alloc_input req = { 0 };
1588 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1590 if (!BNXT_HAS_RING_GRPS(bp))
1591 goto skip_ring_grps;
1593 /* map ring groups to this vnic */
1594 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1595 vnic->start_grp_id, vnic->end_grp_id);
1596 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1597 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1599 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1600 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1601 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1602 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1605 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1606 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1608 if (vnic->func_default)
1610 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1611 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1613 HWRM_CHECK_RESULT();
1615 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1617 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1621 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1622 struct bnxt_vnic_info *vnic,
1623 struct bnxt_plcmodes_cfg *pmode)
1626 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1627 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1629 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1631 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1633 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1635 HWRM_CHECK_RESULT();
1637 pmode->flags = rte_le_to_cpu_32(resp->flags);
1638 /* dflt_vnic bit doesn't exist in the _cfg command */
1639 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1640 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1641 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1642 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1649 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1650 struct bnxt_vnic_info *vnic,
1651 struct bnxt_plcmodes_cfg *pmode)
1654 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1655 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1657 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1658 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1662 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1664 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1665 req.flags = rte_cpu_to_le_32(pmode->flags);
1666 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1667 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1668 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1669 req.enables = rte_cpu_to_le_32(
1670 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1671 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1672 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1675 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1677 HWRM_CHECK_RESULT();
1683 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1686 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1687 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1688 struct bnxt_plcmodes_cfg pmodes = { 0 };
1689 uint32_t ctx_enable_flag = 0;
1690 uint32_t enables = 0;
1692 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1693 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1697 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1701 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1703 if (BNXT_CHIP_THOR(bp)) {
1704 int dflt_rxq = vnic->start_grp_id;
1705 struct bnxt_rx_ring_info *rxr;
1706 struct bnxt_cp_ring_info *cpr;
1707 struct bnxt_rx_queue *rxq;
1711 * The first active receive ring is used as the VNIC
1712 * default receive ring. If there are no active receive
1713 * rings (all corresponding receive queues are stopped),
1714 * the first receive ring is used.
1716 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1717 rxq = bp->eth_dev->data->rx_queues[i];
1718 if (rxq->rx_started) {
1724 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1728 req.default_rx_ring_id =
1729 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1730 req.default_cmpl_ring_id =
1731 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1732 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1733 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1737 /* Only RSS support for now TBD: COS & LB */
1738 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1739 if (vnic->lb_rule != 0xffff)
1740 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1741 if (vnic->cos_rule != 0xffff)
1742 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1743 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1744 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1745 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1747 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1748 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1749 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1752 enables |= ctx_enable_flag;
1753 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1754 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1755 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1756 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1759 req.enables = rte_cpu_to_le_32(enables);
1760 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1761 req.mru = rte_cpu_to_le_16(vnic->mru);
1762 /* Configure default VNIC only once. */
1763 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1765 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1766 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1768 if (vnic->vlan_strip)
1770 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1773 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1774 if (vnic->roce_dual)
1775 req.flags |= rte_cpu_to_le_32(
1776 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1777 if (vnic->roce_only)
1778 req.flags |= rte_cpu_to_le_32(
1779 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1780 if (vnic->rss_dflt_cr)
1781 req.flags |= rte_cpu_to_le_32(
1782 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1784 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1786 HWRM_CHECK_RESULT();
1789 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1794 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1798 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1799 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1801 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1802 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1805 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1808 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1809 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1810 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1812 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1814 HWRM_CHECK_RESULT();
1816 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1817 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1818 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1819 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1820 vnic->mru = rte_le_to_cpu_16(resp->mru);
1821 vnic->func_default = rte_le_to_cpu_32(
1822 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1823 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1824 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1825 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1826 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1827 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1828 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1829 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1830 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1831 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1832 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1839 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1840 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1844 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1845 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1846 bp->hwrm_cmd_resp_addr;
1848 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1850 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1851 HWRM_CHECK_RESULT();
1853 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1854 if (!BNXT_HAS_RING_GRPS(bp))
1855 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1856 else if (ctx_idx == 0)
1857 vnic->rss_rule = ctx_id;
1865 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1866 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1869 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1870 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1871 bp->hwrm_cmd_resp_addr;
1873 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1874 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1877 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1879 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1881 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1883 HWRM_CHECK_RESULT();
1889 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1893 if (BNXT_CHIP_THOR(bp)) {
1896 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1897 rc = _bnxt_hwrm_vnic_ctx_free(bp,
1899 vnic->fw_grp_ids[j]);
1900 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1902 vnic->num_lb_ctxts = 0;
1904 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1905 vnic->rss_rule = INVALID_HW_RING_ID;
1911 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1914 struct hwrm_vnic_free_input req = {.req_type = 0 };
1915 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1917 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1918 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1922 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1924 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1926 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1928 HWRM_CHECK_RESULT();
1931 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1932 /* Configure default VNIC again if necessary. */
1933 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1934 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1940 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1944 int nr_ctxs = vnic->num_lb_ctxts;
1945 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1946 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1948 for (i = 0; i < nr_ctxs; i++) {
1949 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1951 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1952 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1953 req.hash_mode_flags = vnic->hash_mode;
1955 req.hash_key_tbl_addr =
1956 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1958 req.ring_grp_tbl_addr =
1959 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1960 i * HW_HASH_INDEX_SIZE);
1961 req.ring_table_pair_index = i;
1962 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1964 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1967 HWRM_CHECK_RESULT();
1974 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1975 struct bnxt_vnic_info *vnic)
1978 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1979 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1981 if (!vnic->rss_table)
1984 if (BNXT_CHIP_THOR(bp))
1985 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1987 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1989 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1990 req.hash_mode_flags = vnic->hash_mode;
1992 req.ring_grp_tbl_addr =
1993 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1994 req.hash_key_tbl_addr =
1995 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1996 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1997 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1999 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2001 HWRM_CHECK_RESULT();
2007 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2008 struct bnxt_vnic_info *vnic)
2011 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2012 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2015 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2016 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2020 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2022 req.flags = rte_cpu_to_le_32(
2023 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2025 req.enables = rte_cpu_to_le_32(
2026 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2028 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2029 size -= RTE_PKTMBUF_HEADROOM;
2030 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2032 req.jumbo_thresh = rte_cpu_to_le_16(size);
2033 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2035 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2037 HWRM_CHECK_RESULT();
2043 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2044 struct bnxt_vnic_info *vnic, bool enable)
2047 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2048 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2050 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2052 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2056 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2057 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2061 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2064 req.enables = rte_cpu_to_le_32(
2065 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2066 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2067 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2068 req.flags = rte_cpu_to_le_32(
2069 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2070 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2071 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2072 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2073 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2074 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2075 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2076 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2077 req.min_agg_len = rte_cpu_to_le_32(512);
2079 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2081 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2083 HWRM_CHECK_RESULT();
2089 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2091 struct hwrm_func_cfg_input req = {0};
2092 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2095 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2096 req.enables = rte_cpu_to_le_32(
2097 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2098 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2099 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2101 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2103 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2104 HWRM_CHECK_RESULT();
2107 bp->pf.vf_info[vf].random_mac = false;
2112 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2116 struct hwrm_func_qstats_input req = {.req_type = 0};
2117 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2119 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2121 req.fid = rte_cpu_to_le_16(fid);
2123 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2125 HWRM_CHECK_RESULT();
2128 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2135 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2136 struct rte_eth_stats *stats)
2139 struct hwrm_func_qstats_input req = {.req_type = 0};
2140 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2142 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2144 req.fid = rte_cpu_to_le_16(fid);
2146 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2148 HWRM_CHECK_RESULT();
2150 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2151 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2152 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2153 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2154 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2155 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2157 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2158 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2159 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2160 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2161 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2162 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2164 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2165 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2166 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2173 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2176 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2177 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2179 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2181 req.fid = rte_cpu_to_le_16(fid);
2183 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2185 HWRM_CHECK_RESULT();
2191 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2196 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2197 struct bnxt_tx_queue *txq;
2198 struct bnxt_rx_queue *rxq;
2199 struct bnxt_cp_ring_info *cpr;
2201 if (i >= bp->rx_cp_nr_rings) {
2202 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2205 rxq = bp->rx_queues[i];
2209 rc = bnxt_hwrm_stat_clear(bp, cpr);
2216 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2220 struct bnxt_cp_ring_info *cpr;
2222 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2224 if (i >= bp->rx_cp_nr_rings) {
2225 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2227 cpr = bp->rx_queues[i]->cp_ring;
2228 if (BNXT_HAS_RING_GRPS(bp))
2229 bp->grp_info[i].fw_stats_ctx = -1;
2231 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2232 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2233 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2241 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2246 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2247 struct bnxt_tx_queue *txq;
2248 struct bnxt_rx_queue *rxq;
2249 struct bnxt_cp_ring_info *cpr;
2251 if (i >= bp->rx_cp_nr_rings) {
2252 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2255 rxq = bp->rx_queues[i];
2259 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2267 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2272 if (!BNXT_HAS_RING_GRPS(bp))
2275 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2277 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2280 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2288 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2290 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2292 bnxt_hwrm_ring_free(bp, cp_ring,
2293 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2294 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2295 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2296 sizeof(*cpr->cp_desc_ring));
2297 cpr->cp_raw_cons = 0;
2301 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2303 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2305 bnxt_hwrm_ring_free(bp, cp_ring,
2306 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2307 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2308 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2309 sizeof(*cpr->cp_desc_ring));
2310 cpr->cp_raw_cons = 0;
2314 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2316 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2317 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2318 struct bnxt_ring *ring = rxr->rx_ring_struct;
2319 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2321 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2322 bnxt_hwrm_ring_free(bp, ring,
2323 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2324 ring->fw_ring_id = INVALID_HW_RING_ID;
2325 if (BNXT_HAS_RING_GRPS(bp))
2326 bp->grp_info[queue_index].rx_fw_ring_id =
2328 memset(rxr->rx_desc_ring, 0,
2329 rxr->rx_ring_struct->ring_size *
2330 sizeof(*rxr->rx_desc_ring));
2331 memset(rxr->rx_buf_ring, 0,
2332 rxr->rx_ring_struct->ring_size *
2333 sizeof(*rxr->rx_buf_ring));
2336 ring = rxr->ag_ring_struct;
2337 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2338 bnxt_hwrm_ring_free(bp, ring,
2339 BNXT_CHIP_THOR(bp) ?
2340 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2341 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2342 ring->fw_ring_id = INVALID_HW_RING_ID;
2343 memset(rxr->ag_buf_ring, 0,
2344 rxr->ag_ring_struct->ring_size *
2345 sizeof(*rxr->ag_buf_ring));
2347 if (BNXT_HAS_RING_GRPS(bp))
2348 bp->grp_info[queue_index].ag_fw_ring_id =
2351 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2352 bnxt_free_cp_ring(bp, cpr);
2354 if (BNXT_HAS_RING_GRPS(bp))
2355 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2358 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2362 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2363 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2364 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2365 struct bnxt_ring *ring = txr->tx_ring_struct;
2366 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2368 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2369 bnxt_hwrm_ring_free(bp, ring,
2370 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2371 ring->fw_ring_id = INVALID_HW_RING_ID;
2372 memset(txr->tx_desc_ring, 0,
2373 txr->tx_ring_struct->ring_size *
2374 sizeof(*txr->tx_desc_ring));
2375 memset(txr->tx_buf_ring, 0,
2376 txr->tx_ring_struct->ring_size *
2377 sizeof(*txr->tx_buf_ring));
2381 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2382 bnxt_free_cp_ring(bp, cpr);
2383 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2387 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2388 bnxt_free_hwrm_rx_ring(bp, i);
2393 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2398 if (!BNXT_HAS_RING_GRPS(bp))
2401 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2402 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2410 * HWRM utility functions
2413 void bnxt_free_hwrm_resources(struct bnxt *bp)
2415 /* Release memzone */
2416 rte_free(bp->hwrm_cmd_resp_addr);
2417 rte_free(bp->hwrm_short_cmd_req_addr);
2418 bp->hwrm_cmd_resp_addr = NULL;
2419 bp->hwrm_short_cmd_req_addr = NULL;
2420 bp->hwrm_cmd_resp_dma_addr = 0;
2421 bp->hwrm_short_cmd_req_dma_addr = 0;
2424 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2426 struct rte_pci_device *pdev = bp->pdev;
2427 char type[RTE_MEMZONE_NAMESIZE];
2429 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2430 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2431 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2432 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2433 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2434 if (bp->hwrm_cmd_resp_addr == NULL)
2436 bp->hwrm_cmd_resp_dma_addr =
2437 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2438 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2440 "unable to map response address to physical memory\n");
2443 rte_spinlock_init(&bp->hwrm_lock);
2448 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2450 struct bnxt_filter_info *filter;
2453 STAILQ_FOREACH(filter, &vnic->filter, next) {
2454 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2455 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2456 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2457 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2459 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2460 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2461 bnxt_free_filter(bp, filter);
2467 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2469 struct bnxt_filter_info *filter;
2470 struct rte_flow *flow;
2473 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2474 flow = STAILQ_FIRST(&vnic->flow_list);
2475 filter = flow->filter;
2476 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2477 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2478 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2479 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2480 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2482 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2484 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2490 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2492 struct bnxt_filter_info *filter;
2495 STAILQ_FOREACH(filter, &vnic->filter, next) {
2496 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2497 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2499 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2500 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2503 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2511 void bnxt_free_tunnel_ports(struct bnxt *bp)
2513 if (bp->vxlan_port_cnt)
2514 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2515 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2517 if (bp->geneve_port_cnt)
2518 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2519 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2520 bp->geneve_port = 0;
2523 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2527 if (bp->vnic_info == NULL)
2531 * Cleanup VNICs in reverse order, to make sure the L2 filter
2532 * from vnic0 is last to be cleaned up.
2534 for (i = bp->max_vnics - 1; i >= 0; i--) {
2535 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2537 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2540 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2542 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2544 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2546 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2548 bnxt_hwrm_vnic_free(bp, vnic);
2550 rte_free(vnic->fw_grp_ids);
2552 /* Ring resources */
2553 bnxt_free_all_hwrm_rings(bp);
2554 bnxt_free_all_hwrm_ring_grps(bp);
2555 bnxt_free_all_hwrm_stat_ctxs(bp);
2556 bnxt_free_tunnel_ports(bp);
2559 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2561 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2563 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2564 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2566 switch (conf_link_speed) {
2567 case ETH_LINK_SPEED_10M_HD:
2568 case ETH_LINK_SPEED_100M_HD:
2570 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2572 return hw_link_duplex;
2575 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2577 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2580 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2582 uint16_t eth_link_speed = 0;
2584 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2585 return ETH_LINK_SPEED_AUTONEG;
2587 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2588 case ETH_LINK_SPEED_100M:
2589 case ETH_LINK_SPEED_100M_HD:
2592 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2594 case ETH_LINK_SPEED_1G:
2596 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2598 case ETH_LINK_SPEED_2_5G:
2600 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2602 case ETH_LINK_SPEED_10G:
2604 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2606 case ETH_LINK_SPEED_20G:
2608 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2610 case ETH_LINK_SPEED_25G:
2612 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2614 case ETH_LINK_SPEED_40G:
2616 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2618 case ETH_LINK_SPEED_50G:
2620 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2622 case ETH_LINK_SPEED_100G:
2624 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2628 "Unsupported link speed %d; default to AUTO\n",
2632 return eth_link_speed;
2635 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2636 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2637 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2638 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2640 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2644 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2647 if (link_speed & ETH_LINK_SPEED_FIXED) {
2648 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2650 if (one_speed & (one_speed - 1)) {
2652 "Invalid advertised speeds (%u) for port %u\n",
2653 link_speed, port_id);
2656 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2658 "Unsupported advertised speed (%u) for port %u\n",
2659 link_speed, port_id);
2663 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2665 "Unsupported advertised speeds (%u) for port %u\n",
2666 link_speed, port_id);
2674 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2678 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2679 if (bp->link_info.support_speeds)
2680 return bp->link_info.support_speeds;
2681 link_speed = BNXT_SUPPORTED_SPEEDS;
2684 if (link_speed & ETH_LINK_SPEED_100M)
2685 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2686 if (link_speed & ETH_LINK_SPEED_100M_HD)
2687 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2688 if (link_speed & ETH_LINK_SPEED_1G)
2689 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2690 if (link_speed & ETH_LINK_SPEED_2_5G)
2691 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2692 if (link_speed & ETH_LINK_SPEED_10G)
2693 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2694 if (link_speed & ETH_LINK_SPEED_20G)
2695 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2696 if (link_speed & ETH_LINK_SPEED_25G)
2697 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2698 if (link_speed & ETH_LINK_SPEED_40G)
2699 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2700 if (link_speed & ETH_LINK_SPEED_50G)
2701 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2702 if (link_speed & ETH_LINK_SPEED_100G)
2703 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2707 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2709 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2711 switch (hw_link_speed) {
2712 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2713 eth_link_speed = ETH_SPEED_NUM_100M;
2715 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2716 eth_link_speed = ETH_SPEED_NUM_1G;
2718 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2719 eth_link_speed = ETH_SPEED_NUM_2_5G;
2721 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2722 eth_link_speed = ETH_SPEED_NUM_10G;
2724 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2725 eth_link_speed = ETH_SPEED_NUM_20G;
2727 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2728 eth_link_speed = ETH_SPEED_NUM_25G;
2730 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2731 eth_link_speed = ETH_SPEED_NUM_40G;
2733 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2734 eth_link_speed = ETH_SPEED_NUM_50G;
2736 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2737 eth_link_speed = ETH_SPEED_NUM_100G;
2739 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2741 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2745 return eth_link_speed;
2748 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2750 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2752 switch (hw_link_duplex) {
2753 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2754 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2756 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2758 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2759 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2762 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2766 return eth_link_duplex;
2769 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2772 struct bnxt_link_info *link_info = &bp->link_info;
2774 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2777 "Get link config failed with rc %d\n", rc);
2780 if (link_info->link_speed)
2782 bnxt_parse_hw_link_speed(link_info->link_speed);
2784 link->link_speed = ETH_SPEED_NUM_NONE;
2785 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2786 link->link_status = link_info->link_up;
2787 link->link_autoneg = link_info->auto_mode ==
2788 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2789 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2794 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2797 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2798 struct bnxt_link_info link_req;
2799 uint16_t speed, autoneg;
2801 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2804 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2805 bp->eth_dev->data->port_id);
2809 memset(&link_req, 0, sizeof(link_req));
2810 link_req.link_up = link_up;
2814 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2815 if (BNXT_CHIP_THOR(bp) &&
2816 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2817 /* 40G is not supported as part of media auto detect.
2818 * The speed should be forced and autoneg disabled
2819 * to configure 40G speed.
2821 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2825 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2826 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2827 /* Autoneg can be done only when the FW allows.
2828 * When user configures fixed speed of 40G and later changes to
2829 * any other speed, auto_link_speed/force_link_speed is still set
2830 * to 40G until link comes up at new speed.
2833 !(!BNXT_CHIP_THOR(bp) &&
2834 (bp->link_info.auto_link_speed ||
2835 bp->link_info.force_link_speed))) {
2836 link_req.phy_flags |=
2837 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2838 link_req.auto_link_speed_mask =
2839 bnxt_parse_eth_link_speed_mask(bp,
2840 dev_conf->link_speeds);
2842 if (bp->link_info.phy_type ==
2843 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2844 bp->link_info.phy_type ==
2845 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2846 bp->link_info.media_type ==
2847 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2848 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2852 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2853 /* If user wants a particular speed try that first. */
2855 link_req.link_speed = speed;
2856 else if (bp->link_info.force_link_speed)
2857 link_req.link_speed = bp->link_info.force_link_speed;
2859 link_req.link_speed = bp->link_info.auto_link_speed;
2861 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2862 link_req.auto_pause = bp->link_info.auto_pause;
2863 link_req.force_pause = bp->link_info.force_pause;
2866 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2869 "Set link config failed with rc %d\n", rc);
2877 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2879 struct hwrm_func_qcfg_input req = {0};
2880 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2884 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2885 req.fid = rte_cpu_to_le_16(0xffff);
2887 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2889 HWRM_CHECK_RESULT();
2891 /* Hard Coded.. 0xfff VLAN ID mask */
2892 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2893 flags = rte_le_to_cpu_16(resp->flags);
2894 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2895 bp->flags |= BNXT_FLAG_MULTI_HOST;
2898 !BNXT_VF_IS_TRUSTED(bp) &&
2899 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2900 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2901 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2902 } else if (BNXT_VF(bp) &&
2903 BNXT_VF_IS_TRUSTED(bp) &&
2904 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2905 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2906 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2910 *mtu = rte_le_to_cpu_16(resp->mtu);
2912 switch (resp->port_partition_type) {
2913 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2914 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2915 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2917 bp->port_partition_type = resp->port_partition_type;
2920 bp->port_partition_type = 0;
2929 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2930 struct hwrm_func_qcaps_output *qcaps)
2932 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2933 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2934 sizeof(qcaps->mac_address));
2935 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2936 qcaps->max_rx_rings = fcfg->num_rx_rings;
2937 qcaps->max_tx_rings = fcfg->num_tx_rings;
2938 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2939 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2941 qcaps->first_vf_id = 0;
2942 qcaps->max_vnics = fcfg->num_vnics;
2943 qcaps->max_decap_records = 0;
2944 qcaps->max_encap_records = 0;
2945 qcaps->max_tx_wm_flows = 0;
2946 qcaps->max_tx_em_flows = 0;
2947 qcaps->max_rx_wm_flows = 0;
2948 qcaps->max_rx_em_flows = 0;
2949 qcaps->max_flow_id = 0;
2950 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2951 qcaps->max_sp_tx_rings = 0;
2952 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2955 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2957 struct hwrm_func_cfg_input req = {0};
2958 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2962 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2963 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2964 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2965 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2966 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2967 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2968 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2969 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2970 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2972 if (BNXT_HAS_RING_GRPS(bp)) {
2973 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2974 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2975 } else if (BNXT_HAS_NQ(bp)) {
2976 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2977 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2980 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2981 req.mtu = rte_cpu_to_le_16(RTE_MIN(bp->eth_dev->data->mtu,
2982 BNXT_MAX_MTU)); //FW adds hdr sizes
2983 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
2984 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2985 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2986 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2987 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2988 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2989 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2990 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2991 req.fid = rte_cpu_to_le_16(0xffff);
2992 req.enables = rte_cpu_to_le_32(enables);
2994 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2996 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2998 HWRM_CHECK_RESULT();
3004 static void populate_vf_func_cfg_req(struct bnxt *bp,
3005 struct hwrm_func_cfg_input *req,
3008 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3009 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3010 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3011 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3012 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3013 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3014 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3015 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3016 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3017 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3019 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3020 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3022 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3023 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3025 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3026 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3028 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3029 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3030 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3031 /* TODO: For now, do not support VMDq/RFS on VFs. */
3032 req->num_vnics = rte_cpu_to_le_16(1);
3033 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3037 static void add_random_mac_if_needed(struct bnxt *bp,
3038 struct hwrm_func_cfg_input *cfg_req,
3041 struct rte_ether_addr mac;
3043 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3046 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3048 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3049 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3050 bp->pf.vf_info[vf].random_mac = true;
3052 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3053 RTE_ETHER_ADDR_LEN);
3057 static void reserve_resources_from_vf(struct bnxt *bp,
3058 struct hwrm_func_cfg_input *cfg_req,
3061 struct hwrm_func_qcaps_input req = {0};
3062 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3065 /* Get the actual allocated values now */
3066 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3067 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3068 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3071 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3072 copy_func_cfg_to_qcaps(cfg_req, resp);
3073 } else if (resp->error_code) {
3074 rc = rte_le_to_cpu_16(resp->error_code);
3075 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3076 copy_func_cfg_to_qcaps(cfg_req, resp);
3079 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3080 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3081 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3082 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3083 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3084 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3086 * TODO: While not supporting VMDq with VFs, max_vnics is always
3087 * forced to 1 in this case
3089 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3090 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3095 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3097 struct hwrm_func_qcfg_input req = {0};
3098 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3101 /* Check for zero MAC address */
3102 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3103 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3104 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3105 HWRM_CHECK_RESULT();
3106 rc = rte_le_to_cpu_16(resp->vlan);
3113 static int update_pf_resource_max(struct bnxt *bp)
3115 struct hwrm_func_qcfg_input req = {0};
3116 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3119 /* And copy the allocated numbers into the pf struct */
3120 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3121 req.fid = rte_cpu_to_le_16(0xffff);
3122 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3123 HWRM_CHECK_RESULT();
3125 /* Only TX ring value reflects actual allocation? TODO */
3126 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3127 bp->pf.evb_mode = resp->evb_mode;
3134 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3139 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3143 rc = bnxt_hwrm_func_qcaps(bp);
3147 bp->pf.func_cfg_flags &=
3148 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3149 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3150 bp->pf.func_cfg_flags |=
3151 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3152 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3153 rc = __bnxt_hwrm_func_qcaps(bp);
3157 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3159 struct hwrm_func_cfg_input req = {0};
3160 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3167 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3171 rc = bnxt_hwrm_func_qcaps(bp);
3176 bp->pf.active_vfs = num_vfs;
3179 * First, configure the PF to only use one TX ring. This ensures that
3180 * there are enough rings for all VFs.
3182 * If we don't do this, when we call func_alloc() later, we will lock
3183 * extra rings to the PF that won't be available during func_cfg() of
3186 * This has been fixed with firmware versions above 20.6.54
3188 bp->pf.func_cfg_flags &=
3189 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3190 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3191 bp->pf.func_cfg_flags |=
3192 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3193 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3198 * Now, create and register a buffer to hold forwarded VF requests
3200 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3201 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3202 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3203 if (bp->pf.vf_req_buf == NULL) {
3207 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3208 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3209 for (i = 0; i < num_vfs; i++)
3210 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3211 (i * HWRM_MAX_REQ_LEN);
3213 rc = bnxt_hwrm_func_buf_rgtr(bp);
3217 populate_vf_func_cfg_req(bp, &req, num_vfs);
3219 bp->pf.active_vfs = 0;
3220 for (i = 0; i < num_vfs; i++) {
3221 add_random_mac_if_needed(bp, &req, i);
3223 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3224 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3225 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3226 rc = bnxt_hwrm_send_message(bp,
3231 /* Clear enable flag for next pass */
3232 req.enables &= ~rte_cpu_to_le_32(
3233 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3235 if (rc || resp->error_code) {
3237 "Failed to initizlie VF %d\n", i);
3239 "Not all VFs available. (%d, %d)\n",
3240 rc, resp->error_code);
3247 reserve_resources_from_vf(bp, &req, i);
3248 bp->pf.active_vfs++;
3249 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3253 * Now configure the PF to use "the rest" of the resources
3254 * We're using STD_TX_RING_MODE here though which will limit the TX
3255 * rings. This will allow QoS to function properly. Not setting this
3256 * will cause PF rings to break bandwidth settings.
3258 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3262 rc = update_pf_resource_max(bp);
3269 bnxt_hwrm_func_buf_unrgtr(bp);
3273 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3275 struct hwrm_func_cfg_input req = {0};
3276 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3279 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3281 req.fid = rte_cpu_to_le_16(0xffff);
3282 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3283 req.evb_mode = bp->pf.evb_mode;
3285 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3286 HWRM_CHECK_RESULT();
3292 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3293 uint8_t tunnel_type)
3295 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3296 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3299 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3300 req.tunnel_type = tunnel_type;
3301 req.tunnel_dst_port_val = port;
3302 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3303 HWRM_CHECK_RESULT();
3305 switch (tunnel_type) {
3306 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3307 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3308 bp->vxlan_port = port;
3310 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3311 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3312 bp->geneve_port = port;
3323 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3324 uint8_t tunnel_type)
3326 struct hwrm_tunnel_dst_port_free_input req = {0};
3327 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3330 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3332 req.tunnel_type = tunnel_type;
3333 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3334 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3336 HWRM_CHECK_RESULT();
3342 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3345 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3346 struct hwrm_func_cfg_input req = {0};
3349 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3351 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3352 req.flags = rte_cpu_to_le_32(flags);
3353 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3355 HWRM_CHECK_RESULT();
3361 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3363 uint32_t *flag = flagp;
3365 vnic->flags = *flag;
3368 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3370 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3373 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3376 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3377 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3379 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3381 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3382 req.req_buf_page_size = rte_cpu_to_le_16(
3383 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3384 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3385 req.req_buf_page_addr0 =
3386 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3387 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3389 "unable to map buffer address to physical memory\n");
3393 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3395 HWRM_CHECK_RESULT();
3401 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3404 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3405 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3407 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3410 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3412 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3414 HWRM_CHECK_RESULT();
3420 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3422 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3423 struct hwrm_func_cfg_input req = {0};
3426 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3428 req.fid = rte_cpu_to_le_16(0xffff);
3429 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3430 req.enables = rte_cpu_to_le_32(
3431 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3432 req.async_event_cr = rte_cpu_to_le_16(
3433 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3434 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3436 HWRM_CHECK_RESULT();
3442 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3444 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3445 struct hwrm_func_vf_cfg_input req = {0};
3448 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3450 req.enables = rte_cpu_to_le_32(
3451 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3452 req.async_event_cr = rte_cpu_to_le_16(
3453 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3454 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3456 HWRM_CHECK_RESULT();
3462 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3464 struct hwrm_func_cfg_input req = {0};
3465 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3466 uint16_t dflt_vlan, fid;
3467 uint32_t func_cfg_flags;
3470 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3473 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3474 fid = bp->pf.vf_info[vf].fid;
3475 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3477 fid = rte_cpu_to_le_16(0xffff);
3478 func_cfg_flags = bp->pf.func_cfg_flags;
3479 dflt_vlan = bp->vlan;
3482 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3483 req.fid = rte_cpu_to_le_16(fid);
3484 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3485 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3487 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3489 HWRM_CHECK_RESULT();
3495 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3496 uint16_t max_bw, uint16_t enables)
3498 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3499 struct hwrm_func_cfg_input req = {0};
3502 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3504 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3505 req.enables |= rte_cpu_to_le_32(enables);
3506 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3507 req.max_bw = rte_cpu_to_le_32(max_bw);
3508 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3510 HWRM_CHECK_RESULT();
3516 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3518 struct hwrm_func_cfg_input req = {0};
3519 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3522 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3524 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3525 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3526 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3527 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3529 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3531 HWRM_CHECK_RESULT();
3537 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3542 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3544 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3549 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3550 void *encaped, size_t ec_size)
3553 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3554 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3556 if (ec_size > sizeof(req.encap_request))
3559 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3561 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3562 memcpy(req.encap_request, encaped, ec_size);
3564 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3566 HWRM_CHECK_RESULT();
3572 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3573 struct rte_ether_addr *mac)
3575 struct hwrm_func_qcfg_input req = {0};
3576 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3579 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3581 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3582 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3584 HWRM_CHECK_RESULT();
3586 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3593 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3594 void *encaped, size_t ec_size)
3597 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3598 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3600 if (ec_size > sizeof(req.encap_request))
3603 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3605 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3606 memcpy(req.encap_request, encaped, ec_size);
3608 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3610 HWRM_CHECK_RESULT();
3616 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3617 struct rte_eth_stats *stats, uint8_t rx)
3620 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3621 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3623 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3625 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3627 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3629 HWRM_CHECK_RESULT();
3632 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3633 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3634 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3635 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3636 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3637 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3638 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3639 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3641 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3642 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3643 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3644 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3645 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3646 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3654 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3656 struct hwrm_port_qstats_input req = {0};
3657 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3658 struct bnxt_pf_info *pf = &bp->pf;
3661 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3663 req.port_id = rte_cpu_to_le_16(pf->port_id);
3664 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3665 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3666 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3668 HWRM_CHECK_RESULT();
3674 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3676 struct hwrm_port_clr_stats_input req = {0};
3677 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3678 struct bnxt_pf_info *pf = &bp->pf;
3681 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3682 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3683 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3686 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3688 req.port_id = rte_cpu_to_le_16(pf->port_id);
3689 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3691 HWRM_CHECK_RESULT();
3697 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3699 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3700 struct hwrm_port_led_qcaps_input req = {0};
3706 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3707 req.port_id = bp->pf.port_id;
3708 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3710 HWRM_CHECK_RESULT();
3712 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3715 bp->num_leds = resp->num_leds;
3716 memcpy(bp->leds, &resp->led0_id,
3717 sizeof(bp->leds[0]) * bp->num_leds);
3718 for (i = 0; i < bp->num_leds; i++) {
3719 struct bnxt_led_info *led = &bp->leds[i];
3721 uint16_t caps = led->led_state_caps;
3723 if (!led->led_group_id ||
3724 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3736 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3738 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3739 struct hwrm_port_led_cfg_input req = {0};
3740 struct bnxt_led_cfg *led_cfg;
3741 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3742 uint16_t duration = 0;
3745 if (!bp->num_leds || BNXT_VF(bp))
3748 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3751 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3752 duration = rte_cpu_to_le_16(500);
3754 req.port_id = bp->pf.port_id;
3755 req.num_leds = bp->num_leds;
3756 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3757 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3758 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3759 led_cfg->led_id = bp->leds[i].led_id;
3760 led_cfg->led_state = led_state;
3761 led_cfg->led_blink_on = duration;
3762 led_cfg->led_blink_off = duration;
3763 led_cfg->led_group_id = bp->leds[i].led_group_id;
3766 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3768 HWRM_CHECK_RESULT();
3774 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3778 struct hwrm_nvm_get_dir_info_input req = {0};
3779 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3781 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3783 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3785 HWRM_CHECK_RESULT();
3787 *entries = rte_le_to_cpu_32(resp->entries);
3788 *length = rte_le_to_cpu_32(resp->entry_length);
3794 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3797 uint32_t dir_entries;
3798 uint32_t entry_length;
3801 rte_iova_t dma_handle;
3802 struct hwrm_nvm_get_dir_entries_input req = {0};
3803 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3805 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3809 *data++ = dir_entries;
3810 *data++ = entry_length;
3812 memset(data, 0xff, len);
3814 buflen = dir_entries * entry_length;
3815 buf = rte_malloc("nvm_dir", buflen, 0);
3816 rte_mem_lock_page(buf);
3819 dma_handle = rte_mem_virt2iova(buf);
3820 if (dma_handle == RTE_BAD_IOVA) {
3822 "unable to map response address to physical memory\n");
3825 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3826 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3827 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3830 memcpy(data, buf, len > buflen ? buflen : len);
3833 HWRM_CHECK_RESULT();
3839 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3840 uint32_t offset, uint32_t length,
3845 rte_iova_t dma_handle;
3846 struct hwrm_nvm_read_input req = {0};
3847 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3849 buf = rte_malloc("nvm_item", length, 0);
3850 rte_mem_lock_page(buf);
3854 dma_handle = rte_mem_virt2iova(buf);
3855 if (dma_handle == RTE_BAD_IOVA) {
3857 "unable to map response address to physical memory\n");
3860 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3861 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3862 req.dir_idx = rte_cpu_to_le_16(index);
3863 req.offset = rte_cpu_to_le_32(offset);
3864 req.len = rte_cpu_to_le_32(length);
3865 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3867 memcpy(data, buf, length);
3870 HWRM_CHECK_RESULT();
3876 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3879 struct hwrm_nvm_erase_dir_entry_input req = {0};
3880 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3882 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3883 req.dir_idx = rte_cpu_to_le_16(index);
3884 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3885 HWRM_CHECK_RESULT();
3892 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3893 uint16_t dir_ordinal, uint16_t dir_ext,
3894 uint16_t dir_attr, const uint8_t *data,
3898 struct hwrm_nvm_write_input req = {0};
3899 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3900 rte_iova_t dma_handle;
3903 buf = rte_malloc("nvm_write", data_len, 0);
3904 rte_mem_lock_page(buf);
3908 dma_handle = rte_mem_virt2iova(buf);
3909 if (dma_handle == RTE_BAD_IOVA) {
3911 "unable to map response address to physical memory\n");
3914 memcpy(buf, data, data_len);
3916 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3918 req.dir_type = rte_cpu_to_le_16(dir_type);
3919 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3920 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3921 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3922 req.dir_data_length = rte_cpu_to_le_32(data_len);
3923 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3925 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3928 HWRM_CHECK_RESULT();
3935 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3937 uint32_t *count = cbdata;
3939 *count = *count + 1;
3942 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3943 struct bnxt_vnic_info *vnic __rte_unused)
3948 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3952 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3953 &count, bnxt_vnic_count_hwrm_stub);
3958 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3961 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3962 struct hwrm_func_vf_vnic_ids_query_output *resp =
3963 bp->hwrm_cmd_resp_addr;
3966 /* First query all VNIC ids */
3967 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3969 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3970 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3971 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3973 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3976 "unable to map VNIC ID table address to physical memory\n");
3979 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3980 HWRM_CHECK_RESULT();
3981 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3989 * This function queries the VNIC IDs for a specified VF. It then calls
3990 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3991 * Then it calls the hwrm_cb function to program this new vnic configuration.
3993 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3994 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3995 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3997 struct bnxt_vnic_info vnic;
3999 int i, num_vnic_ids;
4004 /* First query all VNIC ids */
4005 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4006 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4007 RTE_CACHE_LINE_SIZE);
4008 if (vnic_ids == NULL)
4011 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4012 rte_mem_lock_page(((char *)vnic_ids) + sz);
4014 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4016 if (num_vnic_ids < 0)
4017 return num_vnic_ids;
4019 /* Retrieve VNIC, update bd_stall then update */
4021 for (i = 0; i < num_vnic_ids; i++) {
4022 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4023 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4024 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4027 if (vnic.mru <= 4) /* Indicates unallocated */
4030 vnic_cb(&vnic, cbdata);
4032 rc = hwrm_cb(bp, &vnic);
4042 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4045 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4046 struct hwrm_func_cfg_input req = {0};
4049 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4051 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4052 req.enables |= rte_cpu_to_le_32(
4053 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4054 req.vlan_antispoof_mode = on ?
4055 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4056 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4057 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4059 HWRM_CHECK_RESULT();
4065 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4067 struct bnxt_vnic_info vnic;
4070 int num_vnic_ids, i;
4074 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4075 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4076 RTE_CACHE_LINE_SIZE);
4077 if (vnic_ids == NULL)
4080 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4081 rte_mem_lock_page(((char *)vnic_ids) + sz);
4083 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4089 * Loop through to find the default VNIC ID.
4090 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4091 * by sending the hwrm_func_qcfg command to the firmware.
4093 for (i = 0; i < num_vnic_ids; i++) {
4094 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4095 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4096 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4097 bp->pf.first_vf_id + vf);
4100 if (vnic.func_default) {
4102 return vnic.fw_vnic_id;
4105 /* Could not find a default VNIC. */
4106 PMD_DRV_LOG(ERR, "No default VNIC\n");
4112 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4114 struct bnxt_filter_info *filter)
4117 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4118 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4119 uint32_t enables = 0;
4121 if (filter->fw_em_filter_id != UINT64_MAX)
4122 bnxt_hwrm_clear_em_filter(bp, filter);
4124 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4126 req.flags = rte_cpu_to_le_32(filter->flags);
4128 enables = filter->enables |
4129 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4130 req.dst_id = rte_cpu_to_le_16(dst_id);
4132 if (filter->ip_addr_type) {
4133 req.ip_addr_type = filter->ip_addr_type;
4134 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4137 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4138 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4140 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4141 memcpy(req.src_macaddr, filter->src_macaddr,
4142 RTE_ETHER_ADDR_LEN);
4144 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4145 memcpy(req.dst_macaddr, filter->dst_macaddr,
4146 RTE_ETHER_ADDR_LEN);
4148 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4149 req.ovlan_vid = filter->l2_ovlan;
4151 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4152 req.ivlan_vid = filter->l2_ivlan;
4154 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4155 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4157 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4158 req.ip_protocol = filter->ip_protocol;
4160 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4161 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4163 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4164 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4166 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4167 req.src_port = rte_cpu_to_be_16(filter->src_port);
4169 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4170 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4172 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4173 req.mirror_vnic_id = filter->mirror_vnic_id;
4175 req.enables = rte_cpu_to_le_32(enables);
4177 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4179 HWRM_CHECK_RESULT();
4181 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4187 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4190 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4191 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4193 if (filter->fw_em_filter_id == UINT64_MAX)
4196 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4197 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4199 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4201 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4203 HWRM_CHECK_RESULT();
4206 filter->fw_em_filter_id = UINT64_MAX;
4207 filter->fw_l2_filter_id = UINT64_MAX;
4212 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4214 struct bnxt_filter_info *filter)
4217 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4218 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4219 bp->hwrm_cmd_resp_addr;
4220 uint32_t enables = 0;
4222 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4223 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4225 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4227 req.flags = rte_cpu_to_le_32(filter->flags);
4229 enables = filter->enables |
4230 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4231 req.dst_id = rte_cpu_to_le_16(dst_id);
4233 if (filter->ip_addr_type) {
4234 req.ip_addr_type = filter->ip_addr_type;
4236 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4239 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4240 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4242 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4243 memcpy(req.src_macaddr, filter->src_macaddr,
4244 RTE_ETHER_ADDR_LEN);
4246 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4247 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4249 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4250 req.ip_protocol = filter->ip_protocol;
4252 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4253 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4255 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4256 req.src_ipaddr_mask[0] =
4257 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4259 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4260 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4262 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4263 req.dst_ipaddr_mask[0] =
4264 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4266 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4267 req.src_port = rte_cpu_to_le_16(filter->src_port);
4269 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4270 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4272 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4273 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4275 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4276 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4278 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4279 req.mirror_vnic_id = filter->mirror_vnic_id;
4281 req.enables = rte_cpu_to_le_32(enables);
4283 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4285 HWRM_CHECK_RESULT();
4287 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4293 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4294 struct bnxt_filter_info *filter)
4297 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4298 struct hwrm_cfa_ntuple_filter_free_output *resp =
4299 bp->hwrm_cmd_resp_addr;
4301 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4304 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4306 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4308 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4310 HWRM_CHECK_RESULT();
4313 filter->fw_ntuple_filter_id = UINT64_MAX;
4319 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4321 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4322 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4323 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4324 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4325 uint16_t *ring_tbl = vnic->rss_table;
4326 int nr_ctxs = vnic->num_lb_ctxts;
4327 int max_rings = bp->rx_nr_rings;
4331 for (i = 0, k = 0; i < nr_ctxs; i++) {
4332 struct bnxt_rx_ring_info *rxr;
4333 struct bnxt_cp_ring_info *cpr;
4335 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4337 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4338 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4339 req.hash_mode_flags = vnic->hash_mode;
4341 req.ring_grp_tbl_addr =
4342 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4343 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4344 2 * sizeof(*ring_tbl));
4345 req.hash_key_tbl_addr =
4346 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4348 req.ring_table_pair_index = i;
4349 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4351 for (j = 0; j < 64; j++) {
4354 /* Find next active ring. */
4355 for (cnt = 0; cnt < max_rings; cnt++) {
4356 if (rx_queue_state[k] !=
4357 RTE_ETH_QUEUE_STATE_STOPPED)
4359 if (++k == max_rings)
4363 /* Return if no rings are active. */
4364 if (cnt == max_rings) {
4369 /* Add rx/cp ring pair to RSS table. */
4370 rxr = rxqs[k]->rx_ring;
4371 cpr = rxqs[k]->cp_ring;
4373 ring_id = rxr->rx_ring_struct->fw_ring_id;
4374 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4375 ring_id = cpr->cp_ring_struct->fw_ring_id;
4376 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4378 if (++k == max_rings)
4381 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4384 HWRM_CHECK_RESULT();
4391 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4393 unsigned int rss_idx, fw_idx, i;
4395 if (!(vnic->rss_table && vnic->hash_type))
4398 if (BNXT_CHIP_THOR(bp))
4399 return bnxt_vnic_rss_configure_thor(bp, vnic);
4401 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4404 if (vnic->rss_table && vnic->hash_type) {
4406 * Fill the RSS hash & redirection table with
4407 * ring group ids for all VNICs
4409 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4410 rss_idx++, fw_idx++) {
4411 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4412 fw_idx %= bp->rx_cp_nr_rings;
4413 if (vnic->fw_grp_ids[fw_idx] !=
4418 if (i == bp->rx_cp_nr_rings)
4420 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4422 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4428 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4429 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4433 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4435 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4436 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4438 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4439 req->num_cmpl_dma_aggr_during_int =
4440 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4442 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4444 /* min timer set to 1/2 of interrupt timer */
4445 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4447 /* buf timer set to 1/4 of interrupt timer */
4448 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4450 req->cmpl_aggr_dma_tmr_during_int =
4451 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4453 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4454 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4455 req->flags = rte_cpu_to_le_16(flags);
4458 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4459 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4461 struct hwrm_ring_aggint_qcaps_input req = {0};
4462 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4467 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4468 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4469 HWRM_CHECK_RESULT();
4471 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4472 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4474 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4475 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4476 agg_req->flags = rte_cpu_to_le_16(flags);
4478 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4479 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4480 agg_req->enables = rte_cpu_to_le_32(enables);
4486 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4487 struct bnxt_coal *coal, uint16_t ring_id)
4489 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4490 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4491 bp->hwrm_cmd_resp_addr;
4494 /* Set ring coalesce parameters only for 100G NICs */
4495 if (BNXT_CHIP_THOR(bp)) {
4496 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4498 } else if (bnxt_stratus_device(bp)) {
4499 bnxt_hwrm_set_coal_params(coal, &req);
4504 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4505 req.ring_id = rte_cpu_to_le_16(ring_id);
4506 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4507 HWRM_CHECK_RESULT();
4512 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4513 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4515 struct hwrm_func_backing_store_qcaps_input req = {0};
4516 struct hwrm_func_backing_store_qcaps_output *resp =
4517 bp->hwrm_cmd_resp_addr;
4518 struct bnxt_ctx_pg_info *ctx_pg;
4519 struct bnxt_ctx_mem_info *ctx;
4520 int total_alloc_len;
4523 if (!BNXT_CHIP_THOR(bp) ||
4524 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4529 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4530 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4531 HWRM_CHECK_RESULT_SILENT();
4533 total_alloc_len = sizeof(*ctx);
4534 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4535 RTE_CACHE_LINE_SIZE);
4541 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4542 sizeof(*ctx_pg) * BNXT_MAX_Q,
4543 RTE_CACHE_LINE_SIZE);
4548 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4549 ctx->tqm_mem[i] = ctx_pg;
4552 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4553 ctx->qp_min_qp1_entries =
4554 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4555 ctx->qp_max_l2_entries =
4556 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4557 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4558 ctx->srq_max_l2_entries =
4559 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4560 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4561 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4562 ctx->cq_max_l2_entries =
4563 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4564 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4565 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4566 ctx->vnic_max_vnic_entries =
4567 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4568 ctx->vnic_max_ring_table_entries =
4569 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4570 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4571 ctx->stat_max_entries =
4572 rte_le_to_cpu_32(resp->stat_max_entries);
4573 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4574 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4575 ctx->tqm_min_entries_per_ring =
4576 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4577 ctx->tqm_max_entries_per_ring =
4578 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4579 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4580 if (!ctx->tqm_entries_multiple)
4581 ctx->tqm_entries_multiple = 1;
4582 ctx->mrav_max_entries =
4583 rte_le_to_cpu_32(resp->mrav_max_entries);
4584 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4585 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4586 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4592 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4594 struct hwrm_func_backing_store_cfg_input req = {0};
4595 struct hwrm_func_backing_store_cfg_output *resp =
4596 bp->hwrm_cmd_resp_addr;
4597 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4598 struct bnxt_ctx_pg_info *ctx_pg;
4599 uint32_t *num_entries;
4608 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4609 req.enables = rte_cpu_to_le_32(enables);
4611 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4612 ctx_pg = &ctx->qp_mem;
4613 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4614 req.qp_num_qp1_entries =
4615 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4616 req.qp_num_l2_entries =
4617 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4618 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4619 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4620 &req.qpc_pg_size_qpc_lvl,
4624 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4625 ctx_pg = &ctx->srq_mem;
4626 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4627 req.srq_num_l2_entries =
4628 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4629 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4630 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4631 &req.srq_pg_size_srq_lvl,
4635 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4636 ctx_pg = &ctx->cq_mem;
4637 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4638 req.cq_num_l2_entries =
4639 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4640 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4641 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4642 &req.cq_pg_size_cq_lvl,
4646 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4647 ctx_pg = &ctx->vnic_mem;
4648 req.vnic_num_vnic_entries =
4649 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4650 req.vnic_num_ring_table_entries =
4651 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4652 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4653 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4654 &req.vnic_pg_size_vnic_lvl,
4655 &req.vnic_page_dir);
4658 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4659 ctx_pg = &ctx->stat_mem;
4660 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4661 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4662 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4663 &req.stat_pg_size_stat_lvl,
4664 &req.stat_page_dir);
4667 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4668 num_entries = &req.tqm_sp_num_entries;
4669 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4670 pg_dir = &req.tqm_sp_page_dir;
4671 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4672 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4673 if (!(enables & ena))
4676 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4678 ctx_pg = ctx->tqm_mem[i];
4679 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4680 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4683 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4684 HWRM_CHECK_RESULT();
4690 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4692 struct hwrm_port_qstats_ext_input req = {0};
4693 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4694 struct bnxt_pf_info *pf = &bp->pf;
4697 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4698 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4701 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4703 req.port_id = rte_cpu_to_le_16(pf->port_id);
4704 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4705 req.tx_stat_host_addr =
4706 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4708 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4710 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4711 req.rx_stat_host_addr =
4712 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4714 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4716 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4719 bp->fw_rx_port_stats_ext_size = 0;
4720 bp->fw_tx_port_stats_ext_size = 0;
4722 bp->fw_rx_port_stats_ext_size =
4723 rte_le_to_cpu_16(resp->rx_stat_size);
4724 bp->fw_tx_port_stats_ext_size =
4725 rte_le_to_cpu_16(resp->tx_stat_size);
4728 HWRM_CHECK_RESULT();
4735 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4737 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4738 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4739 bp->hwrm_cmd_resp_addr;
4742 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4743 req.tunnel_type = type;
4744 req.dest_fid = bp->fw_fid;
4745 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4746 HWRM_CHECK_RESULT();
4754 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4756 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4757 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4758 bp->hwrm_cmd_resp_addr;
4761 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4762 req.tunnel_type = type;
4763 req.dest_fid = bp->fw_fid;
4764 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4765 HWRM_CHECK_RESULT();
4772 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4774 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4775 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4776 bp->hwrm_cmd_resp_addr;
4779 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4780 req.src_fid = bp->fw_fid;
4781 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4782 HWRM_CHECK_RESULT();
4785 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4792 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4795 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4796 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4797 bp->hwrm_cmd_resp_addr;
4800 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4801 req.src_fid = bp->fw_fid;
4802 req.tunnel_type = tun_type;
4803 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4804 HWRM_CHECK_RESULT();
4807 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4809 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4816 int bnxt_hwrm_set_mac(struct bnxt *bp)
4818 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4819 struct hwrm_func_vf_cfg_input req = {0};
4825 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4828 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4829 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4831 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4833 HWRM_CHECK_RESULT();
4835 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4841 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4843 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4844 struct hwrm_func_drv_if_change_input req = {0};
4848 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4851 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4852 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4853 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4855 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4858 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4862 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4864 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4866 HWRM_CHECK_RESULT();
4867 flags = rte_le_to_cpu_32(resp->flags);
4873 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4874 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4875 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4881 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4883 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4884 struct bnxt_error_recovery_info *info = bp->recovery_info;
4885 struct hwrm_error_recovery_qcfg_input req = {0};
4890 /* Older FW does not have error recovery support */
4891 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4895 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4897 bp->recovery_info = info;
4901 memset(info, 0, sizeof(*info));
4904 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4906 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4908 HWRM_CHECK_RESULT();
4910 flags = rte_le_to_cpu_32(resp->flags);
4911 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4912 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4913 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4914 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4916 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4917 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4922 /* FW returned values are in units of 100msec */
4923 info->driver_polling_freq =
4924 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4925 info->master_func_wait_period =
4926 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4927 info->normal_func_wait_period =
4928 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4929 info->master_func_wait_period_after_reset =
4930 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4931 info->max_bailout_time_after_reset =
4932 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4933 info->status_regs[BNXT_FW_STATUS_REG] =
4934 rte_le_to_cpu_32(resp->fw_health_status_reg);
4935 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4936 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4937 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4938 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4939 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4940 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4941 info->reg_array_cnt =
4942 rte_le_to_cpu_32(resp->reg_array_cnt);
4944 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4949 for (i = 0; i < info->reg_array_cnt; i++) {
4950 info->reset_reg[i] =
4951 rte_le_to_cpu_32(resp->reset_reg[i]);
4952 info->reset_reg_val[i] =
4953 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4954 info->delay_after_reset[i] =
4955 resp->delay_after_reset[i];
4960 /* Map the FW status registers */
4962 rc = bnxt_map_fw_health_status_regs(bp);
4965 rte_free(bp->recovery_info);
4966 bp->recovery_info = NULL;
4971 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4973 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4974 struct hwrm_fw_reset_input req = {0};
4980 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4982 req.embedded_proc_type =
4983 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4984 req.selfrst_status =
4985 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4986 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4988 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4991 HWRM_CHECK_RESULT();
4997 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4999 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5000 struct hwrm_port_ts_query_input req = {0};
5001 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5008 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5011 case BNXT_PTP_FLAGS_PATH_TX:
5012 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5014 case BNXT_PTP_FLAGS_PATH_RX:
5015 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5017 case BNXT_PTP_FLAGS_CURRENT_TIME:
5018 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5022 req.flags = rte_cpu_to_le_32(flags);
5023 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5025 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5027 HWRM_CHECK_RESULT();
5030 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5032 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5039 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5041 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5042 bp->hwrm_cmd_resp_addr;
5043 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5047 if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5050 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5052 "Not a PF or trusted VF. Command not supported\n");
5056 HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5057 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5059 HWRM_CHECK_RESULT();
5060 flags = rte_le_to_cpu_32(resp->flags);
5063 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5064 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5065 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");