4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_byteorder.h>
39 #include <rte_common.h>
40 #include <rte_cycles.h>
41 #include <rte_malloc.h>
42 #include <rte_memzone.h>
43 #include <rte_version.h>
47 #include "bnxt_filter.h"
48 #include "bnxt_hwrm.h"
51 #include "bnxt_ring.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
59 #define HWRM_CMD_TIMEOUT 2000
61 struct bnxt_plcmodes_cfg {
63 uint16_t jumbo_thresh;
65 uint16_t hds_threshold;
68 static int page_getenum(size_t size)
84 RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
85 return sizeof(void *) * 8 - 1;
88 static int page_roundup(size_t size)
90 return 1 << page_getenum(size);
94 * HWRM Functions (sent to HWRM)
95 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
96 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
97 * command was failed by the ChiMP.
100 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
104 struct input *req = msg;
105 struct output *resp = bp->hwrm_cmd_resp_addr;
106 uint32_t *data = msg;
110 /* Write request msg to hwrm channel */
111 for (i = 0; i < msg_len; i += 4) {
112 bar = (uint8_t *)bp->bar0 + i;
113 rte_write32(*data, bar);
117 /* Zero the rest of the request space */
118 for (; i < bp->max_req_len; i += 4) {
119 bar = (uint8_t *)bp->bar0 + i;
123 /* Ring channel doorbell */
124 bar = (uint8_t *)bp->bar0 + 0x100;
127 /* Poll for the valid bit */
128 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
129 /* Sanity check on the resp->resp_len */
131 if (resp->resp_len && resp->resp_len <=
133 /* Last byte of resp contains the valid key */
134 valid = (uint8_t *)resp + resp->resp_len - 1;
135 if (*valid == HWRM_RESP_VALID_KEY)
141 if (i >= HWRM_CMD_TIMEOUT) {
142 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
152 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
156 rte_spinlock_lock(&bp->hwrm_lock);
157 rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
158 rte_spinlock_unlock(&bp->hwrm_lock);
162 #define HWRM_PREP(req, type, cr, resp) \
163 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
164 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
165 req.cmpl_ring = rte_cpu_to_le_16(cr); \
166 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
167 req.target_id = rte_cpu_to_le_16(0xffff); \
168 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
170 #define HWRM_CHECK_RESULT \
173 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
177 if (resp->error_code) { \
178 rc = rte_le_to_cpu_16(resp->error_code); \
179 if (resp->resp_len >= 16) { \
180 struct hwrm_err_output *tmp_hwrm_err_op = \
183 "%s error %d:%d:%08x:%04x\n", \
185 rc, tmp_hwrm_err_op->cmd_err, \
187 tmp_hwrm_err_op->opaque_0), \
189 tmp_hwrm_err_op->opaque_1)); \
193 "%s error %d\n", __func__, rc); \
199 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
202 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
203 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
205 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
206 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
209 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
216 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
219 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
220 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
223 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
224 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
226 /* FIXME add multicast flag, when multicast adding options is supported
229 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
230 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
231 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
232 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
233 if (vnic->mc_addr_cnt) {
234 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
235 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
236 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
238 req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
241 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
248 int bnxt_hwrm_clear_filter(struct bnxt *bp,
249 struct bnxt_filter_info *filter)
252 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
253 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
255 HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
257 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
259 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
263 filter->fw_l2_filter_id = -1;
268 int bnxt_hwrm_set_filter(struct bnxt *bp,
270 struct bnxt_filter_info *filter)
273 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
274 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
275 uint32_t enables = 0;
277 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
279 req.flags = rte_cpu_to_le_32(filter->flags);
281 enables = filter->enables |
282 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
283 req.dst_id = rte_cpu_to_le_16(dst_id);
286 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
287 memcpy(req.l2_addr, filter->l2_addr,
290 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
291 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
294 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
295 req.l2_ovlan = filter->l2_ovlan;
297 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
298 req.l2_ovlan_mask = filter->l2_ovlan_mask;
300 req.enables = rte_cpu_to_le_32(enables);
302 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
306 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
311 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
314 struct hwrm_func_qcaps_input req = {.req_type = 0 };
315 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
316 uint16_t new_max_vfs;
319 HWRM_PREP(req, FUNC_QCAPS, -1, resp);
321 req.fid = rte_cpu_to_le_16(0xffff);
323 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
327 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
329 bp->pf.port_id = resp->port_id;
330 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
331 new_max_vfs = bp->pdev->max_vfs;
332 if (new_max_vfs != bp->pf.max_vfs) {
334 rte_free(bp->pf.vf_info);
335 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
336 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
337 bp->pf.max_vfs = new_max_vfs;
338 for (i = 0; i < new_max_vfs; i++) {
339 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
340 bp->pf.vf_info[i].vlan_table =
341 rte_zmalloc("VF VLAN table",
344 if (bp->pf.vf_info[i].vlan_table == NULL)
346 "Fail to alloc VLAN table for VF %d\n",
350 bp->pf.vf_info[i].vlan_table);
351 STAILQ_INIT(&bp->pf.vf_info[i].filter);
356 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
357 memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
358 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
359 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
360 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
361 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
362 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
363 /* TODO: For now, do not support VMDq/RFS on VFs. */
368 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
372 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
374 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
379 int bnxt_hwrm_func_reset(struct bnxt *bp)
382 struct hwrm_func_reset_input req = {.req_type = 0 };
383 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
385 HWRM_PREP(req, FUNC_RESET, -1, resp);
387 req.enables = rte_cpu_to_le_32(0);
389 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
396 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
399 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
400 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
402 if (bp->flags & BNXT_FLAG_REGISTERED)
405 HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
406 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
407 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
408 req.ver_maj = RTE_VER_YEAR;
409 req.ver_min = RTE_VER_MONTH;
410 req.ver_upd = RTE_VER_MINOR;
413 req.enables |= rte_cpu_to_le_32(
414 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
415 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
416 RTE_MIN(sizeof(req.vf_req_fwd),
417 sizeof(bp->pf.vf_req_fwd)));
420 req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1); /* TODO: Use MACRO */
421 memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
423 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
427 bp->flags |= BNXT_FLAG_REGISTERED;
432 int bnxt_hwrm_ver_get(struct bnxt *bp)
435 struct hwrm_ver_get_input req = {.req_type = 0 };
436 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
439 uint16_t max_resp_len;
440 char type[RTE_MEMZONE_NAMESIZE];
442 HWRM_PREP(req, VER_GET, -1, resp);
444 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
445 req.hwrm_intf_min = HWRM_VERSION_MINOR;
446 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
449 * Hold the lock since we may be adjusting the response pointers.
451 rte_spinlock_lock(&bp->hwrm_lock);
452 rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
456 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
457 resp->hwrm_intf_maj, resp->hwrm_intf_min,
459 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
460 bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
461 (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
462 RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
463 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
465 my_version = HWRM_VERSION_MAJOR << 16;
466 my_version |= HWRM_VERSION_MINOR << 8;
467 my_version |= HWRM_VERSION_UPDATE;
469 fw_version = resp->hwrm_intf_maj << 16;
470 fw_version |= resp->hwrm_intf_min << 8;
471 fw_version |= resp->hwrm_intf_upd;
473 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
474 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
479 if (my_version != fw_version) {
480 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
481 if (my_version < fw_version) {
483 "Firmware API version is newer than driver.\n");
485 "The driver may be missing features.\n");
488 "Firmware API version is older than driver.\n");
490 "Not all driver features may be functional.\n");
494 if (bp->max_req_len > resp->max_req_win_len) {
495 RTE_LOG(ERR, PMD, "Unsupported request length\n");
498 bp->max_req_len = resp->max_req_win_len;
499 max_resp_len = resp->max_resp_len;
500 if (bp->max_resp_len != max_resp_len) {
501 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
502 bp->pdev->addr.domain, bp->pdev->addr.bus,
503 bp->pdev->addr.devid, bp->pdev->addr.function);
505 rte_free(bp->hwrm_cmd_resp_addr);
507 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
508 if (bp->hwrm_cmd_resp_addr == NULL) {
512 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
513 bp->hwrm_cmd_resp_dma_addr =
514 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
515 if (bp->hwrm_cmd_resp_dma_addr == 0) {
517 "Unable to map response buffer to physical memory.\n");
521 bp->max_resp_len = max_resp_len;
525 rte_spinlock_unlock(&bp->hwrm_lock);
529 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
532 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
533 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
535 if (!(bp->flags & BNXT_FLAG_REGISTERED))
538 HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
541 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
545 bp->flags &= ~BNXT_FLAG_REGISTERED;
550 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
553 struct hwrm_port_phy_cfg_input req = {0};
554 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
555 uint32_t enables = 0;
557 HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
560 req.flags = rte_cpu_to_le_32(conf->phy_flags);
561 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
563 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
564 * any auto mode, even "none".
566 if (!conf->link_speed) {
567 req.auto_mode |= conf->auto_mode;
568 enables = HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
569 req.auto_link_speed_mask = conf->auto_link_speed_mask;
571 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
572 req.auto_link_speed = bp->link_info.auto_link_speed;
574 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
576 req.auto_duplex = conf->duplex;
577 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
578 req.auto_pause = conf->auto_pause;
579 req.force_pause = conf->force_pause;
580 /* Set force_pause if there is no auto or if there is a force */
581 if (req.auto_pause && !req.force_pause)
582 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
584 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
586 req.enables = rte_cpu_to_le_32(enables);
589 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
590 RTE_LOG(INFO, PMD, "Force Link Down\n");
593 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
600 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
601 struct bnxt_link_info *link_info)
604 struct hwrm_port_phy_qcfg_input req = {0};
605 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
607 HWRM_PREP(req, PORT_PHY_QCFG, -1, resp);
609 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
613 link_info->phy_link_status = resp->link;
614 if (link_info->phy_link_status != HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK) {
615 link_info->link_up = 1;
616 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
618 link_info->link_up = 0;
619 link_info->link_speed = 0;
621 link_info->duplex = resp->duplex;
622 link_info->pause = resp->pause;
623 link_info->auto_pause = resp->auto_pause;
624 link_info->force_pause = resp->force_pause;
625 link_info->auto_mode = resp->auto_mode;
627 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
628 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
629 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
630 link_info->phy_ver[0] = resp->phy_maj;
631 link_info->phy_ver[1] = resp->phy_min;
632 link_info->phy_ver[2] = resp->phy_bld;
637 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
640 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
641 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
643 HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
645 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
649 #define GET_QUEUE_INFO(x) \
650 bp->cos_queue[x].id = resp->queue_id##x; \
651 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
665 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
666 struct bnxt_ring *ring,
667 uint32_t ring_type, uint32_t map_index,
668 uint32_t stats_ctx_id)
671 struct hwrm_ring_alloc_input req = {.req_type = 0 };
672 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
674 HWRM_PREP(req, RING_ALLOC, -1, resp);
676 req.enables = rte_cpu_to_le_32(0);
678 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
679 req.fbo = rte_cpu_to_le_32(0);
680 /* Association of ring index with doorbell index */
681 req.logical_id = rte_cpu_to_le_16(map_index);
684 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
685 req.queue_id = bp->cos_queue[0].id;
687 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
688 req.ring_type = ring_type;
690 rte_cpu_to_le_16(bp->grp_info[map_index].cp_fw_ring_id);
691 req.length = rte_cpu_to_le_32(ring->ring_size);
692 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
693 req.enables = rte_cpu_to_le_32(rte_le_to_cpu_32(req.enables) |
694 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID);
696 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
697 req.ring_type = ring_type;
699 * TODO: Some HWRM versions crash with
700 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
702 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
703 req.length = rte_cpu_to_le_32(ring->ring_size);
706 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
711 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
713 if (rc || resp->error_code) {
714 if (rc == 0 && resp->error_code)
715 rc = rte_le_to_cpu_16(resp->error_code);
717 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
719 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
721 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
723 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
725 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
727 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
730 RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
735 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
739 int bnxt_hwrm_ring_free(struct bnxt *bp,
740 struct bnxt_ring *ring, uint32_t ring_type)
743 struct hwrm_ring_free_input req = {.req_type = 0 };
744 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
746 HWRM_PREP(req, RING_FREE, -1, resp);
748 req.ring_type = ring_type;
749 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
751 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
753 if (rc || resp->error_code) {
754 if (rc == 0 && resp->error_code)
755 rc = rte_le_to_cpu_16(resp->error_code);
758 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
759 RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
762 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
763 RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
766 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
767 RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
771 RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
778 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
781 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
782 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
784 HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
786 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
787 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
788 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
789 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
791 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
795 bp->grp_info[idx].fw_grp_id =
796 rte_le_to_cpu_16(resp->ring_group_id);
801 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
804 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
805 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
807 HWRM_PREP(req, RING_GRP_FREE, -1, resp);
809 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
811 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
815 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
819 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
822 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
823 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
825 HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
827 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
830 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
831 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
833 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
840 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp,
841 struct bnxt_cp_ring_info *cpr, unsigned int idx)
844 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
845 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
847 HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
849 req.update_period_ms = rte_cpu_to_le_32(1000);
851 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
853 rte_cpu_to_le_64(cpr->hw_stats_map);
855 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
859 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
860 bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
865 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp,
866 struct bnxt_cp_ring_info *cpr, unsigned int idx)
869 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
870 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
872 HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
874 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
875 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
877 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
881 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
882 bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
887 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
890 struct hwrm_vnic_alloc_input req = { 0 };
891 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
893 /* map ring groups to this vnic */
894 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++) {
895 if (bp->grp_info[i].fw_grp_id == (uint16_t)HWRM_NA_SIGNATURE) {
897 "Not enough ring groups avail:%x req:%x\n", j,
898 (vnic->end_grp_id - vnic->start_grp_id) + 1);
901 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
903 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
904 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
905 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
906 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
907 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
908 ETHER_CRC_LEN + VLAN_TAG_SIZE;
909 HWRM_PREP(req, VNIC_ALLOC, -1, resp);
911 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
915 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
919 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
920 struct bnxt_vnic_info *vnic,
921 struct bnxt_plcmodes_cfg *pmode)
924 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
925 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
927 HWRM_PREP(req, VNIC_PLCMODES_QCFG, -1, resp);
929 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
931 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
935 pmode->flags = rte_le_to_cpu_32(resp->flags);
936 /* dflt_vnic bit doesn't exist in the _cfg command */
937 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
938 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
939 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
940 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
945 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
946 struct bnxt_vnic_info *vnic,
947 struct bnxt_plcmodes_cfg *pmode)
950 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
951 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
953 HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
955 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
956 req.flags = rte_cpu_to_le_32(pmode->flags);
957 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
958 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
959 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
960 req.enables = rte_cpu_to_le_32(
961 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
962 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
963 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
966 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
973 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
976 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
977 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
978 uint32_t ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
979 struct bnxt_plcmodes_cfg pmodes;
981 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
985 HWRM_PREP(req, VNIC_CFG, -1, resp);
987 /* Only RSS support for now TBD: COS & LB */
989 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
990 HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
991 if (vnic->lb_rule != 0xffff)
992 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
993 if (vnic->cos_rule != 0xffff)
994 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
995 if (vnic->rss_rule != 0xffff)
996 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
997 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
998 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
999 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1000 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1001 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1002 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1003 req.mru = rte_cpu_to_le_16(vnic->mru);
1004 if (vnic->func_default)
1006 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1007 if (vnic->vlan_strip)
1009 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1012 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1013 if (vnic->roce_dual)
1014 req.flags |= rte_cpu_to_le_32(
1015 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1016 if (vnic->roce_only)
1017 req.flags |= rte_cpu_to_le_32(
1018 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1019 if (vnic->rss_dflt_cr)
1020 req.flags |= rte_cpu_to_le_32(
1021 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1023 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1027 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1032 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1036 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1037 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1039 HWRM_PREP(req, VNIC_QCFG, -1, resp);
1042 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1043 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1044 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1046 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1050 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1051 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1052 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1053 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1054 vnic->mru = rte_le_to_cpu_16(resp->mru);
1055 vnic->func_default = rte_le_to_cpu_32(
1056 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1057 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1058 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1059 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1060 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1061 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1062 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1063 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1064 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1065 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1066 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1071 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1074 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1075 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1076 bp->hwrm_cmd_resp_addr;
1078 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
1080 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1084 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1089 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1092 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1093 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1094 bp->hwrm_cmd_resp_addr;
1096 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
1098 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1100 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1104 vnic->rss_rule = INVALID_HW_RING_ID;
1109 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1112 struct hwrm_vnic_free_input req = {.req_type = 0 };
1113 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1115 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
1118 HWRM_PREP(req, VNIC_FREE, -1, resp);
1120 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1122 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1126 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1130 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1131 struct bnxt_vnic_info *vnic)
1134 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1135 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1137 HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
1139 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1141 req.ring_grp_tbl_addr =
1142 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1143 req.hash_key_tbl_addr =
1144 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1145 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1147 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1154 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1156 struct hwrm_func_cfg_input req = {0};
1157 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1160 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1161 req.enables = rte_cpu_to_le_32(
1162 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1163 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1164 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1166 HWRM_PREP(req, FUNC_CFG, -1, resp);
1168 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1171 bp->pf.vf_info[vf].random_mac = false;
1177 * HWRM utility functions
1180 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1185 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1186 struct bnxt_tx_queue *txq;
1187 struct bnxt_rx_queue *rxq;
1188 struct bnxt_cp_ring_info *cpr;
1190 if (i >= bp->rx_cp_nr_rings) {
1191 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1194 rxq = bp->rx_queues[i];
1198 rc = bnxt_hwrm_stat_clear(bp, cpr);
1205 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1209 struct bnxt_cp_ring_info *cpr;
1211 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1212 unsigned int idx = i + 1;
1214 if (i >= bp->rx_cp_nr_rings)
1215 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1217 cpr = bp->rx_queues[i]->cp_ring;
1218 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1219 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, idx);
1227 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1232 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1233 struct bnxt_tx_queue *txq;
1234 struct bnxt_rx_queue *rxq;
1235 struct bnxt_cp_ring_info *cpr;
1236 unsigned int idx = i + 1;
1238 if (i >= bp->rx_cp_nr_rings) {
1239 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1242 rxq = bp->rx_queues[i];
1246 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, idx);
1254 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1259 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1260 unsigned int idx = i + 1;
1262 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1264 "Attempt to free invalid ring group %d\n",
1269 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1277 static void bnxt_free_cp_ring(struct bnxt *bp,
1278 struct bnxt_cp_ring_info *cpr, unsigned int idx)
1280 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1282 bnxt_hwrm_ring_free(bp, cp_ring,
1283 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1284 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1285 bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1286 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1287 sizeof(*cpr->cp_desc_ring));
1288 cpr->cp_raw_cons = 0;
1291 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1296 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1297 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1298 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1299 struct bnxt_ring *ring = txr->tx_ring_struct;
1300 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1301 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1303 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1304 bnxt_hwrm_ring_free(bp, ring,
1305 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1306 ring->fw_ring_id = INVALID_HW_RING_ID;
1307 memset(txr->tx_desc_ring, 0,
1308 txr->tx_ring_struct->ring_size *
1309 sizeof(*txr->tx_desc_ring));
1310 memset(txr->tx_buf_ring, 0,
1311 txr->tx_ring_struct->ring_size *
1312 sizeof(*txr->tx_buf_ring));
1316 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1317 bnxt_free_cp_ring(bp, cpr, idx);
1320 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1321 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1322 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1323 struct bnxt_ring *ring = rxr->rx_ring_struct;
1324 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1325 unsigned int idx = i + 1;
1327 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1328 bnxt_hwrm_ring_free(bp, ring,
1329 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1330 ring->fw_ring_id = INVALID_HW_RING_ID;
1331 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1332 memset(rxr->rx_desc_ring, 0,
1333 rxr->rx_ring_struct->ring_size *
1334 sizeof(*rxr->rx_desc_ring));
1335 memset(rxr->rx_buf_ring, 0,
1336 rxr->rx_ring_struct->ring_size *
1337 sizeof(*rxr->rx_buf_ring));
1340 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1341 bnxt_free_cp_ring(bp, cpr, idx);
1344 /* Default completion ring */
1346 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1348 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1349 bnxt_free_cp_ring(bp, cpr, 0);
1355 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1360 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1361 unsigned int idx = i + 1;
1363 if (bp->grp_info[idx].cp_fw_ring_id == INVALID_HW_RING_ID ||
1364 bp->grp_info[idx].rx_fw_ring_id == INVALID_HW_RING_ID)
1367 rc = bnxt_hwrm_ring_grp_alloc(bp, idx);
1375 void bnxt_free_hwrm_resources(struct bnxt *bp)
1377 /* Release memzone */
1378 rte_free(bp->hwrm_cmd_resp_addr);
1379 bp->hwrm_cmd_resp_addr = NULL;
1380 bp->hwrm_cmd_resp_dma_addr = 0;
1383 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1385 struct rte_pci_device *pdev = bp->pdev;
1386 char type[RTE_MEMZONE_NAMESIZE];
1388 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1389 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1390 bp->max_req_len = HWRM_MAX_REQ_LEN;
1391 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1392 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1393 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1394 if (bp->hwrm_cmd_resp_addr == NULL)
1396 bp->hwrm_cmd_resp_dma_addr =
1397 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
1398 if (bp->hwrm_cmd_resp_dma_addr == 0) {
1400 "unable to map response address to physical memory\n");
1403 rte_spinlock_init(&bp->hwrm_lock);
1408 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1410 struct bnxt_filter_info *filter;
1413 STAILQ_FOREACH(filter, &vnic->filter, next) {
1414 rc = bnxt_hwrm_clear_filter(bp, filter);
1421 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1423 struct bnxt_filter_info *filter;
1426 STAILQ_FOREACH(filter, &vnic->filter, next) {
1427 rc = bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id, filter);
1434 void bnxt_free_tunnel_ports(struct bnxt *bp)
1436 if (bp->vxlan_port_cnt)
1437 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1438 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1440 if (bp->geneve_port_cnt)
1441 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1442 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1443 bp->geneve_port = 0;
1446 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1448 struct bnxt_vnic_info *vnic;
1451 if (bp->vnic_info == NULL)
1454 vnic = &bp->vnic_info[0];
1456 bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1458 /* VNIC resources */
1459 for (i = 0; i < bp->nr_vnics; i++) {
1460 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1462 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1464 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1465 bnxt_hwrm_vnic_free(bp, vnic);
1467 /* Ring resources */
1468 bnxt_free_all_hwrm_rings(bp);
1469 bnxt_free_all_hwrm_ring_grps(bp);
1470 bnxt_free_all_hwrm_stat_ctxs(bp);
1471 bnxt_free_tunnel_ports(bp);
1474 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1476 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1478 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1479 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1481 switch (conf_link_speed) {
1482 case ETH_LINK_SPEED_10M_HD:
1483 case ETH_LINK_SPEED_100M_HD:
1484 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1486 return hw_link_duplex;
1489 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1491 uint16_t eth_link_speed = 0;
1493 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1494 return ETH_LINK_SPEED_AUTONEG;
1496 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1497 case ETH_LINK_SPEED_100M:
1498 case ETH_LINK_SPEED_100M_HD:
1500 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1502 case ETH_LINK_SPEED_1G:
1504 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1506 case ETH_LINK_SPEED_2_5G:
1508 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1510 case ETH_LINK_SPEED_10G:
1512 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1514 case ETH_LINK_SPEED_20G:
1516 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1518 case ETH_LINK_SPEED_25G:
1520 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1522 case ETH_LINK_SPEED_40G:
1524 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1526 case ETH_LINK_SPEED_50G:
1528 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1532 "Unsupported link speed %d; default to AUTO\n",
1536 return eth_link_speed;
1539 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1540 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1541 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1542 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1544 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1548 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1551 if (link_speed & ETH_LINK_SPEED_FIXED) {
1552 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1554 if (one_speed & (one_speed - 1)) {
1556 "Invalid advertised speeds (%u) for port %u\n",
1557 link_speed, port_id);
1560 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1562 "Unsupported advertised speed (%u) for port %u\n",
1563 link_speed, port_id);
1567 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1569 "Unsupported advertised speeds (%u) for port %u\n",
1570 link_speed, port_id);
1577 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
1581 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1582 link_speed = BNXT_SUPPORTED_SPEEDS;
1584 if (link_speed & ETH_LINK_SPEED_100M)
1585 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1586 if (link_speed & ETH_LINK_SPEED_100M_HD)
1587 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1588 if (link_speed & ETH_LINK_SPEED_1G)
1589 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1590 if (link_speed & ETH_LINK_SPEED_2_5G)
1591 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1592 if (link_speed & ETH_LINK_SPEED_10G)
1593 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1594 if (link_speed & ETH_LINK_SPEED_20G)
1595 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1596 if (link_speed & ETH_LINK_SPEED_25G)
1597 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1598 if (link_speed & ETH_LINK_SPEED_40G)
1599 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1600 if (link_speed & ETH_LINK_SPEED_50G)
1601 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1605 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
1607 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
1609 switch (hw_link_speed) {
1610 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
1611 eth_link_speed = ETH_SPEED_NUM_100M;
1613 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
1614 eth_link_speed = ETH_SPEED_NUM_1G;
1616 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
1617 eth_link_speed = ETH_SPEED_NUM_2_5G;
1619 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
1620 eth_link_speed = ETH_SPEED_NUM_10G;
1622 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
1623 eth_link_speed = ETH_SPEED_NUM_20G;
1625 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
1626 eth_link_speed = ETH_SPEED_NUM_25G;
1628 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
1629 eth_link_speed = ETH_SPEED_NUM_40G;
1631 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
1632 eth_link_speed = ETH_SPEED_NUM_50G;
1634 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
1636 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
1640 return eth_link_speed;
1643 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
1645 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1647 switch (hw_link_duplex) {
1648 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
1649 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
1650 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1652 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
1653 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
1656 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
1660 return eth_link_duplex;
1663 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
1666 struct bnxt_link_info *link_info = &bp->link_info;
1668 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
1671 "Get link config failed with rc %d\n", rc);
1674 if (link_info->link_up)
1676 bnxt_parse_hw_link_speed(link_info->link_speed);
1678 link->link_speed = ETH_LINK_SPEED_10M;
1679 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
1680 link->link_status = link_info->link_up;
1681 link->link_autoneg = link_info->auto_mode ==
1682 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
1683 ETH_LINK_SPEED_FIXED : ETH_LINK_SPEED_AUTONEG;
1688 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1691 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1692 struct bnxt_link_info link_req;
1695 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
1698 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1699 bp->eth_dev->data->port_id);
1703 memset(&link_req, 0, sizeof(link_req));
1704 link_req.link_up = link_up;
1708 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1709 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1711 link_req.phy_flags |=
1712 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1713 link_req.auto_mode =
1714 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1715 link_req.auto_link_speed_mask =
1716 bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
1718 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
1719 link_req.link_speed = speed;
1720 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
1722 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1723 link_req.auto_pause = bp->link_info.auto_pause;
1724 link_req.force_pause = bp->link_info.force_pause;
1727 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1730 "Set link config failed with rc %d\n", rc);
1733 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1739 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
1741 struct hwrm_func_qcfg_input req = {0};
1742 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1745 HWRM_PREP(req, FUNC_QCFG, -1, resp);
1746 req.fid = rte_cpu_to_le_16(0xffff);
1748 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1752 /* Hard Coded.. 0xfff VLAN ID mask */
1753 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
1755 switch (resp->port_partition_type) {
1756 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
1757 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
1758 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
1759 bp->port_partition_type = resp->port_partition_type;
1762 bp->port_partition_type = 0;
1769 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
1770 struct hwrm_func_qcaps_output *qcaps)
1772 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
1773 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
1774 sizeof(qcaps->mac_address));
1775 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
1776 qcaps->max_rx_rings = fcfg->num_rx_rings;
1777 qcaps->max_tx_rings = fcfg->num_tx_rings;
1778 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
1779 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
1781 qcaps->first_vf_id = 0;
1782 qcaps->max_vnics = fcfg->num_vnics;
1783 qcaps->max_decap_records = 0;
1784 qcaps->max_encap_records = 0;
1785 qcaps->max_tx_wm_flows = 0;
1786 qcaps->max_tx_em_flows = 0;
1787 qcaps->max_rx_wm_flows = 0;
1788 qcaps->max_rx_em_flows = 0;
1789 qcaps->max_flow_id = 0;
1790 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
1791 qcaps->max_sp_tx_rings = 0;
1792 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
1795 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
1797 struct hwrm_func_cfg_input req = {0};
1798 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1801 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
1802 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
1803 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
1804 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1805 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1806 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1807 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1808 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1809 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
1810 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
1811 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
1812 req.mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1813 ETHER_CRC_LEN + VLAN_TAG_SIZE);
1814 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1815 ETHER_CRC_LEN + VLAN_TAG_SIZE);
1816 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1817 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
1818 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
1819 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
1820 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
1821 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
1822 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
1823 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
1824 req.fid = rte_cpu_to_le_16(0xffff);
1826 HWRM_PREP(req, FUNC_CFG, -1, resp);
1828 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1834 static void populate_vf_func_cfg_req(struct bnxt *bp,
1835 struct hwrm_func_cfg_input *req,
1838 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
1839 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
1840 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
1841 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1842 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1843 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1844 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1845 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1846 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
1847 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
1849 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1850 ETHER_CRC_LEN + VLAN_TAG_SIZE);
1851 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1852 ETHER_CRC_LEN + VLAN_TAG_SIZE);
1853 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
1855 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
1856 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
1858 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
1859 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
1860 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
1861 /* TODO: For now, do not support VMDq/RFS on VFs. */
1862 req->num_vnics = rte_cpu_to_le_16(1);
1863 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
1867 static void add_random_mac_if_needed(struct bnxt *bp,
1868 struct hwrm_func_cfg_input *cfg_req,
1871 struct ether_addr mac;
1873 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
1876 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
1878 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1879 eth_random_addr(cfg_req->dflt_mac_addr);
1880 bp->pf.vf_info[vf].random_mac = true;
1882 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
1886 static void reserve_resources_from_vf(struct bnxt *bp,
1887 struct hwrm_func_cfg_input *cfg_req,
1890 struct hwrm_func_qcaps_input req = {0};
1891 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1894 /* Get the actual allocated values now */
1895 HWRM_PREP(req, FUNC_QCAPS, -1, resp);
1896 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1897 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1900 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
1901 copy_func_cfg_to_qcaps(cfg_req, resp);
1902 } else if (resp->error_code) {
1903 rc = rte_le_to_cpu_16(resp->error_code);
1904 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
1905 copy_func_cfg_to_qcaps(cfg_req, resp);
1908 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
1909 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
1910 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
1911 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
1912 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
1913 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
1915 * TODO: While not supporting VMDq with VFs, max_vnics is always
1916 * forced to 1 in this case
1918 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
1919 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
1922 static int update_pf_resource_max(struct bnxt *bp)
1924 struct hwrm_func_qcfg_input req = {0};
1925 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1928 /* And copy the allocated numbers into the pf struct */
1929 HWRM_PREP(req, FUNC_QCFG, -1, resp);
1930 req.fid = rte_cpu_to_le_16(0xffff);
1931 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1934 /* Only TX ring value reflects actual allocation? TODO */
1935 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
1936 bp->pf.evb_mode = resp->evb_mode;
1941 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
1946 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
1950 rc = bnxt_hwrm_func_qcaps(bp);
1954 bp->pf.func_cfg_flags &=
1955 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
1956 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
1957 bp->pf.func_cfg_flags |=
1958 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
1959 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
1963 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
1965 struct hwrm_func_cfg_input req = {0};
1966 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1973 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
1977 rc = bnxt_hwrm_func_qcaps(bp);
1982 bp->pf.active_vfs = num_vfs;
1985 * First, configure the PF to only use one TX ring. This ensures that
1986 * there are enough rings for all VFs.
1988 * If we don't do this, when we call func_alloc() later, we will lock
1989 * extra rings to the PF that won't be available during func_cfg() of
1992 * This has been fixed with firmware versions above 20.6.54
1994 bp->pf.func_cfg_flags &=
1995 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
1996 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
1997 bp->pf.func_cfg_flags |=
1998 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
1999 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2004 * Now, create and register a buffer to hold forwarded VF requests
2006 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2007 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2008 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2009 if (bp->pf.vf_req_buf == NULL) {
2013 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2014 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2015 for (i = 0; i < num_vfs; i++)
2016 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2017 (i * HWRM_MAX_REQ_LEN);
2019 rc = bnxt_hwrm_func_buf_rgtr(bp);
2023 populate_vf_func_cfg_req(bp, &req, num_vfs);
2025 bp->pf.active_vfs = 0;
2026 for (i = 0; i < num_vfs; i++) {
2027 add_random_mac_if_needed(bp, &req, i);
2029 HWRM_PREP(req, FUNC_CFG, -1, resp);
2030 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2031 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2032 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2034 /* Clear enable flag for next pass */
2035 req.enables &= ~rte_cpu_to_le_32(
2036 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2038 if (rc || resp->error_code) {
2040 "Failed to initizlie VF %d\n", i);
2042 "Not all VFs available. (%d, %d)\n",
2043 rc, resp->error_code);
2047 reserve_resources_from_vf(bp, &req, i);
2048 bp->pf.active_vfs++;
2052 * Now configure the PF to use "the rest" of the resources
2053 * We're using STD_TX_RING_MODE here though which will limit the TX
2054 * rings. This will allow QoS to function properly. Not setting this
2055 * will cause PF rings to break bandwidth settings.
2057 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2061 rc = update_pf_resource_max(bp);
2068 bnxt_hwrm_func_buf_unrgtr(bp);
2072 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2073 uint8_t tunnel_type)
2075 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2076 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2079 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, -1, resp);
2080 req.tunnel_type = tunnel_type;
2081 req.tunnel_dst_port_val = port;
2082 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2085 switch (tunnel_type) {
2086 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2087 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2088 bp->vxlan_port = port;
2090 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2091 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2092 bp->geneve_port = port;
2100 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2101 uint8_t tunnel_type)
2103 struct hwrm_tunnel_dst_port_free_input req = {0};
2104 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2107 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, -1, resp);
2108 req.tunnel_type = tunnel_type;
2109 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2110 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2116 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2119 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2120 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2122 HWRM_PREP(req, FUNC_BUF_RGTR, -1, resp);
2124 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2125 req.req_buf_page_size = rte_cpu_to_le_16(
2126 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2127 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2128 req.req_buf_page_addr[0] =
2129 rte_cpu_to_le_64(rte_mem_virt2phy(bp->pf.vf_req_buf));
2130 if (req.req_buf_page_addr[0] == 0) {
2132 "unable to map buffer address to physical memory\n");
2136 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2143 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2146 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2147 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2149 HWRM_PREP(req, FUNC_BUF_UNRGTR, -1, resp);
2151 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2158 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2160 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2161 struct hwrm_func_cfg_input req = {0};
2164 HWRM_PREP(req, FUNC_CFG, -1, resp);
2165 req.fid = rte_cpu_to_le_16(0xffff);
2166 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2167 req.enables = rte_cpu_to_le_32(
2168 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2169 req.async_event_cr = rte_cpu_to_le_16(
2170 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2171 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2177 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2179 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2180 struct hwrm_func_vf_cfg_input req = {0};
2183 HWRM_PREP(req, FUNC_VF_CFG, -1, resp);
2184 req.enables = rte_cpu_to_le_32(
2185 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2186 req.async_event_cr = rte_cpu_to_le_16(
2187 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2188 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2194 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2195 void *encaped, size_t ec_size)
2198 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2199 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2201 if (ec_size > sizeof(req.encap_request))
2204 HWRM_PREP(req, REJECT_FWD_RESP, -1, resp);
2206 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2207 memcpy(req.encap_request, encaped, ec_size);
2209 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2216 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2217 struct ether_addr *mac)
2219 struct hwrm_func_qcfg_input req = {0};
2220 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2223 HWRM_PREP(req, FUNC_QCFG, -1, resp);
2224 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2225 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2229 memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2233 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2234 void *encaped, size_t ec_size)
2237 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2238 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2240 if (ec_size > sizeof(req.encap_request))
2243 HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
2245 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2246 memcpy(req.encap_request, encaped, ec_size);
2248 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2255 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2257 struct hwrm_port_qstats_input req = {0};
2258 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2259 struct bnxt_pf_info *pf = &bp->pf;
2262 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2265 HWRM_PREP(req, PORT_QSTATS, -1, resp);
2266 req.port_id = rte_cpu_to_le_16(pf->port_id);
2267 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2268 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2269 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2274 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2276 struct hwrm_port_clr_stats_input req = {0};
2277 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2278 struct bnxt_pf_info *pf = &bp->pf;
2281 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2284 HWRM_PREP(req, PORT_CLR_STATS, -1, resp);
2285 req.port_id = rte_cpu_to_le_16(pf->port_id);
2286 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));