1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SPEC_CODE_1_8_3 0x10803
31 #define HWRM_VERSION_1_9_1 0x10901
32 #define HWRM_VERSION_1_9_2 0x10903
34 struct bnxt_plcmodes_cfg {
36 uint16_t jumbo_thresh;
38 uint16_t hds_threshold;
41 static int page_getenum(size_t size)
57 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
58 return sizeof(void *) * 8 - 1;
61 static int page_roundup(size_t size)
63 return 1 << page_getenum(size);
66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
79 * HWRM Functions (sent to HWRM)
80 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
81 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
82 * command was failed by the ChiMP.
85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
86 uint32_t msg_len, bool use_kong_mb)
89 struct input *req = msg;
90 struct output *resp = bp->hwrm_cmd_resp_addr;
94 uint16_t max_req_len = bp->max_req_len;
95 struct hwrm_short_input short_input = { 0 };
96 uint16_t bar_offset = use_kong_mb ?
97 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
98 uint16_t mb_trigger_offset = use_kong_mb ?
99 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
101 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
102 msg_len > bp->max_req_len) {
103 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
105 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
106 memcpy(short_cmd_req, req, msg_len);
108 short_input.req_type = rte_cpu_to_le_16(req->req_type);
109 short_input.signature = rte_cpu_to_le_16(
110 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
111 short_input.size = rte_cpu_to_le_16(msg_len);
112 short_input.req_addr =
113 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
115 data = (uint32_t *)&short_input;
116 msg_len = sizeof(short_input);
118 /* Sync memory write before updating doorbell */
121 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
124 /* Write request msg to hwrm channel */
125 for (i = 0; i < msg_len; i += 4) {
126 bar = (uint8_t *)bp->bar0 + bar_offset + i;
127 rte_write32(*data, bar);
131 /* Zero the rest of the request space */
132 for (; i < max_req_len; i += 4) {
133 bar = (uint8_t *)bp->bar0 + bar_offset + i;
137 /* Ring channel doorbell */
138 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
141 /* Poll for the valid bit */
142 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
143 /* Sanity check on the resp->resp_len */
145 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
146 /* Last byte of resp contains the valid key */
147 valid = (uint8_t *)resp + resp->resp_len - 1;
148 if (*valid == HWRM_RESP_VALID_KEY)
154 if (i >= HWRM_CMD_TIMEOUT) {
155 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
166 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
167 * spinlock, and does initial processing.
169 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
170 * releases the spinlock only if it returns. If the regular int return codes
171 * are not used by the function, HWRM_CHECK_RESULT() should not be used
172 * directly, rather it should be copied and modified to suit the function.
174 * HWRM_UNLOCK() must be called after all response processing is completed.
176 #define HWRM_PREP(req, type, kong) do { \
177 rte_spinlock_lock(&bp->hwrm_lock); \
178 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
179 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
180 req.cmpl_ring = rte_cpu_to_le_16(-1); \
181 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
182 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
183 req.target_id = rte_cpu_to_le_16(0xffff); \
184 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
187 #define HWRM_CHECK_RESULT_SILENT() do {\
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 if (resp->error_code) { \
193 rc = rte_le_to_cpu_16(resp->error_code); \
194 rte_spinlock_unlock(&bp->hwrm_lock); \
199 #define HWRM_CHECK_RESULT() do {\
201 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
202 rte_spinlock_unlock(&bp->hwrm_lock); \
203 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 if (resp->resp_len >= 16) { \
212 struct hwrm_err_output *tmp_hwrm_err_op = \
215 "error %d:%d:%08x:%04x\n", \
216 rc, tmp_hwrm_err_op->cmd_err, \
218 tmp_hwrm_err_op->opaque_0), \
220 tmp_hwrm_err_op->opaque_1)); \
222 PMD_DRV_LOG(ERR, "error %d\n", rc); \
224 rte_spinlock_unlock(&bp->hwrm_lock); \
225 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
233 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
238 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
239 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
241 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
242 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
254 struct bnxt_vnic_info *vnic,
256 struct bnxt_vlan_table_entry *vlan_table)
259 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
260 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
263 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
269 /* FIXME add multicast flag, when multicast adding options is supported
272 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
273 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
274 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
275 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
276 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
277 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
278 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
279 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
280 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
281 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
282 if (vnic->mc_addr_cnt) {
283 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
284 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
285 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
288 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
290 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
291 rte_mem_virt2iova(vlan_table));
292 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
294 req.mask = rte_cpu_to_le_32(mask);
296 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
306 struct bnxt_vlan_antispoof_table_entry *vlan_table)
309 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
310 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
311 bp->hwrm_cmd_resp_addr;
314 * Older HWRM versions did not support this command, and the set_rx_mask
315 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
316 * removed from set_rx_mask call, and this command was added.
318 * This command is also present from 1.7.8.11 and higher,
321 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
322 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
323 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
328 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
329 req.fid = rte_cpu_to_le_16(fid);
331 req.vlan_tag_mask_tbl_addr =
332 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
333 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
344 struct bnxt_filter_info *filter)
347 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
348 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
350 if (filter->fw_l2_filter_id == UINT64_MAX)
353 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
355 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
362 filter->fw_l2_filter_id = UINT64_MAX;
367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
369 struct bnxt_filter_info *filter)
372 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
374 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
375 const struct rte_eth_vmdq_rx_conf *conf =
376 &dev_conf->rx_adv_conf.vmdq_rx_conf;
377 uint32_t enables = 0;
378 uint16_t j = dst_id - 1;
380 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
381 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
382 conf->pool_map[j].pools & (1UL << j)) {
384 "Add vlan %u to vmdq pool %u\n",
385 conf->pool_map[j].vlan_id, j);
387 filter->l2_ivlan = conf->pool_map[j].vlan_id;
389 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
393 if (filter->fw_l2_filter_id != UINT64_MAX)
394 bnxt_hwrm_clear_l2_filter(bp, filter);
396 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
398 req.flags = rte_cpu_to_le_32(filter->flags);
400 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
402 enables = filter->enables |
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
404 req.dst_id = rte_cpu_to_le_16(dst_id);
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
408 memcpy(req.l2_addr, filter->l2_addr,
411 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
412 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
415 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
416 req.l2_ovlan = filter->l2_ovlan;
418 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
419 req.l2_ivlan = filter->l2_ivlan;
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
422 req.l2_ovlan_mask = filter->l2_ovlan_mask;
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
425 req.l2_ivlan_mask = filter->l2_ivlan_mask;
426 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
427 req.src_id = rte_cpu_to_le_32(filter->src_id);
428 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
429 req.src_type = filter->src_type;
431 req.enables = rte_cpu_to_le_32(enables);
433 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
437 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
445 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
446 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
453 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
456 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
459 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
460 if (ptp->tx_tstamp_en)
461 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
464 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
465 req.flags = rte_cpu_to_le_32(flags);
466 req.enables = rte_cpu_to_le_32
467 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
468 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
470 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
479 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
480 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
481 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
483 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
487 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
489 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
495 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
498 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
502 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
503 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
504 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
505 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
506 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
507 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
508 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
509 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
510 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
511 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
512 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
513 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
514 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
515 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
516 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
517 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
518 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
519 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
530 struct hwrm_func_qcaps_input req = {.req_type = 0 };
531 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
532 uint16_t new_max_vfs;
536 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
538 req.fid = rte_cpu_to_le_16(0xffff);
540 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
544 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
545 flags = rte_le_to_cpu_32(resp->flags);
547 bp->pf.port_id = resp->port_id;
548 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
549 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
550 new_max_vfs = bp->pdev->max_vfs;
551 if (new_max_vfs != bp->pf.max_vfs) {
553 rte_free(bp->pf.vf_info);
554 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
555 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
556 bp->pf.max_vfs = new_max_vfs;
557 for (i = 0; i < new_max_vfs; i++) {
558 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
559 bp->pf.vf_info[i].vlan_table =
560 rte_zmalloc("VF VLAN table",
563 if (bp->pf.vf_info[i].vlan_table == NULL)
565 "Fail to alloc VLAN table for VF %d\n",
569 bp->pf.vf_info[i].vlan_table);
570 bp->pf.vf_info[i].vlan_as_table =
571 rte_zmalloc("VF VLAN AS table",
574 if (bp->pf.vf_info[i].vlan_as_table == NULL)
576 "Alloc VLAN AS table for VF %d fail\n",
580 bp->pf.vf_info[i].vlan_as_table);
581 STAILQ_INIT(&bp->pf.vf_info[i].filter);
586 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
587 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
588 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
589 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
590 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
591 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
592 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
593 /* TODO: For now, do not support VMDq/RFS on VFs. */
598 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
602 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
604 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
605 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
606 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
607 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
609 bnxt_hwrm_ptp_qcfg(bp);
618 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
622 rc = __bnxt_hwrm_func_qcaps(bp);
623 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
624 rc = bnxt_alloc_ctx_mem(bp);
628 rc = bnxt_hwrm_func_resc_qcaps(bp);
630 bp->flags |= BNXT_FLAG_NEW_RM;
636 int bnxt_hwrm_func_reset(struct bnxt *bp)
639 struct hwrm_func_reset_input req = {.req_type = 0 };
640 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
642 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
644 req.enables = rte_cpu_to_le_32(0);
646 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
654 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
657 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
658 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
660 if (bp->flags & BNXT_FLAG_REGISTERED)
663 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
664 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
665 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
666 req.ver_maj = RTE_VER_YEAR;
667 req.ver_min = RTE_VER_MONTH;
668 req.ver_upd = RTE_VER_MINOR;
671 req.enables |= rte_cpu_to_le_32(
672 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
673 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
674 RTE_MIN(sizeof(req.vf_req_fwd),
675 sizeof(bp->pf.vf_req_fwd)));
678 * PF can sniff HWRM API issued by VF. This can be set up by
679 * linux driver and inherited by the DPDK PF driver. Clear
680 * this HWRM sniffer list in FW because DPDK PF driver does
684 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
687 req.async_event_fwd[0] |=
688 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
689 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
690 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
691 req.async_event_fwd[1] |=
692 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
693 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
695 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
700 bp->flags |= BNXT_FLAG_REGISTERED;
705 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
707 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
710 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
713 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
718 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
719 struct hwrm_func_vf_cfg_input req = {0};
721 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
723 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
724 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
725 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
726 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
727 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
729 if (BNXT_HAS_RING_GRPS(bp)) {
730 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
731 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
734 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
735 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
736 AGG_RING_MULTIPLIER);
737 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
738 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
740 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
741 if (bp->vf_resv_strategy ==
742 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
743 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
744 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
745 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
746 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
747 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
748 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
752 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
753 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
754 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
755 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
756 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
757 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
759 if (test && BNXT_HAS_RING_GRPS(bp))
760 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
762 req.flags = rte_cpu_to_le_32(flags);
763 req.enables |= rte_cpu_to_le_32(enables);
765 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
768 HWRM_CHECK_RESULT_SILENT();
776 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
779 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
780 struct hwrm_func_resource_qcaps_input req = {0};
782 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
783 req.fid = rte_cpu_to_le_16(0xffff);
785 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
790 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
791 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
792 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
793 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
794 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
795 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
796 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
797 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
799 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
800 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
801 if (bp->vf_resv_strategy >
802 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
803 bp->vf_resv_strategy =
804 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
810 int bnxt_hwrm_ver_get(struct bnxt *bp)
813 struct hwrm_ver_get_input req = {.req_type = 0 };
814 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
816 uint16_t max_resp_len;
817 char type[RTE_MEMZONE_NAMESIZE];
818 uint32_t dev_caps_cfg;
820 bp->max_req_len = HWRM_MAX_REQ_LEN;
821 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
823 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
824 req.hwrm_intf_min = HWRM_VERSION_MINOR;
825 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
827 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
831 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
832 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
833 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
834 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
835 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
836 (resp->hwrm_fw_min_8b << 16) |
837 (resp->hwrm_fw_bld_8b << 8) |
838 resp->hwrm_fw_rsvd_8b;
839 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
840 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
842 fw_version = resp->hwrm_intf_maj_8b << 16;
843 fw_version |= resp->hwrm_intf_min_8b << 8;
844 fw_version |= resp->hwrm_intf_upd_8b;
845 bp->hwrm_spec_code = fw_version;
847 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
848 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
853 if (bp->max_req_len > resp->max_req_win_len) {
854 PMD_DRV_LOG(ERR, "Unsupported request length\n");
857 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
858 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
859 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
860 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
862 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
863 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
865 if (bp->max_resp_len != max_resp_len) {
866 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
867 bp->pdev->addr.domain, bp->pdev->addr.bus,
868 bp->pdev->addr.devid, bp->pdev->addr.function);
870 rte_free(bp->hwrm_cmd_resp_addr);
872 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
873 if (bp->hwrm_cmd_resp_addr == NULL) {
877 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
878 bp->hwrm_cmd_resp_dma_addr =
879 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
880 if (bp->hwrm_cmd_resp_dma_addr == 0) {
882 "Unable to map response buffer to physical memory.\n");
886 bp->max_resp_len = max_resp_len;
890 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
892 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
893 PMD_DRV_LOG(DEBUG, "Short command supported\n");
894 bp->flags |= BNXT_FLAG_SHORT_CMD;
898 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
900 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
901 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
902 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
903 bp->pdev->addr.domain, bp->pdev->addr.bus,
904 bp->pdev->addr.devid, bp->pdev->addr.function);
906 rte_free(bp->hwrm_short_cmd_req_addr);
908 bp->hwrm_short_cmd_req_addr =
909 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
910 if (bp->hwrm_short_cmd_req_addr == NULL) {
914 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
915 bp->hwrm_short_cmd_req_dma_addr =
916 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
917 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
918 rte_free(bp->hwrm_short_cmd_req_addr);
920 "Unable to map buffer to physical memory.\n");
926 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
927 bp->flags |= BNXT_FLAG_KONG_MB_EN;
928 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
931 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
932 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
939 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
942 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
943 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
945 if (!(bp->flags & BNXT_FLAG_REGISTERED))
948 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
951 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
956 bp->flags &= ~BNXT_FLAG_REGISTERED;
961 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
964 struct hwrm_port_phy_cfg_input req = {0};
965 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
966 uint32_t enables = 0;
968 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
971 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
972 if (bp->link_info.auto_mode && conf->link_speed) {
973 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
974 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
977 req.flags = rte_cpu_to_le_32(conf->phy_flags);
978 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
979 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
981 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
982 * any auto mode, even "none".
984 if (!conf->link_speed) {
985 /* No speeds specified. Enable AutoNeg - all speeds */
987 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
989 /* AutoNeg - Advertise speeds specified. */
990 if (conf->auto_link_speed_mask &&
991 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
993 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
994 req.auto_link_speed_mask =
995 conf->auto_link_speed_mask;
997 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1000 req.auto_duplex = conf->duplex;
1001 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1002 req.auto_pause = conf->auto_pause;
1003 req.force_pause = conf->force_pause;
1004 /* Set force_pause if there is no auto or if there is a force */
1005 if (req.auto_pause && !req.force_pause)
1006 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1008 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1010 req.enables = rte_cpu_to_le_32(enables);
1013 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1014 PMD_DRV_LOG(INFO, "Force Link Down\n");
1017 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1019 HWRM_CHECK_RESULT();
1025 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1026 struct bnxt_link_info *link_info)
1029 struct hwrm_port_phy_qcfg_input req = {0};
1030 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1032 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1034 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1036 HWRM_CHECK_RESULT();
1038 link_info->phy_link_status = resp->link;
1039 link_info->link_up =
1040 (link_info->phy_link_status ==
1041 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1042 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1043 link_info->duplex = resp->duplex_cfg;
1044 link_info->pause = resp->pause;
1045 link_info->auto_pause = resp->auto_pause;
1046 link_info->force_pause = resp->force_pause;
1047 link_info->auto_mode = resp->auto_mode;
1048 link_info->phy_type = resp->phy_type;
1049 link_info->media_type = resp->media_type;
1051 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1052 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1053 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1054 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1055 link_info->phy_ver[0] = resp->phy_maj;
1056 link_info->phy_ver[1] = resp->phy_min;
1057 link_info->phy_ver[2] = resp->phy_bld;
1061 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1062 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1063 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1064 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1065 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1066 link_info->auto_link_speed_mask);
1067 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1068 link_info->force_link_speed);
1073 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1076 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1077 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1080 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1082 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1083 /* HWRM Version >= 1.9.1 */
1084 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1086 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1087 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1089 HWRM_CHECK_RESULT();
1091 #define GET_QUEUE_INFO(x) \
1092 bp->cos_queue[x].id = resp->queue_id##x; \
1093 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1106 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1107 bp->tx_cosq_id = bp->cos_queue[0].id;
1109 /* iterate and find the COSq profile to use for Tx */
1110 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1111 if (bp->cos_queue[i].profile ==
1112 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1113 bp->tx_cosq_id = bp->cos_queue[i].id;
1119 bp->max_tc = resp->max_configurable_queues;
1120 bp->max_lltc = resp->max_configurable_lossless_queues;
1121 if (bp->max_tc > BNXT_MAX_QUEUE)
1122 bp->max_tc = BNXT_MAX_QUEUE;
1123 bp->max_q = bp->max_tc;
1125 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1130 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1131 struct bnxt_ring *ring,
1132 uint32_t ring_type, uint32_t map_index,
1133 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1136 uint32_t enables = 0;
1137 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1138 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1139 struct rte_mempool *mb_pool;
1140 uint16_t rx_buf_size;
1142 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1144 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1145 req.fbo = rte_cpu_to_le_32(0);
1146 /* Association of ring index with doorbell index */
1147 req.logical_id = rte_cpu_to_le_16(map_index);
1148 req.length = rte_cpu_to_le_32(ring->ring_size);
1150 switch (ring_type) {
1151 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1152 req.ring_type = ring_type;
1153 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1154 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1155 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1156 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1158 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1160 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1161 req.ring_type = ring_type;
1162 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1163 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1164 if (BNXT_CHIP_THOR(bp)) {
1165 mb_pool = bp->rx_queues[0]->mb_pool;
1166 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1167 RTE_PKTMBUF_HEADROOM;
1168 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1170 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1172 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1174 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1176 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1177 req.ring_type = ring_type;
1178 if (BNXT_HAS_NQ(bp)) {
1179 /* Association of cp ring with nq */
1180 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1182 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1184 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1186 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1187 req.ring_type = ring_type;
1188 req.page_size = BNXT_PAGE_SHFT;
1189 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1191 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1192 req.ring_type = ring_type;
1193 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1195 mb_pool = bp->rx_queues[0]->mb_pool;
1196 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1197 RTE_PKTMBUF_HEADROOM;
1198 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1200 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1201 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1202 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1203 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1206 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1211 req.enables = rte_cpu_to_le_32(enables);
1213 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1215 if (rc || resp->error_code) {
1216 if (rc == 0 && resp->error_code)
1217 rc = rte_le_to_cpu_16(resp->error_code);
1218 switch (ring_type) {
1219 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1221 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1224 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1226 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1229 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1231 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1235 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1237 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1240 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1242 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1246 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1252 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1257 int bnxt_hwrm_ring_free(struct bnxt *bp,
1258 struct bnxt_ring *ring, uint32_t ring_type)
1261 struct hwrm_ring_free_input req = {.req_type = 0 };
1262 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1264 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1266 req.ring_type = ring_type;
1267 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1269 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1271 if (rc || resp->error_code) {
1272 if (rc == 0 && resp->error_code)
1273 rc = rte_le_to_cpu_16(resp->error_code);
1276 switch (ring_type) {
1277 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1278 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1281 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1282 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1285 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1286 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1289 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1291 "hwrm_ring_free nq failed. rc:%d\n", rc);
1293 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1295 "hwrm_ring_free agg failed. rc:%d\n", rc);
1298 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1306 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1309 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1310 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1312 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1314 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1315 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1316 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1317 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1319 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1321 HWRM_CHECK_RESULT();
1323 bp->grp_info[idx].fw_grp_id =
1324 rte_le_to_cpu_16(resp->ring_group_id);
1331 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1334 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1335 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1337 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1339 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1341 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1343 HWRM_CHECK_RESULT();
1346 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1350 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1353 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1354 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1356 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1359 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1361 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1363 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1365 HWRM_CHECK_RESULT();
1371 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1372 unsigned int idx __rte_unused)
1375 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1376 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1378 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1380 req.update_period_ms = rte_cpu_to_le_32(0);
1382 req.stats_dma_addr =
1383 rte_cpu_to_le_64(cpr->hw_stats_map);
1385 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1387 HWRM_CHECK_RESULT();
1389 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1396 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1397 unsigned int idx __rte_unused)
1400 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1401 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1403 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1405 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1407 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1409 HWRM_CHECK_RESULT();
1415 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1418 struct hwrm_vnic_alloc_input req = { 0 };
1419 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1421 if (!BNXT_HAS_RING_GRPS(bp))
1422 goto skip_ring_grps;
1424 /* map ring groups to this vnic */
1425 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1426 vnic->start_grp_id, vnic->end_grp_id);
1427 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1428 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1430 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1431 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1432 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1433 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1436 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1437 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1438 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1440 if (vnic->func_default)
1442 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1443 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1445 HWRM_CHECK_RESULT();
1447 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1449 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1453 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1454 struct bnxt_vnic_info *vnic,
1455 struct bnxt_plcmodes_cfg *pmode)
1458 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1459 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1461 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1463 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1465 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1467 HWRM_CHECK_RESULT();
1469 pmode->flags = rte_le_to_cpu_32(resp->flags);
1470 /* dflt_vnic bit doesn't exist in the _cfg command */
1471 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1472 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1473 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1474 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1481 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1482 struct bnxt_vnic_info *vnic,
1483 struct bnxt_plcmodes_cfg *pmode)
1486 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1487 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1489 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1491 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1492 req.flags = rte_cpu_to_le_32(pmode->flags);
1493 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1494 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1495 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1496 req.enables = rte_cpu_to_le_32(
1497 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1498 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1499 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1502 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1504 HWRM_CHECK_RESULT();
1510 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1513 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1514 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1515 uint32_t ctx_enable_flag = 0;
1516 struct bnxt_plcmodes_cfg pmodes;
1517 uint32_t enables = 0;
1519 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1520 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1524 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1528 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1530 if (BNXT_CHIP_THOR(bp)) {
1531 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1532 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1533 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1535 req.default_rx_ring_id =
1536 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1537 req.default_cmpl_ring_id =
1538 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1539 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1540 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1544 /* Only RSS support for now TBD: COS & LB */
1545 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1546 if (vnic->lb_rule != 0xffff)
1547 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1548 if (vnic->cos_rule != 0xffff)
1549 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1550 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1551 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1552 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1554 enables |= ctx_enable_flag;
1555 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1556 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1557 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1558 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1561 req.enables = rte_cpu_to_le_32(enables);
1562 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1563 req.mru = rte_cpu_to_le_16(vnic->mru);
1564 /* Configure default VNIC only once. */
1565 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1567 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1568 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1570 if (vnic->vlan_strip)
1572 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1575 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1576 if (vnic->roce_dual)
1577 req.flags |= rte_cpu_to_le_32(
1578 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1579 if (vnic->roce_only)
1580 req.flags |= rte_cpu_to_le_32(
1581 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1582 if (vnic->rss_dflt_cr)
1583 req.flags |= rte_cpu_to_le_32(
1584 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1586 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1588 HWRM_CHECK_RESULT();
1591 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1596 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1600 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1601 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1603 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1604 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1607 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1610 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1611 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1612 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1614 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1616 HWRM_CHECK_RESULT();
1618 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1619 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1620 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1621 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1622 vnic->mru = rte_le_to_cpu_16(resp->mru);
1623 vnic->func_default = rte_le_to_cpu_32(
1624 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1625 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1626 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1627 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1628 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1629 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1630 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1631 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1632 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1633 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1634 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1641 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1644 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1645 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1646 bp->hwrm_cmd_resp_addr;
1648 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1650 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1652 HWRM_CHECK_RESULT();
1654 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1656 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1661 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1664 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1665 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1666 bp->hwrm_cmd_resp_addr;
1668 if (vnic->rss_rule == (uint16_t)HWRM_NA_SIGNATURE) {
1669 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1672 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1674 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1676 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1678 HWRM_CHECK_RESULT();
1681 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1686 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1689 struct hwrm_vnic_free_input req = {.req_type = 0 };
1690 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1692 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1693 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1697 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1699 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1701 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1703 HWRM_CHECK_RESULT();
1706 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1707 /* Configure default VNIC again if necessary. */
1708 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1709 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1714 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1715 struct bnxt_vnic_info *vnic)
1718 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1719 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1721 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1723 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1724 req.hash_mode_flags = vnic->hash_mode;
1726 req.ring_grp_tbl_addr =
1727 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1728 req.hash_key_tbl_addr =
1729 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1730 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1731 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1733 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1735 HWRM_CHECK_RESULT();
1741 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1742 struct bnxt_vnic_info *vnic)
1745 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1746 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1749 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1750 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1754 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1756 req.flags = rte_cpu_to_le_32(
1757 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1759 req.enables = rte_cpu_to_le_32(
1760 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1762 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1763 size -= RTE_PKTMBUF_HEADROOM;
1765 req.jumbo_thresh = rte_cpu_to_le_16(size);
1766 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1768 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1770 HWRM_CHECK_RESULT();
1776 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1777 struct bnxt_vnic_info *vnic, bool enable)
1780 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1781 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1783 if (BNXT_CHIP_THOR(bp))
1786 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1789 req.enables = rte_cpu_to_le_32(
1790 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1791 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1792 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1793 req.flags = rte_cpu_to_le_32(
1794 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1795 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1796 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1797 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1798 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1799 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1800 req.max_agg_segs = rte_cpu_to_le_16(5);
1802 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1803 req.min_agg_len = rte_cpu_to_le_32(512);
1805 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1807 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1809 HWRM_CHECK_RESULT();
1815 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1817 struct hwrm_func_cfg_input req = {0};
1818 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1821 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1822 req.enables = rte_cpu_to_le_32(
1823 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1824 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1825 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1827 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1829 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1830 HWRM_CHECK_RESULT();
1833 bp->pf.vf_info[vf].random_mac = false;
1838 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1842 struct hwrm_func_qstats_input req = {.req_type = 0};
1843 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1845 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1847 req.fid = rte_cpu_to_le_16(fid);
1849 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1851 HWRM_CHECK_RESULT();
1854 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1861 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1862 struct rte_eth_stats *stats)
1865 struct hwrm_func_qstats_input req = {.req_type = 0};
1866 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1868 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1870 req.fid = rte_cpu_to_le_16(fid);
1872 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1874 HWRM_CHECK_RESULT();
1876 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1877 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1878 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1879 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1880 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1881 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1883 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1884 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1885 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1886 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1887 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1888 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1890 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1891 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1892 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1899 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1902 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1903 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1905 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1907 req.fid = rte_cpu_to_le_16(fid);
1909 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1911 HWRM_CHECK_RESULT();
1918 * HWRM utility functions
1921 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1926 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1927 struct bnxt_tx_queue *txq;
1928 struct bnxt_rx_queue *rxq;
1929 struct bnxt_cp_ring_info *cpr;
1931 if (i >= bp->rx_cp_nr_rings) {
1932 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1935 rxq = bp->rx_queues[i];
1939 rc = bnxt_hwrm_stat_clear(bp, cpr);
1946 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1950 struct bnxt_cp_ring_info *cpr;
1952 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1954 if (i >= bp->rx_cp_nr_rings) {
1955 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1957 cpr = bp->rx_queues[i]->cp_ring;
1958 bp->grp_info[i].fw_stats_ctx = -1;
1960 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1961 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1962 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1970 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1975 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1976 struct bnxt_tx_queue *txq;
1977 struct bnxt_rx_queue *rxq;
1978 struct bnxt_cp_ring_info *cpr;
1980 if (i >= bp->rx_cp_nr_rings) {
1981 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1984 rxq = bp->rx_queues[i];
1988 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1996 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2001 if (!BNXT_HAS_RING_GRPS(bp))
2004 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2006 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2009 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2017 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2019 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2021 bnxt_hwrm_ring_free(bp, cp_ring,
2022 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2023 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2024 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2025 sizeof(*cpr->cp_desc_ring));
2026 cpr->cp_raw_cons = 0;
2029 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2031 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2033 bnxt_hwrm_ring_free(bp, cp_ring,
2034 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2035 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2036 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2037 sizeof(*cpr->cp_desc_ring));
2038 cpr->cp_raw_cons = 0;
2041 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2043 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2044 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2045 struct bnxt_ring *ring = rxr->rx_ring_struct;
2046 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2048 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2049 bnxt_hwrm_ring_free(bp, ring,
2050 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2051 ring->fw_ring_id = INVALID_HW_RING_ID;
2052 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2053 memset(rxr->rx_desc_ring, 0,
2054 rxr->rx_ring_struct->ring_size *
2055 sizeof(*rxr->rx_desc_ring));
2056 memset(rxr->rx_buf_ring, 0,
2057 rxr->rx_ring_struct->ring_size *
2058 sizeof(*rxr->rx_buf_ring));
2061 ring = rxr->ag_ring_struct;
2062 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2063 bnxt_hwrm_ring_free(bp, ring,
2064 BNXT_CHIP_THOR(bp) ?
2065 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2066 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2067 ring->fw_ring_id = INVALID_HW_RING_ID;
2068 memset(rxr->ag_buf_ring, 0,
2069 rxr->ag_ring_struct->ring_size *
2070 sizeof(*rxr->ag_buf_ring));
2072 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2074 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2075 bnxt_free_cp_ring(bp, cpr);
2077 bnxt_free_nq_ring(bp, rxq->nq_ring);
2080 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2083 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2087 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2088 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2089 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2090 struct bnxt_ring *ring = txr->tx_ring_struct;
2091 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2093 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2094 bnxt_hwrm_ring_free(bp, ring,
2095 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2096 ring->fw_ring_id = INVALID_HW_RING_ID;
2097 memset(txr->tx_desc_ring, 0,
2098 txr->tx_ring_struct->ring_size *
2099 sizeof(*txr->tx_desc_ring));
2100 memset(txr->tx_buf_ring, 0,
2101 txr->tx_ring_struct->ring_size *
2102 sizeof(*txr->tx_buf_ring));
2106 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2107 bnxt_free_cp_ring(bp, cpr);
2108 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2110 bnxt_free_nq_ring(bp, txq->nq_ring);
2114 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2115 bnxt_free_hwrm_rx_ring(bp, i);
2120 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2125 if (!BNXT_HAS_RING_GRPS(bp))
2128 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2129 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2136 void bnxt_free_hwrm_resources(struct bnxt *bp)
2138 /* Release memzone */
2139 rte_free(bp->hwrm_cmd_resp_addr);
2140 rte_free(bp->hwrm_short_cmd_req_addr);
2141 bp->hwrm_cmd_resp_addr = NULL;
2142 bp->hwrm_short_cmd_req_addr = NULL;
2143 bp->hwrm_cmd_resp_dma_addr = 0;
2144 bp->hwrm_short_cmd_req_dma_addr = 0;
2147 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2149 struct rte_pci_device *pdev = bp->pdev;
2150 char type[RTE_MEMZONE_NAMESIZE];
2152 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2153 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2154 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2155 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2156 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2157 if (bp->hwrm_cmd_resp_addr == NULL)
2159 bp->hwrm_cmd_resp_dma_addr =
2160 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2161 if (bp->hwrm_cmd_resp_dma_addr == 0) {
2163 "unable to map response address to physical memory\n");
2166 rte_spinlock_init(&bp->hwrm_lock);
2171 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2173 struct bnxt_filter_info *filter;
2176 STAILQ_FOREACH(filter, &vnic->filter, next) {
2177 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2178 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2179 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2180 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2182 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2183 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2191 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2193 struct bnxt_filter_info *filter;
2194 struct rte_flow *flow;
2197 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2198 filter = flow->filter;
2199 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2200 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2201 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2202 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2203 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2205 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2207 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2215 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2217 struct bnxt_filter_info *filter;
2220 STAILQ_FOREACH(filter, &vnic->filter, next) {
2221 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2222 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2224 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2225 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2228 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2236 void bnxt_free_tunnel_ports(struct bnxt *bp)
2238 if (bp->vxlan_port_cnt)
2239 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2240 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2242 if (bp->geneve_port_cnt)
2243 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2244 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2245 bp->geneve_port = 0;
2248 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2252 if (bp->vnic_info == NULL)
2256 * Cleanup VNICs in reverse order, to make sure the L2 filter
2257 * from vnic0 is last to be cleaned up.
2259 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2260 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2262 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2264 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2266 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2268 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2270 bnxt_hwrm_vnic_free(bp, vnic);
2272 rte_free(vnic->fw_grp_ids);
2274 /* Ring resources */
2275 bnxt_free_all_hwrm_rings(bp);
2276 bnxt_free_all_hwrm_ring_grps(bp);
2277 bnxt_free_all_hwrm_stat_ctxs(bp);
2278 bnxt_free_tunnel_ports(bp);
2281 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2283 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2285 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2286 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2288 switch (conf_link_speed) {
2289 case ETH_LINK_SPEED_10M_HD:
2290 case ETH_LINK_SPEED_100M_HD:
2292 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2294 return hw_link_duplex;
2297 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2299 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2302 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2304 uint16_t eth_link_speed = 0;
2306 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2307 return ETH_LINK_SPEED_AUTONEG;
2309 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2310 case ETH_LINK_SPEED_100M:
2311 case ETH_LINK_SPEED_100M_HD:
2314 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2316 case ETH_LINK_SPEED_1G:
2318 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2320 case ETH_LINK_SPEED_2_5G:
2322 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2324 case ETH_LINK_SPEED_10G:
2326 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2328 case ETH_LINK_SPEED_20G:
2330 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2332 case ETH_LINK_SPEED_25G:
2334 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2336 case ETH_LINK_SPEED_40G:
2338 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2340 case ETH_LINK_SPEED_50G:
2342 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2344 case ETH_LINK_SPEED_100G:
2346 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2350 "Unsupported link speed %d; default to AUTO\n",
2354 return eth_link_speed;
2357 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2358 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2359 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2360 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2362 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2366 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2369 if (link_speed & ETH_LINK_SPEED_FIXED) {
2370 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2372 if (one_speed & (one_speed - 1)) {
2374 "Invalid advertised speeds (%u) for port %u\n",
2375 link_speed, port_id);
2378 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2380 "Unsupported advertised speed (%u) for port %u\n",
2381 link_speed, port_id);
2385 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2387 "Unsupported advertised speeds (%u) for port %u\n",
2388 link_speed, port_id);
2396 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2400 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2401 if (bp->link_info.support_speeds)
2402 return bp->link_info.support_speeds;
2403 link_speed = BNXT_SUPPORTED_SPEEDS;
2406 if (link_speed & ETH_LINK_SPEED_100M)
2407 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2408 if (link_speed & ETH_LINK_SPEED_100M_HD)
2409 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2410 if (link_speed & ETH_LINK_SPEED_1G)
2411 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2412 if (link_speed & ETH_LINK_SPEED_2_5G)
2413 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2414 if (link_speed & ETH_LINK_SPEED_10G)
2415 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2416 if (link_speed & ETH_LINK_SPEED_20G)
2417 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2418 if (link_speed & ETH_LINK_SPEED_25G)
2419 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2420 if (link_speed & ETH_LINK_SPEED_40G)
2421 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2422 if (link_speed & ETH_LINK_SPEED_50G)
2423 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2424 if (link_speed & ETH_LINK_SPEED_100G)
2425 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2429 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2431 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2433 switch (hw_link_speed) {
2434 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2435 eth_link_speed = ETH_SPEED_NUM_100M;
2437 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2438 eth_link_speed = ETH_SPEED_NUM_1G;
2440 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2441 eth_link_speed = ETH_SPEED_NUM_2_5G;
2443 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2444 eth_link_speed = ETH_SPEED_NUM_10G;
2446 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2447 eth_link_speed = ETH_SPEED_NUM_20G;
2449 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2450 eth_link_speed = ETH_SPEED_NUM_25G;
2452 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2453 eth_link_speed = ETH_SPEED_NUM_40G;
2455 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2456 eth_link_speed = ETH_SPEED_NUM_50G;
2458 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2459 eth_link_speed = ETH_SPEED_NUM_100G;
2461 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2463 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2467 return eth_link_speed;
2470 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2472 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2474 switch (hw_link_duplex) {
2475 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2476 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2478 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2480 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2481 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2484 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2488 return eth_link_duplex;
2491 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2494 struct bnxt_link_info *link_info = &bp->link_info;
2496 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2499 "Get link config failed with rc %d\n", rc);
2502 if (link_info->link_speed)
2504 bnxt_parse_hw_link_speed(link_info->link_speed);
2506 link->link_speed = ETH_SPEED_NUM_NONE;
2507 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2508 link->link_status = link_info->link_up;
2509 link->link_autoneg = link_info->auto_mode ==
2510 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2511 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2516 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2519 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2520 struct bnxt_link_info link_req;
2521 uint16_t speed, autoneg;
2523 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2526 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2527 bp->eth_dev->data->port_id);
2531 memset(&link_req, 0, sizeof(link_req));
2532 link_req.link_up = link_up;
2536 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2537 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2538 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2539 /* Autoneg can be done only when the FW allows */
2540 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2541 bp->link_info.force_link_speed)) {
2542 link_req.phy_flags |=
2543 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2544 link_req.auto_link_speed_mask =
2545 bnxt_parse_eth_link_speed_mask(bp,
2546 dev_conf->link_speeds);
2548 if (bp->link_info.phy_type ==
2549 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2550 bp->link_info.phy_type ==
2551 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2552 bp->link_info.media_type ==
2553 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2554 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2558 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2559 /* If user wants a particular speed try that first. */
2561 link_req.link_speed = speed;
2562 else if (bp->link_info.force_link_speed)
2563 link_req.link_speed = bp->link_info.force_link_speed;
2565 link_req.link_speed = bp->link_info.auto_link_speed;
2567 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2568 link_req.auto_pause = bp->link_info.auto_pause;
2569 link_req.force_pause = bp->link_info.force_pause;
2572 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2575 "Set link config failed with rc %d\n", rc);
2583 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2585 struct hwrm_func_qcfg_input req = {0};
2586 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2590 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2591 req.fid = rte_cpu_to_le_16(0xffff);
2593 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2595 HWRM_CHECK_RESULT();
2597 /* Hard Coded.. 0xfff VLAN ID mask */
2598 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2599 flags = rte_le_to_cpu_16(resp->flags);
2600 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2601 bp->flags |= BNXT_FLAG_MULTI_HOST;
2603 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2604 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2605 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2608 switch (resp->port_partition_type) {
2609 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2610 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2611 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2613 bp->port_partition_type = resp->port_partition_type;
2616 bp->port_partition_type = 0;
2625 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2626 struct hwrm_func_qcaps_output *qcaps)
2628 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2629 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2630 sizeof(qcaps->mac_address));
2631 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2632 qcaps->max_rx_rings = fcfg->num_rx_rings;
2633 qcaps->max_tx_rings = fcfg->num_tx_rings;
2634 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2635 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2637 qcaps->first_vf_id = 0;
2638 qcaps->max_vnics = fcfg->num_vnics;
2639 qcaps->max_decap_records = 0;
2640 qcaps->max_encap_records = 0;
2641 qcaps->max_tx_wm_flows = 0;
2642 qcaps->max_tx_em_flows = 0;
2643 qcaps->max_rx_wm_flows = 0;
2644 qcaps->max_rx_em_flows = 0;
2645 qcaps->max_flow_id = 0;
2646 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2647 qcaps->max_sp_tx_rings = 0;
2648 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2651 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2653 struct hwrm_func_cfg_input req = {0};
2654 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2658 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2659 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2660 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2661 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2662 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2663 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2664 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2665 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2666 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2668 if (BNXT_HAS_RING_GRPS(bp)) {
2669 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2670 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2671 } else if (BNXT_HAS_NQ(bp)) {
2672 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2673 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2676 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2677 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2678 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2679 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2681 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2682 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2683 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2684 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2685 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2686 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2687 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2688 req.fid = rte_cpu_to_le_16(0xffff);
2689 req.enables = rte_cpu_to_le_32(enables);
2691 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2693 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2695 HWRM_CHECK_RESULT();
2701 static void populate_vf_func_cfg_req(struct bnxt *bp,
2702 struct hwrm_func_cfg_input *req,
2705 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2706 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2707 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2708 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2709 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2710 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2711 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2712 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2713 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2714 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2716 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2717 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2719 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2720 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2722 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2724 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2725 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2727 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2728 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2729 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2730 /* TODO: For now, do not support VMDq/RFS on VFs. */
2731 req->num_vnics = rte_cpu_to_le_16(1);
2732 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2736 static void add_random_mac_if_needed(struct bnxt *bp,
2737 struct hwrm_func_cfg_input *cfg_req,
2740 struct rte_ether_addr mac;
2742 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2745 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2747 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2748 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2749 bp->pf.vf_info[vf].random_mac = true;
2751 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2752 RTE_ETHER_ADDR_LEN);
2756 static void reserve_resources_from_vf(struct bnxt *bp,
2757 struct hwrm_func_cfg_input *cfg_req,
2760 struct hwrm_func_qcaps_input req = {0};
2761 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2764 /* Get the actual allocated values now */
2765 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2766 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2767 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2770 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2771 copy_func_cfg_to_qcaps(cfg_req, resp);
2772 } else if (resp->error_code) {
2773 rc = rte_le_to_cpu_16(resp->error_code);
2774 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2775 copy_func_cfg_to_qcaps(cfg_req, resp);
2778 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2779 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2780 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2781 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2782 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2783 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2785 * TODO: While not supporting VMDq with VFs, max_vnics is always
2786 * forced to 1 in this case
2788 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2789 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2794 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2796 struct hwrm_func_qcfg_input req = {0};
2797 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2800 /* Check for zero MAC address */
2801 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2802 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2803 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2805 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2807 } else if (resp->error_code) {
2808 rc = rte_le_to_cpu_16(resp->error_code);
2809 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2812 rc = rte_le_to_cpu_16(resp->vlan);
2819 static int update_pf_resource_max(struct bnxt *bp)
2821 struct hwrm_func_qcfg_input req = {0};
2822 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2825 /* And copy the allocated numbers into the pf struct */
2826 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2827 req.fid = rte_cpu_to_le_16(0xffff);
2828 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2829 HWRM_CHECK_RESULT();
2831 /* Only TX ring value reflects actual allocation? TODO */
2832 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2833 bp->pf.evb_mode = resp->evb_mode;
2840 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2845 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2849 rc = bnxt_hwrm_func_qcaps(bp);
2853 bp->pf.func_cfg_flags &=
2854 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2855 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2856 bp->pf.func_cfg_flags |=
2857 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2858 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2859 rc = __bnxt_hwrm_func_qcaps(bp);
2863 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2865 struct hwrm_func_cfg_input req = {0};
2866 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2873 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2877 rc = bnxt_hwrm_func_qcaps(bp);
2882 bp->pf.active_vfs = num_vfs;
2885 * First, configure the PF to only use one TX ring. This ensures that
2886 * there are enough rings for all VFs.
2888 * If we don't do this, when we call func_alloc() later, we will lock
2889 * extra rings to the PF that won't be available during func_cfg() of
2892 * This has been fixed with firmware versions above 20.6.54
2894 bp->pf.func_cfg_flags &=
2895 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2896 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2897 bp->pf.func_cfg_flags |=
2898 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2899 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2904 * Now, create and register a buffer to hold forwarded VF requests
2906 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2907 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2908 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2909 if (bp->pf.vf_req_buf == NULL) {
2913 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2914 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2915 for (i = 0; i < num_vfs; i++)
2916 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2917 (i * HWRM_MAX_REQ_LEN);
2919 rc = bnxt_hwrm_func_buf_rgtr(bp);
2923 populate_vf_func_cfg_req(bp, &req, num_vfs);
2925 bp->pf.active_vfs = 0;
2926 for (i = 0; i < num_vfs; i++) {
2927 add_random_mac_if_needed(bp, &req, i);
2929 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2930 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2931 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2932 rc = bnxt_hwrm_send_message(bp,
2937 /* Clear enable flag for next pass */
2938 req.enables &= ~rte_cpu_to_le_32(
2939 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2941 if (rc || resp->error_code) {
2943 "Failed to initizlie VF %d\n", i);
2945 "Not all VFs available. (%d, %d)\n",
2946 rc, resp->error_code);
2953 reserve_resources_from_vf(bp, &req, i);
2954 bp->pf.active_vfs++;
2955 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2959 * Now configure the PF to use "the rest" of the resources
2960 * We're using STD_TX_RING_MODE here though which will limit the TX
2961 * rings. This will allow QoS to function properly. Not setting this
2962 * will cause PF rings to break bandwidth settings.
2964 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2968 rc = update_pf_resource_max(bp);
2975 bnxt_hwrm_func_buf_unrgtr(bp);
2979 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2981 struct hwrm_func_cfg_input req = {0};
2982 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2985 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2987 req.fid = rte_cpu_to_le_16(0xffff);
2988 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2989 req.evb_mode = bp->pf.evb_mode;
2991 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2992 HWRM_CHECK_RESULT();
2998 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2999 uint8_t tunnel_type)
3001 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3002 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3005 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3006 req.tunnel_type = tunnel_type;
3007 req.tunnel_dst_port_val = port;
3008 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3009 HWRM_CHECK_RESULT();
3011 switch (tunnel_type) {
3012 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3013 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3014 bp->vxlan_port = port;
3016 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3017 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3018 bp->geneve_port = port;
3029 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3030 uint8_t tunnel_type)
3032 struct hwrm_tunnel_dst_port_free_input req = {0};
3033 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3036 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3038 req.tunnel_type = tunnel_type;
3039 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3040 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3042 HWRM_CHECK_RESULT();
3048 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3051 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3052 struct hwrm_func_cfg_input req = {0};
3055 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3057 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3058 req.flags = rte_cpu_to_le_32(flags);
3059 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3061 HWRM_CHECK_RESULT();
3067 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3069 uint32_t *flag = flagp;
3071 vnic->flags = *flag;
3074 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3076 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3079 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3082 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3083 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3085 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3087 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3088 req.req_buf_page_size = rte_cpu_to_le_16(
3089 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3090 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3091 req.req_buf_page_addr0 =
3092 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3093 if (req.req_buf_page_addr0 == 0) {
3095 "unable to map buffer address to physical memory\n");
3099 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3101 HWRM_CHECK_RESULT();
3107 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3110 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3111 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3113 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3115 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3117 HWRM_CHECK_RESULT();
3123 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3125 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3126 struct hwrm_func_cfg_input req = {0};
3129 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3131 req.fid = rte_cpu_to_le_16(0xffff);
3132 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3133 req.enables = rte_cpu_to_le_32(
3134 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3135 req.async_event_cr = rte_cpu_to_le_16(
3136 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3137 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3139 HWRM_CHECK_RESULT();
3145 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3147 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3148 struct hwrm_func_vf_cfg_input req = {0};
3151 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3153 req.enables = rte_cpu_to_le_32(
3154 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3155 req.async_event_cr = rte_cpu_to_le_16(
3156 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3157 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3159 HWRM_CHECK_RESULT();
3165 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3167 struct hwrm_func_cfg_input req = {0};
3168 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3169 uint16_t dflt_vlan, fid;
3170 uint32_t func_cfg_flags;
3173 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3176 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3177 fid = bp->pf.vf_info[vf].fid;
3178 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3180 fid = rte_cpu_to_le_16(0xffff);
3181 func_cfg_flags = bp->pf.func_cfg_flags;
3182 dflt_vlan = bp->vlan;
3185 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3186 req.fid = rte_cpu_to_le_16(fid);
3187 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3188 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3190 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3192 HWRM_CHECK_RESULT();
3198 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3199 uint16_t max_bw, uint16_t enables)
3201 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3202 struct hwrm_func_cfg_input req = {0};
3205 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3207 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3208 req.enables |= rte_cpu_to_le_32(enables);
3209 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3210 req.max_bw = rte_cpu_to_le_32(max_bw);
3211 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3213 HWRM_CHECK_RESULT();
3219 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3221 struct hwrm_func_cfg_input req = {0};
3222 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3225 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3227 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3228 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3229 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3230 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3232 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3234 HWRM_CHECK_RESULT();
3240 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3245 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3247 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3252 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3253 void *encaped, size_t ec_size)
3256 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3257 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3259 if (ec_size > sizeof(req.encap_request))
3262 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3264 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3265 memcpy(req.encap_request, encaped, ec_size);
3267 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3269 HWRM_CHECK_RESULT();
3275 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3276 struct rte_ether_addr *mac)
3278 struct hwrm_func_qcfg_input req = {0};
3279 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3282 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3284 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3285 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3287 HWRM_CHECK_RESULT();
3289 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3296 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3297 void *encaped, size_t ec_size)
3300 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3301 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3303 if (ec_size > sizeof(req.encap_request))
3306 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3308 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3309 memcpy(req.encap_request, encaped, ec_size);
3311 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3313 HWRM_CHECK_RESULT();
3319 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3320 struct rte_eth_stats *stats, uint8_t rx)
3323 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3324 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3326 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3328 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3330 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3332 HWRM_CHECK_RESULT();
3335 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3336 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3337 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3338 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3339 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3340 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3341 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3342 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3344 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3345 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3346 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3347 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3348 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3349 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3358 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3360 struct hwrm_port_qstats_input req = {0};
3361 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3362 struct bnxt_pf_info *pf = &bp->pf;
3365 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3367 req.port_id = rte_cpu_to_le_16(pf->port_id);
3368 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3369 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3370 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3372 HWRM_CHECK_RESULT();
3378 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3380 struct hwrm_port_clr_stats_input req = {0};
3381 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3382 struct bnxt_pf_info *pf = &bp->pf;
3385 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3386 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3387 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3390 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3392 req.port_id = rte_cpu_to_le_16(pf->port_id);
3393 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3395 HWRM_CHECK_RESULT();
3401 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3403 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3404 struct hwrm_port_led_qcaps_input req = {0};
3410 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3411 req.port_id = bp->pf.port_id;
3412 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3414 HWRM_CHECK_RESULT();
3416 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3419 bp->num_leds = resp->num_leds;
3420 memcpy(bp->leds, &resp->led0_id,
3421 sizeof(bp->leds[0]) * bp->num_leds);
3422 for (i = 0; i < bp->num_leds; i++) {
3423 struct bnxt_led_info *led = &bp->leds[i];
3425 uint16_t caps = led->led_state_caps;
3427 if (!led->led_group_id ||
3428 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3440 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3442 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3443 struct hwrm_port_led_cfg_input req = {0};
3444 struct bnxt_led_cfg *led_cfg;
3445 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3446 uint16_t duration = 0;
3449 if (!bp->num_leds || BNXT_VF(bp))
3452 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3455 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3456 duration = rte_cpu_to_le_16(500);
3458 req.port_id = bp->pf.port_id;
3459 req.num_leds = bp->num_leds;
3460 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3461 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3462 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3463 led_cfg->led_id = bp->leds[i].led_id;
3464 led_cfg->led_state = led_state;
3465 led_cfg->led_blink_on = duration;
3466 led_cfg->led_blink_off = duration;
3467 led_cfg->led_group_id = bp->leds[i].led_group_id;
3470 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3472 HWRM_CHECK_RESULT();
3478 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3482 struct hwrm_nvm_get_dir_info_input req = {0};
3483 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3485 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3487 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3489 HWRM_CHECK_RESULT();
3493 *entries = rte_le_to_cpu_32(resp->entries);
3494 *length = rte_le_to_cpu_32(resp->entry_length);
3499 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3502 uint32_t dir_entries;
3503 uint32_t entry_length;
3506 rte_iova_t dma_handle;
3507 struct hwrm_nvm_get_dir_entries_input req = {0};
3508 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3510 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3514 *data++ = dir_entries;
3515 *data++ = entry_length;
3517 memset(data, 0xff, len);
3519 buflen = dir_entries * entry_length;
3520 buf = rte_malloc("nvm_dir", buflen, 0);
3521 rte_mem_lock_page(buf);
3524 dma_handle = rte_mem_virt2iova(buf);
3525 if (dma_handle == 0) {
3527 "unable to map response address to physical memory\n");
3530 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3531 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3532 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3535 memcpy(data, buf, len > buflen ? buflen : len);
3538 HWRM_CHECK_RESULT();
3544 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3545 uint32_t offset, uint32_t length,
3550 rte_iova_t dma_handle;
3551 struct hwrm_nvm_read_input req = {0};
3552 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3554 buf = rte_malloc("nvm_item", length, 0);
3555 rte_mem_lock_page(buf);
3559 dma_handle = rte_mem_virt2iova(buf);
3560 if (dma_handle == 0) {
3562 "unable to map response address to physical memory\n");
3565 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3566 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3567 req.dir_idx = rte_cpu_to_le_16(index);
3568 req.offset = rte_cpu_to_le_32(offset);
3569 req.len = rte_cpu_to_le_32(length);
3570 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3572 memcpy(data, buf, length);
3575 HWRM_CHECK_RESULT();
3581 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3584 struct hwrm_nvm_erase_dir_entry_input req = {0};
3585 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3587 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3588 req.dir_idx = rte_cpu_to_le_16(index);
3589 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3590 HWRM_CHECK_RESULT();
3597 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3598 uint16_t dir_ordinal, uint16_t dir_ext,
3599 uint16_t dir_attr, const uint8_t *data,
3603 struct hwrm_nvm_write_input req = {0};
3604 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3605 rte_iova_t dma_handle;
3608 buf = rte_malloc("nvm_write", data_len, 0);
3609 rte_mem_lock_page(buf);
3613 dma_handle = rte_mem_virt2iova(buf);
3614 if (dma_handle == 0) {
3616 "unable to map response address to physical memory\n");
3619 memcpy(buf, data, data_len);
3621 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3623 req.dir_type = rte_cpu_to_le_16(dir_type);
3624 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3625 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3626 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3627 req.dir_data_length = rte_cpu_to_le_32(data_len);
3628 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3630 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3633 HWRM_CHECK_RESULT();
3640 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3642 uint32_t *count = cbdata;
3644 *count = *count + 1;
3647 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3648 struct bnxt_vnic_info *vnic __rte_unused)
3653 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3657 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3658 &count, bnxt_vnic_count_hwrm_stub);
3663 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3666 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3667 struct hwrm_func_vf_vnic_ids_query_output *resp =
3668 bp->hwrm_cmd_resp_addr;
3671 /* First query all VNIC ids */
3672 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3674 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3675 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3676 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3678 if (req.vnic_id_tbl_addr == 0) {
3681 "unable to map VNIC ID table address to physical memory\n");
3684 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3687 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3689 } else if (resp->error_code) {
3690 rc = rte_le_to_cpu_16(resp->error_code);
3692 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3695 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3703 * This function queries the VNIC IDs for a specified VF. It then calls
3704 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3705 * Then it calls the hwrm_cb function to program this new vnic configuration.
3707 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3708 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3709 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3711 struct bnxt_vnic_info vnic;
3713 int i, num_vnic_ids;
3718 /* First query all VNIC ids */
3719 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3720 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3721 RTE_CACHE_LINE_SIZE);
3722 if (vnic_ids == NULL) {
3726 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3727 rte_mem_lock_page(((char *)vnic_ids) + sz);
3729 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3731 if (num_vnic_ids < 0)
3732 return num_vnic_ids;
3734 /* Retrieve VNIC, update bd_stall then update */
3736 for (i = 0; i < num_vnic_ids; i++) {
3737 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3738 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3739 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3742 if (vnic.mru <= 4) /* Indicates unallocated */
3745 vnic_cb(&vnic, cbdata);
3747 rc = hwrm_cb(bp, &vnic);
3757 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3760 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3761 struct hwrm_func_cfg_input req = {0};
3764 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3766 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3767 req.enables |= rte_cpu_to_le_32(
3768 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3769 req.vlan_antispoof_mode = on ?
3770 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3771 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3772 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3774 HWRM_CHECK_RESULT();
3780 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3782 struct bnxt_vnic_info vnic;
3785 int num_vnic_ids, i;
3789 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3790 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3791 RTE_CACHE_LINE_SIZE);
3792 if (vnic_ids == NULL) {
3797 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3798 rte_mem_lock_page(((char *)vnic_ids) + sz);
3800 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3806 * Loop through to find the default VNIC ID.
3807 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3808 * by sending the hwrm_func_qcfg command to the firmware.
3810 for (i = 0; i < num_vnic_ids; i++) {
3811 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3812 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3813 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3814 bp->pf.first_vf_id + vf);
3817 if (vnic.func_default) {
3819 return vnic.fw_vnic_id;
3822 /* Could not find a default VNIC. */
3823 PMD_DRV_LOG(ERR, "No default VNIC\n");
3829 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3831 struct bnxt_filter_info *filter)
3834 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3835 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3836 uint32_t enables = 0;
3838 if (filter->fw_em_filter_id != UINT64_MAX)
3839 bnxt_hwrm_clear_em_filter(bp, filter);
3841 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3843 req.flags = rte_cpu_to_le_32(filter->flags);
3845 enables = filter->enables |
3846 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3847 req.dst_id = rte_cpu_to_le_16(dst_id);
3849 if (filter->ip_addr_type) {
3850 req.ip_addr_type = filter->ip_addr_type;
3851 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3854 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3855 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3857 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3858 memcpy(req.src_macaddr, filter->src_macaddr,
3859 RTE_ETHER_ADDR_LEN);
3861 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3862 memcpy(req.dst_macaddr, filter->dst_macaddr,
3863 RTE_ETHER_ADDR_LEN);
3865 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3866 req.ovlan_vid = filter->l2_ovlan;
3868 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3869 req.ivlan_vid = filter->l2_ivlan;
3871 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3872 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3874 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3875 req.ip_protocol = filter->ip_protocol;
3877 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3878 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3880 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3881 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3883 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3884 req.src_port = rte_cpu_to_be_16(filter->src_port);
3886 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3887 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3889 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3890 req.mirror_vnic_id = filter->mirror_vnic_id;
3892 req.enables = rte_cpu_to_le_32(enables);
3894 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3896 HWRM_CHECK_RESULT();
3898 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3904 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3907 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3908 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3910 if (filter->fw_em_filter_id == UINT64_MAX)
3913 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3914 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3916 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3918 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3920 HWRM_CHECK_RESULT();
3923 filter->fw_em_filter_id = UINT64_MAX;
3924 filter->fw_l2_filter_id = UINT64_MAX;
3929 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3931 struct bnxt_filter_info *filter)
3934 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3935 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3936 bp->hwrm_cmd_resp_addr;
3937 uint32_t enables = 0;
3939 if (filter->fw_ntuple_filter_id != UINT64_MAX)
3940 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3942 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
3944 req.flags = rte_cpu_to_le_32(filter->flags);
3946 enables = filter->enables |
3947 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3948 req.dst_id = rte_cpu_to_le_16(dst_id);
3951 if (filter->ip_addr_type) {
3952 req.ip_addr_type = filter->ip_addr_type;
3954 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3957 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3958 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3960 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3961 memcpy(req.src_macaddr, filter->src_macaddr,
3962 RTE_ETHER_ADDR_LEN);
3964 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3965 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3966 //RTE_ETHER_ADDR_LEN);
3968 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3969 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3971 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3972 req.ip_protocol = filter->ip_protocol;
3974 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3975 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3977 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3978 req.src_ipaddr_mask[0] =
3979 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3981 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3982 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3984 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3985 req.dst_ipaddr_mask[0] =
3986 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3988 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3989 req.src_port = rte_cpu_to_le_16(filter->src_port);
3991 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3992 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3994 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3995 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3997 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3998 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4000 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4001 req.mirror_vnic_id = filter->mirror_vnic_id;
4003 req.enables = rte_cpu_to_le_32(enables);
4005 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4007 HWRM_CHECK_RESULT();
4009 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4015 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4016 struct bnxt_filter_info *filter)
4019 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4020 struct hwrm_cfa_ntuple_filter_free_output *resp =
4021 bp->hwrm_cmd_resp_addr;
4023 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4026 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4028 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4030 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4032 HWRM_CHECK_RESULT();
4035 filter->fw_ntuple_filter_id = UINT64_MAX;
4040 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4042 unsigned int rss_idx, fw_idx, i;
4044 if (vnic->rss_table && vnic->hash_type) {
4046 * Fill the RSS hash & redirection table with
4047 * ring group ids for all VNICs
4049 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4050 rss_idx++, fw_idx++) {
4051 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4052 fw_idx %= bp->rx_cp_nr_rings;
4053 if (vnic->fw_grp_ids[fw_idx] !=
4058 if (i == bp->rx_cp_nr_rings)
4060 vnic->rss_table[rss_idx] =
4061 vnic->fw_grp_ids[fw_idx];
4063 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4068 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4069 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4073 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4075 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4076 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4078 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4079 req->num_cmpl_dma_aggr_during_int =
4080 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4082 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4084 /* min timer set to 1/2 of interrupt timer */
4085 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4087 /* buf timer set to 1/4 of interrupt timer */
4088 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4090 req->cmpl_aggr_dma_tmr_during_int =
4091 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4093 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4094 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4095 req->flags = rte_cpu_to_le_16(flags);
4098 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4099 struct bnxt_coal *coal, uint16_t ring_id)
4101 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4102 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4103 bp->hwrm_cmd_resp_addr;
4106 /* Set ring coalesce parameters only for Stratus 100G NIC */
4107 if (!bnxt_stratus_device(bp))
4110 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4111 bnxt_hwrm_set_coal_params(coal, &req);
4112 req.ring_id = rte_cpu_to_le_16(ring_id);
4113 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4114 HWRM_CHECK_RESULT();
4119 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4120 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4122 struct hwrm_func_backing_store_qcaps_input req = {0};
4123 struct hwrm_func_backing_store_qcaps_output *resp =
4124 bp->hwrm_cmd_resp_addr;
4127 if (!BNXT_CHIP_THOR(bp) ||
4128 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4133 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4134 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4135 HWRM_CHECK_RESULT_SILENT();
4138 struct bnxt_ctx_pg_info *ctx_pg;
4139 struct bnxt_ctx_mem_info *ctx;
4140 int total_alloc_len;
4143 total_alloc_len = sizeof(*ctx);
4144 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4145 RTE_CACHE_LINE_SIZE);
4150 memset(ctx, 0, total_alloc_len);
4152 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4153 sizeof(*ctx_pg) * BNXT_MAX_Q,
4154 RTE_CACHE_LINE_SIZE);
4159 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4160 ctx->tqm_mem[i] = ctx_pg;
4163 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4164 ctx->qp_min_qp1_entries =
4165 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4166 ctx->qp_max_l2_entries =
4167 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4168 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4169 ctx->srq_max_l2_entries =
4170 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4171 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4172 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4173 ctx->cq_max_l2_entries =
4174 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4175 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4176 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4177 ctx->vnic_max_vnic_entries =
4178 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4179 ctx->vnic_max_ring_table_entries =
4180 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4181 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4182 ctx->stat_max_entries =
4183 rte_le_to_cpu_32(resp->stat_max_entries);
4184 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4185 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4186 ctx->tqm_min_entries_per_ring =
4187 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4188 ctx->tqm_max_entries_per_ring =
4189 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4190 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4191 if (!ctx->tqm_entries_multiple)
4192 ctx->tqm_entries_multiple = 1;
4193 ctx->mrav_max_entries =
4194 rte_le_to_cpu_32(resp->mrav_max_entries);
4195 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4196 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4197 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4206 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4208 struct hwrm_func_backing_store_cfg_input req = {0};
4209 struct hwrm_func_backing_store_cfg_output *resp =
4210 bp->hwrm_cmd_resp_addr;
4211 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4212 struct bnxt_ctx_pg_info *ctx_pg;
4213 uint32_t *num_entries;
4222 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4223 req.enables = rte_cpu_to_le_32(enables);
4225 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4226 ctx_pg = &ctx->qp_mem;
4227 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4228 req.qp_num_qp1_entries =
4229 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4230 req.qp_num_l2_entries =
4231 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4232 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4233 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4234 &req.qpc_pg_size_qpc_lvl,
4238 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4239 ctx_pg = &ctx->srq_mem;
4240 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4241 req.srq_num_l2_entries =
4242 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4243 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4244 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4245 &req.srq_pg_size_srq_lvl,
4249 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4250 ctx_pg = &ctx->cq_mem;
4251 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4252 req.cq_num_l2_entries =
4253 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4254 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4255 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4256 &req.cq_pg_size_cq_lvl,
4260 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4261 ctx_pg = &ctx->vnic_mem;
4262 req.vnic_num_vnic_entries =
4263 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4264 req.vnic_num_ring_table_entries =
4265 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4266 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4267 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4268 &req.vnic_pg_size_vnic_lvl,
4269 &req.vnic_page_dir);
4272 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4273 ctx_pg = &ctx->stat_mem;
4274 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4275 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4276 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4277 &req.stat_pg_size_stat_lvl,
4278 &req.stat_page_dir);
4281 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4282 num_entries = &req.tqm_sp_num_entries;
4283 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4284 pg_dir = &req.tqm_sp_page_dir;
4285 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4286 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4287 if (!(enables & ena))
4290 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4292 ctx_pg = ctx->tqm_mem[i];
4293 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4294 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4297 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4298 HWRM_CHECK_RESULT();
4305 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4307 struct hwrm_port_qstats_ext_input req = {0};
4308 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4309 struct bnxt_pf_info *pf = &bp->pf;
4312 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4313 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4316 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4318 req.port_id = rte_cpu_to_le_16(pf->port_id);
4319 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4320 req.tx_stat_host_addr =
4321 rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4323 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4325 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4326 req.rx_stat_host_addr =
4327 rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4329 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4331 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4334 bp->fw_rx_port_stats_ext_size = 0;
4335 bp->fw_tx_port_stats_ext_size = 0;
4337 bp->fw_rx_port_stats_ext_size =
4338 rte_le_to_cpu_16(resp->rx_stat_size);
4339 bp->fw_tx_port_stats_ext_size =
4340 rte_le_to_cpu_16(resp->tx_stat_size);
4343 HWRM_CHECK_RESULT();