4 * Copyright(c) Broadcom Limited.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_byteorder.h>
35 #include <rte_common.h>
36 #include <rte_cycles.h>
37 #include <rte_malloc.h>
38 #include <rte_memzone.h>
39 #include <rte_version.h>
43 #include "bnxt_filter.h"
44 #include "bnxt_hwrm.h"
47 #include "bnxt_ring.h"
50 #include "bnxt_vnic.h"
51 #include "hsi_struct_def_dpdk.h"
53 #define HWRM_CMD_TIMEOUT 2000
56 * HWRM Functions (sent to HWRM)
57 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
58 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
59 * command was failed by the ChiMP.
62 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
66 struct input *req = msg;
67 struct output *resp = bp->hwrm_cmd_resp_addr;
72 /* Write request msg to hwrm channel */
73 for (i = 0; i < msg_len; i += 4) {
74 bar = (uint8_t *)bp->bar0 + i;
75 *(volatile uint32_t *)bar = *data;
79 /* Zero the rest of the request space */
80 for (; i < bp->max_req_len; i += 4) {
81 bar = (uint8_t *)bp->bar0 + i;
82 *(volatile uint32_t *)bar = 0;
85 /* Ring channel doorbell */
86 bar = (uint8_t *)bp->bar0 + 0x100;
87 *(volatile uint32_t *)bar = 1;
89 /* Poll for the valid bit */
90 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
91 /* Sanity check on the resp->resp_len */
93 if (resp->resp_len && resp->resp_len <=
95 /* Last byte of resp contains the valid key */
96 valid = (uint8_t *)resp + resp->resp_len - 1;
97 if (*valid == HWRM_RESP_VALID_KEY)
103 if (i >= HWRM_CMD_TIMEOUT) {
104 RTE_LOG(ERR, PMD, "Error sending msg %x\n",
114 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
118 rte_spinlock_lock(&bp->hwrm_lock);
119 rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
120 rte_spinlock_unlock(&bp->hwrm_lock);
124 #define HWRM_PREP(req, type, cr, resp) \
125 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
126 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
127 req.cmpl_ring = rte_cpu_to_le_16(cr); \
128 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
129 req.target_id = rte_cpu_to_le_16(0xffff); \
130 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
132 #define HWRM_CHECK_RESULT \
135 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
139 if (resp->error_code) { \
140 rc = rte_le_to_cpu_16(resp->error_code); \
141 RTE_LOG(ERR, PMD, "%s error %d\n", __func__, rc); \
146 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
149 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
150 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
152 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
153 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
156 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
163 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
166 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
167 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
170 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
171 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
173 /* FIXME add multicast flag, when multicast adding options is supported
176 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
177 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
178 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
179 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
180 req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
183 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
190 int bnxt_hwrm_clear_filter(struct bnxt *bp,
191 struct bnxt_filter_info *filter)
194 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
195 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
197 HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
199 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
201 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
205 filter->fw_l2_filter_id = -1;
210 int bnxt_hwrm_set_filter(struct bnxt *bp,
211 struct bnxt_vnic_info *vnic,
212 struct bnxt_filter_info *filter)
215 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
216 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
217 uint32_t enables = 0;
219 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
221 req.flags = rte_cpu_to_le_32(filter->flags);
223 enables = filter->enables |
224 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
225 req.dst_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
228 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
229 memcpy(req.l2_addr, filter->l2_addr,
232 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
233 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
236 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
237 req.l2_ovlan = filter->l2_ovlan;
239 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
240 req.l2_ovlan_mask = filter->l2_ovlan_mask;
242 req.enables = rte_cpu_to_le_32(enables);
244 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
248 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
253 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, void *fwd_cmd)
256 struct hwrm_exec_fwd_resp_input req = {.req_type = 0 };
257 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
259 HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
261 memcpy(req.encap_request, fwd_cmd,
262 sizeof(req.encap_request));
264 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
271 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
274 struct hwrm_func_qcaps_input req = {.req_type = 0 };
275 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
277 HWRM_PREP(req, FUNC_QCAPS, -1, resp);
279 req.fid = rte_cpu_to_le_16(0xffff);
281 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
285 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
287 struct bnxt_pf_info *pf = &bp->pf;
289 pf->fw_fid = rte_le_to_cpu_32(resp->fid);
290 pf->port_id = resp->port_id;
291 memcpy(pf->mac_addr, resp->perm_mac_address, ETHER_ADDR_LEN);
292 pf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
293 pf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
294 pf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
295 pf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
296 pf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
297 pf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
298 pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
299 pf->max_vfs = rte_le_to_cpu_16(resp->max_vfs);
301 struct bnxt_vf_info *vf = &bp->vf;
303 vf->fw_fid = rte_le_to_cpu_32(resp->fid);
304 memcpy(vf->mac_addr, &resp->perm_mac_address, ETHER_ADDR_LEN);
305 vf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
306 vf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
307 vf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
308 vf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
309 vf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
310 vf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
316 int bnxt_hwrm_func_reset(struct bnxt *bp)
319 struct hwrm_func_reset_input req = {.req_type = 0 };
320 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
322 HWRM_PREP(req, FUNC_RESET, -1, resp);
324 req.enables = rte_cpu_to_le_32(0);
326 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
333 int bnxt_hwrm_func_driver_register(struct bnxt *bp, uint32_t flags,
334 uint32_t *vf_req_fwd)
337 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
338 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
340 if (bp->flags & BNXT_FLAG_REGISTERED)
343 HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
345 req.enables = HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER;
346 req.ver_maj = RTE_VER_YEAR;
347 req.ver_min = RTE_VER_MONTH;
348 req.ver_upd = RTE_VER_MINOR;
350 memcpy(req.vf_req_fwd, vf_req_fwd, sizeof(req.vf_req_fwd));
352 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
356 bp->flags |= BNXT_FLAG_REGISTERED;
361 int bnxt_hwrm_ver_get(struct bnxt *bp)
364 struct hwrm_ver_get_input req = {.req_type = 0 };
365 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
368 uint16_t max_resp_len;
369 char type[RTE_MEMZONE_NAMESIZE];
371 HWRM_PREP(req, VER_GET, -1, resp);
373 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
374 req.hwrm_intf_min = HWRM_VERSION_MINOR;
375 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
378 * Hold the lock since we may be adjusting the response pointers.
380 rte_spinlock_lock(&bp->hwrm_lock);
381 rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
385 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
386 resp->hwrm_intf_maj, resp->hwrm_intf_min,
388 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
390 my_version = HWRM_VERSION_MAJOR << 16;
391 my_version |= HWRM_VERSION_MINOR << 8;
392 my_version |= HWRM_VERSION_UPDATE;
394 fw_version = resp->hwrm_intf_maj << 16;
395 fw_version |= resp->hwrm_intf_min << 8;
396 fw_version |= resp->hwrm_intf_upd;
398 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
399 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
404 if (my_version != fw_version) {
405 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
406 if (my_version < fw_version) {
408 "Firmware API version is newer than driver.\n");
410 "The driver may be missing features.\n");
413 "Firmware API version is older than driver.\n");
415 "Not all driver features may be functional.\n");
419 if (bp->max_req_len > resp->max_req_win_len) {
420 RTE_LOG(ERR, PMD, "Unsupported request length\n");
423 bp->max_req_len = resp->max_req_win_len;
424 max_resp_len = resp->max_resp_len;
425 if (bp->max_resp_len != max_resp_len) {
426 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
427 bp->pdev->addr.domain, bp->pdev->addr.bus,
428 bp->pdev->addr.devid, bp->pdev->addr.function);
430 rte_free(bp->hwrm_cmd_resp_addr);
432 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
433 if (bp->hwrm_cmd_resp_addr == NULL) {
437 bp->hwrm_cmd_resp_dma_addr =
438 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
439 bp->max_resp_len = max_resp_len;
443 rte_spinlock_unlock(&bp->hwrm_lock);
447 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
450 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
451 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
453 if (!(bp->flags & BNXT_FLAG_REGISTERED))
456 HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
459 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
463 bp->flags &= ~BNXT_FLAG_REGISTERED;
468 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
471 struct hwrm_port_phy_cfg_input req = {.req_type = 0};
472 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
474 HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
476 req.flags = conf->phy_flags;
478 req.force_link_speed = conf->link_speed;
480 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
481 * any auto mode, even "none".
483 if (req.auto_mode == HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE) {
484 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
486 req.auto_mode = conf->auto_mode;
488 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
489 req.auto_link_speed_mask = conf->auto_link_speed_mask;
491 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
492 req.auto_link_speed = conf->auto_link_speed;
494 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
496 req.auto_duplex = conf->duplex;
497 req.enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
498 req.auto_pause = conf->auto_pause;
499 /* Set force_pause if there is no auto or if there is a force */
502 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
505 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
506 req.force_pause = conf->force_pause;
509 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
511 req.flags &= ~HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
512 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN;
513 req.force_link_speed = 0;
516 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
523 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
524 struct bnxt_link_info *link_info)
527 struct hwrm_port_phy_qcfg_input req = {.req_type = 0};
528 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
530 HWRM_PREP(req, PORT_PHY_QCFG, -1, resp);
532 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
536 link_info->phy_link_status = resp->link;
537 if (link_info->phy_link_status == HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) {
538 link_info->link_up = 1;
539 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
541 link_info->link_up = 0;
542 link_info->link_speed = 0;
544 link_info->duplex = resp->duplex;
545 link_info->pause = resp->pause;
546 link_info->auto_pause = resp->auto_pause;
547 link_info->force_pause = resp->force_pause;
548 link_info->auto_mode = resp->auto_mode;
550 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
551 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
552 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
553 link_info->phy_ver[0] = resp->phy_maj;
554 link_info->phy_ver[1] = resp->phy_min;
555 link_info->phy_ver[2] = resp->phy_bld;
560 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
563 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
564 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
566 HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
568 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
572 #define GET_QUEUE_INFO(x) \
573 bp->cos_queue[x].id = resp->queue_id##x; \
574 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
588 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
589 struct bnxt_ring *ring,
590 uint32_t ring_type, uint32_t map_index,
591 uint32_t stats_ctx_id)
594 struct hwrm_ring_alloc_input req = {.req_type = 0 };
595 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
597 HWRM_PREP(req, RING_ALLOC, -1, resp);
599 req.enables = rte_cpu_to_le_32(0);
601 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
602 req.fbo = rte_cpu_to_le_32(0);
603 /* Association of ring index with doorbell index */
604 req.logical_id = rte_cpu_to_le_16(map_index);
607 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
608 req.queue_id = bp->cos_queue[0].id;
609 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
610 req.ring_type = ring_type;
612 rte_cpu_to_le_16(bp->grp_info[map_index].cp_fw_ring_id);
613 req.length = rte_cpu_to_le_32(ring->ring_size);
614 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
615 req.enables = rte_cpu_to_le_32(rte_le_to_cpu_32(req.enables) |
616 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID);
618 case HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL:
619 req.ring_type = ring_type;
621 * TODO: Some HWRM versions crash with
622 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
624 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
625 req.length = rte_cpu_to_le_32(ring->ring_size);
628 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
633 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
635 if (rc || resp->error_code) {
636 if (rc == 0 && resp->error_code)
637 rc = rte_le_to_cpu_16(resp->error_code);
639 case HWRM_RING_FREE_INPUT_RING_TYPE_CMPL:
641 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
643 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
645 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
647 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
649 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
652 RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
657 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
661 int bnxt_hwrm_ring_free(struct bnxt *bp,
662 struct bnxt_ring *ring, uint32_t ring_type)
665 struct hwrm_ring_free_input req = {.req_type = 0 };
666 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
668 HWRM_PREP(req, RING_FREE, -1, resp);
670 req.ring_type = ring_type;
671 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
673 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
675 if (rc || resp->error_code) {
676 if (rc == 0 && resp->error_code)
677 rc = rte_le_to_cpu_16(resp->error_code);
680 case HWRM_RING_FREE_INPUT_RING_TYPE_CMPL:
681 RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
684 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
685 RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
688 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
689 RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
693 RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
700 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
703 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
704 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
706 HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
708 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
709 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
710 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
711 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
713 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
717 bp->grp_info[idx].fw_grp_id =
718 rte_le_to_cpu_16(resp->ring_group_id);
723 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
726 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
727 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
729 HWRM_PREP(req, RING_GRP_FREE, -1, resp);
731 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
733 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
737 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
741 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
744 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
745 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
747 HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
749 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
752 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
753 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
755 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
762 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp,
763 struct bnxt_cp_ring_info *cpr, unsigned int idx)
766 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
767 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
769 HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
771 req.update_period_ms = rte_cpu_to_le_32(1000);
773 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
775 rte_cpu_to_le_64(cpr->hw_stats_map);
777 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
781 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
782 bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
787 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp,
788 struct bnxt_cp_ring_info *cpr, unsigned int idx)
791 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
792 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
794 HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
796 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
797 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
799 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
803 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
804 bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
809 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
812 struct hwrm_vnic_alloc_input req = {.req_type = 0 };
813 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
815 /* map ring groups to this vnic */
816 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++) {
817 if (bp->grp_info[i].fw_grp_id == (uint16_t)HWRM_NA_SIGNATURE) {
819 "Not enough ring groups avail:%x req:%x\n", j,
820 (vnic->end_grp_id - vnic->start_grp_id) + 1);
823 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
826 vnic->fw_rss_cos_lb_ctx = (uint16_t)HWRM_NA_SIGNATURE;
827 vnic->ctx_is_rss_cos_lb = HW_CONTEXT_NONE;
829 HWRM_PREP(req, VNIC_ALLOC, -1, resp);
831 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
835 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
839 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
842 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
843 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
845 HWRM_PREP(req, VNIC_CFG, -1, resp);
847 /* Only RSS support for now TBD: COS & LB */
849 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
850 HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE |
851 HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
852 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
854 rte_cpu_to_le_16(bp->grp_info[vnic->start_grp_id].fw_grp_id);
855 req.rss_rule = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
856 req.cos_rule = rte_cpu_to_le_16(0xffff);
857 req.lb_rule = rte_cpu_to_le_16(0xffff);
858 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
859 ETHER_CRC_LEN + VLAN_TAG_SIZE);
860 if (vnic->func_default)
862 if (vnic->vlan_strip)
864 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
866 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
873 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
876 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
877 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
878 bp->hwrm_cmd_resp_addr;
880 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
882 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
886 vnic->fw_rss_cos_lb_ctx = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
891 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
894 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
895 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
896 bp->hwrm_cmd_resp_addr;
898 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
900 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
902 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
906 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
911 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
914 struct hwrm_vnic_free_input req = {.req_type = 0 };
915 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
917 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
920 HWRM_PREP(req, VNIC_FREE, -1, resp);
922 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
924 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
928 vnic->fw_vnic_id = INVALID_HW_RING_ID;
932 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
933 struct bnxt_vnic_info *vnic)
936 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
937 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
939 HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
941 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
943 req.ring_grp_tbl_addr =
944 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
945 req.hash_key_tbl_addr =
946 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
947 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
949 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
957 * HWRM utility functions
960 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
965 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
966 struct bnxt_tx_queue *txq;
967 struct bnxt_rx_queue *rxq;
968 struct bnxt_cp_ring_info *cpr;
970 if (i >= bp->rx_cp_nr_rings) {
971 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
974 rxq = bp->rx_queues[i];
978 rc = bnxt_hwrm_stat_clear(bp, cpr);
985 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
989 struct bnxt_cp_ring_info *cpr;
991 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
992 unsigned int idx = i + 1;
994 if (i >= bp->rx_cp_nr_rings)
995 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
997 cpr = bp->rx_queues[i]->cp_ring;
998 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
999 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, idx);
1007 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1012 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1013 struct bnxt_tx_queue *txq;
1014 struct bnxt_rx_queue *rxq;
1015 struct bnxt_cp_ring_info *cpr;
1016 unsigned int idx = i + 1;
1018 if (i >= bp->rx_cp_nr_rings) {
1019 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1022 rxq = bp->rx_queues[i];
1026 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, idx);
1034 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1039 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1040 unsigned int idx = i + 1;
1042 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1044 "Attempt to free invalid ring group %d\n",
1049 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1057 static void bnxt_free_cp_ring(struct bnxt *bp,
1058 struct bnxt_cp_ring_info *cpr, unsigned int idx)
1060 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1062 bnxt_hwrm_ring_free(bp, cp_ring,
1063 HWRM_RING_FREE_INPUT_RING_TYPE_CMPL);
1064 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1065 bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1066 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1067 sizeof(*cpr->cp_desc_ring));
1068 cpr->cp_raw_cons = 0;
1071 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1076 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1077 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1078 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1079 struct bnxt_ring *ring = txr->tx_ring_struct;
1080 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1081 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1083 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1084 bnxt_hwrm_ring_free(bp, ring,
1085 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1086 ring->fw_ring_id = INVALID_HW_RING_ID;
1087 memset(txr->tx_desc_ring, 0,
1088 txr->tx_ring_struct->ring_size *
1089 sizeof(*txr->tx_desc_ring));
1090 memset(txr->tx_buf_ring, 0,
1091 txr->tx_ring_struct->ring_size *
1092 sizeof(*txr->tx_buf_ring));
1096 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1097 bnxt_free_cp_ring(bp, cpr, idx);
1100 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1101 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1102 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1103 struct bnxt_ring *ring = rxr->rx_ring_struct;
1104 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1105 unsigned int idx = i + 1;
1107 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1108 bnxt_hwrm_ring_free(bp, ring,
1109 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1110 ring->fw_ring_id = INVALID_HW_RING_ID;
1111 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1112 memset(rxr->rx_desc_ring, 0,
1113 rxr->rx_ring_struct->ring_size *
1114 sizeof(*rxr->rx_desc_ring));
1115 memset(rxr->rx_buf_ring, 0,
1116 rxr->rx_ring_struct->ring_size *
1117 sizeof(*rxr->rx_buf_ring));
1120 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1121 bnxt_free_cp_ring(bp, cpr, idx);
1124 /* Default completion ring */
1126 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1128 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1129 bnxt_free_cp_ring(bp, cpr, 0);
1135 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1140 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1141 unsigned int idx = i + 1;
1143 if (bp->grp_info[idx].cp_fw_ring_id == INVALID_HW_RING_ID ||
1144 bp->grp_info[idx].rx_fw_ring_id == INVALID_HW_RING_ID)
1147 rc = bnxt_hwrm_ring_grp_alloc(bp, idx);
1155 void bnxt_free_hwrm_resources(struct bnxt *bp)
1157 /* Release memzone */
1158 rte_free(bp->hwrm_cmd_resp_addr);
1159 bp->hwrm_cmd_resp_addr = NULL;
1160 bp->hwrm_cmd_resp_dma_addr = 0;
1163 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1165 struct rte_pci_device *pdev = bp->pdev;
1166 char type[RTE_MEMZONE_NAMESIZE];
1168 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1169 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1170 bp->max_req_len = HWRM_MAX_REQ_LEN;
1171 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1172 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1173 if (bp->hwrm_cmd_resp_addr == NULL)
1175 bp->hwrm_cmd_resp_dma_addr =
1176 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
1177 rte_spinlock_init(&bp->hwrm_lock);
1182 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1184 struct bnxt_filter_info *filter;
1187 STAILQ_FOREACH(filter, &vnic->filter, next) {
1188 rc = bnxt_hwrm_clear_filter(bp, filter);
1195 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1197 struct bnxt_filter_info *filter;
1200 STAILQ_FOREACH(filter, &vnic->filter, next) {
1201 rc = bnxt_hwrm_set_filter(bp, vnic, filter);
1208 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1210 struct bnxt_vnic_info *vnic;
1213 if (bp->vnic_info == NULL)
1216 vnic = &bp->vnic_info[0];
1217 bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1219 /* VNIC resources */
1220 for (i = 0; i < bp->nr_vnics; i++) {
1221 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1223 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1225 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1226 bnxt_hwrm_vnic_free(bp, vnic);
1228 /* Ring resources */
1229 bnxt_free_all_hwrm_rings(bp);
1230 bnxt_free_all_hwrm_ring_grps(bp);
1231 bnxt_free_all_hwrm_stat_ctxs(bp);
1234 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1236 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1238 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1239 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1241 switch (conf_link_speed) {
1242 case ETH_LINK_SPEED_10M_HD:
1243 case ETH_LINK_SPEED_100M_HD:
1244 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1246 return hw_link_duplex;
1249 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1251 uint16_t eth_link_speed = 0;
1253 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1254 return ETH_LINK_SPEED_AUTONEG;
1256 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1257 case ETH_LINK_SPEED_100M:
1258 case ETH_LINK_SPEED_100M_HD:
1260 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB;
1262 case ETH_LINK_SPEED_1G:
1264 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1266 case ETH_LINK_SPEED_2_5G:
1268 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1270 case ETH_LINK_SPEED_10G:
1272 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1274 case ETH_LINK_SPEED_20G:
1276 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1278 case ETH_LINK_SPEED_25G:
1280 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1282 case ETH_LINK_SPEED_40G:
1284 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1286 case ETH_LINK_SPEED_50G:
1288 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1292 "Unsupported link speed %d; default to AUTO\n",
1296 return eth_link_speed;
1299 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1300 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1301 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1302 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1304 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1308 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1311 if (link_speed & ETH_LINK_SPEED_FIXED) {
1312 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1314 if (one_speed & (one_speed - 1)) {
1316 "Invalid advertised speeds (%u) for port %u\n",
1317 link_speed, port_id);
1320 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1322 "Unsupported advertised speed (%u) for port %u\n",
1323 link_speed, port_id);
1327 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1329 "Unsupported advertised speeds (%u) for port %u\n",
1330 link_speed, port_id);
1337 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
1341 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1342 link_speed = BNXT_SUPPORTED_SPEEDS;
1344 if (link_speed & ETH_LINK_SPEED_100M)
1345 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1346 if (link_speed & ETH_LINK_SPEED_100M_HD)
1347 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1348 if (link_speed & ETH_LINK_SPEED_1G)
1349 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1350 if (link_speed & ETH_LINK_SPEED_2_5G)
1351 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1352 if (link_speed & ETH_LINK_SPEED_10G)
1353 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1354 if (link_speed & ETH_LINK_SPEED_20G)
1355 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1356 if (link_speed & ETH_LINK_SPEED_25G)
1357 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1358 if (link_speed & ETH_LINK_SPEED_40G)
1359 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1360 if (link_speed & ETH_LINK_SPEED_50G)
1361 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1365 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
1367 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
1369 switch (hw_link_speed) {
1370 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
1371 eth_link_speed = ETH_SPEED_NUM_100M;
1373 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
1374 eth_link_speed = ETH_SPEED_NUM_1G;
1376 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
1377 eth_link_speed = ETH_SPEED_NUM_2_5G;
1379 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
1380 eth_link_speed = ETH_SPEED_NUM_10G;
1382 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
1383 eth_link_speed = ETH_SPEED_NUM_20G;
1385 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
1386 eth_link_speed = ETH_SPEED_NUM_25G;
1388 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
1389 eth_link_speed = ETH_SPEED_NUM_40G;
1391 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
1392 eth_link_speed = ETH_SPEED_NUM_50G;
1394 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
1396 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
1400 return eth_link_speed;
1403 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
1405 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1407 switch (hw_link_duplex) {
1408 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
1409 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
1410 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1412 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
1413 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
1416 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
1420 return eth_link_duplex;
1423 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
1426 struct bnxt_link_info *link_info = &bp->link_info;
1428 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
1431 "Get link config failed with rc %d\n", rc);
1434 if (link_info->link_up)
1436 bnxt_parse_hw_link_speed(link_info->link_speed);
1438 link->link_speed = ETH_LINK_SPEED_10M;
1439 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
1440 link->link_status = link_info->link_up;
1441 link->link_autoneg = link_info->auto_mode ==
1442 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
1443 ETH_LINK_SPEED_FIXED : ETH_LINK_SPEED_AUTONEG;
1448 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1451 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1452 struct bnxt_link_info link_req;
1455 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1456 bp->eth_dev->data->port_id);
1460 memset(&link_req, 0, sizeof(link_req));
1461 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1462 link_req.link_up = link_up;
1464 link_req.phy_flags =
1465 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1466 link_req.auto_mode =
1467 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW;
1468 link_req.auto_link_speed_mask =
1469 bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
1470 link_req.auto_link_speed =
1471 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB;
1473 link_req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1474 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE |
1475 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1476 link_req.link_speed = speed;
1478 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1479 link_req.auto_pause = bp->link_info.auto_pause;
1480 link_req.force_pause = bp->link_info.force_pause;
1482 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1485 "Set link config failed with rc %d\n", rc);