1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(int) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages > 1) {
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
103 timeout = bp->hwrm_cmd_timeout;
105 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
106 msg_len > bp->max_req_len) {
107 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
109 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
110 memcpy(short_cmd_req, req, msg_len);
112 short_input.req_type = rte_cpu_to_le_16(req->req_type);
113 short_input.signature = rte_cpu_to_le_16(
114 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
115 short_input.size = rte_cpu_to_le_16(msg_len);
116 short_input.req_addr =
117 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
119 data = (uint32_t *)&short_input;
120 msg_len = sizeof(short_input);
122 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
125 /* Write request msg to hwrm channel */
126 for (i = 0; i < msg_len; i += 4) {
127 bar = (uint8_t *)bp->bar0 + bar_offset + i;
128 rte_write32(*data, bar);
132 /* Zero the rest of the request space */
133 for (; i < max_req_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + bar_offset + i;
138 /* Ring channel doorbell */
139 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
142 * Make sure the channel doorbell ring command complete before
143 * reading the response to avoid getting stale or invalid
148 /* Poll for the valid bit */
149 for (i = 0; i < timeout; i++) {
150 /* Sanity check on the resp->resp_len */
152 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
153 /* Last byte of resp contains the valid key */
154 valid = (uint8_t *)resp + resp->resp_len - 1;
155 if (*valid == HWRM_RESP_VALID_KEY)
162 /* Suppress VER_GET timeout messages during reset recovery */
163 if (bp->flags & BNXT_FLAG_FW_RESET &&
164 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
168 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
169 req->req_type, req->seq_id);
176 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
177 * spinlock, and does initial processing.
179 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
180 * releases the spinlock only if it returns. If the regular int return codes
181 * are not used by the function, HWRM_CHECK_RESULT() should not be used
182 * directly, rather it should be copied and modified to suit the function.
184 * HWRM_UNLOCK() must be called after all response processing is completed.
186 #define HWRM_PREP(req, type, kong) do { \
187 rte_spinlock_lock(&bp->hwrm_lock); \
188 if (bp->hwrm_cmd_resp_addr == NULL) { \
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 (req)->req_type = rte_cpu_to_le_16(type); \
194 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
195 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
197 (req)->target_id = rte_cpu_to_le_16(0xffff); \
198 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
219 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
221 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
223 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
225 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
231 if (resp->error_code) { \
232 rc = rte_le_to_cpu_16(resp->error_code); \
233 if (resp->resp_len >= 16) { \
234 struct hwrm_err_output *tmp_hwrm_err_op = \
237 "error %d:%d:%08x:%04x\n", \
238 rc, tmp_hwrm_err_op->cmd_err, \
240 tmp_hwrm_err_op->opaque_0), \
242 tmp_hwrm_err_op->opaque_1)); \
244 PMD_DRV_LOG(ERR, "error %d\n", rc); \
246 rte_spinlock_unlock(&bp->hwrm_lock); \
247 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
249 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
251 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
253 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
255 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
263 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
274 bool mailbox = BNXT_USE_CHIMP_MB;
275 struct input *req = msg;
276 struct output *resp = bp->hwrm_cmd_resp_addr;
279 mailbox = BNXT_USE_KONG(bp);
281 HWRM_PREP(req, msg_type, mailbox);
283 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
288 memcpy(resp_msg, resp, resp_len);
295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
299 uint32_t *tf_response_code,
303 uint32_t response_len)
306 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
307 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
308 bool mailbox = BNXT_USE_CHIMP_MB;
310 if (msg_len > sizeof(req.tf_req))
314 mailbox = BNXT_USE_KONG(bp);
316 HWRM_PREP(&req, HWRM_TF, mailbox);
317 /* Build request using the user supplied request payload.
318 * TLV request size is checked at build time against HWRM
319 * request max size, thus no checking required.
321 req.tf_type = tf_type;
322 req.tf_subtype = tf_subtype;
323 memcpy(req.tf_req, msg, msg_len);
325 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
328 /* Copy the resp to user provided response buffer */
329 if (response != NULL)
330 /* Post process response data. We need to copy only
331 * the 'payload' as the HWRM data structure really is
332 * HWRM header + msg header + payload and the TFLIB
333 * only provided a payload place holder.
335 if (response_len != 0) {
341 /* Extract the internal tflib response code */
342 *tf_response_code = resp->tf_resp_code;
348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
351 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
352 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
354 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
355 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
358 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
367 struct bnxt_vnic_info *vnic,
369 struct bnxt_vlan_table_entry *vlan_table)
372 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
376 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
379 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
380 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
382 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
383 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
384 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
385 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
387 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
388 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
390 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
391 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
392 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
393 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
394 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
395 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
398 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
399 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
400 req.vlan_tag_tbl_addr =
401 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
402 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
404 req.mask = rte_cpu_to_le_32(mask);
406 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
416 struct bnxt_vlan_antispoof_table_entry *vlan_table)
419 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
420 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
421 bp->hwrm_cmd_resp_addr;
424 * Older HWRM versions did not support this command, and the set_rx_mask
425 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
426 * removed from set_rx_mask call, and this command was added.
428 * This command is also present from 1.7.8.11 and higher,
431 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
432 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
433 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
438 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
439 req.fid = rte_cpu_to_le_16(fid);
441 req.vlan_tag_mask_tbl_addr =
442 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
443 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
445 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
454 struct bnxt_filter_info *filter)
457 struct bnxt_filter_info *l2_filter = filter;
458 struct bnxt_vnic_info *vnic = NULL;
459 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
460 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
462 if (filter->fw_l2_filter_id == UINT64_MAX)
465 if (filter->matching_l2_fltr_ptr)
466 l2_filter = filter->matching_l2_fltr_ptr;
468 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
469 filter, l2_filter, l2_filter->l2_ref_cnt);
471 if (l2_filter->l2_ref_cnt == 0)
474 if (l2_filter->l2_ref_cnt > 0)
475 l2_filter->l2_ref_cnt--;
477 if (l2_filter->l2_ref_cnt > 0)
480 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
482 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
489 filter->fw_l2_filter_id = UINT64_MAX;
490 if (l2_filter->l2_ref_cnt == 0) {
491 vnic = l2_filter->vnic;
493 STAILQ_REMOVE(&vnic->filter, l2_filter,
494 bnxt_filter_info, next);
495 bnxt_free_filter(bp, l2_filter);
502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
504 struct bnxt_filter_info *filter)
507 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
508 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
509 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
510 const struct rte_eth_vmdq_rx_conf *conf =
511 &dev_conf->rx_adv_conf.vmdq_rx_conf;
512 uint32_t enables = 0;
513 uint16_t j = dst_id - 1;
515 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
516 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
517 conf->pool_map[j].pools & (1UL << j)) {
519 "Add vlan %u to vmdq pool %u\n",
520 conf->pool_map[j].vlan_id, j);
522 filter->l2_ivlan = conf->pool_map[j].vlan_id;
524 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
525 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
528 if (filter->fw_l2_filter_id != UINT64_MAX)
529 bnxt_hwrm_clear_l2_filter(bp, filter);
531 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
533 /* PMD does not support XDP and RoCE */
534 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
535 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
536 req.flags = rte_cpu_to_le_32(filter->flags);
538 enables = filter->enables |
539 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
540 req.dst_id = rte_cpu_to_le_16(dst_id);
543 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
544 memcpy(req.l2_addr, filter->l2_addr,
547 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
548 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
551 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
552 req.l2_ovlan = filter->l2_ovlan;
554 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
555 req.l2_ivlan = filter->l2_ivlan;
557 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
558 req.l2_ovlan_mask = filter->l2_ovlan_mask;
560 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
561 req.l2_ivlan_mask = filter->l2_ivlan_mask;
562 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
563 req.src_id = rte_cpu_to_le_32(filter->src_id);
564 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
565 req.src_type = filter->src_type;
566 if (filter->pri_hint) {
567 req.pri_hint = filter->pri_hint;
568 req.l2_filter_id_hint =
569 rte_cpu_to_le_64(filter->l2_filter_id_hint);
572 req.enables = rte_cpu_to_le_32(enables);
574 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
578 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
579 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
582 filter->l2_ref_cnt++;
587 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
589 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
590 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
597 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
600 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
603 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
604 if (ptp->tx_tstamp_en)
605 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
608 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
609 req.flags = rte_cpu_to_le_32(flags);
610 req.enables = rte_cpu_to_le_32
611 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
612 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
614 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
620 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
623 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
624 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
625 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
630 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
632 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
634 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
638 if (!BNXT_CHIP_THOR(bp) &&
639 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
642 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
643 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
645 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
649 if (!BNXT_CHIP_THOR(bp)) {
650 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
651 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
652 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
653 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
654 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
655 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
656 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
657 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
658 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
659 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
660 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
661 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
662 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
663 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
664 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
665 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
666 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
667 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
676 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
680 for (i = 0; i < bp->pf->max_vfs; i++) {
681 rte_free(bp->pf->vf_info[i].vlan_table);
682 bp->pf->vf_info[i].vlan_table = NULL;
683 rte_free(bp->pf->vf_info[i].vlan_as_table);
684 bp->pf->vf_info[i].vlan_as_table = NULL;
686 rte_free(bp->pf->vf_info);
687 bp->pf->vf_info = NULL;
690 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
693 struct hwrm_func_qcaps_input req = {.req_type = 0 };
694 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
695 uint16_t new_max_vfs;
699 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
701 req.fid = rte_cpu_to_le_16(0xffff);
703 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
707 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
708 flags = rte_le_to_cpu_32(resp->flags);
710 bp->pf->port_id = resp->port_id;
711 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
712 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
713 new_max_vfs = bp->pdev->max_vfs;
714 if (new_max_vfs != bp->pf->max_vfs) {
716 bnxt_hwrm_free_vf_info(bp);
717 bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
718 sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
719 if (bp->pf->vf_info == NULL) {
720 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
723 bp->pf->max_vfs = new_max_vfs;
724 for (i = 0; i < new_max_vfs; i++) {
725 bp->pf->vf_info[i].fid =
726 bp->pf->first_vf_id + i;
727 bp->pf->vf_info[i].vlan_table =
728 rte_zmalloc("VF VLAN table",
731 if (bp->pf->vf_info[i].vlan_table == NULL)
733 "Fail to alloc VLAN table for VF %d\n",
737 bp->pf->vf_info[i].vlan_table);
738 bp->pf->vf_info[i].vlan_as_table =
739 rte_zmalloc("VF VLAN AS table",
742 if (bp->pf->vf_info[i].vlan_as_table == NULL)
744 "Alloc VLAN AS table for VF %d fail\n",
748 bp->pf->vf_info[i].vlan_as_table);
749 STAILQ_INIT(&bp->pf->vf_info[i].filter);
754 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
755 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
756 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
757 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
759 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
761 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
762 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
763 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
764 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
765 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
766 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
767 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
768 if (!BNXT_CHIP_THOR(bp) && !bp->pdev->max_vfs)
769 bp->max_l2_ctx += bp->max_rx_em_flows;
770 /* TODO: For now, do not support VMDq/RFS on VFs. */
775 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
779 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
780 bp->max_l2_ctx, bp->max_vnics);
781 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
783 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
784 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
785 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
786 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
788 bnxt_hwrm_ptp_qcfg(bp);
792 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
793 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
795 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
796 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
797 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
800 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
801 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
803 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
804 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
806 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
807 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
814 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
818 rc = __bnxt_hwrm_func_qcaps(bp);
819 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
820 rc = bnxt_alloc_ctx_mem(bp);
825 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
826 * But the error can be ignored. Return success.
828 rc = bnxt_hwrm_func_resc_qcaps(bp);
830 bp->flags |= BNXT_FLAG_NEW_RM;
836 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
837 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
841 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
842 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
844 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
846 req.target_id = rte_cpu_to_le_16(0xffff);
848 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
852 flags = rte_le_to_cpu_32(resp->flags);
854 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
855 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
856 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
859 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
860 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
862 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
869 int bnxt_hwrm_func_reset(struct bnxt *bp)
872 struct hwrm_func_reset_input req = {.req_type = 0 };
873 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
875 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
877 req.enables = rte_cpu_to_le_32(0);
879 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
887 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
891 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
892 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
894 if (bp->flags & BNXT_FLAG_REGISTERED)
897 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
898 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
899 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
900 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
902 /* PFs and trusted VFs should indicate the support of the
903 * Master capability on non Stingray platform
905 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
906 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
908 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
909 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
910 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
911 req.ver_maj = RTE_VER_YEAR;
912 req.ver_min = RTE_VER_MONTH;
913 req.ver_upd = RTE_VER_MINOR;
916 req.enables |= rte_cpu_to_le_32(
917 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
918 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
919 RTE_MIN(sizeof(req.vf_req_fwd),
920 sizeof(bp->pf->vf_req_fwd)));
923 req.flags = rte_cpu_to_le_32(flags);
925 req.async_event_fwd[0] |=
926 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
927 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
928 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
929 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
930 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
931 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
932 req.async_event_fwd[0] |=
933 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
934 req.async_event_fwd[1] |=
935 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
936 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
938 req.async_event_fwd[1] |=
939 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
941 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
942 req.async_event_fwd[1] |=
943 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
945 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
949 flags = rte_le_to_cpu_32(resp->flags);
950 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
951 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
955 bp->flags |= BNXT_FLAG_REGISTERED;
960 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
962 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
965 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
968 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
973 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
974 struct hwrm_func_vf_cfg_input req = {0};
976 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
978 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
979 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
980 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
981 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
982 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
984 if (BNXT_HAS_RING_GRPS(bp)) {
985 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
986 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
989 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
990 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
991 AGG_RING_MULTIPLIER);
992 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
993 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
995 BNXT_NUM_ASYNC_CPR(bp));
996 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
997 if (bp->vf_resv_strategy ==
998 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
999 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1000 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1001 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1002 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1003 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1004 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1005 } else if (bp->vf_resv_strategy ==
1006 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1007 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1008 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1012 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1013 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1014 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1015 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1016 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1017 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1019 if (test && BNXT_HAS_RING_GRPS(bp))
1020 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1022 req.flags = rte_cpu_to_le_32(flags);
1023 req.enables |= rte_cpu_to_le_32(enables);
1025 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1028 HWRM_CHECK_RESULT_SILENT();
1030 HWRM_CHECK_RESULT();
1036 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1039 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1040 struct hwrm_func_resource_qcaps_input req = {0};
1042 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1043 req.fid = rte_cpu_to_le_16(0xffff);
1045 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1047 HWRM_CHECK_RESULT_SILENT();
1049 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1050 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1051 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1052 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1053 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1054 /* func_resource_qcaps does not return max_rx_em_flows.
1055 * So use the value provided by func_qcaps.
1057 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1058 if (!BNXT_CHIP_THOR(bp) && !bp->pdev->max_vfs)
1059 bp->max_l2_ctx += bp->max_rx_em_flows;
1060 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1061 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1062 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1063 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1064 if (bp->vf_resv_strategy >
1065 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1066 bp->vf_resv_strategy =
1067 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1073 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1076 struct hwrm_ver_get_input req = {.req_type = 0 };
1077 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1078 uint32_t fw_version;
1079 uint16_t max_resp_len;
1080 char type[RTE_MEMZONE_NAMESIZE];
1081 uint32_t dev_caps_cfg;
1083 bp->max_req_len = HWRM_MAX_REQ_LEN;
1084 bp->hwrm_cmd_timeout = timeout;
1085 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1087 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1088 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1089 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1091 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1093 if (bp->flags & BNXT_FLAG_FW_RESET)
1094 HWRM_CHECK_RESULT_SILENT();
1096 HWRM_CHECK_RESULT();
1098 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1099 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1100 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1101 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1102 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1103 (resp->hwrm_fw_min_8b << 16) |
1104 (resp->hwrm_fw_bld_8b << 8) |
1105 resp->hwrm_fw_rsvd_8b;
1106 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1107 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1109 fw_version = resp->hwrm_intf_maj_8b << 16;
1110 fw_version |= resp->hwrm_intf_min_8b << 8;
1111 fw_version |= resp->hwrm_intf_upd_8b;
1112 bp->hwrm_spec_code = fw_version;
1114 /* def_req_timeout value is in milliseconds */
1115 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1116 /* convert timeout to usec */
1117 bp->hwrm_cmd_timeout *= 1000;
1118 if (!bp->hwrm_cmd_timeout)
1119 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1121 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1122 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1127 if (bp->max_req_len > resp->max_req_win_len) {
1128 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1131 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1132 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1133 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1134 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1136 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1137 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1139 if (bp->max_resp_len != max_resp_len) {
1140 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1141 bp->pdev->addr.domain, bp->pdev->addr.bus,
1142 bp->pdev->addr.devid, bp->pdev->addr.function);
1144 rte_free(bp->hwrm_cmd_resp_addr);
1146 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1147 if (bp->hwrm_cmd_resp_addr == NULL) {
1151 bp->hwrm_cmd_resp_dma_addr =
1152 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1153 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1155 "Unable to map response buffer to physical memory.\n");
1159 bp->max_resp_len = max_resp_len;
1163 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1165 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1166 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1167 bp->flags |= BNXT_FLAG_SHORT_CMD;
1170 if (((dev_caps_cfg &
1171 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1173 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1174 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1175 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1176 bp->pdev->addr.domain, bp->pdev->addr.bus,
1177 bp->pdev->addr.devid, bp->pdev->addr.function);
1179 rte_free(bp->hwrm_short_cmd_req_addr);
1181 bp->hwrm_short_cmd_req_addr =
1182 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1183 if (bp->hwrm_short_cmd_req_addr == NULL) {
1187 bp->hwrm_short_cmd_req_dma_addr =
1188 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1189 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1190 rte_free(bp->hwrm_short_cmd_req_addr);
1192 "Unable to map buffer to physical memory.\n");
1198 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1199 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1200 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1203 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1204 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1206 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1207 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1208 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1212 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1213 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1214 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1223 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1226 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1227 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1229 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1232 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1235 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1237 HWRM_CHECK_RESULT();
1243 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1246 struct hwrm_port_phy_cfg_input req = {0};
1247 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1248 uint32_t enables = 0;
1250 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1252 if (conf->link_up) {
1253 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1254 if (bp->link_info->auto_mode && conf->link_speed) {
1255 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1256 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1259 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1261 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1262 * any auto mode, even "none".
1264 if (!conf->link_speed) {
1265 /* No speeds specified. Enable AutoNeg - all speeds */
1266 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1268 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1270 if (bp->link_info->link_signal_mode) {
1272 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1273 req.force_pam4_link_speed =
1274 rte_cpu_to_le_16(conf->link_speed);
1276 req.force_link_speed =
1277 rte_cpu_to_le_16(conf->link_speed);
1279 /* AutoNeg - Advertise speeds specified. */
1280 if (conf->auto_link_speed_mask &&
1281 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1283 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1284 req.auto_link_speed_mask =
1285 conf->auto_link_speed_mask;
1286 if (conf->auto_pam4_link_speeds) {
1288 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1289 req.auto_link_pam4_speed_mask =
1290 conf->auto_pam4_link_speeds;
1293 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1296 if (conf->auto_link_speed &&
1297 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1299 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1301 req.auto_duplex = conf->duplex;
1302 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1303 req.auto_pause = conf->auto_pause;
1304 req.force_pause = conf->force_pause;
1305 /* Set force_pause if there is no auto or if there is a force */
1306 if (req.auto_pause && !req.force_pause)
1307 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1309 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1311 req.enables = rte_cpu_to_le_32(enables);
1314 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1315 PMD_DRV_LOG(INFO, "Force Link Down\n");
1318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1320 HWRM_CHECK_RESULT();
1326 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1327 struct bnxt_link_info *link_info)
1330 struct hwrm_port_phy_qcfg_input req = {0};
1331 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1333 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1337 HWRM_CHECK_RESULT();
1339 link_info->phy_link_status = resp->link;
1340 link_info->link_up =
1341 (link_info->phy_link_status ==
1342 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1343 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1344 link_info->duplex = resp->duplex_cfg;
1345 link_info->pause = resp->pause;
1346 link_info->auto_pause = resp->auto_pause;
1347 link_info->force_pause = resp->force_pause;
1348 link_info->auto_mode = resp->auto_mode;
1349 link_info->phy_type = resp->phy_type;
1350 link_info->media_type = resp->media_type;
1352 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1353 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1354 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1355 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1356 link_info->phy_ver[0] = resp->phy_maj;
1357 link_info->phy_ver[1] = resp->phy_min;
1358 link_info->phy_ver[2] = resp->phy_bld;
1359 link_info->link_signal_mode =
1360 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1361 link_info->force_pam4_link_speed =
1362 rte_le_to_cpu_16(resp->force_pam4_link_speed);
1363 link_info->support_pam4_speeds =
1364 rte_le_to_cpu_16(resp->support_pam4_speeds);
1365 link_info->auto_pam4_link_speeds =
1366 rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1369 PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1370 link_info->link_speed, link_info->auto_mode,
1371 link_info->auto_link_speed, link_info->auto_link_speed_mask,
1372 link_info->support_speeds, link_info->force_link_speed);
1376 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1379 struct hwrm_port_phy_qcaps_input req = {0};
1380 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1381 struct bnxt_link_info *link_info = bp->link_info;
1383 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1386 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1388 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1390 HWRM_CHECK_RESULT();
1392 bp->port_cnt = resp->port_cnt;
1393 if (resp->supported_speeds_auto_mode)
1394 link_info->support_auto_speeds =
1395 rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1396 if (resp->supported_pam4_speeds_auto_mode)
1397 link_info->support_pam4_auto_speeds =
1398 rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1405 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1409 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1410 if (bp->tx_cos_queue[i].profile ==
1411 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1412 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1419 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1423 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1424 if (bp->tx_cos_queue[i].profile !=
1425 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1426 bp->tx_cos_queue[i].id !=
1427 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1428 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1434 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1437 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1438 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1439 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1443 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1445 req.flags = rte_cpu_to_le_32(dir);
1446 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1447 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1448 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1450 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1451 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1453 HWRM_CHECK_RESULT();
1455 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1456 GET_TX_QUEUE_INFO(0);
1457 GET_TX_QUEUE_INFO(1);
1458 GET_TX_QUEUE_INFO(2);
1459 GET_TX_QUEUE_INFO(3);
1460 GET_TX_QUEUE_INFO(4);
1461 GET_TX_QUEUE_INFO(5);
1462 GET_TX_QUEUE_INFO(6);
1463 GET_TX_QUEUE_INFO(7);
1465 GET_RX_QUEUE_INFO(0);
1466 GET_RX_QUEUE_INFO(1);
1467 GET_RX_QUEUE_INFO(2);
1468 GET_RX_QUEUE_INFO(3);
1469 GET_RX_QUEUE_INFO(4);
1470 GET_RX_QUEUE_INFO(5);
1471 GET_RX_QUEUE_INFO(6);
1472 GET_RX_QUEUE_INFO(7);
1477 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1480 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1481 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1485 /* iterate and find the COSq profile to use for Tx */
1486 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1487 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1488 if (bp->tx_cos_queue[i].id != 0xff)
1489 bp->tx_cosq_id[j++] =
1490 bp->tx_cos_queue[i].id;
1493 /* When CoS classification is disabled, for normal NIC
1494 * operations, ideally we should look to use LOSSY.
1495 * If not found, fallback to the first valid profile
1497 if (!bnxt_find_lossy_profile(bp))
1498 bnxt_find_first_valid_profile(bp);
1503 bp->max_tc = resp->max_configurable_queues;
1504 bp->max_lltc = resp->max_configurable_lossless_queues;
1505 if (bp->max_tc > BNXT_MAX_QUEUE)
1506 bp->max_tc = BNXT_MAX_QUEUE;
1507 bp->max_q = bp->max_tc;
1509 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1510 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1518 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1519 struct bnxt_ring *ring,
1520 uint32_t ring_type, uint32_t map_index,
1521 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1522 uint16_t tx_cosq_id)
1525 uint32_t enables = 0;
1526 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1527 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1528 struct rte_mempool *mb_pool;
1529 uint16_t rx_buf_size;
1531 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1533 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1534 req.fbo = rte_cpu_to_le_32(0);
1535 /* Association of ring index with doorbell index */
1536 req.logical_id = rte_cpu_to_le_16(map_index);
1537 req.length = rte_cpu_to_le_32(ring->ring_size);
1539 switch (ring_type) {
1540 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1541 req.ring_type = ring_type;
1542 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1543 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1544 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1545 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1547 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1549 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1550 req.ring_type = ring_type;
1551 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1552 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1553 if (BNXT_CHIP_THOR(bp)) {
1554 mb_pool = bp->rx_queues[0]->mb_pool;
1555 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1556 RTE_PKTMBUF_HEADROOM;
1557 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1558 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1560 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1562 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1564 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1566 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1567 req.ring_type = ring_type;
1568 if (BNXT_HAS_NQ(bp)) {
1569 /* Association of cp ring with nq */
1570 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1572 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1574 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1576 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1577 req.ring_type = ring_type;
1578 req.page_size = BNXT_PAGE_SHFT;
1579 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1581 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1582 req.ring_type = ring_type;
1583 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1585 mb_pool = bp->rx_queues[0]->mb_pool;
1586 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1587 RTE_PKTMBUF_HEADROOM;
1588 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1589 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1591 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1592 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1593 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1594 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1597 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1602 req.enables = rte_cpu_to_le_32(enables);
1604 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1606 if (rc || resp->error_code) {
1607 if (rc == 0 && resp->error_code)
1608 rc = rte_le_to_cpu_16(resp->error_code);
1609 switch (ring_type) {
1610 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1612 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1615 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1617 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1620 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1622 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1626 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1628 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1631 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1633 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1637 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1643 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1648 int bnxt_hwrm_ring_free(struct bnxt *bp,
1649 struct bnxt_ring *ring, uint32_t ring_type)
1652 struct hwrm_ring_free_input req = {.req_type = 0 };
1653 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1655 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1657 req.ring_type = ring_type;
1658 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1660 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1662 if (rc || resp->error_code) {
1663 if (rc == 0 && resp->error_code)
1664 rc = rte_le_to_cpu_16(resp->error_code);
1667 switch (ring_type) {
1668 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1669 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1672 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1673 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1676 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1677 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1680 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1682 "hwrm_ring_free nq failed. rc:%d\n", rc);
1684 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1686 "hwrm_ring_free agg failed. rc:%d\n", rc);
1689 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1697 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1700 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1701 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1703 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1705 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1706 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1707 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1708 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1710 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1712 HWRM_CHECK_RESULT();
1714 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1721 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1724 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1725 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1727 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1729 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1731 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1733 HWRM_CHECK_RESULT();
1736 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1740 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1743 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1744 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1746 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1749 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1751 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1753 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1755 HWRM_CHECK_RESULT();
1761 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1762 unsigned int idx __rte_unused)
1765 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1766 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1768 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1770 req.update_period_ms = rte_cpu_to_le_32(0);
1772 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1774 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1776 HWRM_CHECK_RESULT();
1778 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1785 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1786 unsigned int idx __rte_unused)
1789 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1790 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1792 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1794 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1796 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1798 HWRM_CHECK_RESULT();
1804 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1807 struct hwrm_vnic_alloc_input req = { 0 };
1808 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1810 if (!BNXT_HAS_RING_GRPS(bp))
1811 goto skip_ring_grps;
1813 /* map ring groups to this vnic */
1814 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1815 vnic->start_grp_id, vnic->end_grp_id);
1816 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1817 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1819 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1820 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1821 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1822 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1825 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1826 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1828 if (vnic->func_default)
1830 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1831 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1833 HWRM_CHECK_RESULT();
1835 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1837 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1841 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1842 struct bnxt_vnic_info *vnic,
1843 struct bnxt_plcmodes_cfg *pmode)
1846 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1847 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1849 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1851 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1853 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1855 HWRM_CHECK_RESULT();
1857 pmode->flags = rte_le_to_cpu_32(resp->flags);
1858 /* dflt_vnic bit doesn't exist in the _cfg command */
1859 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1860 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1861 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1862 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1869 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1870 struct bnxt_vnic_info *vnic,
1871 struct bnxt_plcmodes_cfg *pmode)
1874 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1875 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1877 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1878 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1882 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1884 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1885 req.flags = rte_cpu_to_le_32(pmode->flags);
1886 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1887 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1888 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1889 req.enables = rte_cpu_to_le_32(
1890 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1891 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1892 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1895 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1897 HWRM_CHECK_RESULT();
1903 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1906 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1907 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1908 struct bnxt_plcmodes_cfg pmodes = { 0 };
1909 uint32_t ctx_enable_flag = 0;
1910 uint32_t enables = 0;
1912 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1913 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1917 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1921 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1923 if (BNXT_CHIP_THOR(bp)) {
1924 int dflt_rxq = vnic->start_grp_id;
1925 struct bnxt_rx_ring_info *rxr;
1926 struct bnxt_cp_ring_info *cpr;
1927 struct bnxt_rx_queue *rxq;
1931 * The first active receive ring is used as the VNIC
1932 * default receive ring. If there are no active receive
1933 * rings (all corresponding receive queues are stopped),
1934 * the first receive ring is used.
1936 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1937 rxq = bp->eth_dev->data->rx_queues[i];
1938 if (rxq->rx_started) {
1944 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1948 req.default_rx_ring_id =
1949 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1950 req.default_cmpl_ring_id =
1951 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1952 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1953 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1957 /* Only RSS support for now TBD: COS & LB */
1958 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1959 if (vnic->lb_rule != 0xffff)
1960 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1961 if (vnic->cos_rule != 0xffff)
1962 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1963 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1964 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1965 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1967 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1968 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1969 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1972 enables |= ctx_enable_flag;
1973 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1974 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1975 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1976 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1979 req.enables = rte_cpu_to_le_32(enables);
1980 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1981 req.mru = rte_cpu_to_le_16(vnic->mru);
1982 /* Configure default VNIC only once. */
1983 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1985 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1986 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1988 if (vnic->vlan_strip)
1990 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1993 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1994 if (vnic->roce_dual)
1995 req.flags |= rte_cpu_to_le_32(
1996 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1997 if (vnic->roce_only)
1998 req.flags |= rte_cpu_to_le_32(
1999 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
2000 if (vnic->rss_dflt_cr)
2001 req.flags |= rte_cpu_to_le_32(
2002 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2004 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2006 HWRM_CHECK_RESULT();
2009 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2014 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2018 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2019 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2021 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2022 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2025 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2028 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2029 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2030 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2032 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2034 HWRM_CHECK_RESULT();
2036 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2037 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2038 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2039 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2040 vnic->mru = rte_le_to_cpu_16(resp->mru);
2041 vnic->func_default = rte_le_to_cpu_32(
2042 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2043 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2044 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2045 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2046 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2047 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
2048 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
2049 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
2050 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
2051 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2052 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2059 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2060 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2064 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2065 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2066 bp->hwrm_cmd_resp_addr;
2068 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2070 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2071 HWRM_CHECK_RESULT();
2073 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2074 if (!BNXT_HAS_RING_GRPS(bp))
2075 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2076 else if (ctx_idx == 0)
2077 vnic->rss_rule = ctx_id;
2085 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2086 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2089 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2090 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2091 bp->hwrm_cmd_resp_addr;
2093 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2094 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2097 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2099 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2101 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2103 HWRM_CHECK_RESULT();
2109 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2113 if (BNXT_CHIP_THOR(bp)) {
2116 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2117 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2119 vnic->fw_grp_ids[j]);
2120 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2122 vnic->num_lb_ctxts = 0;
2124 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2125 vnic->rss_rule = INVALID_HW_RING_ID;
2131 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2134 struct hwrm_vnic_free_input req = {.req_type = 0 };
2135 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2137 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2138 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2142 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2144 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2146 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2148 HWRM_CHECK_RESULT();
2151 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2152 /* Configure default VNIC again if necessary. */
2153 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2154 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2160 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2164 int nr_ctxs = vnic->num_lb_ctxts;
2165 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2166 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2168 for (i = 0; i < nr_ctxs; i++) {
2169 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2171 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2172 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2173 req.hash_mode_flags = vnic->hash_mode;
2175 req.hash_key_tbl_addr =
2176 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2178 req.ring_grp_tbl_addr =
2179 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2180 i * HW_HASH_INDEX_SIZE);
2181 req.ring_table_pair_index = i;
2182 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2184 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2187 HWRM_CHECK_RESULT();
2194 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2195 struct bnxt_vnic_info *vnic)
2198 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2199 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2201 if (!vnic->rss_table)
2204 if (BNXT_CHIP_THOR(bp))
2205 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2207 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2209 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2210 req.hash_mode_flags = vnic->hash_mode;
2212 req.ring_grp_tbl_addr =
2213 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2214 req.hash_key_tbl_addr =
2215 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2216 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2217 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2219 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2221 HWRM_CHECK_RESULT();
2227 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2228 struct bnxt_vnic_info *vnic)
2231 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2232 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2235 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2236 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2240 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2242 req.flags = rte_cpu_to_le_32(
2243 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2245 req.enables = rte_cpu_to_le_32(
2246 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2248 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2249 size -= RTE_PKTMBUF_HEADROOM;
2250 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2252 req.jumbo_thresh = rte_cpu_to_le_16(size);
2253 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2255 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2257 HWRM_CHECK_RESULT();
2263 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2264 struct bnxt_vnic_info *vnic, bool enable)
2267 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2268 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2270 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2272 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2276 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2277 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2281 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2284 req.enables = rte_cpu_to_le_32(
2285 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2286 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2287 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2288 req.flags = rte_cpu_to_le_32(
2289 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2290 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2291 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2292 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2293 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2294 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2295 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2296 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2297 req.min_agg_len = rte_cpu_to_le_32(512);
2299 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2301 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2303 HWRM_CHECK_RESULT();
2309 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2311 struct hwrm_func_cfg_input req = {0};
2312 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2315 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2316 req.enables = rte_cpu_to_le_32(
2317 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2318 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2319 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2321 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2323 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2324 HWRM_CHECK_RESULT();
2327 bp->pf->vf_info[vf].random_mac = false;
2332 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2336 struct hwrm_func_qstats_input req = {.req_type = 0};
2337 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2339 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2341 req.fid = rte_cpu_to_le_16(fid);
2343 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2345 HWRM_CHECK_RESULT();
2348 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2355 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2356 struct rte_eth_stats *stats,
2357 struct hwrm_func_qstats_output *func_qstats)
2360 struct hwrm_func_qstats_input req = {.req_type = 0};
2361 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2363 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2365 req.fid = rte_cpu_to_le_16(fid);
2367 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2369 HWRM_CHECK_RESULT();
2371 memcpy(func_qstats, resp,
2372 sizeof(struct hwrm_func_qstats_output));
2377 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2378 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2379 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2380 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2381 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2382 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2384 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2385 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2386 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2387 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2388 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2389 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2391 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2392 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2393 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2401 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2404 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2405 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2407 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2409 req.fid = rte_cpu_to_le_16(fid);
2411 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2413 HWRM_CHECK_RESULT();
2419 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2424 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2425 struct bnxt_tx_queue *txq;
2426 struct bnxt_rx_queue *rxq;
2427 struct bnxt_cp_ring_info *cpr;
2429 if (i >= bp->rx_cp_nr_rings) {
2430 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2433 rxq = bp->rx_queues[i];
2437 rc = bnxt_hwrm_stat_clear(bp, cpr);
2445 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2449 struct bnxt_cp_ring_info *cpr;
2451 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2453 if (i >= bp->rx_cp_nr_rings) {
2454 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2456 cpr = bp->rx_queues[i]->cp_ring;
2457 if (BNXT_HAS_RING_GRPS(bp))
2458 bp->grp_info[i].fw_stats_ctx = -1;
2460 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2461 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2462 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2470 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2475 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2476 struct bnxt_tx_queue *txq;
2477 struct bnxt_rx_queue *rxq;
2478 struct bnxt_cp_ring_info *cpr;
2480 if (i >= bp->rx_cp_nr_rings) {
2481 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2484 rxq = bp->rx_queues[i];
2488 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2497 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2502 if (!BNXT_HAS_RING_GRPS(bp))
2505 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2507 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2510 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2518 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2520 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2522 bnxt_hwrm_ring_free(bp, cp_ring,
2523 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2524 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2525 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2526 sizeof(*cpr->cp_desc_ring));
2527 cpr->cp_raw_cons = 0;
2531 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2533 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2535 bnxt_hwrm_ring_free(bp, cp_ring,
2536 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2537 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2538 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2539 sizeof(*cpr->cp_desc_ring));
2540 cpr->cp_raw_cons = 0;
2544 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2546 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2547 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2548 struct bnxt_ring *ring = rxr->rx_ring_struct;
2549 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2551 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2552 bnxt_hwrm_ring_free(bp, ring,
2553 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2554 ring->fw_ring_id = INVALID_HW_RING_ID;
2555 if (BNXT_HAS_RING_GRPS(bp))
2556 bp->grp_info[queue_index].rx_fw_ring_id =
2559 ring = rxr->ag_ring_struct;
2560 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2561 bnxt_hwrm_ring_free(bp, ring,
2562 BNXT_CHIP_THOR(bp) ?
2563 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2564 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2565 if (BNXT_HAS_RING_GRPS(bp))
2566 bp->grp_info[queue_index].ag_fw_ring_id =
2569 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2570 bnxt_free_cp_ring(bp, cpr);
2572 if (BNXT_HAS_RING_GRPS(bp))
2573 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2577 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2581 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2582 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2583 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2584 struct bnxt_ring *ring = txr->tx_ring_struct;
2585 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2587 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2588 bnxt_hwrm_ring_free(bp, ring,
2589 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2590 ring->fw_ring_id = INVALID_HW_RING_ID;
2591 memset(txr->tx_desc_ring, 0,
2592 txr->tx_ring_struct->ring_size *
2593 sizeof(*txr->tx_desc_ring));
2594 memset(txr->tx_buf_ring, 0,
2595 txr->tx_ring_struct->ring_size *
2596 sizeof(*txr->tx_buf_ring));
2600 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2601 bnxt_free_cp_ring(bp, cpr);
2602 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2606 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2607 bnxt_free_hwrm_rx_ring(bp, i);
2612 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2617 if (!BNXT_HAS_RING_GRPS(bp))
2620 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2621 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2629 * HWRM utility functions
2632 void bnxt_free_hwrm_resources(struct bnxt *bp)
2634 /* Release memzone */
2635 rte_free(bp->hwrm_cmd_resp_addr);
2636 rte_free(bp->hwrm_short_cmd_req_addr);
2637 bp->hwrm_cmd_resp_addr = NULL;
2638 bp->hwrm_short_cmd_req_addr = NULL;
2639 bp->hwrm_cmd_resp_dma_addr = 0;
2640 bp->hwrm_short_cmd_req_dma_addr = 0;
2643 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2645 struct rte_pci_device *pdev = bp->pdev;
2646 char type[RTE_MEMZONE_NAMESIZE];
2648 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2649 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2650 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2651 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2652 if (bp->hwrm_cmd_resp_addr == NULL)
2654 bp->hwrm_cmd_resp_dma_addr =
2655 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2656 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2658 "unable to map response address to physical memory\n");
2661 rte_spinlock_init(&bp->hwrm_lock);
2667 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2671 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2672 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2675 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2676 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2681 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2686 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2688 struct bnxt_filter_info *filter;
2691 STAILQ_FOREACH(filter, &vnic->filter, next) {
2692 rc = bnxt_clear_one_vnic_filter(bp, filter);
2693 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2694 bnxt_free_filter(bp, filter);
2700 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2702 struct bnxt_filter_info *filter;
2703 struct rte_flow *flow;
2706 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2707 flow = STAILQ_FIRST(&vnic->flow_list);
2708 filter = flow->filter;
2709 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2710 rc = bnxt_clear_one_vnic_filter(bp, filter);
2712 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2718 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2720 struct bnxt_filter_info *filter;
2723 STAILQ_FOREACH(filter, &vnic->filter, next) {
2724 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2725 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2727 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2728 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2731 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2740 bnxt_free_tunnel_ports(struct bnxt *bp)
2742 if (bp->vxlan_port_cnt)
2743 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2744 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2746 if (bp->geneve_port_cnt)
2747 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2748 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2751 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2755 if (bp->vnic_info == NULL)
2759 * Cleanup VNICs in reverse order, to make sure the L2 filter
2760 * from vnic0 is last to be cleaned up.
2762 for (i = bp->max_vnics - 1; i >= 0; i--) {
2763 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2765 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2768 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2770 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2772 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2774 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2776 bnxt_hwrm_vnic_free(bp, vnic);
2778 rte_free(vnic->fw_grp_ids);
2780 /* Ring resources */
2781 bnxt_free_all_hwrm_rings(bp);
2782 bnxt_free_all_hwrm_ring_grps(bp);
2783 bnxt_free_all_hwrm_stat_ctxs(bp);
2784 bnxt_free_tunnel_ports(bp);
2787 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2789 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2791 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2792 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2794 switch (conf_link_speed) {
2795 case ETH_LINK_SPEED_10M_HD:
2796 case ETH_LINK_SPEED_100M_HD:
2798 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2800 return hw_link_duplex;
2803 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2808 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2811 uint16_t eth_link_speed = 0;
2813 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2814 return ETH_LINK_SPEED_AUTONEG;
2816 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2817 case ETH_LINK_SPEED_100M:
2818 case ETH_LINK_SPEED_100M_HD:
2821 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2823 case ETH_LINK_SPEED_1G:
2825 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2827 case ETH_LINK_SPEED_2_5G:
2829 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2831 case ETH_LINK_SPEED_10G:
2833 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2835 case ETH_LINK_SPEED_20G:
2837 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2839 case ETH_LINK_SPEED_25G:
2841 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2843 case ETH_LINK_SPEED_40G:
2845 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2847 case ETH_LINK_SPEED_50G:
2848 eth_link_speed = pam4_link ?
2849 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
2850 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2852 case ETH_LINK_SPEED_100G:
2853 eth_link_speed = pam4_link ?
2854 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
2855 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2857 case ETH_LINK_SPEED_200G:
2859 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2863 "Unsupported link speed %d; default to AUTO\n",
2867 return eth_link_speed;
2870 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2871 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2872 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2873 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2874 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2876 static int bnxt_validate_link_speed(struct bnxt *bp)
2878 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2879 uint16_t port_id = bp->eth_dev->data->port_id;
2880 uint32_t link_speed_capa;
2883 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2886 link_speed_capa = bnxt_get_speed_capabilities(bp);
2888 if (link_speed & ETH_LINK_SPEED_FIXED) {
2889 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2891 if (one_speed & (one_speed - 1)) {
2893 "Invalid advertised speeds (%u) for port %u\n",
2894 link_speed, port_id);
2897 if ((one_speed & link_speed_capa) != one_speed) {
2899 "Unsupported advertised speed (%u) for port %u\n",
2900 link_speed, port_id);
2904 if (!(link_speed & link_speed_capa)) {
2906 "Unsupported advertised speeds (%u) for port %u\n",
2907 link_speed, port_id);
2915 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2919 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2920 if (bp->link_info->support_speeds)
2921 return bp->link_info->support_speeds;
2922 link_speed = BNXT_SUPPORTED_SPEEDS;
2925 if (link_speed & ETH_LINK_SPEED_100M)
2926 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2927 if (link_speed & ETH_LINK_SPEED_100M_HD)
2928 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2929 if (link_speed & ETH_LINK_SPEED_1G)
2930 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2931 if (link_speed & ETH_LINK_SPEED_2_5G)
2932 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2933 if (link_speed & ETH_LINK_SPEED_10G)
2934 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2935 if (link_speed & ETH_LINK_SPEED_20G)
2936 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2937 if (link_speed & ETH_LINK_SPEED_25G)
2938 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2939 if (link_speed & ETH_LINK_SPEED_40G)
2940 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2941 if (link_speed & ETH_LINK_SPEED_50G)
2942 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2943 if (link_speed & ETH_LINK_SPEED_100G)
2944 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2945 if (link_speed & ETH_LINK_SPEED_200G)
2946 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2950 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2952 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2954 switch (hw_link_speed) {
2955 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2956 eth_link_speed = ETH_SPEED_NUM_100M;
2958 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2959 eth_link_speed = ETH_SPEED_NUM_1G;
2961 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2962 eth_link_speed = ETH_SPEED_NUM_2_5G;
2964 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2965 eth_link_speed = ETH_SPEED_NUM_10G;
2967 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2968 eth_link_speed = ETH_SPEED_NUM_20G;
2970 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2971 eth_link_speed = ETH_SPEED_NUM_25G;
2973 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2974 eth_link_speed = ETH_SPEED_NUM_40G;
2976 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2977 eth_link_speed = ETH_SPEED_NUM_50G;
2979 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2980 eth_link_speed = ETH_SPEED_NUM_100G;
2982 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2983 eth_link_speed = ETH_SPEED_NUM_200G;
2985 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2987 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2991 return eth_link_speed;
2994 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2996 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2998 switch (hw_link_duplex) {
2999 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3000 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3002 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3004 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3005 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3008 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3012 return eth_link_duplex;
3015 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3018 struct bnxt_link_info *link_info = bp->link_info;
3020 rc = bnxt_hwrm_port_phy_qcaps(bp);
3022 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3024 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3026 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3030 if (link_info->link_speed)
3032 bnxt_parse_hw_link_speed(link_info->link_speed);
3034 link->link_speed = ETH_SPEED_NUM_NONE;
3035 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3036 link->link_status = link_info->link_up;
3037 link->link_autoneg = link_info->auto_mode ==
3038 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3039 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3044 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3047 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3048 struct bnxt_link_info link_req;
3049 uint16_t speed, autoneg;
3051 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3054 rc = bnxt_validate_link_speed(bp);
3058 memset(&link_req, 0, sizeof(link_req));
3059 link_req.link_up = link_up;
3063 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3064 if (BNXT_CHIP_THOR(bp) &&
3065 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3066 /* 40G is not supported as part of media auto detect.
3067 * The speed should be forced and autoneg disabled
3068 * to configure 40G speed.
3070 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3074 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3075 bp->link_info->link_signal_mode);
3076 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3077 /* Autoneg can be done only when the FW allows.
3078 * When user configures fixed speed of 40G and later changes to
3079 * any other speed, auto_link_speed/force_link_speed is still set
3080 * to 40G until link comes up at new speed.
3083 !(!BNXT_CHIP_THOR(bp) &&
3084 (bp->link_info->auto_link_speed ||
3085 bp->link_info->force_link_speed))) {
3086 link_req.phy_flags |=
3087 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3088 link_req.auto_link_speed_mask =
3089 bnxt_parse_eth_link_speed_mask(bp,
3090 dev_conf->link_speeds);
3092 if (bp->link_info->phy_type ==
3093 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3094 bp->link_info->phy_type ==
3095 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3096 bp->link_info->media_type ==
3097 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3098 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3102 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3103 /* If user wants a particular speed try that first. */
3105 link_req.link_speed = speed;
3106 else if (bp->link_info->force_pam4_link_speed)
3107 link_req.link_speed =
3108 bp->link_info->force_pam4_link_speed;
3109 else if (bp->link_info->auto_pam4_link_speeds)
3110 link_req.link_speed =
3111 bp->link_info->auto_pam4_link_speeds;
3112 else if (bp->link_info->support_pam4_speeds)
3113 link_req.link_speed =
3114 bp->link_info->support_pam4_speeds;
3115 else if (bp->link_info->force_link_speed)
3116 link_req.link_speed = bp->link_info->force_link_speed;
3118 link_req.link_speed = bp->link_info->auto_link_speed;
3120 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3121 link_req.auto_pause = bp->link_info->auto_pause;
3122 link_req.force_pause = bp->link_info->force_pause;
3125 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3128 "Set link config failed with rc %d\n", rc);
3136 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3138 struct hwrm_func_qcfg_input req = {0};
3139 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3142 bp->func_svif = BNXT_SVIF_INVALID;
3145 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3146 req.fid = rte_cpu_to_le_16(0xffff);
3148 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3150 HWRM_CHECK_RESULT();
3152 /* Hard Coded.. 0xfff VLAN ID mask */
3153 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3155 svif_info = rte_le_to_cpu_16(resp->svif_info);
3156 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3157 bp->func_svif = svif_info &
3158 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3160 flags = rte_le_to_cpu_16(resp->flags);
3161 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3162 bp->flags |= BNXT_FLAG_MULTI_HOST;
3165 !BNXT_VF_IS_TRUSTED(bp) &&
3166 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3167 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3168 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3169 } else if (BNXT_VF(bp) &&
3170 BNXT_VF_IS_TRUSTED(bp) &&
3171 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3172 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3173 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3177 *mtu = rte_le_to_cpu_16(resp->mtu);
3179 switch (resp->port_partition_type) {
3180 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3181 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3182 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3184 bp->flags |= BNXT_FLAG_NPAR_PF;
3187 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3196 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3198 struct hwrm_func_qcfg_input req = {0};
3199 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3202 if (!BNXT_VF_IS_TRUSTED(bp))
3208 bp->parent->fid = BNXT_PF_FID_INVALID;
3210 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3212 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3214 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3216 HWRM_CHECK_RESULT();
3218 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3219 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3220 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3221 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3223 /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3224 if (bp->parent->vnic == 0) {
3225 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3226 /* Use hard-coded values appropriate for current Wh+ fw. */
3227 if (bp->parent->fid == 2)
3228 bp->parent->vnic = 0x100;
3230 bp->parent->vnic = 1;
3238 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3239 uint16_t *vnic_id, uint16_t *svif)
3241 struct hwrm_func_qcfg_input req = {0};
3242 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3246 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3247 req.fid = rte_cpu_to_le_16(fid);
3249 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3251 HWRM_CHECK_RESULT();
3254 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3256 svif_info = rte_le_to_cpu_16(resp->svif_info);
3257 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3258 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3265 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3267 struct hwrm_port_mac_qcfg_input req = {0};
3268 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3269 uint16_t port_svif_info;
3272 bp->port_svif = BNXT_SVIF_INVALID;
3274 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3277 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3279 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3281 HWRM_CHECK_RESULT_SILENT();
3283 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3284 if (port_svif_info &
3285 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3286 bp->port_svif = port_svif_info &
3287 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3294 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3295 struct bnxt_pf_resource_info *pf_resc)
3297 struct hwrm_func_cfg_input req = {0};
3298 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3302 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3303 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3304 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3305 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3306 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3307 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3308 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3309 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3310 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3312 if (BNXT_HAS_RING_GRPS(bp)) {
3313 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3314 req.num_hw_ring_grps =
3315 rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3316 } else if (BNXT_HAS_NQ(bp)) {
3317 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3318 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3321 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3322 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3323 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3324 req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3325 req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3326 req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3327 req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3328 req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3329 req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3330 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3331 req.fid = rte_cpu_to_le_16(0xffff);
3332 req.enables = rte_cpu_to_le_32(enables);
3334 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3336 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3338 HWRM_CHECK_RESULT();
3344 /* min values are the guaranteed resources and max values are subject
3345 * to availability. The strategy for now is to keep both min & max
3349 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3350 struct hwrm_func_vf_resource_cfg_input *req,
3353 req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3355 req->min_rsscos_ctx = req->max_rsscos_ctx;
3356 req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3357 req->min_stat_ctx = req->max_stat_ctx;
3358 req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3360 req->min_cmpl_rings = req->max_cmpl_rings;
3361 req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3362 req->min_tx_rings = req->max_tx_rings;
3363 req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3364 req->min_rx_rings = req->max_rx_rings;
3365 req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3366 req->min_l2_ctxs = req->max_l2_ctxs;
3367 /* TODO: For now, do not support VMDq/RFS on VFs. */
3368 req->max_vnics = rte_cpu_to_le_16(1);
3369 req->min_vnics = req->max_vnics;
3370 req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3372 req->min_hw_ring_grps = req->max_hw_ring_grps;
3374 rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3378 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3379 struct hwrm_func_cfg_input *req,
3382 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3383 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3384 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3385 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3386 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3387 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3388 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3389 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3390 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3391 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3393 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3394 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3396 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3397 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3399 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3400 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3402 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3403 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3404 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3405 /* TODO: For now, do not support VMDq/RFS on VFs. */
3406 req->num_vnics = rte_cpu_to_le_16(1);
3407 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3411 /* Update the port wide resource values based on how many resources
3412 * got allocated to the VF.
3414 static int bnxt_update_max_resources(struct bnxt *bp,
3417 struct hwrm_func_qcfg_input req = {0};
3418 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3421 /* Get the actual allocated values now */
3422 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3423 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3424 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3425 HWRM_CHECK_RESULT();
3427 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3428 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3429 bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3430 bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3431 bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3432 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3433 bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3440 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3442 struct hwrm_func_qcfg_input req = {0};
3443 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3446 /* Check for zero MAC address */
3447 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3448 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3449 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3450 HWRM_CHECK_RESULT();
3451 rc = rte_le_to_cpu_16(resp->vlan);
3458 static int bnxt_query_pf_resources(struct bnxt *bp,
3459 struct bnxt_pf_resource_info *pf_resc)
3461 struct hwrm_func_qcfg_input req = {0};
3462 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3465 /* And copy the allocated numbers into the pf struct */
3466 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3467 req.fid = rte_cpu_to_le_16(0xffff);
3468 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3469 HWRM_CHECK_RESULT();
3471 pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3472 pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3473 pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3474 pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3475 pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3476 pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3477 pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3478 bp->pf->evb_mode = resp->evb_mode;
3486 bnxt_calculate_pf_resources(struct bnxt *bp,
3487 struct bnxt_pf_resource_info *pf_resc,
3491 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3492 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3493 pf_resc->num_cp_rings = bp->max_cp_rings;
3494 pf_resc->num_tx_rings = bp->max_tx_rings;
3495 pf_resc->num_rx_rings = bp->max_rx_rings;
3496 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3497 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3502 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3503 bp->max_rsscos_ctx % (num_vfs + 1);
3504 pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3505 bp->max_stat_ctx % (num_vfs + 1);
3506 pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3507 bp->max_cp_rings % (num_vfs + 1);
3508 pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3509 bp->max_tx_rings % (num_vfs + 1);
3510 pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3511 bp->max_rx_rings % (num_vfs + 1);
3512 pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3513 bp->max_l2_ctx % (num_vfs + 1);
3514 pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3515 bp->max_ring_grps % (num_vfs + 1);
3518 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3520 struct bnxt_pf_resource_info pf_resc = { 0 };
3524 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3528 rc = bnxt_hwrm_func_qcaps(bp);
3532 bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3534 bp->pf->func_cfg_flags &=
3535 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3536 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3537 bp->pf->func_cfg_flags |=
3538 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3539 rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3540 rc = __bnxt_hwrm_func_qcaps(bp);
3545 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3547 size_t req_buf_sz, sz;
3550 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3551 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3552 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3553 if (bp->pf->vf_req_buf == NULL) {
3557 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3558 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3560 for (i = 0; i < num_vfs; i++)
3561 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3562 (i * HWRM_MAX_REQ_LEN);
3564 rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3566 rte_free(bp->pf->vf_req_buf);
3572 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3574 struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3575 struct hwrm_func_vf_resource_cfg_input req = {0};
3578 bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3579 bp->pf->active_vfs = 0;
3580 for (i = 0; i < num_vfs; i++) {
3581 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3582 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3583 rc = bnxt_hwrm_send_message(bp,
3587 if (rc || resp->error_code) {
3589 "Failed to initialize VF %d\n", i);
3591 "Not all VFs available. (%d, %d)\n",
3592 rc, resp->error_code);
3595 /* If the first VF configuration itself fails,
3596 * unregister the vf_fwd_request buffer.
3599 bnxt_hwrm_func_buf_unrgtr(bp);
3604 /* Update the max resource values based on the resource values
3605 * allocated to the VF.
3607 bnxt_update_max_resources(bp, i);
3608 bp->pf->active_vfs++;
3609 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3616 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3618 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3619 struct hwrm_func_cfg_input req = {0};
3622 bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3624 bp->pf->active_vfs = 0;
3625 for (i = 0; i < num_vfs; i++) {
3626 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3627 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3628 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3629 rc = bnxt_hwrm_send_message(bp,
3634 /* Clear enable flag for next pass */
3635 req.enables &= ~rte_cpu_to_le_32(
3636 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3638 if (rc || resp->error_code) {
3640 "Failed to initialize VF %d\n", i);
3642 "Not all VFs available. (%d, %d)\n",
3643 rc, resp->error_code);
3646 /* If the first VF configuration itself fails,
3647 * unregister the vf_fwd_request buffer.
3650 bnxt_hwrm_func_buf_unrgtr(bp);
3656 /* Update the max resource values based on the resource values
3657 * allocated to the VF.
3659 bnxt_update_max_resources(bp, i);
3660 bp->pf->active_vfs++;
3661 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3668 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3670 if (bp->flags & BNXT_FLAG_NEW_RM)
3671 bnxt_process_vf_resc_config_new(bp, num_vfs);
3673 bnxt_process_vf_resc_config_old(bp, num_vfs);
3677 bnxt_update_pf_resources(struct bnxt *bp,
3678 struct bnxt_pf_resource_info *pf_resc)
3680 bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3681 bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3682 bp->max_cp_rings = pf_resc->num_cp_rings;
3683 bp->max_tx_rings = pf_resc->num_tx_rings;
3684 bp->max_rx_rings = pf_resc->num_rx_rings;
3685 bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3689 bnxt_configure_pf_resources(struct bnxt *bp,
3690 struct bnxt_pf_resource_info *pf_resc)
3693 * We're using STD_TX_RING_MODE here which will limit the TX
3694 * rings. This will allow QoS to function properly. Not setting this
3695 * will cause PF rings to break bandwidth settings.
3697 bp->pf->func_cfg_flags &=
3698 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3699 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3700 bp->pf->func_cfg_flags |=
3701 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3702 return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3705 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3707 struct bnxt_pf_resource_info pf_resc = { 0 };
3711 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3715 rc = bnxt_hwrm_func_qcaps(bp);
3719 bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3721 rc = bnxt_configure_pf_resources(bp, &pf_resc);
3725 rc = bnxt_query_pf_resources(bp, &pf_resc);
3730 * Now, create and register a buffer to hold forwarded VF requests
3732 rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3736 bnxt_configure_vf_resources(bp, num_vfs);
3738 bnxt_update_pf_resources(bp, &pf_resc);
3743 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3745 struct hwrm_func_cfg_input req = {0};
3746 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3749 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3751 req.fid = rte_cpu_to_le_16(0xffff);
3752 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3753 req.evb_mode = bp->pf->evb_mode;
3755 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3756 HWRM_CHECK_RESULT();
3762 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3763 uint8_t tunnel_type)
3765 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3766 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3769 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3770 req.tunnel_type = tunnel_type;
3771 req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3772 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3773 HWRM_CHECK_RESULT();
3775 switch (tunnel_type) {
3776 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3777 bp->vxlan_fw_dst_port_id =
3778 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3779 bp->vxlan_port = port;
3781 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3782 bp->geneve_fw_dst_port_id =
3783 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3784 bp->geneve_port = port;
3795 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3796 uint8_t tunnel_type)
3798 struct hwrm_tunnel_dst_port_free_input req = {0};
3799 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3802 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3804 req.tunnel_type = tunnel_type;
3805 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3806 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3808 HWRM_CHECK_RESULT();
3812 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
3814 bp->vxlan_port_cnt = 0;
3818 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
3819 bp->geneve_port = 0;
3820 bp->geneve_port_cnt = 0;
3826 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3829 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3830 struct hwrm_func_cfg_input req = {0};
3833 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3835 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3836 req.flags = rte_cpu_to_le_32(flags);
3837 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3839 HWRM_CHECK_RESULT();
3845 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3847 uint32_t *flag = flagp;
3849 vnic->flags = *flag;
3852 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3854 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3857 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
3859 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3860 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3863 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3865 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3866 req.req_buf_page_size =
3867 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
3868 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3869 req.req_buf_page_addr0 =
3870 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3871 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3873 "unable to map buffer address to physical memory\n");
3878 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3880 HWRM_CHECK_RESULT();
3886 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3889 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3890 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3892 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3895 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3897 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3899 HWRM_CHECK_RESULT();
3905 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3907 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3908 struct hwrm_func_cfg_input req = {0};
3911 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3913 req.fid = rte_cpu_to_le_16(0xffff);
3914 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3915 req.enables = rte_cpu_to_le_32(
3916 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3917 req.async_event_cr = rte_cpu_to_le_16(
3918 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3919 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3921 HWRM_CHECK_RESULT();
3927 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3929 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3930 struct hwrm_func_vf_cfg_input req = {0};
3933 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3935 req.enables = rte_cpu_to_le_32(
3936 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3937 req.async_event_cr = rte_cpu_to_le_16(
3938 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3939 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3941 HWRM_CHECK_RESULT();
3947 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3949 struct hwrm_func_cfg_input req = {0};
3950 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3951 uint16_t dflt_vlan, fid;
3952 uint32_t func_cfg_flags;
3955 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3958 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3959 fid = bp->pf->vf_info[vf].fid;
3960 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3962 fid = rte_cpu_to_le_16(0xffff);
3963 func_cfg_flags = bp->pf->func_cfg_flags;
3964 dflt_vlan = bp->vlan;
3967 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3968 req.fid = rte_cpu_to_le_16(fid);
3969 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3970 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3972 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3974 HWRM_CHECK_RESULT();
3980 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3981 uint16_t max_bw, uint16_t enables)
3983 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3984 struct hwrm_func_cfg_input req = {0};
3987 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3989 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3990 req.enables |= rte_cpu_to_le_32(enables);
3991 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3992 req.max_bw = rte_cpu_to_le_32(max_bw);
3993 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3995 HWRM_CHECK_RESULT();
4001 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4003 struct hwrm_func_cfg_input req = {0};
4004 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4007 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4009 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4010 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4011 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4012 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4014 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4016 HWRM_CHECK_RESULT();
4022 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4027 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4029 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4034 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4035 void *encaped, size_t ec_size)
4038 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4039 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4041 if (ec_size > sizeof(req.encap_request))
4044 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4046 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4047 memcpy(req.encap_request, encaped, ec_size);
4049 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4051 HWRM_CHECK_RESULT();
4057 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4058 struct rte_ether_addr *mac)
4060 struct hwrm_func_qcfg_input req = {0};
4061 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4064 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4066 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4067 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4069 HWRM_CHECK_RESULT();
4071 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4078 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4079 void *encaped, size_t ec_size)
4082 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4083 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4085 if (ec_size > sizeof(req.encap_request))
4088 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4090 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4091 memcpy(req.encap_request, encaped, ec_size);
4093 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4095 HWRM_CHECK_RESULT();
4101 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
4102 struct rte_eth_stats *stats, uint8_t rx)
4105 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4106 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4108 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4110 req.stat_ctx_id = rte_cpu_to_le_32(cid);
4112 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4114 HWRM_CHECK_RESULT();
4117 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4118 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4119 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4120 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4121 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4122 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4123 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4124 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4126 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4127 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4128 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4129 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4130 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4131 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4139 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4141 struct hwrm_port_qstats_input req = {0};
4142 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4143 struct bnxt_pf_info *pf = bp->pf;
4146 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4148 req.port_id = rte_cpu_to_le_16(pf->port_id);
4149 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4150 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4151 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4153 HWRM_CHECK_RESULT();
4159 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4161 struct hwrm_port_clr_stats_input req = {0};
4162 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4163 struct bnxt_pf_info *pf = bp->pf;
4166 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4167 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4168 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4171 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4173 req.port_id = rte_cpu_to_le_16(pf->port_id);
4174 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4176 HWRM_CHECK_RESULT();
4182 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4184 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4185 struct hwrm_port_led_qcaps_input req = {0};
4191 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4192 req.port_id = bp->pf->port_id;
4193 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4195 HWRM_CHECK_RESULT();
4197 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4200 bp->leds->num_leds = resp->num_leds;
4201 memcpy(bp->leds, &resp->led0_id,
4202 sizeof(bp->leds[0]) * bp->leds->num_leds);
4203 for (i = 0; i < bp->leds->num_leds; i++) {
4204 struct bnxt_led_info *led = &bp->leds[i];
4206 uint16_t caps = led->led_state_caps;
4208 if (!led->led_group_id ||
4209 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4210 bp->leds->num_leds = 0;
4221 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4223 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4224 struct hwrm_port_led_cfg_input req = {0};
4225 struct bnxt_led_cfg *led_cfg;
4226 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4227 uint16_t duration = 0;
4230 if (!bp->leds->num_leds || BNXT_VF(bp))
4233 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4236 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4237 duration = rte_cpu_to_le_16(500);
4239 req.port_id = bp->pf->port_id;
4240 req.num_leds = bp->leds->num_leds;
4241 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4242 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4243 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4244 led_cfg->led_id = bp->leds[i].led_id;
4245 led_cfg->led_state = led_state;
4246 led_cfg->led_blink_on = duration;
4247 led_cfg->led_blink_off = duration;
4248 led_cfg->led_group_id = bp->leds[i].led_group_id;
4251 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4253 HWRM_CHECK_RESULT();
4259 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4263 struct hwrm_nvm_get_dir_info_input req = {0};
4264 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4266 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4268 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4270 HWRM_CHECK_RESULT();
4272 *entries = rte_le_to_cpu_32(resp->entries);
4273 *length = rte_le_to_cpu_32(resp->entry_length);
4279 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4282 uint32_t dir_entries;
4283 uint32_t entry_length;
4286 rte_iova_t dma_handle;
4287 struct hwrm_nvm_get_dir_entries_input req = {0};
4288 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4290 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4294 *data++ = dir_entries;
4295 *data++ = entry_length;
4297 memset(data, 0xff, len);
4299 buflen = dir_entries * entry_length;
4300 buf = rte_malloc("nvm_dir", buflen, 0);
4303 dma_handle = rte_malloc_virt2iova(buf);
4304 if (dma_handle == RTE_BAD_IOVA) {
4306 "unable to map response address to physical memory\n");
4309 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4310 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4311 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4314 memcpy(data, buf, len > buflen ? buflen : len);
4317 HWRM_CHECK_RESULT();
4323 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4324 uint32_t offset, uint32_t length,
4329 rte_iova_t dma_handle;
4330 struct hwrm_nvm_read_input req = {0};
4331 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4333 buf = rte_malloc("nvm_item", length, 0);
4337 dma_handle = rte_malloc_virt2iova(buf);
4338 if (dma_handle == RTE_BAD_IOVA) {
4340 "unable to map response address to physical memory\n");
4343 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4344 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4345 req.dir_idx = rte_cpu_to_le_16(index);
4346 req.offset = rte_cpu_to_le_32(offset);
4347 req.len = rte_cpu_to_le_32(length);
4348 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4350 memcpy(data, buf, length);
4353 HWRM_CHECK_RESULT();
4359 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4362 struct hwrm_nvm_erase_dir_entry_input req = {0};
4363 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4365 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4366 req.dir_idx = rte_cpu_to_le_16(index);
4367 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4368 HWRM_CHECK_RESULT();
4375 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4376 uint16_t dir_ordinal, uint16_t dir_ext,
4377 uint16_t dir_attr, const uint8_t *data,
4381 struct hwrm_nvm_write_input req = {0};
4382 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4383 rte_iova_t dma_handle;
4386 buf = rte_malloc("nvm_write", data_len, 0);
4390 dma_handle = rte_malloc_virt2iova(buf);
4391 if (dma_handle == RTE_BAD_IOVA) {
4393 "unable to map response address to physical memory\n");
4396 memcpy(buf, data, data_len);
4398 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4400 req.dir_type = rte_cpu_to_le_16(dir_type);
4401 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4402 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4403 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4404 req.dir_data_length = rte_cpu_to_le_32(data_len);
4405 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4407 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4410 HWRM_CHECK_RESULT();
4417 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4419 uint32_t *count = cbdata;
4421 *count = *count + 1;
4424 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4425 struct bnxt_vnic_info *vnic __rte_unused)
4430 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4434 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4435 &count, bnxt_vnic_count_hwrm_stub);
4440 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4443 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4444 struct hwrm_func_vf_vnic_ids_query_output *resp =
4445 bp->hwrm_cmd_resp_addr;
4448 /* First query all VNIC ids */
4449 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4451 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4452 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4453 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4455 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4458 "unable to map VNIC ID table address to physical memory\n");
4461 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4462 HWRM_CHECK_RESULT();
4463 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4471 * This function queries the VNIC IDs for a specified VF. It then calls
4472 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4473 * Then it calls the hwrm_cb function to program this new vnic configuration.
4475 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4476 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4477 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4479 struct bnxt_vnic_info vnic;
4481 int i, num_vnic_ids;
4486 /* First query all VNIC ids */
4487 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4488 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4489 RTE_CACHE_LINE_SIZE);
4490 if (vnic_ids == NULL)
4493 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4494 rte_mem_lock_page(((char *)vnic_ids) + sz);
4496 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4498 if (num_vnic_ids < 0)
4499 return num_vnic_ids;
4501 /* Retrieve VNIC, update bd_stall then update */
4503 for (i = 0; i < num_vnic_ids; i++) {
4504 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4505 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4506 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4509 if (vnic.mru <= 4) /* Indicates unallocated */
4512 vnic_cb(&vnic, cbdata);
4514 rc = hwrm_cb(bp, &vnic);
4524 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4527 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4528 struct hwrm_func_cfg_input req = {0};
4531 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4533 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4534 req.enables |= rte_cpu_to_le_32(
4535 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4536 req.vlan_antispoof_mode = on ?
4537 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4538 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4539 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4541 HWRM_CHECK_RESULT();
4547 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4549 struct bnxt_vnic_info vnic;
4552 int num_vnic_ids, i;
4556 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4557 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4558 RTE_CACHE_LINE_SIZE);
4559 if (vnic_ids == NULL)
4562 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4563 rte_mem_lock_page(((char *)vnic_ids) + sz);
4565 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4571 * Loop through to find the default VNIC ID.
4572 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4573 * by sending the hwrm_func_qcfg command to the firmware.
4575 for (i = 0; i < num_vnic_ids; i++) {
4576 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4577 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4578 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4579 bp->pf->first_vf_id + vf);
4582 if (vnic.func_default) {
4584 return vnic.fw_vnic_id;
4587 /* Could not find a default VNIC. */
4588 PMD_DRV_LOG(ERR, "No default VNIC\n");
4594 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4596 struct bnxt_filter_info *filter)
4599 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4600 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4601 uint32_t enables = 0;
4603 if (filter->fw_em_filter_id != UINT64_MAX)
4604 bnxt_hwrm_clear_em_filter(bp, filter);
4606 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4608 req.flags = rte_cpu_to_le_32(filter->flags);
4610 enables = filter->enables |
4611 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4612 req.dst_id = rte_cpu_to_le_16(dst_id);
4614 if (filter->ip_addr_type) {
4615 req.ip_addr_type = filter->ip_addr_type;
4616 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4619 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4620 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4622 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4623 memcpy(req.src_macaddr, filter->src_macaddr,
4624 RTE_ETHER_ADDR_LEN);
4626 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4627 memcpy(req.dst_macaddr, filter->dst_macaddr,
4628 RTE_ETHER_ADDR_LEN);
4630 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4631 req.ovlan_vid = filter->l2_ovlan;
4633 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4634 req.ivlan_vid = filter->l2_ivlan;
4636 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4637 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4639 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4640 req.ip_protocol = filter->ip_protocol;
4642 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4643 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4645 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4646 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4648 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4649 req.src_port = rte_cpu_to_be_16(filter->src_port);
4651 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4652 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4654 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4655 req.mirror_vnic_id = filter->mirror_vnic_id;
4657 req.enables = rte_cpu_to_le_32(enables);
4659 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4661 HWRM_CHECK_RESULT();
4663 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4669 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4672 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4673 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4675 if (filter->fw_em_filter_id == UINT64_MAX)
4678 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4680 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4682 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4684 HWRM_CHECK_RESULT();
4687 filter->fw_em_filter_id = UINT64_MAX;
4688 filter->fw_l2_filter_id = UINT64_MAX;
4693 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4695 struct bnxt_filter_info *filter)
4698 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4699 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4700 bp->hwrm_cmd_resp_addr;
4701 uint32_t enables = 0;
4703 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4704 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4706 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4708 req.flags = rte_cpu_to_le_32(filter->flags);
4710 enables = filter->enables |
4711 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4712 req.dst_id = rte_cpu_to_le_16(dst_id);
4714 if (filter->ip_addr_type) {
4715 req.ip_addr_type = filter->ip_addr_type;
4717 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4720 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4721 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4723 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4724 memcpy(req.src_macaddr, filter->src_macaddr,
4725 RTE_ETHER_ADDR_LEN);
4727 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4728 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4730 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4731 req.ip_protocol = filter->ip_protocol;
4733 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4734 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4736 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4737 req.src_ipaddr_mask[0] =
4738 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4740 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4741 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4743 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4744 req.dst_ipaddr_mask[0] =
4745 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4747 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4748 req.src_port = rte_cpu_to_le_16(filter->src_port);
4750 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4751 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4753 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4754 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4756 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4757 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4759 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4760 req.mirror_vnic_id = filter->mirror_vnic_id;
4762 req.enables = rte_cpu_to_le_32(enables);
4764 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4766 HWRM_CHECK_RESULT();
4768 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4769 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4775 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4776 struct bnxt_filter_info *filter)
4779 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4780 struct hwrm_cfa_ntuple_filter_free_output *resp =
4781 bp->hwrm_cmd_resp_addr;
4783 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4786 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4788 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4790 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4792 HWRM_CHECK_RESULT();
4795 filter->fw_ntuple_filter_id = UINT64_MAX;
4801 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4803 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4804 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4805 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4806 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4807 uint16_t *ring_tbl = vnic->rss_table;
4808 int nr_ctxs = vnic->num_lb_ctxts;
4809 int max_rings = bp->rx_nr_rings;
4813 for (i = 0, k = 0; i < nr_ctxs; i++) {
4814 struct bnxt_rx_ring_info *rxr;
4815 struct bnxt_cp_ring_info *cpr;
4817 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4819 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4820 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4821 req.hash_mode_flags = vnic->hash_mode;
4823 req.ring_grp_tbl_addr =
4824 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4825 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4826 2 * sizeof(*ring_tbl));
4827 req.hash_key_tbl_addr =
4828 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4830 req.ring_table_pair_index = i;
4831 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4833 for (j = 0; j < 64; j++) {
4836 /* Find next active ring. */
4837 for (cnt = 0; cnt < max_rings; cnt++) {
4838 if (rx_queue_state[k] !=
4839 RTE_ETH_QUEUE_STATE_STOPPED)
4841 if (++k == max_rings)
4845 /* Return if no rings are active. */
4846 if (cnt == max_rings) {
4851 /* Add rx/cp ring pair to RSS table. */
4852 rxr = rxqs[k]->rx_ring;
4853 cpr = rxqs[k]->cp_ring;
4855 ring_id = rxr->rx_ring_struct->fw_ring_id;
4856 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4857 ring_id = cpr->cp_ring_struct->fw_ring_id;
4858 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4860 if (++k == max_rings)
4863 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4866 HWRM_CHECK_RESULT();
4873 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4875 unsigned int rss_idx, fw_idx, i;
4877 if (!(vnic->rss_table && vnic->hash_type))
4880 if (BNXT_CHIP_THOR(bp))
4881 return bnxt_vnic_rss_configure_thor(bp, vnic);
4883 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4886 if (vnic->rss_table && vnic->hash_type) {
4888 * Fill the RSS hash & redirection table with
4889 * ring group ids for all VNICs
4891 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4892 rss_idx++, fw_idx++) {
4893 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4894 fw_idx %= bp->rx_cp_nr_rings;
4895 if (vnic->fw_grp_ids[fw_idx] !=
4900 if (i == bp->rx_cp_nr_rings)
4902 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4904 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4910 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4911 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4915 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4917 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4918 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4920 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4921 req->num_cmpl_dma_aggr_during_int =
4922 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4924 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4926 /* min timer set to 1/2 of interrupt timer */
4927 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4929 /* buf timer set to 1/4 of interrupt timer */
4930 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4932 req->cmpl_aggr_dma_tmr_during_int =
4933 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4935 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4936 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4937 req->flags = rte_cpu_to_le_16(flags);
4940 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4941 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4943 struct hwrm_ring_aggint_qcaps_input req = {0};
4944 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4949 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4950 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4951 HWRM_CHECK_RESULT();
4953 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4954 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4956 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4957 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4958 agg_req->flags = rte_cpu_to_le_16(flags);
4960 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4961 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4962 agg_req->enables = rte_cpu_to_le_32(enables);
4968 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4969 struct bnxt_coal *coal, uint16_t ring_id)
4971 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4972 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4973 bp->hwrm_cmd_resp_addr;
4976 /* Set ring coalesce parameters only for 100G NICs */
4977 if (BNXT_CHIP_THOR(bp)) {
4978 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4980 } else if (bnxt_stratus_device(bp)) {
4981 bnxt_hwrm_set_coal_params(coal, &req);
4987 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4989 req.ring_id = rte_cpu_to_le_16(ring_id);
4990 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4991 HWRM_CHECK_RESULT();
4996 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4997 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4999 struct hwrm_func_backing_store_qcaps_input req = {0};
5000 struct hwrm_func_backing_store_qcaps_output *resp =
5001 bp->hwrm_cmd_resp_addr;
5002 struct bnxt_ctx_pg_info *ctx_pg;
5003 struct bnxt_ctx_mem_info *ctx;
5004 int total_alloc_len;
5005 int rc, i, tqm_rings;
5007 if (!BNXT_CHIP_THOR(bp) ||
5008 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5013 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5014 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5015 HWRM_CHECK_RESULT_SILENT();
5017 total_alloc_len = sizeof(*ctx);
5018 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5019 RTE_CACHE_LINE_SIZE);
5025 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5026 ctx->qp_min_qp1_entries =
5027 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5028 ctx->qp_max_l2_entries =
5029 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5030 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5031 ctx->srq_max_l2_entries =
5032 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5033 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5034 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5035 ctx->cq_max_l2_entries =
5036 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5037 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5038 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5039 ctx->vnic_max_vnic_entries =
5040 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5041 ctx->vnic_max_ring_table_entries =
5042 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5043 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5044 ctx->stat_max_entries =
5045 rte_le_to_cpu_32(resp->stat_max_entries);
5046 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5047 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5048 ctx->tqm_min_entries_per_ring =
5049 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5050 ctx->tqm_max_entries_per_ring =
5051 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5052 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5053 if (!ctx->tqm_entries_multiple)
5054 ctx->tqm_entries_multiple = 1;
5055 ctx->mrav_max_entries =
5056 rte_le_to_cpu_32(resp->mrav_max_entries);
5057 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5058 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5059 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5060 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5062 if (!ctx->tqm_fp_rings_count)
5063 ctx->tqm_fp_rings_count = bp->max_q;
5065 tqm_rings = ctx->tqm_fp_rings_count + 1;
5067 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5068 sizeof(*ctx_pg) * tqm_rings,
5069 RTE_CACHE_LINE_SIZE);
5074 for (i = 0; i < tqm_rings; i++, ctx_pg++)
5075 ctx->tqm_mem[i] = ctx_pg;
5083 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5085 struct hwrm_func_backing_store_cfg_input req = {0};
5086 struct hwrm_func_backing_store_cfg_output *resp =
5087 bp->hwrm_cmd_resp_addr;
5088 struct bnxt_ctx_mem_info *ctx = bp->ctx;
5089 struct bnxt_ctx_pg_info *ctx_pg;
5090 uint32_t *num_entries;
5099 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5100 req.enables = rte_cpu_to_le_32(enables);
5102 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5103 ctx_pg = &ctx->qp_mem;
5104 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5105 req.qp_num_qp1_entries =
5106 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5107 req.qp_num_l2_entries =
5108 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5109 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5110 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5111 &req.qpc_pg_size_qpc_lvl,
5115 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5116 ctx_pg = &ctx->srq_mem;
5117 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5118 req.srq_num_l2_entries =
5119 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5120 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5121 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5122 &req.srq_pg_size_srq_lvl,
5126 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5127 ctx_pg = &ctx->cq_mem;
5128 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5129 req.cq_num_l2_entries =
5130 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5131 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5132 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5133 &req.cq_pg_size_cq_lvl,
5137 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5138 ctx_pg = &ctx->vnic_mem;
5139 req.vnic_num_vnic_entries =
5140 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5141 req.vnic_num_ring_table_entries =
5142 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5143 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5144 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5145 &req.vnic_pg_size_vnic_lvl,
5146 &req.vnic_page_dir);
5149 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5150 ctx_pg = &ctx->stat_mem;
5151 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5152 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5153 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5154 &req.stat_pg_size_stat_lvl,
5155 &req.stat_page_dir);
5158 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5159 num_entries = &req.tqm_sp_num_entries;
5160 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5161 pg_dir = &req.tqm_sp_page_dir;
5162 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5163 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5164 if (!(enables & ena))
5167 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5169 ctx_pg = ctx->tqm_mem[i];
5170 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5171 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5174 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5175 HWRM_CHECK_RESULT();
5181 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5183 struct hwrm_port_qstats_ext_input req = {0};
5184 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5185 struct bnxt_pf_info *pf = bp->pf;
5188 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5189 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5192 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5194 req.port_id = rte_cpu_to_le_16(pf->port_id);
5195 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5196 req.tx_stat_host_addr =
5197 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5199 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5201 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5202 req.rx_stat_host_addr =
5203 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5205 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5207 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5210 bp->fw_rx_port_stats_ext_size = 0;
5211 bp->fw_tx_port_stats_ext_size = 0;
5213 bp->fw_rx_port_stats_ext_size =
5214 rte_le_to_cpu_16(resp->rx_stat_size);
5215 bp->fw_tx_port_stats_ext_size =
5216 rte_le_to_cpu_16(resp->tx_stat_size);
5219 HWRM_CHECK_RESULT();
5226 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5228 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5229 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5230 bp->hwrm_cmd_resp_addr;
5233 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5234 req.tunnel_type = type;
5235 req.dest_fid = bp->fw_fid;
5236 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5237 HWRM_CHECK_RESULT();
5245 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5247 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5248 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5249 bp->hwrm_cmd_resp_addr;
5252 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5253 req.tunnel_type = type;
5254 req.dest_fid = bp->fw_fid;
5255 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5256 HWRM_CHECK_RESULT();
5263 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5265 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5266 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5267 bp->hwrm_cmd_resp_addr;
5270 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5271 req.src_fid = bp->fw_fid;
5272 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5273 HWRM_CHECK_RESULT();
5276 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5283 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5286 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5287 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5288 bp->hwrm_cmd_resp_addr;
5291 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5292 req.src_fid = bp->fw_fid;
5293 req.tunnel_type = tun_type;
5294 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5295 HWRM_CHECK_RESULT();
5298 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5300 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5307 int bnxt_hwrm_set_mac(struct bnxt *bp)
5309 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5310 struct hwrm_func_vf_cfg_input req = {0};
5316 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5319 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5320 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5322 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5324 HWRM_CHECK_RESULT();
5331 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5333 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5334 struct hwrm_func_drv_if_change_input req = {0};
5338 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5341 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5342 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5343 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5345 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5348 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5352 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5354 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5356 HWRM_CHECK_RESULT();
5357 flags = rte_le_to_cpu_32(resp->flags);
5363 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5364 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5365 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5371 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5373 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5374 struct bnxt_error_recovery_info *info = bp->recovery_info;
5375 struct hwrm_error_recovery_qcfg_input req = {0};
5380 /* Older FW does not have error recovery support */
5381 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5384 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5386 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5388 HWRM_CHECK_RESULT();
5390 flags = rte_le_to_cpu_32(resp->flags);
5391 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5392 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5393 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5394 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5396 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5397 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5402 /* FW returned values are in units of 100msec */
5403 info->driver_polling_freq =
5404 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5405 info->master_func_wait_period =
5406 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5407 info->normal_func_wait_period =
5408 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5409 info->master_func_wait_period_after_reset =
5410 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5411 info->max_bailout_time_after_reset =
5412 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5413 info->status_regs[BNXT_FW_STATUS_REG] =
5414 rte_le_to_cpu_32(resp->fw_health_status_reg);
5415 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5416 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5417 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5418 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5419 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5420 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5421 info->reg_array_cnt =
5422 rte_le_to_cpu_32(resp->reg_array_cnt);
5424 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5429 for (i = 0; i < info->reg_array_cnt; i++) {
5430 info->reset_reg[i] =
5431 rte_le_to_cpu_32(resp->reset_reg[i]);
5432 info->reset_reg_val[i] =
5433 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5434 info->delay_after_reset[i] =
5435 resp->delay_after_reset[i];
5440 /* Map the FW status registers */
5442 rc = bnxt_map_fw_health_status_regs(bp);
5445 rte_free(bp->recovery_info);
5446 bp->recovery_info = NULL;
5451 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5453 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5454 struct hwrm_fw_reset_input req = {0};
5460 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5462 req.embedded_proc_type =
5463 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5464 req.selfrst_status =
5465 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5466 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5468 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5471 HWRM_CHECK_RESULT();
5477 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5479 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5480 struct hwrm_port_ts_query_input req = {0};
5481 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5488 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5491 case BNXT_PTP_FLAGS_PATH_TX:
5492 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5494 case BNXT_PTP_FLAGS_PATH_RX:
5495 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5497 case BNXT_PTP_FLAGS_CURRENT_TIME:
5498 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5502 req.flags = rte_cpu_to_le_32(flags);
5503 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5507 HWRM_CHECK_RESULT();
5510 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5512 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5519 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5523 struct hwrm_cfa_counter_qcaps_input req = {0};
5524 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5526 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5528 "Not a PF or trusted VF. Command not supported\n");
5532 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5533 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5534 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5536 HWRM_CHECK_RESULT();
5538 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5544 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5547 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5548 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5550 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5552 "Not a PF or trusted VF. Command not supported\n");
5556 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5558 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5559 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5560 req.page_dir = rte_cpu_to_le_64(dma_addr);
5562 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5564 HWRM_CHECK_RESULT();
5566 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5567 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5574 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5577 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5578 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5580 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5582 "Not a PF or trusted VF. Command not supported\n");
5586 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5588 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5590 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5592 HWRM_CHECK_RESULT();
5598 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5599 uint16_t cntr, uint16_t ctx_id,
5600 uint32_t num_entries, bool enable)
5602 struct hwrm_cfa_counter_cfg_input req = {0};
5603 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5607 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5609 "Not a PF or trusted VF. Command not supported\n");
5613 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5615 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5616 req.counter_type = rte_cpu_to_le_16(cntr);
5617 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5618 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5619 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5620 if (dir == BNXT_DIR_RX)
5621 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5622 else if (dir == BNXT_DIR_TX)
5623 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5624 req.flags = rte_cpu_to_le_16(flags);
5625 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5626 req.num_entries = rte_cpu_to_le_32(num_entries);
5628 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5629 HWRM_CHECK_RESULT();
5635 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5636 enum bnxt_flow_dir dir,
5638 uint16_t num_entries)
5640 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5641 struct hwrm_cfa_counter_qstats_input req = {0};
5642 uint16_t flow_ctx_id = 0;
5646 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5648 "Not a PF or trusted VF. Command not supported\n");
5652 if (dir == BNXT_DIR_RX) {
5653 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5654 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5655 } else if (dir == BNXT_DIR_TX) {
5656 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5657 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5660 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5661 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5662 req.counter_type = rte_cpu_to_le_16(cntr);
5663 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5664 req.num_entries = rte_cpu_to_le_16(num_entries);
5665 req.flags = rte_cpu_to_le_16(flags);
5666 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5668 HWRM_CHECK_RESULT();
5674 int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx)
5676 struct hwrm_cfa_vfr_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5677 struct hwrm_cfa_vfr_alloc_input req = {0};
5680 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5682 "Not a PF or trusted VF. Command not supported\n");
5686 HWRM_PREP(&req, HWRM_CFA_VFR_ALLOC, BNXT_USE_CHIMP_MB);
5687 req.vf_id = rte_cpu_to_le_16(vf_idx);
5688 snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5689 bp->eth_dev->data->name, vf_idx);
5691 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5692 HWRM_CHECK_RESULT();
5695 PMD_DRV_LOG(DEBUG, "VFR %d allocated\n", vf_idx);
5699 int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx)
5701 struct hwrm_cfa_vfr_free_output *resp = bp->hwrm_cmd_resp_addr;
5702 struct hwrm_cfa_vfr_free_input req = {0};
5705 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5707 "Not a PF or trusted VF. Command not supported\n");
5711 HWRM_PREP(&req, HWRM_CFA_VFR_FREE, BNXT_USE_CHIMP_MB);
5712 req.vf_id = rte_cpu_to_le_16(vf_idx);
5713 snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5714 bp->eth_dev->data->name, vf_idx);
5716 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5717 HWRM_CHECK_RESULT();
5719 PMD_DRV_LOG(DEBUG, "VFR %d freed\n", vf_idx);
5723 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5724 uint16_t *first_vf_id)
5727 struct hwrm_func_qcaps_input req = {.req_type = 0 };
5728 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5730 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5732 req.fid = rte_cpu_to_le_16(fid);
5734 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5736 HWRM_CHECK_RESULT();
5739 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5746 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5748 struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5749 struct hwrm_cfa_pair_alloc_input req = {0};
5752 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5754 "Not a PF or trusted VF. Command not supported\n");
5758 HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5759 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5760 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5761 bp->eth_dev->data->name, rep_bp->vf_id);
5763 req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
5764 req.vf_b_id = rte_cpu_to_le_16(rep_bp->vf_id);
5765 req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5766 req.host_b_id = 1; /* TBD - Confirm if this is OK */
5768 req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5769 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5770 req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5771 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5772 req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5773 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5774 req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5775 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5777 req.q_ab = rep_bp->rep_q_r2f;
5778 req.q_ba = rep_bp->rep_q_f2r;
5779 req.fc_ab = rep_bp->rep_fc_r2f;
5780 req.fc_ba = rep_bp->rep_fc_f2r;
5782 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5783 HWRM_CHECK_RESULT();
5786 PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5787 BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5791 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5793 struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5794 struct hwrm_cfa_pair_free_input req = {0};
5797 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5799 "Not a PF or trusted VF. Command not supported\n");
5803 HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5804 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5805 bp->eth_dev->data->name, rep_bp->vf_id);
5806 req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
5807 req.vf_id = rte_cpu_to_le_16(rep_bp->vf_id);
5808 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5810 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5811 HWRM_CHECK_RESULT();
5813 PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",