1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
30 #define HWRM_VERSION_1_10_2_13 0x10a020d
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(int) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages == 0)
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
79 * HWRM Functions (sent to HWRM)
80 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
81 * HWRM command times out, or a negative error code if the HWRM
82 * command was failed by the FW.
85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
86 uint32_t msg_len, bool use_kong_mb)
89 struct input *req = msg;
90 struct output *resp = bp->hwrm_cmd_resp_addr;
94 uint16_t max_req_len = bp->max_req_len;
95 struct hwrm_short_input short_input = { 0 };
96 uint16_t bar_offset = use_kong_mb ?
97 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
98 uint16_t mb_trigger_offset = use_kong_mb ?
99 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
102 /* Do not send HWRM commands to firmware in error state */
103 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
106 timeout = bp->hwrm_cmd_timeout;
108 /* Update the message length for backing store config for new FW. */
109 if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
110 rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
111 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
113 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
114 msg_len > bp->max_req_len) {
115 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
117 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
118 memcpy(short_cmd_req, req, msg_len);
120 short_input.req_type = rte_cpu_to_le_16(req->req_type);
121 short_input.signature = rte_cpu_to_le_16(
122 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
123 short_input.size = rte_cpu_to_le_16(msg_len);
124 short_input.req_addr =
125 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
127 data = (uint32_t *)&short_input;
128 msg_len = sizeof(short_input);
130 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
133 /* Write request msg to hwrm channel */
134 for (i = 0; i < msg_len; i += 4) {
135 bar = (uint8_t *)bp->bar0 + bar_offset + i;
136 rte_write32(*data, bar);
140 /* Zero the rest of the request space */
141 for (; i < max_req_len; i += 4) {
142 bar = (uint8_t *)bp->bar0 + bar_offset + i;
146 /* Ring channel doorbell */
147 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
150 * Make sure the channel doorbell ring command complete before
151 * reading the response to avoid getting stale or invalid
156 /* Poll for the valid bit */
157 for (i = 0; i < timeout; i++) {
158 /* Sanity check on the resp->resp_len */
160 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
161 /* Last byte of resp contains the valid key */
162 valid = (uint8_t *)resp + resp->resp_len - 1;
163 if (*valid == HWRM_RESP_VALID_KEY)
170 /* Suppress VER_GET timeout messages during reset recovery */
171 if (bp->flags & BNXT_FLAG_FW_RESET &&
172 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
176 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
177 req->req_type, req->seq_id);
184 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
185 * spinlock, and does initial processing.
187 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
188 * releases the spinlock only if it returns. If the regular int return codes
189 * are not used by the function, HWRM_CHECK_RESULT() should not be used
190 * directly, rather it should be copied and modified to suit the function.
192 * HWRM_UNLOCK() must be called after all response processing is completed.
194 #define HWRM_PREP(req, type, kong) do { \
195 rte_spinlock_lock(&bp->hwrm_lock); \
196 if (bp->hwrm_cmd_resp_addr == NULL) { \
197 rte_spinlock_unlock(&bp->hwrm_lock); \
200 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
201 (req)->req_type = rte_cpu_to_le_16(type); \
202 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
203 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
204 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
205 (req)->target_id = rte_cpu_to_le_16(0xffff); \
206 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
209 #define HWRM_CHECK_RESULT_SILENT() do {\
211 rte_spinlock_unlock(&bp->hwrm_lock); \
214 if (resp->error_code) { \
215 rc = rte_le_to_cpu_16(resp->error_code); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
221 #define HWRM_CHECK_RESULT() do {\
223 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
224 rte_spinlock_unlock(&bp->hwrm_lock); \
225 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
227 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
229 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
231 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
233 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
239 if (resp->error_code) { \
240 rc = rte_le_to_cpu_16(resp->error_code); \
241 if (resp->resp_len >= 16) { \
242 struct hwrm_err_output *tmp_hwrm_err_op = \
245 "error %d:%d:%08x:%04x\n", \
246 rc, tmp_hwrm_err_op->cmd_err, \
248 tmp_hwrm_err_op->opaque_0), \
250 tmp_hwrm_err_op->opaque_1)); \
252 PMD_DRV_LOG(ERR, "error %d\n", rc); \
254 rte_spinlock_unlock(&bp->hwrm_lock); \
255 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
257 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
259 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
261 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
263 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
271 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
273 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
282 bool mailbox = BNXT_USE_CHIMP_MB;
283 struct input *req = msg;
284 struct output *resp = bp->hwrm_cmd_resp_addr;
287 mailbox = BNXT_USE_KONG(bp);
289 HWRM_PREP(req, msg_type, mailbox);
291 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
296 memcpy(resp_msg, resp, resp_len);
303 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
307 uint32_t *tf_response_code,
311 uint32_t response_len)
314 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
315 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
316 bool mailbox = BNXT_USE_CHIMP_MB;
318 if (msg_len > sizeof(req.tf_req))
322 mailbox = BNXT_USE_KONG(bp);
324 HWRM_PREP(&req, HWRM_TF, mailbox);
325 /* Build request using the user supplied request payload.
326 * TLV request size is checked at build time against HWRM
327 * request max size, thus no checking required.
329 req.tf_type = tf_type;
330 req.tf_subtype = tf_subtype;
331 memcpy(req.tf_req, msg, msg_len);
333 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
336 /* Copy the resp to user provided response buffer */
337 if (response != NULL)
338 /* Post process response data. We need to copy only
339 * the 'payload' as the HWRM data structure really is
340 * HWRM header + msg header + payload and the TFLIB
341 * only provided a payload place holder.
343 if (response_len != 0) {
349 /* Extract the internal tflib response code */
350 *tf_response_code = resp->tf_resp_code;
356 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
359 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
360 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
362 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
363 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
366 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
374 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
375 struct bnxt_vnic_info *vnic,
377 struct bnxt_vlan_table_entry *vlan_table)
380 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
381 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
384 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
387 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
388 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
390 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
391 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
392 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
393 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
395 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
396 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
398 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
399 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
400 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
401 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
402 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
403 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
406 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
407 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
408 req.vlan_tag_tbl_addr =
409 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
410 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
412 req.mask = rte_cpu_to_le_32(mask);
414 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
422 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
424 struct bnxt_vlan_antispoof_table_entry *vlan_table)
427 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
428 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
429 bp->hwrm_cmd_resp_addr;
432 * Older HWRM versions did not support this command, and the set_rx_mask
433 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
434 * removed from set_rx_mask call, and this command was added.
436 * This command is also present from 1.7.8.11 and higher,
439 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
440 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
441 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
446 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
447 req.fid = rte_cpu_to_le_16(fid);
449 req.vlan_tag_mask_tbl_addr =
450 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
451 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
453 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
461 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
462 struct bnxt_filter_info *filter)
465 struct bnxt_filter_info *l2_filter = filter;
466 struct bnxt_vnic_info *vnic = NULL;
467 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
468 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
470 if (filter->fw_l2_filter_id == UINT64_MAX)
473 if (filter->matching_l2_fltr_ptr)
474 l2_filter = filter->matching_l2_fltr_ptr;
476 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
477 filter, l2_filter, l2_filter->l2_ref_cnt);
479 if (l2_filter->l2_ref_cnt == 0)
482 if (l2_filter->l2_ref_cnt > 0)
483 l2_filter->l2_ref_cnt--;
485 if (l2_filter->l2_ref_cnt > 0)
488 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
490 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
492 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
497 filter->fw_l2_filter_id = UINT64_MAX;
498 if (l2_filter->l2_ref_cnt == 0) {
499 vnic = l2_filter->vnic;
501 STAILQ_REMOVE(&vnic->filter, l2_filter,
502 bnxt_filter_info, next);
503 bnxt_free_filter(bp, l2_filter);
510 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
512 struct bnxt_filter_info *filter)
515 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
516 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
517 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
518 const struct rte_eth_vmdq_rx_conf *conf =
519 &dev_conf->rx_adv_conf.vmdq_rx_conf;
520 uint32_t enables = 0;
521 uint16_t j = dst_id - 1;
523 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
524 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
525 conf->pool_map[j].pools & (1UL << j)) {
527 "Add vlan %u to vmdq pool %u\n",
528 conf->pool_map[j].vlan_id, j);
530 filter->l2_ivlan = conf->pool_map[j].vlan_id;
532 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
533 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
536 if (filter->fw_l2_filter_id != UINT64_MAX)
537 bnxt_hwrm_clear_l2_filter(bp, filter);
539 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
541 /* PMD does not support XDP and RoCE */
542 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
543 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
544 req.flags = rte_cpu_to_le_32(filter->flags);
546 enables = filter->enables |
547 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
548 req.dst_id = rte_cpu_to_le_16(dst_id);
551 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
552 memcpy(req.l2_addr, filter->l2_addr,
555 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
556 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
559 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
560 req.l2_ovlan = filter->l2_ovlan;
562 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
563 req.l2_ivlan = filter->l2_ivlan;
565 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
566 req.l2_ovlan_mask = filter->l2_ovlan_mask;
568 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
569 req.l2_ivlan_mask = filter->l2_ivlan_mask;
570 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
571 req.src_id = rte_cpu_to_le_32(filter->src_id);
572 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
573 req.src_type = filter->src_type;
574 if (filter->pri_hint) {
575 req.pri_hint = filter->pri_hint;
576 req.l2_filter_id_hint =
577 rte_cpu_to_le_64(filter->l2_filter_id_hint);
580 req.enables = rte_cpu_to_le_32(enables);
582 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
586 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
587 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
590 filter->l2_ref_cnt++;
595 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
597 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
598 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
605 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
608 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
611 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
612 if (ptp->tx_tstamp_en)
613 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
616 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
617 req.flags = rte_cpu_to_le_32(flags);
618 req.enables = rte_cpu_to_le_32
619 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
620 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
622 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
628 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
631 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
632 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
633 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
638 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
640 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
642 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
646 if (!BNXT_CHIP_P5(bp) &&
647 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
650 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
651 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
653 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
657 if (!BNXT_CHIP_P5(bp)) {
658 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
659 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
660 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
661 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
662 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
663 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
664 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
665 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
666 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
667 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
668 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
669 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
670 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
671 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
672 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
673 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
674 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
675 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
684 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
688 for (i = 0; i < bp->pf->max_vfs; i++) {
689 rte_free(bp->pf->vf_info[i].vlan_table);
690 bp->pf->vf_info[i].vlan_table = NULL;
691 rte_free(bp->pf->vf_info[i].vlan_as_table);
692 bp->pf->vf_info[i].vlan_as_table = NULL;
694 rte_free(bp->pf->vf_info);
695 bp->pf->vf_info = NULL;
698 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
701 struct hwrm_func_qcaps_input req = {.req_type = 0 };
702 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
703 uint16_t new_max_vfs;
707 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
709 req.fid = rte_cpu_to_le_16(0xffff);
711 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
715 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
716 flags = rte_le_to_cpu_32(resp->flags);
718 bp->pf->port_id = resp->port_id;
719 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
720 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
721 new_max_vfs = bp->pdev->max_vfs;
722 if (new_max_vfs != bp->pf->max_vfs) {
724 bnxt_hwrm_free_vf_info(bp);
725 bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
726 sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
727 if (bp->pf->vf_info == NULL) {
728 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
732 bp->pf->max_vfs = new_max_vfs;
733 for (i = 0; i < new_max_vfs; i++) {
734 bp->pf->vf_info[i].fid =
735 bp->pf->first_vf_id + i;
736 bp->pf->vf_info[i].vlan_table =
737 rte_zmalloc("VF VLAN table",
740 if (bp->pf->vf_info[i].vlan_table == NULL)
742 "Fail to alloc VLAN table for VF %d\n",
746 bp->pf->vf_info[i].vlan_table);
747 bp->pf->vf_info[i].vlan_as_table =
748 rte_zmalloc("VF VLAN AS table",
751 if (bp->pf->vf_info[i].vlan_as_table == NULL)
753 "Alloc VLAN AS table for VF %d fail\n",
757 bp->pf->vf_info[i].vlan_as_table);
758 STAILQ_INIT(&bp->pf->vf_info[i].filter);
763 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
764 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
765 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
766 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
768 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
770 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
771 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
772 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
773 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
774 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
775 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
776 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
777 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
778 bp->max_l2_ctx += bp->max_rx_em_flows;
779 /* TODO: For now, do not support VMDq/RFS on VFs. */
784 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
788 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
789 bp->max_l2_ctx, bp->max_vnics);
790 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
792 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
793 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
794 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
795 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
797 bnxt_hwrm_ptp_qcfg(bp);
801 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
802 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
804 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
805 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
806 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
809 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
810 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
812 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
813 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
815 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
816 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
823 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
827 rc = __bnxt_hwrm_func_qcaps(bp);
828 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
829 rc = bnxt_alloc_ctx_mem(bp);
834 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
835 * But the error can be ignored. Return success.
837 rc = bnxt_hwrm_func_resc_qcaps(bp);
839 bp->flags |= BNXT_FLAG_NEW_RM;
845 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
846 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
850 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
851 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
853 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
855 req.target_id = rte_cpu_to_le_16(0xffff);
857 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
861 flags = rte_le_to_cpu_32(resp->flags);
863 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
864 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
865 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
868 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
869 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
871 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
872 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
874 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
881 int bnxt_hwrm_func_reset(struct bnxt *bp)
884 struct hwrm_func_reset_input req = {.req_type = 0 };
885 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
887 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
889 req.enables = rte_cpu_to_le_32(0);
891 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
899 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
903 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
904 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
906 if (bp->flags & BNXT_FLAG_REGISTERED)
909 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
910 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
911 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
912 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
914 /* PFs and trusted VFs should indicate the support of the
915 * Master capability on non Stingray platform
917 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
918 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
920 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
921 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
922 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
923 req.ver_maj = RTE_VER_YEAR;
924 req.ver_min = RTE_VER_MONTH;
925 req.ver_upd = RTE_VER_MINOR;
928 req.enables |= rte_cpu_to_le_32(
929 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
930 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
931 RTE_MIN(sizeof(req.vf_req_fwd),
932 sizeof(bp->pf->vf_req_fwd)));
935 req.flags = rte_cpu_to_le_32(flags);
937 req.async_event_fwd[0] |=
938 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
939 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
940 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
941 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
942 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
943 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
944 req.async_event_fwd[0] |=
945 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
946 req.async_event_fwd[1] |=
947 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
948 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
950 req.async_event_fwd[1] |=
951 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
953 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
954 req.async_event_fwd[1] |=
955 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
957 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
961 flags = rte_le_to_cpu_32(resp->flags);
962 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
963 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
967 bp->flags |= BNXT_FLAG_REGISTERED;
972 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
974 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
977 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
980 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
985 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
986 struct hwrm_func_vf_cfg_input req = {0};
988 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
990 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
991 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
992 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
993 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
994 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
996 if (BNXT_HAS_RING_GRPS(bp)) {
997 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
998 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1001 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1002 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1003 AGG_RING_MULTIPLIER);
1004 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1005 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1007 BNXT_NUM_ASYNC_CPR(bp));
1008 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1009 if (bp->vf_resv_strategy ==
1010 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1011 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1012 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1013 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1014 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1015 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1016 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1017 } else if (bp->vf_resv_strategy ==
1018 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1019 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1020 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1024 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1025 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1026 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1027 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1028 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1029 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1031 if (test && BNXT_HAS_RING_GRPS(bp))
1032 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1034 req.flags = rte_cpu_to_le_32(flags);
1035 req.enables |= rte_cpu_to_le_32(enables);
1037 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1040 HWRM_CHECK_RESULT_SILENT();
1042 HWRM_CHECK_RESULT();
1048 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1051 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1052 struct hwrm_func_resource_qcaps_input req = {0};
1054 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1055 req.fid = rte_cpu_to_le_16(0xffff);
1057 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1059 HWRM_CHECK_RESULT_SILENT();
1061 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1062 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1063 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1064 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1065 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1066 /* func_resource_qcaps does not return max_rx_em_flows.
1067 * So use the value provided by func_qcaps.
1069 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1070 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1071 bp->max_l2_ctx += bp->max_rx_em_flows;
1072 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1073 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1074 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1075 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1076 if (bp->vf_resv_strategy >
1077 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1078 bp->vf_resv_strategy =
1079 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1085 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1088 struct hwrm_ver_get_input req = {.req_type = 0 };
1089 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1090 uint32_t fw_version;
1091 uint16_t max_resp_len;
1092 char type[RTE_MEMZONE_NAMESIZE];
1093 uint32_t dev_caps_cfg;
1095 bp->max_req_len = HWRM_MAX_REQ_LEN;
1096 bp->hwrm_cmd_timeout = timeout;
1097 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1099 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1100 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1101 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1103 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1105 if (bp->flags & BNXT_FLAG_FW_RESET)
1106 HWRM_CHECK_RESULT_SILENT();
1108 HWRM_CHECK_RESULT();
1110 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1111 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1112 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1113 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1114 resp->hwrm_fw_rsvd_8b);
1115 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1116 (resp->hwrm_fw_min_8b << 16) |
1117 (resp->hwrm_fw_bld_8b << 8) |
1118 resp->hwrm_fw_rsvd_8b;
1119 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1120 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1122 fw_version = resp->hwrm_intf_maj_8b << 16;
1123 fw_version |= resp->hwrm_intf_min_8b << 8;
1124 fw_version |= resp->hwrm_intf_upd_8b;
1125 bp->hwrm_spec_code = fw_version;
1127 /* def_req_timeout value is in milliseconds */
1128 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1129 /* convert timeout to usec */
1130 bp->hwrm_cmd_timeout *= 1000;
1131 if (!bp->hwrm_cmd_timeout)
1132 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1134 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1135 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1140 if (bp->max_req_len > resp->max_req_win_len) {
1141 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1145 bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1147 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1148 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1149 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1150 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1152 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1153 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1155 if (bp->max_resp_len != max_resp_len) {
1156 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1157 bp->pdev->addr.domain, bp->pdev->addr.bus,
1158 bp->pdev->addr.devid, bp->pdev->addr.function);
1160 rte_free(bp->hwrm_cmd_resp_addr);
1162 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1163 if (bp->hwrm_cmd_resp_addr == NULL) {
1167 bp->hwrm_cmd_resp_dma_addr =
1168 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1169 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1171 "Unable to map response buffer to physical memory.\n");
1175 bp->max_resp_len = max_resp_len;
1179 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1181 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1182 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1183 bp->flags |= BNXT_FLAG_SHORT_CMD;
1186 if (((dev_caps_cfg &
1187 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1189 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1190 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1191 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1192 bp->pdev->addr.domain, bp->pdev->addr.bus,
1193 bp->pdev->addr.devid, bp->pdev->addr.function);
1195 rte_free(bp->hwrm_short_cmd_req_addr);
1197 bp->hwrm_short_cmd_req_addr =
1198 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1199 if (bp->hwrm_short_cmd_req_addr == NULL) {
1203 bp->hwrm_short_cmd_req_dma_addr =
1204 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1205 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1206 rte_free(bp->hwrm_short_cmd_req_addr);
1208 "Unable to map buffer to physical memory.\n");
1214 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1215 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1216 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1219 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1220 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1222 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1223 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1224 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1228 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1229 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1230 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1238 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1241 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1242 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1244 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1247 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1250 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1252 HWRM_CHECK_RESULT();
1258 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1261 struct hwrm_port_phy_cfg_input req = {0};
1262 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1263 uint32_t enables = 0;
1265 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1267 if (conf->link_up) {
1268 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1269 if (bp->link_info->auto_mode && conf->link_speed) {
1270 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1271 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1274 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1276 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1277 * any auto mode, even "none".
1279 if (!conf->link_speed) {
1280 /* No speeds specified. Enable AutoNeg - all speeds */
1281 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1283 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1285 if (bp->link_info->link_signal_mode) {
1287 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1288 req.force_pam4_link_speed =
1289 rte_cpu_to_le_16(conf->link_speed);
1291 req.force_link_speed =
1292 rte_cpu_to_le_16(conf->link_speed);
1295 /* AutoNeg - Advertise speeds specified. */
1296 if (conf->auto_link_speed_mask &&
1297 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1299 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1300 req.auto_link_speed_mask =
1301 conf->auto_link_speed_mask;
1302 if (conf->auto_pam4_link_speeds) {
1304 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1305 req.auto_link_pam4_speed_mask =
1306 conf->auto_pam4_link_speeds;
1309 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1312 if (conf->auto_link_speed &&
1313 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1315 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1317 req.auto_duplex = conf->duplex;
1318 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1319 req.auto_pause = conf->auto_pause;
1320 req.force_pause = conf->force_pause;
1321 /* Set force_pause if there is no auto or if there is a force */
1322 if (req.auto_pause && !req.force_pause)
1323 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1325 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1327 req.enables = rte_cpu_to_le_32(enables);
1330 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1331 PMD_DRV_LOG(INFO, "Force Link Down\n");
1334 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1336 HWRM_CHECK_RESULT();
1339 PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1340 bp->eth_dev->data->port_id);
1344 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1345 struct bnxt_link_info *link_info)
1348 struct hwrm_port_phy_qcfg_input req = {0};
1349 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1351 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1353 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1355 HWRM_CHECK_RESULT();
1357 link_info->phy_link_status = resp->link;
1358 link_info->link_up =
1359 (link_info->phy_link_status ==
1360 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1361 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1362 link_info->duplex = resp->duplex_cfg;
1363 link_info->pause = resp->pause;
1364 link_info->auto_pause = resp->auto_pause;
1365 link_info->force_pause = resp->force_pause;
1366 link_info->auto_mode = resp->auto_mode;
1367 link_info->phy_type = resp->phy_type;
1368 link_info->media_type = resp->media_type;
1370 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1371 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1372 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1373 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1374 link_info->phy_ver[0] = resp->phy_maj;
1375 link_info->phy_ver[1] = resp->phy_min;
1376 link_info->phy_ver[2] = resp->phy_bld;
1377 link_info->link_signal_mode =
1378 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1379 link_info->force_pam4_link_speed =
1380 rte_le_to_cpu_16(resp->force_pam4_link_speed);
1381 link_info->support_pam4_speeds =
1382 rte_le_to_cpu_16(resp->support_pam4_speeds);
1383 link_info->auto_pam4_link_speeds =
1384 rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1387 PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1388 link_info->link_speed, link_info->auto_mode,
1389 link_info->auto_link_speed, link_info->auto_link_speed_mask,
1390 link_info->support_speeds, link_info->force_link_speed);
1391 PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1392 link_info->link_signal_mode,
1393 link_info->auto_pam4_link_speeds,
1394 link_info->support_pam4_speeds,
1395 link_info->force_pam4_link_speed);
1399 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1402 struct hwrm_port_phy_qcaps_input req = {0};
1403 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1404 struct bnxt_link_info *link_info = bp->link_info;
1406 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1409 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1411 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1413 HWRM_CHECK_RESULT();
1415 bp->port_cnt = resp->port_cnt;
1416 if (resp->supported_speeds_auto_mode)
1417 link_info->support_auto_speeds =
1418 rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1419 if (resp->supported_pam4_speeds_auto_mode)
1420 link_info->support_pam4_auto_speeds =
1421 rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1428 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1432 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1433 if (bp->tx_cos_queue[i].profile ==
1434 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1435 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1442 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1446 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1447 if (bp->tx_cos_queue[i].profile !=
1448 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1449 bp->tx_cos_queue[i].id !=
1450 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1451 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1457 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1460 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1461 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1462 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1466 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1468 req.flags = rte_cpu_to_le_32(dir);
1469 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1470 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1471 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1473 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1474 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1476 HWRM_CHECK_RESULT();
1478 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1479 GET_TX_QUEUE_INFO(0);
1480 GET_TX_QUEUE_INFO(1);
1481 GET_TX_QUEUE_INFO(2);
1482 GET_TX_QUEUE_INFO(3);
1483 GET_TX_QUEUE_INFO(4);
1484 GET_TX_QUEUE_INFO(5);
1485 GET_TX_QUEUE_INFO(6);
1486 GET_TX_QUEUE_INFO(7);
1488 GET_RX_QUEUE_INFO(0);
1489 GET_RX_QUEUE_INFO(1);
1490 GET_RX_QUEUE_INFO(2);
1491 GET_RX_QUEUE_INFO(3);
1492 GET_RX_QUEUE_INFO(4);
1493 GET_RX_QUEUE_INFO(5);
1494 GET_RX_QUEUE_INFO(6);
1495 GET_RX_QUEUE_INFO(7);
1500 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1503 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1504 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1508 /* iterate and find the COSq profile to use for Tx */
1509 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1510 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1511 if (bp->tx_cos_queue[i].id != 0xff)
1512 bp->tx_cosq_id[j++] =
1513 bp->tx_cos_queue[i].id;
1516 /* When CoS classification is disabled, for normal NIC
1517 * operations, ideally we should look to use LOSSY.
1518 * If not found, fallback to the first valid profile
1520 if (!bnxt_find_lossy_profile(bp))
1521 bnxt_find_first_valid_profile(bp);
1526 bp->max_tc = resp->max_configurable_queues;
1527 bp->max_lltc = resp->max_configurable_lossless_queues;
1528 if (bp->max_tc > BNXT_MAX_QUEUE)
1529 bp->max_tc = BNXT_MAX_QUEUE;
1530 bp->max_q = bp->max_tc;
1532 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1533 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1541 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1542 struct bnxt_ring *ring,
1543 uint32_t ring_type, uint32_t map_index,
1544 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1545 uint16_t tx_cosq_id)
1548 uint32_t enables = 0;
1549 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1550 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1551 struct rte_mempool *mb_pool;
1552 uint16_t rx_buf_size;
1554 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1556 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1557 req.fbo = rte_cpu_to_le_32(0);
1558 /* Association of ring index with doorbell index */
1559 req.logical_id = rte_cpu_to_le_16(map_index);
1560 req.length = rte_cpu_to_le_32(ring->ring_size);
1562 switch (ring_type) {
1563 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1564 req.ring_type = ring_type;
1565 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1566 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1567 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1568 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1570 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1572 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1573 req.ring_type = ring_type;
1574 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1575 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1576 if (BNXT_CHIP_P5(bp)) {
1577 mb_pool = bp->rx_queues[0]->mb_pool;
1578 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1579 RTE_PKTMBUF_HEADROOM;
1580 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1581 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1583 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1585 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1587 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1589 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1590 req.ring_type = ring_type;
1591 if (BNXT_HAS_NQ(bp)) {
1592 /* Association of cp ring with nq */
1593 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1595 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1597 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1599 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1600 req.ring_type = ring_type;
1601 req.page_size = BNXT_PAGE_SHFT;
1602 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1604 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1605 req.ring_type = ring_type;
1606 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1608 mb_pool = bp->rx_queues[0]->mb_pool;
1609 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1610 RTE_PKTMBUF_HEADROOM;
1611 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1612 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1614 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1615 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1616 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1617 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1620 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1625 req.enables = rte_cpu_to_le_32(enables);
1627 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1629 if (rc || resp->error_code) {
1630 if (rc == 0 && resp->error_code)
1631 rc = rte_le_to_cpu_16(resp->error_code);
1632 switch (ring_type) {
1633 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1635 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1638 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1640 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1643 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1645 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1649 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1651 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1654 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1656 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1660 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1666 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1671 int bnxt_hwrm_ring_free(struct bnxt *bp,
1672 struct bnxt_ring *ring, uint32_t ring_type)
1675 struct hwrm_ring_free_input req = {.req_type = 0 };
1676 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1678 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1680 req.ring_type = ring_type;
1681 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1683 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1685 if (rc || resp->error_code) {
1686 if (rc == 0 && resp->error_code)
1687 rc = rte_le_to_cpu_16(resp->error_code);
1690 switch (ring_type) {
1691 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1692 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1695 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1696 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1699 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1700 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1703 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1705 "hwrm_ring_free nq failed. rc:%d\n", rc);
1707 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1709 "hwrm_ring_free agg failed. rc:%d\n", rc);
1712 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1720 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1723 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1724 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1726 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1728 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1729 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1730 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1731 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1733 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1735 HWRM_CHECK_RESULT();
1737 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1744 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1747 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1748 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1750 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1752 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1754 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1756 HWRM_CHECK_RESULT();
1759 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1763 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1766 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1767 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1769 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1772 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1774 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1776 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1778 HWRM_CHECK_RESULT();
1784 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1785 unsigned int idx __rte_unused)
1788 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1789 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1791 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1793 req.update_period_ms = rte_cpu_to_le_32(0);
1795 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1797 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1799 HWRM_CHECK_RESULT();
1801 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1808 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1809 unsigned int idx __rte_unused)
1812 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1813 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1815 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1817 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1819 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1821 HWRM_CHECK_RESULT();
1827 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1830 struct hwrm_vnic_alloc_input req = { 0 };
1831 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1833 if (!BNXT_HAS_RING_GRPS(bp))
1834 goto skip_ring_grps;
1836 /* map ring groups to this vnic */
1837 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1838 vnic->start_grp_id, vnic->end_grp_id);
1839 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1840 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1842 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1843 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1844 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1845 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1848 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1849 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1851 if (vnic->func_default)
1853 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1854 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1856 HWRM_CHECK_RESULT();
1858 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1860 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1864 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1865 struct bnxt_vnic_info *vnic,
1866 struct bnxt_plcmodes_cfg *pmode)
1869 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1870 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1872 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1874 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1876 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1878 HWRM_CHECK_RESULT();
1880 pmode->flags = rte_le_to_cpu_32(resp->flags);
1881 /* dflt_vnic bit doesn't exist in the _cfg command */
1882 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1883 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1884 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1885 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1892 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1893 struct bnxt_vnic_info *vnic,
1894 struct bnxt_plcmodes_cfg *pmode)
1897 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1898 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1900 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1901 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1905 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1907 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1908 req.flags = rte_cpu_to_le_32(pmode->flags);
1909 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1910 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1911 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1912 req.enables = rte_cpu_to_le_32(
1913 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1914 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1915 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1918 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1920 HWRM_CHECK_RESULT();
1926 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1929 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1930 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1931 struct bnxt_plcmodes_cfg pmodes = { 0 };
1932 uint32_t ctx_enable_flag = 0;
1933 uint32_t enables = 0;
1935 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1936 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1940 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1944 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1946 if (BNXT_CHIP_P5(bp)) {
1947 int dflt_rxq = vnic->start_grp_id;
1948 struct bnxt_rx_ring_info *rxr;
1949 struct bnxt_cp_ring_info *cpr;
1950 struct bnxt_rx_queue *rxq;
1954 * The first active receive ring is used as the VNIC
1955 * default receive ring. If there are no active receive
1956 * rings (all corresponding receive queues are stopped),
1957 * the first receive ring is used.
1959 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1960 rxq = bp->eth_dev->data->rx_queues[i];
1961 if (rxq->rx_started) {
1967 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1971 req.default_rx_ring_id =
1972 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1973 req.default_cmpl_ring_id =
1974 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1975 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1976 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1977 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
1978 enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
1979 req.rx_csum_v2_mode =
1980 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
1985 /* Only RSS support for now TBD: COS & LB */
1986 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1987 if (vnic->lb_rule != 0xffff)
1988 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1989 if (vnic->cos_rule != 0xffff)
1990 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1991 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1992 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1993 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1995 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1996 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1997 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2000 enables |= ctx_enable_flag;
2001 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2002 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2003 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2004 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2007 req.enables = rte_cpu_to_le_32(enables);
2008 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2009 req.mru = rte_cpu_to_le_16(vnic->mru);
2010 /* Configure default VNIC only once. */
2011 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2013 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2014 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2016 if (vnic->vlan_strip)
2018 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2021 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2022 if (vnic->rss_dflt_cr)
2023 req.flags |= rte_cpu_to_le_32(
2024 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2026 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2028 HWRM_CHECK_RESULT();
2031 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2036 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2040 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2041 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2043 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2044 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2047 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2050 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2051 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2052 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2054 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2056 HWRM_CHECK_RESULT();
2058 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2059 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2060 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2061 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2062 vnic->mru = rte_le_to_cpu_16(resp->mru);
2063 vnic->func_default = rte_le_to_cpu_32(
2064 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2065 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2066 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2067 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2068 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2069 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2070 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2077 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2078 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2082 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2083 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2084 bp->hwrm_cmd_resp_addr;
2086 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2088 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2089 HWRM_CHECK_RESULT();
2091 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2092 if (!BNXT_HAS_RING_GRPS(bp))
2093 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2094 else if (ctx_idx == 0)
2095 vnic->rss_rule = ctx_id;
2103 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2104 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2107 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2108 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2109 bp->hwrm_cmd_resp_addr;
2111 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2112 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2115 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2117 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2119 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2121 HWRM_CHECK_RESULT();
2127 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2131 if (BNXT_CHIP_P5(bp)) {
2134 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2135 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2137 vnic->fw_grp_ids[j]);
2138 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2140 vnic->num_lb_ctxts = 0;
2142 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2143 vnic->rss_rule = INVALID_HW_RING_ID;
2149 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2152 struct hwrm_vnic_free_input req = {.req_type = 0 };
2153 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2155 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2156 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2160 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2162 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2164 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2166 HWRM_CHECK_RESULT();
2169 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2170 /* Configure default VNIC again if necessary. */
2171 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2172 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2178 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2182 int nr_ctxs = vnic->num_lb_ctxts;
2183 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2184 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2186 for (i = 0; i < nr_ctxs; i++) {
2187 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2189 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2190 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2191 req.hash_mode_flags = vnic->hash_mode;
2193 req.hash_key_tbl_addr =
2194 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2196 req.ring_grp_tbl_addr =
2197 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2198 i * HW_HASH_INDEX_SIZE);
2199 req.ring_table_pair_index = i;
2200 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2202 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2205 HWRM_CHECK_RESULT();
2212 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2213 struct bnxt_vnic_info *vnic)
2216 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2217 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2219 if (!vnic->rss_table)
2222 if (BNXT_CHIP_P5(bp))
2223 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2225 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2227 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2228 req.hash_mode_flags = vnic->hash_mode;
2230 req.ring_grp_tbl_addr =
2231 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2232 req.hash_key_tbl_addr =
2233 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2234 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2235 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2237 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2239 HWRM_CHECK_RESULT();
2245 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2246 struct bnxt_vnic_info *vnic)
2249 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2250 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2253 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2254 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2258 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2260 req.flags = rte_cpu_to_le_32(
2261 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2263 req.enables = rte_cpu_to_le_32(
2264 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2266 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2267 size -= RTE_PKTMBUF_HEADROOM;
2268 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2270 req.jumbo_thresh = rte_cpu_to_le_16(size);
2271 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2273 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2275 HWRM_CHECK_RESULT();
2281 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2282 struct bnxt_vnic_info *vnic, bool enable)
2285 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2286 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2288 if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2290 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2294 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2295 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2299 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2302 req.enables = rte_cpu_to_le_32(
2303 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2304 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2305 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2306 req.flags = rte_cpu_to_le_32(
2307 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2308 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2309 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2310 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2311 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2312 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2313 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2314 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2315 req.min_agg_len = rte_cpu_to_le_32(512);
2317 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2319 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2321 HWRM_CHECK_RESULT();
2327 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2329 struct hwrm_func_cfg_input req = {0};
2330 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2333 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2334 req.enables = rte_cpu_to_le_32(
2335 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2336 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2337 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2339 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2341 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2342 HWRM_CHECK_RESULT();
2345 bp->pf->vf_info[vf].random_mac = false;
2350 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2354 struct hwrm_func_qstats_input req = {.req_type = 0};
2355 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2357 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2359 req.fid = rte_cpu_to_le_16(fid);
2361 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2363 HWRM_CHECK_RESULT();
2366 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2373 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2374 struct rte_eth_stats *stats,
2375 struct hwrm_func_qstats_output *func_qstats)
2378 struct hwrm_func_qstats_input req = {.req_type = 0};
2379 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2381 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2383 req.fid = rte_cpu_to_le_16(fid);
2385 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2387 HWRM_CHECK_RESULT();
2389 memcpy(func_qstats, resp,
2390 sizeof(struct hwrm_func_qstats_output));
2395 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2396 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2397 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2398 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2399 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2400 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2402 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2403 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2404 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2405 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2406 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2407 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2409 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2410 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2411 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2419 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2422 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2423 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2425 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2427 req.fid = rte_cpu_to_le_16(fid);
2429 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2431 HWRM_CHECK_RESULT();
2437 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2442 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2443 struct bnxt_tx_queue *txq;
2444 struct bnxt_rx_queue *rxq;
2445 struct bnxt_cp_ring_info *cpr;
2447 if (i >= bp->rx_cp_nr_rings) {
2448 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2451 rxq = bp->rx_queues[i];
2455 rc = bnxt_hwrm_stat_clear(bp, cpr);
2463 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2467 struct bnxt_cp_ring_info *cpr;
2469 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2471 if (i >= bp->rx_cp_nr_rings) {
2472 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2474 cpr = bp->rx_queues[i]->cp_ring;
2475 if (BNXT_HAS_RING_GRPS(bp))
2476 bp->grp_info[i].fw_stats_ctx = -1;
2478 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2479 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2480 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2488 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2493 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2494 struct bnxt_tx_queue *txq;
2495 struct bnxt_rx_queue *rxq;
2496 struct bnxt_cp_ring_info *cpr;
2498 if (i >= bp->rx_cp_nr_rings) {
2499 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2502 rxq = bp->rx_queues[i];
2506 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2515 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2520 if (!BNXT_HAS_RING_GRPS(bp))
2523 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2525 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2528 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2536 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2538 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2540 bnxt_hwrm_ring_free(bp, cp_ring,
2541 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2542 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2543 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2544 sizeof(*cpr->cp_desc_ring));
2545 cpr->cp_raw_cons = 0;
2549 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2551 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2553 bnxt_hwrm_ring_free(bp, cp_ring,
2554 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2555 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2556 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2557 sizeof(*cpr->cp_desc_ring));
2558 cpr->cp_raw_cons = 0;
2562 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2564 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2565 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2566 struct bnxt_ring *ring = rxr->rx_ring_struct;
2567 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2569 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2570 bnxt_hwrm_ring_free(bp, ring,
2571 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2572 ring->fw_ring_id = INVALID_HW_RING_ID;
2573 if (BNXT_HAS_RING_GRPS(bp))
2574 bp->grp_info[queue_index].rx_fw_ring_id =
2577 ring = rxr->ag_ring_struct;
2578 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2579 bnxt_hwrm_ring_free(bp, ring,
2581 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2582 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2583 if (BNXT_HAS_RING_GRPS(bp))
2584 bp->grp_info[queue_index].ag_fw_ring_id =
2587 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2588 bnxt_free_cp_ring(bp, cpr);
2590 if (BNXT_HAS_RING_GRPS(bp))
2591 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2595 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2599 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2600 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2601 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2602 struct bnxt_ring *ring = txr->tx_ring_struct;
2603 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2605 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2606 bnxt_hwrm_ring_free(bp, ring,
2607 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2608 ring->fw_ring_id = INVALID_HW_RING_ID;
2609 memset(txr->tx_desc_ring, 0,
2610 txr->tx_ring_struct->ring_size *
2611 sizeof(*txr->tx_desc_ring));
2612 memset(txr->tx_buf_ring, 0,
2613 txr->tx_ring_struct->ring_size *
2614 sizeof(*txr->tx_buf_ring));
2615 txr->tx_raw_prod = 0;
2616 txr->tx_raw_cons = 0;
2618 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2619 bnxt_free_cp_ring(bp, cpr);
2620 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2624 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2625 bnxt_free_hwrm_rx_ring(bp, i);
2630 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2635 if (!BNXT_HAS_RING_GRPS(bp))
2638 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2639 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2647 * HWRM utility functions
2650 void bnxt_free_hwrm_resources(struct bnxt *bp)
2652 /* Release memzone */
2653 rte_free(bp->hwrm_cmd_resp_addr);
2654 rte_free(bp->hwrm_short_cmd_req_addr);
2655 bp->hwrm_cmd_resp_addr = NULL;
2656 bp->hwrm_short_cmd_req_addr = NULL;
2657 bp->hwrm_cmd_resp_dma_addr = 0;
2658 bp->hwrm_short_cmd_req_dma_addr = 0;
2661 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2663 struct rte_pci_device *pdev = bp->pdev;
2664 char type[RTE_MEMZONE_NAMESIZE];
2666 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2667 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2668 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2669 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2670 if (bp->hwrm_cmd_resp_addr == NULL)
2672 bp->hwrm_cmd_resp_dma_addr =
2673 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2674 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2676 "unable to map response address to physical memory\n");
2679 rte_spinlock_init(&bp->hwrm_lock);
2685 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2689 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2690 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2693 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2694 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2699 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2704 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2706 struct bnxt_filter_info *filter;
2709 STAILQ_FOREACH(filter, &vnic->filter, next) {
2710 rc = bnxt_clear_one_vnic_filter(bp, filter);
2711 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2712 bnxt_free_filter(bp, filter);
2718 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2720 struct bnxt_filter_info *filter;
2721 struct rte_flow *flow;
2724 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2725 flow = STAILQ_FIRST(&vnic->flow_list);
2726 filter = flow->filter;
2727 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2728 rc = bnxt_clear_one_vnic_filter(bp, filter);
2730 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2736 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2738 struct bnxt_filter_info *filter;
2741 STAILQ_FOREACH(filter, &vnic->filter, next) {
2742 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2743 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2745 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2746 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2749 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2758 bnxt_free_tunnel_ports(struct bnxt *bp)
2760 if (bp->vxlan_port_cnt)
2761 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2762 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2764 if (bp->geneve_port_cnt)
2765 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2766 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2769 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2773 if (bp->vnic_info == NULL)
2777 * Cleanup VNICs in reverse order, to make sure the L2 filter
2778 * from vnic0 is last to be cleaned up.
2780 for (i = bp->max_vnics - 1; i >= 0; i--) {
2781 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2783 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2786 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2788 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2790 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2792 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2794 bnxt_hwrm_vnic_free(bp, vnic);
2796 rte_free(vnic->fw_grp_ids);
2798 /* Ring resources */
2799 bnxt_free_all_hwrm_rings(bp);
2800 bnxt_free_all_hwrm_ring_grps(bp);
2801 bnxt_free_all_hwrm_stat_ctxs(bp);
2802 bnxt_free_tunnel_ports(bp);
2805 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2807 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2809 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2810 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2812 switch (conf_link_speed) {
2813 case ETH_LINK_SPEED_10M_HD:
2814 case ETH_LINK_SPEED_100M_HD:
2816 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2818 return hw_link_duplex;
2821 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2826 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2829 uint16_t eth_link_speed = 0;
2831 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2832 return ETH_LINK_SPEED_AUTONEG;
2834 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2835 case ETH_LINK_SPEED_100M:
2836 case ETH_LINK_SPEED_100M_HD:
2839 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2841 case ETH_LINK_SPEED_1G:
2843 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2845 case ETH_LINK_SPEED_2_5G:
2847 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2849 case ETH_LINK_SPEED_10G:
2851 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2853 case ETH_LINK_SPEED_20G:
2855 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2857 case ETH_LINK_SPEED_25G:
2859 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2861 case ETH_LINK_SPEED_40G:
2863 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2865 case ETH_LINK_SPEED_50G:
2866 eth_link_speed = pam4_link ?
2867 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
2868 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2870 case ETH_LINK_SPEED_100G:
2871 eth_link_speed = pam4_link ?
2872 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
2873 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2875 case ETH_LINK_SPEED_200G:
2877 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2881 "Unsupported link speed %d; default to AUTO\n",
2885 return eth_link_speed;
2888 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2889 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2890 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2891 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2892 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2894 static int bnxt_validate_link_speed(struct bnxt *bp)
2896 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2897 uint16_t port_id = bp->eth_dev->data->port_id;
2898 uint32_t link_speed_capa;
2901 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2904 link_speed_capa = bnxt_get_speed_capabilities(bp);
2906 if (link_speed & ETH_LINK_SPEED_FIXED) {
2907 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2909 if (one_speed & (one_speed - 1)) {
2911 "Invalid advertised speeds (%u) for port %u\n",
2912 link_speed, port_id);
2915 if ((one_speed & link_speed_capa) != one_speed) {
2917 "Unsupported advertised speed (%u) for port %u\n",
2918 link_speed, port_id);
2922 if (!(link_speed & link_speed_capa)) {
2924 "Unsupported advertised speeds (%u) for port %u\n",
2925 link_speed, port_id);
2933 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2937 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2938 if (bp->link_info->support_speeds)
2939 return bp->link_info->support_speeds;
2940 link_speed = BNXT_SUPPORTED_SPEEDS;
2943 if (link_speed & ETH_LINK_SPEED_100M)
2944 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2945 if (link_speed & ETH_LINK_SPEED_100M_HD)
2946 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2947 if (link_speed & ETH_LINK_SPEED_1G)
2948 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2949 if (link_speed & ETH_LINK_SPEED_2_5G)
2950 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2951 if (link_speed & ETH_LINK_SPEED_10G)
2952 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2953 if (link_speed & ETH_LINK_SPEED_20G)
2954 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2955 if (link_speed & ETH_LINK_SPEED_25G)
2956 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2957 if (link_speed & ETH_LINK_SPEED_40G)
2958 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2959 if (link_speed & ETH_LINK_SPEED_50G)
2960 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2961 if (link_speed & ETH_LINK_SPEED_100G)
2962 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2963 if (link_speed & ETH_LINK_SPEED_200G)
2964 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2968 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2970 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2972 switch (hw_link_speed) {
2973 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2974 eth_link_speed = ETH_SPEED_NUM_100M;
2976 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2977 eth_link_speed = ETH_SPEED_NUM_1G;
2979 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2980 eth_link_speed = ETH_SPEED_NUM_2_5G;
2982 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2983 eth_link_speed = ETH_SPEED_NUM_10G;
2985 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2986 eth_link_speed = ETH_SPEED_NUM_20G;
2988 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2989 eth_link_speed = ETH_SPEED_NUM_25G;
2991 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2992 eth_link_speed = ETH_SPEED_NUM_40G;
2994 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2995 eth_link_speed = ETH_SPEED_NUM_50G;
2997 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2998 eth_link_speed = ETH_SPEED_NUM_100G;
3000 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3001 eth_link_speed = ETH_SPEED_NUM_200G;
3003 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3005 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3009 return eth_link_speed;
3012 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3014 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3016 switch (hw_link_duplex) {
3017 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3018 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3020 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3022 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3023 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3026 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3030 return eth_link_duplex;
3033 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3036 struct bnxt_link_info *link_info = bp->link_info;
3038 rc = bnxt_hwrm_port_phy_qcaps(bp);
3040 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3042 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3044 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3048 if (link_info->link_speed)
3050 bnxt_parse_hw_link_speed(link_info->link_speed);
3052 link->link_speed = ETH_SPEED_NUM_NONE;
3053 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3054 link->link_status = link_info->link_up;
3055 link->link_autoneg = link_info->auto_mode ==
3056 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3057 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3062 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3065 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3066 struct bnxt_link_info link_req;
3067 uint16_t speed, autoneg;
3069 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3072 rc = bnxt_validate_link_speed(bp);
3076 memset(&link_req, 0, sizeof(link_req));
3077 link_req.link_up = link_up;
3081 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3082 if (BNXT_CHIP_P5(bp) &&
3083 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3084 /* 40G is not supported as part of media auto detect.
3085 * The speed should be forced and autoneg disabled
3086 * to configure 40G speed.
3088 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3092 /* No auto speeds and no auto_pam4_link. Disable autoneg */
3093 if (bp->link_info->auto_link_speed == 0 &&
3094 bp->link_info->link_signal_mode &&
3095 bp->link_info->auto_pam4_link_speeds == 0)
3098 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3099 bp->link_info->link_signal_mode);
3100 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3101 /* Autoneg can be done only when the FW allows.
3102 * When user configures fixed speed of 40G and later changes to
3103 * any other speed, auto_link_speed/force_link_speed is still set
3104 * to 40G until link comes up at new speed.
3107 !(!BNXT_CHIP_P5(bp) &&
3108 (bp->link_info->auto_link_speed ||
3109 bp->link_info->force_link_speed))) {
3110 link_req.phy_flags |=
3111 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3112 link_req.auto_link_speed_mask =
3113 bnxt_parse_eth_link_speed_mask(bp,
3114 dev_conf->link_speeds);
3116 if (bp->link_info->phy_type ==
3117 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3118 bp->link_info->phy_type ==
3119 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3120 bp->link_info->media_type ==
3121 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3122 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3126 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3127 /* If user wants a particular speed try that first. */
3129 link_req.link_speed = speed;
3130 else if (bp->link_info->force_pam4_link_speed)
3131 link_req.link_speed =
3132 bp->link_info->force_pam4_link_speed;
3133 else if (bp->link_info->auto_pam4_link_speeds)
3134 link_req.link_speed =
3135 bp->link_info->auto_pam4_link_speeds;
3136 else if (bp->link_info->support_pam4_speeds)
3137 link_req.link_speed =
3138 bp->link_info->support_pam4_speeds;
3139 else if (bp->link_info->force_link_speed)
3140 link_req.link_speed = bp->link_info->force_link_speed;
3142 link_req.link_speed = bp->link_info->auto_link_speed;
3143 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3144 * zero. Use the auto_link_speed.
3146 if (bp->link_info->auto_link_speed != 0 &&
3147 bp->link_info->auto_pam4_link_speeds == 0)
3148 link_req.link_speed = bp->link_info->auto_link_speed;
3150 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3151 link_req.auto_pause = bp->link_info->auto_pause;
3152 link_req.force_pause = bp->link_info->force_pause;
3155 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3158 "Set link config failed with rc %d\n", rc);
3166 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3168 struct hwrm_func_qcfg_input req = {0};
3169 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3172 bp->func_svif = BNXT_SVIF_INVALID;
3175 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3176 req.fid = rte_cpu_to_le_16(0xffff);
3178 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3180 HWRM_CHECK_RESULT();
3182 /* Hard Coded.. 0xfff VLAN ID mask */
3183 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3185 svif_info = rte_le_to_cpu_16(resp->svif_info);
3186 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3187 bp->func_svif = svif_info &
3188 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3190 flags = rte_le_to_cpu_16(resp->flags);
3191 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3192 bp->flags |= BNXT_FLAG_MULTI_HOST;
3195 !BNXT_VF_IS_TRUSTED(bp) &&
3196 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3197 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3198 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3199 } else if (BNXT_VF(bp) &&
3200 BNXT_VF_IS_TRUSTED(bp) &&
3201 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3202 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3203 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3207 *mtu = rte_le_to_cpu_16(resp->mtu);
3209 switch (resp->port_partition_type) {
3210 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3211 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3212 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3214 bp->flags |= BNXT_FLAG_NPAR_PF;
3217 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3221 bp->legacy_db_size =
3222 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3229 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3231 struct hwrm_func_qcfg_input req = {0};
3232 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3235 if (!BNXT_VF_IS_TRUSTED(bp))
3241 bp->parent->fid = BNXT_PF_FID_INVALID;
3243 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3245 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3247 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3249 HWRM_CHECK_RESULT();
3251 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3252 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3253 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3254 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3256 /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3257 if (bp->parent->vnic == 0) {
3258 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3259 /* Use hard-coded values appropriate for current Wh+ fw. */
3260 if (bp->parent->fid == 2)
3261 bp->parent->vnic = 0x100;
3263 bp->parent->vnic = 1;
3271 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3272 uint16_t *vnic_id, uint16_t *svif)
3274 struct hwrm_func_qcfg_input req = {0};
3275 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3279 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3280 req.fid = rte_cpu_to_le_16(fid);
3282 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3284 HWRM_CHECK_RESULT();
3287 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3289 svif_info = rte_le_to_cpu_16(resp->svif_info);
3290 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3291 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3298 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3300 struct hwrm_port_mac_qcfg_input req = {0};
3301 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3302 uint16_t port_svif_info;
3305 bp->port_svif = BNXT_SVIF_INVALID;
3307 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3310 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3312 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3314 HWRM_CHECK_RESULT_SILENT();
3316 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3317 if (port_svif_info &
3318 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3319 bp->port_svif = port_svif_info &
3320 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3327 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3328 struct bnxt_pf_resource_info *pf_resc)
3330 struct hwrm_func_cfg_input req = {0};
3331 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3335 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3336 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3337 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3338 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3339 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3340 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3341 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3342 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3343 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3345 if (BNXT_HAS_RING_GRPS(bp)) {
3346 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3347 req.num_hw_ring_grps =
3348 rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3349 } else if (BNXT_HAS_NQ(bp)) {
3350 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3351 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3354 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3355 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3356 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3357 req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3358 req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3359 req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3360 req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3361 req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3362 req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3363 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3364 req.fid = rte_cpu_to_le_16(0xffff);
3365 req.enables = rte_cpu_to_le_32(enables);
3367 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3369 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3371 HWRM_CHECK_RESULT();
3377 /* min values are the guaranteed resources and max values are subject
3378 * to availability. The strategy for now is to keep both min & max
3382 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3383 struct hwrm_func_vf_resource_cfg_input *req,
3386 req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3388 req->min_rsscos_ctx = req->max_rsscos_ctx;
3389 req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3390 req->min_stat_ctx = req->max_stat_ctx;
3391 req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3393 req->min_cmpl_rings = req->max_cmpl_rings;
3394 req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3395 req->min_tx_rings = req->max_tx_rings;
3396 req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3397 req->min_rx_rings = req->max_rx_rings;
3398 req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3399 req->min_l2_ctxs = req->max_l2_ctxs;
3400 /* TODO: For now, do not support VMDq/RFS on VFs. */
3401 req->max_vnics = rte_cpu_to_le_16(1);
3402 req->min_vnics = req->max_vnics;
3403 req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3405 req->min_hw_ring_grps = req->max_hw_ring_grps;
3407 rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3411 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3412 struct hwrm_func_cfg_input *req,
3415 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3416 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3417 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3418 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3419 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3420 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3421 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3422 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3423 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3424 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3426 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3427 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3429 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3430 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3432 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3433 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3435 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3436 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3437 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3438 /* TODO: For now, do not support VMDq/RFS on VFs. */
3439 req->num_vnics = rte_cpu_to_le_16(1);
3440 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3444 /* Update the port wide resource values based on how many resources
3445 * got allocated to the VF.
3447 static int bnxt_update_max_resources(struct bnxt *bp,
3450 struct hwrm_func_qcfg_input req = {0};
3451 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3454 /* Get the actual allocated values now */
3455 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3456 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3457 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3458 HWRM_CHECK_RESULT();
3460 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3461 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3462 bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3463 bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3464 bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3465 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3466 bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3473 /* Update the PF resource values based on how many resources
3474 * got allocated to it.
3476 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3478 struct hwrm_func_qcfg_input req = {0};
3479 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3482 /* Get the actual allocated values now */
3483 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3484 req.fid = rte_cpu_to_le_16(0xffff);
3485 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3486 HWRM_CHECK_RESULT();
3488 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3489 bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3490 bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3491 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3492 bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3493 bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3494 bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3495 bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3502 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3504 struct hwrm_func_qcfg_input req = {0};
3505 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3508 /* Check for zero MAC address */
3509 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3510 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3511 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3512 HWRM_CHECK_RESULT();
3513 rc = rte_le_to_cpu_16(resp->vlan);
3520 static int bnxt_query_pf_resources(struct bnxt *bp,
3521 struct bnxt_pf_resource_info *pf_resc)
3523 struct hwrm_func_qcfg_input req = {0};
3524 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3527 /* And copy the allocated numbers into the pf struct */
3528 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3529 req.fid = rte_cpu_to_le_16(0xffff);
3530 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3531 HWRM_CHECK_RESULT();
3533 pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3534 pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3535 pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3536 pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3537 pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3538 pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3539 pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3540 bp->pf->evb_mode = resp->evb_mode;
3548 bnxt_calculate_pf_resources(struct bnxt *bp,
3549 struct bnxt_pf_resource_info *pf_resc,
3553 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3554 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3555 pf_resc->num_cp_rings = bp->max_cp_rings;
3556 pf_resc->num_tx_rings = bp->max_tx_rings;
3557 pf_resc->num_rx_rings = bp->max_rx_rings;
3558 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3559 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3564 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3565 bp->max_rsscos_ctx % (num_vfs + 1);
3566 pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3567 bp->max_stat_ctx % (num_vfs + 1);
3568 pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3569 bp->max_cp_rings % (num_vfs + 1);
3570 pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3571 bp->max_tx_rings % (num_vfs + 1);
3572 pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3573 bp->max_rx_rings % (num_vfs + 1);
3574 pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3575 bp->max_l2_ctx % (num_vfs + 1);
3576 pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3577 bp->max_ring_grps % (num_vfs + 1);
3580 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3582 struct bnxt_pf_resource_info pf_resc = { 0 };
3586 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3590 rc = bnxt_hwrm_func_qcaps(bp);
3594 bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3596 bp->pf->func_cfg_flags &=
3597 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3598 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3599 bp->pf->func_cfg_flags |=
3600 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3602 rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3606 rc = bnxt_update_max_resources_pf_only(bp);
3612 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3614 size_t req_buf_sz, sz;
3617 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3618 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3619 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3620 if (bp->pf->vf_req_buf == NULL) {
3624 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3625 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3627 for (i = 0; i < num_vfs; i++)
3628 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3629 (i * HWRM_MAX_REQ_LEN);
3631 rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3633 rte_free(bp->pf->vf_req_buf);
3639 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3641 struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3642 struct hwrm_func_vf_resource_cfg_input req = {0};
3645 bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3646 bp->pf->active_vfs = 0;
3647 for (i = 0; i < num_vfs; i++) {
3648 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3649 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3650 rc = bnxt_hwrm_send_message(bp,
3654 if (rc || resp->error_code) {
3656 "Failed to initialize VF %d\n", i);
3658 "Not all VFs available. (%d, %d)\n",
3659 rc, resp->error_code);
3662 /* If the first VF configuration itself fails,
3663 * unregister the vf_fwd_request buffer.
3666 bnxt_hwrm_func_buf_unrgtr(bp);
3671 /* Update the max resource values based on the resource values
3672 * allocated to the VF.
3674 bnxt_update_max_resources(bp, i);
3675 bp->pf->active_vfs++;
3676 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3683 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3685 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3686 struct hwrm_func_cfg_input req = {0};
3689 bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3691 bp->pf->active_vfs = 0;
3692 for (i = 0; i < num_vfs; i++) {
3693 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3694 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3695 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3696 rc = bnxt_hwrm_send_message(bp,
3701 /* Clear enable flag for next pass */
3702 req.enables &= ~rte_cpu_to_le_32(
3703 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3705 if (rc || resp->error_code) {
3707 "Failed to initialize VF %d\n", i);
3709 "Not all VFs available. (%d, %d)\n",
3710 rc, resp->error_code);
3713 /* If the first VF configuration itself fails,
3714 * unregister the vf_fwd_request buffer.
3717 bnxt_hwrm_func_buf_unrgtr(bp);
3723 /* Update the max resource values based on the resource values
3724 * allocated to the VF.
3726 bnxt_update_max_resources(bp, i);
3727 bp->pf->active_vfs++;
3728 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3735 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3737 if (bp->flags & BNXT_FLAG_NEW_RM)
3738 bnxt_process_vf_resc_config_new(bp, num_vfs);
3740 bnxt_process_vf_resc_config_old(bp, num_vfs);
3744 bnxt_update_pf_resources(struct bnxt *bp,
3745 struct bnxt_pf_resource_info *pf_resc)
3747 bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3748 bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3749 bp->max_cp_rings = pf_resc->num_cp_rings;
3750 bp->max_tx_rings = pf_resc->num_tx_rings;
3751 bp->max_rx_rings = pf_resc->num_rx_rings;
3752 bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3756 bnxt_configure_pf_resources(struct bnxt *bp,
3757 struct bnxt_pf_resource_info *pf_resc)
3760 * We're using STD_TX_RING_MODE here which will limit the TX
3761 * rings. This will allow QoS to function properly. Not setting this
3762 * will cause PF rings to break bandwidth settings.
3764 bp->pf->func_cfg_flags &=
3765 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3766 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3767 bp->pf->func_cfg_flags |=
3768 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3769 return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3772 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3774 struct bnxt_pf_resource_info pf_resc = { 0 };
3778 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3782 rc = bnxt_hwrm_func_qcaps(bp);
3786 bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3788 rc = bnxt_configure_pf_resources(bp, &pf_resc);
3792 rc = bnxt_query_pf_resources(bp, &pf_resc);
3797 * Now, create and register a buffer to hold forwarded VF requests
3799 rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3803 bnxt_configure_vf_resources(bp, num_vfs);
3805 bnxt_update_pf_resources(bp, &pf_resc);
3810 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3812 struct hwrm_func_cfg_input req = {0};
3813 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3816 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3818 req.fid = rte_cpu_to_le_16(0xffff);
3819 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3820 req.evb_mode = bp->pf->evb_mode;
3822 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3823 HWRM_CHECK_RESULT();
3829 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3830 uint8_t tunnel_type)
3832 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3833 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3836 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3837 req.tunnel_type = tunnel_type;
3838 req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3839 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3840 HWRM_CHECK_RESULT();
3842 switch (tunnel_type) {
3843 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3844 bp->vxlan_fw_dst_port_id =
3845 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3846 bp->vxlan_port = port;
3848 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3849 bp->geneve_fw_dst_port_id =
3850 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3851 bp->geneve_port = port;
3862 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3863 uint8_t tunnel_type)
3865 struct hwrm_tunnel_dst_port_free_input req = {0};
3866 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3869 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3871 req.tunnel_type = tunnel_type;
3872 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3873 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3875 HWRM_CHECK_RESULT();
3879 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
3881 bp->vxlan_port_cnt = 0;
3885 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
3886 bp->geneve_port = 0;
3887 bp->geneve_port_cnt = 0;
3893 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3896 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3897 struct hwrm_func_cfg_input req = {0};
3900 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3902 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3903 req.flags = rte_cpu_to_le_32(flags);
3904 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3906 HWRM_CHECK_RESULT();
3912 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3914 uint32_t *flag = flagp;
3916 vnic->flags = *flag;
3919 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3921 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3924 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
3926 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3927 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3930 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3932 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3933 req.req_buf_page_size =
3934 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
3935 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3936 req.req_buf_page_addr0 =
3937 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3938 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3940 "unable to map buffer address to physical memory\n");
3945 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3947 HWRM_CHECK_RESULT();
3953 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3956 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3957 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3959 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3962 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3964 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3966 HWRM_CHECK_RESULT();
3972 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3974 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3975 struct hwrm_func_cfg_input req = {0};
3978 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3980 req.fid = rte_cpu_to_le_16(0xffff);
3981 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3982 req.enables = rte_cpu_to_le_32(
3983 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3984 req.async_event_cr = rte_cpu_to_le_16(
3985 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3986 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3988 HWRM_CHECK_RESULT();
3994 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3996 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3997 struct hwrm_func_vf_cfg_input req = {0};
4000 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4002 req.enables = rte_cpu_to_le_32(
4003 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4004 req.async_event_cr = rte_cpu_to_le_16(
4005 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4006 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4008 HWRM_CHECK_RESULT();
4014 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4016 struct hwrm_func_cfg_input req = {0};
4017 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4018 uint16_t dflt_vlan, fid;
4019 uint32_t func_cfg_flags;
4022 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4025 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4026 fid = bp->pf->vf_info[vf].fid;
4027 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4029 fid = rte_cpu_to_le_16(0xffff);
4030 func_cfg_flags = bp->pf->func_cfg_flags;
4031 dflt_vlan = bp->vlan;
4034 req.flags = rte_cpu_to_le_32(func_cfg_flags);
4035 req.fid = rte_cpu_to_le_16(fid);
4036 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4037 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4039 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4041 HWRM_CHECK_RESULT();
4047 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4048 uint16_t max_bw, uint16_t enables)
4050 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4051 struct hwrm_func_cfg_input req = {0};
4054 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4056 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4057 req.enables |= rte_cpu_to_le_32(enables);
4058 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4059 req.max_bw = rte_cpu_to_le_32(max_bw);
4060 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4062 HWRM_CHECK_RESULT();
4068 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4070 struct hwrm_func_cfg_input req = {0};
4071 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4074 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4076 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4077 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4078 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4079 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4081 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4083 HWRM_CHECK_RESULT();
4089 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4094 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4096 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4101 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4102 void *encaped, size_t ec_size)
4105 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4106 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4108 if (ec_size > sizeof(req.encap_request))
4111 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4113 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4114 memcpy(req.encap_request, encaped, ec_size);
4116 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4118 HWRM_CHECK_RESULT();
4124 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4125 struct rte_ether_addr *mac)
4127 struct hwrm_func_qcfg_input req = {0};
4128 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4131 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4133 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4134 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4136 HWRM_CHECK_RESULT();
4138 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4145 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4146 void *encaped, size_t ec_size)
4149 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4150 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4152 if (ec_size > sizeof(req.encap_request))
4155 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4157 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4158 memcpy(req.encap_request, encaped, ec_size);
4160 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4162 HWRM_CHECK_RESULT();
4168 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
4169 struct rte_eth_stats *stats, uint8_t rx)
4172 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4173 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4175 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4177 req.stat_ctx_id = rte_cpu_to_le_32(cid);
4179 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4181 HWRM_CHECK_RESULT();
4184 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4185 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4186 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4187 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4188 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4189 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4190 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4191 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4193 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4194 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4195 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4196 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4197 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4198 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4206 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4208 struct hwrm_port_qstats_input req = {0};
4209 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4210 struct bnxt_pf_info *pf = bp->pf;
4213 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4215 req.port_id = rte_cpu_to_le_16(pf->port_id);
4216 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4217 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4218 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4220 HWRM_CHECK_RESULT();
4226 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4228 struct hwrm_port_clr_stats_input req = {0};
4229 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4230 struct bnxt_pf_info *pf = bp->pf;
4233 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4234 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4235 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4238 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4240 req.port_id = rte_cpu_to_le_16(pf->port_id);
4241 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4243 HWRM_CHECK_RESULT();
4249 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4251 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4252 struct hwrm_port_led_qcaps_input req = {0};
4258 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4259 req.port_id = bp->pf->port_id;
4260 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4262 HWRM_CHECK_RESULT();
4264 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4267 bp->leds->num_leds = resp->num_leds;
4268 memcpy(bp->leds, &resp->led0_id,
4269 sizeof(bp->leds[0]) * bp->leds->num_leds);
4270 for (i = 0; i < bp->leds->num_leds; i++) {
4271 struct bnxt_led_info *led = &bp->leds[i];
4273 uint16_t caps = led->led_state_caps;
4275 if (!led->led_group_id ||
4276 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4277 bp->leds->num_leds = 0;
4288 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4290 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4291 struct hwrm_port_led_cfg_input req = {0};
4292 struct bnxt_led_cfg *led_cfg;
4293 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4294 uint16_t duration = 0;
4297 if (!bp->leds->num_leds || BNXT_VF(bp))
4300 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4303 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4304 duration = rte_cpu_to_le_16(500);
4306 req.port_id = bp->pf->port_id;
4307 req.num_leds = bp->leds->num_leds;
4308 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4309 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4310 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4311 led_cfg->led_id = bp->leds[i].led_id;
4312 led_cfg->led_state = led_state;
4313 led_cfg->led_blink_on = duration;
4314 led_cfg->led_blink_off = duration;
4315 led_cfg->led_group_id = bp->leds[i].led_group_id;
4318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4320 HWRM_CHECK_RESULT();
4326 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4330 struct hwrm_nvm_get_dir_info_input req = {0};
4331 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4333 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4337 HWRM_CHECK_RESULT();
4339 *entries = rte_le_to_cpu_32(resp->entries);
4340 *length = rte_le_to_cpu_32(resp->entry_length);
4346 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4349 uint32_t dir_entries;
4350 uint32_t entry_length;
4353 rte_iova_t dma_handle;
4354 struct hwrm_nvm_get_dir_entries_input req = {0};
4355 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4357 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4361 *data++ = dir_entries;
4362 *data++ = entry_length;
4364 memset(data, 0xff, len);
4366 buflen = dir_entries * entry_length;
4367 buf = rte_malloc("nvm_dir", buflen, 0);
4370 dma_handle = rte_malloc_virt2iova(buf);
4371 if (dma_handle == RTE_BAD_IOVA) {
4374 "unable to map response address to physical memory\n");
4377 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4378 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4379 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4382 memcpy(data, buf, len > buflen ? buflen : len);
4385 HWRM_CHECK_RESULT();
4391 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4392 uint32_t offset, uint32_t length,
4397 rte_iova_t dma_handle;
4398 struct hwrm_nvm_read_input req = {0};
4399 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4401 buf = rte_malloc("nvm_item", length, 0);
4405 dma_handle = rte_malloc_virt2iova(buf);
4406 if (dma_handle == RTE_BAD_IOVA) {
4409 "unable to map response address to physical memory\n");
4412 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4413 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4414 req.dir_idx = rte_cpu_to_le_16(index);
4415 req.offset = rte_cpu_to_le_32(offset);
4416 req.len = rte_cpu_to_le_32(length);
4417 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4419 memcpy(data, buf, length);
4422 HWRM_CHECK_RESULT();
4428 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4431 struct hwrm_nvm_erase_dir_entry_input req = {0};
4432 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4434 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4435 req.dir_idx = rte_cpu_to_le_16(index);
4436 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4437 HWRM_CHECK_RESULT();
4444 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4445 uint16_t dir_ordinal, uint16_t dir_ext,
4446 uint16_t dir_attr, const uint8_t *data,
4450 struct hwrm_nvm_write_input req = {0};
4451 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4452 rte_iova_t dma_handle;
4455 buf = rte_malloc("nvm_write", data_len, 0);
4459 dma_handle = rte_malloc_virt2iova(buf);
4460 if (dma_handle == RTE_BAD_IOVA) {
4463 "unable to map response address to physical memory\n");
4466 memcpy(buf, data, data_len);
4468 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4470 req.dir_type = rte_cpu_to_le_16(dir_type);
4471 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4472 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4473 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4474 req.dir_data_length = rte_cpu_to_le_32(data_len);
4475 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4477 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4480 HWRM_CHECK_RESULT();
4487 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4489 uint32_t *count = cbdata;
4491 *count = *count + 1;
4494 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4495 struct bnxt_vnic_info *vnic __rte_unused)
4500 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4504 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4505 &count, bnxt_vnic_count_hwrm_stub);
4510 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4513 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4514 struct hwrm_func_vf_vnic_ids_query_output *resp =
4515 bp->hwrm_cmd_resp_addr;
4518 /* First query all VNIC ids */
4519 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4521 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4522 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4523 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4525 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4528 "unable to map VNIC ID table address to physical memory\n");
4531 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4532 HWRM_CHECK_RESULT();
4533 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4541 * This function queries the VNIC IDs for a specified VF. It then calls
4542 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4543 * Then it calls the hwrm_cb function to program this new vnic configuration.
4545 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4546 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4547 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4549 struct bnxt_vnic_info vnic;
4551 int i, num_vnic_ids;
4556 /* First query all VNIC ids */
4557 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4558 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4559 RTE_CACHE_LINE_SIZE);
4560 if (vnic_ids == NULL)
4563 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4564 rte_mem_lock_page(((char *)vnic_ids) + sz);
4566 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4568 if (num_vnic_ids < 0)
4569 return num_vnic_ids;
4571 /* Retrieve VNIC, update bd_stall then update */
4573 for (i = 0; i < num_vnic_ids; i++) {
4574 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4575 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4576 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4579 if (vnic.mru <= 4) /* Indicates unallocated */
4582 vnic_cb(&vnic, cbdata);
4584 rc = hwrm_cb(bp, &vnic);
4594 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4597 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4598 struct hwrm_func_cfg_input req = {0};
4601 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4603 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4604 req.enables |= rte_cpu_to_le_32(
4605 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4606 req.vlan_antispoof_mode = on ?
4607 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4608 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4609 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4611 HWRM_CHECK_RESULT();
4617 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4619 struct bnxt_vnic_info vnic;
4622 int num_vnic_ids, i;
4626 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4627 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4628 RTE_CACHE_LINE_SIZE);
4629 if (vnic_ids == NULL)
4632 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4633 rte_mem_lock_page(((char *)vnic_ids) + sz);
4635 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4641 * Loop through to find the default VNIC ID.
4642 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4643 * by sending the hwrm_func_qcfg command to the firmware.
4645 for (i = 0; i < num_vnic_ids; i++) {
4646 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4647 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4648 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4649 bp->pf->first_vf_id + vf);
4652 if (vnic.func_default) {
4654 return vnic.fw_vnic_id;
4657 /* Could not find a default VNIC. */
4658 PMD_DRV_LOG(ERR, "No default VNIC\n");
4664 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4666 struct bnxt_filter_info *filter)
4669 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4670 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4671 uint32_t enables = 0;
4673 if (filter->fw_em_filter_id != UINT64_MAX)
4674 bnxt_hwrm_clear_em_filter(bp, filter);
4676 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4678 req.flags = rte_cpu_to_le_32(filter->flags);
4680 enables = filter->enables |
4681 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4682 req.dst_id = rte_cpu_to_le_16(dst_id);
4684 if (filter->ip_addr_type) {
4685 req.ip_addr_type = filter->ip_addr_type;
4686 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4689 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4690 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4692 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4693 memcpy(req.src_macaddr, filter->src_macaddr,
4694 RTE_ETHER_ADDR_LEN);
4696 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4697 memcpy(req.dst_macaddr, filter->dst_macaddr,
4698 RTE_ETHER_ADDR_LEN);
4700 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4701 req.ovlan_vid = filter->l2_ovlan;
4703 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4704 req.ivlan_vid = filter->l2_ivlan;
4706 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4707 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4709 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4710 req.ip_protocol = filter->ip_protocol;
4712 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4713 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4715 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4716 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4718 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4719 req.src_port = rte_cpu_to_be_16(filter->src_port);
4721 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4722 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4724 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4725 req.mirror_vnic_id = filter->mirror_vnic_id;
4727 req.enables = rte_cpu_to_le_32(enables);
4729 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4731 HWRM_CHECK_RESULT();
4733 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4739 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4742 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4743 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4745 if (filter->fw_em_filter_id == UINT64_MAX)
4748 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4750 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4752 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4754 HWRM_CHECK_RESULT();
4757 filter->fw_em_filter_id = UINT64_MAX;
4758 filter->fw_l2_filter_id = UINT64_MAX;
4763 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4765 struct bnxt_filter_info *filter)
4768 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4769 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4770 bp->hwrm_cmd_resp_addr;
4771 uint32_t enables = 0;
4773 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4774 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4776 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4778 req.flags = rte_cpu_to_le_32(filter->flags);
4780 enables = filter->enables |
4781 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4782 req.dst_id = rte_cpu_to_le_16(dst_id);
4784 if (filter->ip_addr_type) {
4785 req.ip_addr_type = filter->ip_addr_type;
4787 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4790 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4791 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4793 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4794 memcpy(req.src_macaddr, filter->src_macaddr,
4795 RTE_ETHER_ADDR_LEN);
4797 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4798 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4800 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4801 req.ip_protocol = filter->ip_protocol;
4803 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4804 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4806 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4807 req.src_ipaddr_mask[0] =
4808 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4810 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4811 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4813 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4814 req.dst_ipaddr_mask[0] =
4815 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4817 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4818 req.src_port = rte_cpu_to_le_16(filter->src_port);
4820 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4821 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4823 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4824 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4826 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4827 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4829 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4830 req.mirror_vnic_id = filter->mirror_vnic_id;
4832 req.enables = rte_cpu_to_le_32(enables);
4834 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4836 HWRM_CHECK_RESULT();
4838 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4839 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4845 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4846 struct bnxt_filter_info *filter)
4849 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4850 struct hwrm_cfa_ntuple_filter_free_output *resp =
4851 bp->hwrm_cmd_resp_addr;
4853 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4856 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4858 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4860 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4862 HWRM_CHECK_RESULT();
4865 filter->fw_ntuple_filter_id = UINT64_MAX;
4871 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4873 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4874 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4875 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4876 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4877 uint16_t *ring_tbl = vnic->rss_table;
4878 int nr_ctxs = vnic->num_lb_ctxts;
4879 int max_rings = bp->rx_nr_rings;
4883 for (i = 0, k = 0; i < nr_ctxs; i++) {
4884 struct bnxt_rx_ring_info *rxr;
4885 struct bnxt_cp_ring_info *cpr;
4887 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4889 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4890 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4891 req.hash_mode_flags = vnic->hash_mode;
4893 req.ring_grp_tbl_addr =
4894 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4895 i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
4896 2 * sizeof(*ring_tbl));
4897 req.hash_key_tbl_addr =
4898 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4900 req.ring_table_pair_index = i;
4901 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4903 for (j = 0; j < 64; j++) {
4906 /* Find next active ring. */
4907 for (cnt = 0; cnt < max_rings; cnt++) {
4908 if (rx_queue_state[k] !=
4909 RTE_ETH_QUEUE_STATE_STOPPED)
4911 if (++k == max_rings)
4915 /* Return if no rings are active. */
4916 if (cnt == max_rings) {
4921 /* Add rx/cp ring pair to RSS table. */
4922 rxr = rxqs[k]->rx_ring;
4923 cpr = rxqs[k]->cp_ring;
4925 ring_id = rxr->rx_ring_struct->fw_ring_id;
4926 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4927 ring_id = cpr->cp_ring_struct->fw_ring_id;
4928 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4930 if (++k == max_rings)
4933 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4936 HWRM_CHECK_RESULT();
4943 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4945 unsigned int rss_idx, fw_idx, i;
4947 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4950 if (!(vnic->rss_table && vnic->hash_type))
4953 if (BNXT_CHIP_P5(bp))
4954 return bnxt_vnic_rss_configure_p5(bp, vnic);
4957 * Fill the RSS hash & redirection table with
4958 * ring group ids for all VNICs
4960 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4961 rss_idx++, fw_idx++) {
4962 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4963 fw_idx %= bp->rx_cp_nr_rings;
4964 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4969 if (i == bp->rx_cp_nr_rings)
4972 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4975 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4978 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4979 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4983 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4985 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4986 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4988 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4989 req->num_cmpl_dma_aggr_during_int =
4990 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4992 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4994 /* min timer set to 1/2 of interrupt timer */
4995 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4997 /* buf timer set to 1/4 of interrupt timer */
4998 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5000 req->cmpl_aggr_dma_tmr_during_int =
5001 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5003 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5004 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5005 req->flags = rte_cpu_to_le_16(flags);
5008 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5009 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5011 struct hwrm_ring_aggint_qcaps_input req = {0};
5012 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5017 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5018 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5019 HWRM_CHECK_RESULT();
5021 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5022 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5024 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5025 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5026 agg_req->flags = rte_cpu_to_le_16(flags);
5028 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5029 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5030 agg_req->enables = rte_cpu_to_le_32(enables);
5036 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5037 struct bnxt_coal *coal, uint16_t ring_id)
5039 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5040 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5041 bp->hwrm_cmd_resp_addr;
5044 /* Set ring coalesce parameters only for 100G NICs */
5045 if (BNXT_CHIP_P5(bp)) {
5046 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5048 } else if (bnxt_stratus_device(bp)) {
5049 bnxt_hwrm_set_coal_params(coal, &req);
5055 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5057 req.ring_id = rte_cpu_to_le_16(ring_id);
5058 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5059 HWRM_CHECK_RESULT();
5064 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5065 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5067 struct hwrm_func_backing_store_qcaps_input req = {0};
5068 struct hwrm_func_backing_store_qcaps_output *resp =
5069 bp->hwrm_cmd_resp_addr;
5070 struct bnxt_ctx_pg_info *ctx_pg;
5071 struct bnxt_ctx_mem_info *ctx;
5072 int total_alloc_len;
5073 int rc, i, tqm_rings;
5075 if (!BNXT_CHIP_P5(bp) ||
5076 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5081 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5082 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5083 HWRM_CHECK_RESULT_SILENT();
5085 total_alloc_len = sizeof(*ctx);
5086 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5087 RTE_CACHE_LINE_SIZE);
5093 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5094 ctx->qp_min_qp1_entries =
5095 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5096 ctx->qp_max_l2_entries =
5097 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5098 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5099 ctx->srq_max_l2_entries =
5100 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5101 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5102 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5103 ctx->cq_max_l2_entries =
5104 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5105 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5106 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5107 ctx->vnic_max_vnic_entries =
5108 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5109 ctx->vnic_max_ring_table_entries =
5110 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5111 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5112 ctx->stat_max_entries =
5113 rte_le_to_cpu_32(resp->stat_max_entries);
5114 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5115 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5116 ctx->tqm_min_entries_per_ring =
5117 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5118 ctx->tqm_max_entries_per_ring =
5119 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5120 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5121 if (!ctx->tqm_entries_multiple)
5122 ctx->tqm_entries_multiple = 1;
5123 ctx->mrav_max_entries =
5124 rte_le_to_cpu_32(resp->mrav_max_entries);
5125 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5126 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5127 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5128 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5130 ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5131 RTE_MIN(ctx->tqm_fp_rings_count,
5132 BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5135 /* Check if the ext ring count needs to be counted.
5136 * Ext ring count is available only with new FW so we should not
5137 * look at the field on older FW.
5139 if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5140 bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5141 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5142 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5143 ctx->tqm_fp_rings_count);
5146 tqm_rings = ctx->tqm_fp_rings_count + 1;
5148 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5149 sizeof(*ctx_pg) * tqm_rings,
5150 RTE_CACHE_LINE_SIZE);
5155 for (i = 0; i < tqm_rings; i++, ctx_pg++)
5156 ctx->tqm_mem[i] = ctx_pg;
5164 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5166 struct hwrm_func_backing_store_cfg_input req = {0};
5167 struct hwrm_func_backing_store_cfg_output *resp =
5168 bp->hwrm_cmd_resp_addr;
5169 struct bnxt_ctx_mem_info *ctx = bp->ctx;
5170 struct bnxt_ctx_pg_info *ctx_pg;
5171 uint32_t *num_entries;
5180 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5181 req.enables = rte_cpu_to_le_32(enables);
5183 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5184 ctx_pg = &ctx->qp_mem;
5185 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5186 req.qp_num_qp1_entries =
5187 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5188 req.qp_num_l2_entries =
5189 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5190 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5191 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5192 &req.qpc_pg_size_qpc_lvl,
5196 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5197 ctx_pg = &ctx->srq_mem;
5198 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5199 req.srq_num_l2_entries =
5200 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5201 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5202 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5203 &req.srq_pg_size_srq_lvl,
5207 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5208 ctx_pg = &ctx->cq_mem;
5209 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5210 req.cq_num_l2_entries =
5211 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5212 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5213 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5214 &req.cq_pg_size_cq_lvl,
5218 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5219 ctx_pg = &ctx->vnic_mem;
5220 req.vnic_num_vnic_entries =
5221 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5222 req.vnic_num_ring_table_entries =
5223 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5224 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5225 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5226 &req.vnic_pg_size_vnic_lvl,
5227 &req.vnic_page_dir);
5230 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5231 ctx_pg = &ctx->stat_mem;
5232 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5233 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5234 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5235 &req.stat_pg_size_stat_lvl,
5236 &req.stat_page_dir);
5239 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5240 num_entries = &req.tqm_sp_num_entries;
5241 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5242 pg_dir = &req.tqm_sp_page_dir;
5243 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5244 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5245 if (!(enables & ena))
5248 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5250 ctx_pg = ctx->tqm_mem[i];
5251 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5252 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5255 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5256 /* DPDK does not need to configure MRAV and TIM type.
5257 * So we are skipping over MRAV and TIM. Skip to configure
5258 * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5260 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5261 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5262 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5263 &req.tqm_ring8_pg_size_tqm_ring_lvl,
5264 &req.tqm_ring8_page_dir);
5267 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5268 HWRM_CHECK_RESULT();
5274 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5276 struct hwrm_port_qstats_ext_input req = {0};
5277 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5278 struct bnxt_pf_info *pf = bp->pf;
5281 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5282 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5285 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5287 req.port_id = rte_cpu_to_le_16(pf->port_id);
5288 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5289 req.tx_stat_host_addr =
5290 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5292 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5294 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5295 req.rx_stat_host_addr =
5296 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5298 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5300 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5303 bp->fw_rx_port_stats_ext_size = 0;
5304 bp->fw_tx_port_stats_ext_size = 0;
5306 bp->fw_rx_port_stats_ext_size =
5307 rte_le_to_cpu_16(resp->rx_stat_size);
5308 bp->fw_tx_port_stats_ext_size =
5309 rte_le_to_cpu_16(resp->tx_stat_size);
5312 HWRM_CHECK_RESULT();
5319 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5321 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5322 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5323 bp->hwrm_cmd_resp_addr;
5326 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5327 req.tunnel_type = type;
5328 req.dest_fid = bp->fw_fid;
5329 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5330 HWRM_CHECK_RESULT();
5338 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5340 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5341 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5342 bp->hwrm_cmd_resp_addr;
5345 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5346 req.tunnel_type = type;
5347 req.dest_fid = bp->fw_fid;
5348 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5349 HWRM_CHECK_RESULT();
5356 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5358 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5359 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5360 bp->hwrm_cmd_resp_addr;
5363 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5364 req.src_fid = bp->fw_fid;
5365 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5366 HWRM_CHECK_RESULT();
5369 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5376 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5379 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5380 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5381 bp->hwrm_cmd_resp_addr;
5384 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5385 req.src_fid = bp->fw_fid;
5386 req.tunnel_type = tun_type;
5387 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5388 HWRM_CHECK_RESULT();
5391 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5393 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5400 int bnxt_hwrm_set_mac(struct bnxt *bp)
5402 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5403 struct hwrm_func_vf_cfg_input req = {0};
5409 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5412 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5413 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5415 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5417 HWRM_CHECK_RESULT();
5424 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5426 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5427 struct hwrm_func_drv_if_change_input req = {0};
5431 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5434 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5435 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5436 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5438 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5441 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5445 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5447 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5449 HWRM_CHECK_RESULT();
5450 flags = rte_le_to_cpu_32(resp->flags);
5456 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5457 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5458 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5464 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5466 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5467 struct bnxt_error_recovery_info *info = bp->recovery_info;
5468 struct hwrm_error_recovery_qcfg_input req = {0};
5473 /* Older FW does not have error recovery support */
5474 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5477 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5479 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5481 HWRM_CHECK_RESULT();
5483 flags = rte_le_to_cpu_32(resp->flags);
5484 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5485 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5486 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5487 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5489 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5490 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5495 /* FW returned values are in units of 100msec */
5496 info->driver_polling_freq =
5497 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5498 info->master_func_wait_period =
5499 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5500 info->normal_func_wait_period =
5501 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5502 info->master_func_wait_period_after_reset =
5503 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5504 info->max_bailout_time_after_reset =
5505 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5506 info->status_regs[BNXT_FW_STATUS_REG] =
5507 rte_le_to_cpu_32(resp->fw_health_status_reg);
5508 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5509 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5510 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5511 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5512 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5513 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5514 info->reg_array_cnt =
5515 rte_le_to_cpu_32(resp->reg_array_cnt);
5517 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5522 for (i = 0; i < info->reg_array_cnt; i++) {
5523 info->reset_reg[i] =
5524 rte_le_to_cpu_32(resp->reset_reg[i]);
5525 info->reset_reg_val[i] =
5526 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5527 info->delay_after_reset[i] =
5528 resp->delay_after_reset[i];
5533 /* Map the FW status registers */
5535 rc = bnxt_map_fw_health_status_regs(bp);
5538 rte_free(bp->recovery_info);
5539 bp->recovery_info = NULL;
5544 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5546 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5547 struct hwrm_fw_reset_input req = {0};
5553 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5555 req.embedded_proc_type =
5556 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5557 req.selfrst_status =
5558 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5559 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5561 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5564 HWRM_CHECK_RESULT();
5570 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5572 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5573 struct hwrm_port_ts_query_input req = {0};
5574 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5581 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5584 case BNXT_PTP_FLAGS_PATH_TX:
5585 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5587 case BNXT_PTP_FLAGS_PATH_RX:
5588 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5590 case BNXT_PTP_FLAGS_CURRENT_TIME:
5591 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5595 req.flags = rte_cpu_to_le_32(flags);
5596 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5598 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5600 HWRM_CHECK_RESULT();
5603 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5605 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5612 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5616 struct hwrm_cfa_counter_qcaps_input req = {0};
5617 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5619 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5621 "Not a PF or trusted VF. Command not supported\n");
5625 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5626 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5627 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5629 HWRM_CHECK_RESULT();
5631 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5637 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5640 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5641 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5643 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5645 "Not a PF or trusted VF. Command not supported\n");
5649 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5651 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5652 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5653 req.page_dir = rte_cpu_to_le_64(dma_addr);
5655 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5657 HWRM_CHECK_RESULT();
5659 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5660 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5667 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5670 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5671 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5673 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5675 "Not a PF or trusted VF. Command not supported\n");
5679 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5681 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5683 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5685 HWRM_CHECK_RESULT();
5691 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5692 uint16_t cntr, uint16_t ctx_id,
5693 uint32_t num_entries, bool enable)
5695 struct hwrm_cfa_counter_cfg_input req = {0};
5696 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5700 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5702 "Not a PF or trusted VF. Command not supported\n");
5706 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5708 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5709 req.counter_type = rte_cpu_to_le_16(cntr);
5710 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5711 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5712 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5713 if (dir == BNXT_DIR_RX)
5714 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5715 else if (dir == BNXT_DIR_TX)
5716 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5717 req.flags = rte_cpu_to_le_16(flags);
5718 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5719 req.num_entries = rte_cpu_to_le_32(num_entries);
5721 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5722 HWRM_CHECK_RESULT();
5728 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5729 enum bnxt_flow_dir dir,
5731 uint16_t num_entries)
5733 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5734 struct hwrm_cfa_counter_qstats_input req = {0};
5735 uint16_t flow_ctx_id = 0;
5739 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5741 "Not a PF or trusted VF. Command not supported\n");
5745 if (dir == BNXT_DIR_RX) {
5746 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5747 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5748 } else if (dir == BNXT_DIR_TX) {
5749 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5750 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5753 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5754 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5755 req.counter_type = rte_cpu_to_le_16(cntr);
5756 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5757 req.num_entries = rte_cpu_to_le_16(num_entries);
5758 req.flags = rte_cpu_to_le_16(flags);
5759 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5761 HWRM_CHECK_RESULT();
5767 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5768 uint16_t *first_vf_id)
5771 struct hwrm_func_qcaps_input req = {.req_type = 0 };
5772 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5774 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5776 req.fid = rte_cpu_to_le_16(fid);
5778 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5780 HWRM_CHECK_RESULT();
5783 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5790 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5792 struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5793 struct hwrm_cfa_pair_alloc_input req = {0};
5796 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5798 "Not a PF or trusted VF. Command not supported\n");
5802 HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5803 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5804 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5805 bp->eth_dev->data->name, rep_bp->vf_id);
5807 req.pf_b_id = rep_bp->parent_pf_idx;
5808 req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5809 rte_cpu_to_le_16(rep_bp->vf_id);
5810 req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5811 req.host_b_id = 1; /* TBD - Confirm if this is OK */
5813 req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5814 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5815 req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5816 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5817 req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5818 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5819 req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5820 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5822 req.q_ab = rep_bp->rep_q_r2f;
5823 req.q_ba = rep_bp->rep_q_f2r;
5824 req.fc_ab = rep_bp->rep_fc_r2f;
5825 req.fc_ba = rep_bp->rep_fc_f2r;
5827 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5828 HWRM_CHECK_RESULT();
5831 PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5832 BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5836 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5838 struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5839 struct hwrm_cfa_pair_free_input req = {0};
5842 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5844 "Not a PF or trusted VF. Command not supported\n");
5848 HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5849 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5850 bp->eth_dev->data->name, rep_bp->vf_id);
5851 req.pf_b_id = rep_bp->parent_pf_idx;
5852 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5853 req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5854 rte_cpu_to_le_16(rep_bp->vf_id);
5855 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5856 HWRM_CHECK_RESULT();
5858 PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
5863 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5865 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5866 bp->hwrm_cmd_resp_addr;
5867 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5871 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5874 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5876 "Not a PF or trusted VF. Command not supported\n");
5880 HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
5881 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5883 HWRM_CHECK_RESULT();
5884 flags = rte_le_to_cpu_32(resp->flags);
5887 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
5888 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
5890 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;