drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (!BNXT_CHIP_P5(bp) &&
 754             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 755                 return 0;
 756
 757         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 758                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 759
 760         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 761         if (!ptp)
 762                 return -ENOMEM;
 763
 764         if (!BNXT_CHIP_P5(bp)) {
 765                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 766                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 767                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 768                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 769                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 771                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 773                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 775                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 776                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 777                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 778                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 779                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 781                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 783         }
 784
 785         ptp->bp = bp;
 786         bp->ptp_cfg = ptp;
 787
 788         return 0;
 789 }
 790
 791 void bnxt_free_vf_info(struct bnxt *bp)
 792 {
 793         int i;
 794
 795         if (bp->pf == NULL)
 796                 return;
 797
 798         if (bp->pf->vf_info == NULL)
 799                 return;
 800
 801         for (i = 0; i < bp->pf->max_vfs; i++) {
 802                 rte_free(bp->pf->vf_info[i].vlan_table);
 803                 bp->pf->vf_info[i].vlan_table = NULL;
 804                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 805                 bp->pf->vf_info[i].vlan_as_table = NULL;
 806         }
 807         rte_free(bp->pf->vf_info);
 808         bp->pf->vf_info = NULL;
 809 }
 810
 811 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 812 {
 813         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 814         int i;
 815
 816         if (vf_info)
 817                 bnxt_free_vf_info(bp);
 818
 819         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 820         if (vf_info == NULL) {
 821                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 822                 return -ENOMEM;
 823         }
 824
 825         bp->pf->max_vfs = max_vfs;
 826         for (i = 0; i < max_vfs; i++) {
 827                 vf_info[i].fid = bp->pf->first_vf_id + i;
 828                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 829                                                     getpagesize(), getpagesize());
 830                 if (vf_info[i].vlan_table == NULL) {
 831                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 832                         goto err;
 833                 }
 834                 rte_mem_lock_page(vf_info[i].vlan_table);
 835
 836                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 837                                                        getpagesize(), getpagesize());
 838                 if (vf_info[i].vlan_as_table == NULL) {
 839                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 840                         goto err;
 841                 }
 842                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 843
 844                 STAILQ_INIT(&vf_info[i].filter);
 845         }
 846
 847         bp->pf->vf_info = vf_info;
 848
 849         return 0;
 850 err:
 851         bnxt_free_vf_info(bp);
 852         return -ENOMEM;
 853 }
 854
 855 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 856 {
 857         int rc = 0;
 858         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 859         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 860         uint16_t new_max_vfs;
 861         uint32_t flags;
 862
 863         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 864
 865         req.fid = rte_cpu_to_le_16(0xffff);
 866
 867         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 868
 869         HWRM_CHECK_RESULT();
 870
 871         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 872         flags = rte_le_to_cpu_32(resp->flags);
 873         if (BNXT_PF(bp)) {
 874                 bp->pf->port_id = resp->port_id;
 875                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 876                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 877                 new_max_vfs = bp->pdev->max_vfs;
 878                 if (new_max_vfs != bp->pf->max_vfs) {
 879                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 880                         if (rc)
 881                                 goto unlock;
 882                 }
 883         }
 884
 885         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 886         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 887                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 888                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 889         } else {
 890                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 891         }
 892         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 893         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 894         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 895         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 896         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 897         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 898         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 899         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 900                 bp->max_l2_ctx += bp->max_rx_em_flows;
 901         /* TODO: For now, do not support VMDq/RFS on VFs. */
 902         if (BNXT_PF(bp)) {
 903                 if (bp->pf->max_vfs)
 904                         bp->max_vnics = 1;
 905                 else
 906                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 907         } else {
 908                 bp->max_vnics = 1;
 909         }
 910         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 911                     bp->max_l2_ctx, bp->max_vnics);
 912         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 913         if (BNXT_PF(bp)) {
 914                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 915                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 916                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 917                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 918                         HWRM_UNLOCK();
 919                         bnxt_hwrm_ptp_qcfg(bp);
 920                 }
 921         }
 922
 923         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 924                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 925
 926         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 927                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 928                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 929         }
 930
 931         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 932                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 933
 934         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 935                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 936
 937         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 938                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 939
 940 unlock:
 941         HWRM_UNLOCK();
 942
 943         return rc;
 944 }
 945
 946 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 947 {
 948         int rc;
 949
 950         rc = __bnxt_hwrm_func_qcaps(bp);
 951         if (rc == -ENOMEM)
 952                 return rc;
 953
 954         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 955                 rc = bnxt_alloc_ctx_mem(bp);
 956                 if (rc)
 957                         return rc;
 958
 959                 /* On older FW,
 960                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 961                  * But the error can be ignored. Return success.
 962                  */
 963                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 964                 if (!rc)
 965                         bp->flags |= BNXT_FLAG_NEW_RM;
 966         }
 967
 968         return 0;
 969 }
 970
 971 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 972 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 973 {
 974         int rc = 0;
 975         uint32_t flags;
 976         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 977         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 978
 979         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 980
 981         req.target_id = rte_cpu_to_le_16(0xffff);
 982
 983         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 984
 985         HWRM_CHECK_RESULT();
 986
 987         flags = rte_le_to_cpu_32(resp->flags);
 988
 989         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 990                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 991                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 992         }
 993
 994         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 995                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
 996
 997         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
 998                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
 999
1000         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1001
1002         HWRM_UNLOCK();
1003
1004         return rc;
1005 }
1006
1007 int bnxt_hwrm_func_reset(struct bnxt *bp)
1008 {
1009         int rc = 0;
1010         struct hwrm_func_reset_input req = {.req_type = 0 };
1011         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1012
1013         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1014
1015         req.enables = rte_cpu_to_le_32(0);
1016
1017         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1018
1019         HWRM_CHECK_RESULT();
1020         HWRM_UNLOCK();
1021
1022         return rc;
1023 }
1024
1025 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1026 {
1027         int rc;
1028         uint32_t flags = 0;
1029         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1030         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1031
1032         if (bp->flags & BNXT_FLAG_REGISTERED)
1033                 return 0;
1034
1035         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1036                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1037         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1038                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1039
1040         /* PFs and trusted VFs should indicate the support of the
1041          * Master capability on non Stingray platform
1042          */
1043         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1044                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1045
1046         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1047         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1048                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1049         req.ver_maj = RTE_VER_YEAR;
1050         req.ver_min = RTE_VER_MONTH;
1051         req.ver_upd = RTE_VER_MINOR;
1052
1053         if (BNXT_PF(bp)) {
1054                 req.enables |= rte_cpu_to_le_32(
1055                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1056                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1057                        RTE_MIN(sizeof(req.vf_req_fwd),
1058                                sizeof(bp->pf->vf_req_fwd)));
1059         }
1060
1061         req.flags = rte_cpu_to_le_32(flags);
1062
1063         req.async_event_fwd[0] |=
1064                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1065                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1066                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1067                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1068                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1069         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1070                 req.async_event_fwd[0] |=
1071                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1072         req.async_event_fwd[1] |=
1073                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1074                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1075         if (BNXT_PF(bp))
1076                 req.async_event_fwd[1] |=
1077                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1078
1079         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1080                 req.async_event_fwd[1] |=
1081                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1082
1083         req.async_event_fwd[2] |=
1084                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
1085
1086         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1087
1088         HWRM_CHECK_RESULT();
1089
1090         flags = rte_le_to_cpu_32(resp->flags);
1091         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1092                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1093
1094         HWRM_UNLOCK();
1095
1096         bp->flags |= BNXT_FLAG_REGISTERED;
1097
1098         return rc;
1099 }
1100
1101 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1102 {
1103         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1104                 return 0;
1105
1106         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1107 }
1108
1109 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1110 {
1111         int rc;
1112         uint32_t flags = 0;
1113         uint32_t enables;
1114         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1115         struct hwrm_func_vf_cfg_input req = {0};
1116
1117         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1118
1119         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1120                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1121                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1122                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1123                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1124
1125         if (BNXT_HAS_RING_GRPS(bp)) {
1126                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1127                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1128         }
1129
1130         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1131         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1132                                             AGG_RING_MULTIPLIER);
1133         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1134         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1135                                               bp->tx_nr_rings +
1136                                               BNXT_NUM_ASYNC_CPR(bp));
1137         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1138         if (bp->vf_resv_strategy ==
1139             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1140                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1141                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1142                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1143                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1144                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1145                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1146         } else if (bp->vf_resv_strategy ==
1147                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1148                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1149                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1150         }
1151
1152         if (test)
1153                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1154                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1155                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1156                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1157                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1158                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1159
1160         if (test && BNXT_HAS_RING_GRPS(bp))
1161                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1162
1163         req.flags = rte_cpu_to_le_32(flags);
1164         req.enables |= rte_cpu_to_le_32(enables);
1165
1166         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1167
1168         if (test)
1169                 HWRM_CHECK_RESULT_SILENT();
1170         else
1171                 HWRM_CHECK_RESULT();
1172
1173         HWRM_UNLOCK();
1174         return rc;
1175 }
1176
1177 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1178 {
1179         int rc;
1180         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1181         struct hwrm_func_resource_qcaps_input req = {0};
1182
1183         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1184         req.fid = rte_cpu_to_le_16(0xffff);
1185
1186         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1187
1188         HWRM_CHECK_RESULT_SILENT();
1189
1190         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1191         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1192         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1193         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1194         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1195         /* func_resource_qcaps does not return max_rx_em_flows.
1196          * So use the value provided by func_qcaps.
1197          */
1198         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1199         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1200                 bp->max_l2_ctx += bp->max_rx_em_flows;
1201         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1202         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1203         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1204         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1205         if (bp->vf_resv_strategy >
1206             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1207                 bp->vf_resv_strategy =
1208                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1209
1210         HWRM_UNLOCK();
1211         return rc;
1212 }
1213
1214 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1215 {
1216         int rc = 0;
1217         struct hwrm_ver_get_input req = {.req_type = 0 };
1218         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1219         uint32_t fw_version;
1220         uint16_t max_resp_len;
1221         char type[RTE_MEMZONE_NAMESIZE];
1222         uint32_t dev_caps_cfg;
1223
1224         bp->max_req_len = HWRM_MAX_REQ_LEN;
1225         bp->hwrm_cmd_timeout = timeout;
1226         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1227
1228         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1229         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1230         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1231
1232         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1233
1234         if (bp->flags & BNXT_FLAG_FW_RESET)
1235                 HWRM_CHECK_RESULT_SILENT();
1236         else
1237                 HWRM_CHECK_RESULT();
1238
1239         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1240                 rc = -EAGAIN;
1241                 goto error;
1242         }
1243
1244         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1245                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1246                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1247                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1248                 resp->hwrm_fw_rsvd_8b);
1249         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1250                      (resp->hwrm_fw_min_8b << 16) |
1251                      (resp->hwrm_fw_bld_8b << 8) |
1252                      resp->hwrm_fw_rsvd_8b;
1253         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1254                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1255
1256         fw_version = resp->hwrm_intf_maj_8b << 16;
1257         fw_version |= resp->hwrm_intf_min_8b << 8;
1258         fw_version |= resp->hwrm_intf_upd_8b;
1259         bp->hwrm_spec_code = fw_version;
1260
1261         /* def_req_timeout value is in milliseconds */
1262         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1263         /* convert timeout to usec */
1264         bp->hwrm_cmd_timeout *= 1000;
1265         if (!bp->hwrm_cmd_timeout)
1266                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1267
1268         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1269                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1270                 rc = -EINVAL;
1271                 goto error;
1272         }
1273
1274         if (bp->max_req_len > resp->max_req_win_len) {
1275                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1276                 rc = -EINVAL;
1277                 goto error;
1278         }
1279
1280         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1281
1282         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1283         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1284         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1285                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1286
1287         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1288         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1289
1290         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1291         bp->max_resp_len = max_resp_len;
1292
1293         if ((dev_caps_cfg &
1294                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1295             (dev_caps_cfg &
1296              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1297                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1298                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1299         }
1300
1301         if (((dev_caps_cfg &
1302               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1303              (dev_caps_cfg &
1304               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1305             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1306                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1307                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1308                         bp->pdev->addr.devid, bp->pdev->addr.function);
1309
1310                 rte_free(bp->hwrm_short_cmd_req_addr);
1311
1312                 bp->hwrm_short_cmd_req_addr =
1313                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1314                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1315                         rc = -ENOMEM;
1316                         goto error;
1317                 }
1318                 bp->hwrm_short_cmd_req_dma_addr =
1319                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1320                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1321                         rte_free(bp->hwrm_short_cmd_req_addr);
1322                         PMD_DRV_LOG(ERR,
1323                                 "Unable to map buffer to physical memory.\n");
1324                         rc = -ENOMEM;
1325                         goto error;
1326                 }
1327         }
1328         if (dev_caps_cfg &
1329             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1330                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1331                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1332         }
1333         if (dev_caps_cfg &
1334             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1335                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1336         if (dev_caps_cfg &
1337             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1338                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1339                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1340         }
1341
1342         if (dev_caps_cfg &
1343             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1344                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1345                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1346         }
1347
1348 error:
1349         HWRM_UNLOCK();
1350         return rc;
1351 }
1352
1353 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1354 {
1355         int rc;
1356         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1357         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1358
1359         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1360                 return 0;
1361
1362         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1363         req.flags = flags;
1364
1365         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1366
1367         HWRM_CHECK_RESULT();
1368         HWRM_UNLOCK();
1369
1370         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1371                     bp->eth_dev->data->port_id);
1372
1373         return rc;
1374 }
1375
1376 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1377 {
1378         int rc = 0;
1379         struct hwrm_port_phy_cfg_input req = {0};
1380         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1381         uint32_t enables = 0;
1382
1383         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1384
1385         if (conf->link_up) {
1386                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1387                 if (bp->link_info->auto_mode && conf->link_speed) {
1388                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1389                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1390                 }
1391
1392                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1393                 /*
1394                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1395                  * any auto mode, even "none".
1396                  */
1397                 if (!conf->link_speed) {
1398                         /* No speeds specified. Enable AutoNeg - all speeds */
1399                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1400                         req.auto_mode =
1401                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1402                 } else {
1403                         if (bp->link_info->link_signal_mode) {
1404                                 enables |=
1405                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1406                                 req.force_pam4_link_speed =
1407                                         rte_cpu_to_le_16(conf->link_speed);
1408                         } else {
1409                                 req.force_link_speed =
1410                                         rte_cpu_to_le_16(conf->link_speed);
1411                         }
1412                 }
1413                 /* AutoNeg - Advertise speeds specified. */
1414                 if (conf->auto_link_speed_mask &&
1415                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1416                         req.auto_mode =
1417                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1418                         req.auto_link_speed_mask =
1419                                 conf->auto_link_speed_mask;
1420                         if (conf->auto_pam4_link_speeds) {
1421                                 enables |=
1422                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1423                                 req.auto_link_pam4_speed_mask =
1424                                         conf->auto_pam4_link_speeds;
1425                         } else {
1426                                 enables |=
1427                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1428                         }
1429                 }
1430                 if (conf->auto_link_speed &&
1431                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1432                         enables |=
1433                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1434
1435                 req.auto_duplex = conf->duplex;
1436                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1437                 req.auto_pause = conf->auto_pause;
1438                 req.force_pause = conf->force_pause;
1439                 /* Set force_pause if there is no auto or if there is a force */
1440                 if (req.auto_pause && !req.force_pause)
1441                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1442                 else
1443                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1444
1445                 req.enables = rte_cpu_to_le_32(enables);
1446         } else {
1447                 req.flags =
1448                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1449                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1450         }
1451
1452         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1453
1454         HWRM_CHECK_RESULT();
1455         HWRM_UNLOCK();
1456
1457         return rc;
1458 }
1459
1460 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1461                                    struct bnxt_link_info *link_info)
1462 {
1463         int rc = 0;
1464         struct hwrm_port_phy_qcfg_input req = {0};
1465         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1466
1467         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1468
1469         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1470
1471         HWRM_CHECK_RESULT();
1472
1473         link_info->phy_link_status = resp->link;
1474         link_info->link_up =
1475                 (link_info->phy_link_status ==
1476                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1477         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1478         link_info->duplex = resp->duplex_cfg;
1479         link_info->pause = resp->pause;
1480         link_info->auto_pause = resp->auto_pause;
1481         link_info->force_pause = resp->force_pause;
1482         link_info->auto_mode = resp->auto_mode;
1483         link_info->phy_type = resp->phy_type;
1484         link_info->media_type = resp->media_type;
1485
1486         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1487         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1488         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1489         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1490         link_info->phy_ver[0] = resp->phy_maj;
1491         link_info->phy_ver[1] = resp->phy_min;
1492         link_info->phy_ver[2] = resp->phy_bld;
1493         link_info->link_signal_mode =
1494                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1495         link_info->force_pam4_link_speed =
1496                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1497         link_info->support_pam4_speeds =
1498                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1499         link_info->auto_pam4_link_speeds =
1500                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1501         HWRM_UNLOCK();
1502
1503         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1504                     link_info->link_speed, link_info->auto_mode,
1505                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1506                     link_info->support_speeds, link_info->force_link_speed);
1507         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1508                     link_info->link_signal_mode,
1509                     link_info->auto_pam4_link_speeds,
1510                     link_info->support_pam4_speeds,
1511                     link_info->force_pam4_link_speed);
1512         return rc;
1513 }
1514
1515 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1516 {
1517         int rc = 0;
1518         struct hwrm_port_phy_qcaps_input req = {0};
1519         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1520         struct bnxt_link_info *link_info = bp->link_info;
1521
1522         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1523                 return 0;
1524
1525         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1526
1527         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1528
1529         HWRM_CHECK_RESULT_SILENT();
1530
1531         bp->port_cnt = resp->port_cnt;
1532         if (resp->supported_speeds_auto_mode)
1533                 link_info->support_auto_speeds =
1534                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1535         if (resp->supported_pam4_speeds_auto_mode)
1536                 link_info->support_pam4_auto_speeds =
1537                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1538
1539         HWRM_UNLOCK();
1540
1541         return 0;
1542 }
1543
1544 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1545 {
1546         int i = 0;
1547
1548         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1549                 if (bp->tx_cos_queue[i].profile ==
1550                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1551                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1552                         return true;
1553                 }
1554         }
1555         return false;
1556 }
1557
1558 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1559 {
1560         int i = 0;
1561
1562         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1563                 if (bp->tx_cos_queue[i].profile !=
1564                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1565                     bp->tx_cos_queue[i].id !=
1566                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1567                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1568                         break;
1569                 }
1570         }
1571 }
1572
1573 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1574 {
1575         int rc = 0;
1576         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1577         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1578         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1579         int i;
1580
1581 get_rx_info:
1582         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1583
1584         req.flags = rte_cpu_to_le_32(dir);
1585         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1586         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1587             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1588                 req.drv_qmap_cap =
1589                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1590         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1591
1592         HWRM_CHECK_RESULT();
1593
1594         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1595                 GET_TX_QUEUE_INFO(0);
1596                 GET_TX_QUEUE_INFO(1);
1597                 GET_TX_QUEUE_INFO(2);
1598                 GET_TX_QUEUE_INFO(3);
1599                 GET_TX_QUEUE_INFO(4);
1600                 GET_TX_QUEUE_INFO(5);
1601                 GET_TX_QUEUE_INFO(6);
1602                 GET_TX_QUEUE_INFO(7);
1603         } else  {
1604                 GET_RX_QUEUE_INFO(0);
1605                 GET_RX_QUEUE_INFO(1);
1606                 GET_RX_QUEUE_INFO(2);
1607                 GET_RX_QUEUE_INFO(3);
1608                 GET_RX_QUEUE_INFO(4);
1609                 GET_RX_QUEUE_INFO(5);
1610                 GET_RX_QUEUE_INFO(6);
1611                 GET_RX_QUEUE_INFO(7);
1612         }
1613
1614         HWRM_UNLOCK();
1615
1616         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1617                 goto done;
1618
1619         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1620                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1621         } else {
1622                 int j;
1623
1624                 /* iterate and find the COSq profile to use for Tx */
1625                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1626                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1627                                 if (bp->tx_cos_queue[i].id != 0xff)
1628                                         bp->tx_cosq_id[j++] =
1629                                                 bp->tx_cos_queue[i].id;
1630                         }
1631                 } else {
1632                         /* When CoS classification is disabled, for normal NIC
1633                          * operations, ideally we should look to use LOSSY.
1634                          * If not found, fallback to the first valid profile
1635                          */
1636                         if (!bnxt_find_lossy_profile(bp))
1637                                 bnxt_find_first_valid_profile(bp);
1638
1639                 }
1640         }
1641
1642         bp->max_tc = resp->max_configurable_queues;
1643         bp->max_lltc = resp->max_configurable_lossless_queues;
1644         if (bp->max_tc > BNXT_MAX_QUEUE)
1645                 bp->max_tc = BNXT_MAX_QUEUE;
1646         bp->max_q = bp->max_tc;
1647
1648         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1649                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1650                 goto get_rx_info;
1651         }
1652
1653 done:
1654         return rc;
1655 }
1656
1657 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1658                          struct bnxt_ring *ring,
1659                          uint32_t ring_type, uint32_t map_index,
1660                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1661                          uint16_t tx_cosq_id)
1662 {
1663         int rc = 0;
1664         uint32_t enables = 0;
1665         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1666         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1667         struct rte_mempool *mb_pool;
1668         uint16_t rx_buf_size;
1669
1670         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1671
1672         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1673         req.fbo = rte_cpu_to_le_32(0);
1674         /* Association of ring index with doorbell index */
1675         req.logical_id = rte_cpu_to_le_16(map_index);
1676         req.length = rte_cpu_to_le_32(ring->ring_size);
1677
1678         switch (ring_type) {
1679         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1680                 req.ring_type = ring_type;
1681                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1682                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1683                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1684                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1685                         enables |=
1686                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1687                 break;
1688         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1689                 req.ring_type = ring_type;
1690                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1691                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1692                 if (BNXT_CHIP_P5(bp)) {
1693                         mb_pool = bp->rx_queues[0]->mb_pool;
1694                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1695                                       RTE_PKTMBUF_HEADROOM;
1696                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1697                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1698                         enables |=
1699                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1700                 }
1701                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1702                         enables |=
1703                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1704                 break;
1705         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1706                 req.ring_type = ring_type;
1707                 if (BNXT_HAS_NQ(bp)) {
1708                         /* Association of cp ring with nq */
1709                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1710                         enables |=
1711                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1712                 }
1713                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1714                 break;
1715         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1716                 req.ring_type = ring_type;
1717                 req.page_size = BNXT_PAGE_SHFT;
1718                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1719                 break;
1720         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1721                 req.ring_type = ring_type;
1722                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1723
1724                 mb_pool = bp->rx_queues[0]->mb_pool;
1725                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1726                               RTE_PKTMBUF_HEADROOM;
1727                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1728                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1729
1730                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1731                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1732                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1733                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1734                 break;
1735         default:
1736                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1737                         ring_type);
1738                 HWRM_UNLOCK();
1739                 return -EINVAL;
1740         }
1741         req.enables = rte_cpu_to_le_32(enables);
1742
1743         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1744
1745         if (rc || resp->error_code) {
1746                 if (rc == 0 && resp->error_code)
1747                         rc = rte_le_to_cpu_16(resp->error_code);
1748                 switch (ring_type) {
1749                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1750                         PMD_DRV_LOG(ERR,
1751                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1752                         HWRM_UNLOCK();
1753                         return rc;
1754                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1755                         PMD_DRV_LOG(ERR,
1756                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1757                         HWRM_UNLOCK();
1758                         return rc;
1759                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1760                         PMD_DRV_LOG(ERR,
1761                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1762                                     rc);
1763                         HWRM_UNLOCK();
1764                         return rc;
1765                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1766                         PMD_DRV_LOG(ERR,
1767                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1768                         HWRM_UNLOCK();
1769                         return rc;
1770                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1771                         PMD_DRV_LOG(ERR,
1772                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1773                         HWRM_UNLOCK();
1774                         return rc;
1775                 default:
1776                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1777                         HWRM_UNLOCK();
1778                         return rc;
1779                 }
1780         }
1781
1782         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1783         HWRM_UNLOCK();
1784         return rc;
1785 }
1786
1787 int bnxt_hwrm_ring_free(struct bnxt *bp,
1788                         struct bnxt_ring *ring, uint32_t ring_type,
1789                         uint16_t cp_ring_id)
1790 {
1791         int rc;
1792         struct hwrm_ring_free_input req = {.req_type = 0 };
1793         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1794
1795         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1796
1797         req.ring_type = ring_type;
1798         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1799         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1800
1801         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1802
1803         if (rc || resp->error_code) {
1804                 if (rc == 0 && resp->error_code)
1805                         rc = rte_le_to_cpu_16(resp->error_code);
1806                 HWRM_UNLOCK();
1807
1808                 switch (ring_type) {
1809                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1810                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1811                                 rc);
1812                         return rc;
1813                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1814                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1815                                 rc);
1816                         return rc;
1817                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1818                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1819                                 rc);
1820                         return rc;
1821                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1822                         PMD_DRV_LOG(ERR,
1823                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1824                         return rc;
1825                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1826                         PMD_DRV_LOG(ERR,
1827                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1828                         return rc;
1829                 default:
1830                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1831                         return rc;
1832                 }
1833         }
1834         HWRM_UNLOCK();
1835         return 0;
1836 }
1837
1838 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1839 {
1840         int rc = 0;
1841         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1842         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1843
1844         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1845
1846         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1847         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1848         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1849         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1850
1851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1852
1853         HWRM_CHECK_RESULT();
1854
1855         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1856
1857         HWRM_UNLOCK();
1858
1859         return rc;
1860 }
1861
1862 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1863 {
1864         int rc;
1865         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1866         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1867
1868         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1869
1870         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1871
1872         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1873
1874         HWRM_CHECK_RESULT();
1875         HWRM_UNLOCK();
1876
1877         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1878         return rc;
1879 }
1880
1881 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1882 {
1883         int rc = 0;
1884         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1885         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1886
1887         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1888                 return rc;
1889
1890         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1891
1892         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1893
1894         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1895
1896         HWRM_CHECK_RESULT();
1897         HWRM_UNLOCK();
1898
1899         return rc;
1900 }
1901
1902 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1903 {
1904         int rc;
1905         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1906         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1907
1908         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1909
1910         req.update_period_ms = rte_cpu_to_le_32(0);
1911
1912         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1913
1914         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1915
1916         HWRM_CHECK_RESULT();
1917
1918         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1919
1920         HWRM_UNLOCK();
1921
1922         return rc;
1923 }
1924
1925 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1926 {
1927         int rc;
1928         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1929         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1930
1931         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1932
1933         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1934
1935         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1936
1937         HWRM_CHECK_RESULT();
1938         HWRM_UNLOCK();
1939
1940         return rc;
1941 }
1942
1943 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1944 {
1945         int rc = 0, i, j;
1946         struct hwrm_vnic_alloc_input req = { 0 };
1947         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1948
1949         if (!BNXT_HAS_RING_GRPS(bp))
1950                 goto skip_ring_grps;
1951
1952         /* map ring groups to this vnic */
1953         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1954                 vnic->start_grp_id, vnic->end_grp_id);
1955         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1956                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1957
1958         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1959         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1960         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1961         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1962
1963 skip_ring_grps:
1964         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1965         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1966
1967         if (vnic->func_default)
1968                 req.flags =
1969                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1970         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1971
1972         HWRM_CHECK_RESULT();
1973
1974         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1975         HWRM_UNLOCK();
1976         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1977         return rc;
1978 }
1979
1980 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1981                                         struct bnxt_vnic_info *vnic,
1982                                         struct bnxt_plcmodes_cfg *pmode)
1983 {
1984         int rc = 0;
1985         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1986         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1987
1988         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1989
1990         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1991
1992         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1993
1994         HWRM_CHECK_RESULT();
1995
1996         pmode->flags = rte_le_to_cpu_32(resp->flags);
1997         /* dflt_vnic bit doesn't exist in the _cfg command */
1998         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1999         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2000         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2001         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2002
2003         HWRM_UNLOCK();
2004
2005         return rc;
2006 }
2007
2008 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2009                                        struct bnxt_vnic_info *vnic,
2010                                        struct bnxt_plcmodes_cfg *pmode)
2011 {
2012         int rc = 0;
2013         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2014         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2015
2016         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2017                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2018                 return rc;
2019         }
2020
2021         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2022
2023         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2024         req.flags = rte_cpu_to_le_32(pmode->flags);
2025         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2026         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2027         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2028         req.enables = rte_cpu_to_le_32(
2029             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2030             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2031             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2032         );
2033
2034         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2035
2036         HWRM_CHECK_RESULT();
2037         HWRM_UNLOCK();
2038
2039         return rc;
2040 }
2041
2042 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2043 {
2044         int rc = 0;
2045         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2046         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2047         struct bnxt_plcmodes_cfg pmodes = { 0 };
2048         uint32_t ctx_enable_flag = 0;
2049         uint32_t enables = 0;
2050
2051         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2052                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2053                 return rc;
2054         }
2055
2056         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2057         if (rc)
2058                 return rc;
2059
2060         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2061
2062         if (BNXT_CHIP_P5(bp)) {
2063                 int dflt_rxq = vnic->start_grp_id;
2064                 struct bnxt_rx_ring_info *rxr;
2065                 struct bnxt_cp_ring_info *cpr;
2066                 struct bnxt_rx_queue *rxq;
2067                 int i;
2068
2069                 /*
2070                  * The first active receive ring is used as the VNIC
2071                  * default receive ring. If there are no active receive
2072                  * rings (all corresponding receive queues are stopped),
2073                  * the first receive ring is used.
2074                  */
2075                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2076                         rxq = bp->eth_dev->data->rx_queues[i];
2077                         if (rxq->rx_started) {
2078                                 dflt_rxq = i;
2079                                 break;
2080                         }
2081                 }
2082
2083                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2084                 rxr = rxq->rx_ring;
2085                 cpr = rxq->cp_ring;
2086
2087                 req.default_rx_ring_id =
2088                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2089                 req.default_cmpl_ring_id =
2090                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2091                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2092                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2093                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2094                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2095                         req.rx_csum_v2_mode =
2096                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2097                 }
2098                 goto config_mru;
2099         }
2100
2101         /* Only RSS support for now TBD: COS & LB */
2102         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2103         if (vnic->lb_rule != 0xffff)
2104                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2105         if (vnic->cos_rule != 0xffff)
2106                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2107         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2108                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2109                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2110         }
2111         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2112                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2113                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2114         }
2115
2116         enables |= ctx_enable_flag;
2117         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2118         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2119         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2120         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2121
2122 config_mru:
2123         req.enables = rte_cpu_to_le_32(enables);
2124         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2125         req.mru = rte_cpu_to_le_16(vnic->mru);
2126         /* Configure default VNIC only once. */
2127         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2128                 req.flags |=
2129                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2130                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2131         }
2132         if (vnic->vlan_strip)
2133                 req.flags |=
2134                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2135         if (vnic->bd_stall)
2136                 req.flags |=
2137                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2138         if (vnic->rss_dflt_cr)
2139                 req.flags |= rte_cpu_to_le_32(
2140                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2141
2142         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2143
2144         HWRM_CHECK_RESULT();
2145         HWRM_UNLOCK();
2146
2147         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2148
2149         return rc;
2150 }
2151
2152 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2153                 int16_t fw_vf_id)
2154 {
2155         int rc = 0;
2156         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2157         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2158
2159         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2160                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2161                 return rc;
2162         }
2163         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2164
2165         req.enables =
2166                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2167         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2168         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2169
2170         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2171
2172         HWRM_CHECK_RESULT();
2173
2174         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2175         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2176         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2177         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2178         vnic->mru = rte_le_to_cpu_16(resp->mru);
2179         vnic->func_default = rte_le_to_cpu_32(
2180                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2181         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2182                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2183         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2184                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2185         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2186                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2187
2188         HWRM_UNLOCK();
2189
2190         return rc;
2191 }
2192
2193 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2194                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2195 {
2196         int rc = 0;
2197         uint16_t ctx_id;
2198         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2199         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2200                                                 bp->hwrm_cmd_resp_addr;
2201
2202         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2203
2204         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2205         HWRM_CHECK_RESULT();
2206
2207         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2208         if (!BNXT_HAS_RING_GRPS(bp))
2209                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2210         else if (ctx_idx == 0)
2211                 vnic->rss_rule = ctx_id;
2212
2213         HWRM_UNLOCK();
2214
2215         return rc;
2216 }
2217
2218 static
2219 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2220                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2221 {
2222         int rc = 0;
2223         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2224         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2225                                                 bp->hwrm_cmd_resp_addr;
2226
2227         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2228                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2229                 return rc;
2230         }
2231         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2232
2233         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2234
2235         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2236
2237         HWRM_CHECK_RESULT();
2238         HWRM_UNLOCK();
2239
2240         return rc;
2241 }
2242
2243 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2244 {
2245         int rc = 0;
2246
2247         if (BNXT_CHIP_P5(bp)) {
2248                 int j;
2249
2250                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2251                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2252                                                       vnic,
2253                                                       vnic->fw_grp_ids[j]);
2254                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2255                 }
2256                 vnic->num_lb_ctxts = 0;
2257         } else {
2258                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2259                 vnic->rss_rule = INVALID_HW_RING_ID;
2260         }
2261
2262         return rc;
2263 }
2264
2265 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2266 {
2267         int rc = 0;
2268         struct hwrm_vnic_free_input req = {.req_type = 0 };
2269         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2270
2271         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2272                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2273                 return rc;
2274         }
2275
2276         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2277
2278         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2279
2280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2281
2282         HWRM_CHECK_RESULT();
2283         HWRM_UNLOCK();
2284
2285         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2286         /* Configure default VNIC again if necessary. */
2287         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2288                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2289
2290         return rc;
2291 }
2292
2293 static int
2294 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2295 {
2296         int i;
2297         int rc = 0;
2298         int nr_ctxs = vnic->num_lb_ctxts;
2299         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2300         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2301
2302         for (i = 0; i < nr_ctxs; i++) {
2303                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2304
2305                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2306                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2307                 req.hash_mode_flags = vnic->hash_mode;
2308
2309                 req.hash_key_tbl_addr =
2310                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2311
2312                 req.ring_grp_tbl_addr =
2313                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2314                                          i * HW_HASH_INDEX_SIZE);
2315                 req.ring_table_pair_index = i;
2316                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2317
2318                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2319                                             BNXT_USE_CHIMP_MB);
2320
2321                 HWRM_CHECK_RESULT();
2322                 HWRM_UNLOCK();
2323         }
2324
2325         return rc;
2326 }
2327
2328 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2329                            struct bnxt_vnic_info *vnic)
2330 {
2331         int rc = 0;
2332         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2333         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2334
2335         if (!vnic->rss_table)
2336                 return 0;
2337
2338         if (BNXT_CHIP_P5(bp))
2339                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2340
2341         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2342
2343         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2344         req.hash_mode_flags = vnic->hash_mode;
2345
2346         req.ring_grp_tbl_addr =
2347             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2348         req.hash_key_tbl_addr =
2349             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2350         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2351         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2352
2353         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2354
2355         HWRM_CHECK_RESULT();
2356         HWRM_UNLOCK();
2357
2358         return rc;
2359 }
2360
2361 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2362                         struct bnxt_vnic_info *vnic)
2363 {
2364         int rc = 0;
2365         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2366         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2367         uint16_t size;
2368
2369         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2370                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2371                 return rc;
2372         }
2373
2374         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2375
2376         req.flags = rte_cpu_to_le_32(
2377                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2378
2379         req.enables = rte_cpu_to_le_32(
2380                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2381
2382         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2383         size -= RTE_PKTMBUF_HEADROOM;
2384         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2385
2386         req.jumbo_thresh = rte_cpu_to_le_16(size);
2387         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2388
2389         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2390
2391         HWRM_CHECK_RESULT();
2392         HWRM_UNLOCK();
2393
2394         return rc;
2395 }
2396
2397 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2398                         struct bnxt_vnic_info *vnic, bool enable)
2399 {
2400         int rc = 0;
2401         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2402         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2403
2404         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2405                 if (enable)
2406                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2407                 return -ENOTSUP;
2408         }
2409
2410         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2411                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2412                 return 0;
2413         }
2414
2415         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2416
2417         if (enable) {
2418                 req.enables = rte_cpu_to_le_32(
2419                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2420                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2421                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2422                 req.flags = rte_cpu_to_le_32(
2423                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2424                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2425                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2426                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2427                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2428                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2429                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2430                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2431                 req.min_agg_len = rte_cpu_to_le_32(512);
2432         }
2433         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2434
2435         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2436
2437         HWRM_CHECK_RESULT();
2438         HWRM_UNLOCK();
2439
2440         return rc;
2441 }
2442
2443 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2444 {
2445         struct hwrm_func_cfg_input req = {0};
2446         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2447         int rc;
2448
2449         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2450         req.enables = rte_cpu_to_le_32(
2451                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2452         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2453         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2454
2455         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2456
2457         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2458         HWRM_CHECK_RESULT();
2459         HWRM_UNLOCK();
2460
2461         bp->pf->vf_info[vf].random_mac = false;
2462
2463         return rc;
2464 }
2465
2466 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2467                                   uint64_t *dropped)
2468 {
2469         int rc = 0;
2470         struct hwrm_func_qstats_input req = {.req_type = 0};
2471         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2472
2473         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2474
2475         req.fid = rte_cpu_to_le_16(fid);
2476
2477         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2478
2479         HWRM_CHECK_RESULT();
2480
2481         if (dropped)
2482                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2483
2484         HWRM_UNLOCK();
2485
2486         return rc;
2487 }
2488
2489 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2490                           struct rte_eth_stats *stats,
2491                           struct hwrm_func_qstats_output *func_qstats)
2492 {
2493         int rc = 0;
2494         struct hwrm_func_qstats_input req = {.req_type = 0};
2495         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2496
2497         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2498
2499         req.fid = rte_cpu_to_le_16(fid);
2500
2501         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2502
2503         HWRM_CHECK_RESULT();
2504         if (func_qstats)
2505                 memcpy(func_qstats, resp,
2506                        sizeof(struct hwrm_func_qstats_output));
2507
2508         if (!stats)
2509                 goto exit;
2510
2511         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2512         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2513         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2514         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2515         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2516         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2517
2518         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2519         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2520         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2521         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2522         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2523         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2524
2525         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2526         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2527         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2528
2529 exit:
2530         HWRM_UNLOCK();
2531
2532         return rc;
2533 }
2534
2535 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2536 {
2537         int rc = 0;
2538         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2539         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2540
2541         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2542
2543         req.fid = rte_cpu_to_le_16(fid);
2544
2545         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2546
2547         HWRM_CHECK_RESULT();
2548         HWRM_UNLOCK();
2549
2550         return rc;
2551 }
2552
2553 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2554 {
2555         unsigned int i;
2556         int rc = 0;
2557
2558         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2559                 struct bnxt_tx_queue *txq;
2560                 struct bnxt_rx_queue *rxq;
2561                 struct bnxt_cp_ring_info *cpr;
2562
2563                 if (i >= bp->rx_cp_nr_rings) {
2564                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2565                         cpr = txq->cp_ring;
2566                 } else {
2567                         rxq = bp->rx_queues[i];
2568                         cpr = rxq->cp_ring;
2569                 }
2570
2571                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2572                 if (rc)
2573                         return rc;
2574         }
2575         return 0;
2576 }
2577
2578 static int
2579 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2580 {
2581         int rc;
2582         unsigned int i;
2583         struct bnxt_cp_ring_info *cpr;
2584
2585         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2586
2587                 if (i >= bp->rx_cp_nr_rings) {
2588                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2589                 } else {
2590                         cpr = bp->rx_queues[i]->cp_ring;
2591                         if (BNXT_HAS_RING_GRPS(bp))
2592                                 bp->grp_info[i].fw_stats_ctx = -1;
2593                 }
2594                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2595                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2596                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2597                         if (rc)
2598                                 return rc;
2599                 }
2600         }
2601         return 0;
2602 }
2603
2604 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2605 {
2606         unsigned int i;
2607         int rc = 0;
2608
2609         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2610                 struct bnxt_tx_queue *txq;
2611                 struct bnxt_rx_queue *rxq;
2612                 struct bnxt_cp_ring_info *cpr;
2613
2614                 if (i >= bp->rx_cp_nr_rings) {
2615                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2616                         cpr = txq->cp_ring;
2617                 } else {
2618                         rxq = bp->rx_queues[i];
2619                         cpr = rxq->cp_ring;
2620                 }
2621
2622                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2623
2624                 if (rc)
2625                         return rc;
2626         }
2627         return rc;
2628 }
2629
2630 static int
2631 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2632 {
2633         uint16_t idx;
2634         uint32_t rc = 0;
2635
2636         if (!BNXT_HAS_RING_GRPS(bp))
2637                 return 0;
2638
2639         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2640
2641                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2642                         continue;
2643
2644                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2645
2646                 if (rc)
2647                         return rc;
2648         }
2649         return rc;
2650 }
2651
2652 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2653 {
2654         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2655
2656         bnxt_hwrm_ring_free(bp, cp_ring,
2657                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2658                             INVALID_HW_RING_ID);
2659         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2660         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2661                                      sizeof(*cpr->cp_desc_ring));
2662         cpr->cp_raw_cons = 0;
2663         cpr->valid = 0;
2664 }
2665
2666 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2667 {
2668         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2669
2670         bnxt_hwrm_ring_free(bp, cp_ring,
2671                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2672                         INVALID_HW_RING_ID);
2673         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2674         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2675                         sizeof(*cpr->cp_desc_ring));
2676         cpr->cp_raw_cons = 0;
2677         cpr->valid = 0;
2678 }
2679
2680 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2681 {
2682         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2683         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2684         struct bnxt_ring *ring = rxr->rx_ring_struct;
2685         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2686
2687         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2688                 bnxt_hwrm_ring_free(bp, ring,
2689                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2690                                     cpr->cp_ring_struct->fw_ring_id);
2691                 ring->fw_ring_id = INVALID_HW_RING_ID;
2692                 if (BNXT_HAS_RING_GRPS(bp))
2693                         bp->grp_info[queue_index].rx_fw_ring_id =
2694                                                         INVALID_HW_RING_ID;
2695         }
2696         ring = rxr->ag_ring_struct;
2697         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2698                 bnxt_hwrm_ring_free(bp, ring,
2699                                     BNXT_CHIP_P5(bp) ?
2700                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2701                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2702                                     cpr->cp_ring_struct->fw_ring_id);
2703                 if (BNXT_HAS_RING_GRPS(bp))
2704                         bp->grp_info[queue_index].ag_fw_ring_id =
2705                                                         INVALID_HW_RING_ID;
2706         }
2707         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2708                 bnxt_free_cp_ring(bp, cpr);
2709
2710         if (BNXT_HAS_RING_GRPS(bp))
2711                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2712 }
2713
2714 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2715 {
2716         int rc;
2717         struct hwrm_ring_reset_input req = {.req_type = 0 };
2718         struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2719
2720         HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2721
2722         req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2723         req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2724         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2725
2726         HWRM_CHECK_RESULT();
2727
2728         HWRM_UNLOCK();
2729
2730         return rc;
2731 }
2732
2733 static int
2734 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2735 {
2736         unsigned int i;
2737
2738         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2739                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2740                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2741                 struct bnxt_ring *ring = txr->tx_ring_struct;
2742                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2743
2744                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2745                         bnxt_hwrm_ring_free(bp, ring,
2746                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX,
2747                                         cpr->cp_ring_struct->fw_ring_id);
2748                         ring->fw_ring_id = INVALID_HW_RING_ID;
2749                         memset(txr->tx_desc_ring, 0,
2750                                         txr->tx_ring_struct->ring_size *
2751                                         sizeof(*txr->tx_desc_ring));
2752                         memset(txr->tx_buf_ring, 0,
2753                                         txr->tx_ring_struct->ring_size *
2754                                         sizeof(*txr->tx_buf_ring));
2755                         txr->tx_raw_prod = 0;
2756                         txr->tx_raw_cons = 0;
2757                 }
2758                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2759                         bnxt_free_cp_ring(bp, cpr);
2760                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2761                 }
2762         }
2763
2764         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2765                 bnxt_free_hwrm_rx_ring(bp, i);
2766
2767         return 0;
2768 }
2769
2770 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2771 {
2772         uint16_t i;
2773         uint32_t rc = 0;
2774
2775         if (!BNXT_HAS_RING_GRPS(bp))
2776                 return 0;
2777
2778         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2779                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2780                 if (rc)
2781                         return rc;
2782         }
2783         return rc;
2784 }
2785
2786 /*
2787  * HWRM utility functions
2788  */
2789
2790 void bnxt_free_hwrm_resources(struct bnxt *bp)
2791 {
2792         /* Release memzone */
2793         rte_free(bp->hwrm_cmd_resp_addr);
2794         rte_free(bp->hwrm_short_cmd_req_addr);
2795         bp->hwrm_cmd_resp_addr = NULL;
2796         bp->hwrm_short_cmd_req_addr = NULL;
2797         bp->hwrm_cmd_resp_dma_addr = 0;
2798         bp->hwrm_short_cmd_req_dma_addr = 0;
2799 }
2800
2801 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2802 {
2803         struct rte_pci_device *pdev = bp->pdev;
2804         char type[RTE_MEMZONE_NAMESIZE];
2805
2806         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2807                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2808         bp->max_resp_len = BNXT_PAGE_SIZE;
2809         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2810         if (bp->hwrm_cmd_resp_addr == NULL)
2811                 return -ENOMEM;
2812         bp->hwrm_cmd_resp_dma_addr =
2813                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2814         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2815                 PMD_DRV_LOG(ERR,
2816                         "unable to map response address to physical memory\n");
2817                 return -ENOMEM;
2818         }
2819         rte_spinlock_init(&bp->hwrm_lock);
2820
2821         return 0;
2822 }
2823
2824 int
2825 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2826 {
2827         int rc = 0;
2828
2829         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2830                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2831                 if (rc)
2832                         return rc;
2833         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2834                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2835                 if (rc)
2836                         return rc;
2837         }
2838
2839         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2840         return rc;
2841 }
2842
2843 static int
2844 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2845 {
2846         struct bnxt_filter_info *filter;
2847         int rc = 0;
2848
2849         STAILQ_FOREACH(filter, &vnic->filter, next) {
2850                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2851                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2852                 bnxt_free_filter(bp, filter);
2853         }
2854         return rc;
2855 }
2856
2857 static int
2858 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2859 {
2860         struct bnxt_filter_info *filter;
2861         struct rte_flow *flow;
2862         int rc = 0;
2863
2864         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2865                 flow = STAILQ_FIRST(&vnic->flow_list);
2866                 filter = flow->filter;
2867                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2868                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2869
2870                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2871                 rte_free(flow);
2872         }
2873         return rc;
2874 }
2875
2876 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2877 {
2878         struct bnxt_filter_info *filter;
2879         int rc = 0;
2880
2881         STAILQ_FOREACH(filter, &vnic->filter, next) {
2882                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2883                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2884                                                      filter);
2885                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2886                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2887                                                          filter);
2888                 else
2889                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2890                                                      filter);
2891                 if (rc)
2892                         break;
2893         }
2894         return rc;
2895 }
2896
2897 static void
2898 bnxt_free_tunnel_ports(struct bnxt *bp)
2899 {
2900         if (bp->vxlan_port_cnt)
2901                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2902                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2903
2904         if (bp->geneve_port_cnt)
2905                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2906                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2907 }
2908
2909 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2910 {
2911         int i;
2912
2913         if (bp->vnic_info == NULL)
2914                 return;
2915
2916         /*
2917          * Cleanup VNICs in reverse order, to make sure the L2 filter
2918          * from vnic0 is last to be cleaned up.
2919          */
2920         for (i = bp->max_vnics - 1; i >= 0; i--) {
2921                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2922
2923                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2924                         continue;
2925
2926                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2927
2928                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2929
2930                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2931
2932                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2933
2934                 bnxt_hwrm_vnic_free(bp, vnic);
2935
2936                 rte_free(vnic->fw_grp_ids);
2937         }
2938         /* Ring resources */
2939         bnxt_free_all_hwrm_rings(bp);
2940         bnxt_free_all_hwrm_ring_grps(bp);
2941         bnxt_free_all_hwrm_stat_ctxs(bp);
2942         bnxt_free_tunnel_ports(bp);
2943 }
2944
2945 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2946 {
2947         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2948
2949         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2950                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2951
2952         switch (conf_link_speed) {
2953         case ETH_LINK_SPEED_10M_HD:
2954         case ETH_LINK_SPEED_100M_HD:
2955                 /* FALLTHROUGH */
2956                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2957         }
2958         return hw_link_duplex;
2959 }
2960
2961 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2962 {
2963         return !conf_link;
2964 }
2965
2966 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2967                                           uint16_t pam4_link)
2968 {
2969         uint16_t eth_link_speed = 0;
2970
2971         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2972                 return ETH_LINK_SPEED_AUTONEG;
2973
2974         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2975         case ETH_LINK_SPEED_100M:
2976         case ETH_LINK_SPEED_100M_HD:
2977                 /* FALLTHROUGH */
2978                 eth_link_speed =
2979                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2980                 break;
2981         case ETH_LINK_SPEED_1G:
2982                 eth_link_speed =
2983                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2984                 break;
2985         case ETH_LINK_SPEED_2_5G:
2986                 eth_link_speed =
2987                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2988                 break;
2989         case ETH_LINK_SPEED_10G:
2990                 eth_link_speed =
2991                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2992                 break;
2993         case ETH_LINK_SPEED_20G:
2994                 eth_link_speed =
2995                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2996                 break;
2997         case ETH_LINK_SPEED_25G:
2998                 eth_link_speed =
2999                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3000                 break;
3001         case ETH_LINK_SPEED_40G:
3002                 eth_link_speed =
3003                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3004                 break;
3005         case ETH_LINK_SPEED_50G:
3006                 eth_link_speed = pam4_link ?
3007                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3008                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3009                 break;
3010         case ETH_LINK_SPEED_100G:
3011                 eth_link_speed = pam4_link ?
3012                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3013                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3014                 break;
3015         case ETH_LINK_SPEED_200G:
3016                 eth_link_speed =
3017                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3018                 break;
3019         default:
3020                 PMD_DRV_LOG(ERR,
3021                         "Unsupported link speed %d; default to AUTO\n",
3022                         conf_link_speed);
3023                 break;
3024         }
3025         return eth_link_speed;
3026 }
3027
3028 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3029                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3030                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3031                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3032                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3033
3034 static int bnxt_validate_link_speed(struct bnxt *bp)
3035 {
3036         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3037         uint16_t port_id = bp->eth_dev->data->port_id;
3038         uint32_t link_speed_capa;
3039         uint32_t one_speed;
3040
3041         if (link_speed == ETH_LINK_SPEED_AUTONEG)
3042                 return 0;
3043
3044         link_speed_capa = bnxt_get_speed_capabilities(bp);
3045
3046         if (link_speed & ETH_LINK_SPEED_FIXED) {
3047                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3048
3049                 if (one_speed & (one_speed - 1)) {
3050                         PMD_DRV_LOG(ERR,
3051                                 "Invalid advertised speeds (%u) for port %u\n",
3052                                 link_speed, port_id);
3053                         return -EINVAL;
3054                 }
3055                 if ((one_speed & link_speed_capa) != one_speed) {
3056                         PMD_DRV_LOG(ERR,
3057                                 "Unsupported advertised speed (%u) for port %u\n",
3058                                 link_speed, port_id);
3059                         return -EINVAL;
3060                 }
3061         } else {
3062                 if (!(link_speed & link_speed_capa)) {
3063                         PMD_DRV_LOG(ERR,
3064                                 "Unsupported advertised speeds (%u) for port %u\n",
3065                                 link_speed, port_id);
3066                         return -EINVAL;
3067                 }
3068         }
3069         return 0;
3070 }
3071
3072 static uint16_t
3073 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3074 {
3075         uint16_t ret = 0;
3076
3077         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3078                 if (bp->link_info->support_speeds)
3079                         return bp->link_info->support_speeds;
3080                 link_speed = BNXT_SUPPORTED_SPEEDS;
3081         }
3082
3083         if (link_speed & ETH_LINK_SPEED_100M)
3084                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3085         if (link_speed & ETH_LINK_SPEED_100M_HD)
3086                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3087         if (link_speed & ETH_LINK_SPEED_1G)
3088                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3089         if (link_speed & ETH_LINK_SPEED_2_5G)
3090                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3091         if (link_speed & ETH_LINK_SPEED_10G)
3092                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3093         if (link_speed & ETH_LINK_SPEED_20G)
3094                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3095         if (link_speed & ETH_LINK_SPEED_25G)
3096                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3097         if (link_speed & ETH_LINK_SPEED_40G)
3098                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3099         if (link_speed & ETH_LINK_SPEED_50G)
3100                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3101         if (link_speed & ETH_LINK_SPEED_100G)
3102                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3103         if (link_speed & ETH_LINK_SPEED_200G)
3104                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3105         return ret;
3106 }
3107
3108 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3109 {
3110         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3111
3112         switch (hw_link_speed) {
3113         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3114                 eth_link_speed = ETH_SPEED_NUM_100M;
3115                 break;
3116         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3117                 eth_link_speed = ETH_SPEED_NUM_1G;
3118                 break;
3119         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3120                 eth_link_speed = ETH_SPEED_NUM_2_5G;
3121                 break;
3122         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3123                 eth_link_speed = ETH_SPEED_NUM_10G;
3124                 break;
3125         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3126                 eth_link_speed = ETH_SPEED_NUM_20G;
3127                 break;
3128         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3129                 eth_link_speed = ETH_SPEED_NUM_25G;
3130                 break;
3131         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3132                 eth_link_speed = ETH_SPEED_NUM_40G;
3133                 break;
3134         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3135                 eth_link_speed = ETH_SPEED_NUM_50G;
3136                 break;
3137         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3138                 eth_link_speed = ETH_SPEED_NUM_100G;
3139                 break;
3140         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3141                 eth_link_speed = ETH_SPEED_NUM_200G;
3142                 break;
3143         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3144         default:
3145                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3146                         hw_link_speed);
3147                 break;
3148         }
3149         return eth_link_speed;
3150 }
3151
3152 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3153 {
3154         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3155
3156         switch (hw_link_duplex) {
3157         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3158         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3159                 /* FALLTHROUGH */
3160                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3161                 break;
3162         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3163                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3164                 break;
3165         default:
3166                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3167                         hw_link_duplex);
3168                 break;
3169         }
3170         return eth_link_duplex;
3171 }
3172
3173 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3174 {
3175         int rc = 0;
3176         struct bnxt_link_info *link_info = bp->link_info;
3177
3178         rc = bnxt_hwrm_port_phy_qcaps(bp);
3179         if (rc)
3180                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3181
3182         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3183         if (rc) {
3184                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3185                 goto exit;
3186         }
3187
3188         if (link_info->link_speed)
3189                 link->link_speed =
3190                         bnxt_parse_hw_link_speed(link_info->link_speed);
3191         else
3192                 link->link_speed = ETH_SPEED_NUM_NONE;
3193         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3194         link->link_status = link_info->link_up;
3195         link->link_autoneg = link_info->auto_mode ==
3196                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3197                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3198 exit:
3199         return rc;
3200 }
3201
3202 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3203 {
3204         int rc = 0;
3205         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3206         struct bnxt_link_info link_req;
3207         uint16_t speed, autoneg;
3208
3209         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3210                 return 0;
3211
3212         rc = bnxt_validate_link_speed(bp);
3213         if (rc)
3214                 goto error;
3215
3216         memset(&link_req, 0, sizeof(link_req));
3217         link_req.link_up = link_up;
3218         if (!link_up)
3219                 goto port_phy_cfg;
3220
3221         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3222         if (BNXT_CHIP_P5(bp) &&
3223             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3224                 /* 40G is not supported as part of media auto detect.
3225                  * The speed should be forced and autoneg disabled
3226                  * to configure 40G speed.
3227                  */
3228                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3229                 autoneg = 0;
3230         }
3231
3232         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3233         if (bp->link_info->auto_link_speed == 0 &&
3234             bp->link_info->link_signal_mode &&
3235             bp->link_info->auto_pam4_link_speeds == 0)
3236                 autoneg = 0;
3237
3238         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3239                                           bp->link_info->link_signal_mode);
3240         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3241         /* Autoneg can be done only when the FW allows.
3242          * When user configures fixed speed of 40G and later changes to
3243          * any other speed, auto_link_speed/force_link_speed is still set
3244          * to 40G until link comes up at new speed.
3245          */
3246         if (autoneg == 1 &&
3247             !(!BNXT_CHIP_P5(bp) &&
3248               (bp->link_info->auto_link_speed ||
3249                bp->link_info->force_link_speed))) {
3250                 link_req.phy_flags |=
3251                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3252                 link_req.auto_link_speed_mask =
3253                         bnxt_parse_eth_link_speed_mask(bp,
3254                                                        dev_conf->link_speeds);
3255         } else {
3256                 if (bp->link_info->phy_type ==
3257                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3258                     bp->link_info->phy_type ==
3259                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3260                     bp->link_info->media_type ==
3261                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3262                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3263                         return -EINVAL;
3264                 }
3265
3266                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3267                 /* If user wants a particular speed try that first. */
3268                 if (speed)
3269                         link_req.link_speed = speed;
3270                 else if (bp->link_info->force_pam4_link_speed)
3271                         link_req.link_speed =
3272                                 bp->link_info->force_pam4_link_speed;
3273                 else if (bp->link_info->auto_pam4_link_speeds)
3274                         link_req.link_speed =
3275                                 bp->link_info->auto_pam4_link_speeds;
3276                 else if (bp->link_info->support_pam4_speeds)
3277                         link_req.link_speed =
3278                                 bp->link_info->support_pam4_speeds;
3279                 else if (bp->link_info->force_link_speed)
3280                         link_req.link_speed = bp->link_info->force_link_speed;
3281                 else
3282                         link_req.link_speed = bp->link_info->auto_link_speed;
3283                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3284                  * zero. Use the auto_link_speed.
3285                  */
3286                 if (bp->link_info->auto_link_speed != 0 &&
3287                     bp->link_info->auto_pam4_link_speeds == 0)
3288                         link_req.link_speed = bp->link_info->auto_link_speed;
3289         }
3290         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3291         link_req.auto_pause = bp->link_info->auto_pause;
3292         link_req.force_pause = bp->link_info->force_pause;
3293
3294 port_phy_cfg:
3295         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3296         if (rc) {
3297                 PMD_DRV_LOG(ERR,
3298                         "Set link config failed with rc %d\n", rc);
3299         }
3300
3301 error:
3302         return rc;
3303 }
3304
3305 /* JIRA 22088 */
3306 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3307 {
3308         struct hwrm_func_qcfg_input req = {0};
3309         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3310         uint16_t flags;
3311         int rc = 0;
3312         bp->func_svif = BNXT_SVIF_INVALID;
3313         uint16_t svif_info;
3314
3315         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3316         req.fid = rte_cpu_to_le_16(0xffff);
3317
3318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3319
3320         HWRM_CHECK_RESULT();
3321
3322         /* Hard Coded.. 0xfff VLAN ID mask */
3323         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3324
3325         svif_info = rte_le_to_cpu_16(resp->svif_info);
3326         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3327                 bp->func_svif = svif_info &
3328                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3329
3330         flags = rte_le_to_cpu_16(resp->flags);
3331         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3332                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3333
3334         if (BNXT_VF(bp) &&
3335             !BNXT_VF_IS_TRUSTED(bp) &&
3336             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3337                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3338                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3339         } else if (BNXT_VF(bp) &&
3340                    BNXT_VF_IS_TRUSTED(bp) &&
3341                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3342                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3343                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3344         }
3345
3346         if (mtu)
3347                 *mtu = rte_le_to_cpu_16(resp->mtu);
3348
3349         switch (resp->port_partition_type) {
3350         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3351         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3352         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3353                 /* FALLTHROUGH */
3354                 bp->flags |= BNXT_FLAG_NPAR_PF;
3355                 break;
3356         default:
3357                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3358                 break;
3359         }
3360
3361         bp->legacy_db_size =
3362                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3363
3364         HWRM_UNLOCK();
3365
3366         return rc;
3367 }
3368
3369 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3370 {
3371         struct hwrm_func_qcfg_input req = {0};
3372         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3373         int rc;
3374
3375         if (!BNXT_VF_IS_TRUSTED(bp))
3376                 return 0;
3377
3378         if (!bp->parent)
3379                 return -EINVAL;
3380
3381         bp->parent->fid = BNXT_PF_FID_INVALID;
3382
3383         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3384
3385         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3386
3387         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3388
3389         HWRM_CHECK_RESULT_SILENT();
3390
3391         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3392         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3393         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3394         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3395
3396         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3397         if (bp->parent->vnic == 0) {
3398                 PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
3399                 /* Use hard-coded values appropriate for current Wh+ fw. */
3400                 if (bp->parent->fid == 2)
3401                         bp->parent->vnic = 0x100;
3402                 else
3403                         bp->parent->vnic = 1;
3404         }
3405
3406         HWRM_UNLOCK();
3407
3408         return 0;
3409 }
3410
3411 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3412                                  uint16_t *vnic_id, uint16_t *svif)
3413 {
3414         struct hwrm_func_qcfg_input req = {0};
3415         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3416         uint16_t svif_info;
3417         int rc = 0;
3418
3419         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3420         req.fid = rte_cpu_to_le_16(fid);
3421
3422         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3423
3424         HWRM_CHECK_RESULT();
3425
3426         if (vnic_id)
3427                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3428
3429         svif_info = rte_le_to_cpu_16(resp->svif_info);
3430         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3431                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3432
3433         HWRM_UNLOCK();
3434
3435         return rc;
3436 }
3437
3438 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3439 {
3440         struct hwrm_port_mac_qcfg_input req = {0};
3441         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3442         uint16_t port_svif_info;
3443         int rc;
3444
3445         bp->port_svif = BNXT_SVIF_INVALID;
3446
3447         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3448                 return 0;
3449
3450         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3451
3452         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3453
3454         HWRM_CHECK_RESULT_SILENT();
3455
3456         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3457         if (port_svif_info &
3458             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3459                 bp->port_svif = port_svif_info &
3460                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3461
3462         HWRM_UNLOCK();
3463
3464         return 0;
3465 }
3466
3467 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3468                                  struct bnxt_pf_resource_info *pf_resc)
3469 {
3470         struct hwrm_func_cfg_input req = {0};
3471         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3472         uint32_t enables;
3473         int rc;
3474
3475         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3476                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3477                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3478                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3479                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3480                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3481                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3482                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3483                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3484
3485         if (BNXT_HAS_RING_GRPS(bp)) {
3486                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3487                 req.num_hw_ring_grps =
3488                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3489         } else if (BNXT_HAS_NQ(bp)) {
3490                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3491                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3492         }
3493
3494         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3495         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3496         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3497         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3498         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3499         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3500         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3501         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3502         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3503         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3504         req.fid = rte_cpu_to_le_16(0xffff);
3505         req.enables = rte_cpu_to_le_32(enables);
3506
3507         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3508
3509         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3510
3511         HWRM_CHECK_RESULT();
3512         HWRM_UNLOCK();
3513
3514         return rc;
3515 }
3516
3517 /* min values are the guaranteed resources and max values are subject
3518  * to availability. The strategy for now is to keep both min & max
3519  * values the same.
3520  */
3521 static void
3522 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3523                               struct hwrm_func_vf_resource_cfg_input *req,
3524                               int num_vfs)
3525 {
3526         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3527                                                (num_vfs + 1));
3528         req->min_rsscos_ctx = req->max_rsscos_ctx;
3529         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3530         req->min_stat_ctx = req->max_stat_ctx;
3531         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3532                                                (num_vfs + 1));
3533         req->min_cmpl_rings = req->max_cmpl_rings;
3534         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3535         req->min_tx_rings = req->max_tx_rings;
3536         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3537         req->min_rx_rings = req->max_rx_rings;
3538         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3539         req->min_l2_ctxs = req->max_l2_ctxs;
3540         /* TODO: For now, do not support VMDq/RFS on VFs. */
3541         req->max_vnics = rte_cpu_to_le_16(1);
3542         req->min_vnics = req->max_vnics;
3543         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3544                                                  (num_vfs + 1));
3545         req->min_hw_ring_grps = req->max_hw_ring_grps;
3546         req->flags =
3547          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3548 }
3549
3550 static void
3551 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3552                               struct hwrm_func_cfg_input *req,
3553                               int num_vfs)
3554 {
3555         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3556                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3557                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3558                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3559                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3560                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3561                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3562                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3563                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3564                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3565
3566         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3567                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3568                                     BNXT_NUM_VLANS);
3569         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3570         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3571                                                 (num_vfs + 1));
3572         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3573         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3574                                                (num_vfs + 1));
3575         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3576         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3577         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3578         /* TODO: For now, do not support VMDq/RFS on VFs. */
3579         req->num_vnics = rte_cpu_to_le_16(1);
3580         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3581                                                  (num_vfs + 1));
3582 }
3583
3584 /* Update the port wide resource values based on how many resources
3585  * got allocated to the VF.
3586  */
3587 static int bnxt_update_max_resources(struct bnxt *bp,
3588                                      int vf)
3589 {
3590         struct hwrm_func_qcfg_input req = {0};
3591         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3592         int rc;
3593
3594         /* Get the actual allocated values now */
3595         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3596         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3597         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3598         HWRM_CHECK_RESULT();
3599
3600         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3601         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3602         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3603         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3604         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3605         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3606         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3607
3608         HWRM_UNLOCK();
3609
3610         return 0;
3611 }
3612
3613 /* Update the PF resource values based on how many resources
3614  * got allocated to it.
3615  */
3616 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3617 {
3618         struct hwrm_func_qcfg_input req = {0};
3619         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3620         int rc;
3621
3622         /* Get the actual allocated values now */
3623         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3624         req.fid = rte_cpu_to_le_16(0xffff);
3625         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3626         HWRM_CHECK_RESULT();
3627
3628         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3629         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3630         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3631         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3632         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3633         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3634         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3635         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3636
3637         HWRM_UNLOCK();
3638
3639         return 0;
3640 }
3641
3642 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3643 {
3644         struct hwrm_func_qcfg_input req = {0};
3645         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3646         int rc;
3647
3648         /* Check for zero MAC address */
3649         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3650         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3651         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3652         HWRM_CHECK_RESULT();
3653         rc = rte_le_to_cpu_16(resp->vlan);
3654
3655         HWRM_UNLOCK();
3656
3657         return rc;
3658 }
3659
3660 static int bnxt_query_pf_resources(struct bnxt *bp,
3661                                    struct bnxt_pf_resource_info *pf_resc)
3662 {
3663         struct hwrm_func_qcfg_input req = {0};
3664         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3665         int rc;
3666
3667         /* And copy the allocated numbers into the pf struct */
3668         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3669         req.fid = rte_cpu_to_le_16(0xffff);
3670         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3671         HWRM_CHECK_RESULT();
3672
3673         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3674         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3675         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3676         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3677         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3678         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3679         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3680         bp->pf->evb_mode = resp->evb_mode;
3681
3682         HWRM_UNLOCK();
3683
3684         return rc;
3685 }
3686
3687 static void
3688 bnxt_calculate_pf_resources(struct bnxt *bp,
3689                             struct bnxt_pf_resource_info *pf_resc,
3690                             int num_vfs)
3691 {
3692         if (!num_vfs) {
3693                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3694                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3695                 pf_resc->num_cp_rings = bp->max_cp_rings;
3696                 pf_resc->num_tx_rings = bp->max_tx_rings;
3697                 pf_resc->num_rx_rings = bp->max_rx_rings;
3698                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3699                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3700
3701                 return;
3702         }
3703
3704         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3705                                    bp->max_rsscos_ctx % (num_vfs + 1);
3706         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3707                                  bp->max_stat_ctx % (num_vfs + 1);
3708         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3709                                 bp->max_cp_rings % (num_vfs + 1);
3710         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3711                                 bp->max_tx_rings % (num_vfs + 1);
3712         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3713                                 bp->max_rx_rings % (num_vfs + 1);
3714         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3715                                bp->max_l2_ctx % (num_vfs + 1);
3716         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3717                                     bp->max_ring_grps % (num_vfs + 1);
3718 }
3719
3720 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3721 {
3722         struct bnxt_pf_resource_info pf_resc = { 0 };
3723         int rc;
3724
3725         if (!BNXT_PF(bp)) {
3726                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3727                 return -EINVAL;
3728         }
3729
3730         rc = bnxt_hwrm_func_qcaps(bp);
3731         if (rc)
3732                 return rc;
3733
3734         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3735
3736         bp->pf->func_cfg_flags &=
3737                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3738                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3739         bp->pf->func_cfg_flags |=
3740                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3741
3742         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3743         if (rc)
3744                 return rc;
3745
3746         rc = bnxt_update_max_resources_pf_only(bp);
3747
3748         return rc;
3749 }
3750
3751 static int
3752 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3753 {
3754         size_t req_buf_sz, sz;
3755         int i, rc;
3756
3757         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3758         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3759                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3760         if (bp->pf->vf_req_buf == NULL) {
3761                 return -ENOMEM;
3762         }
3763
3764         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3765                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3766
3767         for (i = 0; i < num_vfs; i++)
3768                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3769                                              (i * HWRM_MAX_REQ_LEN);
3770
3771         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3772         if (rc)
3773                 rte_free(bp->pf->vf_req_buf);
3774
3775         return rc;
3776 }
3777
3778 static int
3779 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3780 {
3781         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3782         struct hwrm_func_vf_resource_cfg_input req = {0};
3783         int i, rc = 0;
3784
3785         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3786         bp->pf->active_vfs = 0;
3787         for (i = 0; i < num_vfs; i++) {
3788                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3789                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3790                 rc = bnxt_hwrm_send_message(bp,
3791                                             &req,
3792                                             sizeof(req),
3793                                             BNXT_USE_CHIMP_MB);
3794                 if (rc || resp->error_code) {
3795                         PMD_DRV_LOG(ERR,
3796                                 "Failed to initialize VF %d\n", i);
3797                         PMD_DRV_LOG(ERR,
3798                                 "Not all VFs available. (%d, %d)\n",
3799                                 rc, resp->error_code);
3800                         HWRM_UNLOCK();
3801
3802                         /* If the first VF configuration itself fails,
3803                          * unregister the vf_fwd_request buffer.
3804                          */
3805                         if (i == 0)
3806                                 bnxt_hwrm_func_buf_unrgtr(bp);
3807                         break;
3808                 }
3809                 HWRM_UNLOCK();
3810
3811                 /* Update the max resource values based on the resource values
3812                  * allocated to the VF.
3813                  */
3814                 bnxt_update_max_resources(bp, i);
3815                 bp->pf->active_vfs++;
3816                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3817         }
3818
3819         return 0;
3820 }
3821
3822 static int
3823 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3824 {
3825         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3826         struct hwrm_func_cfg_input req = {0};
3827         int i, rc;
3828
3829         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3830
3831         bp->pf->active_vfs = 0;
3832         for (i = 0; i < num_vfs; i++) {
3833                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3834                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3835                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3836                 rc = bnxt_hwrm_send_message(bp,
3837                                             &req,
3838                                             sizeof(req),
3839                                             BNXT_USE_CHIMP_MB);
3840
3841                 /* Clear enable flag for next pass */
3842                 req.enables &= ~rte_cpu_to_le_32(
3843                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3844
3845                 if (rc || resp->error_code) {
3846                         PMD_DRV_LOG(ERR,
3847                                 "Failed to initialize VF %d\n", i);
3848                         PMD_DRV_LOG(ERR,
3849                                 "Not all VFs available. (%d, %d)\n",
3850                                 rc, resp->error_code);
3851                         HWRM_UNLOCK();
3852
3853                         /* If the first VF configuration itself fails,
3854                          * unregister the vf_fwd_request buffer.
3855                          */
3856                         if (i == 0)
3857                                 bnxt_hwrm_func_buf_unrgtr(bp);
3858                         break;
3859                 }
3860
3861                 HWRM_UNLOCK();
3862
3863                 /* Update the max resource values based on the resource values
3864                  * allocated to the VF.
3865                  */
3866                 bnxt_update_max_resources(bp, i);
3867                 bp->pf->active_vfs++;
3868                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3869         }
3870
3871         return 0;
3872 }
3873
3874 static void
3875 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3876 {
3877         if (bp->flags & BNXT_FLAG_NEW_RM)
3878                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3879         else
3880                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3881 }
3882
3883 static void
3884 bnxt_update_pf_resources(struct bnxt *bp,
3885                          struct bnxt_pf_resource_info *pf_resc)
3886 {
3887         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3888         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3889         bp->max_cp_rings = pf_resc->num_cp_rings;
3890         bp->max_tx_rings = pf_resc->num_tx_rings;
3891         bp->max_rx_rings = pf_resc->num_rx_rings;
3892         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3893 }
3894
3895 static int32_t
3896 bnxt_configure_pf_resources(struct bnxt *bp,
3897                             struct bnxt_pf_resource_info *pf_resc)
3898 {
3899         /*
3900          * We're using STD_TX_RING_MODE here which will limit the TX
3901          * rings. This will allow QoS to function properly. Not setting this
3902          * will cause PF rings to break bandwidth settings.
3903          */
3904         bp->pf->func_cfg_flags &=
3905                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3906                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3907         bp->pf->func_cfg_flags |=
3908                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3909         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3910 }
3911
3912 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3913 {
3914         struct bnxt_pf_resource_info pf_resc = { 0 };
3915         int rc;
3916
3917         if (!BNXT_PF(bp)) {
3918                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3919                 return -EINVAL;
3920         }
3921
3922         rc = bnxt_hwrm_func_qcaps(bp);
3923         if (rc)
3924                 return rc;
3925
3926         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3927
3928         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3929         if (rc)
3930                 return rc;
3931
3932         rc = bnxt_query_pf_resources(bp, &pf_resc);
3933         if (rc)
3934                 return rc;
3935
3936         /*
3937          * Now, create and register a buffer to hold forwarded VF requests
3938          */
3939         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3940         if (rc)
3941                 return rc;
3942
3943         bnxt_configure_vf_resources(bp, num_vfs);
3944
3945         bnxt_update_pf_resources(bp, &pf_resc);
3946
3947         return 0;
3948 }
3949
3950 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3951 {
3952         struct hwrm_func_cfg_input req = {0};
3953         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3954         int rc;
3955
3956         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3957
3958         req.fid = rte_cpu_to_le_16(0xffff);
3959         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3960         req.evb_mode = bp->pf->evb_mode;
3961
3962         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3963         HWRM_CHECK_RESULT();
3964         HWRM_UNLOCK();
3965
3966         return rc;
3967 }
3968
3969 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3970                                 uint8_t tunnel_type)
3971 {
3972         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3973         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3974         int rc = 0;
3975
3976         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3977         req.tunnel_type = tunnel_type;
3978         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3979         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3980         HWRM_CHECK_RESULT();
3981
3982         switch (tunnel_type) {
3983         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3984                 bp->vxlan_fw_dst_port_id =
3985                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3986                 bp->vxlan_port = port;
3987                 break;
3988         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3989                 bp->geneve_fw_dst_port_id =
3990                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3991                 bp->geneve_port = port;
3992                 break;
3993         default:
3994                 break;
3995         }
3996
3997         HWRM_UNLOCK();
3998
3999         return rc;
4000 }
4001
4002 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4003                                 uint8_t tunnel_type)
4004 {
4005         struct hwrm_tunnel_dst_port_free_input req = {0};
4006         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4007         int rc = 0;
4008
4009         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4010
4011         req.tunnel_type = tunnel_type;
4012         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4013         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4014
4015         HWRM_CHECK_RESULT();
4016         HWRM_UNLOCK();
4017
4018         if (tunnel_type ==
4019             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4020                 bp->vxlan_port = 0;
4021                 bp->vxlan_port_cnt = 0;
4022         }
4023
4024         if (tunnel_type ==
4025             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4026                 bp->geneve_port = 0;
4027                 bp->geneve_port_cnt = 0;
4028         }
4029
4030         return rc;
4031 }
4032
4033 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4034                                         uint32_t flags)
4035 {
4036         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4037         struct hwrm_func_cfg_input req = {0};
4038         int rc;
4039
4040         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4041
4042         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4043         req.flags = rte_cpu_to_le_32(flags);
4044         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4045
4046         HWRM_CHECK_RESULT();
4047         HWRM_UNLOCK();
4048
4049         return rc;
4050 }
4051
4052 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4053 {
4054         uint32_t *flag = flagp;
4055
4056         vnic->flags = *flag;
4057 }
4058
4059 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4060 {
4061         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4062 }
4063
4064 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4065 {
4066         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4067         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4068         int rc;
4069
4070         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4071
4072         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4073         req.req_buf_page_size =
4074                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4075         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4076         req.req_buf_page_addr0 =
4077                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4078         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4079                 PMD_DRV_LOG(ERR,
4080                         "unable to map buffer address to physical memory\n");
4081                 HWRM_UNLOCK();
4082                 return -ENOMEM;
4083         }
4084
4085         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4086
4087         HWRM_CHECK_RESULT();
4088         HWRM_UNLOCK();
4089
4090         return rc;
4091 }
4092
4093 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4094 {
4095         int rc = 0;
4096         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4097         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4098
4099         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4100                 return 0;
4101
4102         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4103
4104         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4105
4106         HWRM_CHECK_RESULT();
4107         HWRM_UNLOCK();
4108
4109         return rc;
4110 }
4111
4112 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4113 {
4114         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4115         struct hwrm_func_cfg_input req = {0};
4116         int rc;
4117
4118         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4119
4120         req.fid = rte_cpu_to_le_16(0xffff);
4121         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4122         req.enables = rte_cpu_to_le_32(
4123                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4124         req.async_event_cr = rte_cpu_to_le_16(
4125                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4126         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4127
4128         HWRM_CHECK_RESULT();
4129         HWRM_UNLOCK();
4130
4131         return rc;
4132 }
4133
4134 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4135 {
4136         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4137         struct hwrm_func_vf_cfg_input req = {0};
4138         int rc;
4139
4140         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4141
4142         req.enables = rte_cpu_to_le_32(
4143                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4144         req.async_event_cr = rte_cpu_to_le_16(
4145                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4146         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4147
4148         HWRM_CHECK_RESULT();
4149         HWRM_UNLOCK();
4150
4151         return rc;
4152 }
4153
4154 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4155 {
4156         struct hwrm_func_cfg_input req = {0};
4157         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4158         uint16_t dflt_vlan, fid;
4159         uint32_t func_cfg_flags;
4160         int rc = 0;
4161
4162         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4163
4164         if (is_vf) {
4165                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4166                 fid = bp->pf->vf_info[vf].fid;
4167                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4168         } else {
4169                 fid = rte_cpu_to_le_16(0xffff);
4170                 func_cfg_flags = bp->pf->func_cfg_flags;
4171                 dflt_vlan = bp->vlan;
4172         }
4173
4174         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4175         req.fid = rte_cpu_to_le_16(fid);
4176         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4177         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4178
4179         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4180
4181         HWRM_CHECK_RESULT();
4182         HWRM_UNLOCK();
4183
4184         return rc;
4185 }
4186
4187 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4188                         uint16_t max_bw, uint16_t enables)
4189 {
4190         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4191         struct hwrm_func_cfg_input req = {0};
4192         int rc;
4193
4194         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4195
4196         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4197         req.enables |= rte_cpu_to_le_32(enables);
4198         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4199         req.max_bw = rte_cpu_to_le_32(max_bw);
4200         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4201
4202         HWRM_CHECK_RESULT();
4203         HWRM_UNLOCK();
4204
4205         return rc;
4206 }
4207
4208 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4209 {
4210         struct hwrm_func_cfg_input req = {0};
4211         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4212         int rc = 0;
4213
4214         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4215
4216         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4217         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4218         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4219         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4220
4221         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4222
4223         HWRM_CHECK_RESULT();
4224         HWRM_UNLOCK();
4225
4226         return rc;
4227 }
4228
4229 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4230 {
4231         int rc;
4232
4233         if (BNXT_PF(bp))
4234                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4235         else
4236                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4237
4238         return rc;
4239 }
4240
4241 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4242                               void *encaped, size_t ec_size)
4243 {
4244         int rc = 0;
4245         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4246         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4247
4248         if (ec_size > sizeof(req.encap_request))
4249                 return -1;
4250
4251         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4252
4253         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4254         memcpy(req.encap_request, encaped, ec_size);
4255
4256         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4257
4258         HWRM_CHECK_RESULT();
4259         HWRM_UNLOCK();
4260
4261         return rc;
4262 }
4263
4264 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4265                                        struct rte_ether_addr *mac)
4266 {
4267         struct hwrm_func_qcfg_input req = {0};
4268         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4269         int rc;
4270
4271         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4272
4273         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4274         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4275
4276         HWRM_CHECK_RESULT();
4277
4278         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4279
4280         HWRM_UNLOCK();
4281
4282         return rc;
4283 }
4284
4285 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4286                             void *encaped, size_t ec_size)
4287 {
4288         int rc = 0;
4289         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4290         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4291
4292         if (ec_size > sizeof(req.encap_request))
4293                 return -1;
4294
4295         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4296
4297         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4298         memcpy(req.encap_request, encaped, ec_size);
4299
4300         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4301
4302         HWRM_CHECK_RESULT();
4303         HWRM_UNLOCK();
4304
4305         return rc;
4306 }
4307
4308 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
4309                          struct rte_eth_stats *stats, uint8_t rx)
4310 {
4311         int rc = 0;
4312         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4313         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4314
4315         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4316
4317         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4318
4319         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4320
4321         HWRM_CHECK_RESULT();
4322
4323         if (rx) {
4324                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4325                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4326                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4327                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4328                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4329                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4330                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4331                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4332         } else {
4333                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4334                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4335                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4336                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4337                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4338                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4339         }
4340
4341         HWRM_UNLOCK();
4342
4343         return rc;
4344 }
4345
4346 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4347 {
4348         struct hwrm_port_qstats_input req = {0};
4349         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4350         struct bnxt_pf_info *pf = bp->pf;
4351         int rc;
4352
4353         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4354
4355         req.port_id = rte_cpu_to_le_16(pf->port_id);
4356         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4357         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4359
4360         HWRM_CHECK_RESULT();
4361         HWRM_UNLOCK();
4362
4363         return rc;
4364 }
4365
4366 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4367 {
4368         struct hwrm_port_clr_stats_input req = {0};
4369         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4370         struct bnxt_pf_info *pf = bp->pf;
4371         int rc;
4372
4373         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4374         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4375             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4376                 return 0;
4377
4378         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4379
4380         req.port_id = rte_cpu_to_le_16(pf->port_id);
4381         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4382
4383         HWRM_CHECK_RESULT();
4384         HWRM_UNLOCK();
4385
4386         return rc;
4387 }
4388
4389 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4390 {
4391         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4392         struct hwrm_port_led_qcaps_input req = {0};
4393         int rc;
4394
4395         if (BNXT_VF(bp))
4396                 return 0;
4397
4398         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4399         req.port_id = bp->pf->port_id;
4400         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4401
4402         HWRM_CHECK_RESULT_SILENT();
4403
4404         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4405                 unsigned int i;
4406
4407                 bp->leds->num_leds = resp->num_leds;
4408                 memcpy(bp->leds, &resp->led0_id,
4409                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4410                 for (i = 0; i < bp->leds->num_leds; i++) {
4411                         struct bnxt_led_info *led = &bp->leds[i];
4412
4413                         uint16_t caps = led->led_state_caps;
4414
4415                         if (!led->led_group_id ||
4416                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4417                                 bp->leds->num_leds = 0;
4418                                 break;
4419                         }
4420                 }
4421         }
4422
4423         HWRM_UNLOCK();
4424
4425         return rc;
4426 }
4427
4428 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4429 {
4430         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4431         struct hwrm_port_led_cfg_input req = {0};
4432         struct bnxt_led_cfg *led_cfg;
4433         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4434         uint16_t duration = 0;
4435         int rc, i;
4436
4437         if (!bp->leds->num_leds || BNXT_VF(bp))
4438                 return -EOPNOTSUPP;
4439
4440         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4441
4442         if (led_on) {
4443                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4444                 duration = rte_cpu_to_le_16(500);
4445         }
4446         req.port_id = bp->pf->port_id;
4447         req.num_leds = bp->leds->num_leds;
4448         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4449         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4450                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4451                 led_cfg->led_id = bp->leds[i].led_id;
4452                 led_cfg->led_state = led_state;
4453                 led_cfg->led_blink_on = duration;
4454                 led_cfg->led_blink_off = duration;
4455                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4456         }
4457
4458         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4459
4460         HWRM_CHECK_RESULT();
4461         HWRM_UNLOCK();
4462
4463         return rc;
4464 }
4465
4466 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4467                                uint32_t *length)
4468 {
4469         int rc;
4470         struct hwrm_nvm_get_dir_info_input req = {0};
4471         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4472
4473         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4474
4475         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4476
4477         HWRM_CHECK_RESULT();
4478
4479         *entries = rte_le_to_cpu_32(resp->entries);
4480         *length = rte_le_to_cpu_32(resp->entry_length);
4481
4482         HWRM_UNLOCK();
4483         return rc;
4484 }
4485
4486 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4487 {
4488         int rc;
4489         uint32_t dir_entries;
4490         uint32_t entry_length;
4491         uint8_t *buf;
4492         size_t buflen;
4493         rte_iova_t dma_handle;
4494         struct hwrm_nvm_get_dir_entries_input req = {0};
4495         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4496
4497         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4498         if (rc != 0)
4499                 return rc;
4500
4501         *data++ = dir_entries;
4502         *data++ = entry_length;
4503         len -= 2;
4504         memset(data, 0xff, len);
4505
4506         buflen = dir_entries * entry_length;
4507         buf = rte_malloc("nvm_dir", buflen, 0);
4508         if (buf == NULL)
4509                 return -ENOMEM;
4510         dma_handle = rte_malloc_virt2iova(buf);
4511         if (dma_handle == RTE_BAD_IOVA) {
4512                 rte_free(buf);
4513                 PMD_DRV_LOG(ERR,
4514                         "unable to map response address to physical memory\n");
4515                 return -ENOMEM;
4516         }
4517         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4518         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4519         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4520
4521         if (rc == 0)
4522                 memcpy(data, buf, len > buflen ? buflen : len);
4523
4524         rte_free(buf);
4525         HWRM_CHECK_RESULT();
4526         HWRM_UNLOCK();
4527
4528         return rc;
4529 }
4530
4531 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4532                              uint32_t offset, uint32_t length,
4533                              uint8_t *data)
4534 {
4535         int rc;
4536         uint8_t *buf;
4537         rte_iova_t dma_handle;
4538         struct hwrm_nvm_read_input req = {0};
4539         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4540
4541         buf = rte_malloc("nvm_item", length, 0);
4542         if (!buf)
4543                 return -ENOMEM;
4544
4545         dma_handle = rte_malloc_virt2iova(buf);
4546         if (dma_handle == RTE_BAD_IOVA) {
4547                 rte_free(buf);
4548                 PMD_DRV_LOG(ERR,
4549                         "unable to map response address to physical memory\n");
4550                 return -ENOMEM;
4551         }
4552         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4553         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4554         req.dir_idx = rte_cpu_to_le_16(index);
4555         req.offset = rte_cpu_to_le_32(offset);
4556         req.len = rte_cpu_to_le_32(length);
4557         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4558         if (rc == 0)
4559                 memcpy(data, buf, length);
4560
4561         rte_free(buf);
4562         HWRM_CHECK_RESULT();
4563         HWRM_UNLOCK();
4564
4565         return rc;
4566 }
4567
4568 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4569 {
4570         int rc;
4571         struct hwrm_nvm_erase_dir_entry_input req = {0};
4572         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4573
4574         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4575         req.dir_idx = rte_cpu_to_le_16(index);
4576         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4577         HWRM_CHECK_RESULT();
4578         HWRM_UNLOCK();
4579
4580         return rc;
4581 }
4582
4583
4584 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4585                           uint16_t dir_ordinal, uint16_t dir_ext,
4586                           uint16_t dir_attr, const uint8_t *data,
4587                           size_t data_len)
4588 {
4589         int rc;
4590         struct hwrm_nvm_write_input req = {0};
4591         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4592         rte_iova_t dma_handle;
4593         uint8_t *buf;
4594
4595         buf = rte_malloc("nvm_write", data_len, 0);
4596         if (!buf)
4597                 return -ENOMEM;
4598
4599         dma_handle = rte_malloc_virt2iova(buf);
4600         if (dma_handle == RTE_BAD_IOVA) {
4601                 rte_free(buf);
4602                 PMD_DRV_LOG(ERR,
4603                         "unable to map response address to physical memory\n");
4604                 return -ENOMEM;
4605         }
4606         memcpy(buf, data, data_len);
4607
4608         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4609
4610         req.dir_type = rte_cpu_to_le_16(dir_type);
4611         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4612         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4613         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4614         req.dir_data_length = rte_cpu_to_le_32(data_len);
4615         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4616
4617         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4618
4619         rte_free(buf);
4620         HWRM_CHECK_RESULT();
4621         HWRM_UNLOCK();
4622
4623         return rc;
4624 }
4625
4626 static void
4627 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4628 {
4629         uint32_t *count = cbdata;
4630
4631         *count = *count + 1;
4632 }
4633
4634 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4635                                      struct bnxt_vnic_info *vnic __rte_unused)
4636 {
4637         return 0;
4638 }
4639
4640 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4641 {
4642         uint32_t count = 0;
4643
4644         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4645             &count, bnxt_vnic_count_hwrm_stub);
4646
4647         return count;
4648 }
4649
4650 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4651                                         uint16_t *vnic_ids)
4652 {
4653         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4654         struct hwrm_func_vf_vnic_ids_query_output *resp =
4655                                                 bp->hwrm_cmd_resp_addr;
4656         int rc;
4657
4658         /* First query all VNIC ids */
4659         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4660
4661         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4662         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4663         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4664
4665         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4666                 HWRM_UNLOCK();
4667                 PMD_DRV_LOG(ERR,
4668                 "unable to map VNIC ID table address to physical memory\n");
4669                 return -ENOMEM;
4670         }
4671         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4672         HWRM_CHECK_RESULT();
4673         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4674
4675         HWRM_UNLOCK();
4676
4677         return rc;
4678 }
4679
4680 /*
4681  * This function queries the VNIC IDs  for a specified VF. It then calls
4682  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4683  * Then it calls the hwrm_cb function to program this new vnic configuration.
4684  */
4685 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4686         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4687         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4688 {
4689         struct bnxt_vnic_info vnic;
4690         int rc = 0;
4691         int i, num_vnic_ids;
4692         uint16_t *vnic_ids;
4693         size_t vnic_id_sz;
4694         size_t sz;
4695
4696         /* First query all VNIC ids */
4697         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4698         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4699                         RTE_CACHE_LINE_SIZE);
4700         if (vnic_ids == NULL)
4701                 return -ENOMEM;
4702
4703         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4704                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4705
4706         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4707
4708         if (num_vnic_ids < 0)
4709                 return num_vnic_ids;
4710
4711         /* Retrieve VNIC, update bd_stall then update */
4712
4713         for (i = 0; i < num_vnic_ids; i++) {
4714                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4715                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4716                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4717                 if (rc)
4718                         break;
4719                 if (vnic.mru <= 4)      /* Indicates unallocated */
4720                         continue;
4721
4722                 vnic_cb(&vnic, cbdata);
4723
4724                 rc = hwrm_cb(bp, &vnic);
4725                 if (rc)
4726                         break;
4727         }
4728
4729         rte_free(vnic_ids);
4730
4731         return rc;
4732 }
4733
4734 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4735                                               bool on)
4736 {
4737         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4738         struct hwrm_func_cfg_input req = {0};
4739         int rc;
4740
4741         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4742
4743         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4744         req.enables |= rte_cpu_to_le_32(
4745                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4746         req.vlan_antispoof_mode = on ?
4747                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4748                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4750
4751         HWRM_CHECK_RESULT();
4752         HWRM_UNLOCK();
4753
4754         return rc;
4755 }
4756
4757 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4758 {
4759         struct bnxt_vnic_info vnic;
4760         uint16_t *vnic_ids;
4761         size_t vnic_id_sz;
4762         int num_vnic_ids, i;
4763         size_t sz;
4764         int rc;
4765
4766         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4767         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4768                         RTE_CACHE_LINE_SIZE);
4769         if (vnic_ids == NULL)
4770                 return -ENOMEM;
4771
4772         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4773                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4774
4775         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4776         if (rc <= 0)
4777                 goto exit;
4778         num_vnic_ids = rc;
4779
4780         /*
4781          * Loop through to find the default VNIC ID.
4782          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4783          * by sending the hwrm_func_qcfg command to the firmware.
4784          */
4785         for (i = 0; i < num_vnic_ids; i++) {
4786                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4787                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4788                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4789                                         bp->pf->first_vf_id + vf);
4790                 if (rc)
4791                         goto exit;
4792                 if (vnic.func_default) {
4793                         rte_free(vnic_ids);
4794                         return vnic.fw_vnic_id;
4795                 }
4796         }
4797         /* Could not find a default VNIC. */
4798         PMD_DRV_LOG(ERR, "No default VNIC\n");
4799 exit:
4800         rte_free(vnic_ids);
4801         return rc;
4802 }
4803
4804 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4805                          uint16_t dst_id,
4806                          struct bnxt_filter_info *filter)
4807 {
4808         int rc = 0;
4809         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4810         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4811         uint32_t enables = 0;
4812
4813         if (filter->fw_em_filter_id != UINT64_MAX)
4814                 bnxt_hwrm_clear_em_filter(bp, filter);
4815
4816         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4817
4818         req.flags = rte_cpu_to_le_32(filter->flags);
4819
4820         enables = filter->enables |
4821               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4822         req.dst_id = rte_cpu_to_le_16(dst_id);
4823
4824         if (filter->ip_addr_type) {
4825                 req.ip_addr_type = filter->ip_addr_type;
4826                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4827         }
4828         if (enables &
4829             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4830                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4831         if (enables &
4832             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4833                 memcpy(req.src_macaddr, filter->src_macaddr,
4834                        RTE_ETHER_ADDR_LEN);
4835         if (enables &
4836             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4837                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4838                        RTE_ETHER_ADDR_LEN);
4839         if (enables &
4840             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4841                 req.ovlan_vid = filter->l2_ovlan;
4842         if (enables &
4843             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4844                 req.ivlan_vid = filter->l2_ivlan;
4845         if (enables &
4846             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4847                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4848         if (enables &
4849             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4850                 req.ip_protocol = filter->ip_protocol;
4851         if (enables &
4852             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4853                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4854         if (enables &
4855             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4856                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4857         if (enables &
4858             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4859                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4860         if (enables &
4861             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4862                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4863         if (enables &
4864             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4865                 req.mirror_vnic_id = filter->mirror_vnic_id;
4866
4867         req.enables = rte_cpu_to_le_32(enables);
4868
4869         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4870
4871         HWRM_CHECK_RESULT();
4872
4873         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4874         HWRM_UNLOCK();
4875
4876         return rc;
4877 }
4878
4879 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4880 {
4881         int rc = 0;
4882         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4883         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4884
4885         if (filter->fw_em_filter_id == UINT64_MAX)
4886                 return 0;
4887
4888         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4889
4890         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4891
4892         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4893
4894         HWRM_CHECK_RESULT();
4895         HWRM_UNLOCK();
4896
4897         filter->fw_em_filter_id = UINT64_MAX;
4898         filter->fw_l2_filter_id = UINT64_MAX;
4899
4900         return 0;
4901 }
4902
4903 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4904                          uint16_t dst_id,
4905                          struct bnxt_filter_info *filter)
4906 {
4907         int rc = 0;
4908         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4909         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4910                                                 bp->hwrm_cmd_resp_addr;
4911         uint32_t enables = 0;
4912
4913         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4914                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4915
4916         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4917
4918         req.flags = rte_cpu_to_le_32(filter->flags);
4919
4920         enables = filter->enables |
4921               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4922         req.dst_id = rte_cpu_to_le_16(dst_id);
4923
4924         if (filter->ip_addr_type) {
4925                 req.ip_addr_type = filter->ip_addr_type;
4926                 enables |=
4927                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4928         }
4929         if (enables &
4930             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4931                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4932         if (enables &
4933             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4934                 memcpy(req.src_macaddr, filter->src_macaddr,
4935                        RTE_ETHER_ADDR_LEN);
4936         if (enables &
4937             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4938                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4939         if (enables &
4940             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4941                 req.ip_protocol = filter->ip_protocol;
4942         if (enables &
4943             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4944                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4945         if (enables &
4946             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4947                 req.src_ipaddr_mask[0] =
4948                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4949         if (enables &
4950             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4951                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4952         if (enables &
4953             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4954                 req.dst_ipaddr_mask[0] =
4955                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4956         if (enables &
4957             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4958                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4959         if (enables &
4960             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4961                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4962         if (enables &
4963             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4964                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4965         if (enables &
4966             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4967                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4968         if (enables &
4969             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4970                 req.mirror_vnic_id = filter->mirror_vnic_id;
4971
4972         req.enables = rte_cpu_to_le_32(enables);
4973
4974         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4975
4976         HWRM_CHECK_RESULT();
4977
4978         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4979         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4980         HWRM_UNLOCK();
4981
4982         return rc;
4983 }
4984
4985 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4986                                 struct bnxt_filter_info *filter)
4987 {
4988         int rc = 0;
4989         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4990         struct hwrm_cfa_ntuple_filter_free_output *resp =
4991                                                 bp->hwrm_cmd_resp_addr;
4992
4993         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4994                 return 0;
4995
4996         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4997
4998         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4999
5000         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5001
5002         HWRM_CHECK_RESULT();
5003         HWRM_UNLOCK();
5004
5005         filter->fw_ntuple_filter_id = UINT64_MAX;
5006
5007         return 0;
5008 }
5009
5010 static int
5011 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5012 {
5013         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5014         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
5015         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5016         struct bnxt_rx_queue **rxqs = bp->rx_queues;
5017         uint16_t *ring_tbl = vnic->rss_table;
5018         int nr_ctxs = vnic->num_lb_ctxts;
5019         int max_rings = bp->rx_nr_rings;
5020         int i, j, k, cnt;
5021         int rc = 0;
5022
5023         for (i = 0, k = 0; i < nr_ctxs; i++) {
5024                 struct bnxt_rx_ring_info *rxr;
5025                 struct bnxt_cp_ring_info *cpr;
5026
5027                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5028
5029                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5030                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5031                 req.hash_mode_flags = vnic->hash_mode;
5032
5033                 req.ring_grp_tbl_addr =
5034                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5035                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5036                                      2 * sizeof(*ring_tbl));
5037                 req.hash_key_tbl_addr =
5038                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5039
5040                 req.ring_table_pair_index = i;
5041                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5042
5043                 for (j = 0; j < 64; j++) {
5044                         uint16_t ring_id;
5045
5046                         /* Find next active ring. */
5047                         for (cnt = 0; cnt < max_rings; cnt++) {
5048                                 if (rx_queue_state[k] !=
5049                                                 RTE_ETH_QUEUE_STATE_STOPPED)
5050                                         break;
5051                                 if (++k == max_rings)
5052                                         k = 0;
5053                         }
5054
5055                         /* Return if no rings are active. */
5056                         if (cnt == max_rings) {
5057                                 HWRM_UNLOCK();
5058                                 return 0;
5059                         }
5060
5061                         /* Add rx/cp ring pair to RSS table. */
5062                         rxr = rxqs[k]->rx_ring;
5063                         cpr = rxqs[k]->cp_ring;
5064
5065                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5066                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5067                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5068                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5069
5070                         if (++k == max_rings)
5071                                 k = 0;
5072                 }
5073                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5074                                             BNXT_USE_CHIMP_MB);
5075
5076                 HWRM_CHECK_RESULT();
5077                 HWRM_UNLOCK();
5078         }
5079
5080         return rc;
5081 }
5082
5083 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5084 {
5085         unsigned int rss_idx, fw_idx, i;
5086
5087         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5088                 return 0;
5089
5090         if (!(vnic->rss_table && vnic->hash_type))
5091                 return 0;
5092
5093         if (BNXT_CHIP_P5(bp))
5094                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5095
5096         /*
5097          * Fill the RSS hash & redirection table with
5098          * ring group ids for all VNICs
5099          */
5100         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5101              rss_idx++, fw_idx++) {
5102                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5103                         fw_idx %= bp->rx_cp_nr_rings;
5104                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5105                                 break;
5106                         fw_idx++;
5107                 }
5108
5109                 if (i == bp->rx_cp_nr_rings)
5110                         return 0;
5111
5112                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5113         }
5114
5115         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5116 }
5117
5118 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5119         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5120 {
5121         uint16_t flags;
5122
5123         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5124
5125         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5126         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5127
5128         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5129         req->num_cmpl_dma_aggr_during_int =
5130                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5131
5132         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5133
5134         /* min timer set to 1/2 of interrupt timer */
5135         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5136
5137         /* buf timer set to 1/4 of interrupt timer */
5138         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5139
5140         req->cmpl_aggr_dma_tmr_during_int =
5141                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5142
5143         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5144                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5145         req->flags = rte_cpu_to_le_16(flags);
5146 }
5147
5148 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5149                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5150 {
5151         struct hwrm_ring_aggint_qcaps_input req = {0};
5152         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5153         uint32_t enables;
5154         uint16_t flags;
5155         int rc;
5156
5157         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5158         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5159         HWRM_CHECK_RESULT();
5160
5161         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5162         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5163
5164         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5165                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5166         agg_req->flags = rte_cpu_to_le_16(flags);
5167         enables =
5168          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5169          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5170         agg_req->enables = rte_cpu_to_le_32(enables);
5171
5172         HWRM_UNLOCK();
5173         return rc;
5174 }
5175
5176 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5177                         struct bnxt_coal *coal, uint16_t ring_id)
5178 {
5179         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5180         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5181                                                 bp->hwrm_cmd_resp_addr;
5182         int rc;
5183
5184         /* Set ring coalesce parameters only for 100G NICs */
5185         if (BNXT_CHIP_P5(bp)) {
5186                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5187                         return -1;
5188         } else if (bnxt_stratus_device(bp)) {
5189                 bnxt_hwrm_set_coal_params(coal, &req);
5190         } else {
5191                 return 0;
5192         }
5193
5194         HWRM_PREP(&req,
5195                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5196                   BNXT_USE_CHIMP_MB);
5197         req.ring_id = rte_cpu_to_le_16(ring_id);
5198         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5199         HWRM_CHECK_RESULT();
5200         HWRM_UNLOCK();
5201         return 0;
5202 }
5203
5204 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5205 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5206 {
5207         struct hwrm_func_backing_store_qcaps_input req = {0};
5208         struct hwrm_func_backing_store_qcaps_output *resp =
5209                 bp->hwrm_cmd_resp_addr;
5210         struct bnxt_ctx_pg_info *ctx_pg;
5211         struct bnxt_ctx_mem_info *ctx;
5212         int total_alloc_len;
5213         int rc, i, tqm_rings;
5214
5215         if (!BNXT_CHIP_P5(bp) ||
5216             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5217             BNXT_VF(bp) ||
5218             bp->ctx)
5219                 return 0;
5220
5221         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5222         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5223         HWRM_CHECK_RESULT_SILENT();
5224
5225         total_alloc_len = sizeof(*ctx);
5226         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5227                           RTE_CACHE_LINE_SIZE);
5228         if (!ctx) {
5229                 rc = -ENOMEM;
5230                 goto ctx_err;
5231         }
5232
5233         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5234         ctx->qp_min_qp1_entries =
5235                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5236         ctx->qp_max_l2_entries =
5237                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5238         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5239         ctx->srq_max_l2_entries =
5240                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5241         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5242         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5243         ctx->cq_max_l2_entries =
5244                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5245         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5246         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5247         ctx->vnic_max_vnic_entries =
5248                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5249         ctx->vnic_max_ring_table_entries =
5250                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5251         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5252         ctx->stat_max_entries =
5253                 rte_le_to_cpu_32(resp->stat_max_entries);
5254         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5255         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5256         ctx->tqm_min_entries_per_ring =
5257                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5258         ctx->tqm_max_entries_per_ring =
5259                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5260         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5261         if (!ctx->tqm_entries_multiple)
5262                 ctx->tqm_entries_multiple = 1;
5263         ctx->mrav_max_entries =
5264                 rte_le_to_cpu_32(resp->mrav_max_entries);
5265         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5266         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5267         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5268         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5269
5270         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5271                                   RTE_MIN(ctx->tqm_fp_rings_count,
5272                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5273                                   bp->max_q;
5274
5275         /* Check if the ext ring count needs to be counted.
5276          * Ext ring count is available only with new FW so we should not
5277          * look at the field on older FW.
5278          */
5279         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5280             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5281                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5282                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5283                                                   ctx->tqm_fp_rings_count);
5284         }
5285
5286         tqm_rings = ctx->tqm_fp_rings_count + 1;
5287
5288         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5289                             sizeof(*ctx_pg) * tqm_rings,
5290                             RTE_CACHE_LINE_SIZE);
5291         if (!ctx_pg) {
5292                 rc = -ENOMEM;
5293                 goto ctx_err;
5294         }
5295         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5296                 ctx->tqm_mem[i] = ctx_pg;
5297
5298         bp->ctx = ctx;
5299 ctx_err:
5300         HWRM_UNLOCK();
5301         return rc;
5302 }
5303
5304 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5305 {
5306         struct hwrm_func_backing_store_cfg_input req = {0};
5307         struct hwrm_func_backing_store_cfg_output *resp =
5308                 bp->hwrm_cmd_resp_addr;
5309         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5310         struct bnxt_ctx_pg_info *ctx_pg;
5311         uint32_t *num_entries;
5312         uint64_t *pg_dir;
5313         uint8_t *pg_attr;
5314         uint32_t ena;
5315         int i, rc;
5316
5317         if (!ctx)
5318                 return 0;
5319
5320         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5321         req.enables = rte_cpu_to_le_32(enables);
5322
5323         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5324                 ctx_pg = &ctx->qp_mem;
5325                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5326                 req.qp_num_qp1_entries =
5327                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5328                 req.qp_num_l2_entries =
5329                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5330                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5331                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5332                                       &req.qpc_pg_size_qpc_lvl,
5333                                       &req.qpc_page_dir);
5334         }
5335
5336         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5337                 ctx_pg = &ctx->srq_mem;
5338                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5339                 req.srq_num_l2_entries =
5340                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5341                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5342                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5343                                       &req.srq_pg_size_srq_lvl,
5344                                       &req.srq_page_dir);
5345         }
5346
5347         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5348                 ctx_pg = &ctx->cq_mem;
5349                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5350                 req.cq_num_l2_entries =
5351                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5352                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5353                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5354                                       &req.cq_pg_size_cq_lvl,
5355                                       &req.cq_page_dir);
5356         }
5357
5358         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5359                 ctx_pg = &ctx->vnic_mem;
5360                 req.vnic_num_vnic_entries =
5361                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5362                 req.vnic_num_ring_table_entries =
5363                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5364                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5365                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5366                                       &req.vnic_pg_size_vnic_lvl,
5367                                       &req.vnic_page_dir);
5368         }
5369
5370         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5371                 ctx_pg = &ctx->stat_mem;
5372                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5373                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5374                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5375                                       &req.stat_pg_size_stat_lvl,
5376                                       &req.stat_page_dir);
5377         }
5378
5379         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5380         num_entries = &req.tqm_sp_num_entries;
5381         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5382         pg_dir = &req.tqm_sp_page_dir;
5383         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5384         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5385                 if (!(enables & ena))
5386                         continue;
5387
5388                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5389
5390                 ctx_pg = ctx->tqm_mem[i];
5391                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5392                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5393         }
5394
5395         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5396                 /* DPDK does not need to configure MRAV and TIM type.
5397                  * So we are skipping over MRAV and TIM. Skip to configure
5398                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5399                  */
5400                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5401                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5402                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5403                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5404                                       &req.tqm_ring8_page_dir);
5405         }
5406
5407         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5408         HWRM_CHECK_RESULT();
5409         HWRM_UNLOCK();
5410
5411         return rc;
5412 }
5413
5414 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5415 {
5416         struct hwrm_port_qstats_ext_input req = {0};
5417         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5418         struct bnxt_pf_info *pf = bp->pf;
5419         int rc;
5420
5421         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5422               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5423                 return 0;
5424
5425         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5426
5427         req.port_id = rte_cpu_to_le_16(pf->port_id);
5428         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5429                 req.tx_stat_host_addr =
5430                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5431                 req.tx_stat_size =
5432                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5433         }
5434         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5435                 req.rx_stat_host_addr =
5436                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5437                 req.rx_stat_size =
5438                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5439         }
5440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5441
5442         if (rc) {
5443                 bp->fw_rx_port_stats_ext_size = 0;
5444                 bp->fw_tx_port_stats_ext_size = 0;
5445         } else {
5446                 bp->fw_rx_port_stats_ext_size =
5447                         rte_le_to_cpu_16(resp->rx_stat_size);
5448                 bp->fw_tx_port_stats_ext_size =
5449                         rte_le_to_cpu_16(resp->tx_stat_size);
5450         }
5451
5452         HWRM_CHECK_RESULT();
5453         HWRM_UNLOCK();
5454
5455         return rc;
5456 }
5457
5458 int
5459 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5460 {
5461         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5462         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5463                 bp->hwrm_cmd_resp_addr;
5464         int rc = 0;
5465
5466         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5467         req.tunnel_type = type;
5468         req.dest_fid = bp->fw_fid;
5469         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5470         HWRM_CHECK_RESULT();
5471
5472         HWRM_UNLOCK();
5473
5474         return rc;
5475 }
5476
5477 int
5478 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5479 {
5480         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5481         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5482                 bp->hwrm_cmd_resp_addr;
5483         int rc = 0;
5484
5485         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5486         req.tunnel_type = type;
5487         req.dest_fid = bp->fw_fid;
5488         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5489         HWRM_CHECK_RESULT();
5490
5491         HWRM_UNLOCK();
5492
5493         return rc;
5494 }
5495
5496 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5497 {
5498         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5499         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5500                 bp->hwrm_cmd_resp_addr;
5501         int rc = 0;
5502
5503         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5504         req.src_fid = bp->fw_fid;
5505         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5506         HWRM_CHECK_RESULT();
5507
5508         if (type)
5509                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5510
5511         HWRM_UNLOCK();
5512
5513         return rc;
5514 }
5515
5516 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5517                                    uint16_t *dst_fid)
5518 {
5519         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5520         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5521                 bp->hwrm_cmd_resp_addr;
5522         int rc = 0;
5523
5524         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5525         req.src_fid = bp->fw_fid;
5526         req.tunnel_type = tun_type;
5527         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5528         HWRM_CHECK_RESULT();
5529
5530         if (dst_fid)
5531                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5532
5533         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5534
5535         HWRM_UNLOCK();
5536
5537         return rc;
5538 }
5539
5540 int bnxt_hwrm_set_mac(struct bnxt *bp)
5541 {
5542         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5543         struct hwrm_func_vf_cfg_input req = {0};
5544         int rc = 0;
5545
5546         if (!BNXT_VF(bp))
5547                 return 0;
5548
5549         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5550
5551         req.enables =
5552                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5553         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5554
5555         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5556
5557         HWRM_CHECK_RESULT();
5558
5559         HWRM_UNLOCK();
5560
5561         return rc;
5562 }
5563
5564 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5565 {
5566         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5567         struct hwrm_func_drv_if_change_input req = {0};
5568         uint32_t flags;
5569         int rc;
5570
5571         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5572                 return 0;
5573
5574         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5575          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5576          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5577          */
5578         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5579                 return 0;
5580
5581         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5582
5583         if (up)
5584                 req.flags =
5585                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5586
5587         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5588
5589         HWRM_CHECK_RESULT();
5590         flags = rte_le_to_cpu_32(resp->flags);
5591         HWRM_UNLOCK();
5592
5593         if (!up)
5594                 return 0;
5595
5596         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5597                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5598                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5599         }
5600
5601         return 0;
5602 }
5603
5604 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5605 {
5606         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5607         struct bnxt_error_recovery_info *info = bp->recovery_info;
5608         struct hwrm_error_recovery_qcfg_input req = {0};
5609         uint32_t flags = 0;
5610         unsigned int i;
5611         int rc;
5612
5613         /* Older FW does not have error recovery support */
5614         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5615                 return 0;
5616
5617         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5618
5619         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5620
5621         HWRM_CHECK_RESULT();
5622
5623         flags = rte_le_to_cpu_32(resp->flags);
5624         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5625                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5626         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5627                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5628
5629         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5630             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5631                 rc = -EINVAL;
5632                 goto err;
5633         }
5634
5635         /* FW returned values are in units of 100msec */
5636         info->driver_polling_freq =
5637                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5638         info->master_func_wait_period =
5639                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5640         info->normal_func_wait_period =
5641                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5642         info->master_func_wait_period_after_reset =
5643                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5644         info->max_bailout_time_after_reset =
5645                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5646         info->status_regs[BNXT_FW_STATUS_REG] =
5647                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5648         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5649                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5650         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5651                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5652         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5653                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5654         info->reg_array_cnt =
5655                 rte_le_to_cpu_32(resp->reg_array_cnt);
5656
5657         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5658                 rc = -EINVAL;
5659                 goto err;
5660         }
5661
5662         for (i = 0; i < info->reg_array_cnt; i++) {
5663                 info->reset_reg[i] =
5664                         rte_le_to_cpu_32(resp->reset_reg[i]);
5665                 info->reset_reg_val[i] =
5666                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5667                 info->delay_after_reset[i] =
5668                         resp->delay_after_reset[i];
5669         }
5670 err:
5671         HWRM_UNLOCK();
5672
5673         /* Map the FW status registers */
5674         if (!rc)
5675                 rc = bnxt_map_fw_health_status_regs(bp);
5676
5677         if (rc) {
5678                 rte_free(bp->recovery_info);
5679                 bp->recovery_info = NULL;
5680         }
5681         return rc;
5682 }
5683
5684 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5685 {
5686         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5687         struct hwrm_fw_reset_input req = {0};
5688         int rc;
5689
5690         if (!BNXT_PF(bp))
5691                 return -EOPNOTSUPP;
5692
5693         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5694
5695         req.embedded_proc_type =
5696                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5697         req.selfrst_status =
5698                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5699         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5700
5701         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5702                                     BNXT_USE_KONG(bp));
5703
5704         HWRM_CHECK_RESULT();
5705         HWRM_UNLOCK();
5706
5707         return rc;
5708 }
5709
5710 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5711 {
5712         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5713         struct hwrm_port_ts_query_input req = {0};
5714         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5715         uint32_t flags = 0;
5716         int rc;
5717
5718         if (!ptp)
5719                 return 0;
5720
5721         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5722
5723         switch (path) {
5724         case BNXT_PTP_FLAGS_PATH_TX:
5725                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5726                 break;
5727         case BNXT_PTP_FLAGS_PATH_RX:
5728                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5729                 break;
5730         case BNXT_PTP_FLAGS_CURRENT_TIME:
5731                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5732                 break;
5733         }
5734
5735         req.flags = rte_cpu_to_le_32(flags);
5736         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5737
5738         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5739
5740         HWRM_CHECK_RESULT();
5741
5742         if (timestamp) {
5743                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5744                 *timestamp |=
5745                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5746         }
5747         HWRM_UNLOCK();
5748
5749         return rc;
5750 }
5751
5752 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5753 {
5754         int rc = 0;
5755
5756         struct hwrm_cfa_counter_qcaps_input req = {0};
5757         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5758
5759         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5760                 PMD_DRV_LOG(DEBUG,
5761                             "Not a PF or trusted VF. Command not supported\n");
5762                 return 0;
5763         }
5764
5765         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5766         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5767         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5768
5769         HWRM_CHECK_RESULT();
5770         if (max_fc)
5771                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5772         HWRM_UNLOCK();
5773
5774         return 0;
5775 }
5776
5777 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5778 {
5779         int rc = 0;
5780         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5781         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5782
5783         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5784                 PMD_DRV_LOG(DEBUG,
5785                             "Not a PF or trusted VF. Command not supported\n");
5786                 return 0;
5787         }
5788
5789         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5790
5791         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5792         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5793         req.page_dir = rte_cpu_to_le_64(dma_addr);
5794
5795         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5796
5797         HWRM_CHECK_RESULT();
5798         if (ctx_id) {
5799                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5800                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5801         }
5802         HWRM_UNLOCK();
5803
5804         return 0;
5805 }
5806
5807 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5808 {
5809         int rc = 0;
5810         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5811         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5812
5813         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5814                 PMD_DRV_LOG(DEBUG,
5815                             "Not a PF or trusted VF. Command not supported\n");
5816                 return 0;
5817         }
5818
5819         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5820
5821         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5822
5823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5824
5825         HWRM_CHECK_RESULT();
5826         HWRM_UNLOCK();
5827
5828         return rc;
5829 }
5830
5831 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5832                               uint16_t cntr, uint16_t ctx_id,
5833                               uint32_t num_entries, bool enable)
5834 {
5835         struct hwrm_cfa_counter_cfg_input req = {0};
5836         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5837         uint16_t flags = 0;
5838         int rc;
5839
5840         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5841                 PMD_DRV_LOG(DEBUG,
5842                             "Not a PF or trusted VF. Command not supported\n");
5843                 return 0;
5844         }
5845
5846         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5847
5848         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5849         req.counter_type = rte_cpu_to_le_16(cntr);
5850         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5851                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5852         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5853         if (dir == BNXT_DIR_RX)
5854                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5855         else if (dir == BNXT_DIR_TX)
5856                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5857         req.flags = rte_cpu_to_le_16(flags);
5858         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5859         req.num_entries = rte_cpu_to_le_32(num_entries);
5860
5861         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5862         HWRM_CHECK_RESULT();
5863         HWRM_UNLOCK();
5864
5865         return 0;
5866 }
5867
5868 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5869                                  enum bnxt_flow_dir dir,
5870                                  uint16_t cntr,
5871                                  uint16_t num_entries)
5872 {
5873         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5874         struct hwrm_cfa_counter_qstats_input req = {0};
5875         uint16_t flow_ctx_id = 0;
5876         uint16_t flags = 0;
5877         int rc = 0;
5878
5879         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5880                 PMD_DRV_LOG(DEBUG,
5881                             "Not a PF or trusted VF. Command not supported\n");
5882                 return 0;
5883         }
5884
5885         if (dir == BNXT_DIR_RX) {
5886                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5887                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5888         } else if (dir == BNXT_DIR_TX) {
5889                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5890                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5891         }
5892
5893         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5894         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5895         req.counter_type = rte_cpu_to_le_16(cntr);
5896         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5897         req.num_entries = rte_cpu_to_le_16(num_entries);
5898         req.flags = rte_cpu_to_le_16(flags);
5899         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5900
5901         HWRM_CHECK_RESULT();
5902         HWRM_UNLOCK();
5903
5904         return 0;
5905 }
5906
5907 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5908                                 uint16_t *first_vf_id)
5909 {
5910         int rc = 0;
5911         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5912         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5913
5914         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5915
5916         req.fid = rte_cpu_to_le_16(fid);
5917
5918         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5919
5920         HWRM_CHECK_RESULT();
5921
5922         if (first_vf_id)
5923                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5924
5925         HWRM_UNLOCK();
5926
5927         return rc;
5928 }
5929
5930 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5931 {
5932         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5933         struct hwrm_cfa_pair_alloc_input req = {0};
5934         int rc;
5935
5936         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5937                 PMD_DRV_LOG(DEBUG,
5938                             "Not a PF or trusted VF. Command not supported\n");
5939                 return 0;
5940         }
5941
5942         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5943         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5944         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5945                  bp->eth_dev->data->name, rep_bp->vf_id);
5946
5947         req.pf_b_id = rep_bp->parent_pf_idx;
5948         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5949                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5950         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5951         req.host_b_id = 1; /* TBD - Confirm if this is OK */
5952
5953         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5954                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5955         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5956                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5957         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5958                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5959         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5960                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5961
5962         req.q_ab = rep_bp->rep_q_r2f;
5963         req.q_ba = rep_bp->rep_q_f2r;
5964         req.fc_ab = rep_bp->rep_fc_r2f;
5965         req.fc_ba = rep_bp->rep_fc_f2r;
5966
5967         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5968         HWRM_CHECK_RESULT();
5969
5970         HWRM_UNLOCK();
5971         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5972                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5973         return rc;
5974 }
5975
5976 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5977 {
5978         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5979         struct hwrm_cfa_pair_free_input req = {0};
5980         int rc;
5981
5982         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5983                 PMD_DRV_LOG(DEBUG,
5984                             "Not a PF or trusted VF. Command not supported\n");
5985                 return 0;
5986         }
5987
5988         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5989         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5990                  bp->eth_dev->data->name, rep_bp->vf_id);
5991         req.pf_b_id = rep_bp->parent_pf_idx;
5992         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5993         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5994                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5995         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5996         HWRM_CHECK_RESULT();
5997         HWRM_UNLOCK();
5998         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
5999                     rep_bp->vf_id);
6000         return rc;
6001 }
6002
6003 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6004 {
6005         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6006                                         bp->hwrm_cmd_resp_addr;
6007         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6008         uint32_t flags = 0;
6009         int rc = 0;
6010
6011         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6012                 return 0;
6013
6014         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6015                 PMD_DRV_LOG(DEBUG,
6016                             "Not a PF or trusted VF. Command not supported\n");
6017                 return 0;
6018         }
6019
6020         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6021         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6022
6023         HWRM_CHECK_RESULT();
6024         flags = rte_le_to_cpu_32(resp->flags);
6025         HWRM_UNLOCK();
6026
6027         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6028                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6029         else
6030                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6031
6032         return rc;
6033 }
6034
6035 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6036                             uint32_t echo_req_data2)
6037 {
6038         struct hwrm_func_echo_response_input req = {0};
6039         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6040         int rc;
6041
6042         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6043         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6044         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6045
6046         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6047
6048         HWRM_CHECK_RESULT();
6049         HWRM_UNLOCK();
6050
6051         return rc;
6052 }
6053
6054 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6055 {
6056         struct hwrm_ver_get_input req = {.req_type = 0 };
6057         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6058         int rc = 0;
6059
6060         bp->max_req_len = HWRM_MAX_REQ_LEN;
6061         bp->max_resp_len = BNXT_PAGE_SIZE;
6062         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6063
6064         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6065         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6066         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6067         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6068
6069         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6070
6071         HWRM_CHECK_RESULT_SILENT();
6072
6073         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6074                 rc = -EAGAIN;
6075
6076         HWRM_UNLOCK();
6077
6078         return rc;
6079 }