3d2d408b68ad4abf36cbac4643edb3afa67d70c4
[dpdk.git] / drivers / net / bnxt / bnxt_hwrm.c
1 /*-
2  *   BSD LICENSE
3  *
4  *   Copyright(c) Broadcom Limited.
5  *   All rights reserved.
6  *
7  *   Redistribution and use in source and binary forms, with or without
8  *   modification, are permitted provided that the following conditions
9  *   are met:
10  *
11  *     * Redistributions of source code must retain the above copyright
12  *       notice, this list of conditions and the following disclaimer.
13  *     * Redistributions in binary form must reproduce the above copyright
14  *       notice, this list of conditions and the following disclaimer in
15  *       the documentation and/or other materials provided with the
16  *       distribution.
17  *     * Neither the name of Broadcom Corporation nor the names of its
18  *       contributors may be used to endorse or promote products derived
19  *       from this software without specific prior written permission.
20  *
21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33
34 #include <unistd.h>
35
36 #include <unistd.h>
37
38 #include <rte_byteorder.h>
39 #include <rte_common.h>
40 #include <rte_cycles.h>
41 #include <rte_malloc.h>
42 #include <rte_memzone.h>
43 #include <rte_version.h>
44
45 #include "bnxt.h"
46 #include "bnxt_cpr.h"
47 #include "bnxt_filter.h"
48 #include "bnxt_hwrm.h"
49 #include "bnxt_rxq.h"
50 #include "bnxt_rxr.h"
51 #include "bnxt_ring.h"
52 #include "bnxt_txq.h"
53 #include "bnxt_txr.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
56
57 #include <rte_io.h>
58
59 #define HWRM_CMD_TIMEOUT                2000
60
61 struct bnxt_plcmodes_cfg {
62         uint32_t        flags;
63         uint16_t        jumbo_thresh;
64         uint16_t        hds_offset;
65         uint16_t        hds_threshold;
66 };
67
68 static int page_getenum(size_t size)
69 {
70         if (size <= 1 << 4)
71                 return 4;
72         if (size <= 1 << 12)
73                 return 12;
74         if (size <= 1 << 13)
75                 return 13;
76         if (size <= 1 << 16)
77                 return 16;
78         if (size <= 1 << 21)
79                 return 21;
80         if (size <= 1 << 22)
81                 return 22;
82         if (size <= 1 << 30)
83                 return 30;
84         RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
85         return sizeof(void *) * 8 - 1;
86 }
87
88 static int page_roundup(size_t size)
89 {
90         return 1 << page_getenum(size);
91 }
92
93 /*
94  * HWRM Functions (sent to HWRM)
95  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
96  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
97  * command was failed by the ChiMP.
98  */
99
100 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
101                                         uint32_t msg_len)
102 {
103         unsigned int i;
104         struct input *req = msg;
105         struct output *resp = bp->hwrm_cmd_resp_addr;
106         uint32_t *data = msg;
107         uint8_t *bar;
108         uint8_t *valid;
109         uint16_t max_req_len = bp->max_req_len;
110         struct hwrm_short_input short_input = { 0 };
111
112         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
113                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
114
115                 memset(short_cmd_req, 0, bp->max_req_len);
116                 memcpy(short_cmd_req, req, msg_len);
117
118                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
119                 short_input.signature = rte_cpu_to_le_16(
120                                         HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
121                 short_input.size = rte_cpu_to_le_16(msg_len);
122                 short_input.req_addr =
123                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
124
125                 data = (uint32_t *)&short_input;
126                 msg_len = sizeof(short_input);
127
128                 /* Sync memory write before updating doorbell */
129                 rte_wmb();
130
131                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
132         }
133
134         /* Write request msg to hwrm channel */
135         for (i = 0; i < msg_len; i += 4) {
136                 bar = (uint8_t *)bp->bar0 + i;
137                 rte_write32(*data, bar);
138                 data++;
139         }
140
141         /* Zero the rest of the request space */
142         for (; i < max_req_len; i += 4) {
143                 bar = (uint8_t *)bp->bar0 + i;
144                 rte_write32(0, bar);
145         }
146
147         /* Ring channel doorbell */
148         bar = (uint8_t *)bp->bar0 + 0x100;
149         rte_write32(1, bar);
150
151         /* Poll for the valid bit */
152         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
153                 /* Sanity check on the resp->resp_len */
154                 rte_rmb();
155                 if (resp->resp_len && resp->resp_len <=
156                                 bp->max_resp_len) {
157                         /* Last byte of resp contains the valid key */
158                         valid = (uint8_t *)resp + resp->resp_len - 1;
159                         if (*valid == HWRM_RESP_VALID_KEY)
160                                 break;
161                 }
162                 rte_delay_us(600);
163         }
164
165         if (i >= HWRM_CMD_TIMEOUT) {
166                 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
167                         req->req_type);
168                 goto err_ret;
169         }
170         return 0;
171
172 err_ret:
173         return -1;
174 }
175
176 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
177 {
178         int rc;
179
180         rte_spinlock_lock(&bp->hwrm_lock);
181         rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
182         rte_spinlock_unlock(&bp->hwrm_lock);
183         return rc;
184 }
185
186 #define HWRM_PREP(req, type, cr, resp) \
187         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
188         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
189         req.cmpl_ring = rte_cpu_to_le_16(cr); \
190         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
191         req.target_id = rte_cpu_to_le_16(0xffff); \
192         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
193
194 #define HWRM_CHECK_RESULT \
195         { \
196                 if (rc) { \
197                         RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
198                                 __func__, rc); \
199                         return rc; \
200                 } \
201                 if (resp->error_code) { \
202                         rc = rte_le_to_cpu_16(resp->error_code); \
203                         if (resp->resp_len >= 16) { \
204                                 struct hwrm_err_output *tmp_hwrm_err_op = \
205                                                         (void *)resp; \
206                                 RTE_LOG(ERR, PMD, \
207                                         "%s error %d:%d:%08x:%04x\n", \
208                                         __func__, \
209                                         rc, tmp_hwrm_err_op->cmd_err, \
210                                         rte_le_to_cpu_32(\
211                                                 tmp_hwrm_err_op->opaque_0), \
212                                         rte_le_to_cpu_16(\
213                                                 tmp_hwrm_err_op->opaque_1)); \
214                         } \
215                         else { \
216                                 RTE_LOG(ERR, PMD, \
217                                         "%s error %d\n", __func__, rc); \
218                         } \
219                         return rc; \
220                 } \
221         }
222
223 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
224 {
225         int rc = 0;
226         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
227         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
228
229         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
230         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
231         req.mask = 0;
232
233         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
234
235         HWRM_CHECK_RESULT;
236
237         return rc;
238 }
239
240 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
241                                  struct bnxt_vnic_info *vnic,
242                                  uint16_t vlan_count,
243                                  struct bnxt_vlan_table_entry *vlan_table)
244 {
245         int rc = 0;
246         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
247         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
248         uint32_t mask = 0;
249
250         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
251         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
252
253         /* FIXME add multicast flag, when multicast adding options is supported
254          * by ethtool.
255          */
256         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
257                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
258         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
259                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
260         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
261                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
262         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
263                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
264         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
265                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
266         if (vnic->mc_addr_cnt) {
267                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
268                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
269                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
270         }
271         if (vlan_count && vlan_table) {
272                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
273                 req.vlan_tag_tbl_addr = rte_cpu_to_le_16(
274                          rte_mem_virt2phy(vlan_table));
275                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
276         }
277         req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
278                                     mask);
279
280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
281
282         HWRM_CHECK_RESULT;
283
284         return rc;
285 }
286
287 int bnxt_hwrm_clear_filter(struct bnxt *bp,
288                            struct bnxt_filter_info *filter)
289 {
290         int rc = 0;
291         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
292         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
293
294         HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
295
296         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
297
298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
299
300         HWRM_CHECK_RESULT;
301
302         filter->fw_l2_filter_id = -1;
303
304         return 0;
305 }
306
307 int bnxt_hwrm_set_filter(struct bnxt *bp,
308                          uint16_t dst_id,
309                          struct bnxt_filter_info *filter)
310 {
311         int rc = 0;
312         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
313         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
314         uint32_t enables = 0;
315
316         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
317
318         req.flags = rte_cpu_to_le_32(filter->flags);
319
320         enables = filter->enables |
321               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
322         req.dst_id = rte_cpu_to_le_16(dst_id);
323
324         if (enables &
325             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
326                 memcpy(req.l2_addr, filter->l2_addr,
327                        ETHER_ADDR_LEN);
328         if (enables &
329             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
330                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
331                        ETHER_ADDR_LEN);
332         if (enables &
333             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
334                 req.l2_ovlan = filter->l2_ovlan;
335         if (enables &
336             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
337                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
338         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
339                 req.src_id = rte_cpu_to_le_32(filter->src_id);
340         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
341                 req.src_type = filter->src_type;
342
343         req.enables = rte_cpu_to_le_32(enables);
344
345         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
346
347         HWRM_CHECK_RESULT;
348
349         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
350
351         return rc;
352 }
353
354 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
355 {
356         int rc = 0;
357         struct hwrm_func_qcaps_input req = {.req_type = 0 };
358         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
359         uint16_t new_max_vfs;
360         int i;
361
362         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
363
364         req.fid = rte_cpu_to_le_16(0xffff);
365
366         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
367
368         HWRM_CHECK_RESULT;
369
370         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
371         if (BNXT_PF(bp)) {
372                 bp->pf.port_id = resp->port_id;
373                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
374                 new_max_vfs = bp->pdev->max_vfs;
375                 if (new_max_vfs != bp->pf.max_vfs) {
376                         if (bp->pf.vf_info)
377                                 rte_free(bp->pf.vf_info);
378                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
379                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
380                         bp->pf.max_vfs = new_max_vfs;
381                         for (i = 0; i < new_max_vfs; i++) {
382                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
383                                 bp->pf.vf_info[i].vlan_table =
384                                         rte_zmalloc("VF VLAN table",
385                                                     getpagesize(),
386                                                     getpagesize());
387                                 if (bp->pf.vf_info[i].vlan_table == NULL)
388                                         RTE_LOG(ERR, PMD,
389                                         "Fail to alloc VLAN table for VF %d\n",
390                                         i);
391                                 else
392                                         rte_mem_lock_page(
393                                                 bp->pf.vf_info[i].vlan_table);
394                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
395                         }
396                 }
397         }
398
399         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
400         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
401         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
402         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
403         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
404         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
405         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
406         /* TODO: For now, do not support VMDq/RFS on VFs. */
407         if (BNXT_PF(bp)) {
408                 if (bp->pf.max_vfs)
409                         bp->max_vnics = 1;
410                 else
411                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
412         } else {
413                 bp->max_vnics = 1;
414         }
415         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
416         if (BNXT_PF(bp))
417                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
418
419         return rc;
420 }
421
422 int bnxt_hwrm_func_reset(struct bnxt *bp)
423 {
424         int rc = 0;
425         struct hwrm_func_reset_input req = {.req_type = 0 };
426         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
427
428         HWRM_PREP(req, FUNC_RESET, -1, resp);
429
430         req.enables = rte_cpu_to_le_32(0);
431
432         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
433
434         HWRM_CHECK_RESULT;
435
436         return rc;
437 }
438
439 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
440 {
441         int rc;
442         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
443         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
444
445         if (bp->flags & BNXT_FLAG_REGISTERED)
446                 return 0;
447
448         HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
449         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
450                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
451         req.ver_maj = RTE_VER_YEAR;
452         req.ver_min = RTE_VER_MONTH;
453         req.ver_upd = RTE_VER_MINOR;
454
455         if (BNXT_PF(bp)) {
456                 req.enables |= rte_cpu_to_le_32(
457                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
458                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
459                        RTE_MIN(sizeof(req.vf_req_fwd),
460                                sizeof(bp->pf.vf_req_fwd)));
461         }
462
463         req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1);   /* TODO: Use MACRO */
464         memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
465
466         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
467
468         HWRM_CHECK_RESULT;
469
470         bp->flags |= BNXT_FLAG_REGISTERED;
471
472         return rc;
473 }
474
475 int bnxt_hwrm_ver_get(struct bnxt *bp)
476 {
477         int rc = 0;
478         struct hwrm_ver_get_input req = {.req_type = 0 };
479         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
480         uint32_t my_version;
481         uint32_t fw_version;
482         uint16_t max_resp_len;
483         char type[RTE_MEMZONE_NAMESIZE];
484         uint32_t dev_caps_cfg;
485
486         bp->max_req_len = HWRM_MAX_REQ_LEN;
487         HWRM_PREP(req, VER_GET, -1, resp);
488
489         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
490         req.hwrm_intf_min = HWRM_VERSION_MINOR;
491         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
492
493         /*
494          * Hold the lock since we may be adjusting the response pointers.
495          */
496         rte_spinlock_lock(&bp->hwrm_lock);
497         rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
498
499         HWRM_CHECK_RESULT;
500
501         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
502                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
503                 resp->hwrm_intf_upd,
504                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
505         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
506                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
507         RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
508                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
509
510         my_version = HWRM_VERSION_MAJOR << 16;
511         my_version |= HWRM_VERSION_MINOR << 8;
512         my_version |= HWRM_VERSION_UPDATE;
513
514         fw_version = resp->hwrm_intf_maj << 16;
515         fw_version |= resp->hwrm_intf_min << 8;
516         fw_version |= resp->hwrm_intf_upd;
517
518         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
519                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
520                 rc = -EINVAL;
521                 goto error;
522         }
523
524         if (my_version != fw_version) {
525                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
526                 if (my_version < fw_version) {
527                         RTE_LOG(INFO, PMD,
528                                 "Firmware API version is newer than driver.\n");
529                         RTE_LOG(INFO, PMD,
530                                 "The driver may be missing features.\n");
531                 } else {
532                         RTE_LOG(INFO, PMD,
533                                 "Firmware API version is older than driver.\n");
534                         RTE_LOG(INFO, PMD,
535                                 "Not all driver features may be functional.\n");
536                 }
537         }
538
539         if (bp->max_req_len > resp->max_req_win_len) {
540                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
541                 rc = -EINVAL;
542         }
543         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
544         max_resp_len = resp->max_resp_len;
545         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
546
547         if (bp->max_resp_len != max_resp_len) {
548                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
549                         bp->pdev->addr.domain, bp->pdev->addr.bus,
550                         bp->pdev->addr.devid, bp->pdev->addr.function);
551
552                 rte_free(bp->hwrm_cmd_resp_addr);
553
554                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
555                 if (bp->hwrm_cmd_resp_addr == NULL) {
556                         rc = -ENOMEM;
557                         goto error;
558                 }
559                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
560                 bp->hwrm_cmd_resp_dma_addr =
561                         rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
562                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
563                         RTE_LOG(ERR, PMD,
564                         "Unable to map response buffer to physical memory.\n");
565                         rc = -ENOMEM;
566                         goto error;
567                 }
568                 bp->max_resp_len = max_resp_len;
569         }
570
571         if ((dev_caps_cfg &
572                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
573             (dev_caps_cfg &
574              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
575                 RTE_LOG(DEBUG, PMD, "Short command supported\n");
576
577                 rte_free(bp->hwrm_short_cmd_req_addr);
578
579                 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
580                                                         bp->max_req_len, 0);
581                 if (bp->hwrm_short_cmd_req_addr == NULL) {
582                         rc = -ENOMEM;
583                         goto error;
584                 }
585                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
586                 bp->hwrm_short_cmd_req_dma_addr =
587                         rte_mem_virt2phy(bp->hwrm_short_cmd_req_addr);
588                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
589                         rte_free(bp->hwrm_short_cmd_req_addr);
590                         RTE_LOG(ERR, PMD,
591                                 "Unable to map buffer to physical memory.\n");
592                         rc = -ENOMEM;
593                         goto error;
594                 }
595
596                 bp->flags |= BNXT_FLAG_SHORT_CMD;
597         }
598
599 error:
600         rte_spinlock_unlock(&bp->hwrm_lock);
601         return rc;
602 }
603
604 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
605 {
606         int rc;
607         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
608         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
609
610         if (!(bp->flags & BNXT_FLAG_REGISTERED))
611                 return 0;
612
613         HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
614         req.flags = flags;
615
616         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
617
618         HWRM_CHECK_RESULT;
619
620         bp->flags &= ~BNXT_FLAG_REGISTERED;
621
622         return rc;
623 }
624
625 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
626 {
627         int rc = 0;
628         struct hwrm_port_phy_cfg_input req = {0};
629         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
630         uint32_t enables = 0;
631
632         HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
633
634         if (conf->link_up) {
635                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
636                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
637                 /*
638                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
639                  * any auto mode, even "none".
640                  */
641                 if (!conf->link_speed) {
642                         req.auto_mode |= conf->auto_mode;
643                         enables = HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
644                         req.auto_link_speed_mask = conf->auto_link_speed_mask;
645                         enables |=
646                            HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
647                         req.auto_link_speed = bp->link_info.auto_link_speed;
648                         enables |=
649                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
650                 }
651                 req.auto_duplex = conf->duplex;
652                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
653                 req.auto_pause = conf->auto_pause;
654                 req.force_pause = conf->force_pause;
655                 /* Set force_pause if there is no auto or if there is a force */
656                 if (req.auto_pause && !req.force_pause)
657                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
658                 else
659                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
660
661                 req.enables = rte_cpu_to_le_32(enables);
662         } else {
663                 req.flags =
664                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
665                 RTE_LOG(INFO, PMD, "Force Link Down\n");
666         }
667
668         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
669
670         HWRM_CHECK_RESULT;
671
672         return rc;
673 }
674
675 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
676                                    struct bnxt_link_info *link_info)
677 {
678         int rc = 0;
679         struct hwrm_port_phy_qcfg_input req = {0};
680         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
681
682         HWRM_PREP(req, PORT_PHY_QCFG, -1, resp);
683
684         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
685
686         HWRM_CHECK_RESULT;
687
688         link_info->phy_link_status = resp->link;
689         if (link_info->phy_link_status == HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) {
690                 link_info->link_up = 1;
691                 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
692         } else {
693                 link_info->link_up = 0;
694                 link_info->link_speed = 0;
695         }
696         link_info->duplex = resp->duplex;
697         link_info->pause = resp->pause;
698         link_info->auto_pause = resp->auto_pause;
699         link_info->force_pause = resp->force_pause;
700         link_info->auto_mode = resp->auto_mode;
701
702         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
703         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
704         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
705         link_info->phy_ver[0] = resp->phy_maj;
706         link_info->phy_ver[1] = resp->phy_min;
707         link_info->phy_ver[2] = resp->phy_bld;
708
709         return rc;
710 }
711
712 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
713 {
714         int rc = 0;
715         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
716         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
717
718         HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
719
720         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
721
722         HWRM_CHECK_RESULT;
723
724 #define GET_QUEUE_INFO(x) \
725         bp->cos_queue[x].id = resp->queue_id##x; \
726         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
727
728         GET_QUEUE_INFO(0);
729         GET_QUEUE_INFO(1);
730         GET_QUEUE_INFO(2);
731         GET_QUEUE_INFO(3);
732         GET_QUEUE_INFO(4);
733         GET_QUEUE_INFO(5);
734         GET_QUEUE_INFO(6);
735         GET_QUEUE_INFO(7);
736
737         return rc;
738 }
739
740 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
741                          struct bnxt_ring *ring,
742                          uint32_t ring_type, uint32_t map_index,
743                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
744 {
745         int rc = 0;
746         uint32_t enables = 0;
747         struct hwrm_ring_alloc_input req = {.req_type = 0 };
748         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
749
750         HWRM_PREP(req, RING_ALLOC, -1, resp);
751
752         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
753         req.fbo = rte_cpu_to_le_32(0);
754         /* Association of ring index with doorbell index */
755         req.logical_id = rte_cpu_to_le_16(map_index);
756         req.length = rte_cpu_to_le_32(ring->ring_size);
757
758         switch (ring_type) {
759         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
760                 req.queue_id = bp->cos_queue[0].id;
761                 /* FALLTHROUGH */
762         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
763                 req.ring_type = ring_type;
764                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
765                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
766                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
767                         enables |=
768                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
769                 break;
770         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
771                 req.ring_type = ring_type;
772                 /*
773                  * TODO: Some HWRM versions crash with
774                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
775                  */
776                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
777                 break;
778         default:
779                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
780                         ring_type);
781                 return -1;
782         }
783         req.enables = rte_cpu_to_le_32(enables);
784
785         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
786
787         if (rc || resp->error_code) {
788                 if (rc == 0 && resp->error_code)
789                         rc = rte_le_to_cpu_16(resp->error_code);
790                 switch (ring_type) {
791                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
792                         RTE_LOG(ERR, PMD,
793                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
794                         return rc;
795                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
796                         RTE_LOG(ERR, PMD,
797                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
798                         return rc;
799                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
800                         RTE_LOG(ERR, PMD,
801                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
802                         return rc;
803                 default:
804                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
805                         return rc;
806                 }
807         }
808
809         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
810         return rc;
811 }
812
813 int bnxt_hwrm_ring_free(struct bnxt *bp,
814                         struct bnxt_ring *ring, uint32_t ring_type)
815 {
816         int rc;
817         struct hwrm_ring_free_input req = {.req_type = 0 };
818         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
819
820         HWRM_PREP(req, RING_FREE, -1, resp);
821
822         req.ring_type = ring_type;
823         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
824
825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
826
827         if (rc || resp->error_code) {
828                 if (rc == 0 && resp->error_code)
829                         rc = rte_le_to_cpu_16(resp->error_code);
830
831                 switch (ring_type) {
832                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
833                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
834                                 rc);
835                         return rc;
836                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
837                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
838                                 rc);
839                         return rc;
840                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
841                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
842                                 rc);
843                         return rc;
844                 default:
845                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
846                         return rc;
847                 }
848         }
849         return 0;
850 }
851
852 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
853 {
854         int rc = 0;
855         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
856         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
857
858         HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
859
860         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
861         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
862         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
863         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
864
865         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
866
867         HWRM_CHECK_RESULT;
868
869         bp->grp_info[idx].fw_grp_id =
870             rte_le_to_cpu_16(resp->ring_group_id);
871
872         return rc;
873 }
874
875 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
876 {
877         int rc;
878         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
879         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
880
881         HWRM_PREP(req, RING_GRP_FREE, -1, resp);
882
883         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
884
885         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
886
887         HWRM_CHECK_RESULT;
888
889         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
890         return rc;
891 }
892
893 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
894 {
895         int rc = 0;
896         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
897         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
898
899         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
900                 return rc;
901
902         HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
903
904         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
905
906         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
907
908         HWRM_CHECK_RESULT;
909
910         return rc;
911 }
912
913 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
914                                 unsigned int idx __rte_unused)
915 {
916         int rc;
917         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
918         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
919
920         HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
921
922         req.update_period_ms = rte_cpu_to_le_32(0);
923
924         req.stats_dma_addr =
925             rte_cpu_to_le_64(cpr->hw_stats_map);
926
927         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
928
929         HWRM_CHECK_RESULT;
930
931         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
932
933         return rc;
934 }
935
936 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
937                                 unsigned int idx __rte_unused)
938 {
939         int rc;
940         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
941         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
942
943         HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
944
945         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
946
947         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
948
949         HWRM_CHECK_RESULT;
950
951         return rc;
952 }
953
954 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
955 {
956         int rc = 0, i, j;
957         struct hwrm_vnic_alloc_input req = { 0 };
958         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
959
960         /* map ring groups to this vnic */
961         RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
962                 vnic->start_grp_id, vnic->end_grp_id);
963         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
964                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
965         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
966         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
967         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
968         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
969         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
970                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
971         HWRM_PREP(req, VNIC_ALLOC, -1, resp);
972
973         if (vnic->func_default)
974                 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
976
977         HWRM_CHECK_RESULT;
978
979         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
980         return rc;
981 }
982
983 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
984                                         struct bnxt_vnic_info *vnic,
985                                         struct bnxt_plcmodes_cfg *pmode)
986 {
987         int rc = 0;
988         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
989         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
990
991         HWRM_PREP(req, VNIC_PLCMODES_QCFG, -1, resp);
992
993         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
994
995         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
996
997         HWRM_CHECK_RESULT;
998
999         pmode->flags = rte_le_to_cpu_32(resp->flags);
1000         /* dflt_vnic bit doesn't exist in the _cfg command */
1001         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1002         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1003         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1004         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1005
1006         return rc;
1007 }
1008
1009 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1010                                        struct bnxt_vnic_info *vnic,
1011                                        struct bnxt_plcmodes_cfg *pmode)
1012 {
1013         int rc = 0;
1014         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1015         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1016
1017         HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
1018
1019         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1020         req.flags = rte_cpu_to_le_32(pmode->flags);
1021         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1022         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1023         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1024         req.enables = rte_cpu_to_le_32(
1025             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1026             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1027             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1028         );
1029
1030         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1031
1032         HWRM_CHECK_RESULT;
1033
1034         return rc;
1035 }
1036
1037 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1038 {
1039         int rc = 0;
1040         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1041         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1042         uint32_t ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1043         struct bnxt_plcmodes_cfg pmodes;
1044
1045         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1046         if (rc)
1047                 return rc;
1048
1049         HWRM_PREP(req, VNIC_CFG, -1, resp);
1050
1051         /* Only RSS support for now TBD: COS & LB */
1052         req.enables =
1053             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
1054                              HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
1055         if (vnic->lb_rule != 0xffff)
1056                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1057         if (vnic->cos_rule != 0xffff)
1058                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1059         if (vnic->rss_rule != 0xffff)
1060                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1061         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1062         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1063         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1064         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1065         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1066         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1067         req.mru = rte_cpu_to_le_16(vnic->mru);
1068         if (vnic->func_default)
1069                 req.flags |=
1070                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1071         if (vnic->vlan_strip)
1072                 req.flags |=
1073                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1074         if (vnic->bd_stall)
1075                 req.flags |=
1076                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1077         if (vnic->roce_dual)
1078                 req.flags |= rte_cpu_to_le_32(
1079                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1080         if (vnic->roce_only)
1081                 req.flags |= rte_cpu_to_le_32(
1082                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1083         if (vnic->rss_dflt_cr)
1084                 req.flags |= rte_cpu_to_le_32(
1085                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1086
1087         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1088
1089         HWRM_CHECK_RESULT;
1090
1091         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1092
1093         return rc;
1094 }
1095
1096 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1097                 int16_t fw_vf_id)
1098 {
1099         int rc = 0;
1100         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1101         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1102
1103         HWRM_PREP(req, VNIC_QCFG, -1, resp);
1104
1105         req.enables =
1106                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1107         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1108         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1109
1110         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1111
1112         HWRM_CHECK_RESULT;
1113
1114         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1115         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1116         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1117         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1118         vnic->mru = rte_le_to_cpu_16(resp->mru);
1119         vnic->func_default = rte_le_to_cpu_32(
1120                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1121         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1122                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1123         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1124                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1125         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1126                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1127         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1128                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1129         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1130                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1131
1132         return rc;
1133 }
1134
1135 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1136 {
1137         int rc = 0;
1138         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1139         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1140                                                 bp->hwrm_cmd_resp_addr;
1141
1142         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
1143
1144         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1145
1146         HWRM_CHECK_RESULT;
1147
1148         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1149
1150         return rc;
1151 }
1152
1153 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1154 {
1155         int rc = 0;
1156         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1157         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1158                                                 bp->hwrm_cmd_resp_addr;
1159
1160         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
1161
1162         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1163
1164         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1165
1166         HWRM_CHECK_RESULT;
1167
1168         vnic->rss_rule = INVALID_HW_RING_ID;
1169
1170         return rc;
1171 }
1172
1173 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1174 {
1175         int rc = 0;
1176         struct hwrm_vnic_free_input req = {.req_type = 0 };
1177         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1178
1179         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
1180                 return rc;
1181
1182         HWRM_PREP(req, VNIC_FREE, -1, resp);
1183
1184         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1185
1186         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1187
1188         HWRM_CHECK_RESULT;
1189
1190         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1191         return rc;
1192 }
1193
1194 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1195                            struct bnxt_vnic_info *vnic)
1196 {
1197         int rc = 0;
1198         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1199         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1200
1201         HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
1202
1203         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1204
1205         req.ring_grp_tbl_addr =
1206             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1207         req.hash_key_tbl_addr =
1208             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1209         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1210
1211         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1212
1213         HWRM_CHECK_RESULT;
1214
1215         return rc;
1216 }
1217
1218 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1219                         struct bnxt_vnic_info *vnic)
1220 {
1221         int rc = 0;
1222         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1223         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1224         uint16_t size;
1225
1226         HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
1227
1228         req.flags = rte_cpu_to_le_32(
1229                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1230
1231         req.enables = rte_cpu_to_le_32(
1232                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1233
1234         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1235         size -= RTE_PKTMBUF_HEADROOM;
1236
1237         req.jumbo_thresh = rte_cpu_to_le_16(size);
1238         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1239
1240         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1241
1242         HWRM_CHECK_RESULT;
1243
1244         return rc;
1245 }
1246
1247 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1248                         struct bnxt_vnic_info *vnic, bool enable)
1249 {
1250         int rc = 0;
1251         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1252         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1253
1254         HWRM_PREP(req, VNIC_TPA_CFG, -1, resp);
1255
1256         if (enable) {
1257                 req.enables = rte_cpu_to_le_32(
1258                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1259                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1260                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1261                 req.flags = rte_cpu_to_le_32(
1262                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1263                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1264                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1265                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1266                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1267                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1268                 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1269                 req.max_agg_segs = rte_cpu_to_le_16(5);
1270                 req.max_aggs =
1271                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1272                 req.min_agg_len = rte_cpu_to_le_32(512);
1273         }
1274
1275         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1276
1277         HWRM_CHECK_RESULT;
1278
1279         return rc;
1280 }
1281
1282 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1283 {
1284         struct hwrm_func_cfg_input req = {0};
1285         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1286         int rc;
1287
1288         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1289         req.enables = rte_cpu_to_le_32(
1290                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1291         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1292         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1293
1294         HWRM_PREP(req, FUNC_CFG, -1, resp);
1295
1296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1297         HWRM_CHECK_RESULT;
1298
1299         bp->pf.vf_info[vf].random_mac = false;
1300
1301         return rc;
1302 }
1303
1304 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1305                                   uint64_t *dropped)
1306 {
1307         int rc = 0;
1308         struct hwrm_func_qstats_input req = {.req_type = 0};
1309         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1310
1311         HWRM_PREP(req, FUNC_QSTATS, -1, resp);
1312
1313         req.fid = rte_cpu_to_le_16(fid);
1314
1315         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1316
1317         HWRM_CHECK_RESULT;
1318
1319         if (dropped)
1320                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1321
1322         return rc;
1323 }
1324
1325 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1326                           struct rte_eth_stats *stats)
1327 {
1328         int rc = 0;
1329         struct hwrm_func_qstats_input req = {.req_type = 0};
1330         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1331
1332         HWRM_PREP(req, FUNC_QSTATS, -1, resp);
1333
1334         req.fid = rte_cpu_to_le_16(fid);
1335
1336         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1337
1338         HWRM_CHECK_RESULT;
1339
1340         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1341         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1342         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1343         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1344         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1345         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1346
1347         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1348         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1349         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1350         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1351         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1352         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1353
1354         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1355         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1356
1357         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1358
1359         return rc;
1360 }
1361
1362 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1363 {
1364         int rc = 0;
1365         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1366         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1367
1368         HWRM_PREP(req, FUNC_CLR_STATS, -1, resp);
1369
1370         req.fid = rte_cpu_to_le_16(fid);
1371
1372         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1373
1374         HWRM_CHECK_RESULT;
1375
1376         return rc;
1377 }
1378
1379 /*
1380  * HWRM utility functions
1381  */
1382
1383 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1384 {
1385         unsigned int i;
1386         int rc = 0;
1387
1388         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1389                 struct bnxt_tx_queue *txq;
1390                 struct bnxt_rx_queue *rxq;
1391                 struct bnxt_cp_ring_info *cpr;
1392
1393                 if (i >= bp->rx_cp_nr_rings) {
1394                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1395                         cpr = txq->cp_ring;
1396                 } else {
1397                         rxq = bp->rx_queues[i];
1398                         cpr = rxq->cp_ring;
1399                 }
1400
1401                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1402                 if (rc)
1403                         return rc;
1404         }
1405         return 0;
1406 }
1407
1408 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1409 {
1410         int rc;
1411         unsigned int i;
1412         struct bnxt_cp_ring_info *cpr;
1413
1414         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1415
1416                 if (i >= bp->rx_cp_nr_rings)
1417                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1418                 else
1419                         cpr = bp->rx_queues[i]->cp_ring;
1420                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1421                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1422                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1423                         /*
1424                          * TODO. Need a better way to reset grp_info.stats_ctx
1425                          * for Rx rings only. stats_ctx is not saved for Tx
1426                          * in grp_info.
1427                          */
1428                         bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1429                         if (rc)
1430                                 return rc;
1431                 }
1432         }
1433         return 0;
1434 }
1435
1436 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1437 {
1438         unsigned int i;
1439         int rc = 0;
1440
1441         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1442                 struct bnxt_tx_queue *txq;
1443                 struct bnxt_rx_queue *rxq;
1444                 struct bnxt_cp_ring_info *cpr;
1445
1446                 if (i >= bp->rx_cp_nr_rings) {
1447                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1448                         cpr = txq->cp_ring;
1449                 } else {
1450                         rxq = bp->rx_queues[i];
1451                         cpr = rxq->cp_ring;
1452                 }
1453
1454                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1455
1456                 if (rc)
1457                         return rc;
1458         }
1459         return rc;
1460 }
1461
1462 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1463 {
1464         uint16_t idx;
1465         uint32_t rc = 0;
1466
1467         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1468
1469                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1470                         RTE_LOG(ERR, PMD,
1471                                 "Attempt to free invalid ring group %d\n",
1472                                 idx);
1473                         continue;
1474                 }
1475
1476                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1477
1478                 if (rc)
1479                         return rc;
1480         }
1481         return rc;
1482 }
1483
1484 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1485                                 unsigned int idx __rte_unused)
1486 {
1487         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1488
1489         bnxt_hwrm_ring_free(bp, cp_ring,
1490                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1491         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1492         bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1493         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1494                         sizeof(*cpr->cp_desc_ring));
1495         cpr->cp_raw_cons = 0;
1496 }
1497
1498 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1499 {
1500         unsigned int i;
1501         int rc = 0;
1502
1503         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1504                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1505                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1506                 struct bnxt_ring *ring = txr->tx_ring_struct;
1507                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1508                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1509
1510                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1511                         bnxt_hwrm_ring_free(bp, ring,
1512                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1513                         ring->fw_ring_id = INVALID_HW_RING_ID;
1514                         memset(txr->tx_desc_ring, 0,
1515                                         txr->tx_ring_struct->ring_size *
1516                                         sizeof(*txr->tx_desc_ring));
1517                         memset(txr->tx_buf_ring, 0,
1518                                         txr->tx_ring_struct->ring_size *
1519                                         sizeof(*txr->tx_buf_ring));
1520                         txr->tx_prod = 0;
1521                         txr->tx_cons = 0;
1522                 }
1523                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1524                         bnxt_free_cp_ring(bp, cpr, idx);
1525                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1526                 }
1527         }
1528
1529         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1530                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1531                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1532                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1533                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1534                 unsigned int idx = i + 1;
1535
1536                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1537                         bnxt_hwrm_ring_free(bp, ring,
1538                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1539                         ring->fw_ring_id = INVALID_HW_RING_ID;
1540                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1541                         memset(rxr->rx_desc_ring, 0,
1542                                         rxr->rx_ring_struct->ring_size *
1543                                         sizeof(*rxr->rx_desc_ring));
1544                         memset(rxr->rx_buf_ring, 0,
1545                                         rxr->rx_ring_struct->ring_size *
1546                                         sizeof(*rxr->rx_buf_ring));
1547                         rxr->rx_prod = 0;
1548                         memset(rxr->ag_buf_ring, 0,
1549                                         rxr->ag_ring_struct->ring_size *
1550                                         sizeof(*rxr->ag_buf_ring));
1551                         rxr->ag_prod = 0;
1552                 }
1553                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1554                         bnxt_free_cp_ring(bp, cpr, idx);
1555                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1556                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1557                 }
1558         }
1559
1560         /* Default completion ring */
1561         {
1562                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1563
1564                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1565                         bnxt_free_cp_ring(bp, cpr, 0);
1566                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1567                 }
1568         }
1569
1570         return rc;
1571 }
1572
1573 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1574 {
1575         uint16_t i;
1576         uint32_t rc = 0;
1577
1578         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1579                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1580                 if (rc)
1581                         return rc;
1582         }
1583         return rc;
1584 }
1585
1586 void bnxt_free_hwrm_resources(struct bnxt *bp)
1587 {
1588         /* Release memzone */
1589         rte_free(bp->hwrm_cmd_resp_addr);
1590         rte_free(bp->hwrm_short_cmd_req_addr);
1591         bp->hwrm_cmd_resp_addr = NULL;
1592         bp->hwrm_short_cmd_req_addr = NULL;
1593         bp->hwrm_cmd_resp_dma_addr = 0;
1594         bp->hwrm_short_cmd_req_dma_addr = 0;
1595 }
1596
1597 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1598 {
1599         struct rte_pci_device *pdev = bp->pdev;
1600         char type[RTE_MEMZONE_NAMESIZE];
1601
1602         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1603                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1604         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1605         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1606         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1607         if (bp->hwrm_cmd_resp_addr == NULL)
1608                 return -ENOMEM;
1609         bp->hwrm_cmd_resp_dma_addr =
1610                 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
1611         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1612                 RTE_LOG(ERR, PMD,
1613                         "unable to map response address to physical memory\n");
1614                 return -ENOMEM;
1615         }
1616         rte_spinlock_init(&bp->hwrm_lock);
1617
1618         return 0;
1619 }
1620
1621 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1622 {
1623         struct bnxt_filter_info *filter;
1624         int rc = 0;
1625
1626         STAILQ_FOREACH(filter, &vnic->filter, next) {
1627                 rc = bnxt_hwrm_clear_filter(bp, filter);
1628                 if (rc)
1629                         break;
1630         }
1631         return rc;
1632 }
1633
1634 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1635 {
1636         struct bnxt_filter_info *filter;
1637         int rc = 0;
1638
1639         STAILQ_FOREACH(filter, &vnic->filter, next) {
1640                 rc = bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id, filter);
1641                 if (rc)
1642                         break;
1643         }
1644         return rc;
1645 }
1646
1647 void bnxt_free_tunnel_ports(struct bnxt *bp)
1648 {
1649         if (bp->vxlan_port_cnt)
1650                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1651                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1652         bp->vxlan_port = 0;
1653         if (bp->geneve_port_cnt)
1654                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1655                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1656         bp->geneve_port = 0;
1657 }
1658
1659 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1660 {
1661         struct bnxt_vnic_info *vnic;
1662         unsigned int i;
1663
1664         if (bp->vnic_info == NULL)
1665                 return;
1666
1667         vnic = &bp->vnic_info[0];
1668         if (BNXT_PF(bp))
1669                 bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1670
1671         /* VNIC resources */
1672         for (i = 0; i < bp->nr_vnics; i++) {
1673                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1674
1675                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1676
1677                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1678
1679                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1680
1681                 bnxt_hwrm_vnic_free(bp, vnic);
1682         }
1683         /* Ring resources */
1684         bnxt_free_all_hwrm_rings(bp);
1685         bnxt_free_all_hwrm_ring_grps(bp);
1686         bnxt_free_all_hwrm_stat_ctxs(bp);
1687         bnxt_free_tunnel_ports(bp);
1688 }
1689
1690 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1691 {
1692         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1693
1694         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1695                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1696
1697         switch (conf_link_speed) {
1698         case ETH_LINK_SPEED_10M_HD:
1699         case ETH_LINK_SPEED_100M_HD:
1700                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1701         }
1702         return hw_link_duplex;
1703 }
1704
1705 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1706 {
1707         uint16_t eth_link_speed = 0;
1708
1709         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1710                 return ETH_LINK_SPEED_AUTONEG;
1711
1712         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1713         case ETH_LINK_SPEED_100M:
1714         case ETH_LINK_SPEED_100M_HD:
1715                 eth_link_speed =
1716                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1717                 break;
1718         case ETH_LINK_SPEED_1G:
1719                 eth_link_speed =
1720                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1721                 break;
1722         case ETH_LINK_SPEED_2_5G:
1723                 eth_link_speed =
1724                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1725                 break;
1726         case ETH_LINK_SPEED_10G:
1727                 eth_link_speed =
1728                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1729                 break;
1730         case ETH_LINK_SPEED_20G:
1731                 eth_link_speed =
1732                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1733                 break;
1734         case ETH_LINK_SPEED_25G:
1735                 eth_link_speed =
1736                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1737                 break;
1738         case ETH_LINK_SPEED_40G:
1739                 eth_link_speed =
1740                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1741                 break;
1742         case ETH_LINK_SPEED_50G:
1743                 eth_link_speed =
1744                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1745                 break;
1746         default:
1747                 RTE_LOG(ERR, PMD,
1748                         "Unsupported link speed %d; default to AUTO\n",
1749                         conf_link_speed);
1750                 break;
1751         }
1752         return eth_link_speed;
1753 }
1754
1755 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1756                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1757                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1758                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1759
1760 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1761 {
1762         uint32_t one_speed;
1763
1764         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1765                 return 0;
1766
1767         if (link_speed & ETH_LINK_SPEED_FIXED) {
1768                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1769
1770                 if (one_speed & (one_speed - 1)) {
1771                         RTE_LOG(ERR, PMD,
1772                                 "Invalid advertised speeds (%u) for port %u\n",
1773                                 link_speed, port_id);
1774                         return -EINVAL;
1775                 }
1776                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1777                         RTE_LOG(ERR, PMD,
1778                                 "Unsupported advertised speed (%u) for port %u\n",
1779                                 link_speed, port_id);
1780                         return -EINVAL;
1781                 }
1782         } else {
1783                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1784                         RTE_LOG(ERR, PMD,
1785                                 "Unsupported advertised speeds (%u) for port %u\n",
1786                                 link_speed, port_id);
1787                         return -EINVAL;
1788                 }
1789         }
1790         return 0;
1791 }
1792
1793 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
1794 {
1795         uint16_t ret = 0;
1796
1797         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1798                 link_speed = BNXT_SUPPORTED_SPEEDS;
1799
1800         if (link_speed & ETH_LINK_SPEED_100M)
1801                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1802         if (link_speed & ETH_LINK_SPEED_100M_HD)
1803                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1804         if (link_speed & ETH_LINK_SPEED_1G)
1805                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1806         if (link_speed & ETH_LINK_SPEED_2_5G)
1807                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1808         if (link_speed & ETH_LINK_SPEED_10G)
1809                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1810         if (link_speed & ETH_LINK_SPEED_20G)
1811                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1812         if (link_speed & ETH_LINK_SPEED_25G)
1813                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1814         if (link_speed & ETH_LINK_SPEED_40G)
1815                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1816         if (link_speed & ETH_LINK_SPEED_50G)
1817                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1818         return ret;
1819 }
1820
1821 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
1822 {
1823         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
1824
1825         switch (hw_link_speed) {
1826         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
1827                 eth_link_speed = ETH_SPEED_NUM_100M;
1828                 break;
1829         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
1830                 eth_link_speed = ETH_SPEED_NUM_1G;
1831                 break;
1832         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
1833                 eth_link_speed = ETH_SPEED_NUM_2_5G;
1834                 break;
1835         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
1836                 eth_link_speed = ETH_SPEED_NUM_10G;
1837                 break;
1838         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
1839                 eth_link_speed = ETH_SPEED_NUM_20G;
1840                 break;
1841         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
1842                 eth_link_speed = ETH_SPEED_NUM_25G;
1843                 break;
1844         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
1845                 eth_link_speed = ETH_SPEED_NUM_40G;
1846                 break;
1847         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
1848                 eth_link_speed = ETH_SPEED_NUM_50G;
1849                 break;
1850         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
1851         default:
1852                 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
1853                         hw_link_speed);
1854                 break;
1855         }
1856         return eth_link_speed;
1857 }
1858
1859 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
1860 {
1861         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1862
1863         switch (hw_link_duplex) {
1864         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
1865         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
1866                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1867                 break;
1868         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
1869                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
1870                 break;
1871         default:
1872                 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
1873                         hw_link_duplex);
1874                 break;
1875         }
1876         return eth_link_duplex;
1877 }
1878
1879 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
1880 {
1881         int rc = 0;
1882         struct bnxt_link_info *link_info = &bp->link_info;
1883
1884         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
1885         if (rc) {
1886                 RTE_LOG(ERR, PMD,
1887                         "Get link config failed with rc %d\n", rc);
1888                 goto exit;
1889         }
1890         if (link_info->link_up)
1891                 link->link_speed =
1892                         bnxt_parse_hw_link_speed(link_info->link_speed);
1893         else
1894                 link->link_speed = ETH_SPEED_NUM_NONE;
1895         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
1896         link->link_status = link_info->link_up;
1897         link->link_autoneg = link_info->auto_mode ==
1898                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
1899                 ETH_LINK_SPEED_FIXED : ETH_LINK_SPEED_AUTONEG;
1900 exit:
1901         return rc;
1902 }
1903
1904 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1905 {
1906         int rc = 0;
1907         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1908         struct bnxt_link_info link_req;
1909         uint16_t speed;
1910
1911         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
1912                 return 0;
1913
1914         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1915                         bp->eth_dev->data->port_id);
1916         if (rc)
1917                 goto error;
1918
1919         memset(&link_req, 0, sizeof(link_req));
1920         link_req.link_up = link_up;
1921         if (!link_up)
1922                 goto port_phy_cfg;
1923
1924         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1925         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1926         if (speed == 0) {
1927                 link_req.phy_flags |=
1928                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1929                 link_req.auto_mode =
1930                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1931                 link_req.auto_link_speed_mask =
1932                         bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
1933         } else {
1934                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
1935                 link_req.link_speed = speed;
1936                 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
1937         }
1938         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1939         link_req.auto_pause = bp->link_info.auto_pause;
1940         link_req.force_pause = bp->link_info.force_pause;
1941
1942 port_phy_cfg:
1943         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1944         if (rc) {
1945                 RTE_LOG(ERR, PMD,
1946                         "Set link config failed with rc %d\n", rc);
1947         }
1948
1949         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1950 error:
1951         return rc;
1952 }
1953
1954 /* JIRA 22088 */
1955 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
1956 {
1957         struct hwrm_func_qcfg_input req = {0};
1958         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1959         int rc = 0;
1960
1961         HWRM_PREP(req, FUNC_QCFG, -1, resp);
1962         req.fid = rte_cpu_to_le_16(0xffff);
1963
1964         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1965
1966         HWRM_CHECK_RESULT;
1967
1968         /* Hard Coded.. 0xfff VLAN ID mask */
1969         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
1970
1971         switch (resp->port_partition_type) {
1972         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
1973         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
1974         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
1975                 bp->port_partition_type = resp->port_partition_type;
1976                 break;
1977         default:
1978                 bp->port_partition_type = 0;
1979                 break;
1980         }
1981
1982         return rc;
1983 }
1984
1985 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
1986                                    struct hwrm_func_qcaps_output *qcaps)
1987 {
1988         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
1989         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
1990                sizeof(qcaps->mac_address));
1991         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
1992         qcaps->max_rx_rings = fcfg->num_rx_rings;
1993         qcaps->max_tx_rings = fcfg->num_tx_rings;
1994         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
1995         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
1996         qcaps->max_vfs = 0;
1997         qcaps->first_vf_id = 0;
1998         qcaps->max_vnics = fcfg->num_vnics;
1999         qcaps->max_decap_records = 0;
2000         qcaps->max_encap_records = 0;
2001         qcaps->max_tx_wm_flows = 0;
2002         qcaps->max_tx_em_flows = 0;
2003         qcaps->max_rx_wm_flows = 0;
2004         qcaps->max_rx_em_flows = 0;
2005         qcaps->max_flow_id = 0;
2006         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2007         qcaps->max_sp_tx_rings = 0;
2008         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2009 }
2010
2011 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2012 {
2013         struct hwrm_func_cfg_input req = {0};
2014         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2015         int rc;
2016
2017         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2018                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2019                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2020                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2021                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2022                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2023                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2024                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2025                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2026                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2027         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2028         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2029         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2030                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
2031         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2032         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2033         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2034         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2035         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2036         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2037         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2038         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2039         req.fid = rte_cpu_to_le_16(0xffff);
2040
2041         HWRM_PREP(req, FUNC_CFG, -1, resp);
2042
2043         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2044         HWRM_CHECK_RESULT;
2045
2046         return rc;
2047 }
2048
2049 static void populate_vf_func_cfg_req(struct bnxt *bp,
2050                                      struct hwrm_func_cfg_input *req,
2051                                      int num_vfs)
2052 {
2053         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2054                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2055                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2056                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2057                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2058                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2059                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2060                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2061                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2062                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2063
2064         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2065                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2066         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2067                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2068         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2069                                                 (num_vfs + 1));
2070         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2071         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2072                                                (num_vfs + 1));
2073         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2074         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2075         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2076         /* TODO: For now, do not support VMDq/RFS on VFs. */
2077         req->num_vnics = rte_cpu_to_le_16(1);
2078         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2079                                                  (num_vfs + 1));
2080 }
2081
2082 static void add_random_mac_if_needed(struct bnxt *bp,
2083                                      struct hwrm_func_cfg_input *cfg_req,
2084                                      int vf)
2085 {
2086         struct ether_addr mac;
2087
2088         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2089                 return;
2090
2091         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2092                 cfg_req->enables |=
2093                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2094                 eth_random_addr(cfg_req->dflt_mac_addr);
2095                 bp->pf.vf_info[vf].random_mac = true;
2096         } else {
2097                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2098         }
2099 }
2100
2101 static void reserve_resources_from_vf(struct bnxt *bp,
2102                                       struct hwrm_func_cfg_input *cfg_req,
2103                                       int vf)
2104 {
2105         struct hwrm_func_qcaps_input req = {0};
2106         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2107         int rc;
2108
2109         /* Get the actual allocated values now */
2110         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
2111         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2112         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2113
2114         if (rc) {
2115                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2116                 copy_func_cfg_to_qcaps(cfg_req, resp);
2117         } else if (resp->error_code) {
2118                 rc = rte_le_to_cpu_16(resp->error_code);
2119                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2120                 copy_func_cfg_to_qcaps(cfg_req, resp);
2121         }
2122
2123         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2124         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2125         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2126         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2127         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2128         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2129         /*
2130          * TODO: While not supporting VMDq with VFs, max_vnics is always
2131          * forced to 1 in this case
2132          */
2133         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2134         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2135 }
2136
2137 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2138 {
2139         struct hwrm_func_qcfg_input req = {0};
2140         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2141         int rc;
2142
2143         /* Check for zero MAC address */
2144         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2145         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2146         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2147         if (rc) {
2148                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2149                 return -1;
2150         } else if (resp->error_code) {
2151                 rc = rte_le_to_cpu_16(resp->error_code);
2152                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2153                 return -1;
2154         }
2155         return rte_le_to_cpu_16(resp->vlan);
2156 }
2157
2158 static int update_pf_resource_max(struct bnxt *bp)
2159 {
2160         struct hwrm_func_qcfg_input req = {0};
2161         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2162         int rc;
2163
2164         /* And copy the allocated numbers into the pf struct */
2165         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2166         req.fid = rte_cpu_to_le_16(0xffff);
2167         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2168         HWRM_CHECK_RESULT;
2169
2170         /* Only TX ring value reflects actual allocation? TODO */
2171         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2172         bp->pf.evb_mode = resp->evb_mode;
2173
2174         return rc;
2175 }
2176
2177 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2178 {
2179         int rc;
2180
2181         if (!BNXT_PF(bp)) {
2182                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2183                 return -1;
2184         }
2185
2186         rc = bnxt_hwrm_func_qcaps(bp);
2187         if (rc)
2188                 return rc;
2189
2190         bp->pf.func_cfg_flags &=
2191                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2192                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2193         bp->pf.func_cfg_flags |=
2194                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2195         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2196         return rc;
2197 }
2198
2199 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2200 {
2201         struct hwrm_func_cfg_input req = {0};
2202         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2203         int i;
2204         size_t sz;
2205         int rc = 0;
2206         size_t req_buf_sz;
2207
2208         if (!BNXT_PF(bp)) {
2209                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2210                 return -1;
2211         }
2212
2213         rc = bnxt_hwrm_func_qcaps(bp);
2214
2215         if (rc)
2216                 return rc;
2217
2218         bp->pf.active_vfs = num_vfs;
2219
2220         /*
2221          * First, configure the PF to only use one TX ring.  This ensures that
2222          * there are enough rings for all VFs.
2223          *
2224          * If we don't do this, when we call func_alloc() later, we will lock
2225          * extra rings to the PF that won't be available during func_cfg() of
2226          * the VFs.
2227          *
2228          * This has been fixed with firmware versions above 20.6.54
2229          */
2230         bp->pf.func_cfg_flags &=
2231                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2232                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2233         bp->pf.func_cfg_flags |=
2234                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2235         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2236         if (rc)
2237                 return rc;
2238
2239         /*
2240          * Now, create and register a buffer to hold forwarded VF requests
2241          */
2242         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2243         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2244                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2245         if (bp->pf.vf_req_buf == NULL) {
2246                 rc = -ENOMEM;
2247                 goto error_free;
2248         }
2249         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2250                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2251         for (i = 0; i < num_vfs; i++)
2252                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2253                                         (i * HWRM_MAX_REQ_LEN);
2254
2255         rc = bnxt_hwrm_func_buf_rgtr(bp);
2256         if (rc)
2257                 goto error_free;
2258
2259         populate_vf_func_cfg_req(bp, &req, num_vfs);
2260
2261         bp->pf.active_vfs = 0;
2262         for (i = 0; i < num_vfs; i++) {
2263                 add_random_mac_if_needed(bp, &req, i);
2264
2265                 HWRM_PREP(req, FUNC_CFG, -1, resp);
2266                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2267                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2268                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2269
2270                 /* Clear enable flag for next pass */
2271                 req.enables &= ~rte_cpu_to_le_32(
2272                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2273
2274                 if (rc || resp->error_code) {
2275                         RTE_LOG(ERR, PMD,
2276                                 "Failed to initizlie VF %d\n", i);
2277                         RTE_LOG(ERR, PMD,
2278                                 "Not all VFs available. (%d, %d)\n",
2279                                 rc, resp->error_code);
2280                         break;
2281                 }
2282
2283                 reserve_resources_from_vf(bp, &req, i);
2284                 bp->pf.active_vfs++;
2285         }
2286
2287         /*
2288          * Now configure the PF to use "the rest" of the resources
2289          * We're using STD_TX_RING_MODE here though which will limit the TX
2290          * rings.  This will allow QoS to function properly.  Not setting this
2291          * will cause PF rings to break bandwidth settings.
2292          */
2293         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2294         if (rc)
2295                 goto error_free;
2296
2297         rc = update_pf_resource_max(bp);
2298         if (rc)
2299                 goto error_free;
2300
2301         return rc;
2302
2303 error_free:
2304         bnxt_hwrm_func_buf_unrgtr(bp);
2305         return rc;
2306 }
2307
2308 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2309 {
2310         struct hwrm_func_cfg_input req = {0};
2311         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2312         int rc;
2313
2314         HWRM_PREP(req, FUNC_CFG, -1, resp);
2315
2316         req.fid = rte_cpu_to_le_16(0xffff);
2317         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2318         req.evb_mode = bp->pf.evb_mode;
2319
2320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2321         HWRM_CHECK_RESULT;
2322
2323         return rc;
2324 }
2325
2326 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2327                                 uint8_t tunnel_type)
2328 {
2329         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2330         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2331         int rc = 0;
2332
2333         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, -1, resp);
2334         req.tunnel_type = tunnel_type;
2335         req.tunnel_dst_port_val = port;
2336         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2337         HWRM_CHECK_RESULT;
2338
2339         switch (tunnel_type) {
2340         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2341                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2342                 bp->vxlan_port = port;
2343                 break;
2344         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2345                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2346                 bp->geneve_port = port;
2347                 break;
2348         default:
2349                 break;
2350         }
2351         return rc;
2352 }
2353
2354 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2355                                 uint8_t tunnel_type)
2356 {
2357         struct hwrm_tunnel_dst_port_free_input req = {0};
2358         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2359         int rc = 0;
2360
2361         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, -1, resp);
2362         req.tunnel_type = tunnel_type;
2363         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2365         HWRM_CHECK_RESULT;
2366
2367         return rc;
2368 }
2369
2370 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2371                                         uint32_t flags)
2372 {
2373         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2374         struct hwrm_func_cfg_input req = {0};
2375         int rc;
2376
2377         HWRM_PREP(req, FUNC_CFG, -1, resp);
2378         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2379         req.flags = rte_cpu_to_le_32(flags);
2380         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2381         HWRM_CHECK_RESULT;
2382
2383         return rc;
2384 }
2385
2386 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2387 {
2388         uint32_t *flag = flagp;
2389
2390         vnic->flags = *flag;
2391 }
2392
2393 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2394 {
2395         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2396 }
2397
2398 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2399 {
2400         int rc = 0;
2401         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2402         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2403
2404         HWRM_PREP(req, FUNC_BUF_RGTR, -1, resp);
2405
2406         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2407         req.req_buf_page_size = rte_cpu_to_le_16(
2408                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2409         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2410         req.req_buf_page_addr[0] =
2411                 rte_cpu_to_le_64(rte_mem_virt2phy(bp->pf.vf_req_buf));
2412         if (req.req_buf_page_addr[0] == 0) {
2413                 RTE_LOG(ERR, PMD,
2414                         "unable to map buffer address to physical memory\n");
2415                 return -ENOMEM;
2416         }
2417
2418         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2419
2420         HWRM_CHECK_RESULT;
2421
2422         return rc;
2423 }
2424
2425 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2426 {
2427         int rc = 0;
2428         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2429         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2430
2431         HWRM_PREP(req, FUNC_BUF_UNRGTR, -1, resp);
2432
2433         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2434
2435         HWRM_CHECK_RESULT;
2436
2437         return rc;
2438 }
2439
2440 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2441 {
2442         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2443         struct hwrm_func_cfg_input req = {0};
2444         int rc;
2445
2446         HWRM_PREP(req, FUNC_CFG, -1, resp);
2447         req.fid = rte_cpu_to_le_16(0xffff);
2448         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2449         req.enables = rte_cpu_to_le_32(
2450                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2451         req.async_event_cr = rte_cpu_to_le_16(
2452                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2453         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2454         HWRM_CHECK_RESULT;
2455
2456         return rc;
2457 }
2458
2459 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2460 {
2461         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2462         struct hwrm_func_vf_cfg_input req = {0};
2463         int rc;
2464
2465         HWRM_PREP(req, FUNC_VF_CFG, -1, resp);
2466         req.enables = rte_cpu_to_le_32(
2467                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2468         req.async_event_cr = rte_cpu_to_le_16(
2469                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2470         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2471         HWRM_CHECK_RESULT;
2472
2473         return rc;
2474 }
2475
2476 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2477 {
2478         struct hwrm_func_cfg_input req = {0};
2479         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2480         uint16_t dflt_vlan, fid;
2481         uint32_t func_cfg_flags;
2482         int rc = 0;
2483
2484         HWRM_PREP(req, FUNC_CFG, -1, resp);
2485
2486         if (is_vf) {
2487                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2488                 fid = bp->pf.vf_info[vf].fid;
2489                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2490         } else {
2491                 fid = rte_cpu_to_le_16(0xffff);
2492                 func_cfg_flags = bp->pf.func_cfg_flags;
2493                 dflt_vlan = bp->vlan;
2494         }
2495
2496         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2497         req.fid = rte_cpu_to_le_16(fid);
2498         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2499         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2500
2501         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2502         HWRM_CHECK_RESULT;
2503
2504         return rc;
2505 }
2506
2507 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2508                         uint16_t max_bw, uint16_t enables)
2509 {
2510         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2511         struct hwrm_func_cfg_input req = {0};
2512         int rc;
2513
2514         HWRM_PREP(req, FUNC_CFG, -1, resp);
2515         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2516         req.enables |= rte_cpu_to_le_32(enables);
2517         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2518         req.max_bw = rte_cpu_to_le_32(max_bw);
2519         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2520         HWRM_CHECK_RESULT;
2521
2522         return rc;
2523 }
2524
2525 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2526 {
2527         struct hwrm_func_cfg_input req = {0};
2528         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2529         int rc = 0;
2530
2531         HWRM_PREP(req, FUNC_CFG, -1, resp);
2532         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2533         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2534         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2535         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2536
2537         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2538         HWRM_CHECK_RESULT;
2539
2540         return rc;
2541 }
2542
2543 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2544                               void *encaped, size_t ec_size)
2545 {
2546         int rc = 0;
2547         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2548         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2549
2550         if (ec_size > sizeof(req.encap_request))
2551                 return -1;
2552
2553         HWRM_PREP(req, REJECT_FWD_RESP, -1, resp);
2554
2555         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2556         memcpy(req.encap_request, encaped, ec_size);
2557
2558         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2559
2560         HWRM_CHECK_RESULT;
2561
2562         return rc;
2563 }
2564
2565 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2566                                        struct ether_addr *mac)
2567 {
2568         struct hwrm_func_qcfg_input req = {0};
2569         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2570         int rc;
2571
2572         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2573         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2574         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2575
2576         HWRM_CHECK_RESULT;
2577
2578         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2579         return rc;
2580 }
2581
2582 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2583                             void *encaped, size_t ec_size)
2584 {
2585         int rc = 0;
2586         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2587         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2588
2589         if (ec_size > sizeof(req.encap_request))
2590                 return -1;
2591
2592         HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
2593
2594         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2595         memcpy(req.encap_request, encaped, ec_size);
2596
2597         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2598
2599         HWRM_CHECK_RESULT;
2600
2601         return rc;
2602 }
2603
2604 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2605                          struct rte_eth_stats *stats)
2606 {
2607         int rc = 0;
2608         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2609         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2610
2611         HWRM_PREP(req, STAT_CTX_QUERY, -1, resp);
2612
2613         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2614
2615         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2616
2617         HWRM_CHECK_RESULT;
2618
2619         stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2620         stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2621         stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2622         stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2623         stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2624         stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2625
2626         stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2627         stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2628         stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2629         stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2630         stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2631         stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2632
2633         stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2634         stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2635         stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2636
2637         return rc;
2638 }
2639
2640 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2641 {
2642         struct hwrm_port_qstats_input req = {0};
2643         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2644         struct bnxt_pf_info *pf = &bp->pf;
2645         int rc;
2646
2647         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2648                 return 0;
2649
2650         HWRM_PREP(req, PORT_QSTATS, -1, resp);
2651         req.port_id = rte_cpu_to_le_16(pf->port_id);
2652         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2653         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2654         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2655         HWRM_CHECK_RESULT;
2656         return rc;
2657 }
2658
2659 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2660 {
2661         struct hwrm_port_clr_stats_input req = {0};
2662         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2663         struct bnxt_pf_info *pf = &bp->pf;
2664         int rc;
2665
2666         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2667                 return 0;
2668
2669         HWRM_PREP(req, PORT_CLR_STATS, -1, resp);
2670         req.port_id = rte_cpu_to_le_16(pf->port_id);
2671         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2672         HWRM_CHECK_RESULT;
2673         return rc;
2674 }
2675
2676 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2677 {
2678         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2679         struct hwrm_port_led_qcaps_input req = {0};
2680         int rc;
2681
2682         if (BNXT_VF(bp))
2683                 return 0;
2684
2685         HWRM_PREP(req, PORT_LED_QCAPS, -1, resp);
2686         req.port_id = bp->pf.port_id;
2687         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2688         HWRM_CHECK_RESULT;
2689
2690         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2691                 unsigned int i;
2692
2693                 bp->num_leds = resp->num_leds;
2694                 memcpy(bp->leds, &resp->led0_id,
2695                         sizeof(bp->leds[0]) * bp->num_leds);
2696                 for (i = 0; i < bp->num_leds; i++) {
2697                         struct bnxt_led_info *led = &bp->leds[i];
2698
2699                         uint16_t caps = led->led_state_caps;
2700
2701                         if (!led->led_group_id ||
2702                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
2703                                 bp->num_leds = 0;
2704                                 break;
2705                         }
2706                 }
2707         }
2708         return rc;
2709 }
2710
2711 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
2712 {
2713         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2714         struct hwrm_port_led_cfg_input req = {0};
2715         struct bnxt_led_cfg *led_cfg;
2716         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
2717         uint16_t duration = 0;
2718         int rc, i;
2719
2720         if (!bp->num_leds || BNXT_VF(bp))
2721                 return -EOPNOTSUPP;
2722
2723         HWRM_PREP(req, PORT_LED_CFG, -1, resp);
2724         if (led_on) {
2725                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
2726                 duration = rte_cpu_to_le_16(500);
2727         }
2728         req.port_id = bp->pf.port_id;
2729         req.num_leds = bp->num_leds;
2730         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
2731         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
2732                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
2733                 led_cfg->led_id = bp->leds[i].led_id;
2734                 led_cfg->led_state = led_state;
2735                 led_cfg->led_blink_on = duration;
2736                 led_cfg->led_blink_off = duration;
2737                 led_cfg->led_group_id = bp->leds[i].led_group_id;
2738         }
2739
2740         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2741         HWRM_CHECK_RESULT;
2742
2743         return rc;
2744 }
2745
2746 static void
2747 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
2748 {
2749         uint32_t *count = cbdata;
2750
2751         *count = *count + 1;
2752 }
2753
2754 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
2755                                      struct bnxt_vnic_info *vnic __rte_unused)
2756 {
2757         return 0;
2758 }
2759
2760 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
2761 {
2762         uint32_t count = 0;
2763
2764         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
2765             &count, bnxt_vnic_count_hwrm_stub);
2766
2767         return count;
2768 }
2769
2770 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
2771                                         uint16_t *vnic_ids)
2772 {
2773         struct hwrm_func_vf_vnic_ids_query_input req = {0};
2774         struct hwrm_func_vf_vnic_ids_query_output *resp =
2775                                                 bp->hwrm_cmd_resp_addr;
2776         int rc;
2777
2778         /* First query all VNIC ids */
2779         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, -1, resp_vf_vnic_ids);
2780
2781         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
2782         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
2783         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2phy(vnic_ids));
2784
2785         if (req.vnic_id_tbl_addr == 0) {
2786                 RTE_LOG(ERR, PMD,
2787                 "unable to map VNIC ID table address to physical memory\n");
2788                 return -ENOMEM;
2789         }
2790         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2791         if (rc) {
2792                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
2793                 return -1;
2794         } else if (resp->error_code) {
2795                 rc = rte_le_to_cpu_16(resp->error_code);
2796                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
2797                 return -1;
2798         }
2799
2800         return rte_le_to_cpu_32(resp->vnic_id_cnt);
2801 }
2802
2803 /*
2804  * This function queries the VNIC IDs  for a specified VF. It then calls
2805  * the vnic_cb to update the necessary field in vnic_info with cbdata.
2806  * Then it calls the hwrm_cb function to program this new vnic configuration.
2807  */
2808 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
2809         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
2810         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
2811 {
2812         struct bnxt_vnic_info vnic;
2813         int rc = 0;
2814         int i, num_vnic_ids;
2815         uint16_t *vnic_ids;
2816         size_t vnic_id_sz;
2817         size_t sz;
2818
2819         /* First query all VNIC ids */
2820         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2821         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2822                         RTE_CACHE_LINE_SIZE);
2823         if (vnic_ids == NULL) {
2824                 rc = -ENOMEM;
2825                 return rc;
2826         }
2827         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2828                 rte_mem_lock_page(((char *)vnic_ids) + sz);
2829
2830         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2831
2832         if (num_vnic_ids < 0)
2833                 return num_vnic_ids;
2834
2835         /* Retrieve VNIC, update bd_stall then update */
2836
2837         for (i = 0; i < num_vnic_ids; i++) {
2838                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2839                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2840                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
2841                 if (rc)
2842                         break;
2843                 if (vnic.mru <= 4)      /* Indicates unallocated */
2844                         continue;
2845
2846                 vnic_cb(&vnic, cbdata);
2847
2848                 rc = hwrm_cb(bp, &vnic);
2849                 if (rc)
2850                         break;
2851         }
2852
2853         rte_free(vnic_ids);
2854
2855         return rc;
2856 }
2857
2858 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
2859                                               bool on)
2860 {
2861         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2862         struct hwrm_func_cfg_input req = {0};
2863         int rc;
2864
2865         HWRM_PREP(req, FUNC_CFG, -1, resp);
2866         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2867         req.enables |= rte_cpu_to_le_32(
2868                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
2869         req.vlan_antispoof_mode = on ?
2870                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
2871                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
2872         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2873         HWRM_CHECK_RESULT;
2874
2875         return rc;
2876 }
2877
2878 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
2879 {
2880         struct bnxt_vnic_info vnic;
2881         uint16_t *vnic_ids;
2882         size_t vnic_id_sz;
2883         int num_vnic_ids, i;
2884         size_t sz;
2885         int rc;
2886
2887         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2888         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2889                         RTE_CACHE_LINE_SIZE);
2890         if (vnic_ids == NULL) {
2891                 rc = -ENOMEM;
2892                 return rc;
2893         }
2894
2895         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2896                 rte_mem_lock_page(((char *)vnic_ids) + sz);
2897
2898         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2899         if (rc <= 0)
2900                 goto exit;
2901         num_vnic_ids = rc;
2902
2903         /*
2904          * Loop through to find the default VNIC ID.
2905          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
2906          * by sending the hwrm_func_qcfg command to the firmware.
2907          */
2908         for (i = 0; i < num_vnic_ids; i++) {
2909                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2910                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2911                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
2912                                         bp->pf.first_vf_id + vf);
2913                 if (rc)
2914                         goto exit;
2915                 if (vnic.func_default) {
2916                         rte_free(vnic_ids);
2917                         return vnic.fw_vnic_id;
2918                 }
2919         }
2920         /* Could not find a default VNIC. */
2921         RTE_LOG(ERR, PMD, "No default VNIC\n");
2922 exit:
2923         rte_free(vnic_ids);
2924         return -1;
2925 }