4 * Copyright(c) Broadcom Limited.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_byteorder.h>
35 #include <rte_common.h>
36 #include <rte_cycles.h>
37 #include <rte_malloc.h>
38 #include <rte_memzone.h>
39 #include <rte_version.h>
43 #include "bnxt_filter.h"
44 #include "bnxt_hwrm.h"
46 #include "bnxt_ring.h"
48 #include "bnxt_vnic.h"
49 #include "hsi_struct_def_dpdk.h"
51 #define HWRM_CMD_TIMEOUT 2000
54 * HWRM Functions (sent to HWRM)
55 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
56 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
57 * command was failed by the ChiMP.
60 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
64 struct input *req = msg;
65 struct output *resp = bp->hwrm_cmd_resp_addr;
70 /* Write request msg to hwrm channel */
71 for (i = 0; i < msg_len; i += 4) {
72 bar = (uint8_t *)bp->bar0 + i;
73 *(volatile uint32_t *)bar = *data;
77 /* Zero the rest of the request space */
78 for (; i < bp->max_req_len; i += 4) {
79 bar = (uint8_t *)bp->bar0 + i;
80 *(volatile uint32_t *)bar = 0;
83 /* Ring channel doorbell */
84 bar = (uint8_t *)bp->bar0 + 0x100;
85 *(volatile uint32_t *)bar = 1;
87 /* Poll for the valid bit */
88 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
89 /* Sanity check on the resp->resp_len */
91 if (resp->resp_len && resp->resp_len <=
93 /* Last byte of resp contains the valid key */
94 valid = (uint8_t *)resp + resp->resp_len - 1;
95 if (*valid == HWRM_RESP_VALID_KEY)
101 if (i >= HWRM_CMD_TIMEOUT) {
102 RTE_LOG(ERR, PMD, "Error sending msg %x\n",
112 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
116 rte_spinlock_lock(&bp->hwrm_lock);
117 rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
118 rte_spinlock_unlock(&bp->hwrm_lock);
122 #define HWRM_PREP(req, type, cr, resp) \
123 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
124 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
125 req.cmpl_ring = rte_cpu_to_le_16(cr); \
126 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
127 req.target_id = rte_cpu_to_le_16(0xffff); \
128 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
130 #define HWRM_CHECK_RESULT \
133 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
137 if (resp->error_code) { \
138 rc = rte_le_to_cpu_16(resp->error_code); \
139 RTE_LOG(ERR, PMD, "%s error %d\n", __func__, rc); \
144 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
147 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
148 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
150 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
151 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
154 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
161 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
164 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
165 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
168 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
169 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
171 /* FIXME add multicast flag, when multicast adding options is supported
174 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
175 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
176 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
177 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
178 req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST |
179 HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
182 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
189 int bnxt_hwrm_clear_filter(struct bnxt *bp,
190 struct bnxt_filter_info *filter)
193 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
194 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
196 HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
198 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
200 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
204 filter->fw_l2_filter_id = -1;
209 int bnxt_hwrm_set_filter(struct bnxt *bp,
210 struct bnxt_vnic_info *vnic,
211 struct bnxt_filter_info *filter)
214 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
215 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
216 uint32_t enables = 0;
218 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
220 req.flags = rte_cpu_to_le_32(filter->flags);
222 enables = filter->enables |
223 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
224 req.dst_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
227 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
228 memcpy(req.l2_addr, filter->l2_addr,
231 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
232 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
235 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
236 req.l2_ovlan = filter->l2_ovlan;
238 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
239 req.l2_ovlan_mask = filter->l2_ovlan_mask;
241 req.enables = rte_cpu_to_le_32(enables);
243 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
247 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
252 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, void *fwd_cmd)
255 struct hwrm_exec_fwd_resp_input req = {.req_type = 0 };
256 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
258 HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
260 memcpy(req.encap_request, fwd_cmd,
261 sizeof(req.encap_request));
263 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
270 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
273 struct hwrm_func_qcaps_input req = {.req_type = 0 };
274 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
276 HWRM_PREP(req, FUNC_QCAPS, -1, resp);
278 req.fid = rte_cpu_to_le_16(0xffff);
280 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
284 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
286 struct bnxt_pf_info *pf = &bp->pf;
288 pf->fw_fid = rte_le_to_cpu_32(resp->fid);
289 pf->port_id = resp->port_id;
290 memcpy(pf->mac_addr, resp->perm_mac_address, ETHER_ADDR_LEN);
291 pf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
292 pf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
293 pf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
294 pf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
295 pf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
296 pf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
297 pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
298 pf->max_vfs = rte_le_to_cpu_16(resp->max_vfs);
300 struct bnxt_vf_info *vf = &bp->vf;
302 vf->fw_fid = rte_le_to_cpu_32(resp->fid);
303 memcpy(vf->mac_addr, &resp->perm_mac_address, ETHER_ADDR_LEN);
304 vf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
305 vf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
306 vf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
307 vf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
308 vf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
309 vf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
315 int bnxt_hwrm_func_reset(struct bnxt *bp)
318 struct hwrm_func_reset_input req = {.req_type = 0 };
319 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
321 HWRM_PREP(req, FUNC_RESET, -1, resp);
323 req.enables = rte_cpu_to_le_32(0);
325 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
332 int bnxt_hwrm_func_driver_register(struct bnxt *bp, uint32_t flags,
333 uint32_t *vf_req_fwd)
336 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
337 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
339 if (bp->flags & BNXT_FLAG_REGISTERED)
342 HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
344 req.enables = HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER;
345 req.ver_maj = RTE_VER_YEAR;
346 req.ver_min = RTE_VER_MONTH;
347 req.ver_upd = RTE_VER_MINOR;
349 memcpy(req.vf_req_fwd, vf_req_fwd, sizeof(req.vf_req_fwd));
351 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
355 bp->flags |= BNXT_FLAG_REGISTERED;
360 int bnxt_hwrm_ver_get(struct bnxt *bp)
363 struct hwrm_ver_get_input req = {.req_type = 0 };
364 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
367 uint16_t max_resp_len;
368 char type[RTE_MEMZONE_NAMESIZE];
370 HWRM_PREP(req, VER_GET, -1, resp);
372 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
373 req.hwrm_intf_min = HWRM_VERSION_MINOR;
374 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
377 * Hold the lock since we may be adjusting the response pointers.
379 rte_spinlock_lock(&bp->hwrm_lock);
380 rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
384 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
385 resp->hwrm_intf_maj, resp->hwrm_intf_min,
387 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
389 my_version = HWRM_VERSION_MAJOR << 16;
390 my_version |= HWRM_VERSION_MINOR << 8;
391 my_version |= HWRM_VERSION_UPDATE;
393 fw_version = resp->hwrm_intf_maj << 16;
394 fw_version |= resp->hwrm_intf_min << 8;
395 fw_version |= resp->hwrm_intf_upd;
397 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
398 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
403 if (my_version != fw_version) {
404 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
405 if (my_version < fw_version) {
407 "Firmware API version is newer than driver.\n");
409 "The driver may be missing features.\n");
412 "Firmware API version is older than driver.\n");
414 "Not all driver features may be functional.\n");
418 if (bp->max_req_len > resp->max_req_win_len) {
419 RTE_LOG(ERR, PMD, "Unsupported request length\n");
422 bp->max_req_len = resp->max_req_win_len;
423 max_resp_len = resp->max_resp_len;
424 if (bp->max_resp_len != max_resp_len) {
425 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
426 bp->pdev->addr.domain, bp->pdev->addr.bus,
427 bp->pdev->addr.devid, bp->pdev->addr.function);
429 rte_free(bp->hwrm_cmd_resp_addr);
431 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
432 if (bp->hwrm_cmd_resp_addr == NULL) {
436 bp->hwrm_cmd_resp_dma_addr =
437 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
438 bp->max_resp_len = max_resp_len;
442 rte_spinlock_unlock(&bp->hwrm_lock);
446 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
449 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
450 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
452 if (!(bp->flags & BNXT_FLAG_REGISTERED))
455 HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
458 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
462 bp->flags &= ~BNXT_FLAG_REGISTERED;
467 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
470 struct hwrm_port_phy_cfg_input req = {.req_type = 0};
471 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
473 HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
475 req.flags = conf->phy_flags;
477 req.force_link_speed = conf->link_speed;
479 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
480 * any auto mode, even "none".
482 if (req.auto_mode == HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE) {
483 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
485 req.auto_mode = conf->auto_mode;
487 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
488 req.auto_link_speed_mask = conf->auto_link_speed_mask;
490 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
491 req.auto_link_speed = conf->auto_link_speed;
493 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
495 req.auto_duplex = conf->duplex;
496 req.enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
497 req.auto_pause = conf->auto_pause;
498 /* Set force_pause if there is no auto or if there is a force */
501 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
504 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
505 req.force_pause = conf->force_pause;
508 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
510 req.flags &= ~HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
511 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN;
512 req.force_link_speed = 0;
515 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
522 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
525 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
526 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
528 HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
530 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
534 #define GET_QUEUE_INFO(x) \
535 bp->cos_queue[x].id = resp->queue_id##x; \
536 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
550 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
553 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
554 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
556 HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
558 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
561 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
562 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
564 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
571 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp,
572 struct bnxt_cp_ring_info *cpr, unsigned int idx)
575 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
576 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
578 HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
580 req.update_period_ms = rte_cpu_to_le_32(1000);
582 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
584 rte_cpu_to_le_64(cpr->hw_stats_map);
586 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
590 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
591 bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
596 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
599 struct hwrm_vnic_alloc_input req = {.req_type = 0 };
600 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
602 /* map ring groups to this vnic */
603 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++) {
604 if (bp->grp_info[i].fw_grp_id == (uint16_t)HWRM_NA_SIGNATURE) {
606 "Not enough ring groups avail:%x req:%x\n", j,
607 (vnic->end_grp_id - vnic->start_grp_id) + 1);
610 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
613 vnic->fw_rss_cos_lb_ctx = (uint16_t)HWRM_NA_SIGNATURE;
614 vnic->ctx_is_rss_cos_lb = HW_CONTEXT_NONE;
616 HWRM_PREP(req, VNIC_ALLOC, -1, resp);
618 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
622 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
626 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
629 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
630 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
632 HWRM_PREP(req, VNIC_CFG, -1, resp);
634 /* Only RSS support for now TBD: COS & LB */
636 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
637 HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE |
638 HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
639 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
641 rte_cpu_to_le_16(bp->grp_info[vnic->start_grp_id].fw_grp_id);
642 req.rss_rule = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
643 req.cos_rule = rte_cpu_to_le_16(0xffff);
644 req.lb_rule = rte_cpu_to_le_16(0xffff);
645 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
646 ETHER_CRC_LEN + VLAN_TAG_SIZE);
647 if (vnic->func_default)
649 if (vnic->vlan_strip)
651 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
653 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
660 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
663 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
664 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
665 bp->hwrm_cmd_resp_addr;
667 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
669 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
673 vnic->fw_rss_cos_lb_ctx = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
678 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
681 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
682 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
683 bp->hwrm_cmd_resp_addr;
685 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
687 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
689 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
693 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
698 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
701 struct hwrm_vnic_free_input req = {.req_type = 0 };
702 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
704 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
707 HWRM_PREP(req, VNIC_FREE, -1, resp);
709 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
711 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
715 vnic->fw_vnic_id = INVALID_HW_RING_ID;
719 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
720 struct bnxt_vnic_info *vnic)
723 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
724 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
726 HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
728 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
730 req.ring_grp_tbl_addr =
731 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
732 req.hash_key_tbl_addr =
733 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
734 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
736 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
744 * HWRM utility functions
747 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
752 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
753 struct bnxt_tx_queue *txq;
754 struct bnxt_rx_queue *rxq;
755 struct bnxt_cp_ring_info *cpr;
757 if (i >= bp->rx_cp_nr_rings) {
758 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
761 rxq = bp->rx_queues[i];
765 rc = bnxt_hwrm_stat_clear(bp, cpr);
772 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
777 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
778 struct bnxt_tx_queue *txq;
779 struct bnxt_rx_queue *rxq;
780 struct bnxt_cp_ring_info *cpr;
781 unsigned int idx = i + 1;
783 if (i >= bp->rx_cp_nr_rings) {
784 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
787 rxq = bp->rx_queues[i];
791 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, idx);
799 void bnxt_free_hwrm_resources(struct bnxt *bp)
801 /* Release memzone */
802 rte_free(bp->hwrm_cmd_resp_addr);
803 bp->hwrm_cmd_resp_addr = NULL;
804 bp->hwrm_cmd_resp_dma_addr = 0;
807 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
809 struct rte_pci_device *pdev = bp->pdev;
810 char type[RTE_MEMZONE_NAMESIZE];
812 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
813 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
814 bp->max_req_len = HWRM_MAX_REQ_LEN;
815 bp->max_resp_len = HWRM_MAX_RESP_LEN;
816 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
817 if (bp->hwrm_cmd_resp_addr == NULL)
819 bp->hwrm_cmd_resp_dma_addr =
820 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
821 rte_spinlock_init(&bp->hwrm_lock);
826 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
828 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
830 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
831 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
833 switch (conf_link_speed) {
834 case ETH_LINK_SPEED_10M_HD:
835 case ETH_LINK_SPEED_100M_HD:
836 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
838 return hw_link_duplex;
841 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
843 uint16_t eth_link_speed = 0;
845 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
846 return ETH_LINK_SPEED_AUTONEG;
848 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
849 case ETH_LINK_SPEED_100M:
850 case ETH_LINK_SPEED_100M_HD:
852 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB;
854 case ETH_LINK_SPEED_1G:
856 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
858 case ETH_LINK_SPEED_2_5G:
860 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
862 case ETH_LINK_SPEED_10G:
864 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
866 case ETH_LINK_SPEED_20G:
868 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
870 case ETH_LINK_SPEED_25G:
872 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
874 case ETH_LINK_SPEED_40G:
876 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
878 case ETH_LINK_SPEED_50G:
880 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
884 "Unsupported link speed %d; default to AUTO\n",
888 return eth_link_speed;
891 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
892 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
893 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
894 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
896 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
900 if (link_speed == ETH_LINK_SPEED_AUTONEG)
903 if (link_speed & ETH_LINK_SPEED_FIXED) {
904 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
906 if (one_speed & (one_speed - 1)) {
908 "Invalid advertised speeds (%u) for port %u\n",
909 link_speed, port_id);
912 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
914 "Unsupported advertised speed (%u) for port %u\n",
915 link_speed, port_id);
919 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
921 "Unsupported advertised speeds (%u) for port %u\n",
922 link_speed, port_id);
929 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
933 if (link_speed == ETH_LINK_SPEED_AUTONEG)
934 link_speed = BNXT_SUPPORTED_SPEEDS;
936 if (link_speed & ETH_LINK_SPEED_100M)
937 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
938 if (link_speed & ETH_LINK_SPEED_100M_HD)
939 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
940 if (link_speed & ETH_LINK_SPEED_1G)
941 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
942 if (link_speed & ETH_LINK_SPEED_2_5G)
943 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
944 if (link_speed & ETH_LINK_SPEED_10G)
945 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
946 if (link_speed & ETH_LINK_SPEED_20G)
947 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
948 if (link_speed & ETH_LINK_SPEED_25G)
949 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
950 if (link_speed & ETH_LINK_SPEED_40G)
951 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
952 if (link_speed & ETH_LINK_SPEED_50G)
953 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
957 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
960 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
961 struct bnxt_link_info link_req;
964 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
965 bp->eth_dev->data->port_id);
969 memset(&link_req, 0, sizeof(link_req));
970 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
971 link_req.link_up = link_up;
974 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
976 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW;
977 link_req.auto_link_speed_mask =
978 bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
979 link_req.auto_link_speed =
980 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB;
982 link_req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
983 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE |
984 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
985 link_req.link_speed = speed;
987 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
988 link_req.auto_pause = bp->link_info.auto_pause;
989 link_req.force_pause = bp->link_info.force_pause;
991 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
994 "Set link config failed with rc %d\n", rc);