drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR,
 168                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 169                             req->req_type, req->seq_id);
 170                 return -ETIMEDOUT;
 171         }
 172         return 0;
 173 }
 174
 175 /*
 176  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 177  * spinlock, and does initial processing.
 178  *
 179  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 180  * releases the spinlock only if it returns. If the regular int return codes
 181  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 182  * directly, rather it should be copied and modified to suit the function.
 183  *
 184  * HWRM_UNLOCK() must be called after all response processing is completed.
 185  */
 186 #define HWRM_PREP(req, type, kong) do { \
 187         rte_spinlock_lock(&bp->hwrm_lock); \
 188         if (bp->hwrm_cmd_resp_addr == NULL) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return -EACCES; \
 191         } \
 192         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 193         (req)->req_type = rte_cpu_to_le_16(type); \
 194         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 195         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 196                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 197         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 198         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 199 } while (0)
 200
 201 #define HWRM_CHECK_RESULT_SILENT() do {\
 202         if (rc) { \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 rte_spinlock_unlock(&bp->hwrm_lock); \
 209                 return rc; \
 210         } \
 211 } while (0)
 212
 213 #define HWRM_CHECK_RESULT() do {\
 214         if (rc) { \
 215                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 218                         rc = -EACCES; \
 219                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 220                         rc = -ENOSPC; \
 221                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 222                         rc = -EINVAL; \
 223                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 224                         rc = -ENOTSUP; \
 225                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 226                         rc = -EAGAIN; \
 227                 else if (rc > 0) \
 228                         rc = -EIO; \
 229                 return rc; \
 230         } \
 231         if (resp->error_code) { \
 232                 rc = rte_le_to_cpu_16(resp->error_code); \
 233                 if (resp->resp_len >= 16) { \
 234                         struct hwrm_err_output *tmp_hwrm_err_op = \
 235                                                 (void *)resp; \
 236                         PMD_DRV_LOG(ERR, \
 237                                 "error %d:%d:%08x:%04x\n", \
 238                                 rc, tmp_hwrm_err_op->cmd_err, \
 239                                 rte_le_to_cpu_32(\
 240                                         tmp_hwrm_err_op->opaque_0), \
 241                                 rte_le_to_cpu_16(\
 242                                         tmp_hwrm_err_op->opaque_1)); \
 243                 } else { \
 244                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 245                 } \
 246                 rte_spinlock_unlock(&bp->hwrm_lock); \
 247                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 248                         rc = -EACCES; \
 249                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 250                         rc = -ENOSPC; \
 251                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 252                         rc = -EINVAL; \
 253                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 254                         rc = -ENOTSUP; \
 255                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 256                         rc = -EAGAIN; \
 257                 else if (rc > 0) \
 258                         rc = -EIO; \
 259                 return rc; \
 260         } \
 261 } while (0)
 262
 263 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 264
 265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 266                                 bool use_kong_mb,
 267                                 uint16_t msg_type,
 268                                 void *msg,
 269                                 uint32_t msg_len,
 270                                 void *resp_msg,
 271                                 uint32_t resp_len)
 272 {
 273         int rc = 0;
 274         bool mailbox = BNXT_USE_CHIMP_MB;
 275         struct input *req = msg;
 276         struct output *resp = bp->hwrm_cmd_resp_addr;
 277
 278         if (use_kong_mb)
 279                 mailbox = BNXT_USE_KONG(bp);
 280
 281         HWRM_PREP(req, msg_type, mailbox);
 282
 283         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 284
 285         HWRM_CHECK_RESULT();
 286
 287         if (resp_msg)
 288                 memcpy(resp_msg, resp, resp_len);
 289
 290         HWRM_UNLOCK();
 291
 292         return rc;
 293 }
 294
 295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 296                                   bool use_kong_mb,
 297                                   uint16_t tf_type,
 298                                   uint16_t tf_subtype,
 299                                   uint32_t *tf_response_code,
 300                                   void *msg,
 301                                   uint32_t msg_len,
 302                                   void *response,
 303                                   uint32_t response_len)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 307         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 308         bool mailbox = BNXT_USE_CHIMP_MB;
 309
 310         if (msg_len > sizeof(req.tf_req))
 311                 return -ENOMEM;
 312
 313         if (use_kong_mb)
 314                 mailbox = BNXT_USE_KONG(bp);
 315
 316         HWRM_PREP(&req, HWRM_TF, mailbox);
 317         /* Build request using the user supplied request payload.
 318          * TLV request size is checked at build time against HWRM
 319          * request max size, thus no checking required.
 320          */
 321         req.tf_type = tf_type;
 322         req.tf_subtype = tf_subtype;
 323         memcpy(req.tf_req, msg, msg_len);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 326         HWRM_CHECK_RESULT();
 327
 328         /* Copy the resp to user provided response buffer */
 329         if (response != NULL)
 330                 /* Post process response data. We need to copy only
 331                  * the 'payload' as the HWRM data structure really is
 332                  * HWRM header + msg header + payload and the TFLIB
 333                  * only provided a payload place holder.
 334                  */
 335                 if (response_len != 0) {
 336                         memcpy(response,
 337                                resp->tf_resp,
 338                                response_len);
 339                 }
 340
 341         /* Extract the internal tflib response code */
 342         *tf_response_code = resp->tf_resp_code;
 343         HWRM_UNLOCK();
 344
 345         return rc;
 346 }
 347
 348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 349 {
 350         int rc = 0;
 351         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 352         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 353
 354         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 355         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 356         req.mask = 0;
 357
 358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 359
 360         HWRM_CHECK_RESULT();
 361         HWRM_UNLOCK();
 362
 363         return rc;
 364 }
 365
 366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 367                                  struct bnxt_vnic_info *vnic,
 368                                  uint16_t vlan_count,
 369                                  struct bnxt_vlan_table_entry *vlan_table)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 374         uint32_t mask = 0;
 375
 376         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 377                 return rc;
 378
 379         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 380         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 384         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 385                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 386
 387         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 389
 390         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 391                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 392         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 393                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 394                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 395                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 396         }
 397         if (vlan_table) {
 398                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 399                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 400                 req.vlan_tag_tbl_addr =
 401                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 402                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 403         }
 404         req.mask = rte_cpu_to_le_32(mask);
 405
 406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 407
 408         HWRM_CHECK_RESULT();
 409         HWRM_UNLOCK();
 410
 411         return rc;
 412 }
 413
 414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 415                         uint16_t vlan_count,
 416                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 420         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 421                                                 bp->hwrm_cmd_resp_addr;
 422
 423         /*
 424          * Older HWRM versions did not support this command, and the set_rx_mask
 425          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 426          * removed from set_rx_mask call, and this command was added.
 427          *
 428          * This command is also present from 1.7.8.11 and higher,
 429          * as well as 1.7.8.0
 430          */
 431         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 432                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 433                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 434                                         (11)))
 435                                 return 0;
 436                 }
 437         }
 438         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 439         req.fid = rte_cpu_to_le_16(fid);
 440
 441         req.vlan_tag_mask_tbl_addr =
 442                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 443         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 444
 445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 446
 447         HWRM_CHECK_RESULT();
 448         HWRM_UNLOCK();
 449
 450         return rc;
 451 }
 452
 453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 454                              struct bnxt_filter_info *filter)
 455 {
 456         int rc = 0;
 457         struct bnxt_filter_info *l2_filter = filter;
 458         struct bnxt_vnic_info *vnic = NULL;
 459         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 460         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 461
 462         if (filter->fw_l2_filter_id == UINT64_MAX)
 463                 return 0;
 464
 465         if (filter->matching_l2_fltr_ptr)
 466                 l2_filter = filter->matching_l2_fltr_ptr;
 467
 468         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 469                     filter, l2_filter, l2_filter->l2_ref_cnt);
 470
 471         if (l2_filter->l2_ref_cnt == 0)
 472                 return 0;
 473
 474         if (l2_filter->l2_ref_cnt > 0)
 475                 l2_filter->l2_ref_cnt--;
 476
 477         if (l2_filter->l2_ref_cnt > 0)
 478                 return 0;
 479
 480         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 481
 482         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 483
 484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 485
 486         HWRM_CHECK_RESULT();
 487         HWRM_UNLOCK();
 488
 489         filter->fw_l2_filter_id = UINT64_MAX;
 490         if (l2_filter->l2_ref_cnt == 0) {
 491                 vnic = l2_filter->vnic;
 492                 if (vnic) {
 493                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 494                                       bnxt_filter_info, next);
 495                         bnxt_free_filter(bp, l2_filter);
 496                 }
 497         }
 498
 499         return 0;
 500 }
 501
 502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 503                          uint16_t dst_id,
 504                          struct bnxt_filter_info *filter)
 505 {
 506         int rc = 0;
 507         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 508         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 509         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 510         const struct rte_eth_vmdq_rx_conf *conf =
 511                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 512         uint32_t enables = 0;
 513         uint16_t j = dst_id - 1;
 514
 515         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 516         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 517             conf->pool_map[j].pools & (1UL << j)) {
 518                 PMD_DRV_LOG(DEBUG,
 519                         "Add vlan %u to vmdq pool %u\n",
 520                         conf->pool_map[j].vlan_id, j);
 521
 522                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 523                 filter->enables |=
 524                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 525                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 526         }
 527
 528         if (filter->fw_l2_filter_id != UINT64_MAX)
 529                 bnxt_hwrm_clear_l2_filter(bp, filter);
 530
 531         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 532
 533         req.flags = rte_cpu_to_le_32(filter->flags);
 534
 535         enables = filter->enables |
 536               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 537         req.dst_id = rte_cpu_to_le_16(dst_id);
 538
 539         if (enables &
 540             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 541                 memcpy(req.l2_addr, filter->l2_addr,
 542                        RTE_ETHER_ADDR_LEN);
 543         if (enables &
 544             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 545                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 546                        RTE_ETHER_ADDR_LEN);
 547         if (enables &
 548             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 549                 req.l2_ovlan = filter->l2_ovlan;
 550         if (enables &
 551             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 552                 req.l2_ivlan = filter->l2_ivlan;
 553         if (enables &
 554             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 555                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 556         if (enables &
 557             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 558                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 559         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 560                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 561         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 562                 req.src_type = filter->src_type;
 563         if (filter->pri_hint) {
 564                 req.pri_hint = filter->pri_hint;
 565                 req.l2_filter_id_hint =
 566                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 567         }
 568
 569         req.enables = rte_cpu_to_le_32(enables);
 570
 571         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 572
 573         HWRM_CHECK_RESULT();
 574
 575         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 576         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 577         HWRM_UNLOCK();
 578
 579         filter->l2_ref_cnt++;
 580
 581         return rc;
 582 }
 583
 584 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 585 {
 586         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 587         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 588         uint32_t flags = 0;
 589         int rc;
 590
 591         if (!ptp)
 592                 return 0;
 593
 594         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 595
 596         if (ptp->rx_filter)
 597                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 598         else
 599                 flags |=
 600                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 601         if (ptp->tx_tstamp_en)
 602                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 603         else
 604                 flags |=
 605                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 606         req.flags = rte_cpu_to_le_32(flags);
 607         req.enables = rte_cpu_to_le_32
 608                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 609         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 610
 611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 612         HWRM_UNLOCK();
 613
 614         return rc;
 615 }
 616
 617 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 618 {
 619         int rc = 0;
 620         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 621         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 622         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 623
 624         if (ptp)
 625                 return 0;
 626
 627         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 628
 629         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 630
 631         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 632
 633         HWRM_CHECK_RESULT();
 634
 635         if (!BNXT_CHIP_THOR(bp) &&
 636             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 637                 return 0;
 638
 639         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 640                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 641
 642         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 643         if (!ptp)
 644                 return -ENOMEM;
 645
 646         if (!BNXT_CHIP_THOR(bp)) {
 647                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 648                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 649                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 650                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 651                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 652                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 653                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 654                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 655                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 656                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 657                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 658                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 659                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 660                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 661                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 662                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 663                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 664                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 665         }
 666
 667         ptp->bp = bp;
 668         bp->ptp_cfg = ptp;
 669
 670         return 0;
 671 }
 672
 673 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
 674 {
 675         int i;
 676
 677         for (i = 0; i < bp->pf->max_vfs; i++) {
 678                 rte_free(bp->pf->vf_info[i].vlan_table);
 679                 bp->pf->vf_info[i].vlan_table = NULL;
 680                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 681                 bp->pf->vf_info[i].vlan_as_table = NULL;
 682         }
 683         rte_free(bp->pf->vf_info);
 684         bp->pf->vf_info = NULL;
 685 }
 686
 687 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 688 {
 689         int rc = 0;
 690         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 691         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 692         uint16_t new_max_vfs;
 693         uint32_t flags;
 694         int i;
 695
 696         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 697
 698         req.fid = rte_cpu_to_le_16(0xffff);
 699
 700         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 701
 702         HWRM_CHECK_RESULT();
 703
 704         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 705         flags = rte_le_to_cpu_32(resp->flags);
 706         if (BNXT_PF(bp)) {
 707                 bp->pf->port_id = resp->port_id;
 708                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 709                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 710                 new_max_vfs = bp->pdev->max_vfs;
 711                 if (new_max_vfs != bp->pf->max_vfs) {
 712                         if (bp->pf->vf_info)
 713                                 bnxt_hwrm_free_vf_info(bp);
 714                         bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
 715                             sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
 716                         if (bp->pf->vf_info == NULL) {
 717                                 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
 718                                 return -ENOMEM;
 719                         }
 720                         bp->pf->max_vfs = new_max_vfs;
 721                         for (i = 0; i < new_max_vfs; i++) {
 722                                 bp->pf->vf_info[i].fid =
 723                                         bp->pf->first_vf_id + i;
 724                                 bp->pf->vf_info[i].vlan_table =
 725                                         rte_zmalloc("VF VLAN table",
 726                                                     getpagesize(),
 727                                                     getpagesize());
 728                                 if (bp->pf->vf_info[i].vlan_table == NULL)
 729                                         PMD_DRV_LOG(ERR,
 730                                         "Fail to alloc VLAN table for VF %d\n",
 731                                         i);
 732                                 else
 733                                         rte_mem_lock_page(
 734                                                 bp->pf->vf_info[i].vlan_table);
 735                                 bp->pf->vf_info[i].vlan_as_table =
 736                                         rte_zmalloc("VF VLAN AS table",
 737                                                     getpagesize(),
 738                                                     getpagesize());
 739                                 if (bp->pf->vf_info[i].vlan_as_table == NULL)
 740                                         PMD_DRV_LOG(ERR,
 741                                         "Alloc VLAN AS table for VF %d fail\n",
 742                                         i);
 743                                 else
 744                                         rte_mem_lock_page(
 745                                               bp->pf->vf_info[i].vlan_as_table);
 746                                 STAILQ_INIT(&bp->pf->vf_info[i].filter);
 747                         }
 748                 }
 749         }
 750
 751         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 752         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 753                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 754                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 755         } else {
 756                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 757         }
 758         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 759         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 760         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 761         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 762         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 763         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 764         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 765         if (!BNXT_CHIP_THOR(bp))
 766                 bp->max_l2_ctx += bp->max_rx_em_flows;
 767         /* TODO: For now, do not support VMDq/RFS on VFs. */
 768         if (BNXT_PF(bp)) {
 769                 if (bp->pf->max_vfs)
 770                         bp->max_vnics = 1;
 771                 else
 772                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 773         } else {
 774                 bp->max_vnics = 1;
 775         }
 776         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 777                     bp->max_l2_ctx, bp->max_vnics);
 778         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 779         if (BNXT_PF(bp)) {
 780                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 781                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 782                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 783                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 784                         HWRM_UNLOCK();
 785                         bnxt_hwrm_ptp_qcfg(bp);
 786                 }
 787         }
 788
 789         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 790                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 791
 792         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 793                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 794                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 795         }
 796
 797         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 798                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 799
 800         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 801                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 802
 803         HWRM_UNLOCK();
 804
 805         return rc;
 806 }
 807
 808 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 809 {
 810         int rc;
 811
 812         rc = __bnxt_hwrm_func_qcaps(bp);
 813         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 814                 rc = bnxt_alloc_ctx_mem(bp);
 815                 if (rc)
 816                         return rc;
 817
 818                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 819                 if (!rc)
 820                         bp->flags |= BNXT_FLAG_NEW_RM;
 821         }
 822
 823         /* On older FW,
 824          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 825          * But the error can be ignored. Return success.
 826          */
 827
 828         return 0;
 829 }
 830
 831 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 832 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 833 {
 834         int rc = 0;
 835         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 836         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 837
 838         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 839
 840         req.target_id = rte_cpu_to_le_16(0xffff);
 841
 842         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 843
 844         HWRM_CHECK_RESULT();
 845
 846         if (rte_le_to_cpu_32(resp->flags) &
 847             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 848                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 849                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 850         }
 851
 852         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 853
 854         HWRM_UNLOCK();
 855
 856         return rc;
 857 }
 858
 859 int bnxt_hwrm_func_reset(struct bnxt *bp)
 860 {
 861         int rc = 0;
 862         struct hwrm_func_reset_input req = {.req_type = 0 };
 863         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 864
 865         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 866
 867         req.enables = rte_cpu_to_le_32(0);
 868
 869         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 870
 871         HWRM_CHECK_RESULT();
 872         HWRM_UNLOCK();
 873
 874         return rc;
 875 }
 876
 877 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 878 {
 879         int rc;
 880         uint32_t flags = 0;
 881         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 882         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 883
 884         if (bp->flags & BNXT_FLAG_REGISTERED)
 885                 return 0;
 886
 887         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 888                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 889         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 890                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 891
 892         /* PFs and trusted VFs should indicate the support of the
 893          * Master capability on non Stingray platform
 894          */
 895         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 896                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 897
 898         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 899         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 900                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 901         req.ver_maj = RTE_VER_YEAR;
 902         req.ver_min = RTE_VER_MONTH;
 903         req.ver_upd = RTE_VER_MINOR;
 904
 905         if (BNXT_PF(bp)) {
 906                 req.enables |= rte_cpu_to_le_32(
 907                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 908                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
 909                        RTE_MIN(sizeof(req.vf_req_fwd),
 910                                sizeof(bp->pf->vf_req_fwd)));
 911
 912                 /*
 913                  * PF can sniff HWRM API issued by VF. This can be set up by
 914                  * linux driver and inherited by the DPDK PF driver. Clear
 915                  * this HWRM sniffer list in FW because DPDK PF driver does
 916                  * not support this.
 917                  */
 918                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 919         }
 920
 921         req.flags = rte_cpu_to_le_32(flags);
 922
 923         req.async_event_fwd[0] |=
 924                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 925                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 926                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 927                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 928                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 929         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 930                 req.async_event_fwd[0] |=
 931                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 932         req.async_event_fwd[1] |=
 933                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 934                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 935         if (BNXT_PF(bp))
 936                 req.async_event_fwd[1] |=
 937                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 938
 939         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 940
 941         HWRM_CHECK_RESULT();
 942
 943         flags = rte_le_to_cpu_32(resp->flags);
 944         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 945                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 946
 947         HWRM_UNLOCK();
 948
 949         bp->flags |= BNXT_FLAG_REGISTERED;
 950
 951         return rc;
 952 }
 953
 954 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 955 {
 956         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 957                 return 0;
 958
 959         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 960 }
 961
 962 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 963 {
 964         int rc;
 965         uint32_t flags = 0;
 966         uint32_t enables;
 967         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 968         struct hwrm_func_vf_cfg_input req = {0};
 969
 970         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 971
 972         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 973                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 974                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 975                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 976                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 977
 978         if (BNXT_HAS_RING_GRPS(bp)) {
 979                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 980                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 981         }
 982
 983         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 984         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 985                                             AGG_RING_MULTIPLIER);
 986         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 987         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 988                                               bp->tx_nr_rings +
 989                                               BNXT_NUM_ASYNC_CPR(bp));
 990         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 991         if (bp->vf_resv_strategy ==
 992             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 993                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 994                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 995                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 996                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 997                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 998                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 999         } else if (bp->vf_resv_strategy ==
1000                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1001                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1002                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1003         }
1004
1005         if (test)
1006                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1007                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1008                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1009                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1010                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1011                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1012
1013         if (test && BNXT_HAS_RING_GRPS(bp))
1014                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1015
1016         req.flags = rte_cpu_to_le_32(flags);
1017         req.enables |= rte_cpu_to_le_32(enables);
1018
1019         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1020
1021         if (test)
1022                 HWRM_CHECK_RESULT_SILENT();
1023         else
1024                 HWRM_CHECK_RESULT();
1025
1026         HWRM_UNLOCK();
1027         return rc;
1028 }
1029
1030 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1031 {
1032         int rc;
1033         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1034         struct hwrm_func_resource_qcaps_input req = {0};
1035
1036         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1037         req.fid = rte_cpu_to_le_16(0xffff);
1038
1039         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1040
1041         HWRM_CHECK_RESULT_SILENT();
1042
1043         if (BNXT_VF(bp)) {
1044                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1045                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1046                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1047                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1048                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1049                 /* func_resource_qcaps does not return max_rx_em_flows.
1050                  * So use the value provided by func_qcaps.
1051                  */
1052                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1053                 if (!BNXT_CHIP_THOR(bp))
1054                         bp->max_l2_ctx += bp->max_rx_em_flows;
1055                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1056                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1057         }
1058         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1059         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1060         if (bp->vf_resv_strategy >
1061             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1062                 bp->vf_resv_strategy =
1063                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1064
1065         HWRM_UNLOCK();
1066         return rc;
1067 }
1068
1069 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1070 {
1071         int rc = 0;
1072         struct hwrm_ver_get_input req = {.req_type = 0 };
1073         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1074         uint32_t fw_version;
1075         uint16_t max_resp_len;
1076         char type[RTE_MEMZONE_NAMESIZE];
1077         uint32_t dev_caps_cfg;
1078
1079         bp->max_req_len = HWRM_MAX_REQ_LEN;
1080         bp->hwrm_cmd_timeout = timeout;
1081         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1082
1083         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1084         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1085         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1086
1087         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1088
1089         if (bp->flags & BNXT_FLAG_FW_RESET)
1090                 HWRM_CHECK_RESULT_SILENT();
1091         else
1092                 HWRM_CHECK_RESULT();
1093
1094         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1095                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1096                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1097                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1098         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1099                      (resp->hwrm_fw_min_8b << 16) |
1100                      (resp->hwrm_fw_bld_8b << 8) |
1101                      resp->hwrm_fw_rsvd_8b;
1102         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1103                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1104
1105         fw_version = resp->hwrm_intf_maj_8b << 16;
1106         fw_version |= resp->hwrm_intf_min_8b << 8;
1107         fw_version |= resp->hwrm_intf_upd_8b;
1108         bp->hwrm_spec_code = fw_version;
1109
1110         /* def_req_timeout value is in milliseconds */
1111         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1112         /* convert timeout to usec */
1113         bp->hwrm_cmd_timeout *= 1000;
1114         if (!bp->hwrm_cmd_timeout)
1115                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1116
1117         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1118                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1119                 rc = -EINVAL;
1120                 goto error;
1121         }
1122
1123         if (bp->max_req_len > resp->max_req_win_len) {
1124                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1125                 rc = -EINVAL;
1126         }
1127         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1128         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1129         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1130                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1131
1132         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1133         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1134
1135         if (bp->max_resp_len != max_resp_len) {
1136                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1137                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1138                         bp->pdev->addr.devid, bp->pdev->addr.function);
1139
1140                 rte_free(bp->hwrm_cmd_resp_addr);
1141
1142                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1143                 if (bp->hwrm_cmd_resp_addr == NULL) {
1144                         rc = -ENOMEM;
1145                         goto error;
1146                 }
1147                 bp->hwrm_cmd_resp_dma_addr =
1148                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1149                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1150                         PMD_DRV_LOG(ERR,
1151                         "Unable to map response buffer to physical memory.\n");
1152                         rc = -ENOMEM;
1153                         goto error;
1154                 }
1155                 bp->max_resp_len = max_resp_len;
1156         }
1157
1158         if ((dev_caps_cfg &
1159                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1160             (dev_caps_cfg &
1161              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1162                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1163                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1164         }
1165
1166         if (((dev_caps_cfg &
1167               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1168              (dev_caps_cfg &
1169               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1170             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1171                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1172                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1173                         bp->pdev->addr.devid, bp->pdev->addr.function);
1174
1175                 rte_free(bp->hwrm_short_cmd_req_addr);
1176
1177                 bp->hwrm_short_cmd_req_addr =
1178                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1179                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1180                         rc = -ENOMEM;
1181                         goto error;
1182                 }
1183                 bp->hwrm_short_cmd_req_dma_addr =
1184                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1185                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1186                         rte_free(bp->hwrm_short_cmd_req_addr);
1187                         PMD_DRV_LOG(ERR,
1188                                 "Unable to map buffer to physical memory.\n");
1189                         rc = -ENOMEM;
1190                         goto error;
1191                 }
1192         }
1193         if (dev_caps_cfg &
1194             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1195                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1196                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1197         }
1198         if (dev_caps_cfg &
1199             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1200                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1201         if (dev_caps_cfg &
1202             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1203                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1204                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1205         }
1206
1207         if (dev_caps_cfg &
1208             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1209                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1210                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1211         }
1212
1213
1214 error:
1215         HWRM_UNLOCK();
1216         return rc;
1217 }
1218
1219 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1220 {
1221         int rc;
1222         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1223         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1224
1225         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1226                 return 0;
1227
1228         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1229         req.flags = flags;
1230
1231         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1232
1233         HWRM_CHECK_RESULT();
1234         HWRM_UNLOCK();
1235
1236         return rc;
1237 }
1238
1239 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1240 {
1241         int rc = 0;
1242         struct hwrm_port_phy_cfg_input req = {0};
1243         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1244         uint32_t enables = 0;
1245
1246         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1247
1248         if (conf->link_up) {
1249                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1250                 if (bp->link_info->auto_mode && conf->link_speed) {
1251                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1252                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1253                 }
1254
1255                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1256                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1257                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1258                 /*
1259                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1260                  * any auto mode, even "none".
1261                  */
1262                 if (!conf->link_speed) {
1263                         /* No speeds specified. Enable AutoNeg - all speeds */
1264                         req.auto_mode =
1265                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1266                 }
1267                 /* AutoNeg - Advertise speeds specified. */
1268                 if (conf->auto_link_speed_mask &&
1269                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1270                         req.auto_mode =
1271                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1272                         req.auto_link_speed_mask =
1273                                 conf->auto_link_speed_mask;
1274                         enables |=
1275                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1276                 }
1277
1278                 req.auto_duplex = conf->duplex;
1279                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1280                 req.auto_pause = conf->auto_pause;
1281                 req.force_pause = conf->force_pause;
1282                 /* Set force_pause if there is no auto or if there is a force */
1283                 if (req.auto_pause && !req.force_pause)
1284                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1285                 else
1286                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1287
1288                 req.enables = rte_cpu_to_le_32(enables);
1289         } else {
1290                 req.flags =
1291                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1292                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1293         }
1294
1295         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1296
1297         HWRM_CHECK_RESULT();
1298         HWRM_UNLOCK();
1299
1300         return rc;
1301 }
1302
1303 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1304                                    struct bnxt_link_info *link_info)
1305 {
1306         int rc = 0;
1307         struct hwrm_port_phy_qcfg_input req = {0};
1308         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1309
1310         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1311
1312         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1313
1314         HWRM_CHECK_RESULT();
1315
1316         link_info->phy_link_status = resp->link;
1317         link_info->link_up =
1318                 (link_info->phy_link_status ==
1319                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1320         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1321         link_info->duplex = resp->duplex_cfg;
1322         link_info->pause = resp->pause;
1323         link_info->auto_pause = resp->auto_pause;
1324         link_info->force_pause = resp->force_pause;
1325         link_info->auto_mode = resp->auto_mode;
1326         link_info->phy_type = resp->phy_type;
1327         link_info->media_type = resp->media_type;
1328
1329         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1330         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1331         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1332         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1333         link_info->phy_ver[0] = resp->phy_maj;
1334         link_info->phy_ver[1] = resp->phy_min;
1335         link_info->phy_ver[2] = resp->phy_bld;
1336
1337         HWRM_UNLOCK();
1338
1339         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1340         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1341         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1342         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1343         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1344                     link_info->auto_link_speed_mask);
1345         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1346                     link_info->force_link_speed);
1347
1348         return rc;
1349 }
1350
1351 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1352 {
1353         int rc = 0;
1354         struct hwrm_port_phy_qcaps_input req = {0};
1355         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1356
1357         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1358                 return 0;
1359
1360         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1361
1362         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1363
1364         HWRM_CHECK_RESULT();
1365
1366         bp->port_cnt = resp->port_cnt;
1367
1368         HWRM_UNLOCK();
1369
1370         return 0;
1371 }
1372
1373 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1374 {
1375         int i = 0;
1376
1377         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1378                 if (bp->tx_cos_queue[i].profile ==
1379                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1380                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1381                         return true;
1382                 }
1383         }
1384         return false;
1385 }
1386
1387 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1388 {
1389         int i = 0;
1390
1391         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1392                 if (bp->tx_cos_queue[i].profile !=
1393                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1394                     bp->tx_cos_queue[i].id !=
1395                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1396                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1397                         break;
1398                 }
1399         }
1400 }
1401
1402 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1403 {
1404         int rc = 0;
1405         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1406         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1407         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1408         int i;
1409
1410 get_rx_info:
1411         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1412
1413         req.flags = rte_cpu_to_le_32(dir);
1414         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1415         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1416             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1417                 req.drv_qmap_cap =
1418                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1419         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1420
1421         HWRM_CHECK_RESULT();
1422
1423         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1424                 GET_TX_QUEUE_INFO(0);
1425                 GET_TX_QUEUE_INFO(1);
1426                 GET_TX_QUEUE_INFO(2);
1427                 GET_TX_QUEUE_INFO(3);
1428                 GET_TX_QUEUE_INFO(4);
1429                 GET_TX_QUEUE_INFO(5);
1430                 GET_TX_QUEUE_INFO(6);
1431                 GET_TX_QUEUE_INFO(7);
1432         } else  {
1433                 GET_RX_QUEUE_INFO(0);
1434                 GET_RX_QUEUE_INFO(1);
1435                 GET_RX_QUEUE_INFO(2);
1436                 GET_RX_QUEUE_INFO(3);
1437                 GET_RX_QUEUE_INFO(4);
1438                 GET_RX_QUEUE_INFO(5);
1439                 GET_RX_QUEUE_INFO(6);
1440                 GET_RX_QUEUE_INFO(7);
1441         }
1442
1443         HWRM_UNLOCK();
1444
1445         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1446                 goto done;
1447
1448         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1449                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1450         } else {
1451                 int j;
1452
1453                 /* iterate and find the COSq profile to use for Tx */
1454                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1455                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1456                                 if (bp->tx_cos_queue[i].id != 0xff)
1457                                         bp->tx_cosq_id[j++] =
1458                                                 bp->tx_cos_queue[i].id;
1459                         }
1460                 } else {
1461                         /* When CoS classification is disabled, for normal NIC
1462                          * operations, ideally we should look to use LOSSY.
1463                          * If not found, fallback to the first valid profile
1464                          */
1465                         if (!bnxt_find_lossy_profile(bp))
1466                                 bnxt_find_first_valid_profile(bp);
1467
1468                 }
1469         }
1470
1471         bp->max_tc = resp->max_configurable_queues;
1472         bp->max_lltc = resp->max_configurable_lossless_queues;
1473         if (bp->max_tc > BNXT_MAX_QUEUE)
1474                 bp->max_tc = BNXT_MAX_QUEUE;
1475         bp->max_q = bp->max_tc;
1476
1477         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1478                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1479                 goto get_rx_info;
1480         }
1481
1482 done:
1483         return rc;
1484 }
1485
1486 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1487                          struct bnxt_ring *ring,
1488                          uint32_t ring_type, uint32_t map_index,
1489                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1490                          uint16_t tx_cosq_id)
1491 {
1492         int rc = 0;
1493         uint32_t enables = 0;
1494         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1495         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1496         struct rte_mempool *mb_pool;
1497         uint16_t rx_buf_size;
1498
1499         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1500
1501         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1502         req.fbo = rte_cpu_to_le_32(0);
1503         /* Association of ring index with doorbell index */
1504         req.logical_id = rte_cpu_to_le_16(map_index);
1505         req.length = rte_cpu_to_le_32(ring->ring_size);
1506
1507         switch (ring_type) {
1508         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1509                 req.ring_type = ring_type;
1510                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1511                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1512                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1513                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1514                         enables |=
1515                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1516                 break;
1517         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1518                 req.ring_type = ring_type;
1519                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1520                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1521                 if (BNXT_CHIP_THOR(bp)) {
1522                         mb_pool = bp->rx_queues[0]->mb_pool;
1523                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1524                                       RTE_PKTMBUF_HEADROOM;
1525                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1526                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1527                         enables |=
1528                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1529                 }
1530                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1531                         enables |=
1532                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1533                 break;
1534         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1535                 req.ring_type = ring_type;
1536                 if (BNXT_HAS_NQ(bp)) {
1537                         /* Association of cp ring with nq */
1538                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1539                         enables |=
1540                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1541                 }
1542                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1543                 break;
1544         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1545                 req.ring_type = ring_type;
1546                 req.page_size = BNXT_PAGE_SHFT;
1547                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1548                 break;
1549         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1550                 req.ring_type = ring_type;
1551                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1552
1553                 mb_pool = bp->rx_queues[0]->mb_pool;
1554                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1555                               RTE_PKTMBUF_HEADROOM;
1556                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1557                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1558
1559                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1560                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1561                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1562                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1563                 break;
1564         default:
1565                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1566                         ring_type);
1567                 HWRM_UNLOCK();
1568                 return -EINVAL;
1569         }
1570         req.enables = rte_cpu_to_le_32(enables);
1571
1572         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1573
1574         if (rc || resp->error_code) {
1575                 if (rc == 0 && resp->error_code)
1576                         rc = rte_le_to_cpu_16(resp->error_code);
1577                 switch (ring_type) {
1578                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1579                         PMD_DRV_LOG(ERR,
1580                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1581                         HWRM_UNLOCK();
1582                         return rc;
1583                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1584                         PMD_DRV_LOG(ERR,
1585                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1586                         HWRM_UNLOCK();
1587                         return rc;
1588                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1589                         PMD_DRV_LOG(ERR,
1590                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1591                                     rc);
1592                         HWRM_UNLOCK();
1593                         return rc;
1594                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1595                         PMD_DRV_LOG(ERR,
1596                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1597                         HWRM_UNLOCK();
1598                         return rc;
1599                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1600                         PMD_DRV_LOG(ERR,
1601                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1602                         HWRM_UNLOCK();
1603                         return rc;
1604                 default:
1605                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1606                         HWRM_UNLOCK();
1607                         return rc;
1608                 }
1609         }
1610
1611         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1612         HWRM_UNLOCK();
1613         return rc;
1614 }
1615
1616 int bnxt_hwrm_ring_free(struct bnxt *bp,
1617                         struct bnxt_ring *ring, uint32_t ring_type)
1618 {
1619         int rc;
1620         struct hwrm_ring_free_input req = {.req_type = 0 };
1621         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1622
1623         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1624
1625         req.ring_type = ring_type;
1626         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1627
1628         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1629
1630         if (rc || resp->error_code) {
1631                 if (rc == 0 && resp->error_code)
1632                         rc = rte_le_to_cpu_16(resp->error_code);
1633                 HWRM_UNLOCK();
1634
1635                 switch (ring_type) {
1636                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1637                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1638                                 rc);
1639                         return rc;
1640                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1641                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1642                                 rc);
1643                         return rc;
1644                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1645                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1646                                 rc);
1647                         return rc;
1648                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1649                         PMD_DRV_LOG(ERR,
1650                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1651                         return rc;
1652                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1653                         PMD_DRV_LOG(ERR,
1654                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1655                         return rc;
1656                 default:
1657                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1658                         return rc;
1659                 }
1660         }
1661         HWRM_UNLOCK();
1662         return 0;
1663 }
1664
1665 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1666 {
1667         int rc = 0;
1668         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1669         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1670
1671         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1672
1673         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1674         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1675         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1676         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1677
1678         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1679
1680         HWRM_CHECK_RESULT();
1681
1682         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1683
1684         HWRM_UNLOCK();
1685
1686         return rc;
1687 }
1688
1689 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1690 {
1691         int rc;
1692         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1693         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1694
1695         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1696
1697         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1698
1699         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1700
1701         HWRM_CHECK_RESULT();
1702         HWRM_UNLOCK();
1703
1704         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1705         return rc;
1706 }
1707
1708 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1709 {
1710         int rc = 0;
1711         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1712         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1713
1714         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1715                 return rc;
1716
1717         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1718
1719         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1720
1721         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1722
1723         HWRM_CHECK_RESULT();
1724         HWRM_UNLOCK();
1725
1726         return rc;
1727 }
1728
1729 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1730                                 unsigned int idx __rte_unused)
1731 {
1732         int rc;
1733         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1734         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1735
1736         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1737
1738         req.update_period_ms = rte_cpu_to_le_32(0);
1739
1740         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1741
1742         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1743
1744         HWRM_CHECK_RESULT();
1745
1746         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1747
1748         HWRM_UNLOCK();
1749
1750         return rc;
1751 }
1752
1753 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1754                                 unsigned int idx __rte_unused)
1755 {
1756         int rc;
1757         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1758         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1759
1760         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1761
1762         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1763
1764         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1765
1766         HWRM_CHECK_RESULT();
1767         HWRM_UNLOCK();
1768
1769         return rc;
1770 }
1771
1772 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1773 {
1774         int rc = 0, i, j;
1775         struct hwrm_vnic_alloc_input req = { 0 };
1776         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1777
1778         if (!BNXT_HAS_RING_GRPS(bp))
1779                 goto skip_ring_grps;
1780
1781         /* map ring groups to this vnic */
1782         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1783                 vnic->start_grp_id, vnic->end_grp_id);
1784         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1785                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1786
1787         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1788         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1789         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1790         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1791
1792 skip_ring_grps:
1793         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1794         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1795
1796         if (vnic->func_default)
1797                 req.flags =
1798                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1799         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1800
1801         HWRM_CHECK_RESULT();
1802
1803         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1804         HWRM_UNLOCK();
1805         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1806         return rc;
1807 }
1808
1809 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1810                                         struct bnxt_vnic_info *vnic,
1811                                         struct bnxt_plcmodes_cfg *pmode)
1812 {
1813         int rc = 0;
1814         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1815         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1816
1817         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1818
1819         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1820
1821         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1822
1823         HWRM_CHECK_RESULT();
1824
1825         pmode->flags = rte_le_to_cpu_32(resp->flags);
1826         /* dflt_vnic bit doesn't exist in the _cfg command */
1827         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1828         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1829         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1830         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1831
1832         HWRM_UNLOCK();
1833
1834         return rc;
1835 }
1836
1837 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1838                                        struct bnxt_vnic_info *vnic,
1839                                        struct bnxt_plcmodes_cfg *pmode)
1840 {
1841         int rc = 0;
1842         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1843         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1844
1845         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1846                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1847                 return rc;
1848         }
1849
1850         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1851
1852         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1853         req.flags = rte_cpu_to_le_32(pmode->flags);
1854         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1855         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1856         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1857         req.enables = rte_cpu_to_le_32(
1858             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1859             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1860             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1861         );
1862
1863         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1864
1865         HWRM_CHECK_RESULT();
1866         HWRM_UNLOCK();
1867
1868         return rc;
1869 }
1870
1871 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1872 {
1873         int rc = 0;
1874         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1875         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1876         struct bnxt_plcmodes_cfg pmodes = { 0 };
1877         uint32_t ctx_enable_flag = 0;
1878         uint32_t enables = 0;
1879
1880         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1881                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1882                 return rc;
1883         }
1884
1885         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1886         if (rc)
1887                 return rc;
1888
1889         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1890
1891         if (BNXT_CHIP_THOR(bp)) {
1892                 int dflt_rxq = vnic->start_grp_id;
1893                 struct bnxt_rx_ring_info *rxr;
1894                 struct bnxt_cp_ring_info *cpr;
1895                 struct bnxt_rx_queue *rxq;
1896                 int i;
1897
1898                 /*
1899                  * The first active receive ring is used as the VNIC
1900                  * default receive ring. If there are no active receive
1901                  * rings (all corresponding receive queues are stopped),
1902                  * the first receive ring is used.
1903                  */
1904                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1905                         rxq = bp->eth_dev->data->rx_queues[i];
1906                         if (rxq->rx_started) {
1907                                 dflt_rxq = i;
1908                                 break;
1909                         }
1910                 }
1911
1912                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1913                 rxr = rxq->rx_ring;
1914                 cpr = rxq->cp_ring;
1915
1916                 req.default_rx_ring_id =
1917                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1918                 req.default_cmpl_ring_id =
1919                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1920                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1921                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1922                 goto config_mru;
1923         }
1924
1925         /* Only RSS support for now TBD: COS & LB */
1926         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1927         if (vnic->lb_rule != 0xffff)
1928                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1929         if (vnic->cos_rule != 0xffff)
1930                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1931         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1932                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1933                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1934         }
1935         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1936                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1937                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1938         }
1939
1940         enables |= ctx_enable_flag;
1941         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1942         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1943         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1944         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1945
1946 config_mru:
1947         req.enables = rte_cpu_to_le_32(enables);
1948         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1949         req.mru = rte_cpu_to_le_16(vnic->mru);
1950         /* Configure default VNIC only once. */
1951         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1952                 req.flags |=
1953                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1954                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1955         }
1956         if (vnic->vlan_strip)
1957                 req.flags |=
1958                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1959         if (vnic->bd_stall)
1960                 req.flags |=
1961                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1962         if (vnic->roce_dual)
1963                 req.flags |= rte_cpu_to_le_32(
1964                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1965         if (vnic->roce_only)
1966                 req.flags |= rte_cpu_to_le_32(
1967                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1968         if (vnic->rss_dflt_cr)
1969                 req.flags |= rte_cpu_to_le_32(
1970                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1971
1972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1973
1974         HWRM_CHECK_RESULT();
1975         HWRM_UNLOCK();
1976
1977         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1978
1979         return rc;
1980 }
1981
1982 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1983                 int16_t fw_vf_id)
1984 {
1985         int rc = 0;
1986         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1987         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1988
1989         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1990                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1991                 return rc;
1992         }
1993         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1994
1995         req.enables =
1996                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1997         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1998         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1999
2000         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2001
2002         HWRM_CHECK_RESULT();
2003
2004         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2005         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2006         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2007         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2008         vnic->mru = rte_le_to_cpu_16(resp->mru);
2009         vnic->func_default = rte_le_to_cpu_32(
2010                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2011         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2012                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2013         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2014                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2015         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
2016                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
2017         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
2018                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
2019         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2020                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2021
2022         HWRM_UNLOCK();
2023
2024         return rc;
2025 }
2026
2027 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2028                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2029 {
2030         int rc = 0;
2031         uint16_t ctx_id;
2032         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2033         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2034                                                 bp->hwrm_cmd_resp_addr;
2035
2036         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2037
2038         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2039         HWRM_CHECK_RESULT();
2040
2041         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2042         if (!BNXT_HAS_RING_GRPS(bp))
2043                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2044         else if (ctx_idx == 0)
2045                 vnic->rss_rule = ctx_id;
2046
2047         HWRM_UNLOCK();
2048
2049         return rc;
2050 }
2051
2052 static
2053 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2054                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2055 {
2056         int rc = 0;
2057         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2058         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2059                                                 bp->hwrm_cmd_resp_addr;
2060
2061         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2062                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2063                 return rc;
2064         }
2065         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2066
2067         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2068
2069         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2070
2071         HWRM_CHECK_RESULT();
2072         HWRM_UNLOCK();
2073
2074         return rc;
2075 }
2076
2077 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2078 {
2079         int rc = 0;
2080
2081         if (BNXT_CHIP_THOR(bp)) {
2082                 int j;
2083
2084                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2085                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2086                                                       vnic,
2087                                                       vnic->fw_grp_ids[j]);
2088                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2089                 }
2090                 vnic->num_lb_ctxts = 0;
2091         } else {
2092                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2093                 vnic->rss_rule = INVALID_HW_RING_ID;
2094         }
2095
2096         return rc;
2097 }
2098
2099 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2100 {
2101         int rc = 0;
2102         struct hwrm_vnic_free_input req = {.req_type = 0 };
2103         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2104
2105         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2106                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2107                 return rc;
2108         }
2109
2110         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2111
2112         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2113
2114         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2115
2116         HWRM_CHECK_RESULT();
2117         HWRM_UNLOCK();
2118
2119         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2120         /* Configure default VNIC again if necessary. */
2121         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2122                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2123
2124         return rc;
2125 }
2126
2127 static int
2128 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2129 {
2130         int i;
2131         int rc = 0;
2132         int nr_ctxs = vnic->num_lb_ctxts;
2133         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2134         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2135
2136         for (i = 0; i < nr_ctxs; i++) {
2137                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2138
2139                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2140                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2141                 req.hash_mode_flags = vnic->hash_mode;
2142
2143                 req.hash_key_tbl_addr =
2144                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2145
2146                 req.ring_grp_tbl_addr =
2147                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2148                                          i * HW_HASH_INDEX_SIZE);
2149                 req.ring_table_pair_index = i;
2150                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2151
2152                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2153                                             BNXT_USE_CHIMP_MB);
2154
2155                 HWRM_CHECK_RESULT();
2156                 HWRM_UNLOCK();
2157         }
2158
2159         return rc;
2160 }
2161
2162 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2163                            struct bnxt_vnic_info *vnic)
2164 {
2165         int rc = 0;
2166         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2167         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2168
2169         if (!vnic->rss_table)
2170                 return 0;
2171
2172         if (BNXT_CHIP_THOR(bp))
2173                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2174
2175         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2176
2177         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2178         req.hash_mode_flags = vnic->hash_mode;
2179
2180         req.ring_grp_tbl_addr =
2181             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2182         req.hash_key_tbl_addr =
2183             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2184         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2185         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2186
2187         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2188
2189         HWRM_CHECK_RESULT();
2190         HWRM_UNLOCK();
2191
2192         return rc;
2193 }
2194
2195 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2196                         struct bnxt_vnic_info *vnic)
2197 {
2198         int rc = 0;
2199         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2200         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2201         uint16_t size;
2202
2203         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2204                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2205                 return rc;
2206         }
2207
2208         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2209
2210         req.flags = rte_cpu_to_le_32(
2211                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2212
2213         req.enables = rte_cpu_to_le_32(
2214                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2215
2216         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2217         size -= RTE_PKTMBUF_HEADROOM;
2218         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2219
2220         req.jumbo_thresh = rte_cpu_to_le_16(size);
2221         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2222
2223         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2224
2225         HWRM_CHECK_RESULT();
2226         HWRM_UNLOCK();
2227
2228         return rc;
2229 }
2230
2231 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2232                         struct bnxt_vnic_info *vnic, bool enable)
2233 {
2234         int rc = 0;
2235         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2236         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2237
2238         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2239                 if (enable)
2240                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2241                 return -ENOTSUP;
2242         }
2243
2244         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2245                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2246                 return 0;
2247         }
2248
2249         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2250
2251         if (enable) {
2252                 req.enables = rte_cpu_to_le_32(
2253                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2254                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2255                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2256                 req.flags = rte_cpu_to_le_32(
2257                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2258                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2259                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2260                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2261                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2262                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2263                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2264                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2265                 req.min_agg_len = rte_cpu_to_le_32(512);
2266         }
2267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2268
2269         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2270
2271         HWRM_CHECK_RESULT();
2272         HWRM_UNLOCK();
2273
2274         return rc;
2275 }
2276
2277 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2278 {
2279         struct hwrm_func_cfg_input req = {0};
2280         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2281         int rc;
2282
2283         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2284         req.enables = rte_cpu_to_le_32(
2285                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2286         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2287         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2288
2289         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2290
2291         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2292         HWRM_CHECK_RESULT();
2293         HWRM_UNLOCK();
2294
2295         bp->pf->vf_info[vf].random_mac = false;
2296
2297         return rc;
2298 }
2299
2300 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2301                                   uint64_t *dropped)
2302 {
2303         int rc = 0;
2304         struct hwrm_func_qstats_input req = {.req_type = 0};
2305         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2306
2307         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2308
2309         req.fid = rte_cpu_to_le_16(fid);
2310
2311         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2312
2313         HWRM_CHECK_RESULT();
2314
2315         if (dropped)
2316                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2317
2318         HWRM_UNLOCK();
2319
2320         return rc;
2321 }
2322
2323 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2324                           struct rte_eth_stats *stats,
2325                           struct hwrm_func_qstats_output *func_qstats)
2326 {
2327         int rc = 0;
2328         struct hwrm_func_qstats_input req = {.req_type = 0};
2329         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2330
2331         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2332
2333         req.fid = rte_cpu_to_le_16(fid);
2334
2335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2336
2337         HWRM_CHECK_RESULT();
2338         if (func_qstats)
2339                 memcpy(func_qstats, resp,
2340                        sizeof(struct hwrm_func_qstats_output));
2341
2342         if (!stats)
2343                 goto exit;
2344
2345         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2346         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2347         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2348         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2349         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2350         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2351
2352         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2353         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2354         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2355         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2356         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2357         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2358
2359         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2360         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2361         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2362
2363 exit:
2364         HWRM_UNLOCK();
2365
2366         return rc;
2367 }
2368
2369 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2370 {
2371         int rc = 0;
2372         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2373         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2374
2375         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2376
2377         req.fid = rte_cpu_to_le_16(fid);
2378
2379         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2380
2381         HWRM_CHECK_RESULT();
2382         HWRM_UNLOCK();
2383
2384         return rc;
2385 }
2386
2387 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2388 {
2389         unsigned int i;
2390         int rc = 0;
2391
2392         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2393                 struct bnxt_tx_queue *txq;
2394                 struct bnxt_rx_queue *rxq;
2395                 struct bnxt_cp_ring_info *cpr;
2396
2397                 if (i >= bp->rx_cp_nr_rings) {
2398                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2399                         cpr = txq->cp_ring;
2400                 } else {
2401                         rxq = bp->rx_queues[i];
2402                         cpr = rxq->cp_ring;
2403                 }
2404
2405                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2406                 if (rc)
2407                         return rc;
2408         }
2409         return 0;
2410 }
2411
2412 static int
2413 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2414 {
2415         int rc;
2416         unsigned int i;
2417         struct bnxt_cp_ring_info *cpr;
2418
2419         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2420
2421                 if (i >= bp->rx_cp_nr_rings) {
2422                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2423                 } else {
2424                         cpr = bp->rx_queues[i]->cp_ring;
2425                         if (BNXT_HAS_RING_GRPS(bp))
2426                                 bp->grp_info[i].fw_stats_ctx = -1;
2427                 }
2428                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2429                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2430                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2431                         if (rc)
2432                                 return rc;
2433                 }
2434         }
2435         return 0;
2436 }
2437
2438 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2439 {
2440         unsigned int i;
2441         int rc = 0;
2442
2443         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2444                 struct bnxt_tx_queue *txq;
2445                 struct bnxt_rx_queue *rxq;
2446                 struct bnxt_cp_ring_info *cpr;
2447
2448                 if (i >= bp->rx_cp_nr_rings) {
2449                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2450                         cpr = txq->cp_ring;
2451                 } else {
2452                         rxq = bp->rx_queues[i];
2453                         cpr = rxq->cp_ring;
2454                 }
2455
2456                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2457
2458                 if (rc)
2459                         return rc;
2460         }
2461         return rc;
2462 }
2463
2464 static int
2465 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2466 {
2467         uint16_t idx;
2468         uint32_t rc = 0;
2469
2470         if (!BNXT_HAS_RING_GRPS(bp))
2471                 return 0;
2472
2473         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2474
2475                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2476                         continue;
2477
2478                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2479
2480                 if (rc)
2481                         return rc;
2482         }
2483         return rc;
2484 }
2485
2486 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2487 {
2488         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2489
2490         bnxt_hwrm_ring_free(bp, cp_ring,
2491                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2492         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2493         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2494                                      sizeof(*cpr->cp_desc_ring));
2495         cpr->cp_raw_cons = 0;
2496         cpr->valid = 0;
2497 }
2498
2499 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2500 {
2501         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2502
2503         bnxt_hwrm_ring_free(bp, cp_ring,
2504                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2505         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2506         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2507                         sizeof(*cpr->cp_desc_ring));
2508         cpr->cp_raw_cons = 0;
2509         cpr->valid = 0;
2510 }
2511
2512 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2513 {
2514         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2515         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2516         struct bnxt_ring *ring = rxr->rx_ring_struct;
2517         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2518
2519         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2520                 bnxt_hwrm_ring_free(bp, ring,
2521                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2522                 ring->fw_ring_id = INVALID_HW_RING_ID;
2523                 if (BNXT_HAS_RING_GRPS(bp))
2524                         bp->grp_info[queue_index].rx_fw_ring_id =
2525                                                         INVALID_HW_RING_ID;
2526         }
2527         ring = rxr->ag_ring_struct;
2528         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2529                 bnxt_hwrm_ring_free(bp, ring,
2530                                     BNXT_CHIP_THOR(bp) ?
2531                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2532                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2533                 if (BNXT_HAS_RING_GRPS(bp))
2534                         bp->grp_info[queue_index].ag_fw_ring_id =
2535                                                         INVALID_HW_RING_ID;
2536         }
2537         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2538                 bnxt_free_cp_ring(bp, cpr);
2539
2540         if (BNXT_HAS_RING_GRPS(bp))
2541                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2542 }
2543
2544 static int
2545 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2546 {
2547         unsigned int i;
2548
2549         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2550                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2551                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2552                 struct bnxt_ring *ring = txr->tx_ring_struct;
2553                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2554
2555                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2556                         bnxt_hwrm_ring_free(bp, ring,
2557                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2558                         ring->fw_ring_id = INVALID_HW_RING_ID;
2559                         memset(txr->tx_desc_ring, 0,
2560                                         txr->tx_ring_struct->ring_size *
2561                                         sizeof(*txr->tx_desc_ring));
2562                         memset(txr->tx_buf_ring, 0,
2563                                         txr->tx_ring_struct->ring_size *
2564                                         sizeof(*txr->tx_buf_ring));
2565                         txr->tx_prod = 0;
2566                         txr->tx_cons = 0;
2567                 }
2568                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2569                         bnxt_free_cp_ring(bp, cpr);
2570                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2571                 }
2572         }
2573
2574         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2575                 bnxt_free_hwrm_rx_ring(bp, i);
2576
2577         return 0;
2578 }
2579
2580 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2581 {
2582         uint16_t i;
2583         uint32_t rc = 0;
2584
2585         if (!BNXT_HAS_RING_GRPS(bp))
2586                 return 0;
2587
2588         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2589                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2590                 if (rc)
2591                         return rc;
2592         }
2593         return rc;
2594 }
2595
2596 /*
2597  * HWRM utility functions
2598  */
2599
2600 void bnxt_free_hwrm_resources(struct bnxt *bp)
2601 {
2602         /* Release memzone */
2603         rte_free(bp->hwrm_cmd_resp_addr);
2604         rte_free(bp->hwrm_short_cmd_req_addr);
2605         bp->hwrm_cmd_resp_addr = NULL;
2606         bp->hwrm_short_cmd_req_addr = NULL;
2607         bp->hwrm_cmd_resp_dma_addr = 0;
2608         bp->hwrm_short_cmd_req_dma_addr = 0;
2609 }
2610
2611 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2612 {
2613         struct rte_pci_device *pdev = bp->pdev;
2614         char type[RTE_MEMZONE_NAMESIZE];
2615
2616         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2617                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2618         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2619         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2620         if (bp->hwrm_cmd_resp_addr == NULL)
2621                 return -ENOMEM;
2622         bp->hwrm_cmd_resp_dma_addr =
2623                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2624         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2625                 PMD_DRV_LOG(ERR,
2626                         "unable to map response address to physical memory\n");
2627                 return -ENOMEM;
2628         }
2629         rte_spinlock_init(&bp->hwrm_lock);
2630
2631         return 0;
2632 }
2633
2634 int
2635 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2636 {
2637         int rc = 0;
2638
2639         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2640                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2641                 if (rc)
2642                         return rc;
2643         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2644                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2645                 if (rc)
2646                         return rc;
2647         }
2648
2649         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2650         return rc;
2651 }
2652
2653 static int
2654 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2655 {
2656         struct bnxt_filter_info *filter;
2657         int rc = 0;
2658
2659         STAILQ_FOREACH(filter, &vnic->filter, next) {
2660                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2661                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2662                 bnxt_free_filter(bp, filter);
2663         }
2664         return rc;
2665 }
2666
2667 static int
2668 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2669 {
2670         struct bnxt_filter_info *filter;
2671         struct rte_flow *flow;
2672         int rc = 0;
2673
2674         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2675                 flow = STAILQ_FIRST(&vnic->flow_list);
2676                 filter = flow->filter;
2677                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2678                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2679
2680                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2681                 rte_free(flow);
2682         }
2683         return rc;
2684 }
2685
2686 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2687 {
2688         struct bnxt_filter_info *filter;
2689         int rc = 0;
2690
2691         STAILQ_FOREACH(filter, &vnic->filter, next) {
2692                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2693                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2694                                                      filter);
2695                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2696                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2697                                                          filter);
2698                 else
2699                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2700                                                      filter);
2701                 if (rc)
2702                         break;
2703         }
2704         return rc;
2705 }
2706
2707 static void
2708 bnxt_free_tunnel_ports(struct bnxt *bp)
2709 {
2710         if (bp->vxlan_port_cnt)
2711                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2712                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2713         bp->vxlan_port = 0;
2714         if (bp->geneve_port_cnt)
2715                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2716                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2717         bp->geneve_port = 0;
2718 }
2719
2720 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2721 {
2722         int i;
2723
2724         if (bp->vnic_info == NULL)
2725                 return;
2726
2727         /*
2728          * Cleanup VNICs in reverse order, to make sure the L2 filter
2729          * from vnic0 is last to be cleaned up.
2730          */
2731         for (i = bp->max_vnics - 1; i >= 0; i--) {
2732                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2733
2734                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2735                         continue;
2736
2737                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2738
2739                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2740
2741                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2742
2743                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2744
2745                 bnxt_hwrm_vnic_free(bp, vnic);
2746
2747                 rte_free(vnic->fw_grp_ids);
2748         }
2749         /* Ring resources */
2750         bnxt_free_all_hwrm_rings(bp);
2751         bnxt_free_all_hwrm_ring_grps(bp);
2752         bnxt_free_all_hwrm_stat_ctxs(bp);
2753         bnxt_free_tunnel_ports(bp);
2754 }
2755
2756 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2757 {
2758         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2759
2760         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2761                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2762
2763         switch (conf_link_speed) {
2764         case ETH_LINK_SPEED_10M_HD:
2765         case ETH_LINK_SPEED_100M_HD:
2766                 /* FALLTHROUGH */
2767                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2768         }
2769         return hw_link_duplex;
2770 }
2771
2772 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2773 {
2774         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2775 }
2776
2777 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2778 {
2779         uint16_t eth_link_speed = 0;
2780
2781         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2782                 return ETH_LINK_SPEED_AUTONEG;
2783
2784         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2785         case ETH_LINK_SPEED_100M:
2786         case ETH_LINK_SPEED_100M_HD:
2787                 /* FALLTHROUGH */
2788                 eth_link_speed =
2789                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2790                 break;
2791         case ETH_LINK_SPEED_1G:
2792                 eth_link_speed =
2793                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2794                 break;
2795         case ETH_LINK_SPEED_2_5G:
2796                 eth_link_speed =
2797                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2798                 break;
2799         case ETH_LINK_SPEED_10G:
2800                 eth_link_speed =
2801                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2802                 break;
2803         case ETH_LINK_SPEED_20G:
2804                 eth_link_speed =
2805                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2806                 break;
2807         case ETH_LINK_SPEED_25G:
2808                 eth_link_speed =
2809                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2810                 break;
2811         case ETH_LINK_SPEED_40G:
2812                 eth_link_speed =
2813                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2814                 break;
2815         case ETH_LINK_SPEED_50G:
2816                 eth_link_speed =
2817                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2818                 break;
2819         case ETH_LINK_SPEED_100G:
2820                 eth_link_speed =
2821                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2822                 break;
2823         case ETH_LINK_SPEED_200G:
2824                 eth_link_speed =
2825                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2826                 break;
2827         default:
2828                 PMD_DRV_LOG(ERR,
2829                         "Unsupported link speed %d; default to AUTO\n",
2830                         conf_link_speed);
2831                 break;
2832         }
2833         return eth_link_speed;
2834 }
2835
2836 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2837                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2838                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2839                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2840                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2841
2842 static int bnxt_validate_link_speed(struct bnxt *bp)
2843 {
2844         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2845         uint16_t port_id = bp->eth_dev->data->port_id;
2846         uint32_t link_speed_capa;
2847         uint32_t one_speed;
2848
2849         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2850                 return 0;
2851
2852         link_speed_capa = bnxt_get_speed_capabilities(bp);
2853
2854         if (link_speed & ETH_LINK_SPEED_FIXED) {
2855                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2856
2857                 if (one_speed & (one_speed - 1)) {
2858                         PMD_DRV_LOG(ERR,
2859                                 "Invalid advertised speeds (%u) for port %u\n",
2860                                 link_speed, port_id);
2861                         return -EINVAL;
2862                 }
2863                 if ((one_speed & link_speed_capa) != one_speed) {
2864                         PMD_DRV_LOG(ERR,
2865                                 "Unsupported advertised speed (%u) for port %u\n",
2866                                 link_speed, port_id);
2867                         return -EINVAL;
2868                 }
2869         } else {
2870                 if (!(link_speed & link_speed_capa)) {
2871                         PMD_DRV_LOG(ERR,
2872                                 "Unsupported advertised speeds (%u) for port %u\n",
2873                                 link_speed, port_id);
2874                         return -EINVAL;
2875                 }
2876         }
2877         return 0;
2878 }
2879
2880 static uint16_t
2881 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2882 {
2883         uint16_t ret = 0;
2884
2885         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2886                 if (bp->link_info->support_speeds)
2887                         return bp->link_info->support_speeds;
2888                 link_speed = BNXT_SUPPORTED_SPEEDS;
2889         }
2890
2891         if (link_speed & ETH_LINK_SPEED_100M)
2892                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2893         if (link_speed & ETH_LINK_SPEED_100M_HD)
2894                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2895         if (link_speed & ETH_LINK_SPEED_1G)
2896                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2897         if (link_speed & ETH_LINK_SPEED_2_5G)
2898                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2899         if (link_speed & ETH_LINK_SPEED_10G)
2900                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2901         if (link_speed & ETH_LINK_SPEED_20G)
2902                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2903         if (link_speed & ETH_LINK_SPEED_25G)
2904                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2905         if (link_speed & ETH_LINK_SPEED_40G)
2906                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2907         if (link_speed & ETH_LINK_SPEED_50G)
2908                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2909         if (link_speed & ETH_LINK_SPEED_100G)
2910                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2911         if (link_speed & ETH_LINK_SPEED_200G)
2912                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2913         return ret;
2914 }
2915
2916 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2917 {
2918         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2919
2920         switch (hw_link_speed) {
2921         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2922                 eth_link_speed = ETH_SPEED_NUM_100M;
2923                 break;
2924         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2925                 eth_link_speed = ETH_SPEED_NUM_1G;
2926                 break;
2927         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2928                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2929                 break;
2930         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2931                 eth_link_speed = ETH_SPEED_NUM_10G;
2932                 break;
2933         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2934                 eth_link_speed = ETH_SPEED_NUM_20G;
2935                 break;
2936         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2937                 eth_link_speed = ETH_SPEED_NUM_25G;
2938                 break;
2939         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2940                 eth_link_speed = ETH_SPEED_NUM_40G;
2941                 break;
2942         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2943                 eth_link_speed = ETH_SPEED_NUM_50G;
2944                 break;
2945         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2946                 eth_link_speed = ETH_SPEED_NUM_100G;
2947                 break;
2948         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2949                 eth_link_speed = ETH_SPEED_NUM_200G;
2950                 break;
2951         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2952         default:
2953                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2954                         hw_link_speed);
2955                 break;
2956         }
2957         return eth_link_speed;
2958 }
2959
2960 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2961 {
2962         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2963
2964         switch (hw_link_duplex) {
2965         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2966         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2967                 /* FALLTHROUGH */
2968                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2969                 break;
2970         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2971                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2972                 break;
2973         default:
2974                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2975                         hw_link_duplex);
2976                 break;
2977         }
2978         return eth_link_duplex;
2979 }
2980
2981 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2982 {
2983         int rc = 0;
2984         struct bnxt_link_info *link_info = bp->link_info;
2985
2986         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2987         if (rc) {
2988                 PMD_DRV_LOG(ERR,
2989                         "Get link config failed with rc %d\n", rc);
2990                 goto exit;
2991         }
2992         if (link_info->link_speed)
2993                 link->link_speed =
2994                         bnxt_parse_hw_link_speed(link_info->link_speed);
2995         else
2996                 link->link_speed = ETH_SPEED_NUM_NONE;
2997         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2998         link->link_status = link_info->link_up;
2999         link->link_autoneg = link_info->auto_mode ==
3000                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3001                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3002 exit:
3003         return rc;
3004 }
3005
3006 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3007 {
3008         int rc = 0;
3009         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3010         struct bnxt_link_info link_req;
3011         uint16_t speed, autoneg;
3012
3013         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3014                 return 0;
3015
3016         rc = bnxt_validate_link_speed(bp);
3017         if (rc)
3018                 goto error;
3019
3020         memset(&link_req, 0, sizeof(link_req));
3021         link_req.link_up = link_up;
3022         if (!link_up)
3023                 goto port_phy_cfg;
3024
3025         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3026         if (BNXT_CHIP_THOR(bp) &&
3027             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3028                 /* 40G is not supported as part of media auto detect.
3029                  * The speed should be forced and autoneg disabled
3030                  * to configure 40G speed.
3031                  */
3032                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3033                 autoneg = 0;
3034         }
3035
3036         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
3037         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3038         /* Autoneg can be done only when the FW allows.
3039          * When user configures fixed speed of 40G and later changes to
3040          * any other speed, auto_link_speed/force_link_speed is still set
3041          * to 40G until link comes up at new speed.
3042          */
3043         if (autoneg == 1 &&
3044             !(!BNXT_CHIP_THOR(bp) &&
3045               (bp->link_info->auto_link_speed ||
3046                bp->link_info->force_link_speed))) {
3047                 link_req.phy_flags |=
3048                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3049                 link_req.auto_link_speed_mask =
3050                         bnxt_parse_eth_link_speed_mask(bp,
3051                                                        dev_conf->link_speeds);
3052         } else {
3053                 if (bp->link_info->phy_type ==
3054                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3055                     bp->link_info->phy_type ==
3056                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3057                     bp->link_info->media_type ==
3058                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3059                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3060                         return -EINVAL;
3061                 }
3062
3063                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3064                 /* If user wants a particular speed try that first. */
3065                 if (speed)
3066                         link_req.link_speed = speed;
3067                 else if (bp->link_info->force_link_speed)
3068                         link_req.link_speed = bp->link_info->force_link_speed;
3069                 else
3070                         link_req.link_speed = bp->link_info->auto_link_speed;
3071         }
3072         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3073         link_req.auto_pause = bp->link_info->auto_pause;
3074         link_req.force_pause = bp->link_info->force_pause;
3075
3076 port_phy_cfg:
3077         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3078         if (rc) {
3079                 PMD_DRV_LOG(ERR,
3080                         "Set link config failed with rc %d\n", rc);
3081         }
3082
3083 error:
3084         return rc;
3085 }
3086
3087 /* JIRA 22088 */
3088 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3089 {
3090         struct hwrm_func_qcfg_input req = {0};
3091         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3092         uint16_t flags;
3093         int rc = 0;
3094         bp->func_svif = BNXT_SVIF_INVALID;
3095         uint16_t svif_info;
3096
3097         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3098         req.fid = rte_cpu_to_le_16(0xffff);
3099
3100         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3101
3102         HWRM_CHECK_RESULT();
3103
3104         /* Hard Coded.. 0xfff VLAN ID mask */
3105         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3106
3107         svif_info = rte_le_to_cpu_16(resp->svif_info);
3108         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3109                 bp->func_svif = svif_info &
3110                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3111
3112         flags = rte_le_to_cpu_16(resp->flags);
3113         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3114                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3115
3116         if (BNXT_VF(bp) &&
3117             !BNXT_VF_IS_TRUSTED(bp) &&
3118             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3119                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3120                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3121         } else if (BNXT_VF(bp) &&
3122                    BNXT_VF_IS_TRUSTED(bp) &&
3123                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3124                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3125                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3126         }
3127
3128         if (mtu)
3129                 *mtu = rte_le_to_cpu_16(resp->mtu);
3130
3131         switch (resp->port_partition_type) {
3132         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3133         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3134         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3135                 /* FALLTHROUGH */
3136                 bp->flags |= BNXT_FLAG_NPAR_PF;
3137                 break;
3138         default:
3139                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3140                 break;
3141         }
3142
3143         HWRM_UNLOCK();
3144
3145         return rc;
3146 }
3147
3148 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3149 {
3150         struct hwrm_func_qcfg_input req = {0};
3151         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3152         int rc;
3153
3154         if (!BNXT_VF_IS_TRUSTED(bp))
3155                 return 0;
3156
3157         if (!bp->parent)
3158                 return -EINVAL;
3159
3160         bp->parent->fid = BNXT_PF_FID_INVALID;
3161
3162         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3163
3164         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3165
3166         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3167
3168         HWRM_CHECK_RESULT();
3169
3170         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3171         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3172         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3173         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3174
3175         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3176         if (bp->parent->vnic == 0) {
3177                 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3178                 /* Use hard-coded values appropriate for current Wh+ fw. */
3179                 if (bp->parent->fid == 2)
3180                         bp->parent->vnic = 0x100;
3181                 else
3182                         bp->parent->vnic = 1;
3183         }
3184
3185         HWRM_UNLOCK();
3186
3187         return 0;
3188 }
3189
3190 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3191                                  uint16_t *vnic_id, uint16_t *svif)
3192 {
3193         struct hwrm_func_qcfg_input req = {0};
3194         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3195         uint16_t svif_info;
3196         int rc = 0;
3197
3198         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3199         req.fid = rte_cpu_to_le_16(fid);
3200
3201         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3202
3203         HWRM_CHECK_RESULT();
3204
3205         if (vnic_id)
3206                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3207
3208         svif_info = rte_le_to_cpu_16(resp->svif_info);
3209         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3210                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3211
3212         HWRM_UNLOCK();
3213
3214         return rc;
3215 }
3216
3217 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3218 {
3219         struct hwrm_port_mac_qcfg_input req = {0};
3220         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3221         uint16_t port_svif_info;
3222         int rc;
3223
3224         bp->port_svif = BNXT_SVIF_INVALID;
3225
3226         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3227                 return 0;
3228
3229         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3230
3231         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3232
3233         HWRM_CHECK_RESULT_SILENT();
3234
3235         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3236         if (port_svif_info &
3237             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3238                 bp->port_svif = port_svif_info &
3239                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3240
3241         HWRM_UNLOCK();
3242
3243         return 0;
3244 }
3245
3246 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3247                                    struct hwrm_func_qcaps_output *qcaps)
3248 {
3249         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3250         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3251                sizeof(qcaps->mac_address));
3252         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3253         qcaps->max_rx_rings = fcfg->num_rx_rings;
3254         qcaps->max_tx_rings = fcfg->num_tx_rings;
3255         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3256         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3257         qcaps->max_vfs = 0;
3258         qcaps->first_vf_id = 0;
3259         qcaps->max_vnics = fcfg->num_vnics;
3260         qcaps->max_decap_records = 0;
3261         qcaps->max_encap_records = 0;
3262         qcaps->max_tx_wm_flows = 0;
3263         qcaps->max_tx_em_flows = 0;
3264         qcaps->max_rx_wm_flows = 0;
3265         qcaps->max_rx_em_flows = 0;
3266         qcaps->max_flow_id = 0;
3267         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3268         qcaps->max_sp_tx_rings = 0;
3269         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3270 }
3271
3272 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3273 {
3274         struct hwrm_func_cfg_input req = {0};
3275         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3276         uint32_t enables;
3277         int rc;
3278
3279         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3280                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3281                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3282                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3283                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3284                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3285                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3286                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3287                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3288
3289         if (BNXT_HAS_RING_GRPS(bp)) {
3290                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3291                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3292         } else if (BNXT_HAS_NQ(bp)) {
3293                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3294                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3295         }
3296
3297         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3298         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3299         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3300         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3301         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3302         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3303         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3304         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3305         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3306         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3307         req.fid = rte_cpu_to_le_16(0xffff);
3308         req.enables = rte_cpu_to_le_32(enables);
3309
3310         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3311
3312         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3313
3314         HWRM_CHECK_RESULT();
3315         HWRM_UNLOCK();
3316
3317         return rc;
3318 }
3319
3320 static void populate_vf_func_cfg_req(struct bnxt *bp,
3321                                      struct hwrm_func_cfg_input *req,
3322                                      int num_vfs)
3323 {
3324         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3325                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3326                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3327                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3328                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3329                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3330                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3331                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3332                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3333                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3334
3335         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3336                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3337                                     BNXT_NUM_VLANS);
3338         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3339         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3340                                                 (num_vfs + 1));
3341         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3342         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3343                                                (num_vfs + 1));
3344         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3345         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3346         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3347         /* TODO: For now, do not support VMDq/RFS on VFs. */
3348         req->num_vnics = rte_cpu_to_le_16(1);
3349         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3350                                                  (num_vfs + 1));
3351 }
3352
3353 static void add_random_mac_if_needed(struct bnxt *bp,
3354                                      struct hwrm_func_cfg_input *cfg_req,
3355                                      int vf)
3356 {
3357         struct rte_ether_addr mac;
3358
3359         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3360                 return;
3361
3362         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3363                 cfg_req->enables |=
3364                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3365                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3366                 bp->pf->vf_info[vf].random_mac = true;
3367         } else {
3368                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3369                         RTE_ETHER_ADDR_LEN);
3370         }
3371 }
3372
3373 static int reserve_resources_from_vf(struct bnxt *bp,
3374                                      struct hwrm_func_cfg_input *cfg_req,
3375                                      int vf)
3376 {
3377         struct hwrm_func_qcaps_input req = {0};
3378         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3379         int rc;
3380
3381         /* Get the actual allocated values now */
3382         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3383         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3384         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3385
3386         if (rc) {
3387                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3388                 copy_func_cfg_to_qcaps(cfg_req, resp);
3389         } else if (resp->error_code) {
3390                 rc = rte_le_to_cpu_16(resp->error_code);
3391                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3392                 copy_func_cfg_to_qcaps(cfg_req, resp);
3393         }
3394
3395         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3396         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3397         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3398         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3399         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3400         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3401         /*
3402          * TODO: While not supporting VMDq with VFs, max_vnics is always
3403          * forced to 1 in this case
3404          */
3405         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3406         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3407
3408         HWRM_UNLOCK();
3409
3410         return 0;
3411 }
3412
3413 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3414 {
3415         struct hwrm_func_qcfg_input req = {0};
3416         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3417         int rc;
3418
3419         /* Check for zero MAC address */
3420         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3421         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3422         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3423         HWRM_CHECK_RESULT();
3424         rc = rte_le_to_cpu_16(resp->vlan);
3425
3426         HWRM_UNLOCK();
3427
3428         return rc;
3429 }
3430
3431 static int update_pf_resource_max(struct bnxt *bp)
3432 {
3433         struct hwrm_func_qcfg_input req = {0};
3434         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3435         int rc;
3436
3437         /* And copy the allocated numbers into the pf struct */
3438         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3439         req.fid = rte_cpu_to_le_16(0xffff);
3440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3441         HWRM_CHECK_RESULT();
3442
3443         /* Only TX ring value reflects actual allocation? TODO */
3444         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3445         bp->pf->evb_mode = resp->evb_mode;
3446
3447         HWRM_UNLOCK();
3448
3449         return rc;
3450 }
3451
3452 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3453 {
3454         int rc;
3455
3456         if (!BNXT_PF(bp)) {
3457                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3458                 return -EINVAL;
3459         }
3460
3461         rc = bnxt_hwrm_func_qcaps(bp);
3462         if (rc)
3463                 return rc;
3464
3465         bp->pf->func_cfg_flags &=
3466                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3467                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3468         bp->pf->func_cfg_flags |=
3469                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3470         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3471         rc = __bnxt_hwrm_func_qcaps(bp);
3472         return rc;
3473 }
3474
3475 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3476 {
3477         struct hwrm_func_cfg_input req = {0};
3478         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3479         int i;
3480         size_t sz;
3481         int rc = 0;
3482         size_t req_buf_sz;
3483
3484         if (!BNXT_PF(bp)) {
3485                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3486                 return -EINVAL;
3487         }
3488
3489         rc = bnxt_hwrm_func_qcaps(bp);
3490
3491         if (rc)
3492                 return rc;
3493
3494         bp->pf->active_vfs = num_vfs;
3495
3496         /*
3497          * First, configure the PF to only use one TX ring.  This ensures that
3498          * there are enough rings for all VFs.
3499          *
3500          * If we don't do this, when we call func_alloc() later, we will lock
3501          * extra rings to the PF that won't be available during func_cfg() of
3502          * the VFs.
3503          *
3504          * This has been fixed with firmware versions above 20.6.54
3505          */
3506         bp->pf->func_cfg_flags &=
3507                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3508                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3509         bp->pf->func_cfg_flags |=
3510                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3511         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3512         if (rc)
3513                 return rc;
3514
3515         /*
3516          * Now, create and register a buffer to hold forwarded VF requests
3517          */
3518         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3519         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3520                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3521         if (bp->pf->vf_req_buf == NULL) {
3522                 rc = -ENOMEM;
3523                 goto error_free;
3524         }
3525         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3526                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3527         for (i = 0; i < num_vfs; i++)
3528                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3529                                         (i * HWRM_MAX_REQ_LEN);
3530
3531         rc = bnxt_hwrm_func_buf_rgtr(bp);
3532         if (rc)
3533                 goto error_free;
3534
3535         populate_vf_func_cfg_req(bp, &req, num_vfs);
3536
3537         bp->pf->active_vfs = 0;
3538         for (i = 0; i < num_vfs; i++) {
3539                 add_random_mac_if_needed(bp, &req, i);
3540
3541                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3542                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3543                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3544                 rc = bnxt_hwrm_send_message(bp,
3545                                             &req,
3546                                             sizeof(req),
3547                                             BNXT_USE_CHIMP_MB);
3548
3549                 /* Clear enable flag for next pass */
3550                 req.enables &= ~rte_cpu_to_le_32(
3551                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3552
3553                 if (rc || resp->error_code) {
3554                         PMD_DRV_LOG(ERR,
3555                                 "Failed to initizlie VF %d\n", i);
3556                         PMD_DRV_LOG(ERR,
3557                                 "Not all VFs available. (%d, %d)\n",
3558                                 rc, resp->error_code);
3559                         HWRM_UNLOCK();
3560                         break;
3561                 }
3562
3563                 HWRM_UNLOCK();
3564
3565                 reserve_resources_from_vf(bp, &req, i);
3566                 bp->pf->active_vfs++;
3567                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3568         }
3569
3570         /*
3571          * Now configure the PF to use "the rest" of the resources
3572          * We're using STD_TX_RING_MODE here though which will limit the TX
3573          * rings.  This will allow QoS to function properly.  Not setting this
3574          * will cause PF rings to break bandwidth settings.
3575          */
3576         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3577         if (rc)
3578                 goto error_free;
3579
3580         rc = update_pf_resource_max(bp);
3581         if (rc)
3582                 goto error_free;
3583
3584         return rc;
3585
3586 error_free:
3587         bnxt_hwrm_func_buf_unrgtr(bp);
3588         return rc;
3589 }
3590
3591 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3592 {
3593         struct hwrm_func_cfg_input req = {0};
3594         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3595         int rc;
3596
3597         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3598
3599         req.fid = rte_cpu_to_le_16(0xffff);
3600         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3601         req.evb_mode = bp->pf->evb_mode;
3602
3603         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3604         HWRM_CHECK_RESULT();
3605         HWRM_UNLOCK();
3606
3607         return rc;
3608 }
3609
3610 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3611                                 uint8_t tunnel_type)
3612 {
3613         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3614         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3615         int rc = 0;
3616
3617         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3618         req.tunnel_type = tunnel_type;
3619         req.tunnel_dst_port_val = port;
3620         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3621         HWRM_CHECK_RESULT();
3622
3623         switch (tunnel_type) {
3624         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3625                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3626                 bp->vxlan_port = port;
3627                 break;
3628         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3629                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3630                 bp->geneve_port = port;
3631                 break;
3632         default:
3633                 break;
3634         }
3635
3636         HWRM_UNLOCK();
3637
3638         return rc;
3639 }
3640
3641 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3642                                 uint8_t tunnel_type)
3643 {
3644         struct hwrm_tunnel_dst_port_free_input req = {0};
3645         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3646         int rc = 0;
3647
3648         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3649
3650         req.tunnel_type = tunnel_type;
3651         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3653
3654         HWRM_CHECK_RESULT();
3655         HWRM_UNLOCK();
3656
3657         return rc;
3658 }
3659
3660 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3661                                         uint32_t flags)
3662 {
3663         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3664         struct hwrm_func_cfg_input req = {0};
3665         int rc;
3666
3667         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3668
3669         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3670         req.flags = rte_cpu_to_le_32(flags);
3671         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3672
3673         HWRM_CHECK_RESULT();
3674         HWRM_UNLOCK();
3675
3676         return rc;
3677 }
3678
3679 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3680 {
3681         uint32_t *flag = flagp;
3682
3683         vnic->flags = *flag;
3684 }
3685
3686 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3687 {
3688         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3689 }
3690
3691 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3692 {
3693         int rc = 0;
3694         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3695         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3696
3697         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3698
3699         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3700         req.req_buf_page_size = rte_cpu_to_le_16(
3701                          page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3702         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3703         req.req_buf_page_addr0 =
3704                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3705         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3706                 PMD_DRV_LOG(ERR,
3707                         "unable to map buffer address to physical memory\n");
3708                 return -ENOMEM;
3709         }
3710
3711         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3712
3713         HWRM_CHECK_RESULT();
3714         HWRM_UNLOCK();
3715
3716         return rc;
3717 }
3718
3719 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3720 {
3721         int rc = 0;
3722         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3723         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3724
3725         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3726                 return 0;
3727
3728         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3729
3730         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3731
3732         HWRM_CHECK_RESULT();
3733         HWRM_UNLOCK();
3734
3735         return rc;
3736 }
3737
3738 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3739 {
3740         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3741         struct hwrm_func_cfg_input req = {0};
3742         int rc;
3743
3744         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3745
3746         req.fid = rte_cpu_to_le_16(0xffff);
3747         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3748         req.enables = rte_cpu_to_le_32(
3749                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3750         req.async_event_cr = rte_cpu_to_le_16(
3751                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3752         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3753
3754         HWRM_CHECK_RESULT();
3755         HWRM_UNLOCK();
3756
3757         return rc;
3758 }
3759
3760 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3761 {
3762         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3763         struct hwrm_func_vf_cfg_input req = {0};
3764         int rc;
3765
3766         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3767
3768         req.enables = rte_cpu_to_le_32(
3769                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3770         req.async_event_cr = rte_cpu_to_le_16(
3771                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3772         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3773
3774         HWRM_CHECK_RESULT();
3775         HWRM_UNLOCK();
3776
3777         return rc;
3778 }
3779
3780 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3781 {
3782         struct hwrm_func_cfg_input req = {0};
3783         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3784         uint16_t dflt_vlan, fid;
3785         uint32_t func_cfg_flags;
3786         int rc = 0;
3787
3788         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3789
3790         if (is_vf) {
3791                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3792                 fid = bp->pf->vf_info[vf].fid;
3793                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3794         } else {
3795                 fid = rte_cpu_to_le_16(0xffff);
3796                 func_cfg_flags = bp->pf->func_cfg_flags;
3797                 dflt_vlan = bp->vlan;
3798         }
3799
3800         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3801         req.fid = rte_cpu_to_le_16(fid);
3802         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3803         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3804
3805         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3806
3807         HWRM_CHECK_RESULT();
3808         HWRM_UNLOCK();
3809
3810         return rc;
3811 }
3812
3813 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3814                         uint16_t max_bw, uint16_t enables)
3815 {
3816         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3817         struct hwrm_func_cfg_input req = {0};
3818         int rc;
3819
3820         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3821
3822         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3823         req.enables |= rte_cpu_to_le_32(enables);
3824         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3825         req.max_bw = rte_cpu_to_le_32(max_bw);
3826         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3827
3828         HWRM_CHECK_RESULT();
3829         HWRM_UNLOCK();
3830
3831         return rc;
3832 }
3833
3834 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3835 {
3836         struct hwrm_func_cfg_input req = {0};
3837         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3838         int rc = 0;
3839
3840         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3841
3842         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3843         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3844         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3845         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3846
3847         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3848
3849         HWRM_CHECK_RESULT();
3850         HWRM_UNLOCK();
3851
3852         return rc;
3853 }
3854
3855 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3856 {
3857         int rc;
3858
3859         if (BNXT_PF(bp))
3860                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3861         else
3862                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3863
3864         return rc;
3865 }
3866
3867 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3868                               void *encaped, size_t ec_size)
3869 {
3870         int rc = 0;
3871         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3872         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3873
3874         if (ec_size > sizeof(req.encap_request))
3875                 return -1;
3876
3877         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3878
3879         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3880         memcpy(req.encap_request, encaped, ec_size);
3881
3882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3883
3884         HWRM_CHECK_RESULT();
3885         HWRM_UNLOCK();
3886
3887         return rc;
3888 }
3889
3890 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3891                                        struct rte_ether_addr *mac)
3892 {
3893         struct hwrm_func_qcfg_input req = {0};
3894         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3895         int rc;
3896
3897         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3898
3899         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3900         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3901
3902         HWRM_CHECK_RESULT();
3903
3904         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3905
3906         HWRM_UNLOCK();
3907
3908         return rc;
3909 }
3910
3911 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3912                             void *encaped, size_t ec_size)
3913 {
3914         int rc = 0;
3915         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3916         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3917
3918         if (ec_size > sizeof(req.encap_request))
3919                 return -1;
3920
3921         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3922
3923         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3924         memcpy(req.encap_request, encaped, ec_size);
3925
3926         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3927
3928         HWRM_CHECK_RESULT();
3929         HWRM_UNLOCK();
3930
3931         return rc;
3932 }
3933
3934 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3935                          struct rte_eth_stats *stats, uint8_t rx)
3936 {
3937         int rc = 0;
3938         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3939         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3940
3941         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3942
3943         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3944
3945         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3946
3947         HWRM_CHECK_RESULT();
3948
3949         if (rx) {
3950                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3951                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3952                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3953                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3954                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3955                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3956                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3957                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3958         } else {
3959                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3960                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3961                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3962                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3963                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3964                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3965         }
3966
3967         HWRM_UNLOCK();
3968
3969         return rc;
3970 }
3971
3972 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3973 {
3974         struct hwrm_port_qstats_input req = {0};
3975         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3976         struct bnxt_pf_info *pf = bp->pf;
3977         int rc;
3978
3979         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3980
3981         req.port_id = rte_cpu_to_le_16(pf->port_id);
3982         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3983         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3984         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3985
3986         HWRM_CHECK_RESULT();
3987         HWRM_UNLOCK();
3988
3989         return rc;
3990 }
3991
3992 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3993 {
3994         struct hwrm_port_clr_stats_input req = {0};
3995         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3996         struct bnxt_pf_info *pf = bp->pf;
3997         int rc;
3998
3999         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4000         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4001             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4002                 return 0;
4003
4004         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4005
4006         req.port_id = rte_cpu_to_le_16(pf->port_id);
4007         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4008
4009         HWRM_CHECK_RESULT();
4010         HWRM_UNLOCK();
4011
4012         return rc;
4013 }
4014
4015 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4016 {
4017         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4018         struct hwrm_port_led_qcaps_input req = {0};
4019         int rc;
4020
4021         if (BNXT_VF(bp))
4022                 return 0;
4023
4024         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4025         req.port_id = bp->pf->port_id;
4026         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4027
4028         HWRM_CHECK_RESULT();
4029
4030         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4031                 unsigned int i;
4032
4033                 bp->leds->num_leds = resp->num_leds;
4034                 memcpy(bp->leds, &resp->led0_id,
4035                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4036                 for (i = 0; i < bp->leds->num_leds; i++) {
4037                         struct bnxt_led_info *led = &bp->leds[i];
4038
4039                         uint16_t caps = led->led_state_caps;
4040
4041                         if (!led->led_group_id ||
4042                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4043                                 bp->leds->num_leds = 0;
4044                                 break;
4045                         }
4046                 }
4047         }
4048
4049         HWRM_UNLOCK();
4050
4051         return rc;
4052 }
4053
4054 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4055 {
4056         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4057         struct hwrm_port_led_cfg_input req = {0};
4058         struct bnxt_led_cfg *led_cfg;
4059         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4060         uint16_t duration = 0;
4061         int rc, i;
4062
4063         if (!bp->leds->num_leds || BNXT_VF(bp))
4064                 return -EOPNOTSUPP;
4065
4066         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4067
4068         if (led_on) {
4069                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4070                 duration = rte_cpu_to_le_16(500);
4071         }
4072         req.port_id = bp->pf->port_id;
4073         req.num_leds = bp->leds->num_leds;
4074         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4075         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4076                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4077                 led_cfg->led_id = bp->leds[i].led_id;
4078                 led_cfg->led_state = led_state;
4079                 led_cfg->led_blink_on = duration;
4080                 led_cfg->led_blink_off = duration;
4081                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4082         }
4083
4084         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4085
4086         HWRM_CHECK_RESULT();
4087         HWRM_UNLOCK();
4088
4089         return rc;
4090 }
4091
4092 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4093                                uint32_t *length)
4094 {
4095         int rc;
4096         struct hwrm_nvm_get_dir_info_input req = {0};
4097         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4098
4099         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4100
4101         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4102
4103         HWRM_CHECK_RESULT();
4104
4105         *entries = rte_le_to_cpu_32(resp->entries);
4106         *length = rte_le_to_cpu_32(resp->entry_length);
4107
4108         HWRM_UNLOCK();
4109         return rc;
4110 }
4111
4112 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4113 {
4114         int rc;
4115         uint32_t dir_entries;
4116         uint32_t entry_length;
4117         uint8_t *buf;
4118         size_t buflen;
4119         rte_iova_t dma_handle;
4120         struct hwrm_nvm_get_dir_entries_input req = {0};
4121         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4122
4123         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4124         if (rc != 0)
4125                 return rc;
4126
4127         *data++ = dir_entries;
4128         *data++ = entry_length;
4129         len -= 2;
4130         memset(data, 0xff, len);
4131
4132         buflen = dir_entries * entry_length;
4133         buf = rte_malloc("nvm_dir", buflen, 0);
4134         if (buf == NULL)
4135                 return -ENOMEM;
4136         dma_handle = rte_malloc_virt2iova(buf);
4137         if (dma_handle == RTE_BAD_IOVA) {
4138                 PMD_DRV_LOG(ERR,
4139                         "unable to map response address to physical memory\n");
4140                 return -ENOMEM;
4141         }
4142         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4143         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4144         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4145
4146         if (rc == 0)
4147                 memcpy(data, buf, len > buflen ? buflen : len);
4148
4149         rte_free(buf);
4150         HWRM_CHECK_RESULT();
4151         HWRM_UNLOCK();
4152
4153         return rc;
4154 }
4155
4156 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4157                              uint32_t offset, uint32_t length,
4158                              uint8_t *data)
4159 {
4160         int rc;
4161         uint8_t *buf;
4162         rte_iova_t dma_handle;
4163         struct hwrm_nvm_read_input req = {0};
4164         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4165
4166         buf = rte_malloc("nvm_item", length, 0);
4167         if (!buf)
4168                 return -ENOMEM;
4169
4170         dma_handle = rte_malloc_virt2iova(buf);
4171         if (dma_handle == RTE_BAD_IOVA) {
4172                 PMD_DRV_LOG(ERR,
4173                         "unable to map response address to physical memory\n");
4174                 return -ENOMEM;
4175         }
4176         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4177         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4178         req.dir_idx = rte_cpu_to_le_16(index);
4179         req.offset = rte_cpu_to_le_32(offset);
4180         req.len = rte_cpu_to_le_32(length);
4181         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4182         if (rc == 0)
4183                 memcpy(data, buf, length);
4184
4185         rte_free(buf);
4186         HWRM_CHECK_RESULT();
4187         HWRM_UNLOCK();
4188
4189         return rc;
4190 }
4191
4192 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4193 {
4194         int rc;
4195         struct hwrm_nvm_erase_dir_entry_input req = {0};
4196         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4197
4198         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4199         req.dir_idx = rte_cpu_to_le_16(index);
4200         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4201         HWRM_CHECK_RESULT();
4202         HWRM_UNLOCK();
4203
4204         return rc;
4205 }
4206
4207
4208 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4209                           uint16_t dir_ordinal, uint16_t dir_ext,
4210                           uint16_t dir_attr, const uint8_t *data,
4211                           size_t data_len)
4212 {
4213         int rc;
4214         struct hwrm_nvm_write_input req = {0};
4215         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4216         rte_iova_t dma_handle;
4217         uint8_t *buf;
4218
4219         buf = rte_malloc("nvm_write", data_len, 0);
4220         if (!buf)
4221                 return -ENOMEM;
4222
4223         dma_handle = rte_malloc_virt2iova(buf);
4224         if (dma_handle == RTE_BAD_IOVA) {
4225                 PMD_DRV_LOG(ERR,
4226                         "unable to map response address to physical memory\n");
4227                 return -ENOMEM;
4228         }
4229         memcpy(buf, data, data_len);
4230
4231         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4232
4233         req.dir_type = rte_cpu_to_le_16(dir_type);
4234         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4235         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4236         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4237         req.dir_data_length = rte_cpu_to_le_32(data_len);
4238         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4239
4240         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4241
4242         rte_free(buf);
4243         HWRM_CHECK_RESULT();
4244         HWRM_UNLOCK();
4245
4246         return rc;
4247 }
4248
4249 static void
4250 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4251 {
4252         uint32_t *count = cbdata;
4253
4254         *count = *count + 1;
4255 }
4256
4257 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4258                                      struct bnxt_vnic_info *vnic __rte_unused)
4259 {
4260         return 0;
4261 }
4262
4263 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4264 {
4265         uint32_t count = 0;
4266
4267         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4268             &count, bnxt_vnic_count_hwrm_stub);
4269
4270         return count;
4271 }
4272
4273 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4274                                         uint16_t *vnic_ids)
4275 {
4276         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4277         struct hwrm_func_vf_vnic_ids_query_output *resp =
4278                                                 bp->hwrm_cmd_resp_addr;
4279         int rc;
4280
4281         /* First query all VNIC ids */
4282         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4283
4284         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4285         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4286         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4287
4288         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4289                 HWRM_UNLOCK();
4290                 PMD_DRV_LOG(ERR,
4291                 "unable to map VNIC ID table address to physical memory\n");
4292                 return -ENOMEM;
4293         }
4294         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4295         HWRM_CHECK_RESULT();
4296         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4297
4298         HWRM_UNLOCK();
4299
4300         return rc;
4301 }
4302
4303 /*
4304  * This function queries the VNIC IDs  for a specified VF. It then calls
4305  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4306  * Then it calls the hwrm_cb function to program this new vnic configuration.
4307  */
4308 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4309         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4310         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4311 {
4312         struct bnxt_vnic_info vnic;
4313         int rc = 0;
4314         int i, num_vnic_ids;
4315         uint16_t *vnic_ids;
4316         size_t vnic_id_sz;
4317         size_t sz;
4318
4319         /* First query all VNIC ids */
4320         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4321         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4322                         RTE_CACHE_LINE_SIZE);
4323         if (vnic_ids == NULL)
4324                 return -ENOMEM;
4325
4326         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4327                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4328
4329         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4330
4331         if (num_vnic_ids < 0)
4332                 return num_vnic_ids;
4333
4334         /* Retrieve VNIC, update bd_stall then update */
4335
4336         for (i = 0; i < num_vnic_ids; i++) {
4337                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4338                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4339                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4340                 if (rc)
4341                         break;
4342                 if (vnic.mru <= 4)      /* Indicates unallocated */
4343                         continue;
4344
4345                 vnic_cb(&vnic, cbdata);
4346
4347                 rc = hwrm_cb(bp, &vnic);
4348                 if (rc)
4349                         break;
4350         }
4351
4352         rte_free(vnic_ids);
4353
4354         return rc;
4355 }
4356
4357 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4358                                               bool on)
4359 {
4360         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4361         struct hwrm_func_cfg_input req = {0};
4362         int rc;
4363
4364         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4365
4366         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4367         req.enables |= rte_cpu_to_le_32(
4368                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4369         req.vlan_antispoof_mode = on ?
4370                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4371                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4372         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4373
4374         HWRM_CHECK_RESULT();
4375         HWRM_UNLOCK();
4376
4377         return rc;
4378 }
4379
4380 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4381 {
4382         struct bnxt_vnic_info vnic;
4383         uint16_t *vnic_ids;
4384         size_t vnic_id_sz;
4385         int num_vnic_ids, i;
4386         size_t sz;
4387         int rc;
4388
4389         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4390         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4391                         RTE_CACHE_LINE_SIZE);
4392         if (vnic_ids == NULL)
4393                 return -ENOMEM;
4394
4395         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4396                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4397
4398         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4399         if (rc <= 0)
4400                 goto exit;
4401         num_vnic_ids = rc;
4402
4403         /*
4404          * Loop through to find the default VNIC ID.
4405          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4406          * by sending the hwrm_func_qcfg command to the firmware.
4407          */
4408         for (i = 0; i < num_vnic_ids; i++) {
4409                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4410                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4411                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4412                                         bp->pf->first_vf_id + vf);
4413                 if (rc)
4414                         goto exit;
4415                 if (vnic.func_default) {
4416                         rte_free(vnic_ids);
4417                         return vnic.fw_vnic_id;
4418                 }
4419         }
4420         /* Could not find a default VNIC. */
4421         PMD_DRV_LOG(ERR, "No default VNIC\n");
4422 exit:
4423         rte_free(vnic_ids);
4424         return rc;
4425 }
4426
4427 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4428                          uint16_t dst_id,
4429                          struct bnxt_filter_info *filter)
4430 {
4431         int rc = 0;
4432         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4433         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4434         uint32_t enables = 0;
4435
4436         if (filter->fw_em_filter_id != UINT64_MAX)
4437                 bnxt_hwrm_clear_em_filter(bp, filter);
4438
4439         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4440
4441         req.flags = rte_cpu_to_le_32(filter->flags);
4442
4443         enables = filter->enables |
4444               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4445         req.dst_id = rte_cpu_to_le_16(dst_id);
4446
4447         if (filter->ip_addr_type) {
4448                 req.ip_addr_type = filter->ip_addr_type;
4449                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4450         }
4451         if (enables &
4452             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4453                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4454         if (enables &
4455             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4456                 memcpy(req.src_macaddr, filter->src_macaddr,
4457                        RTE_ETHER_ADDR_LEN);
4458         if (enables &
4459             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4460                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4461                        RTE_ETHER_ADDR_LEN);
4462         if (enables &
4463             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4464                 req.ovlan_vid = filter->l2_ovlan;
4465         if (enables &
4466             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4467                 req.ivlan_vid = filter->l2_ivlan;
4468         if (enables &
4469             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4470                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4471         if (enables &
4472             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4473                 req.ip_protocol = filter->ip_protocol;
4474         if (enables &
4475             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4476                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4477         if (enables &
4478             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4479                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4480         if (enables &
4481             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4482                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4483         if (enables &
4484             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4485                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4486         if (enables &
4487             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4488                 req.mirror_vnic_id = filter->mirror_vnic_id;
4489
4490         req.enables = rte_cpu_to_le_32(enables);
4491
4492         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4493
4494         HWRM_CHECK_RESULT();
4495
4496         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4497         HWRM_UNLOCK();
4498
4499         return rc;
4500 }
4501
4502 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4503 {
4504         int rc = 0;
4505         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4506         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4507
4508         if (filter->fw_em_filter_id == UINT64_MAX)
4509                 return 0;
4510
4511         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4512
4513         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4514
4515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4516
4517         HWRM_CHECK_RESULT();
4518         HWRM_UNLOCK();
4519
4520         filter->fw_em_filter_id = UINT64_MAX;
4521         filter->fw_l2_filter_id = UINT64_MAX;
4522
4523         return 0;
4524 }
4525
4526 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4527                          uint16_t dst_id,
4528                          struct bnxt_filter_info *filter)
4529 {
4530         int rc = 0;
4531         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4532         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4533                                                 bp->hwrm_cmd_resp_addr;
4534         uint32_t enables = 0;
4535
4536         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4537                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4538
4539         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4540
4541         req.flags = rte_cpu_to_le_32(filter->flags);
4542
4543         enables = filter->enables |
4544               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4545         req.dst_id = rte_cpu_to_le_16(dst_id);
4546
4547         if (filter->ip_addr_type) {
4548                 req.ip_addr_type = filter->ip_addr_type;
4549                 enables |=
4550                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4551         }
4552         if (enables &
4553             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4554                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4555         if (enables &
4556             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4557                 memcpy(req.src_macaddr, filter->src_macaddr,
4558                        RTE_ETHER_ADDR_LEN);
4559         if (enables &
4560             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4561                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4562         if (enables &
4563             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4564                 req.ip_protocol = filter->ip_protocol;
4565         if (enables &
4566             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4567                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4568         if (enables &
4569             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4570                 req.src_ipaddr_mask[0] =
4571                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4572         if (enables &
4573             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4574                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4575         if (enables &
4576             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4577                 req.dst_ipaddr_mask[0] =
4578                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4579         if (enables &
4580             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4581                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4582         if (enables &
4583             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4584                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4585         if (enables &
4586             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4587                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4588         if (enables &
4589             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4590                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4591         if (enables &
4592             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4593                 req.mirror_vnic_id = filter->mirror_vnic_id;
4594
4595         req.enables = rte_cpu_to_le_32(enables);
4596
4597         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4598
4599         HWRM_CHECK_RESULT();
4600
4601         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4602         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4603         HWRM_UNLOCK();
4604
4605         return rc;
4606 }
4607
4608 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4609                                 struct bnxt_filter_info *filter)
4610 {
4611         int rc = 0;
4612         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4613         struct hwrm_cfa_ntuple_filter_free_output *resp =
4614                                                 bp->hwrm_cmd_resp_addr;
4615
4616         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4617                 return 0;
4618
4619         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4620
4621         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4622
4623         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4624
4625         HWRM_CHECK_RESULT();
4626         HWRM_UNLOCK();
4627
4628         filter->fw_ntuple_filter_id = UINT64_MAX;
4629
4630         return 0;
4631 }
4632
4633 static int
4634 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4635 {
4636         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4637         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4638         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4639         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4640         uint16_t *ring_tbl = vnic->rss_table;
4641         int nr_ctxs = vnic->num_lb_ctxts;
4642         int max_rings = bp->rx_nr_rings;
4643         int i, j, k, cnt;
4644         int rc = 0;
4645
4646         for (i = 0, k = 0; i < nr_ctxs; i++) {
4647                 struct bnxt_rx_ring_info *rxr;
4648                 struct bnxt_cp_ring_info *cpr;
4649
4650                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4651
4652                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4653                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4654                 req.hash_mode_flags = vnic->hash_mode;
4655
4656                 req.ring_grp_tbl_addr =
4657                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4658                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4659                                      2 * sizeof(*ring_tbl));
4660                 req.hash_key_tbl_addr =
4661                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4662
4663                 req.ring_table_pair_index = i;
4664                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4665
4666                 for (j = 0; j < 64; j++) {
4667                         uint16_t ring_id;
4668
4669                         /* Find next active ring. */
4670                         for (cnt = 0; cnt < max_rings; cnt++) {
4671                                 if (rx_queue_state[k] !=
4672                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4673                                         break;
4674                                 if (++k == max_rings)
4675                                         k = 0;
4676                         }
4677
4678                         /* Return if no rings are active. */
4679                         if (cnt == max_rings) {
4680                                 HWRM_UNLOCK();
4681                                 return 0;
4682                         }
4683
4684                         /* Add rx/cp ring pair to RSS table. */
4685                         rxr = rxqs[k]->rx_ring;
4686                         cpr = rxqs[k]->cp_ring;
4687
4688                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4689                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4690                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4691                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4692
4693                         if (++k == max_rings)
4694                                 k = 0;
4695                 }
4696                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4697                                             BNXT_USE_CHIMP_MB);
4698
4699                 HWRM_CHECK_RESULT();
4700                 HWRM_UNLOCK();
4701         }
4702
4703         return rc;
4704 }
4705
4706 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4707 {
4708         unsigned int rss_idx, fw_idx, i;
4709
4710         if (!(vnic->rss_table && vnic->hash_type))
4711                 return 0;
4712
4713         if (BNXT_CHIP_THOR(bp))
4714                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4715
4716         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4717                 return 0;
4718
4719         if (vnic->rss_table && vnic->hash_type) {
4720                 /*
4721                  * Fill the RSS hash & redirection table with
4722                  * ring group ids for all VNICs
4723                  */
4724                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4725                         rss_idx++, fw_idx++) {
4726                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4727                                 fw_idx %= bp->rx_cp_nr_rings;
4728                                 if (vnic->fw_grp_ids[fw_idx] !=
4729                                     INVALID_HW_RING_ID)
4730                                         break;
4731                                 fw_idx++;
4732                         }
4733                         if (i == bp->rx_cp_nr_rings)
4734                                 return 0;
4735                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4736                 }
4737                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4738         }
4739
4740         return 0;
4741 }
4742
4743 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4744         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4745 {
4746         uint16_t flags;
4747
4748         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4749
4750         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4751         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4752
4753         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4754         req->num_cmpl_dma_aggr_during_int =
4755                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4756
4757         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4758
4759         /* min timer set to 1/2 of interrupt timer */
4760         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4761
4762         /* buf timer set to 1/4 of interrupt timer */
4763         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4764
4765         req->cmpl_aggr_dma_tmr_during_int =
4766                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4767
4768         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4769                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4770         req->flags = rte_cpu_to_le_16(flags);
4771 }
4772
4773 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4774                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4775 {
4776         struct hwrm_ring_aggint_qcaps_input req = {0};
4777         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4778         uint32_t enables;
4779         uint16_t flags;
4780         int rc;
4781
4782         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4783         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4784         HWRM_CHECK_RESULT();
4785
4786         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4787         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4788
4789         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4790                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4791         agg_req->flags = rte_cpu_to_le_16(flags);
4792         enables =
4793          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4794          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4795         agg_req->enables = rte_cpu_to_le_32(enables);
4796
4797         HWRM_UNLOCK();
4798         return rc;
4799 }
4800
4801 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4802                         struct bnxt_coal *coal, uint16_t ring_id)
4803 {
4804         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4805         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4806                                                 bp->hwrm_cmd_resp_addr;
4807         int rc;
4808
4809         /* Set ring coalesce parameters only for 100G NICs */
4810         if (BNXT_CHIP_THOR(bp)) {
4811                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4812                         return -1;
4813         } else if (bnxt_stratus_device(bp)) {
4814                 bnxt_hwrm_set_coal_params(coal, &req);
4815         } else {
4816                 return 0;
4817         }
4818
4819         HWRM_PREP(&req,
4820                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4821                   BNXT_USE_CHIMP_MB);
4822         req.ring_id = rte_cpu_to_le_16(ring_id);
4823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4824         HWRM_CHECK_RESULT();
4825         HWRM_UNLOCK();
4826         return 0;
4827 }
4828
4829 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4830 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4831 {
4832         struct hwrm_func_backing_store_qcaps_input req = {0};
4833         struct hwrm_func_backing_store_qcaps_output *resp =
4834                 bp->hwrm_cmd_resp_addr;
4835         struct bnxt_ctx_pg_info *ctx_pg;
4836         struct bnxt_ctx_mem_info *ctx;
4837         int total_alloc_len;
4838         int rc, i, tqm_rings;
4839
4840         if (!BNXT_CHIP_THOR(bp) ||
4841             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4842             BNXT_VF(bp) ||
4843             bp->ctx)
4844                 return 0;
4845
4846         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4847         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4848         HWRM_CHECK_RESULT_SILENT();
4849
4850         total_alloc_len = sizeof(*ctx);
4851         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4852                           RTE_CACHE_LINE_SIZE);
4853         if (!ctx) {
4854                 rc = -ENOMEM;
4855                 goto ctx_err;
4856         }
4857
4858         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4859         ctx->qp_min_qp1_entries =
4860                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4861         ctx->qp_max_l2_entries =
4862                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4863         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4864         ctx->srq_max_l2_entries =
4865                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4866         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4867         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4868         ctx->cq_max_l2_entries =
4869                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4870         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4871         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4872         ctx->vnic_max_vnic_entries =
4873                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4874         ctx->vnic_max_ring_table_entries =
4875                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4876         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4877         ctx->stat_max_entries =
4878                 rte_le_to_cpu_32(resp->stat_max_entries);
4879         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4880         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4881         ctx->tqm_min_entries_per_ring =
4882                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4883         ctx->tqm_max_entries_per_ring =
4884                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4885         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4886         if (!ctx->tqm_entries_multiple)
4887                 ctx->tqm_entries_multiple = 1;
4888         ctx->mrav_max_entries =
4889                 rte_le_to_cpu_32(resp->mrav_max_entries);
4890         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4891         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4892         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4893         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4894
4895         if (!ctx->tqm_fp_rings_count)
4896                 ctx->tqm_fp_rings_count = bp->max_q;
4897
4898         tqm_rings = ctx->tqm_fp_rings_count + 1;
4899
4900         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4901                             sizeof(*ctx_pg) * tqm_rings,
4902                             RTE_CACHE_LINE_SIZE);
4903         if (!ctx_pg) {
4904                 rc = -ENOMEM;
4905                 goto ctx_err;
4906         }
4907         for (i = 0; i < tqm_rings; i++, ctx_pg++)
4908                 ctx->tqm_mem[i] = ctx_pg;
4909
4910         bp->ctx = ctx;
4911 ctx_err:
4912         HWRM_UNLOCK();
4913         return rc;
4914 }
4915
4916 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4917 {
4918         struct hwrm_func_backing_store_cfg_input req = {0};
4919         struct hwrm_func_backing_store_cfg_output *resp =
4920                 bp->hwrm_cmd_resp_addr;
4921         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4922         struct bnxt_ctx_pg_info *ctx_pg;
4923         uint32_t *num_entries;
4924         uint64_t *pg_dir;
4925         uint8_t *pg_attr;
4926         uint32_t ena;
4927         int i, rc;
4928
4929         if (!ctx)
4930                 return 0;
4931
4932         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4933         req.enables = rte_cpu_to_le_32(enables);
4934
4935         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4936                 ctx_pg = &ctx->qp_mem;
4937                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4938                 req.qp_num_qp1_entries =
4939                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4940                 req.qp_num_l2_entries =
4941                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4942                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4943                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4944                                       &req.qpc_pg_size_qpc_lvl,
4945                                       &req.qpc_page_dir);
4946         }
4947
4948         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4949                 ctx_pg = &ctx->srq_mem;
4950                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4951                 req.srq_num_l2_entries =
4952                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4953                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4954                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4955                                       &req.srq_pg_size_srq_lvl,
4956                                       &req.srq_page_dir);
4957         }
4958
4959         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4960                 ctx_pg = &ctx->cq_mem;
4961                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4962                 req.cq_num_l2_entries =
4963                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4964                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4965                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4966                                       &req.cq_pg_size_cq_lvl,
4967                                       &req.cq_page_dir);
4968         }
4969
4970         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4971                 ctx_pg = &ctx->vnic_mem;
4972                 req.vnic_num_vnic_entries =
4973                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4974                 req.vnic_num_ring_table_entries =
4975                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4976                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4977                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4978                                       &req.vnic_pg_size_vnic_lvl,
4979                                       &req.vnic_page_dir);
4980         }
4981
4982         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4983                 ctx_pg = &ctx->stat_mem;
4984                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4985                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4986                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4987                                       &req.stat_pg_size_stat_lvl,
4988                                       &req.stat_page_dir);
4989         }
4990
4991         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4992         num_entries = &req.tqm_sp_num_entries;
4993         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4994         pg_dir = &req.tqm_sp_page_dir;
4995         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4996         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4997                 if (!(enables & ena))
4998                         continue;
4999
5000                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5001
5002                 ctx_pg = ctx->tqm_mem[i];
5003                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5004                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5005         }
5006
5007         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5008         HWRM_CHECK_RESULT();
5009         HWRM_UNLOCK();
5010
5011         return rc;
5012 }
5013
5014 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5015 {
5016         struct hwrm_port_qstats_ext_input req = {0};
5017         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5018         struct bnxt_pf_info *pf = bp->pf;
5019         int rc;
5020
5021         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5022               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5023                 return 0;
5024
5025         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5026
5027         req.port_id = rte_cpu_to_le_16(pf->port_id);
5028         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5029                 req.tx_stat_host_addr =
5030                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5031                 req.tx_stat_size =
5032                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5033         }
5034         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5035                 req.rx_stat_host_addr =
5036                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5037                 req.rx_stat_size =
5038                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5039         }
5040         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5041
5042         if (rc) {
5043                 bp->fw_rx_port_stats_ext_size = 0;
5044                 bp->fw_tx_port_stats_ext_size = 0;
5045         } else {
5046                 bp->fw_rx_port_stats_ext_size =
5047                         rte_le_to_cpu_16(resp->rx_stat_size);
5048                 bp->fw_tx_port_stats_ext_size =
5049                         rte_le_to_cpu_16(resp->tx_stat_size);
5050         }
5051
5052         HWRM_CHECK_RESULT();
5053         HWRM_UNLOCK();
5054
5055         return rc;
5056 }
5057
5058 int
5059 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5060 {
5061         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5062         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5063                 bp->hwrm_cmd_resp_addr;
5064         int rc = 0;
5065
5066         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5067         req.tunnel_type = type;
5068         req.dest_fid = bp->fw_fid;
5069         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5070         HWRM_CHECK_RESULT();
5071
5072         HWRM_UNLOCK();
5073
5074         return rc;
5075 }
5076
5077 int
5078 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5079 {
5080         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5081         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5082                 bp->hwrm_cmd_resp_addr;
5083         int rc = 0;
5084
5085         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5086         req.tunnel_type = type;
5087         req.dest_fid = bp->fw_fid;
5088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5089         HWRM_CHECK_RESULT();
5090
5091         HWRM_UNLOCK();
5092
5093         return rc;
5094 }
5095
5096 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5097 {
5098         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5099         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5100                 bp->hwrm_cmd_resp_addr;
5101         int rc = 0;
5102
5103         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5104         req.src_fid = bp->fw_fid;
5105         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5106         HWRM_CHECK_RESULT();
5107
5108         if (type)
5109                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5110
5111         HWRM_UNLOCK();
5112
5113         return rc;
5114 }
5115
5116 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5117                                    uint16_t *dst_fid)
5118 {
5119         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5120         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5121                 bp->hwrm_cmd_resp_addr;
5122         int rc = 0;
5123
5124         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5125         req.src_fid = bp->fw_fid;
5126         req.tunnel_type = tun_type;
5127         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5128         HWRM_CHECK_RESULT();
5129
5130         if (dst_fid)
5131                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5132
5133         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5134
5135         HWRM_UNLOCK();
5136
5137         return rc;
5138 }
5139
5140 int bnxt_hwrm_set_mac(struct bnxt *bp)
5141 {
5142         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5143         struct hwrm_func_vf_cfg_input req = {0};
5144         int rc = 0;
5145
5146         if (!BNXT_VF(bp))
5147                 return 0;
5148
5149         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5150
5151         req.enables =
5152                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5153         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5154
5155         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5156
5157         HWRM_CHECK_RESULT();
5158
5159         HWRM_UNLOCK();
5160
5161         return rc;
5162 }
5163
5164 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5165 {
5166         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5167         struct hwrm_func_drv_if_change_input req = {0};
5168         uint32_t flags;
5169         int rc;
5170
5171         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5172                 return 0;
5173
5174         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5175          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5176          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5177          */
5178         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5179                 return 0;
5180
5181         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5182
5183         if (up)
5184                 req.flags =
5185                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5186
5187         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5188
5189         HWRM_CHECK_RESULT();
5190         flags = rte_le_to_cpu_32(resp->flags);
5191         HWRM_UNLOCK();
5192
5193         if (!up)
5194                 return 0;
5195
5196         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5197                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5198                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5199         }
5200
5201         return 0;
5202 }
5203
5204 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5205 {
5206         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5207         struct bnxt_error_recovery_info *info = bp->recovery_info;
5208         struct hwrm_error_recovery_qcfg_input req = {0};
5209         uint32_t flags = 0;
5210         unsigned int i;
5211         int rc;
5212
5213         /* Older FW does not have error recovery support */
5214         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5215                 return 0;
5216
5217         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5218
5219         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5220
5221         HWRM_CHECK_RESULT();
5222
5223         flags = rte_le_to_cpu_32(resp->flags);
5224         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5225                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5226         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5227                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5228
5229         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5230             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5231                 rc = -EINVAL;
5232                 goto err;
5233         }
5234
5235         /* FW returned values are in units of 100msec */
5236         info->driver_polling_freq =
5237                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5238         info->master_func_wait_period =
5239                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5240         info->normal_func_wait_period =
5241                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5242         info->master_func_wait_period_after_reset =
5243                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5244         info->max_bailout_time_after_reset =
5245                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5246         info->status_regs[BNXT_FW_STATUS_REG] =
5247                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5248         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5249                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5250         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5251                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5252         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5253                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5254         info->reg_array_cnt =
5255                 rte_le_to_cpu_32(resp->reg_array_cnt);
5256
5257         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5258                 rc = -EINVAL;
5259                 goto err;
5260         }
5261
5262         for (i = 0; i < info->reg_array_cnt; i++) {
5263                 info->reset_reg[i] =
5264                         rte_le_to_cpu_32(resp->reset_reg[i]);
5265                 info->reset_reg_val[i] =
5266                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5267                 info->delay_after_reset[i] =
5268                         resp->delay_after_reset[i];
5269         }
5270 err:
5271         HWRM_UNLOCK();
5272
5273         /* Map the FW status registers */
5274         if (!rc)
5275                 rc = bnxt_map_fw_health_status_regs(bp);
5276
5277         if (rc) {
5278                 rte_free(bp->recovery_info);
5279                 bp->recovery_info = NULL;
5280         }
5281         return rc;
5282 }
5283
5284 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5285 {
5286         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5287         struct hwrm_fw_reset_input req = {0};
5288         int rc;
5289
5290         if (!BNXT_PF(bp))
5291                 return -EOPNOTSUPP;
5292
5293         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5294
5295         req.embedded_proc_type =
5296                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5297         req.selfrst_status =
5298                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5299         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5300
5301         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5302                                     BNXT_USE_KONG(bp));
5303
5304         HWRM_CHECK_RESULT();
5305         HWRM_UNLOCK();
5306
5307         return rc;
5308 }
5309
5310 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5311 {
5312         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5313         struct hwrm_port_ts_query_input req = {0};
5314         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5315         uint32_t flags = 0;
5316         int rc;
5317
5318         if (!ptp)
5319                 return 0;
5320
5321         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5322
5323         switch (path) {
5324         case BNXT_PTP_FLAGS_PATH_TX:
5325                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5326                 break;
5327         case BNXT_PTP_FLAGS_PATH_RX:
5328                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5329                 break;
5330         case BNXT_PTP_FLAGS_CURRENT_TIME:
5331                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5332                 break;
5333         }
5334
5335         req.flags = rte_cpu_to_le_32(flags);
5336         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5337
5338         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5339
5340         HWRM_CHECK_RESULT();
5341
5342         if (timestamp) {
5343                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5344                 *timestamp |=
5345                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5346         }
5347         HWRM_UNLOCK();
5348
5349         return rc;
5350 }
5351
5352 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5353 {
5354         int rc = 0;
5355
5356         struct hwrm_cfa_counter_qcaps_input req = {0};
5357         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5358
5359         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5360                 PMD_DRV_LOG(DEBUG,
5361                             "Not a PF or trusted VF. Command not supported\n");
5362                 return 0;
5363         }
5364
5365         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5366         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5367         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5368
5369         HWRM_CHECK_RESULT();
5370         if (max_fc)
5371                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5372         HWRM_UNLOCK();
5373
5374         return 0;
5375 }
5376
5377 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5378 {
5379         int rc = 0;
5380         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5381         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5382
5383         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5384                 PMD_DRV_LOG(DEBUG,
5385                             "Not a PF or trusted VF. Command not supported\n");
5386                 return 0;
5387         }
5388
5389         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5390
5391         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5392         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5393         req.page_dir = rte_cpu_to_le_64(dma_addr);
5394
5395         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5396
5397         HWRM_CHECK_RESULT();
5398         if (ctx_id) {
5399                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5400                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5401         }
5402         HWRM_UNLOCK();
5403
5404         return 0;
5405 }
5406
5407 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5408 {
5409         int rc = 0;
5410         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5411         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5412
5413         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5414                 PMD_DRV_LOG(DEBUG,
5415                             "Not a PF or trusted VF. Command not supported\n");
5416                 return 0;
5417         }
5418
5419         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5420
5421         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5422
5423         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5424
5425         HWRM_CHECK_RESULT();
5426         HWRM_UNLOCK();
5427
5428         return rc;
5429 }
5430
5431 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5432                               uint16_t cntr, uint16_t ctx_id,
5433                               uint32_t num_entries, bool enable)
5434 {
5435         struct hwrm_cfa_counter_cfg_input req = {0};
5436         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5437         uint16_t flags = 0;
5438         int rc;
5439
5440         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5441                 PMD_DRV_LOG(DEBUG,
5442                             "Not a PF or trusted VF. Command not supported\n");
5443                 return 0;
5444         }
5445
5446         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5447
5448         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5449         req.counter_type = rte_cpu_to_le_16(cntr);
5450         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5451                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5452         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5453         if (dir == BNXT_DIR_RX)
5454                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5455         else if (dir == BNXT_DIR_TX)
5456                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5457         req.flags = rte_cpu_to_le_16(flags);
5458         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5459         req.num_entries = rte_cpu_to_le_32(num_entries);
5460
5461         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5462         HWRM_CHECK_RESULT();
5463         HWRM_UNLOCK();
5464
5465         return 0;
5466 }
5467
5468 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5469                                  enum bnxt_flow_dir dir,
5470                                  uint16_t cntr,
5471                                  uint16_t num_entries)
5472 {
5473         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5474         struct hwrm_cfa_counter_qstats_input req = {0};
5475         uint16_t flow_ctx_id = 0;
5476         uint16_t flags = 0;
5477         int rc = 0;
5478
5479         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5480                 PMD_DRV_LOG(DEBUG,
5481                             "Not a PF or trusted VF. Command not supported\n");
5482                 return 0;
5483         }
5484
5485         if (dir == BNXT_DIR_RX) {
5486                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5487                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5488         } else if (dir == BNXT_DIR_TX) {
5489                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5490                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5491         }
5492
5493         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5494         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5495         req.counter_type = rte_cpu_to_le_16(cntr);
5496         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5497         req.num_entries = rte_cpu_to_le_16(num_entries);
5498         req.flags = rte_cpu_to_le_16(flags);
5499         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5500
5501         HWRM_CHECK_RESULT();
5502         HWRM_UNLOCK();
5503
5504         return 0;
5505 }
5506
5507 int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx)
5508 {
5509         struct hwrm_cfa_vfr_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5510         struct hwrm_cfa_vfr_alloc_input req = {0};
5511         int rc;
5512
5513         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5514                 PMD_DRV_LOG(DEBUG,
5515                             "Not a PF or trusted VF. Command not supported\n");
5516                 return 0;
5517         }
5518
5519         HWRM_PREP(&req, HWRM_CFA_VFR_ALLOC, BNXT_USE_CHIMP_MB);
5520         req.vf_id = rte_cpu_to_le_16(vf_idx);
5521         snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5522                  bp->eth_dev->data->name, vf_idx);
5523
5524         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5525         HWRM_CHECK_RESULT();
5526
5527         HWRM_UNLOCK();
5528         PMD_DRV_LOG(DEBUG, "VFR %d allocated\n", vf_idx);
5529         return rc;
5530 }
5531
5532 int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx)
5533 {
5534         struct hwrm_cfa_vfr_free_output *resp = bp->hwrm_cmd_resp_addr;
5535         struct hwrm_cfa_vfr_free_input req = {0};
5536         int rc;
5537
5538         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5539                 PMD_DRV_LOG(DEBUG,
5540                             "Not a PF or trusted VF. Command not supported\n");
5541                 return 0;
5542         }
5543
5544         HWRM_PREP(&req, HWRM_CFA_VFR_FREE, BNXT_USE_CHIMP_MB);
5545         req.vf_id = rte_cpu_to_le_16(vf_idx);
5546         snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5547                  bp->eth_dev->data->name, vf_idx);
5548
5549         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5550         HWRM_CHECK_RESULT();
5551         HWRM_UNLOCK();
5552         PMD_DRV_LOG(DEBUG, "VFR %d freed\n", vf_idx);
5553         return rc;
5554 }