4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <rte_byteorder.h>
37 #include <rte_common.h>
38 #include <rte_cycles.h>
39 #include <rte_malloc.h>
40 #include <rte_memzone.h>
41 #include <rte_version.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
49 #include "bnxt_ring.h"
52 #include "bnxt_vnic.h"
53 #include "hsi_struct_def_dpdk.h"
57 #define HWRM_CMD_TIMEOUT 10000
59 struct bnxt_plcmodes_cfg {
61 uint16_t jumbo_thresh;
63 uint16_t hds_threshold;
66 static int page_getenum(size_t size)
82 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
83 return sizeof(void *) * 8 - 1;
86 static int page_roundup(size_t size)
88 return 1 << page_getenum(size);
92 * HWRM Functions (sent to HWRM)
93 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
94 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
95 * command was failed by the ChiMP.
98 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
102 struct input *req = msg;
103 struct output *resp = bp->hwrm_cmd_resp_addr;
104 uint32_t *data = msg;
107 uint16_t max_req_len = bp->max_req_len;
108 struct hwrm_short_input short_input = { 0 };
110 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
111 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
113 memset(short_cmd_req, 0, bp->max_req_len);
114 memcpy(short_cmd_req, req, msg_len);
116 short_input.req_type = rte_cpu_to_le_16(req->req_type);
117 short_input.signature = rte_cpu_to_le_16(
118 HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
119 short_input.size = rte_cpu_to_le_16(msg_len);
120 short_input.req_addr =
121 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
123 data = (uint32_t *)&short_input;
124 msg_len = sizeof(short_input);
126 /* Sync memory write before updating doorbell */
129 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
132 /* Write request msg to hwrm channel */
133 for (i = 0; i < msg_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + i;
135 rte_write32(*data, bar);
139 /* Zero the rest of the request space */
140 for (; i < max_req_len; i += 4) {
141 bar = (uint8_t *)bp->bar0 + i;
145 /* Ring channel doorbell */
146 bar = (uint8_t *)bp->bar0 + 0x100;
149 /* Poll for the valid bit */
150 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
151 /* Sanity check on the resp->resp_len */
153 if (resp->resp_len && resp->resp_len <=
155 /* Last byte of resp contains the valid key */
156 valid = (uint8_t *)resp + resp->resp_len - 1;
157 if (*valid == HWRM_RESP_VALID_KEY)
163 if (i >= HWRM_CMD_TIMEOUT) {
164 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
175 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
176 * spinlock, and does initial processing.
178 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
179 * releases the spinlock only if it returns. If the regular int return codes
180 * are not used by the function, HWRM_CHECK_RESULT() should not be used
181 * directly, rather it should be copied and modified to suit the function.
183 * HWRM_UNLOCK() must be called after all response processing is completed.
185 #define HWRM_PREP(req, type) do { \
186 rte_spinlock_lock(&bp->hwrm_lock); \
187 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
188 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
189 req.cmpl_ring = rte_cpu_to_le_16(-1); \
190 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
191 req.target_id = rte_cpu_to_le_16(0xffff); \
192 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
195 #define HWRM_CHECK_RESULT() do {\
197 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
198 rte_spinlock_unlock(&bp->hwrm_lock); \
201 if (resp->error_code) { \
202 rc = rte_le_to_cpu_16(resp->error_code); \
203 if (resp->resp_len >= 16) { \
204 struct hwrm_err_output *tmp_hwrm_err_op = \
207 "error %d:%d:%08x:%04x\n", \
208 rc, tmp_hwrm_err_op->cmd_err, \
210 tmp_hwrm_err_op->opaque_0), \
212 tmp_hwrm_err_op->opaque_1)); \
214 PMD_DRV_LOG(ERR, "error %d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
221 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
223 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
226 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
227 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
229 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
230 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
233 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
241 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
242 struct bnxt_vnic_info *vnic,
244 struct bnxt_vlan_table_entry *vlan_table)
247 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
248 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
251 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
252 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
254 /* FIXME add multicast flag, when multicast adding options is supported
257 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
258 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
259 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
260 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
261 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
262 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
263 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
264 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
265 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
266 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
267 if (vnic->mc_addr_cnt) {
268 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
269 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
270 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
273 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
274 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
275 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
276 rte_mem_virt2iova(vlan_table));
277 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
279 req.mask = rte_cpu_to_le_32(mask);
281 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
289 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
291 struct bnxt_vlan_antispoof_table_entry *vlan_table)
294 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
295 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
296 bp->hwrm_cmd_resp_addr;
299 * Older HWRM versions did not support this command, and the set_rx_mask
300 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
301 * removed from set_rx_mask call, and this command was added.
303 * This command is also present from 1.7.8.11 and higher,
306 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
307 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
308 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
313 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
314 req.fid = rte_cpu_to_le_16(fid);
316 req.vlan_tag_mask_tbl_addr =
317 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
318 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
320 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
328 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
329 struct bnxt_filter_info *filter)
332 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
333 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
335 if (filter->fw_l2_filter_id == UINT64_MAX)
338 HWRM_PREP(req, CFA_L2_FILTER_FREE);
340 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
342 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
347 filter->fw_l2_filter_id = -1;
352 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
354 struct bnxt_filter_info *filter)
357 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
358 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
359 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
360 const struct rte_eth_vmdq_rx_conf *conf =
361 &dev_conf->rx_adv_conf.vmdq_rx_conf;
362 uint32_t enables = 0;
363 uint16_t j = dst_id - 1;
365 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
366 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
367 conf->pool_map[j].pools & (1UL << j)) {
369 "Add vlan %u to vmdq pool %u\n",
370 conf->pool_map[j].vlan_id, j);
372 filter->l2_ivlan = conf->pool_map[j].vlan_id;
374 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
375 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
378 if (filter->fw_l2_filter_id != UINT64_MAX)
379 bnxt_hwrm_clear_l2_filter(bp, filter);
381 HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
383 req.flags = rte_cpu_to_le_32(filter->flags);
385 enables = filter->enables |
386 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
387 req.dst_id = rte_cpu_to_le_16(dst_id);
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
391 memcpy(req.l2_addr, filter->l2_addr,
394 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
395 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
398 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
399 req.l2_ovlan = filter->l2_ovlan;
401 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
402 req.l2_ovlan = filter->l2_ivlan;
404 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
405 req.l2_ovlan_mask = filter->l2_ovlan_mask;
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
408 req.l2_ovlan_mask = filter->l2_ivlan_mask;
409 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
410 req.src_id = rte_cpu_to_le_32(filter->src_id);
411 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
412 req.src_type = filter->src_type;
414 req.enables = rte_cpu_to_le_32(enables);
416 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
420 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
426 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
428 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
429 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
436 HWRM_PREP(req, PORT_MAC_CFG);
439 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
441 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
442 if (ptp->tx_tstamp_en)
443 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
445 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
446 req.flags = rte_cpu_to_le_32(flags);
448 rte_cpu_to_le_32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
449 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
451 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
457 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
460 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
461 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
462 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
464 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
468 HWRM_PREP(req, PORT_MAC_PTP_QCFG);
470 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
472 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
476 if (!(resp->flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS))
479 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
483 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
484 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
485 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
486 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
487 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
488 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
489 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
490 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
491 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
492 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
493 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
494 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
495 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
496 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
497 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
498 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
499 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
500 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
508 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
511 struct hwrm_func_qcaps_input req = {.req_type = 0 };
512 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
513 uint16_t new_max_vfs;
517 HWRM_PREP(req, FUNC_QCAPS);
519 req.fid = rte_cpu_to_le_16(0xffff);
521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
525 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
526 flags = rte_le_to_cpu_32(resp->flags);
528 bp->pf.port_id = resp->port_id;
529 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
530 new_max_vfs = bp->pdev->max_vfs;
531 if (new_max_vfs != bp->pf.max_vfs) {
533 rte_free(bp->pf.vf_info);
534 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
535 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
536 bp->pf.max_vfs = new_max_vfs;
537 for (i = 0; i < new_max_vfs; i++) {
538 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
539 bp->pf.vf_info[i].vlan_table =
540 rte_zmalloc("VF VLAN table",
543 if (bp->pf.vf_info[i].vlan_table == NULL)
545 "Fail to alloc VLAN table for VF %d\n",
549 bp->pf.vf_info[i].vlan_table);
550 bp->pf.vf_info[i].vlan_as_table =
551 rte_zmalloc("VF VLAN AS table",
554 if (bp->pf.vf_info[i].vlan_as_table == NULL)
556 "Alloc VLAN AS table for VF %d fail\n",
560 bp->pf.vf_info[i].vlan_as_table);
561 STAILQ_INIT(&bp->pf.vf_info[i].filter);
566 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
567 memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
568 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
569 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
570 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
571 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
572 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
573 /* TODO: For now, do not support VMDq/RFS on VFs. */
578 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
582 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
584 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
585 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
586 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
587 PMD_DRV_LOG(INFO, "PTP SUPPORTED\n");
589 bnxt_hwrm_ptp_qcfg(bp);
598 int bnxt_hwrm_func_reset(struct bnxt *bp)
601 struct hwrm_func_reset_input req = {.req_type = 0 };
602 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
604 HWRM_PREP(req, FUNC_RESET);
606 req.enables = rte_cpu_to_le_32(0);
608 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
616 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
619 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
620 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
622 if (bp->flags & BNXT_FLAG_REGISTERED)
625 HWRM_PREP(req, FUNC_DRV_RGTR);
626 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
627 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
628 req.ver_maj = RTE_VER_YEAR;
629 req.ver_min = RTE_VER_MONTH;
630 req.ver_upd = RTE_VER_MINOR;
633 req.enables |= rte_cpu_to_le_32(
634 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
635 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
636 RTE_MIN(sizeof(req.vf_req_fwd),
637 sizeof(bp->pf.vf_req_fwd)));
640 req.async_event_fwd[0] |=
641 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
642 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
643 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
644 req.async_event_fwd[1] |=
645 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
646 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
648 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
653 bp->flags |= BNXT_FLAG_REGISTERED;
658 int bnxt_hwrm_ver_get(struct bnxt *bp)
661 struct hwrm_ver_get_input req = {.req_type = 0 };
662 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
665 uint16_t max_resp_len;
666 char type[RTE_MEMZONE_NAMESIZE];
667 uint32_t dev_caps_cfg;
669 bp->max_req_len = HWRM_MAX_REQ_LEN;
670 HWRM_PREP(req, VER_GET);
672 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
673 req.hwrm_intf_min = HWRM_VERSION_MINOR;
674 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
676 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
680 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
681 resp->hwrm_intf_maj, resp->hwrm_intf_min,
683 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
684 bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
685 (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
686 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
687 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
689 my_version = HWRM_VERSION_MAJOR << 16;
690 my_version |= HWRM_VERSION_MINOR << 8;
691 my_version |= HWRM_VERSION_UPDATE;
693 fw_version = resp->hwrm_intf_maj << 16;
694 fw_version |= resp->hwrm_intf_min << 8;
695 fw_version |= resp->hwrm_intf_upd;
697 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
698 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
703 if (my_version != fw_version) {
704 PMD_DRV_LOG(INFO, "BNXT Driver/HWRM API mismatch.\n");
705 if (my_version < fw_version) {
707 "Firmware API version is newer than driver.\n");
709 "The driver may be missing features.\n");
712 "Firmware API version is older than driver.\n");
714 "Not all driver features may be functional.\n");
718 if (bp->max_req_len > resp->max_req_win_len) {
719 PMD_DRV_LOG(ERR, "Unsupported request length\n");
722 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
723 max_resp_len = resp->max_resp_len;
724 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
726 if (bp->max_resp_len != max_resp_len) {
727 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
728 bp->pdev->addr.domain, bp->pdev->addr.bus,
729 bp->pdev->addr.devid, bp->pdev->addr.function);
731 rte_free(bp->hwrm_cmd_resp_addr);
733 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
734 if (bp->hwrm_cmd_resp_addr == NULL) {
738 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
739 bp->hwrm_cmd_resp_dma_addr =
740 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
741 if (bp->hwrm_cmd_resp_dma_addr == 0) {
743 "Unable to map response buffer to physical memory.\n");
747 bp->max_resp_len = max_resp_len;
751 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
753 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
754 PMD_DRV_LOG(DEBUG, "Short command supported\n");
756 rte_free(bp->hwrm_short_cmd_req_addr);
758 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
760 if (bp->hwrm_short_cmd_req_addr == NULL) {
764 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
765 bp->hwrm_short_cmd_req_dma_addr =
766 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
767 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
768 rte_free(bp->hwrm_short_cmd_req_addr);
770 "Unable to map buffer to physical memory.\n");
775 bp->flags |= BNXT_FLAG_SHORT_CMD;
783 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
786 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
787 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
789 if (!(bp->flags & BNXT_FLAG_REGISTERED))
792 HWRM_PREP(req, FUNC_DRV_UNRGTR);
795 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
800 bp->flags &= ~BNXT_FLAG_REGISTERED;
805 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
808 struct hwrm_port_phy_cfg_input req = {0};
809 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
810 uint32_t enables = 0;
812 HWRM_PREP(req, PORT_PHY_CFG);
815 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
816 if (bp->link_info.auto_mode && conf->link_speed) {
817 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
818 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
821 req.flags = rte_cpu_to_le_32(conf->phy_flags);
822 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
823 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
825 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
826 * any auto mode, even "none".
828 if (!conf->link_speed) {
829 /* No speeds specified. Enable AutoNeg - all speeds */
831 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
833 /* AutoNeg - Advertise speeds specified. */
834 if (conf->auto_link_speed_mask) {
836 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
837 req.auto_link_speed_mask =
838 conf->auto_link_speed_mask;
840 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
843 req.auto_duplex = conf->duplex;
844 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
845 req.auto_pause = conf->auto_pause;
846 req.force_pause = conf->force_pause;
847 /* Set force_pause if there is no auto or if there is a force */
848 if (req.auto_pause && !req.force_pause)
849 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
851 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
853 req.enables = rte_cpu_to_le_32(enables);
856 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
857 PMD_DRV_LOG(INFO, "Force Link Down\n");
860 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
868 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
869 struct bnxt_link_info *link_info)
872 struct hwrm_port_phy_qcfg_input req = {0};
873 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
875 HWRM_PREP(req, PORT_PHY_QCFG);
877 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
881 link_info->phy_link_status = resp->link;
883 (link_info->phy_link_status ==
884 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
885 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
886 link_info->duplex = resp->duplex_cfg;
887 link_info->pause = resp->pause;
888 link_info->auto_pause = resp->auto_pause;
889 link_info->force_pause = resp->force_pause;
890 link_info->auto_mode = resp->auto_mode;
891 link_info->phy_type = resp->phy_type;
892 link_info->media_type = resp->media_type;
894 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
895 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
896 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
897 link_info->phy_ver[0] = resp->phy_maj;
898 link_info->phy_ver[1] = resp->phy_min;
899 link_info->phy_ver[2] = resp->phy_bld;
906 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
909 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
910 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
912 HWRM_PREP(req, QUEUE_QPORTCFG);
914 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
918 #define GET_QUEUE_INFO(x) \
919 bp->cos_queue[x].id = resp->queue_id##x; \
920 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
936 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
937 struct bnxt_ring *ring,
938 uint32_t ring_type, uint32_t map_index,
939 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
942 uint32_t enables = 0;
943 struct hwrm_ring_alloc_input req = {.req_type = 0 };
944 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
946 HWRM_PREP(req, RING_ALLOC);
948 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
949 req.fbo = rte_cpu_to_le_32(0);
950 /* Association of ring index with doorbell index */
951 req.logical_id = rte_cpu_to_le_16(map_index);
952 req.length = rte_cpu_to_le_32(ring->ring_size);
955 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
956 req.queue_id = bp->cos_queue[0].id;
958 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
959 req.ring_type = ring_type;
960 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
961 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
962 if (stats_ctx_id != INVALID_STATS_CTX_ID)
964 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
966 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
967 req.ring_type = ring_type;
969 * TODO: Some HWRM versions crash with
970 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
972 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
975 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
980 req.enables = rte_cpu_to_le_32(enables);
982 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
984 if (rc || resp->error_code) {
985 if (rc == 0 && resp->error_code)
986 rc = rte_le_to_cpu_16(resp->error_code);
988 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
990 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
993 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
995 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
998 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1000 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1004 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1010 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1015 int bnxt_hwrm_ring_free(struct bnxt *bp,
1016 struct bnxt_ring *ring, uint32_t ring_type)
1019 struct hwrm_ring_free_input req = {.req_type = 0 };
1020 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1022 HWRM_PREP(req, RING_FREE);
1024 req.ring_type = ring_type;
1025 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1027 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1029 if (rc || resp->error_code) {
1030 if (rc == 0 && resp->error_code)
1031 rc = rte_le_to_cpu_16(resp->error_code);
1034 switch (ring_type) {
1035 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1036 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1039 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1040 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1043 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1044 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1048 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1056 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1059 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1060 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1062 HWRM_PREP(req, RING_GRP_ALLOC);
1064 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1065 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1066 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1067 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1069 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1071 HWRM_CHECK_RESULT();
1073 bp->grp_info[idx].fw_grp_id =
1074 rte_le_to_cpu_16(resp->ring_group_id);
1081 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1084 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1085 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1087 HWRM_PREP(req, RING_GRP_FREE);
1089 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1091 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1093 HWRM_CHECK_RESULT();
1096 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1100 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1103 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1104 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1106 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1109 HWRM_PREP(req, STAT_CTX_CLR_STATS);
1111 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1113 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1115 HWRM_CHECK_RESULT();
1121 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1122 unsigned int idx __rte_unused)
1125 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1126 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1128 HWRM_PREP(req, STAT_CTX_ALLOC);
1130 req.update_period_ms = rte_cpu_to_le_32(0);
1132 req.stats_dma_addr =
1133 rte_cpu_to_le_64(cpr->hw_stats_map);
1135 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1137 HWRM_CHECK_RESULT();
1139 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1146 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1147 unsigned int idx __rte_unused)
1150 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1151 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1153 HWRM_PREP(req, STAT_CTX_FREE);
1155 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1157 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1159 HWRM_CHECK_RESULT();
1165 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1168 struct hwrm_vnic_alloc_input req = { 0 };
1169 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1171 /* map ring groups to this vnic */
1172 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1173 vnic->start_grp_id, vnic->end_grp_id);
1174 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1175 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1176 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1177 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1178 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1179 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1180 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1181 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1182 HWRM_PREP(req, VNIC_ALLOC);
1184 if (vnic->func_default)
1185 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
1186 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1188 HWRM_CHECK_RESULT();
1190 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1192 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1196 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1197 struct bnxt_vnic_info *vnic,
1198 struct bnxt_plcmodes_cfg *pmode)
1201 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1202 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1204 HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1206 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1208 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1210 HWRM_CHECK_RESULT();
1212 pmode->flags = rte_le_to_cpu_32(resp->flags);
1213 /* dflt_vnic bit doesn't exist in the _cfg command */
1214 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1215 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1216 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1217 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1224 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1225 struct bnxt_vnic_info *vnic,
1226 struct bnxt_plcmodes_cfg *pmode)
1229 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1230 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1232 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1234 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1235 req.flags = rte_cpu_to_le_32(pmode->flags);
1236 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1237 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1238 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1239 req.enables = rte_cpu_to_le_32(
1240 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1241 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1242 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1247 HWRM_CHECK_RESULT();
1253 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1256 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1257 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1258 uint32_t ctx_enable_flag = 0;
1259 struct bnxt_plcmodes_cfg pmodes;
1261 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1262 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1266 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1270 HWRM_PREP(req, VNIC_CFG);
1272 /* Only RSS support for now TBD: COS & LB */
1274 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1275 if (vnic->lb_rule != 0xffff)
1276 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1277 if (vnic->cos_rule != 0xffff)
1278 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1279 if (vnic->rss_rule != 0xffff) {
1280 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1281 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1283 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1284 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1285 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1286 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1287 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1288 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1289 req.mru = rte_cpu_to_le_16(vnic->mru);
1290 if (vnic->func_default)
1292 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1293 if (vnic->vlan_strip)
1295 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1298 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1299 if (vnic->roce_dual)
1300 req.flags |= rte_cpu_to_le_32(
1301 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1302 if (vnic->roce_only)
1303 req.flags |= rte_cpu_to_le_32(
1304 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1305 if (vnic->rss_dflt_cr)
1306 req.flags |= rte_cpu_to_le_32(
1307 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1309 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1311 HWRM_CHECK_RESULT();
1314 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1319 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1323 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1324 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1326 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1327 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1330 HWRM_PREP(req, VNIC_QCFG);
1333 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1334 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1335 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1337 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1339 HWRM_CHECK_RESULT();
1341 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1342 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1343 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1344 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1345 vnic->mru = rte_le_to_cpu_16(resp->mru);
1346 vnic->func_default = rte_le_to_cpu_32(
1347 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1348 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1349 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1350 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1351 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1352 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1353 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1354 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1355 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1356 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1357 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1364 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1367 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1368 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1369 bp->hwrm_cmd_resp_addr;
1371 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1373 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1375 HWRM_CHECK_RESULT();
1377 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1379 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1384 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1387 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1388 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1389 bp->hwrm_cmd_resp_addr;
1391 if (vnic->rss_rule == 0xffff) {
1392 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1395 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1397 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1399 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1401 HWRM_CHECK_RESULT();
1404 vnic->rss_rule = INVALID_HW_RING_ID;
1409 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1412 struct hwrm_vnic_free_input req = {.req_type = 0 };
1413 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1415 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1416 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1420 HWRM_PREP(req, VNIC_FREE);
1422 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1424 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1426 HWRM_CHECK_RESULT();
1429 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1433 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1434 struct bnxt_vnic_info *vnic)
1437 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1438 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1440 HWRM_PREP(req, VNIC_RSS_CFG);
1442 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1444 req.ring_grp_tbl_addr =
1445 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1446 req.hash_key_tbl_addr =
1447 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1448 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1450 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1452 HWRM_CHECK_RESULT();
1458 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1459 struct bnxt_vnic_info *vnic)
1462 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1463 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1466 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1468 req.flags = rte_cpu_to_le_32(
1469 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1471 req.enables = rte_cpu_to_le_32(
1472 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1474 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1475 size -= RTE_PKTMBUF_HEADROOM;
1477 req.jumbo_thresh = rte_cpu_to_le_16(size);
1478 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1480 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1482 HWRM_CHECK_RESULT();
1488 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1489 struct bnxt_vnic_info *vnic, bool enable)
1492 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1493 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1495 HWRM_PREP(req, VNIC_TPA_CFG);
1498 req.enables = rte_cpu_to_le_32(
1499 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1500 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1501 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1502 req.flags = rte_cpu_to_le_32(
1503 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1504 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1505 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1506 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1507 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1508 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1509 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1510 req.max_agg_segs = rte_cpu_to_le_16(5);
1512 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1513 req.min_agg_len = rte_cpu_to_le_32(512);
1516 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1518 HWRM_CHECK_RESULT();
1524 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1526 struct hwrm_func_cfg_input req = {0};
1527 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1530 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1531 req.enables = rte_cpu_to_le_32(
1532 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1533 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1534 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1536 HWRM_PREP(req, FUNC_CFG);
1538 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1539 HWRM_CHECK_RESULT();
1542 bp->pf.vf_info[vf].random_mac = false;
1547 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1551 struct hwrm_func_qstats_input req = {.req_type = 0};
1552 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1554 HWRM_PREP(req, FUNC_QSTATS);
1556 req.fid = rte_cpu_to_le_16(fid);
1558 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1560 HWRM_CHECK_RESULT();
1563 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1570 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1571 struct rte_eth_stats *stats)
1574 struct hwrm_func_qstats_input req = {.req_type = 0};
1575 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1577 HWRM_PREP(req, FUNC_QSTATS);
1579 req.fid = rte_cpu_to_le_16(fid);
1581 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1583 HWRM_CHECK_RESULT();
1585 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1586 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1587 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1588 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1589 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1590 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1592 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1593 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1594 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1595 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1596 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1597 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1599 stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1600 stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1602 stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1609 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1612 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1613 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1615 HWRM_PREP(req, FUNC_CLR_STATS);
1617 req.fid = rte_cpu_to_le_16(fid);
1619 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1621 HWRM_CHECK_RESULT();
1628 * HWRM utility functions
1631 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1636 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1637 struct bnxt_tx_queue *txq;
1638 struct bnxt_rx_queue *rxq;
1639 struct bnxt_cp_ring_info *cpr;
1641 if (i >= bp->rx_cp_nr_rings) {
1642 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1645 rxq = bp->rx_queues[i];
1649 rc = bnxt_hwrm_stat_clear(bp, cpr);
1656 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1660 struct bnxt_cp_ring_info *cpr;
1662 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1664 if (i >= bp->rx_cp_nr_rings) {
1665 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1667 cpr = bp->rx_queues[i]->cp_ring;
1668 bp->grp_info[i].fw_stats_ctx = -1;
1670 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1671 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1672 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1680 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1685 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1686 struct bnxt_tx_queue *txq;
1687 struct bnxt_rx_queue *rxq;
1688 struct bnxt_cp_ring_info *cpr;
1690 if (i >= bp->rx_cp_nr_rings) {
1691 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1694 rxq = bp->rx_queues[i];
1698 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1706 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1711 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1713 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1716 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1724 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1725 unsigned int idx __rte_unused)
1727 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1729 bnxt_hwrm_ring_free(bp, cp_ring,
1730 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1731 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1732 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1733 sizeof(*cpr->cp_desc_ring));
1734 cpr->cp_raw_cons = 0;
1737 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1742 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1743 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1744 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1745 struct bnxt_ring *ring = txr->tx_ring_struct;
1746 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1747 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1749 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1750 bnxt_hwrm_ring_free(bp, ring,
1751 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1752 ring->fw_ring_id = INVALID_HW_RING_ID;
1753 memset(txr->tx_desc_ring, 0,
1754 txr->tx_ring_struct->ring_size *
1755 sizeof(*txr->tx_desc_ring));
1756 memset(txr->tx_buf_ring, 0,
1757 txr->tx_ring_struct->ring_size *
1758 sizeof(*txr->tx_buf_ring));
1762 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1763 bnxt_free_cp_ring(bp, cpr, idx);
1764 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1768 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1769 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1770 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1771 struct bnxt_ring *ring = rxr->rx_ring_struct;
1772 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1773 unsigned int idx = i + 1;
1775 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1776 bnxt_hwrm_ring_free(bp, ring,
1777 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1778 ring->fw_ring_id = INVALID_HW_RING_ID;
1779 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1780 memset(rxr->rx_desc_ring, 0,
1781 rxr->rx_ring_struct->ring_size *
1782 sizeof(*rxr->rx_desc_ring));
1783 memset(rxr->rx_buf_ring, 0,
1784 rxr->rx_ring_struct->ring_size *
1785 sizeof(*rxr->rx_buf_ring));
1788 ring = rxr->ag_ring_struct;
1789 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1790 bnxt_hwrm_ring_free(bp, ring,
1791 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1792 ring->fw_ring_id = INVALID_HW_RING_ID;
1793 memset(rxr->ag_buf_ring, 0,
1794 rxr->ag_ring_struct->ring_size *
1795 sizeof(*rxr->ag_buf_ring));
1797 bp->grp_info[i].ag_fw_ring_id = INVALID_HW_RING_ID;
1799 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1800 bnxt_free_cp_ring(bp, cpr, idx);
1801 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1802 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1806 /* Default completion ring */
1808 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1810 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1811 bnxt_free_cp_ring(bp, cpr, 0);
1812 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1819 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1824 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1825 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1832 void bnxt_free_hwrm_resources(struct bnxt *bp)
1834 /* Release memzone */
1835 rte_free(bp->hwrm_cmd_resp_addr);
1836 rte_free(bp->hwrm_short_cmd_req_addr);
1837 bp->hwrm_cmd_resp_addr = NULL;
1838 bp->hwrm_short_cmd_req_addr = NULL;
1839 bp->hwrm_cmd_resp_dma_addr = 0;
1840 bp->hwrm_short_cmd_req_dma_addr = 0;
1843 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1845 struct rte_pci_device *pdev = bp->pdev;
1846 char type[RTE_MEMZONE_NAMESIZE];
1848 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1849 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1850 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1851 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1852 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1853 if (bp->hwrm_cmd_resp_addr == NULL)
1855 bp->hwrm_cmd_resp_dma_addr =
1856 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1857 if (bp->hwrm_cmd_resp_dma_addr == 0) {
1859 "unable to map response address to physical memory\n");
1862 rte_spinlock_init(&bp->hwrm_lock);
1867 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1869 struct bnxt_filter_info *filter;
1872 STAILQ_FOREACH(filter, &vnic->filter, next) {
1873 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1874 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1875 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1876 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1878 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1886 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1888 struct bnxt_filter_info *filter;
1889 struct rte_flow *flow;
1892 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1893 filter = flow->filter;
1894 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
1895 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1896 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1897 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1898 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1900 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1902 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1910 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1912 struct bnxt_filter_info *filter;
1915 STAILQ_FOREACH(filter, &vnic->filter, next) {
1916 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1917 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1919 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1920 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1923 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1931 void bnxt_free_tunnel_ports(struct bnxt *bp)
1933 if (bp->vxlan_port_cnt)
1934 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1935 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1937 if (bp->geneve_port_cnt)
1938 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1939 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1940 bp->geneve_port = 0;
1943 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1947 if (bp->vnic_info == NULL)
1951 * Cleanup VNICs in reverse order, to make sure the L2 filter
1952 * from vnic0 is last to be cleaned up.
1954 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1955 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1957 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1959 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1961 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1963 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1965 bnxt_hwrm_vnic_free(bp, vnic);
1967 /* Ring resources */
1968 bnxt_free_all_hwrm_rings(bp);
1969 bnxt_free_all_hwrm_ring_grps(bp);
1970 bnxt_free_all_hwrm_stat_ctxs(bp);
1971 bnxt_free_tunnel_ports(bp);
1974 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1976 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1978 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1979 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1981 switch (conf_link_speed) {
1982 case ETH_LINK_SPEED_10M_HD:
1983 case ETH_LINK_SPEED_100M_HD:
1984 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1986 return hw_link_duplex;
1989 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
1991 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
1994 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1996 uint16_t eth_link_speed = 0;
1998 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1999 return ETH_LINK_SPEED_AUTONEG;
2001 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2002 case ETH_LINK_SPEED_100M:
2003 case ETH_LINK_SPEED_100M_HD:
2005 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2007 case ETH_LINK_SPEED_1G:
2009 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2011 case ETH_LINK_SPEED_2_5G:
2013 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2015 case ETH_LINK_SPEED_10G:
2017 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2019 case ETH_LINK_SPEED_20G:
2021 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2023 case ETH_LINK_SPEED_25G:
2025 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2027 case ETH_LINK_SPEED_40G:
2029 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2031 case ETH_LINK_SPEED_50G:
2033 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2037 "Unsupported link speed %d; default to AUTO\n",
2041 return eth_link_speed;
2044 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2045 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2046 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2047 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
2049 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2053 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2056 if (link_speed & ETH_LINK_SPEED_FIXED) {
2057 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2059 if (one_speed & (one_speed - 1)) {
2061 "Invalid advertised speeds (%u) for port %u\n",
2062 link_speed, port_id);
2065 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2067 "Unsupported advertised speed (%u) for port %u\n",
2068 link_speed, port_id);
2072 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2074 "Unsupported advertised speeds (%u) for port %u\n",
2075 link_speed, port_id);
2083 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2087 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2088 if (bp->link_info.support_speeds)
2089 return bp->link_info.support_speeds;
2090 link_speed = BNXT_SUPPORTED_SPEEDS;
2093 if (link_speed & ETH_LINK_SPEED_100M)
2094 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2095 if (link_speed & ETH_LINK_SPEED_100M_HD)
2096 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2097 if (link_speed & ETH_LINK_SPEED_1G)
2098 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2099 if (link_speed & ETH_LINK_SPEED_2_5G)
2100 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2101 if (link_speed & ETH_LINK_SPEED_10G)
2102 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2103 if (link_speed & ETH_LINK_SPEED_20G)
2104 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2105 if (link_speed & ETH_LINK_SPEED_25G)
2106 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2107 if (link_speed & ETH_LINK_SPEED_40G)
2108 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2109 if (link_speed & ETH_LINK_SPEED_50G)
2110 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2114 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2116 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2118 switch (hw_link_speed) {
2119 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2120 eth_link_speed = ETH_SPEED_NUM_100M;
2122 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2123 eth_link_speed = ETH_SPEED_NUM_1G;
2125 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2126 eth_link_speed = ETH_SPEED_NUM_2_5G;
2128 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2129 eth_link_speed = ETH_SPEED_NUM_10G;
2131 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2132 eth_link_speed = ETH_SPEED_NUM_20G;
2134 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2135 eth_link_speed = ETH_SPEED_NUM_25G;
2137 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2138 eth_link_speed = ETH_SPEED_NUM_40G;
2140 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2141 eth_link_speed = ETH_SPEED_NUM_50G;
2143 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2144 eth_link_speed = ETH_SPEED_NUM_100G;
2146 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2148 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2152 return eth_link_speed;
2155 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2157 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2159 switch (hw_link_duplex) {
2160 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2161 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2162 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2164 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2165 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2168 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2172 return eth_link_duplex;
2175 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2178 struct bnxt_link_info *link_info = &bp->link_info;
2180 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2183 "Get link config failed with rc %d\n", rc);
2186 if (link_info->link_speed)
2188 bnxt_parse_hw_link_speed(link_info->link_speed);
2190 link->link_speed = ETH_SPEED_NUM_NONE;
2191 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2192 link->link_status = link_info->link_up;
2193 link->link_autoneg = link_info->auto_mode ==
2194 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2195 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2200 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2203 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2204 struct bnxt_link_info link_req;
2205 uint16_t speed, autoneg;
2207 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2210 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2211 bp->eth_dev->data->port_id);
2215 memset(&link_req, 0, sizeof(link_req));
2216 link_req.link_up = link_up;
2220 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2221 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2222 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2224 link_req.phy_flags |=
2225 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2226 link_req.auto_link_speed_mask =
2227 bnxt_parse_eth_link_speed_mask(bp,
2228 dev_conf->link_speeds);
2230 if (bp->link_info.phy_type ==
2231 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2232 bp->link_info.phy_type ==
2233 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2234 bp->link_info.media_type ==
2235 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2236 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2240 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2241 link_req.link_speed = speed;
2243 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2244 link_req.auto_pause = bp->link_info.auto_pause;
2245 link_req.force_pause = bp->link_info.force_pause;
2248 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2251 "Set link config failed with rc %d\n", rc);
2259 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2261 struct hwrm_func_qcfg_input req = {0};
2262 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2266 HWRM_PREP(req, FUNC_QCFG);
2267 req.fid = rte_cpu_to_le_16(0xffff);
2269 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2271 HWRM_CHECK_RESULT();
2273 /* Hard Coded.. 0xfff VLAN ID mask */
2274 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2275 flags = rte_le_to_cpu_16(resp->flags);
2276 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2277 bp->flags |= BNXT_FLAG_MULTI_HOST;
2279 switch (resp->port_partition_type) {
2280 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2281 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2282 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2283 bp->port_partition_type = resp->port_partition_type;
2286 bp->port_partition_type = 0;
2295 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2296 struct hwrm_func_qcaps_output *qcaps)
2298 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2299 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2300 sizeof(qcaps->mac_address));
2301 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2302 qcaps->max_rx_rings = fcfg->num_rx_rings;
2303 qcaps->max_tx_rings = fcfg->num_tx_rings;
2304 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2305 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2307 qcaps->first_vf_id = 0;
2308 qcaps->max_vnics = fcfg->num_vnics;
2309 qcaps->max_decap_records = 0;
2310 qcaps->max_encap_records = 0;
2311 qcaps->max_tx_wm_flows = 0;
2312 qcaps->max_tx_em_flows = 0;
2313 qcaps->max_rx_wm_flows = 0;
2314 qcaps->max_rx_em_flows = 0;
2315 qcaps->max_flow_id = 0;
2316 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2317 qcaps->max_sp_tx_rings = 0;
2318 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2321 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2323 struct hwrm_func_cfg_input req = {0};
2324 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2327 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2328 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2329 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2330 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2331 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2332 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2333 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2334 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2335 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2336 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2337 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2338 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2339 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2340 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2341 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2342 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2343 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2344 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2345 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2346 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2347 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2348 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2349 req.fid = rte_cpu_to_le_16(0xffff);
2351 HWRM_PREP(req, FUNC_CFG);
2353 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2355 HWRM_CHECK_RESULT();
2361 static void populate_vf_func_cfg_req(struct bnxt *bp,
2362 struct hwrm_func_cfg_input *req,
2365 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2366 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2367 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2368 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2369 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2370 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2371 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2372 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2373 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2374 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2376 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2377 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2378 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2379 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2380 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2382 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2383 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2385 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2386 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2387 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2388 /* TODO: For now, do not support VMDq/RFS on VFs. */
2389 req->num_vnics = rte_cpu_to_le_16(1);
2390 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2394 static void add_random_mac_if_needed(struct bnxt *bp,
2395 struct hwrm_func_cfg_input *cfg_req,
2398 struct ether_addr mac;
2400 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2403 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2405 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2406 eth_random_addr(cfg_req->dflt_mac_addr);
2407 bp->pf.vf_info[vf].random_mac = true;
2409 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2413 static void reserve_resources_from_vf(struct bnxt *bp,
2414 struct hwrm_func_cfg_input *cfg_req,
2417 struct hwrm_func_qcaps_input req = {0};
2418 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2421 /* Get the actual allocated values now */
2422 HWRM_PREP(req, FUNC_QCAPS);
2423 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2424 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2427 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2428 copy_func_cfg_to_qcaps(cfg_req, resp);
2429 } else if (resp->error_code) {
2430 rc = rte_le_to_cpu_16(resp->error_code);
2431 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2432 copy_func_cfg_to_qcaps(cfg_req, resp);
2435 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2436 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2437 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2438 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2439 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2440 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2442 * TODO: While not supporting VMDq with VFs, max_vnics is always
2443 * forced to 1 in this case
2445 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2446 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2451 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2453 struct hwrm_func_qcfg_input req = {0};
2454 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2457 /* Check for zero MAC address */
2458 HWRM_PREP(req, FUNC_QCFG);
2459 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2460 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2462 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2464 } else if (resp->error_code) {
2465 rc = rte_le_to_cpu_16(resp->error_code);
2466 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2469 rc = rte_le_to_cpu_16(resp->vlan);
2476 static int update_pf_resource_max(struct bnxt *bp)
2478 struct hwrm_func_qcfg_input req = {0};
2479 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2482 /* And copy the allocated numbers into the pf struct */
2483 HWRM_PREP(req, FUNC_QCFG);
2484 req.fid = rte_cpu_to_le_16(0xffff);
2485 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2486 HWRM_CHECK_RESULT();
2488 /* Only TX ring value reflects actual allocation? TODO */
2489 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2490 bp->pf.evb_mode = resp->evb_mode;
2497 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2502 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2506 rc = bnxt_hwrm_func_qcaps(bp);
2510 bp->pf.func_cfg_flags &=
2511 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2512 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2513 bp->pf.func_cfg_flags |=
2514 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2515 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2519 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2521 struct hwrm_func_cfg_input req = {0};
2522 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2529 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2533 rc = bnxt_hwrm_func_qcaps(bp);
2538 bp->pf.active_vfs = num_vfs;
2541 * First, configure the PF to only use one TX ring. This ensures that
2542 * there are enough rings for all VFs.
2544 * If we don't do this, when we call func_alloc() later, we will lock
2545 * extra rings to the PF that won't be available during func_cfg() of
2548 * This has been fixed with firmware versions above 20.6.54
2550 bp->pf.func_cfg_flags &=
2551 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2552 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2553 bp->pf.func_cfg_flags |=
2554 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2555 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2560 * Now, create and register a buffer to hold forwarded VF requests
2562 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2563 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2564 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2565 if (bp->pf.vf_req_buf == NULL) {
2569 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2570 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2571 for (i = 0; i < num_vfs; i++)
2572 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2573 (i * HWRM_MAX_REQ_LEN);
2575 rc = bnxt_hwrm_func_buf_rgtr(bp);
2579 populate_vf_func_cfg_req(bp, &req, num_vfs);
2581 bp->pf.active_vfs = 0;
2582 for (i = 0; i < num_vfs; i++) {
2583 add_random_mac_if_needed(bp, &req, i);
2585 HWRM_PREP(req, FUNC_CFG);
2586 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2587 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2588 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2590 /* Clear enable flag for next pass */
2591 req.enables &= ~rte_cpu_to_le_32(
2592 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2594 if (rc || resp->error_code) {
2596 "Failed to initizlie VF %d\n", i);
2598 "Not all VFs available. (%d, %d)\n",
2599 rc, resp->error_code);
2606 reserve_resources_from_vf(bp, &req, i);
2607 bp->pf.active_vfs++;
2608 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2612 * Now configure the PF to use "the rest" of the resources
2613 * We're using STD_TX_RING_MODE here though which will limit the TX
2614 * rings. This will allow QoS to function properly. Not setting this
2615 * will cause PF rings to break bandwidth settings.
2617 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2621 rc = update_pf_resource_max(bp);
2628 bnxt_hwrm_func_buf_unrgtr(bp);
2632 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2634 struct hwrm_func_cfg_input req = {0};
2635 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2638 HWRM_PREP(req, FUNC_CFG);
2640 req.fid = rte_cpu_to_le_16(0xffff);
2641 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2642 req.evb_mode = bp->pf.evb_mode;
2644 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2645 HWRM_CHECK_RESULT();
2651 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2652 uint8_t tunnel_type)
2654 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2655 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2658 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2659 req.tunnel_type = tunnel_type;
2660 req.tunnel_dst_port_val = port;
2661 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2662 HWRM_CHECK_RESULT();
2664 switch (tunnel_type) {
2665 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2666 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2667 bp->vxlan_port = port;
2669 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2670 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2671 bp->geneve_port = port;
2682 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2683 uint8_t tunnel_type)
2685 struct hwrm_tunnel_dst_port_free_input req = {0};
2686 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2689 HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2691 req.tunnel_type = tunnel_type;
2692 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2693 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2695 HWRM_CHECK_RESULT();
2701 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2704 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2705 struct hwrm_func_cfg_input req = {0};
2708 HWRM_PREP(req, FUNC_CFG);
2710 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2711 req.flags = rte_cpu_to_le_32(flags);
2712 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2714 HWRM_CHECK_RESULT();
2720 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2722 uint32_t *flag = flagp;
2724 vnic->flags = *flag;
2727 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2729 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2732 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2735 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2736 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2738 HWRM_PREP(req, FUNC_BUF_RGTR);
2740 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2741 req.req_buf_page_size = rte_cpu_to_le_16(
2742 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2743 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2744 req.req_buf_page_addr[0] =
2745 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2746 if (req.req_buf_page_addr[0] == 0) {
2748 "unable to map buffer address to physical memory\n");
2752 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2754 HWRM_CHECK_RESULT();
2760 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2763 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2764 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2766 HWRM_PREP(req, FUNC_BUF_UNRGTR);
2768 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2770 HWRM_CHECK_RESULT();
2776 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2778 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2779 struct hwrm_func_cfg_input req = {0};
2782 HWRM_PREP(req, FUNC_CFG);
2784 req.fid = rte_cpu_to_le_16(0xffff);
2785 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2786 req.enables = rte_cpu_to_le_32(
2787 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2788 req.async_event_cr = rte_cpu_to_le_16(
2789 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2790 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2792 HWRM_CHECK_RESULT();
2798 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2800 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2801 struct hwrm_func_vf_cfg_input req = {0};
2804 HWRM_PREP(req, FUNC_VF_CFG);
2806 req.enables = rte_cpu_to_le_32(
2807 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2808 req.async_event_cr = rte_cpu_to_le_16(
2809 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2810 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2812 HWRM_CHECK_RESULT();
2818 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2820 struct hwrm_func_cfg_input req = {0};
2821 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2822 uint16_t dflt_vlan, fid;
2823 uint32_t func_cfg_flags;
2826 HWRM_PREP(req, FUNC_CFG);
2829 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2830 fid = bp->pf.vf_info[vf].fid;
2831 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2833 fid = rte_cpu_to_le_16(0xffff);
2834 func_cfg_flags = bp->pf.func_cfg_flags;
2835 dflt_vlan = bp->vlan;
2838 req.flags = rte_cpu_to_le_32(func_cfg_flags);
2839 req.fid = rte_cpu_to_le_16(fid);
2840 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2841 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2843 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2845 HWRM_CHECK_RESULT();
2851 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2852 uint16_t max_bw, uint16_t enables)
2854 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2855 struct hwrm_func_cfg_input req = {0};
2858 HWRM_PREP(req, FUNC_CFG);
2860 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2861 req.enables |= rte_cpu_to_le_32(enables);
2862 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2863 req.max_bw = rte_cpu_to_le_32(max_bw);
2864 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2866 HWRM_CHECK_RESULT();
2872 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2874 struct hwrm_func_cfg_input req = {0};
2875 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2878 HWRM_PREP(req, FUNC_CFG);
2880 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2881 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2882 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2883 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2885 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2887 HWRM_CHECK_RESULT();
2893 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2894 void *encaped, size_t ec_size)
2897 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2898 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2900 if (ec_size > sizeof(req.encap_request))
2903 HWRM_PREP(req, REJECT_FWD_RESP);
2905 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2906 memcpy(req.encap_request, encaped, ec_size);
2908 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2910 HWRM_CHECK_RESULT();
2916 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2917 struct ether_addr *mac)
2919 struct hwrm_func_qcfg_input req = {0};
2920 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2923 HWRM_PREP(req, FUNC_QCFG);
2925 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2926 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2928 HWRM_CHECK_RESULT();
2930 memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2937 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2938 void *encaped, size_t ec_size)
2941 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2942 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2944 if (ec_size > sizeof(req.encap_request))
2947 HWRM_PREP(req, EXEC_FWD_RESP);
2949 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2950 memcpy(req.encap_request, encaped, ec_size);
2952 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2954 HWRM_CHECK_RESULT();
2960 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2961 struct rte_eth_stats *stats, uint8_t rx)
2964 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2965 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2967 HWRM_PREP(req, STAT_CTX_QUERY);
2969 req.stat_ctx_id = rte_cpu_to_le_32(cid);
2971 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2973 HWRM_CHECK_RESULT();
2976 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2977 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2978 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2979 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2980 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2981 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2982 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2983 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2985 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2986 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2987 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2988 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2989 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2990 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2991 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
3000 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3002 struct hwrm_port_qstats_input req = {0};
3003 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3004 struct bnxt_pf_info *pf = &bp->pf;
3007 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3010 HWRM_PREP(req, PORT_QSTATS);
3012 req.port_id = rte_cpu_to_le_16(pf->port_id);
3013 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3014 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3015 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3017 HWRM_CHECK_RESULT();
3023 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3025 struct hwrm_port_clr_stats_input req = {0};
3026 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3027 struct bnxt_pf_info *pf = &bp->pf;
3030 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3033 HWRM_PREP(req, PORT_CLR_STATS);
3035 req.port_id = rte_cpu_to_le_16(pf->port_id);
3036 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3038 HWRM_CHECK_RESULT();
3044 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3046 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3047 struct hwrm_port_led_qcaps_input req = {0};
3053 HWRM_PREP(req, PORT_LED_QCAPS);
3054 req.port_id = bp->pf.port_id;
3055 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3057 HWRM_CHECK_RESULT();
3059 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3062 bp->num_leds = resp->num_leds;
3063 memcpy(bp->leds, &resp->led0_id,
3064 sizeof(bp->leds[0]) * bp->num_leds);
3065 for (i = 0; i < bp->num_leds; i++) {
3066 struct bnxt_led_info *led = &bp->leds[i];
3068 uint16_t caps = led->led_state_caps;
3070 if (!led->led_group_id ||
3071 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3083 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3085 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3086 struct hwrm_port_led_cfg_input req = {0};
3087 struct bnxt_led_cfg *led_cfg;
3088 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3089 uint16_t duration = 0;
3092 if (!bp->num_leds || BNXT_VF(bp))
3095 HWRM_PREP(req, PORT_LED_CFG);
3098 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3099 duration = rte_cpu_to_le_16(500);
3101 req.port_id = bp->pf.port_id;
3102 req.num_leds = bp->num_leds;
3103 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3104 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3105 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3106 led_cfg->led_id = bp->leds[i].led_id;
3107 led_cfg->led_state = led_state;
3108 led_cfg->led_blink_on = duration;
3109 led_cfg->led_blink_off = duration;
3110 led_cfg->led_group_id = bp->leds[i].led_group_id;
3113 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3115 HWRM_CHECK_RESULT();
3121 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3125 struct hwrm_nvm_get_dir_info_input req = {0};
3126 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3128 HWRM_PREP(req, NVM_GET_DIR_INFO);
3130 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3132 HWRM_CHECK_RESULT();
3136 *entries = rte_le_to_cpu_32(resp->entries);
3137 *length = rte_le_to_cpu_32(resp->entry_length);
3142 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3145 uint32_t dir_entries;
3146 uint32_t entry_length;
3149 rte_iova_t dma_handle;
3150 struct hwrm_nvm_get_dir_entries_input req = {0};
3151 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3153 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3157 *data++ = dir_entries;
3158 *data++ = entry_length;
3160 memset(data, 0xff, len);
3162 buflen = dir_entries * entry_length;
3163 buf = rte_malloc("nvm_dir", buflen, 0);
3164 rte_mem_lock_page(buf);
3167 dma_handle = rte_mem_virt2iova(buf);
3168 if (dma_handle == 0) {
3170 "unable to map response address to physical memory\n");
3173 HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3174 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3175 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3177 HWRM_CHECK_RESULT();
3181 memcpy(data, buf, len > buflen ? buflen : len);
3188 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3189 uint32_t offset, uint32_t length,
3194 rte_iova_t dma_handle;
3195 struct hwrm_nvm_read_input req = {0};
3196 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3198 buf = rte_malloc("nvm_item", length, 0);
3199 rte_mem_lock_page(buf);
3203 dma_handle = rte_mem_virt2iova(buf);
3204 if (dma_handle == 0) {
3206 "unable to map response address to physical memory\n");
3209 HWRM_PREP(req, NVM_READ);
3210 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3211 req.dir_idx = rte_cpu_to_le_16(index);
3212 req.offset = rte_cpu_to_le_32(offset);
3213 req.len = rte_cpu_to_le_32(length);
3214 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3215 HWRM_CHECK_RESULT();
3218 memcpy(data, buf, length);
3224 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3227 struct hwrm_nvm_erase_dir_entry_input req = {0};
3228 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3230 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3231 req.dir_idx = rte_cpu_to_le_16(index);
3232 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3233 HWRM_CHECK_RESULT();
3240 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3241 uint16_t dir_ordinal, uint16_t dir_ext,
3242 uint16_t dir_attr, const uint8_t *data,
3246 struct hwrm_nvm_write_input req = {0};
3247 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3248 rte_iova_t dma_handle;
3251 HWRM_PREP(req, NVM_WRITE);
3253 req.dir_type = rte_cpu_to_le_16(dir_type);
3254 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3255 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3256 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3257 req.dir_data_length = rte_cpu_to_le_32(data_len);
3259 buf = rte_malloc("nvm_write", data_len, 0);
3260 rte_mem_lock_page(buf);
3264 dma_handle = rte_mem_virt2iova(buf);
3265 if (dma_handle == 0) {
3267 "unable to map response address to physical memory\n");
3270 memcpy(buf, data, data_len);
3271 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3273 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3275 HWRM_CHECK_RESULT();
3283 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3285 uint32_t *count = cbdata;
3287 *count = *count + 1;
3290 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3291 struct bnxt_vnic_info *vnic __rte_unused)
3296 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3300 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3301 &count, bnxt_vnic_count_hwrm_stub);
3306 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3309 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3310 struct hwrm_func_vf_vnic_ids_query_output *resp =
3311 bp->hwrm_cmd_resp_addr;
3314 /* First query all VNIC ids */
3315 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3317 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3318 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3319 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3321 if (req.vnic_id_tbl_addr == 0) {
3324 "unable to map VNIC ID table address to physical memory\n");
3327 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3330 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3332 } else if (resp->error_code) {
3333 rc = rte_le_to_cpu_16(resp->error_code);
3335 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3338 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3346 * This function queries the VNIC IDs for a specified VF. It then calls
3347 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3348 * Then it calls the hwrm_cb function to program this new vnic configuration.
3350 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3351 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3352 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3354 struct bnxt_vnic_info vnic;
3356 int i, num_vnic_ids;
3361 /* First query all VNIC ids */
3362 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3363 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3364 RTE_CACHE_LINE_SIZE);
3365 if (vnic_ids == NULL) {
3369 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3370 rte_mem_lock_page(((char *)vnic_ids) + sz);
3372 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3374 if (num_vnic_ids < 0)
3375 return num_vnic_ids;
3377 /* Retrieve VNIC, update bd_stall then update */
3379 for (i = 0; i < num_vnic_ids; i++) {
3380 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3381 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3382 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3385 if (vnic.mru <= 4) /* Indicates unallocated */
3388 vnic_cb(&vnic, cbdata);
3390 rc = hwrm_cb(bp, &vnic);
3400 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3403 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3404 struct hwrm_func_cfg_input req = {0};
3407 HWRM_PREP(req, FUNC_CFG);
3409 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3410 req.enables |= rte_cpu_to_le_32(
3411 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3412 req.vlan_antispoof_mode = on ?
3413 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3414 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3415 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3417 HWRM_CHECK_RESULT();
3423 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3425 struct bnxt_vnic_info vnic;
3428 int num_vnic_ids, i;
3432 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3433 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3434 RTE_CACHE_LINE_SIZE);
3435 if (vnic_ids == NULL) {
3440 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3441 rte_mem_lock_page(((char *)vnic_ids) + sz);
3443 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3449 * Loop through to find the default VNIC ID.
3450 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3451 * by sending the hwrm_func_qcfg command to the firmware.
3453 for (i = 0; i < num_vnic_ids; i++) {
3454 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3455 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3456 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3457 bp->pf.first_vf_id + vf);
3460 if (vnic.func_default) {
3462 return vnic.fw_vnic_id;
3465 /* Could not find a default VNIC. */
3466 PMD_DRV_LOG(ERR, "No default VNIC\n");
3472 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3474 struct bnxt_filter_info *filter)
3477 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3478 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3479 uint32_t enables = 0;
3481 if (filter->fw_em_filter_id != UINT64_MAX)
3482 bnxt_hwrm_clear_em_filter(bp, filter);
3484 HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3486 req.flags = rte_cpu_to_le_32(filter->flags);
3488 enables = filter->enables |
3489 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3490 req.dst_id = rte_cpu_to_le_16(dst_id);
3492 if (filter->ip_addr_type) {
3493 req.ip_addr_type = filter->ip_addr_type;
3494 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3497 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3498 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3500 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3501 memcpy(req.src_macaddr, filter->src_macaddr,
3504 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3505 memcpy(req.dst_macaddr, filter->dst_macaddr,
3508 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3509 req.ovlan_vid = filter->l2_ovlan;
3511 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3512 req.ivlan_vid = filter->l2_ivlan;
3514 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3515 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3517 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3518 req.ip_protocol = filter->ip_protocol;
3520 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3521 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3523 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3524 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3526 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3527 req.src_port = rte_cpu_to_be_16(filter->src_port);
3529 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3530 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3532 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3533 req.mirror_vnic_id = filter->mirror_vnic_id;
3535 req.enables = rte_cpu_to_le_32(enables);
3537 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3539 HWRM_CHECK_RESULT();
3541 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3547 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3550 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3551 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3553 if (filter->fw_em_filter_id == UINT64_MAX)
3556 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3557 HWRM_PREP(req, CFA_EM_FLOW_FREE);
3559 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3561 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3563 HWRM_CHECK_RESULT();
3566 filter->fw_em_filter_id = -1;
3567 filter->fw_l2_filter_id = -1;
3572 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3574 struct bnxt_filter_info *filter)
3577 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3578 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3579 bp->hwrm_cmd_resp_addr;
3580 uint32_t enables = 0;
3582 if (filter->fw_ntuple_filter_id != UINT64_MAX)
3583 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3585 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3587 req.flags = rte_cpu_to_le_32(filter->flags);
3589 enables = filter->enables |
3590 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3591 req.dst_id = rte_cpu_to_le_16(dst_id);
3594 if (filter->ip_addr_type) {
3595 req.ip_addr_type = filter->ip_addr_type;
3597 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3600 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3601 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3603 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3604 memcpy(req.src_macaddr, filter->src_macaddr,
3607 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3608 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3611 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3612 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3614 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3615 req.ip_protocol = filter->ip_protocol;
3617 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3618 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3620 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3621 req.src_ipaddr_mask[0] =
3622 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3624 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3625 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3627 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3628 req.dst_ipaddr_mask[0] =
3629 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3631 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3632 req.src_port = rte_cpu_to_le_16(filter->src_port);
3634 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3635 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3637 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3638 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3640 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3641 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3643 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3644 req.mirror_vnic_id = filter->mirror_vnic_id;
3646 req.enables = rte_cpu_to_le_32(enables);
3648 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3650 HWRM_CHECK_RESULT();
3652 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3658 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3659 struct bnxt_filter_info *filter)
3662 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3663 struct hwrm_cfa_ntuple_filter_free_output *resp =
3664 bp->hwrm_cmd_resp_addr;
3666 if (filter->fw_ntuple_filter_id == UINT64_MAX)
3669 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3671 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3673 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3675 HWRM_CHECK_RESULT();
3678 filter->fw_ntuple_filter_id = -1;
3683 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3685 unsigned int rss_idx, fw_idx, i;
3687 if (vnic->rss_table && vnic->hash_type) {
3689 * Fill the RSS hash & redirection table with
3690 * ring group ids for all VNICs
3692 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
3693 rss_idx++, fw_idx++) {
3694 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
3695 fw_idx %= bp->rx_cp_nr_rings;
3696 if (vnic->fw_grp_ids[fw_idx] !=
3701 if (i == bp->rx_cp_nr_rings)
3703 vnic->rss_table[rss_idx] =
3704 vnic->fw_grp_ids[fw_idx];
3706 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);