1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SHORT_CMD_TIMEOUT 50000
31 #define HWRM_SPEC_CODE_1_8_3 0x10803
32 #define HWRM_VERSION_1_9_1 0x10901
33 #define HWRM_VERSION_1_9_2 0x10903
35 struct bnxt_plcmodes_cfg {
37 uint16_t jumbo_thresh;
39 uint16_t hds_threshold;
42 static int page_getenum(size_t size)
58 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
59 return sizeof(void *) * 8 - 1;
62 static int page_roundup(size_t size)
64 return 1 << page_getenum(size);
67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
71 if (rmem->nr_pages > 1) {
73 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
75 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
80 * HWRM Functions (sent to HWRM)
81 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
82 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
83 * command was failed by the ChiMP.
86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
87 uint32_t msg_len, bool use_kong_mb)
90 struct input *req = msg;
91 struct output *resp = bp->hwrm_cmd_resp_addr;
95 uint16_t max_req_len = bp->max_req_len;
96 struct hwrm_short_input short_input = { 0 };
97 uint16_t bar_offset = use_kong_mb ?
98 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
99 uint16_t mb_trigger_offset = use_kong_mb ?
100 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
103 /* Do not send HWRM commands to firmware in error state */
104 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
107 /* For VER_GET command, set timeout as 50ms */
108 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
109 timeout = HWRM_SHORT_CMD_TIMEOUT;
111 timeout = HWRM_CMD_TIMEOUT;
113 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
114 msg_len > bp->max_req_len) {
115 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
117 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
118 memcpy(short_cmd_req, req, msg_len);
120 short_input.req_type = rte_cpu_to_le_16(req->req_type);
121 short_input.signature = rte_cpu_to_le_16(
122 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
123 short_input.size = rte_cpu_to_le_16(msg_len);
124 short_input.req_addr =
125 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
127 data = (uint32_t *)&short_input;
128 msg_len = sizeof(short_input);
130 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
133 /* Write request msg to hwrm channel */
134 for (i = 0; i < msg_len; i += 4) {
135 bar = (uint8_t *)bp->bar0 + bar_offset + i;
136 rte_write32(*data, bar);
140 /* Zero the rest of the request space */
141 for (; i < max_req_len; i += 4) {
142 bar = (uint8_t *)bp->bar0 + bar_offset + i;
146 /* Ring channel doorbell */
147 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
150 * Make sure the channel doorbell ring command complete before
151 * reading the response to avoid getting stale or invalid
156 /* Poll for the valid bit */
157 for (i = 0; i < timeout; i++) {
158 /* Sanity check on the resp->resp_len */
160 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
161 /* Last byte of resp contains the valid key */
162 valid = (uint8_t *)resp + resp->resp_len - 1;
163 if (*valid == HWRM_RESP_VALID_KEY)
170 /* Suppress VER_GET timeout messages during reset recovery */
171 if (bp->flags & BNXT_FLAG_FW_RESET &&
172 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
175 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
183 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
184 * spinlock, and does initial processing.
186 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
187 * releases the spinlock only if it returns. If the regular int return codes
188 * are not used by the function, HWRM_CHECK_RESULT() should not be used
189 * directly, rather it should be copied and modified to suit the function.
191 * HWRM_UNLOCK() must be called after all response processing is completed.
193 #define HWRM_PREP(req, type, kong) do { \
194 rte_spinlock_lock(&bp->hwrm_lock); \
195 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
196 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
197 req.cmpl_ring = rte_cpu_to_le_16(-1); \
198 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
199 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
200 req.target_id = rte_cpu_to_le_16(0xffff); \
201 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
204 #define HWRM_CHECK_RESULT_SILENT() do {\
206 rte_spinlock_unlock(&bp->hwrm_lock); \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 rte_spinlock_unlock(&bp->hwrm_lock); \
216 #define HWRM_CHECK_RESULT() do {\
218 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
219 rte_spinlock_unlock(&bp->hwrm_lock); \
220 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
226 if (resp->error_code) { \
227 rc = rte_le_to_cpu_16(resp->error_code); \
228 if (resp->resp_len >= 16) { \
229 struct hwrm_err_output *tmp_hwrm_err_op = \
232 "error %d:%d:%08x:%04x\n", \
233 rc, tmp_hwrm_err_op->cmd_err, \
235 tmp_hwrm_err_op->opaque_0), \
237 tmp_hwrm_err_op->opaque_1)); \
239 PMD_DRV_LOG(ERR, "error %d\n", rc); \
241 rte_spinlock_unlock(&bp->hwrm_lock); \
242 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
250 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
252 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
255 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
256 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
258 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
259 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
262 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
270 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
271 struct bnxt_vnic_info *vnic,
273 struct bnxt_vlan_table_entry *vlan_table)
276 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
277 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
280 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
283 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
284 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
286 /* FIXME add multicast flag, when multicast adding options is supported
289 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
290 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
291 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
292 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
293 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
294 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
295 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
296 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
297 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
298 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
299 if (vnic->mc_addr_cnt) {
300 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
301 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
302 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
305 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
306 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
307 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
308 rte_mem_virt2iova(vlan_table));
309 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
311 req.mask = rte_cpu_to_le_32(mask);
313 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
321 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
323 struct bnxt_vlan_antispoof_table_entry *vlan_table)
326 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
327 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
328 bp->hwrm_cmd_resp_addr;
331 * Older HWRM versions did not support this command, and the set_rx_mask
332 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
333 * removed from set_rx_mask call, and this command was added.
335 * This command is also present from 1.7.8.11 and higher,
338 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
339 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
340 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
345 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
346 req.fid = rte_cpu_to_le_16(fid);
348 req.vlan_tag_mask_tbl_addr =
349 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
350 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
352 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
360 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
361 struct bnxt_filter_info *filter)
364 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
365 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
367 if (filter->fw_l2_filter_id == UINT64_MAX)
370 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
372 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
374 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
379 filter->fw_l2_filter_id = UINT64_MAX;
384 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
386 struct bnxt_filter_info *filter)
389 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
390 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
391 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
392 const struct rte_eth_vmdq_rx_conf *conf =
393 &dev_conf->rx_adv_conf.vmdq_rx_conf;
394 uint32_t enables = 0;
395 uint16_t j = dst_id - 1;
397 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
398 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
399 conf->pool_map[j].pools & (1UL << j)) {
401 "Add vlan %u to vmdq pool %u\n",
402 conf->pool_map[j].vlan_id, j);
404 filter->l2_ivlan = conf->pool_map[j].vlan_id;
406 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
410 if (filter->fw_l2_filter_id != UINT64_MAX)
411 bnxt_hwrm_clear_l2_filter(bp, filter);
413 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
415 req.flags = rte_cpu_to_le_32(filter->flags);
417 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
419 enables = filter->enables |
420 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
421 req.dst_id = rte_cpu_to_le_16(dst_id);
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
425 memcpy(req.l2_addr, filter->l2_addr,
428 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
429 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
432 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
433 req.l2_ovlan = filter->l2_ovlan;
435 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
436 req.l2_ivlan = filter->l2_ivlan;
438 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
439 req.l2_ovlan_mask = filter->l2_ovlan_mask;
441 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
442 req.l2_ivlan_mask = filter->l2_ivlan_mask;
443 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
444 req.src_id = rte_cpu_to_le_32(filter->src_id);
445 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
446 req.src_type = filter->src_type;
448 req.enables = rte_cpu_to_le_32(enables);
450 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
454 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
460 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
462 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
463 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
470 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
473 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
476 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
477 if (ptp->tx_tstamp_en)
478 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
481 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
482 req.flags = rte_cpu_to_le_32(flags);
483 req.enables = rte_cpu_to_le_32
484 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
485 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
487 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
493 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
496 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
497 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
498 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
500 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
504 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
506 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
508 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
512 if (!BNXT_CHIP_THOR(bp) &&
513 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
516 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
517 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
519 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
523 if (!BNXT_CHIP_THOR(bp)) {
524 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
525 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
526 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
527 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
528 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
529 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
530 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
531 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
532 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
533 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
534 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
535 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
536 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
537 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
538 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
539 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
540 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
541 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
550 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
553 struct hwrm_func_qcaps_input req = {.req_type = 0 };
554 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
555 uint16_t new_max_vfs;
559 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
561 req.fid = rte_cpu_to_le_16(0xffff);
563 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
567 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
568 flags = rte_le_to_cpu_32(resp->flags);
570 bp->pf.port_id = resp->port_id;
571 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
572 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
573 new_max_vfs = bp->pdev->max_vfs;
574 if (new_max_vfs != bp->pf.max_vfs) {
576 rte_free(bp->pf.vf_info);
577 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
578 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
579 bp->pf.max_vfs = new_max_vfs;
580 for (i = 0; i < new_max_vfs; i++) {
581 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
582 bp->pf.vf_info[i].vlan_table =
583 rte_zmalloc("VF VLAN table",
586 if (bp->pf.vf_info[i].vlan_table == NULL)
588 "Fail to alloc VLAN table for VF %d\n",
592 bp->pf.vf_info[i].vlan_table);
593 bp->pf.vf_info[i].vlan_as_table =
594 rte_zmalloc("VF VLAN AS table",
597 if (bp->pf.vf_info[i].vlan_as_table == NULL)
599 "Alloc VLAN AS table for VF %d fail\n",
603 bp->pf.vf_info[i].vlan_as_table);
604 STAILQ_INIT(&bp->pf.vf_info[i].filter);
609 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
610 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
611 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
612 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
613 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
614 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
615 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
616 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
618 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
619 /* TODO: For now, do not support VMDq/RFS on VFs. */
624 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
628 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
630 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
631 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
632 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
633 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
635 bnxt_hwrm_ptp_qcfg(bp);
639 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
640 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
642 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
643 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
644 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
646 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
649 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
650 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
652 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
659 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
663 rc = __bnxt_hwrm_func_qcaps(bp);
664 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
665 rc = bnxt_alloc_ctx_mem(bp);
669 rc = bnxt_hwrm_func_resc_qcaps(bp);
671 bp->flags |= BNXT_FLAG_NEW_RM;
677 int bnxt_hwrm_func_reset(struct bnxt *bp)
680 struct hwrm_func_reset_input req = {.req_type = 0 };
681 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
683 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
685 req.enables = rte_cpu_to_le_32(0);
687 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
695 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
699 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
700 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
702 if (bp->flags & BNXT_FLAG_REGISTERED)
705 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
706 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
707 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
709 /* PFs and trusted VFs should indicate the support of the
710 * Master capability on non Stingray platform
712 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
713 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
715 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
716 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
717 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
718 req.ver_maj = RTE_VER_YEAR;
719 req.ver_min = RTE_VER_MONTH;
720 req.ver_upd = RTE_VER_MINOR;
723 req.enables |= rte_cpu_to_le_32(
724 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
725 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
726 RTE_MIN(sizeof(req.vf_req_fwd),
727 sizeof(bp->pf.vf_req_fwd)));
730 * PF can sniff HWRM API issued by VF. This can be set up by
731 * linux driver and inherited by the DPDK PF driver. Clear
732 * this HWRM sniffer list in FW because DPDK PF driver does
735 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
738 req.flags = rte_cpu_to_le_32(flags);
740 req.async_event_fwd[0] |=
741 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
742 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
743 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
744 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
745 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
746 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
747 req.async_event_fwd[0] |=
748 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
749 req.async_event_fwd[1] |=
750 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
751 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
753 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
757 flags = rte_le_to_cpu_32(resp->flags);
758 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
759 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
763 bp->flags |= BNXT_FLAG_REGISTERED;
768 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
770 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
773 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
776 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
781 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
782 struct hwrm_func_vf_cfg_input req = {0};
784 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
786 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
787 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
788 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
789 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
790 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
792 if (BNXT_HAS_RING_GRPS(bp)) {
793 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
794 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
797 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
798 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
799 AGG_RING_MULTIPLIER);
800 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
802 BNXT_NUM_ASYNC_CPR(bp));
803 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
805 BNXT_NUM_ASYNC_CPR(bp));
806 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
807 if (bp->vf_resv_strategy ==
808 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
809 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
810 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
811 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
812 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
813 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
814 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
818 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
819 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
820 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
821 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
822 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
823 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
825 if (test && BNXT_HAS_RING_GRPS(bp))
826 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
828 req.flags = rte_cpu_to_le_32(flags);
829 req.enables |= rte_cpu_to_le_32(enables);
831 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
834 HWRM_CHECK_RESULT_SILENT();
842 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
845 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
846 struct hwrm_func_resource_qcaps_input req = {0};
848 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
849 req.fid = rte_cpu_to_le_16(0xffff);
851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
856 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
857 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
858 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
859 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
860 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
861 /* func_resource_qcaps does not return max_rx_em_flows.
862 * So use the value provided by func_qcaps.
865 rte_le_to_cpu_16(resp->max_l2_ctxs) +
867 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
868 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
870 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
871 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
872 if (bp->vf_resv_strategy >
873 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
874 bp->vf_resv_strategy =
875 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
881 int bnxt_hwrm_ver_get(struct bnxt *bp)
884 struct hwrm_ver_get_input req = {.req_type = 0 };
885 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
887 uint16_t max_resp_len;
888 char type[RTE_MEMZONE_NAMESIZE];
889 uint32_t dev_caps_cfg;
891 bp->max_req_len = HWRM_MAX_REQ_LEN;
892 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
894 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
895 req.hwrm_intf_min = HWRM_VERSION_MINOR;
896 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
898 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
900 if (bp->flags & BNXT_FLAG_FW_RESET)
901 HWRM_CHECK_RESULT_SILENT();
905 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
906 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
907 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
908 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
909 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
910 (resp->hwrm_fw_min_8b << 16) |
911 (resp->hwrm_fw_bld_8b << 8) |
912 resp->hwrm_fw_rsvd_8b;
913 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
914 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
916 fw_version = resp->hwrm_intf_maj_8b << 16;
917 fw_version |= resp->hwrm_intf_min_8b << 8;
918 fw_version |= resp->hwrm_intf_upd_8b;
919 bp->hwrm_spec_code = fw_version;
921 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
922 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
927 if (bp->max_req_len > resp->max_req_win_len) {
928 PMD_DRV_LOG(ERR, "Unsupported request length\n");
931 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
932 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
933 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
934 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
936 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
937 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
939 if (bp->max_resp_len != max_resp_len) {
940 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
941 bp->pdev->addr.domain, bp->pdev->addr.bus,
942 bp->pdev->addr.devid, bp->pdev->addr.function);
944 rte_free(bp->hwrm_cmd_resp_addr);
946 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
947 if (bp->hwrm_cmd_resp_addr == NULL) {
951 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
952 bp->hwrm_cmd_resp_dma_addr =
953 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
954 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
956 "Unable to map response buffer to physical memory.\n");
960 bp->max_resp_len = max_resp_len;
964 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
966 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
967 PMD_DRV_LOG(DEBUG, "Short command supported\n");
968 bp->flags |= BNXT_FLAG_SHORT_CMD;
972 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
974 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
975 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
976 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
977 bp->pdev->addr.domain, bp->pdev->addr.bus,
978 bp->pdev->addr.devid, bp->pdev->addr.function);
980 rte_free(bp->hwrm_short_cmd_req_addr);
982 bp->hwrm_short_cmd_req_addr =
983 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
984 if (bp->hwrm_short_cmd_req_addr == NULL) {
988 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
989 bp->hwrm_short_cmd_req_dma_addr =
990 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
991 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
992 rte_free(bp->hwrm_short_cmd_req_addr);
994 "Unable to map buffer to physical memory.\n");
1000 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1001 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1002 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1005 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1006 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1013 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1016 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1017 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1019 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1022 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1025 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1027 HWRM_CHECK_RESULT();
1033 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1036 struct hwrm_port_phy_cfg_input req = {0};
1037 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1038 uint32_t enables = 0;
1040 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1042 if (conf->link_up) {
1043 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1044 if (bp->link_info.auto_mode && conf->link_speed) {
1045 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1046 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1049 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1050 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1051 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1053 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1054 * any auto mode, even "none".
1056 if (!conf->link_speed) {
1057 /* No speeds specified. Enable AutoNeg - all speeds */
1059 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1061 /* AutoNeg - Advertise speeds specified. */
1062 if (conf->auto_link_speed_mask &&
1063 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1065 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1066 req.auto_link_speed_mask =
1067 conf->auto_link_speed_mask;
1069 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1072 req.auto_duplex = conf->duplex;
1073 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1074 req.auto_pause = conf->auto_pause;
1075 req.force_pause = conf->force_pause;
1076 /* Set force_pause if there is no auto or if there is a force */
1077 if (req.auto_pause && !req.force_pause)
1078 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1080 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1082 req.enables = rte_cpu_to_le_32(enables);
1085 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1086 PMD_DRV_LOG(INFO, "Force Link Down\n");
1089 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1091 HWRM_CHECK_RESULT();
1097 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1098 struct bnxt_link_info *link_info)
1101 struct hwrm_port_phy_qcfg_input req = {0};
1102 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1104 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1106 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1108 HWRM_CHECK_RESULT();
1110 link_info->phy_link_status = resp->link;
1111 link_info->link_up =
1112 (link_info->phy_link_status ==
1113 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1114 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1115 link_info->duplex = resp->duplex_cfg;
1116 link_info->pause = resp->pause;
1117 link_info->auto_pause = resp->auto_pause;
1118 link_info->force_pause = resp->force_pause;
1119 link_info->auto_mode = resp->auto_mode;
1120 link_info->phy_type = resp->phy_type;
1121 link_info->media_type = resp->media_type;
1123 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1124 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1125 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1126 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1127 link_info->phy_ver[0] = resp->phy_maj;
1128 link_info->phy_ver[1] = resp->phy_min;
1129 link_info->phy_ver[2] = resp->phy_bld;
1133 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1134 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1135 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1136 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1137 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1138 link_info->auto_link_speed_mask);
1139 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1140 link_info->force_link_speed);
1145 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1148 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1149 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1152 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1154 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1155 /* HWRM Version >= 1.9.1 */
1156 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1158 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1159 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1161 HWRM_CHECK_RESULT();
1163 #define GET_QUEUE_INFO(x) \
1164 bp->cos_queue[x].id = resp->queue_id##x; \
1165 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1178 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1179 bp->tx_cosq_id = bp->cos_queue[0].id;
1181 /* iterate and find the COSq profile to use for Tx */
1182 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1183 if (bp->cos_queue[i].profile ==
1184 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1185 bp->tx_cosq_id = bp->cos_queue[i].id;
1191 bp->max_tc = resp->max_configurable_queues;
1192 bp->max_lltc = resp->max_configurable_lossless_queues;
1193 if (bp->max_tc > BNXT_MAX_QUEUE)
1194 bp->max_tc = BNXT_MAX_QUEUE;
1195 bp->max_q = bp->max_tc;
1197 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1202 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1203 struct bnxt_ring *ring,
1204 uint32_t ring_type, uint32_t map_index,
1205 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1208 uint32_t enables = 0;
1209 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1210 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1211 struct rte_mempool *mb_pool;
1212 uint16_t rx_buf_size;
1214 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1216 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1217 req.fbo = rte_cpu_to_le_32(0);
1218 /* Association of ring index with doorbell index */
1219 req.logical_id = rte_cpu_to_le_16(map_index);
1220 req.length = rte_cpu_to_le_32(ring->ring_size);
1222 switch (ring_type) {
1223 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1224 req.ring_type = ring_type;
1225 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1226 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1227 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1228 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1230 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1232 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1233 req.ring_type = ring_type;
1234 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1235 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1236 if (BNXT_CHIP_THOR(bp)) {
1237 mb_pool = bp->rx_queues[0]->mb_pool;
1238 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1239 RTE_PKTMBUF_HEADROOM;
1240 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1241 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1243 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1245 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1247 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1249 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1250 req.ring_type = ring_type;
1251 if (BNXT_HAS_NQ(bp)) {
1252 /* Association of cp ring with nq */
1253 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1255 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1257 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1259 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1260 req.ring_type = ring_type;
1261 req.page_size = BNXT_PAGE_SHFT;
1262 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1264 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1265 req.ring_type = ring_type;
1266 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1268 mb_pool = bp->rx_queues[0]->mb_pool;
1269 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1270 RTE_PKTMBUF_HEADROOM;
1271 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1272 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1274 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1275 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1276 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1277 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1280 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1285 req.enables = rte_cpu_to_le_32(enables);
1287 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1289 if (rc || resp->error_code) {
1290 if (rc == 0 && resp->error_code)
1291 rc = rte_le_to_cpu_16(resp->error_code);
1292 switch (ring_type) {
1293 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1295 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1298 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1300 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1303 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1305 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1309 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1311 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1314 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1316 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1320 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1326 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1331 int bnxt_hwrm_ring_free(struct bnxt *bp,
1332 struct bnxt_ring *ring, uint32_t ring_type)
1335 struct hwrm_ring_free_input req = {.req_type = 0 };
1336 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1338 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1340 req.ring_type = ring_type;
1341 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1343 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1345 if (rc || resp->error_code) {
1346 if (rc == 0 && resp->error_code)
1347 rc = rte_le_to_cpu_16(resp->error_code);
1350 switch (ring_type) {
1351 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1352 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1355 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1356 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1359 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1360 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1363 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1365 "hwrm_ring_free nq failed. rc:%d\n", rc);
1367 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1369 "hwrm_ring_free agg failed. rc:%d\n", rc);
1372 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1380 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1383 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1384 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1386 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1388 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1389 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1390 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1391 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1393 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1395 HWRM_CHECK_RESULT();
1397 bp->grp_info[idx].fw_grp_id =
1398 rte_le_to_cpu_16(resp->ring_group_id);
1405 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1408 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1409 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1411 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1413 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1415 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1417 HWRM_CHECK_RESULT();
1420 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1424 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1427 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1428 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1430 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1433 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1435 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1437 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1439 HWRM_CHECK_RESULT();
1445 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1446 unsigned int idx __rte_unused)
1449 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1450 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1452 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1454 req.update_period_ms = rte_cpu_to_le_32(0);
1456 req.stats_dma_addr =
1457 rte_cpu_to_le_64(cpr->hw_stats_map);
1459 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1461 HWRM_CHECK_RESULT();
1463 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1470 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1471 unsigned int idx __rte_unused)
1474 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1475 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1477 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1479 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1481 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1483 HWRM_CHECK_RESULT();
1489 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1492 struct hwrm_vnic_alloc_input req = { 0 };
1493 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1495 if (!BNXT_HAS_RING_GRPS(bp))
1496 goto skip_ring_grps;
1498 /* map ring groups to this vnic */
1499 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1500 vnic->start_grp_id, vnic->end_grp_id);
1501 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1502 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1504 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1505 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1506 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1507 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1510 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1511 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1512 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1514 if (vnic->func_default)
1516 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1517 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1519 HWRM_CHECK_RESULT();
1521 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1523 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1527 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1528 struct bnxt_vnic_info *vnic,
1529 struct bnxt_plcmodes_cfg *pmode)
1532 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1533 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1535 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1537 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1539 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1541 HWRM_CHECK_RESULT();
1543 pmode->flags = rte_le_to_cpu_32(resp->flags);
1544 /* dflt_vnic bit doesn't exist in the _cfg command */
1545 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1546 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1547 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1548 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1555 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1556 struct bnxt_vnic_info *vnic,
1557 struct bnxt_plcmodes_cfg *pmode)
1560 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1561 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1563 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1564 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1568 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1570 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1571 req.flags = rte_cpu_to_le_32(pmode->flags);
1572 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1573 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1574 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1575 req.enables = rte_cpu_to_le_32(
1576 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1577 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1578 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1581 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1583 HWRM_CHECK_RESULT();
1589 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1592 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1593 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1594 struct bnxt_plcmodes_cfg pmodes = { 0 };
1595 uint32_t ctx_enable_flag = 0;
1596 uint32_t enables = 0;
1598 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1599 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1603 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1607 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1609 if (BNXT_CHIP_THOR(bp)) {
1610 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1611 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1612 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1614 req.default_rx_ring_id =
1615 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1616 req.default_cmpl_ring_id =
1617 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1618 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1619 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1623 /* Only RSS support for now TBD: COS & LB */
1624 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1625 if (vnic->lb_rule != 0xffff)
1626 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1627 if (vnic->cos_rule != 0xffff)
1628 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1629 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1630 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1631 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1633 enables |= ctx_enable_flag;
1634 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1635 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1636 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1637 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1640 req.enables = rte_cpu_to_le_32(enables);
1641 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1642 req.mru = rte_cpu_to_le_16(vnic->mru);
1643 /* Configure default VNIC only once. */
1644 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1646 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1647 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1649 if (vnic->vlan_strip)
1651 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1654 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1655 if (vnic->roce_dual)
1656 req.flags |= rte_cpu_to_le_32(
1657 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1658 if (vnic->roce_only)
1659 req.flags |= rte_cpu_to_le_32(
1660 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1661 if (vnic->rss_dflt_cr)
1662 req.flags |= rte_cpu_to_le_32(
1663 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1665 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1667 HWRM_CHECK_RESULT();
1670 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1675 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1679 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1680 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1682 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1683 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1686 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1689 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1690 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1691 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1693 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1695 HWRM_CHECK_RESULT();
1697 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1698 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1699 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1700 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1701 vnic->mru = rte_le_to_cpu_16(resp->mru);
1702 vnic->func_default = rte_le_to_cpu_32(
1703 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1704 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1705 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1706 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1707 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1708 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1709 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1710 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1711 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1712 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1713 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1720 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1721 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1725 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1726 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1727 bp->hwrm_cmd_resp_addr;
1729 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1731 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1732 HWRM_CHECK_RESULT();
1734 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1735 if (!BNXT_HAS_RING_GRPS(bp))
1736 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1737 else if (ctx_idx == 0)
1738 vnic->rss_rule = ctx_id;
1745 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1746 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1749 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1750 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1751 bp->hwrm_cmd_resp_addr;
1753 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1754 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1757 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1759 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1761 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1763 HWRM_CHECK_RESULT();
1769 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1772 struct hwrm_vnic_free_input req = {.req_type = 0 };
1773 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1775 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1776 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1780 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1782 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1784 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1786 HWRM_CHECK_RESULT();
1789 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1790 /* Configure default VNIC again if necessary. */
1791 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1792 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1798 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1802 int nr_ctxs = vnic->num_lb_ctxts;
1803 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1804 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1806 for (i = 0; i < nr_ctxs; i++) {
1807 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1809 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1810 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1811 req.hash_mode_flags = vnic->hash_mode;
1813 req.hash_key_tbl_addr =
1814 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1816 req.ring_grp_tbl_addr =
1817 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1818 i * HW_HASH_INDEX_SIZE);
1819 req.ring_table_pair_index = i;
1820 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1822 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1825 HWRM_CHECK_RESULT();
1832 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1833 struct bnxt_vnic_info *vnic)
1836 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1837 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1839 if (!vnic->rss_table)
1842 if (BNXT_CHIP_THOR(bp))
1843 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1845 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1847 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1848 req.hash_mode_flags = vnic->hash_mode;
1850 req.ring_grp_tbl_addr =
1851 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1852 req.hash_key_tbl_addr =
1853 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1854 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1855 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1857 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1859 HWRM_CHECK_RESULT();
1865 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1866 struct bnxt_vnic_info *vnic)
1869 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1870 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1873 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1874 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1878 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1880 req.flags = rte_cpu_to_le_32(
1881 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1883 req.enables = rte_cpu_to_le_32(
1884 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1886 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1887 size -= RTE_PKTMBUF_HEADROOM;
1888 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1890 req.jumbo_thresh = rte_cpu_to_le_16(size);
1891 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1893 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1895 HWRM_CHECK_RESULT();
1901 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1902 struct bnxt_vnic_info *vnic, bool enable)
1905 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1906 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1908 if (BNXT_CHIP_THOR(bp))
1911 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1914 req.enables = rte_cpu_to_le_32(
1915 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1916 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1917 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1918 req.flags = rte_cpu_to_le_32(
1919 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1920 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1921 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1922 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1923 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1924 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1925 req.max_agg_segs = rte_cpu_to_le_16(5);
1927 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1928 req.min_agg_len = rte_cpu_to_le_32(512);
1930 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1932 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1934 HWRM_CHECK_RESULT();
1940 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1942 struct hwrm_func_cfg_input req = {0};
1943 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1946 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1947 req.enables = rte_cpu_to_le_32(
1948 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1949 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1950 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1952 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1954 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1955 HWRM_CHECK_RESULT();
1958 bp->pf.vf_info[vf].random_mac = false;
1963 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1967 struct hwrm_func_qstats_input req = {.req_type = 0};
1968 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1970 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1972 req.fid = rte_cpu_to_le_16(fid);
1974 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1976 HWRM_CHECK_RESULT();
1979 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1986 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1987 struct rte_eth_stats *stats)
1990 struct hwrm_func_qstats_input req = {.req_type = 0};
1991 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1993 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1995 req.fid = rte_cpu_to_le_16(fid);
1997 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1999 HWRM_CHECK_RESULT();
2001 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2002 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2003 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2004 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2005 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2006 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2008 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2009 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2010 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2011 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2012 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2013 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2015 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2016 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2017 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2024 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2027 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2028 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2030 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2032 req.fid = rte_cpu_to_le_16(fid);
2034 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2036 HWRM_CHECK_RESULT();
2043 * HWRM utility functions
2046 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2051 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2052 struct bnxt_tx_queue *txq;
2053 struct bnxt_rx_queue *rxq;
2054 struct bnxt_cp_ring_info *cpr;
2056 if (i >= bp->rx_cp_nr_rings) {
2057 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2060 rxq = bp->rx_queues[i];
2064 rc = bnxt_hwrm_stat_clear(bp, cpr);
2071 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2075 struct bnxt_cp_ring_info *cpr;
2077 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2079 if (i >= bp->rx_cp_nr_rings) {
2080 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2082 cpr = bp->rx_queues[i]->cp_ring;
2083 if (BNXT_HAS_RING_GRPS(bp))
2084 bp->grp_info[i].fw_stats_ctx = -1;
2086 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2087 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2088 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2096 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2101 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2102 struct bnxt_tx_queue *txq;
2103 struct bnxt_rx_queue *rxq;
2104 struct bnxt_cp_ring_info *cpr;
2106 if (i >= bp->rx_cp_nr_rings) {
2107 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2110 rxq = bp->rx_queues[i];
2114 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2122 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2127 if (!BNXT_HAS_RING_GRPS(bp))
2130 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2132 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2135 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2143 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2145 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2147 bnxt_hwrm_ring_free(bp, cp_ring,
2148 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2149 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2150 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2151 sizeof(*cpr->cp_desc_ring));
2152 cpr->cp_raw_cons = 0;
2156 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2158 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2160 bnxt_hwrm_ring_free(bp, cp_ring,
2161 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2162 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2163 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2164 sizeof(*cpr->cp_desc_ring));
2165 cpr->cp_raw_cons = 0;
2169 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2171 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2172 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2173 struct bnxt_ring *ring = rxr->rx_ring_struct;
2174 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2176 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2177 bnxt_hwrm_ring_free(bp, ring,
2178 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2179 ring->fw_ring_id = INVALID_HW_RING_ID;
2180 if (BNXT_HAS_RING_GRPS(bp))
2181 bp->grp_info[queue_index].rx_fw_ring_id =
2183 memset(rxr->rx_desc_ring, 0,
2184 rxr->rx_ring_struct->ring_size *
2185 sizeof(*rxr->rx_desc_ring));
2186 memset(rxr->rx_buf_ring, 0,
2187 rxr->rx_ring_struct->ring_size *
2188 sizeof(*rxr->rx_buf_ring));
2191 ring = rxr->ag_ring_struct;
2192 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2193 bnxt_hwrm_ring_free(bp, ring,
2194 BNXT_CHIP_THOR(bp) ?
2195 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2196 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2197 ring->fw_ring_id = INVALID_HW_RING_ID;
2198 memset(rxr->ag_buf_ring, 0,
2199 rxr->ag_ring_struct->ring_size *
2200 sizeof(*rxr->ag_buf_ring));
2202 if (BNXT_HAS_RING_GRPS(bp))
2203 bp->grp_info[queue_index].ag_fw_ring_id =
2206 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2207 bnxt_free_cp_ring(bp, cpr);
2209 bnxt_free_nq_ring(bp, rxq->nq_ring);
2212 if (BNXT_HAS_RING_GRPS(bp))
2213 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2216 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2220 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2221 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2222 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2223 struct bnxt_ring *ring = txr->tx_ring_struct;
2224 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2226 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2227 bnxt_hwrm_ring_free(bp, ring,
2228 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2229 ring->fw_ring_id = INVALID_HW_RING_ID;
2230 memset(txr->tx_desc_ring, 0,
2231 txr->tx_ring_struct->ring_size *
2232 sizeof(*txr->tx_desc_ring));
2233 memset(txr->tx_buf_ring, 0,
2234 txr->tx_ring_struct->ring_size *
2235 sizeof(*txr->tx_buf_ring));
2239 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2240 bnxt_free_cp_ring(bp, cpr);
2241 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2243 bnxt_free_nq_ring(bp, txq->nq_ring);
2247 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2248 bnxt_free_hwrm_rx_ring(bp, i);
2253 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2258 if (!BNXT_HAS_RING_GRPS(bp))
2261 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2262 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2269 void bnxt_free_hwrm_resources(struct bnxt *bp)
2271 /* Release memzone */
2272 rte_free(bp->hwrm_cmd_resp_addr);
2273 rte_free(bp->hwrm_short_cmd_req_addr);
2274 bp->hwrm_cmd_resp_addr = NULL;
2275 bp->hwrm_short_cmd_req_addr = NULL;
2276 bp->hwrm_cmd_resp_dma_addr = 0;
2277 bp->hwrm_short_cmd_req_dma_addr = 0;
2280 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2282 struct rte_pci_device *pdev = bp->pdev;
2283 char type[RTE_MEMZONE_NAMESIZE];
2285 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2286 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2287 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2288 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2289 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2290 if (bp->hwrm_cmd_resp_addr == NULL)
2292 bp->hwrm_cmd_resp_dma_addr =
2293 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2294 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2296 "unable to map response address to physical memory\n");
2299 rte_spinlock_init(&bp->hwrm_lock);
2304 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2306 struct bnxt_filter_info *filter;
2309 STAILQ_FOREACH(filter, &vnic->filter, next) {
2310 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2311 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2312 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2313 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2315 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2316 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2324 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2326 struct bnxt_filter_info *filter;
2327 struct rte_flow *flow;
2330 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2331 filter = flow->filter;
2332 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2333 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2334 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2335 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2336 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2338 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2340 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2348 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2350 struct bnxt_filter_info *filter;
2353 STAILQ_FOREACH(filter, &vnic->filter, next) {
2354 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2355 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2357 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2358 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2361 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2369 void bnxt_free_tunnel_ports(struct bnxt *bp)
2371 if (bp->vxlan_port_cnt)
2372 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2373 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2375 if (bp->geneve_port_cnt)
2376 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2377 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2378 bp->geneve_port = 0;
2381 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2385 if (bp->vnic_info == NULL)
2389 * Cleanup VNICs in reverse order, to make sure the L2 filter
2390 * from vnic0 is last to be cleaned up.
2392 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2393 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2395 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2396 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2400 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2402 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2404 if (BNXT_CHIP_THOR(bp)) {
2405 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2406 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2407 vnic->fw_grp_ids[j]);
2408 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2410 vnic->num_lb_ctxts = 0;
2412 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2413 vnic->rss_rule = INVALID_HW_RING_ID;
2416 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2418 bnxt_hwrm_vnic_free(bp, vnic);
2420 rte_free(vnic->fw_grp_ids);
2422 /* Ring resources */
2423 bnxt_free_all_hwrm_rings(bp);
2424 bnxt_free_all_hwrm_ring_grps(bp);
2425 bnxt_free_all_hwrm_stat_ctxs(bp);
2426 bnxt_free_tunnel_ports(bp);
2429 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2431 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2433 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2434 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2436 switch (conf_link_speed) {
2437 case ETH_LINK_SPEED_10M_HD:
2438 case ETH_LINK_SPEED_100M_HD:
2440 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2442 return hw_link_duplex;
2445 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2447 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2450 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2452 uint16_t eth_link_speed = 0;
2454 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2455 return ETH_LINK_SPEED_AUTONEG;
2457 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2458 case ETH_LINK_SPEED_100M:
2459 case ETH_LINK_SPEED_100M_HD:
2462 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2464 case ETH_LINK_SPEED_1G:
2466 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2468 case ETH_LINK_SPEED_2_5G:
2470 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2472 case ETH_LINK_SPEED_10G:
2474 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2476 case ETH_LINK_SPEED_20G:
2478 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2480 case ETH_LINK_SPEED_25G:
2482 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2484 case ETH_LINK_SPEED_40G:
2486 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2488 case ETH_LINK_SPEED_50G:
2490 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2492 case ETH_LINK_SPEED_100G:
2494 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2498 "Unsupported link speed %d; default to AUTO\n",
2502 return eth_link_speed;
2505 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2506 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2507 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2508 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2510 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2514 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2517 if (link_speed & ETH_LINK_SPEED_FIXED) {
2518 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2520 if (one_speed & (one_speed - 1)) {
2522 "Invalid advertised speeds (%u) for port %u\n",
2523 link_speed, port_id);
2526 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2528 "Unsupported advertised speed (%u) for port %u\n",
2529 link_speed, port_id);
2533 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2535 "Unsupported advertised speeds (%u) for port %u\n",
2536 link_speed, port_id);
2544 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2548 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2549 if (bp->link_info.support_speeds)
2550 return bp->link_info.support_speeds;
2551 link_speed = BNXT_SUPPORTED_SPEEDS;
2554 if (link_speed & ETH_LINK_SPEED_100M)
2555 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2556 if (link_speed & ETH_LINK_SPEED_100M_HD)
2557 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2558 if (link_speed & ETH_LINK_SPEED_1G)
2559 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2560 if (link_speed & ETH_LINK_SPEED_2_5G)
2561 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2562 if (link_speed & ETH_LINK_SPEED_10G)
2563 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2564 if (link_speed & ETH_LINK_SPEED_20G)
2565 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2566 if (link_speed & ETH_LINK_SPEED_25G)
2567 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2568 if (link_speed & ETH_LINK_SPEED_40G)
2569 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2570 if (link_speed & ETH_LINK_SPEED_50G)
2571 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2572 if (link_speed & ETH_LINK_SPEED_100G)
2573 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2577 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2579 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2581 switch (hw_link_speed) {
2582 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2583 eth_link_speed = ETH_SPEED_NUM_100M;
2585 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2586 eth_link_speed = ETH_SPEED_NUM_1G;
2588 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2589 eth_link_speed = ETH_SPEED_NUM_2_5G;
2591 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2592 eth_link_speed = ETH_SPEED_NUM_10G;
2594 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2595 eth_link_speed = ETH_SPEED_NUM_20G;
2597 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2598 eth_link_speed = ETH_SPEED_NUM_25G;
2600 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2601 eth_link_speed = ETH_SPEED_NUM_40G;
2603 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2604 eth_link_speed = ETH_SPEED_NUM_50G;
2606 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2607 eth_link_speed = ETH_SPEED_NUM_100G;
2609 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2611 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2615 return eth_link_speed;
2618 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2620 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2622 switch (hw_link_duplex) {
2623 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2624 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2626 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2628 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2629 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2632 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2636 return eth_link_duplex;
2639 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2642 struct bnxt_link_info *link_info = &bp->link_info;
2644 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2647 "Get link config failed with rc %d\n", rc);
2650 if (link_info->link_speed)
2652 bnxt_parse_hw_link_speed(link_info->link_speed);
2654 link->link_speed = ETH_SPEED_NUM_NONE;
2655 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2656 link->link_status = link_info->link_up;
2657 link->link_autoneg = link_info->auto_mode ==
2658 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2659 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2664 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2667 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2668 struct bnxt_link_info link_req;
2669 uint16_t speed, autoneg;
2671 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2674 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2675 bp->eth_dev->data->port_id);
2679 memset(&link_req, 0, sizeof(link_req));
2680 link_req.link_up = link_up;
2684 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2685 if (BNXT_CHIP_THOR(bp) &&
2686 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2687 /* 40G is not supported as part of media auto detect.
2688 * The speed should be forced and autoneg disabled
2689 * to configure 40G speed.
2691 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2695 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2696 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2697 /* Autoneg can be done only when the FW allows.
2698 * When user configures fixed speed of 40G and later changes to
2699 * any other speed, auto_link_speed/force_link_speed is still set
2700 * to 40G until link comes up at new speed.
2703 !(!BNXT_CHIP_THOR(bp) &&
2704 (bp->link_info.auto_link_speed ||
2705 bp->link_info.force_link_speed))) {
2706 link_req.phy_flags |=
2707 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2708 link_req.auto_link_speed_mask =
2709 bnxt_parse_eth_link_speed_mask(bp,
2710 dev_conf->link_speeds);
2712 if (bp->link_info.phy_type ==
2713 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2714 bp->link_info.phy_type ==
2715 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2716 bp->link_info.media_type ==
2717 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2718 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2722 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2723 /* If user wants a particular speed try that first. */
2725 link_req.link_speed = speed;
2726 else if (bp->link_info.force_link_speed)
2727 link_req.link_speed = bp->link_info.force_link_speed;
2729 link_req.link_speed = bp->link_info.auto_link_speed;
2731 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2732 link_req.auto_pause = bp->link_info.auto_pause;
2733 link_req.force_pause = bp->link_info.force_pause;
2736 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2739 "Set link config failed with rc %d\n", rc);
2747 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2749 struct hwrm_func_qcfg_input req = {0};
2750 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2754 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2755 req.fid = rte_cpu_to_le_16(0xffff);
2757 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2759 HWRM_CHECK_RESULT();
2761 /* Hard Coded.. 0xfff VLAN ID mask */
2762 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2763 flags = rte_le_to_cpu_16(resp->flags);
2764 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2765 bp->flags |= BNXT_FLAG_MULTI_HOST;
2767 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2768 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2769 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2770 } else if (BNXT_VF(bp) &&
2771 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2772 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2773 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2779 switch (resp->port_partition_type) {
2780 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2781 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2782 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2784 bp->port_partition_type = resp->port_partition_type;
2787 bp->port_partition_type = 0;
2796 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2797 struct hwrm_func_qcaps_output *qcaps)
2799 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2800 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2801 sizeof(qcaps->mac_address));
2802 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2803 qcaps->max_rx_rings = fcfg->num_rx_rings;
2804 qcaps->max_tx_rings = fcfg->num_tx_rings;
2805 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2806 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2808 qcaps->first_vf_id = 0;
2809 qcaps->max_vnics = fcfg->num_vnics;
2810 qcaps->max_decap_records = 0;
2811 qcaps->max_encap_records = 0;
2812 qcaps->max_tx_wm_flows = 0;
2813 qcaps->max_tx_em_flows = 0;
2814 qcaps->max_rx_wm_flows = 0;
2815 qcaps->max_rx_em_flows = 0;
2816 qcaps->max_flow_id = 0;
2817 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2818 qcaps->max_sp_tx_rings = 0;
2819 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2822 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2824 struct hwrm_func_cfg_input req = {0};
2825 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2829 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2830 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2831 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2832 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2833 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2834 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2835 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2836 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2837 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2839 if (BNXT_HAS_RING_GRPS(bp)) {
2840 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2841 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2842 } else if (BNXT_HAS_NQ(bp)) {
2843 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2844 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2847 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2848 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2849 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2850 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2852 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2853 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2854 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2855 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2856 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2857 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2858 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2859 req.fid = rte_cpu_to_le_16(0xffff);
2860 req.enables = rte_cpu_to_le_32(enables);
2862 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2864 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2866 HWRM_CHECK_RESULT();
2872 static void populate_vf_func_cfg_req(struct bnxt *bp,
2873 struct hwrm_func_cfg_input *req,
2876 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2877 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2878 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2879 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2880 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2881 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2882 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2883 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2884 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2885 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2887 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2888 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2890 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2891 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2893 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2895 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2896 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2898 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2899 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2900 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2901 /* TODO: For now, do not support VMDq/RFS on VFs. */
2902 req->num_vnics = rte_cpu_to_le_16(1);
2903 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2907 static void add_random_mac_if_needed(struct bnxt *bp,
2908 struct hwrm_func_cfg_input *cfg_req,
2911 struct rte_ether_addr mac;
2913 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2916 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2918 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2919 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2920 bp->pf.vf_info[vf].random_mac = true;
2922 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2923 RTE_ETHER_ADDR_LEN);
2927 static void reserve_resources_from_vf(struct bnxt *bp,
2928 struct hwrm_func_cfg_input *cfg_req,
2931 struct hwrm_func_qcaps_input req = {0};
2932 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2935 /* Get the actual allocated values now */
2936 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2937 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2938 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2941 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2942 copy_func_cfg_to_qcaps(cfg_req, resp);
2943 } else if (resp->error_code) {
2944 rc = rte_le_to_cpu_16(resp->error_code);
2945 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2946 copy_func_cfg_to_qcaps(cfg_req, resp);
2949 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2950 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2951 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2952 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2953 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2954 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2956 * TODO: While not supporting VMDq with VFs, max_vnics is always
2957 * forced to 1 in this case
2959 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2960 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2965 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2967 struct hwrm_func_qcfg_input req = {0};
2968 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2971 /* Check for zero MAC address */
2972 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2973 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2974 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2975 HWRM_CHECK_RESULT();
2976 rc = rte_le_to_cpu_16(resp->vlan);
2983 static int update_pf_resource_max(struct bnxt *bp)
2985 struct hwrm_func_qcfg_input req = {0};
2986 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2989 /* And copy the allocated numbers into the pf struct */
2990 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2991 req.fid = rte_cpu_to_le_16(0xffff);
2992 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2993 HWRM_CHECK_RESULT();
2995 /* Only TX ring value reflects actual allocation? TODO */
2996 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2997 bp->pf.evb_mode = resp->evb_mode;
3004 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3009 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3013 rc = bnxt_hwrm_func_qcaps(bp);
3017 bp->pf.func_cfg_flags &=
3018 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3019 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3020 bp->pf.func_cfg_flags |=
3021 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3022 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3023 rc = __bnxt_hwrm_func_qcaps(bp);
3027 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3029 struct hwrm_func_cfg_input req = {0};
3030 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3037 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3041 rc = bnxt_hwrm_func_qcaps(bp);
3046 bp->pf.active_vfs = num_vfs;
3049 * First, configure the PF to only use one TX ring. This ensures that
3050 * there are enough rings for all VFs.
3052 * If we don't do this, when we call func_alloc() later, we will lock
3053 * extra rings to the PF that won't be available during func_cfg() of
3056 * This has been fixed with firmware versions above 20.6.54
3058 bp->pf.func_cfg_flags &=
3059 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3060 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3061 bp->pf.func_cfg_flags |=
3062 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3063 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3068 * Now, create and register a buffer to hold forwarded VF requests
3070 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3071 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3072 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3073 if (bp->pf.vf_req_buf == NULL) {
3077 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3078 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3079 for (i = 0; i < num_vfs; i++)
3080 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3081 (i * HWRM_MAX_REQ_LEN);
3083 rc = bnxt_hwrm_func_buf_rgtr(bp);
3087 populate_vf_func_cfg_req(bp, &req, num_vfs);
3089 bp->pf.active_vfs = 0;
3090 for (i = 0; i < num_vfs; i++) {
3091 add_random_mac_if_needed(bp, &req, i);
3093 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3094 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3095 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3096 rc = bnxt_hwrm_send_message(bp,
3101 /* Clear enable flag for next pass */
3102 req.enables &= ~rte_cpu_to_le_32(
3103 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3105 if (rc || resp->error_code) {
3107 "Failed to initizlie VF %d\n", i);
3109 "Not all VFs available. (%d, %d)\n",
3110 rc, resp->error_code);
3117 reserve_resources_from_vf(bp, &req, i);
3118 bp->pf.active_vfs++;
3119 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3123 * Now configure the PF to use "the rest" of the resources
3124 * We're using STD_TX_RING_MODE here though which will limit the TX
3125 * rings. This will allow QoS to function properly. Not setting this
3126 * will cause PF rings to break bandwidth settings.
3128 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3132 rc = update_pf_resource_max(bp);
3139 bnxt_hwrm_func_buf_unrgtr(bp);
3143 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3145 struct hwrm_func_cfg_input req = {0};
3146 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3149 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3151 req.fid = rte_cpu_to_le_16(0xffff);
3152 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3153 req.evb_mode = bp->pf.evb_mode;
3155 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3156 HWRM_CHECK_RESULT();
3162 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3163 uint8_t tunnel_type)
3165 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3166 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3169 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3170 req.tunnel_type = tunnel_type;
3171 req.tunnel_dst_port_val = port;
3172 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3173 HWRM_CHECK_RESULT();
3175 switch (tunnel_type) {
3176 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3177 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3178 bp->vxlan_port = port;
3180 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3181 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3182 bp->geneve_port = port;
3193 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3194 uint8_t tunnel_type)
3196 struct hwrm_tunnel_dst_port_free_input req = {0};
3197 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3200 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3202 req.tunnel_type = tunnel_type;
3203 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3204 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3206 HWRM_CHECK_RESULT();
3212 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3215 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3216 struct hwrm_func_cfg_input req = {0};
3219 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3221 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3222 req.flags = rte_cpu_to_le_32(flags);
3223 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3225 HWRM_CHECK_RESULT();
3231 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3233 uint32_t *flag = flagp;
3235 vnic->flags = *flag;
3238 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3240 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3243 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3246 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3247 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3249 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3251 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3252 req.req_buf_page_size = rte_cpu_to_le_16(
3253 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3254 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3255 req.req_buf_page_addr0 =
3256 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3257 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3259 "unable to map buffer address to physical memory\n");
3263 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3265 HWRM_CHECK_RESULT();
3271 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3274 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3275 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3277 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3280 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3282 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3284 HWRM_CHECK_RESULT();
3290 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3292 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3293 struct hwrm_func_cfg_input req = {0};
3296 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3298 req.fid = rte_cpu_to_le_16(0xffff);
3299 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3300 req.enables = rte_cpu_to_le_32(
3301 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3302 req.async_event_cr = rte_cpu_to_le_16(
3303 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3304 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3306 HWRM_CHECK_RESULT();
3312 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3314 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3315 struct hwrm_func_vf_cfg_input req = {0};
3318 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3320 req.enables = rte_cpu_to_le_32(
3321 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3322 req.async_event_cr = rte_cpu_to_le_16(
3323 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3324 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3326 HWRM_CHECK_RESULT();
3332 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3334 struct hwrm_func_cfg_input req = {0};
3335 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3336 uint16_t dflt_vlan, fid;
3337 uint32_t func_cfg_flags;
3340 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3343 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3344 fid = bp->pf.vf_info[vf].fid;
3345 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3347 fid = rte_cpu_to_le_16(0xffff);
3348 func_cfg_flags = bp->pf.func_cfg_flags;
3349 dflt_vlan = bp->vlan;
3352 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3353 req.fid = rte_cpu_to_le_16(fid);
3354 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3355 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3359 HWRM_CHECK_RESULT();
3365 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3366 uint16_t max_bw, uint16_t enables)
3368 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3369 struct hwrm_func_cfg_input req = {0};
3372 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3374 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3375 req.enables |= rte_cpu_to_le_32(enables);
3376 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3377 req.max_bw = rte_cpu_to_le_32(max_bw);
3378 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3380 HWRM_CHECK_RESULT();
3386 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3388 struct hwrm_func_cfg_input req = {0};
3389 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3392 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3394 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3395 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3396 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3397 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3399 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3401 HWRM_CHECK_RESULT();
3407 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3412 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3414 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3419 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3420 void *encaped, size_t ec_size)
3423 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3424 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3426 if (ec_size > sizeof(req.encap_request))
3429 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3431 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3432 memcpy(req.encap_request, encaped, ec_size);
3434 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3436 HWRM_CHECK_RESULT();
3442 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3443 struct rte_ether_addr *mac)
3445 struct hwrm_func_qcfg_input req = {0};
3446 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3449 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3451 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3452 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3454 HWRM_CHECK_RESULT();
3456 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3463 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3464 void *encaped, size_t ec_size)
3467 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3468 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3470 if (ec_size > sizeof(req.encap_request))
3473 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3475 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3476 memcpy(req.encap_request, encaped, ec_size);
3478 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3480 HWRM_CHECK_RESULT();
3486 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3487 struct rte_eth_stats *stats, uint8_t rx)
3490 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3491 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3493 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3495 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3497 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3499 HWRM_CHECK_RESULT();
3502 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3503 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3504 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3505 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3506 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3507 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3508 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3509 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3511 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3512 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3513 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3514 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3515 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3516 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3525 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3527 struct hwrm_port_qstats_input req = {0};
3528 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3529 struct bnxt_pf_info *pf = &bp->pf;
3532 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3534 req.port_id = rte_cpu_to_le_16(pf->port_id);
3535 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3536 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3537 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3539 HWRM_CHECK_RESULT();
3545 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3547 struct hwrm_port_clr_stats_input req = {0};
3548 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3549 struct bnxt_pf_info *pf = &bp->pf;
3552 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3553 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3554 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3557 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3559 req.port_id = rte_cpu_to_le_16(pf->port_id);
3560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3562 HWRM_CHECK_RESULT();
3568 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3570 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3571 struct hwrm_port_led_qcaps_input req = {0};
3577 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3578 req.port_id = bp->pf.port_id;
3579 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3581 HWRM_CHECK_RESULT();
3583 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3586 bp->num_leds = resp->num_leds;
3587 memcpy(bp->leds, &resp->led0_id,
3588 sizeof(bp->leds[0]) * bp->num_leds);
3589 for (i = 0; i < bp->num_leds; i++) {
3590 struct bnxt_led_info *led = &bp->leds[i];
3592 uint16_t caps = led->led_state_caps;
3594 if (!led->led_group_id ||
3595 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3607 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3609 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3610 struct hwrm_port_led_cfg_input req = {0};
3611 struct bnxt_led_cfg *led_cfg;
3612 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3613 uint16_t duration = 0;
3616 if (!bp->num_leds || BNXT_VF(bp))
3619 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3622 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3623 duration = rte_cpu_to_le_16(500);
3625 req.port_id = bp->pf.port_id;
3626 req.num_leds = bp->num_leds;
3627 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3628 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3629 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3630 led_cfg->led_id = bp->leds[i].led_id;
3631 led_cfg->led_state = led_state;
3632 led_cfg->led_blink_on = duration;
3633 led_cfg->led_blink_off = duration;
3634 led_cfg->led_group_id = bp->leds[i].led_group_id;
3637 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3639 HWRM_CHECK_RESULT();
3645 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3649 struct hwrm_nvm_get_dir_info_input req = {0};
3650 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3652 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3654 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3656 HWRM_CHECK_RESULT();
3658 *entries = rte_le_to_cpu_32(resp->entries);
3659 *length = rte_le_to_cpu_32(resp->entry_length);
3665 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3668 uint32_t dir_entries;
3669 uint32_t entry_length;
3672 rte_iova_t dma_handle;
3673 struct hwrm_nvm_get_dir_entries_input req = {0};
3674 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3676 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3680 *data++ = dir_entries;
3681 *data++ = entry_length;
3683 memset(data, 0xff, len);
3685 buflen = dir_entries * entry_length;
3686 buf = rte_malloc("nvm_dir", buflen, 0);
3687 rte_mem_lock_page(buf);
3690 dma_handle = rte_mem_virt2iova(buf);
3691 if (dma_handle == RTE_BAD_IOVA) {
3693 "unable to map response address to physical memory\n");
3696 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3697 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3698 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3701 memcpy(data, buf, len > buflen ? buflen : len);
3704 HWRM_CHECK_RESULT();
3710 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3711 uint32_t offset, uint32_t length,
3716 rte_iova_t dma_handle;
3717 struct hwrm_nvm_read_input req = {0};
3718 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3720 buf = rte_malloc("nvm_item", length, 0);
3721 rte_mem_lock_page(buf);
3725 dma_handle = rte_mem_virt2iova(buf);
3726 if (dma_handle == RTE_BAD_IOVA) {
3728 "unable to map response address to physical memory\n");
3731 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3732 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3733 req.dir_idx = rte_cpu_to_le_16(index);
3734 req.offset = rte_cpu_to_le_32(offset);
3735 req.len = rte_cpu_to_le_32(length);
3736 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3738 memcpy(data, buf, length);
3741 HWRM_CHECK_RESULT();
3747 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3750 struct hwrm_nvm_erase_dir_entry_input req = {0};
3751 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3753 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3754 req.dir_idx = rte_cpu_to_le_16(index);
3755 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3756 HWRM_CHECK_RESULT();
3763 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3764 uint16_t dir_ordinal, uint16_t dir_ext,
3765 uint16_t dir_attr, const uint8_t *data,
3769 struct hwrm_nvm_write_input req = {0};
3770 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3771 rte_iova_t dma_handle;
3774 buf = rte_malloc("nvm_write", data_len, 0);
3775 rte_mem_lock_page(buf);
3779 dma_handle = rte_mem_virt2iova(buf);
3780 if (dma_handle == RTE_BAD_IOVA) {
3782 "unable to map response address to physical memory\n");
3785 memcpy(buf, data, data_len);
3787 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3789 req.dir_type = rte_cpu_to_le_16(dir_type);
3790 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3791 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3792 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3793 req.dir_data_length = rte_cpu_to_le_32(data_len);
3794 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3796 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3799 HWRM_CHECK_RESULT();
3806 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3808 uint32_t *count = cbdata;
3810 *count = *count + 1;
3813 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3814 struct bnxt_vnic_info *vnic __rte_unused)
3819 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3823 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3824 &count, bnxt_vnic_count_hwrm_stub);
3829 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3832 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3833 struct hwrm_func_vf_vnic_ids_query_output *resp =
3834 bp->hwrm_cmd_resp_addr;
3837 /* First query all VNIC ids */
3838 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3840 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3841 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3842 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3844 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3847 "unable to map VNIC ID table address to physical memory\n");
3850 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3851 HWRM_CHECK_RESULT();
3852 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3860 * This function queries the VNIC IDs for a specified VF. It then calls
3861 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3862 * Then it calls the hwrm_cb function to program this new vnic configuration.
3864 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3865 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3866 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3868 struct bnxt_vnic_info vnic;
3870 int i, num_vnic_ids;
3875 /* First query all VNIC ids */
3876 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3877 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3878 RTE_CACHE_LINE_SIZE);
3879 if (vnic_ids == NULL)
3882 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3883 rte_mem_lock_page(((char *)vnic_ids) + sz);
3885 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3887 if (num_vnic_ids < 0)
3888 return num_vnic_ids;
3890 /* Retrieve VNIC, update bd_stall then update */
3892 for (i = 0; i < num_vnic_ids; i++) {
3893 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3894 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3895 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3898 if (vnic.mru <= 4) /* Indicates unallocated */
3901 vnic_cb(&vnic, cbdata);
3903 rc = hwrm_cb(bp, &vnic);
3913 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3916 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3917 struct hwrm_func_cfg_input req = {0};
3920 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3922 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3923 req.enables |= rte_cpu_to_le_32(
3924 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3925 req.vlan_antispoof_mode = on ?
3926 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3927 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3928 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3930 HWRM_CHECK_RESULT();
3936 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3938 struct bnxt_vnic_info vnic;
3941 int num_vnic_ids, i;
3945 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3946 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3947 RTE_CACHE_LINE_SIZE);
3948 if (vnic_ids == NULL)
3951 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3952 rte_mem_lock_page(((char *)vnic_ids) + sz);
3954 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3960 * Loop through to find the default VNIC ID.
3961 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3962 * by sending the hwrm_func_qcfg command to the firmware.
3964 for (i = 0; i < num_vnic_ids; i++) {
3965 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3966 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3967 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3968 bp->pf.first_vf_id + vf);
3971 if (vnic.func_default) {
3973 return vnic.fw_vnic_id;
3976 /* Could not find a default VNIC. */
3977 PMD_DRV_LOG(ERR, "No default VNIC\n");
3983 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3985 struct bnxt_filter_info *filter)
3988 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3989 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3990 uint32_t enables = 0;
3992 if (filter->fw_em_filter_id != UINT64_MAX)
3993 bnxt_hwrm_clear_em_filter(bp, filter);
3995 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3997 req.flags = rte_cpu_to_le_32(filter->flags);
3999 enables = filter->enables |
4000 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4001 req.dst_id = rte_cpu_to_le_16(dst_id);
4003 if (filter->ip_addr_type) {
4004 req.ip_addr_type = filter->ip_addr_type;
4005 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4008 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4009 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4011 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4012 memcpy(req.src_macaddr, filter->src_macaddr,
4013 RTE_ETHER_ADDR_LEN);
4015 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4016 memcpy(req.dst_macaddr, filter->dst_macaddr,
4017 RTE_ETHER_ADDR_LEN);
4019 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4020 req.ovlan_vid = filter->l2_ovlan;
4022 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4023 req.ivlan_vid = filter->l2_ivlan;
4025 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4026 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4028 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4029 req.ip_protocol = filter->ip_protocol;
4031 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4032 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4034 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4035 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4037 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4038 req.src_port = rte_cpu_to_be_16(filter->src_port);
4040 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4041 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4043 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4044 req.mirror_vnic_id = filter->mirror_vnic_id;
4046 req.enables = rte_cpu_to_le_32(enables);
4048 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4050 HWRM_CHECK_RESULT();
4052 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4058 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4061 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4062 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4064 if (filter->fw_em_filter_id == UINT64_MAX)
4067 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4068 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4070 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4072 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4074 HWRM_CHECK_RESULT();
4077 filter->fw_em_filter_id = UINT64_MAX;
4078 filter->fw_l2_filter_id = UINT64_MAX;
4083 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4085 struct bnxt_filter_info *filter)
4088 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4089 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4090 bp->hwrm_cmd_resp_addr;
4091 uint32_t enables = 0;
4093 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4094 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4096 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4098 req.flags = rte_cpu_to_le_32(filter->flags);
4100 enables = filter->enables |
4101 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4102 req.dst_id = rte_cpu_to_le_16(dst_id);
4105 if (filter->ip_addr_type) {
4106 req.ip_addr_type = filter->ip_addr_type;
4108 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4111 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4112 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4114 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4115 memcpy(req.src_macaddr, filter->src_macaddr,
4116 RTE_ETHER_ADDR_LEN);
4118 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4119 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4120 //RTE_ETHER_ADDR_LEN);
4122 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4123 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4125 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4126 req.ip_protocol = filter->ip_protocol;
4128 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4129 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4131 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4132 req.src_ipaddr_mask[0] =
4133 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4135 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4136 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4138 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4139 req.dst_ipaddr_mask[0] =
4140 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4142 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4143 req.src_port = rte_cpu_to_le_16(filter->src_port);
4145 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4146 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4148 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4149 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4151 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4152 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4154 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4155 req.mirror_vnic_id = filter->mirror_vnic_id;
4157 req.enables = rte_cpu_to_le_32(enables);
4159 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4161 HWRM_CHECK_RESULT();
4163 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4169 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4170 struct bnxt_filter_info *filter)
4173 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4174 struct hwrm_cfa_ntuple_filter_free_output *resp =
4175 bp->hwrm_cmd_resp_addr;
4177 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4180 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4182 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4184 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4186 HWRM_CHECK_RESULT();
4189 filter->fw_ntuple_filter_id = UINT64_MAX;
4195 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4197 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4198 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4199 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4200 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4201 uint16_t *ring_tbl = vnic->rss_table;
4202 int nr_ctxs = vnic->num_lb_ctxts;
4203 int max_rings = bp->rx_nr_rings;
4207 for (i = 0, k = 0; i < nr_ctxs; i++) {
4208 struct bnxt_rx_ring_info *rxr;
4209 struct bnxt_cp_ring_info *cpr;
4211 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4213 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4214 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4215 req.hash_mode_flags = vnic->hash_mode;
4217 req.ring_grp_tbl_addr =
4218 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4219 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4220 2 * sizeof(*ring_tbl));
4221 req.hash_key_tbl_addr =
4222 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4224 req.ring_table_pair_index = i;
4225 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4227 for (j = 0; j < 64; j++) {
4230 /* Find next active ring. */
4231 for (cnt = 0; cnt < max_rings; cnt++) {
4232 if (rx_queue_state[k] !=
4233 RTE_ETH_QUEUE_STATE_STOPPED)
4235 if (++k == max_rings)
4239 /* Return if no rings are active. */
4240 if (cnt == max_rings)
4243 /* Add rx/cp ring pair to RSS table. */
4244 rxr = rxqs[k]->rx_ring;
4245 cpr = rxqs[k]->cp_ring;
4247 ring_id = rxr->rx_ring_struct->fw_ring_id;
4248 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4249 ring_id = cpr->cp_ring_struct->fw_ring_id;
4250 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4252 if (++k == max_rings)
4255 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4258 HWRM_CHECK_RESULT();
4265 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4267 unsigned int rss_idx, fw_idx, i;
4269 if (!(vnic->rss_table && vnic->hash_type))
4272 if (BNXT_CHIP_THOR(bp))
4273 return bnxt_vnic_rss_configure_thor(bp, vnic);
4276 * Fill the RSS hash & redirection table with
4277 * ring group ids for all VNICs
4279 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4280 rss_idx++, fw_idx++) {
4281 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4282 fw_idx %= bp->rx_cp_nr_rings;
4283 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4287 if (i == bp->rx_cp_nr_rings)
4289 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4291 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4294 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4295 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4299 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4301 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4302 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4304 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4305 req->num_cmpl_dma_aggr_during_int =
4306 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4308 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4310 /* min timer set to 1/2 of interrupt timer */
4311 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4313 /* buf timer set to 1/4 of interrupt timer */
4314 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4316 req->cmpl_aggr_dma_tmr_during_int =
4317 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4319 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4320 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4321 req->flags = rte_cpu_to_le_16(flags);
4324 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4325 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4327 struct hwrm_ring_aggint_qcaps_input req = {0};
4328 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4333 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4334 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4335 HWRM_CHECK_RESULT();
4337 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4338 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4340 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4341 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4342 agg_req->flags = rte_cpu_to_le_16(flags);
4344 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4345 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4346 agg_req->enables = rte_cpu_to_le_32(enables);
4352 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4353 struct bnxt_coal *coal, uint16_t ring_id)
4355 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4356 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4357 bp->hwrm_cmd_resp_addr;
4360 /* Set ring coalesce parameters only for 100G NICs */
4361 if (BNXT_CHIP_THOR(bp)) {
4362 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4364 } else if (bnxt_stratus_device(bp)) {
4365 bnxt_hwrm_set_coal_params(coal, &req);
4370 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4371 req.ring_id = rte_cpu_to_le_16(ring_id);
4372 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4373 HWRM_CHECK_RESULT();
4378 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4379 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4381 struct hwrm_func_backing_store_qcaps_input req = {0};
4382 struct hwrm_func_backing_store_qcaps_output *resp =
4383 bp->hwrm_cmd_resp_addr;
4386 if (!BNXT_CHIP_THOR(bp) ||
4387 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4392 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4393 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4394 HWRM_CHECK_RESULT_SILENT();
4397 struct bnxt_ctx_pg_info *ctx_pg;
4398 struct bnxt_ctx_mem_info *ctx;
4399 int total_alloc_len;
4402 total_alloc_len = sizeof(*ctx);
4403 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4404 RTE_CACHE_LINE_SIZE);
4409 memset(ctx, 0, total_alloc_len);
4411 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4412 sizeof(*ctx_pg) * BNXT_MAX_Q,
4413 RTE_CACHE_LINE_SIZE);
4418 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4419 ctx->tqm_mem[i] = ctx_pg;
4422 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4423 ctx->qp_min_qp1_entries =
4424 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4425 ctx->qp_max_l2_entries =
4426 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4427 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4428 ctx->srq_max_l2_entries =
4429 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4430 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4431 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4432 ctx->cq_max_l2_entries =
4433 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4434 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4435 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4436 ctx->vnic_max_vnic_entries =
4437 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4438 ctx->vnic_max_ring_table_entries =
4439 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4440 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4441 ctx->stat_max_entries =
4442 rte_le_to_cpu_32(resp->stat_max_entries);
4443 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4444 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4445 ctx->tqm_min_entries_per_ring =
4446 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4447 ctx->tqm_max_entries_per_ring =
4448 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4449 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4450 if (!ctx->tqm_entries_multiple)
4451 ctx->tqm_entries_multiple = 1;
4452 ctx->mrav_max_entries =
4453 rte_le_to_cpu_32(resp->mrav_max_entries);
4454 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4455 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4456 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4465 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4467 struct hwrm_func_backing_store_cfg_input req = {0};
4468 struct hwrm_func_backing_store_cfg_output *resp =
4469 bp->hwrm_cmd_resp_addr;
4470 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4471 struct bnxt_ctx_pg_info *ctx_pg;
4472 uint32_t *num_entries;
4481 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4482 req.enables = rte_cpu_to_le_32(enables);
4484 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4485 ctx_pg = &ctx->qp_mem;
4486 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4487 req.qp_num_qp1_entries =
4488 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4489 req.qp_num_l2_entries =
4490 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4491 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4492 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4493 &req.qpc_pg_size_qpc_lvl,
4497 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4498 ctx_pg = &ctx->srq_mem;
4499 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4500 req.srq_num_l2_entries =
4501 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4502 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4503 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4504 &req.srq_pg_size_srq_lvl,
4508 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4509 ctx_pg = &ctx->cq_mem;
4510 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4511 req.cq_num_l2_entries =
4512 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4513 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4514 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4515 &req.cq_pg_size_cq_lvl,
4519 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4520 ctx_pg = &ctx->vnic_mem;
4521 req.vnic_num_vnic_entries =
4522 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4523 req.vnic_num_ring_table_entries =
4524 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4525 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4526 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4527 &req.vnic_pg_size_vnic_lvl,
4528 &req.vnic_page_dir);
4531 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4532 ctx_pg = &ctx->stat_mem;
4533 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4534 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4535 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4536 &req.stat_pg_size_stat_lvl,
4537 &req.stat_page_dir);
4540 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4541 num_entries = &req.tqm_sp_num_entries;
4542 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4543 pg_dir = &req.tqm_sp_page_dir;
4544 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4545 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4546 if (!(enables & ena))
4549 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4551 ctx_pg = ctx->tqm_mem[i];
4552 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4553 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4556 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4557 HWRM_CHECK_RESULT();
4563 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4565 struct hwrm_port_qstats_ext_input req = {0};
4566 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4567 struct bnxt_pf_info *pf = &bp->pf;
4570 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4571 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4574 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4576 req.port_id = rte_cpu_to_le_16(pf->port_id);
4577 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4578 req.tx_stat_host_addr =
4579 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4581 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4583 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4584 req.rx_stat_host_addr =
4585 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4587 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4589 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4592 bp->fw_rx_port_stats_ext_size = 0;
4593 bp->fw_tx_port_stats_ext_size = 0;
4595 bp->fw_rx_port_stats_ext_size =
4596 rte_le_to_cpu_16(resp->rx_stat_size);
4597 bp->fw_tx_port_stats_ext_size =
4598 rte_le_to_cpu_16(resp->tx_stat_size);
4601 HWRM_CHECK_RESULT();
4608 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4610 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4611 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4612 bp->hwrm_cmd_resp_addr;
4615 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4616 req.tunnel_type = type;
4617 req.dest_fid = bp->fw_fid;
4618 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4619 HWRM_CHECK_RESULT();
4627 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4629 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4630 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4631 bp->hwrm_cmd_resp_addr;
4634 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4635 req.tunnel_type = type;
4636 req.dest_fid = bp->fw_fid;
4637 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4638 HWRM_CHECK_RESULT();
4645 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4647 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4648 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4649 bp->hwrm_cmd_resp_addr;
4652 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4653 req.src_fid = bp->fw_fid;
4654 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4655 HWRM_CHECK_RESULT();
4658 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4665 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4668 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4669 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4670 bp->hwrm_cmd_resp_addr;
4673 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4674 req.src_fid = bp->fw_fid;
4675 req.tunnel_type = tun_type;
4676 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4677 HWRM_CHECK_RESULT();
4680 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4682 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4689 int bnxt_hwrm_set_mac(struct bnxt *bp)
4691 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4692 struct hwrm_func_vf_cfg_input req = {0};
4698 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4701 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4702 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4704 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4706 HWRM_CHECK_RESULT();
4708 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4714 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4716 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4717 struct hwrm_func_drv_if_change_input req = {0};
4721 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4724 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4725 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4726 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4728 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4731 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4735 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4737 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4739 HWRM_CHECK_RESULT();
4740 flags = rte_le_to_cpu_32(resp->flags);
4743 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4744 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4745 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4751 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4753 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4754 struct bnxt_error_recovery_info *info = bp->recovery_info;
4755 struct hwrm_error_recovery_qcfg_input req = {0};
4760 /* Older FW does not have error recovery support */
4761 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4765 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4767 bp->recovery_info = info;
4771 memset(info, 0, sizeof(*info));
4774 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4776 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4778 HWRM_CHECK_RESULT();
4780 flags = rte_le_to_cpu_32(resp->flags);
4781 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4782 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4783 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4784 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4786 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4787 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4792 /* FW returned values are in units of 100msec */
4793 info->driver_polling_freq =
4794 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4795 info->master_func_wait_period =
4796 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4797 info->normal_func_wait_period =
4798 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4799 info->master_func_wait_period_after_reset =
4800 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4801 info->max_bailout_time_after_reset =
4802 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4803 info->status_regs[BNXT_FW_STATUS_REG] =
4804 rte_le_to_cpu_32(resp->fw_health_status_reg);
4805 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4806 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4807 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4808 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4809 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4810 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4811 info->reg_array_cnt =
4812 rte_le_to_cpu_32(resp->reg_array_cnt);
4814 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4819 for (i = 0; i < info->reg_array_cnt; i++) {
4820 info->reset_reg[i] =
4821 rte_le_to_cpu_32(resp->reset_reg[i]);
4822 info->reset_reg_val[i] =
4823 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4824 info->delay_after_reset[i] =
4825 resp->delay_after_reset[i];
4830 /* Map the FW status registers */
4832 rc = bnxt_map_fw_health_status_regs(bp);
4835 rte_free(bp->recovery_info);
4836 bp->recovery_info = NULL;
4841 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4843 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4844 struct hwrm_fw_reset_input req = {0};
4850 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4852 req.embedded_proc_type =
4853 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4854 req.selfrst_status =
4855 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4856 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4858 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4861 HWRM_CHECK_RESULT();
4867 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4869 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4870 struct hwrm_port_ts_query_input req = {0};
4871 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4878 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4881 case BNXT_PTP_FLAGS_PATH_TX:
4882 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4884 case BNXT_PTP_FLAGS_PATH_RX:
4885 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4887 case BNXT_PTP_FLAGS_CURRENT_TIME:
4888 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4892 req.flags = rte_cpu_to_le_32(flags);
4893 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4895 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4897 HWRM_CHECK_RESULT();
4900 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
4902 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;