1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(void *) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages > 1) {
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
103 timeout = bp->hwrm_cmd_timeout;
105 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
106 msg_len > bp->max_req_len) {
107 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
109 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
110 memcpy(short_cmd_req, req, msg_len);
112 short_input.req_type = rte_cpu_to_le_16(req->req_type);
113 short_input.signature = rte_cpu_to_le_16(
114 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
115 short_input.size = rte_cpu_to_le_16(msg_len);
116 short_input.req_addr =
117 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
119 data = (uint32_t *)&short_input;
120 msg_len = sizeof(short_input);
122 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
125 /* Write request msg to hwrm channel */
126 for (i = 0; i < msg_len; i += 4) {
127 bar = (uint8_t *)bp->bar0 + bar_offset + i;
128 rte_write32(*data, bar);
132 /* Zero the rest of the request space */
133 for (; i < max_req_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + bar_offset + i;
138 /* Ring channel doorbell */
139 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
142 * Make sure the channel doorbell ring command complete before
143 * reading the response to avoid getting stale or invalid
148 /* Poll for the valid bit */
149 for (i = 0; i < timeout; i++) {
150 /* Sanity check on the resp->resp_len */
152 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
153 /* Last byte of resp contains the valid key */
154 valid = (uint8_t *)resp + resp->resp_len - 1;
155 if (*valid == HWRM_RESP_VALID_KEY)
162 /* Suppress VER_GET timeout messages during reset recovery */
163 if (bp->flags & BNXT_FLAG_FW_RESET &&
164 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
168 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
169 req->req_type, req->seq_id);
176 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
177 * spinlock, and does initial processing.
179 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
180 * releases the spinlock only if it returns. If the regular int return codes
181 * are not used by the function, HWRM_CHECK_RESULT() should not be used
182 * directly, rather it should be copied and modified to suit the function.
184 * HWRM_UNLOCK() must be called after all response processing is completed.
186 #define HWRM_PREP(req, type, kong) do { \
187 rte_spinlock_lock(&bp->hwrm_lock); \
188 if (bp->hwrm_cmd_resp_addr == NULL) { \
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 (req)->req_type = rte_cpu_to_le_16(type); \
194 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
195 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
197 (req)->target_id = rte_cpu_to_le_16(0xffff); \
198 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
219 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
221 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
223 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
225 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
231 if (resp->error_code) { \
232 rc = rte_le_to_cpu_16(resp->error_code); \
233 if (resp->resp_len >= 16) { \
234 struct hwrm_err_output *tmp_hwrm_err_op = \
237 "error %d:%d:%08x:%04x\n", \
238 rc, tmp_hwrm_err_op->cmd_err, \
240 tmp_hwrm_err_op->opaque_0), \
242 tmp_hwrm_err_op->opaque_1)); \
244 PMD_DRV_LOG(ERR, "error %d\n", rc); \
246 rte_spinlock_unlock(&bp->hwrm_lock); \
247 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
249 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
251 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
253 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
255 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
263 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
274 bool mailbox = BNXT_USE_CHIMP_MB;
275 struct input *req = msg;
276 struct output *resp = bp->hwrm_cmd_resp_addr;
279 mailbox = BNXT_USE_KONG(bp);
281 HWRM_PREP(req, msg_type, mailbox);
283 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
288 memcpy(resp_msg, resp, resp_len);
295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
299 uint32_t *tf_response_code,
303 uint32_t response_len)
306 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
307 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
308 bool mailbox = BNXT_USE_CHIMP_MB;
310 if (msg_len > sizeof(req.tf_req))
314 mailbox = BNXT_USE_KONG(bp);
316 HWRM_PREP(&req, HWRM_TF, mailbox);
317 /* Build request using the user supplied request payload.
318 * TLV request size is checked at build time against HWRM
319 * request max size, thus no checking required.
321 req.tf_type = tf_type;
322 req.tf_subtype = tf_subtype;
323 memcpy(req.tf_req, msg, msg_len);
325 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
328 /* Copy the resp to user provided response buffer */
329 if (response != NULL)
330 /* Post process response data. We need to copy only
331 * the 'payload' as the HWRM data structure really is
332 * HWRM header + msg header + payload and the TFLIB
333 * only provided a payload place holder.
335 if (response_len != 0) {
341 /* Extract the internal tflib response code */
342 *tf_response_code = resp->tf_resp_code;
348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
351 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
352 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
354 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
355 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
358 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
367 struct bnxt_vnic_info *vnic,
369 struct bnxt_vlan_table_entry *vlan_table)
372 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
376 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
379 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
380 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
382 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
383 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
384 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
385 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
387 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
388 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
390 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
391 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
392 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
393 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
394 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
395 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
398 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
399 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
400 req.vlan_tag_tbl_addr =
401 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
402 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
404 req.mask = rte_cpu_to_le_32(mask);
406 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
416 struct bnxt_vlan_antispoof_table_entry *vlan_table)
419 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
420 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
421 bp->hwrm_cmd_resp_addr;
424 * Older HWRM versions did not support this command, and the set_rx_mask
425 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
426 * removed from set_rx_mask call, and this command was added.
428 * This command is also present from 1.7.8.11 and higher,
431 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
432 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
433 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
438 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
439 req.fid = rte_cpu_to_le_16(fid);
441 req.vlan_tag_mask_tbl_addr =
442 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
443 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
445 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
454 struct bnxt_filter_info *filter)
457 struct bnxt_filter_info *l2_filter = filter;
458 struct bnxt_vnic_info *vnic = NULL;
459 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
460 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
462 if (filter->fw_l2_filter_id == UINT64_MAX)
465 if (filter->matching_l2_fltr_ptr)
466 l2_filter = filter->matching_l2_fltr_ptr;
468 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
469 filter, l2_filter, l2_filter->l2_ref_cnt);
471 if (l2_filter->l2_ref_cnt == 0)
474 if (l2_filter->l2_ref_cnt > 0)
475 l2_filter->l2_ref_cnt--;
477 if (l2_filter->l2_ref_cnt > 0)
480 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
482 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
489 filter->fw_l2_filter_id = UINT64_MAX;
490 if (l2_filter->l2_ref_cnt == 0) {
491 vnic = l2_filter->vnic;
493 STAILQ_REMOVE(&vnic->filter, l2_filter,
494 bnxt_filter_info, next);
495 bnxt_free_filter(bp, l2_filter);
502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
504 struct bnxt_filter_info *filter)
507 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
508 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
509 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
510 const struct rte_eth_vmdq_rx_conf *conf =
511 &dev_conf->rx_adv_conf.vmdq_rx_conf;
512 uint32_t enables = 0;
513 uint16_t j = dst_id - 1;
515 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
516 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
517 conf->pool_map[j].pools & (1UL << j)) {
519 "Add vlan %u to vmdq pool %u\n",
520 conf->pool_map[j].vlan_id, j);
522 filter->l2_ivlan = conf->pool_map[j].vlan_id;
524 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
525 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
528 if (filter->fw_l2_filter_id != UINT64_MAX)
529 bnxt_hwrm_clear_l2_filter(bp, filter);
531 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
533 /* PMD does not support XDP and RoCE */
534 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
535 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
536 req.flags = rte_cpu_to_le_32(filter->flags);
538 enables = filter->enables |
539 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
540 req.dst_id = rte_cpu_to_le_16(dst_id);
543 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
544 memcpy(req.l2_addr, filter->l2_addr,
547 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
548 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
551 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
552 req.l2_ovlan = filter->l2_ovlan;
554 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
555 req.l2_ivlan = filter->l2_ivlan;
557 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
558 req.l2_ovlan_mask = filter->l2_ovlan_mask;
560 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
561 req.l2_ivlan_mask = filter->l2_ivlan_mask;
562 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
563 req.src_id = rte_cpu_to_le_32(filter->src_id);
564 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
565 req.src_type = filter->src_type;
566 if (filter->pri_hint) {
567 req.pri_hint = filter->pri_hint;
568 req.l2_filter_id_hint =
569 rte_cpu_to_le_64(filter->l2_filter_id_hint);
572 req.enables = rte_cpu_to_le_32(enables);
574 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
578 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
579 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
582 filter->l2_ref_cnt++;
587 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
589 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
590 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
597 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
600 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
603 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
604 if (ptp->tx_tstamp_en)
605 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
608 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
609 req.flags = rte_cpu_to_le_32(flags);
610 req.enables = rte_cpu_to_le_32
611 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
612 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
614 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
620 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
623 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
624 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
625 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
630 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
632 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
634 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
638 if (!BNXT_CHIP_THOR(bp) &&
639 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
642 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
643 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
645 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
649 if (!BNXT_CHIP_THOR(bp)) {
650 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
651 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
652 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
653 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
654 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
655 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
656 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
657 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
658 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
659 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
660 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
661 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
662 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
663 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
664 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
665 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
666 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
667 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
676 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
680 for (i = 0; i < bp->pf->max_vfs; i++) {
681 rte_free(bp->pf->vf_info[i].vlan_table);
682 bp->pf->vf_info[i].vlan_table = NULL;
683 rte_free(bp->pf->vf_info[i].vlan_as_table);
684 bp->pf->vf_info[i].vlan_as_table = NULL;
686 rte_free(bp->pf->vf_info);
687 bp->pf->vf_info = NULL;
690 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
693 struct hwrm_func_qcaps_input req = {.req_type = 0 };
694 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
695 uint16_t new_max_vfs;
699 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
701 req.fid = rte_cpu_to_le_16(0xffff);
703 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
707 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
708 flags = rte_le_to_cpu_32(resp->flags);
710 bp->pf->port_id = resp->port_id;
711 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
712 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
713 new_max_vfs = bp->pdev->max_vfs;
714 if (new_max_vfs != bp->pf->max_vfs) {
716 bnxt_hwrm_free_vf_info(bp);
717 bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
718 sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
719 if (bp->pf->vf_info == NULL) {
720 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
723 bp->pf->max_vfs = new_max_vfs;
724 for (i = 0; i < new_max_vfs; i++) {
725 bp->pf->vf_info[i].fid =
726 bp->pf->first_vf_id + i;
727 bp->pf->vf_info[i].vlan_table =
728 rte_zmalloc("VF VLAN table",
731 if (bp->pf->vf_info[i].vlan_table == NULL)
733 "Fail to alloc VLAN table for VF %d\n",
737 bp->pf->vf_info[i].vlan_table);
738 bp->pf->vf_info[i].vlan_as_table =
739 rte_zmalloc("VF VLAN AS table",
742 if (bp->pf->vf_info[i].vlan_as_table == NULL)
744 "Alloc VLAN AS table for VF %d fail\n",
748 bp->pf->vf_info[i].vlan_as_table);
749 STAILQ_INIT(&bp->pf->vf_info[i].filter);
754 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
755 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
756 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
757 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
759 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
761 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
762 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
763 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
764 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
765 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
766 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
767 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
768 if (!BNXT_CHIP_THOR(bp))
769 bp->max_l2_ctx += bp->max_rx_em_flows;
770 /* TODO: For now, do not support VMDq/RFS on VFs. */
775 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
779 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
780 bp->max_l2_ctx, bp->max_vnics);
781 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
783 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
784 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
785 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
786 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
788 bnxt_hwrm_ptp_qcfg(bp);
792 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
793 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
795 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
796 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
797 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
800 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
801 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
803 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
804 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
811 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
815 rc = __bnxt_hwrm_func_qcaps(bp);
816 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
817 rc = bnxt_alloc_ctx_mem(bp);
821 rc = bnxt_hwrm_func_resc_qcaps(bp);
823 bp->flags |= BNXT_FLAG_NEW_RM;
827 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
828 * But the error can be ignored. Return success.
834 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
835 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
838 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
839 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
841 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
843 req.target_id = rte_cpu_to_le_16(0xffff);
845 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
849 if (rte_le_to_cpu_32(resp->flags) &
850 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
851 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
852 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
855 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
862 int bnxt_hwrm_func_reset(struct bnxt *bp)
865 struct hwrm_func_reset_input req = {.req_type = 0 };
866 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
868 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
870 req.enables = rte_cpu_to_le_32(0);
872 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
880 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
884 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
885 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
887 if (bp->flags & BNXT_FLAG_REGISTERED)
890 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
891 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
892 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
893 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
895 /* PFs and trusted VFs should indicate the support of the
896 * Master capability on non Stingray platform
898 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
899 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
901 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
902 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
903 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
904 req.ver_maj = RTE_VER_YEAR;
905 req.ver_min = RTE_VER_MONTH;
906 req.ver_upd = RTE_VER_MINOR;
909 req.enables |= rte_cpu_to_le_32(
910 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
911 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
912 RTE_MIN(sizeof(req.vf_req_fwd),
913 sizeof(bp->pf->vf_req_fwd)));
916 * PF can sniff HWRM API issued by VF. This can be set up by
917 * linux driver and inherited by the DPDK PF driver. Clear
918 * this HWRM sniffer list in FW because DPDK PF driver does
921 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
924 req.flags = rte_cpu_to_le_32(flags);
926 req.async_event_fwd[0] |=
927 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
928 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
929 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
930 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
931 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
932 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
933 req.async_event_fwd[0] |=
934 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
935 req.async_event_fwd[1] |=
936 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
937 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
939 req.async_event_fwd[1] |=
940 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
942 if (BNXT_VF_IS_TRUSTED(bp))
943 req.async_event_fwd[1] |=
944 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
946 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
950 flags = rte_le_to_cpu_32(resp->flags);
951 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
952 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
956 bp->flags |= BNXT_FLAG_REGISTERED;
961 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
963 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
966 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
969 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
974 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
975 struct hwrm_func_vf_cfg_input req = {0};
977 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
979 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
980 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
981 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
982 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
983 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
985 if (BNXT_HAS_RING_GRPS(bp)) {
986 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
987 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
990 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
991 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
992 AGG_RING_MULTIPLIER);
993 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
994 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
996 BNXT_NUM_ASYNC_CPR(bp));
997 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
998 if (bp->vf_resv_strategy ==
999 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1000 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1001 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1002 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1003 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1004 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1005 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1006 } else if (bp->vf_resv_strategy ==
1007 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1008 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1009 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1013 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1014 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1015 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1016 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1017 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1018 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1020 if (test && BNXT_HAS_RING_GRPS(bp))
1021 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1023 req.flags = rte_cpu_to_le_32(flags);
1024 req.enables |= rte_cpu_to_le_32(enables);
1026 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1029 HWRM_CHECK_RESULT_SILENT();
1031 HWRM_CHECK_RESULT();
1037 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1040 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1041 struct hwrm_func_resource_qcaps_input req = {0};
1043 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1044 req.fid = rte_cpu_to_le_16(0xffff);
1046 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1048 HWRM_CHECK_RESULT_SILENT();
1051 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1052 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1053 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1054 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1055 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1056 /* func_resource_qcaps does not return max_rx_em_flows.
1057 * So use the value provided by func_qcaps.
1059 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1060 if (!BNXT_CHIP_THOR(bp))
1061 bp->max_l2_ctx += bp->max_rx_em_flows;
1062 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1063 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1065 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1066 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1067 if (bp->vf_resv_strategy >
1068 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1069 bp->vf_resv_strategy =
1070 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1076 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1079 struct hwrm_ver_get_input req = {.req_type = 0 };
1080 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1081 uint32_t fw_version;
1082 uint16_t max_resp_len;
1083 char type[RTE_MEMZONE_NAMESIZE];
1084 uint32_t dev_caps_cfg;
1086 bp->max_req_len = HWRM_MAX_REQ_LEN;
1087 bp->hwrm_cmd_timeout = timeout;
1088 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1090 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1091 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1092 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1094 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1096 if (bp->flags & BNXT_FLAG_FW_RESET)
1097 HWRM_CHECK_RESULT_SILENT();
1099 HWRM_CHECK_RESULT();
1101 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1102 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1103 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1104 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1105 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1106 (resp->hwrm_fw_min_8b << 16) |
1107 (resp->hwrm_fw_bld_8b << 8) |
1108 resp->hwrm_fw_rsvd_8b;
1109 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1110 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1112 fw_version = resp->hwrm_intf_maj_8b << 16;
1113 fw_version |= resp->hwrm_intf_min_8b << 8;
1114 fw_version |= resp->hwrm_intf_upd_8b;
1115 bp->hwrm_spec_code = fw_version;
1117 /* def_req_timeout value is in milliseconds */
1118 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1119 /* convert timeout to usec */
1120 bp->hwrm_cmd_timeout *= 1000;
1121 if (!bp->hwrm_cmd_timeout)
1122 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1124 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1125 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1130 if (bp->max_req_len > resp->max_req_win_len) {
1131 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1134 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1135 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1136 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1137 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1139 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1140 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1142 if (bp->max_resp_len != max_resp_len) {
1143 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1144 bp->pdev->addr.domain, bp->pdev->addr.bus,
1145 bp->pdev->addr.devid, bp->pdev->addr.function);
1147 rte_free(bp->hwrm_cmd_resp_addr);
1149 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1150 if (bp->hwrm_cmd_resp_addr == NULL) {
1154 bp->hwrm_cmd_resp_dma_addr =
1155 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1156 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1158 "Unable to map response buffer to physical memory.\n");
1162 bp->max_resp_len = max_resp_len;
1166 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1168 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1169 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1170 bp->flags |= BNXT_FLAG_SHORT_CMD;
1173 if (((dev_caps_cfg &
1174 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1176 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1177 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1178 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1179 bp->pdev->addr.domain, bp->pdev->addr.bus,
1180 bp->pdev->addr.devid, bp->pdev->addr.function);
1182 rte_free(bp->hwrm_short_cmd_req_addr);
1184 bp->hwrm_short_cmd_req_addr =
1185 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1186 if (bp->hwrm_short_cmd_req_addr == NULL) {
1190 bp->hwrm_short_cmd_req_dma_addr =
1191 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1192 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1193 rte_free(bp->hwrm_short_cmd_req_addr);
1195 "Unable to map buffer to physical memory.\n");
1201 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1202 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1203 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1206 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1207 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1209 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1210 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1211 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1215 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1216 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1217 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1226 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1229 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1230 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1232 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1235 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1238 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1240 HWRM_CHECK_RESULT();
1246 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1249 struct hwrm_port_phy_cfg_input req = {0};
1250 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1251 uint32_t enables = 0;
1253 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1255 if (conf->link_up) {
1256 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1257 if (bp->link_info->auto_mode && conf->link_speed) {
1258 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1259 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1262 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1263 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1264 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1266 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1267 * any auto mode, even "none".
1269 if (!conf->link_speed) {
1270 /* No speeds specified. Enable AutoNeg - all speeds */
1272 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1274 /* AutoNeg - Advertise speeds specified. */
1275 if (conf->auto_link_speed_mask &&
1276 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1278 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1279 req.auto_link_speed_mask =
1280 conf->auto_link_speed_mask;
1282 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1285 req.auto_duplex = conf->duplex;
1286 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1287 req.auto_pause = conf->auto_pause;
1288 req.force_pause = conf->force_pause;
1289 /* Set force_pause if there is no auto or if there is a force */
1290 if (req.auto_pause && !req.force_pause)
1291 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1293 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1295 req.enables = rte_cpu_to_le_32(enables);
1298 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1299 PMD_DRV_LOG(INFO, "Force Link Down\n");
1302 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1304 HWRM_CHECK_RESULT();
1310 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1311 struct bnxt_link_info *link_info)
1314 struct hwrm_port_phy_qcfg_input req = {0};
1315 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1317 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1319 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1321 HWRM_CHECK_RESULT();
1323 link_info->phy_link_status = resp->link;
1324 link_info->link_up =
1325 (link_info->phy_link_status ==
1326 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1327 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1328 link_info->duplex = resp->duplex_cfg;
1329 link_info->pause = resp->pause;
1330 link_info->auto_pause = resp->auto_pause;
1331 link_info->force_pause = resp->force_pause;
1332 link_info->auto_mode = resp->auto_mode;
1333 link_info->phy_type = resp->phy_type;
1334 link_info->media_type = resp->media_type;
1336 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1337 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1338 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1339 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1340 link_info->phy_ver[0] = resp->phy_maj;
1341 link_info->phy_ver[1] = resp->phy_min;
1342 link_info->phy_ver[2] = resp->phy_bld;
1346 PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1347 link_info->link_speed, link_info->auto_mode,
1348 link_info->auto_link_speed, link_info->auto_link_speed_mask,
1349 link_info->support_speeds, link_info->force_link_speed);
1353 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1356 struct hwrm_port_phy_qcaps_input req = {0};
1357 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1359 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1362 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1364 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1366 HWRM_CHECK_RESULT();
1368 bp->port_cnt = resp->port_cnt;
1375 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1379 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1380 if (bp->tx_cos_queue[i].profile ==
1381 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1382 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1389 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1393 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1394 if (bp->tx_cos_queue[i].profile !=
1395 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1396 bp->tx_cos_queue[i].id !=
1397 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1398 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1404 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1407 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1408 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1409 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1413 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1415 req.flags = rte_cpu_to_le_32(dir);
1416 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1417 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1418 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1420 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1421 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1423 HWRM_CHECK_RESULT();
1425 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1426 GET_TX_QUEUE_INFO(0);
1427 GET_TX_QUEUE_INFO(1);
1428 GET_TX_QUEUE_INFO(2);
1429 GET_TX_QUEUE_INFO(3);
1430 GET_TX_QUEUE_INFO(4);
1431 GET_TX_QUEUE_INFO(5);
1432 GET_TX_QUEUE_INFO(6);
1433 GET_TX_QUEUE_INFO(7);
1435 GET_RX_QUEUE_INFO(0);
1436 GET_RX_QUEUE_INFO(1);
1437 GET_RX_QUEUE_INFO(2);
1438 GET_RX_QUEUE_INFO(3);
1439 GET_RX_QUEUE_INFO(4);
1440 GET_RX_QUEUE_INFO(5);
1441 GET_RX_QUEUE_INFO(6);
1442 GET_RX_QUEUE_INFO(7);
1447 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1450 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1451 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1455 /* iterate and find the COSq profile to use for Tx */
1456 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1457 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1458 if (bp->tx_cos_queue[i].id != 0xff)
1459 bp->tx_cosq_id[j++] =
1460 bp->tx_cos_queue[i].id;
1463 /* When CoS classification is disabled, for normal NIC
1464 * operations, ideally we should look to use LOSSY.
1465 * If not found, fallback to the first valid profile
1467 if (!bnxt_find_lossy_profile(bp))
1468 bnxt_find_first_valid_profile(bp);
1473 bp->max_tc = resp->max_configurable_queues;
1474 bp->max_lltc = resp->max_configurable_lossless_queues;
1475 if (bp->max_tc > BNXT_MAX_QUEUE)
1476 bp->max_tc = BNXT_MAX_QUEUE;
1477 bp->max_q = bp->max_tc;
1479 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1480 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1488 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1489 struct bnxt_ring *ring,
1490 uint32_t ring_type, uint32_t map_index,
1491 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1492 uint16_t tx_cosq_id)
1495 uint32_t enables = 0;
1496 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1497 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1498 struct rte_mempool *mb_pool;
1499 uint16_t rx_buf_size;
1501 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1503 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1504 req.fbo = rte_cpu_to_le_32(0);
1505 /* Association of ring index with doorbell index */
1506 req.logical_id = rte_cpu_to_le_16(map_index);
1507 req.length = rte_cpu_to_le_32(ring->ring_size);
1509 switch (ring_type) {
1510 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1511 req.ring_type = ring_type;
1512 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1513 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1514 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1515 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1517 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1519 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1520 req.ring_type = ring_type;
1521 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1522 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1523 if (BNXT_CHIP_THOR(bp)) {
1524 mb_pool = bp->rx_queues[0]->mb_pool;
1525 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1526 RTE_PKTMBUF_HEADROOM;
1527 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1528 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1530 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1532 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1534 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1536 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1537 req.ring_type = ring_type;
1538 if (BNXT_HAS_NQ(bp)) {
1539 /* Association of cp ring with nq */
1540 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1542 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1544 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1546 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1547 req.ring_type = ring_type;
1548 req.page_size = BNXT_PAGE_SHFT;
1549 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1551 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1552 req.ring_type = ring_type;
1553 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1555 mb_pool = bp->rx_queues[0]->mb_pool;
1556 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1557 RTE_PKTMBUF_HEADROOM;
1558 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1559 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1561 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1562 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1563 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1564 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1567 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1572 req.enables = rte_cpu_to_le_32(enables);
1574 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1576 if (rc || resp->error_code) {
1577 if (rc == 0 && resp->error_code)
1578 rc = rte_le_to_cpu_16(resp->error_code);
1579 switch (ring_type) {
1580 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1582 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1585 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1587 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1590 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1592 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1596 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1598 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1601 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1603 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1607 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1613 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1618 int bnxt_hwrm_ring_free(struct bnxt *bp,
1619 struct bnxt_ring *ring, uint32_t ring_type)
1622 struct hwrm_ring_free_input req = {.req_type = 0 };
1623 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1625 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1627 req.ring_type = ring_type;
1628 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1630 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1632 if (rc || resp->error_code) {
1633 if (rc == 0 && resp->error_code)
1634 rc = rte_le_to_cpu_16(resp->error_code);
1637 switch (ring_type) {
1638 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1639 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1642 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1643 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1646 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1647 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1650 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1652 "hwrm_ring_free nq failed. rc:%d\n", rc);
1654 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1656 "hwrm_ring_free agg failed. rc:%d\n", rc);
1659 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1667 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1670 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1671 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1673 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1675 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1676 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1677 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1678 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1680 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1682 HWRM_CHECK_RESULT();
1684 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1691 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1694 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1695 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1697 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1699 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1701 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1703 HWRM_CHECK_RESULT();
1706 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1710 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1713 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1714 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1716 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1719 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1721 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1723 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1725 HWRM_CHECK_RESULT();
1731 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1732 unsigned int idx __rte_unused)
1735 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1736 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1738 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1740 req.update_period_ms = rte_cpu_to_le_32(0);
1742 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1744 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1746 HWRM_CHECK_RESULT();
1748 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1755 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1756 unsigned int idx __rte_unused)
1759 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1760 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1762 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1764 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1766 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1768 HWRM_CHECK_RESULT();
1774 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1777 struct hwrm_vnic_alloc_input req = { 0 };
1778 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1780 if (!BNXT_HAS_RING_GRPS(bp))
1781 goto skip_ring_grps;
1783 /* map ring groups to this vnic */
1784 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1785 vnic->start_grp_id, vnic->end_grp_id);
1786 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1787 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1789 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1790 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1791 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1792 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1795 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1796 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1798 if (vnic->func_default)
1800 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1801 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1803 HWRM_CHECK_RESULT();
1805 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1807 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1811 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1812 struct bnxt_vnic_info *vnic,
1813 struct bnxt_plcmodes_cfg *pmode)
1816 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1817 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1819 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1821 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1823 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1825 HWRM_CHECK_RESULT();
1827 pmode->flags = rte_le_to_cpu_32(resp->flags);
1828 /* dflt_vnic bit doesn't exist in the _cfg command */
1829 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1830 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1831 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1832 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1839 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1840 struct bnxt_vnic_info *vnic,
1841 struct bnxt_plcmodes_cfg *pmode)
1844 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1845 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1847 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1848 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1852 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1854 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1855 req.flags = rte_cpu_to_le_32(pmode->flags);
1856 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1857 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1858 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1859 req.enables = rte_cpu_to_le_32(
1860 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1861 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1862 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1865 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1867 HWRM_CHECK_RESULT();
1873 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1876 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1877 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1878 struct bnxt_plcmodes_cfg pmodes = { 0 };
1879 uint32_t ctx_enable_flag = 0;
1880 uint32_t enables = 0;
1882 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1883 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1887 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1891 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1893 if (BNXT_CHIP_THOR(bp)) {
1894 int dflt_rxq = vnic->start_grp_id;
1895 struct bnxt_rx_ring_info *rxr;
1896 struct bnxt_cp_ring_info *cpr;
1897 struct bnxt_rx_queue *rxq;
1901 * The first active receive ring is used as the VNIC
1902 * default receive ring. If there are no active receive
1903 * rings (all corresponding receive queues are stopped),
1904 * the first receive ring is used.
1906 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1907 rxq = bp->eth_dev->data->rx_queues[i];
1908 if (rxq->rx_started) {
1914 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1918 req.default_rx_ring_id =
1919 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1920 req.default_cmpl_ring_id =
1921 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1922 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1923 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1927 /* Only RSS support for now TBD: COS & LB */
1928 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1929 if (vnic->lb_rule != 0xffff)
1930 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1931 if (vnic->cos_rule != 0xffff)
1932 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1933 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1934 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1935 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1937 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1938 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1939 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1942 enables |= ctx_enable_flag;
1943 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1944 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1945 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1946 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1949 req.enables = rte_cpu_to_le_32(enables);
1950 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1951 req.mru = rte_cpu_to_le_16(vnic->mru);
1952 /* Configure default VNIC only once. */
1953 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1955 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1956 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1958 if (vnic->vlan_strip)
1960 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1963 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1964 if (vnic->roce_dual)
1965 req.flags |= rte_cpu_to_le_32(
1966 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1967 if (vnic->roce_only)
1968 req.flags |= rte_cpu_to_le_32(
1969 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1970 if (vnic->rss_dflt_cr)
1971 req.flags |= rte_cpu_to_le_32(
1972 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1974 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1976 HWRM_CHECK_RESULT();
1979 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1984 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1988 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1989 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1991 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1992 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1995 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1998 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1999 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2000 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2002 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2004 HWRM_CHECK_RESULT();
2006 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2007 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2008 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2009 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2010 vnic->mru = rte_le_to_cpu_16(resp->mru);
2011 vnic->func_default = rte_le_to_cpu_32(
2012 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2013 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2014 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2015 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2016 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2017 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
2018 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
2019 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
2020 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
2021 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2022 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2029 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2030 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2034 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2035 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2036 bp->hwrm_cmd_resp_addr;
2038 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2040 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2041 HWRM_CHECK_RESULT();
2043 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2044 if (!BNXT_HAS_RING_GRPS(bp))
2045 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2046 else if (ctx_idx == 0)
2047 vnic->rss_rule = ctx_id;
2055 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2056 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2059 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2060 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2061 bp->hwrm_cmd_resp_addr;
2063 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2064 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2067 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2069 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2071 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2073 HWRM_CHECK_RESULT();
2079 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2083 if (BNXT_CHIP_THOR(bp)) {
2086 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2087 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2089 vnic->fw_grp_ids[j]);
2090 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2092 vnic->num_lb_ctxts = 0;
2094 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2095 vnic->rss_rule = INVALID_HW_RING_ID;
2101 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2104 struct hwrm_vnic_free_input req = {.req_type = 0 };
2105 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2107 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2108 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2112 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2114 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2116 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2118 HWRM_CHECK_RESULT();
2121 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2122 /* Configure default VNIC again if necessary. */
2123 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2124 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2130 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2134 int nr_ctxs = vnic->num_lb_ctxts;
2135 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2136 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2138 for (i = 0; i < nr_ctxs; i++) {
2139 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2141 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2142 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2143 req.hash_mode_flags = vnic->hash_mode;
2145 req.hash_key_tbl_addr =
2146 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2148 req.ring_grp_tbl_addr =
2149 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2150 i * HW_HASH_INDEX_SIZE);
2151 req.ring_table_pair_index = i;
2152 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2154 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2157 HWRM_CHECK_RESULT();
2164 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2165 struct bnxt_vnic_info *vnic)
2168 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2169 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2171 if (!vnic->rss_table)
2174 if (BNXT_CHIP_THOR(bp))
2175 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2177 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2179 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2180 req.hash_mode_flags = vnic->hash_mode;
2182 req.ring_grp_tbl_addr =
2183 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2184 req.hash_key_tbl_addr =
2185 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2186 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2187 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2189 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2191 HWRM_CHECK_RESULT();
2197 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2198 struct bnxt_vnic_info *vnic)
2201 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2202 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2205 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2206 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2210 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2212 req.flags = rte_cpu_to_le_32(
2213 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2215 req.enables = rte_cpu_to_le_32(
2216 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2218 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2219 size -= RTE_PKTMBUF_HEADROOM;
2220 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2222 req.jumbo_thresh = rte_cpu_to_le_16(size);
2223 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2225 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2227 HWRM_CHECK_RESULT();
2233 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2234 struct bnxt_vnic_info *vnic, bool enable)
2237 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2238 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2240 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2242 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2246 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2247 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2251 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2254 req.enables = rte_cpu_to_le_32(
2255 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2256 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2257 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2258 req.flags = rte_cpu_to_le_32(
2259 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2260 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2261 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2262 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2263 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2264 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2265 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2266 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2267 req.min_agg_len = rte_cpu_to_le_32(512);
2269 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2271 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2273 HWRM_CHECK_RESULT();
2279 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2281 struct hwrm_func_cfg_input req = {0};
2282 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2285 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2286 req.enables = rte_cpu_to_le_32(
2287 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2288 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2289 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2291 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2293 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2294 HWRM_CHECK_RESULT();
2297 bp->pf->vf_info[vf].random_mac = false;
2302 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2306 struct hwrm_func_qstats_input req = {.req_type = 0};
2307 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2309 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2311 req.fid = rte_cpu_to_le_16(fid);
2313 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2315 HWRM_CHECK_RESULT();
2318 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2325 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2326 struct rte_eth_stats *stats,
2327 struct hwrm_func_qstats_output *func_qstats)
2330 struct hwrm_func_qstats_input req = {.req_type = 0};
2331 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2333 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2335 req.fid = rte_cpu_to_le_16(fid);
2337 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2339 HWRM_CHECK_RESULT();
2341 memcpy(func_qstats, resp,
2342 sizeof(struct hwrm_func_qstats_output));
2347 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2348 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2349 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2350 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2351 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2352 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2354 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2355 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2356 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2357 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2358 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2359 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2361 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2362 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2363 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2371 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2374 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2375 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2377 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2379 req.fid = rte_cpu_to_le_16(fid);
2381 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2383 HWRM_CHECK_RESULT();
2389 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2394 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2395 struct bnxt_tx_queue *txq;
2396 struct bnxt_rx_queue *rxq;
2397 struct bnxt_cp_ring_info *cpr;
2399 if (i >= bp->rx_cp_nr_rings) {
2400 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2403 rxq = bp->rx_queues[i];
2407 rc = bnxt_hwrm_stat_clear(bp, cpr);
2415 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2419 struct bnxt_cp_ring_info *cpr;
2421 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2423 if (i >= bp->rx_cp_nr_rings) {
2424 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2426 cpr = bp->rx_queues[i]->cp_ring;
2427 if (BNXT_HAS_RING_GRPS(bp))
2428 bp->grp_info[i].fw_stats_ctx = -1;
2430 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2431 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2432 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2440 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2445 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2446 struct bnxt_tx_queue *txq;
2447 struct bnxt_rx_queue *rxq;
2448 struct bnxt_cp_ring_info *cpr;
2450 if (i >= bp->rx_cp_nr_rings) {
2451 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2454 rxq = bp->rx_queues[i];
2458 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2467 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2472 if (!BNXT_HAS_RING_GRPS(bp))
2475 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2477 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2480 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2488 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2490 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2492 bnxt_hwrm_ring_free(bp, cp_ring,
2493 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2494 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2495 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2496 sizeof(*cpr->cp_desc_ring));
2497 cpr->cp_raw_cons = 0;
2501 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2503 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2505 bnxt_hwrm_ring_free(bp, cp_ring,
2506 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2507 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2508 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2509 sizeof(*cpr->cp_desc_ring));
2510 cpr->cp_raw_cons = 0;
2514 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2516 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2517 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2518 struct bnxt_ring *ring = rxr->rx_ring_struct;
2519 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2521 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2522 bnxt_hwrm_ring_free(bp, ring,
2523 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2524 ring->fw_ring_id = INVALID_HW_RING_ID;
2525 if (BNXT_HAS_RING_GRPS(bp))
2526 bp->grp_info[queue_index].rx_fw_ring_id =
2529 ring = rxr->ag_ring_struct;
2530 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2531 bnxt_hwrm_ring_free(bp, ring,
2532 BNXT_CHIP_THOR(bp) ?
2533 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2534 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2535 if (BNXT_HAS_RING_GRPS(bp))
2536 bp->grp_info[queue_index].ag_fw_ring_id =
2539 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2540 bnxt_free_cp_ring(bp, cpr);
2542 if (BNXT_HAS_RING_GRPS(bp))
2543 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2547 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2551 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2552 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2553 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2554 struct bnxt_ring *ring = txr->tx_ring_struct;
2555 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2557 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2558 bnxt_hwrm_ring_free(bp, ring,
2559 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2560 ring->fw_ring_id = INVALID_HW_RING_ID;
2561 memset(txr->tx_desc_ring, 0,
2562 txr->tx_ring_struct->ring_size *
2563 sizeof(*txr->tx_desc_ring));
2564 memset(txr->tx_buf_ring, 0,
2565 txr->tx_ring_struct->ring_size *
2566 sizeof(*txr->tx_buf_ring));
2570 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2571 bnxt_free_cp_ring(bp, cpr);
2572 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2576 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2577 bnxt_free_hwrm_rx_ring(bp, i);
2582 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2587 if (!BNXT_HAS_RING_GRPS(bp))
2590 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2591 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2599 * HWRM utility functions
2602 void bnxt_free_hwrm_resources(struct bnxt *bp)
2604 /* Release memzone */
2605 rte_free(bp->hwrm_cmd_resp_addr);
2606 rte_free(bp->hwrm_short_cmd_req_addr);
2607 bp->hwrm_cmd_resp_addr = NULL;
2608 bp->hwrm_short_cmd_req_addr = NULL;
2609 bp->hwrm_cmd_resp_dma_addr = 0;
2610 bp->hwrm_short_cmd_req_dma_addr = 0;
2613 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2615 struct rte_pci_device *pdev = bp->pdev;
2616 char type[RTE_MEMZONE_NAMESIZE];
2618 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2619 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2620 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2621 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2622 if (bp->hwrm_cmd_resp_addr == NULL)
2624 bp->hwrm_cmd_resp_dma_addr =
2625 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2626 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2628 "unable to map response address to physical memory\n");
2631 rte_spinlock_init(&bp->hwrm_lock);
2637 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2641 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2642 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2645 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2646 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2651 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2656 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2658 struct bnxt_filter_info *filter;
2661 STAILQ_FOREACH(filter, &vnic->filter, next) {
2662 rc = bnxt_clear_one_vnic_filter(bp, filter);
2663 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2664 bnxt_free_filter(bp, filter);
2670 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2672 struct bnxt_filter_info *filter;
2673 struct rte_flow *flow;
2676 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2677 flow = STAILQ_FIRST(&vnic->flow_list);
2678 filter = flow->filter;
2679 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2680 rc = bnxt_clear_one_vnic_filter(bp, filter);
2682 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2688 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2690 struct bnxt_filter_info *filter;
2693 STAILQ_FOREACH(filter, &vnic->filter, next) {
2694 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2695 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2697 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2698 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2701 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2710 bnxt_free_tunnel_ports(struct bnxt *bp)
2712 if (bp->vxlan_port_cnt)
2713 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2714 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2716 if (bp->geneve_port_cnt)
2717 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2718 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2719 bp->geneve_port = 0;
2722 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2726 if (bp->vnic_info == NULL)
2730 * Cleanup VNICs in reverse order, to make sure the L2 filter
2731 * from vnic0 is last to be cleaned up.
2733 for (i = bp->max_vnics - 1; i >= 0; i--) {
2734 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2736 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2739 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2741 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2743 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2745 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2747 bnxt_hwrm_vnic_free(bp, vnic);
2749 rte_free(vnic->fw_grp_ids);
2751 /* Ring resources */
2752 bnxt_free_all_hwrm_rings(bp);
2753 bnxt_free_all_hwrm_ring_grps(bp);
2754 bnxt_free_all_hwrm_stat_ctxs(bp);
2755 bnxt_free_tunnel_ports(bp);
2758 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2760 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2762 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2763 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2765 switch (conf_link_speed) {
2766 case ETH_LINK_SPEED_10M_HD:
2767 case ETH_LINK_SPEED_100M_HD:
2769 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2771 return hw_link_duplex;
2774 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2776 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2779 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2781 uint16_t eth_link_speed = 0;
2783 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2784 return ETH_LINK_SPEED_AUTONEG;
2786 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2787 case ETH_LINK_SPEED_100M:
2788 case ETH_LINK_SPEED_100M_HD:
2791 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2793 case ETH_LINK_SPEED_1G:
2795 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2797 case ETH_LINK_SPEED_2_5G:
2799 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2801 case ETH_LINK_SPEED_10G:
2803 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2805 case ETH_LINK_SPEED_20G:
2807 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2809 case ETH_LINK_SPEED_25G:
2811 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2813 case ETH_LINK_SPEED_40G:
2815 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2817 case ETH_LINK_SPEED_50G:
2819 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2821 case ETH_LINK_SPEED_100G:
2823 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2825 case ETH_LINK_SPEED_200G:
2827 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2831 "Unsupported link speed %d; default to AUTO\n",
2835 return eth_link_speed;
2838 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2839 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2840 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2841 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2842 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2844 static int bnxt_validate_link_speed(struct bnxt *bp)
2846 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2847 uint16_t port_id = bp->eth_dev->data->port_id;
2848 uint32_t link_speed_capa;
2851 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2854 link_speed_capa = bnxt_get_speed_capabilities(bp);
2856 if (link_speed & ETH_LINK_SPEED_FIXED) {
2857 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2859 if (one_speed & (one_speed - 1)) {
2861 "Invalid advertised speeds (%u) for port %u\n",
2862 link_speed, port_id);
2865 if ((one_speed & link_speed_capa) != one_speed) {
2867 "Unsupported advertised speed (%u) for port %u\n",
2868 link_speed, port_id);
2872 if (!(link_speed & link_speed_capa)) {
2874 "Unsupported advertised speeds (%u) for port %u\n",
2875 link_speed, port_id);
2883 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2887 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2888 if (bp->link_info->support_speeds)
2889 return bp->link_info->support_speeds;
2890 link_speed = BNXT_SUPPORTED_SPEEDS;
2893 if (link_speed & ETH_LINK_SPEED_100M)
2894 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2895 if (link_speed & ETH_LINK_SPEED_100M_HD)
2896 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2897 if (link_speed & ETH_LINK_SPEED_1G)
2898 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2899 if (link_speed & ETH_LINK_SPEED_2_5G)
2900 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2901 if (link_speed & ETH_LINK_SPEED_10G)
2902 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2903 if (link_speed & ETH_LINK_SPEED_20G)
2904 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2905 if (link_speed & ETH_LINK_SPEED_25G)
2906 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2907 if (link_speed & ETH_LINK_SPEED_40G)
2908 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2909 if (link_speed & ETH_LINK_SPEED_50G)
2910 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2911 if (link_speed & ETH_LINK_SPEED_100G)
2912 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2913 if (link_speed & ETH_LINK_SPEED_200G)
2914 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2918 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2920 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2922 switch (hw_link_speed) {
2923 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2924 eth_link_speed = ETH_SPEED_NUM_100M;
2926 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2927 eth_link_speed = ETH_SPEED_NUM_1G;
2929 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2930 eth_link_speed = ETH_SPEED_NUM_2_5G;
2932 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2933 eth_link_speed = ETH_SPEED_NUM_10G;
2935 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2936 eth_link_speed = ETH_SPEED_NUM_20G;
2938 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2939 eth_link_speed = ETH_SPEED_NUM_25G;
2941 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2942 eth_link_speed = ETH_SPEED_NUM_40G;
2944 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2945 eth_link_speed = ETH_SPEED_NUM_50G;
2947 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2948 eth_link_speed = ETH_SPEED_NUM_100G;
2950 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2951 eth_link_speed = ETH_SPEED_NUM_200G;
2953 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2955 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2959 return eth_link_speed;
2962 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2964 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2966 switch (hw_link_duplex) {
2967 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2968 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2970 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2972 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2973 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2976 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2980 return eth_link_duplex;
2983 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2986 struct bnxt_link_info *link_info = bp->link_info;
2988 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2991 "Get link config failed with rc %d\n", rc);
2994 if (link_info->link_speed)
2996 bnxt_parse_hw_link_speed(link_info->link_speed);
2998 link->link_speed = ETH_SPEED_NUM_NONE;
2999 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3000 link->link_status = link_info->link_up;
3001 link->link_autoneg = link_info->auto_mode ==
3002 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3003 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3008 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3011 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3012 struct bnxt_link_info link_req;
3013 uint16_t speed, autoneg;
3015 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3018 rc = bnxt_validate_link_speed(bp);
3022 memset(&link_req, 0, sizeof(link_req));
3023 link_req.link_up = link_up;
3027 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3028 if (BNXT_CHIP_THOR(bp) &&
3029 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3030 /* 40G is not supported as part of media auto detect.
3031 * The speed should be forced and autoneg disabled
3032 * to configure 40G speed.
3034 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3038 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
3039 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3040 /* Autoneg can be done only when the FW allows.
3041 * When user configures fixed speed of 40G and later changes to
3042 * any other speed, auto_link_speed/force_link_speed is still set
3043 * to 40G until link comes up at new speed.
3046 !(!BNXT_CHIP_THOR(bp) &&
3047 (bp->link_info->auto_link_speed ||
3048 bp->link_info->force_link_speed))) {
3049 link_req.phy_flags |=
3050 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3051 link_req.auto_link_speed_mask =
3052 bnxt_parse_eth_link_speed_mask(bp,
3053 dev_conf->link_speeds);
3055 if (bp->link_info->phy_type ==
3056 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3057 bp->link_info->phy_type ==
3058 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3059 bp->link_info->media_type ==
3060 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3061 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3065 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3066 /* If user wants a particular speed try that first. */
3068 link_req.link_speed = speed;
3069 else if (bp->link_info->force_link_speed)
3070 link_req.link_speed = bp->link_info->force_link_speed;
3072 link_req.link_speed = bp->link_info->auto_link_speed;
3074 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3075 link_req.auto_pause = bp->link_info->auto_pause;
3076 link_req.force_pause = bp->link_info->force_pause;
3079 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3082 "Set link config failed with rc %d\n", rc);
3090 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3092 struct hwrm_func_qcfg_input req = {0};
3093 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3096 bp->func_svif = BNXT_SVIF_INVALID;
3099 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3100 req.fid = rte_cpu_to_le_16(0xffff);
3102 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3104 HWRM_CHECK_RESULT();
3106 /* Hard Coded.. 0xfff VLAN ID mask */
3107 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3109 svif_info = rte_le_to_cpu_16(resp->svif_info);
3110 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3111 bp->func_svif = svif_info &
3112 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3114 flags = rte_le_to_cpu_16(resp->flags);
3115 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3116 bp->flags |= BNXT_FLAG_MULTI_HOST;
3119 !BNXT_VF_IS_TRUSTED(bp) &&
3120 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3121 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3122 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3123 } else if (BNXT_VF(bp) &&
3124 BNXT_VF_IS_TRUSTED(bp) &&
3125 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3126 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3127 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3131 *mtu = rte_le_to_cpu_16(resp->mtu);
3133 switch (resp->port_partition_type) {
3134 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3135 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3136 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3138 bp->flags |= BNXT_FLAG_NPAR_PF;
3141 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3150 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3152 struct hwrm_func_qcfg_input req = {0};
3153 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3156 if (!BNXT_VF_IS_TRUSTED(bp))
3162 bp->parent->fid = BNXT_PF_FID_INVALID;
3164 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3166 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3168 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3170 HWRM_CHECK_RESULT();
3172 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3173 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3174 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3175 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3177 /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3178 if (bp->parent->vnic == 0) {
3179 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3180 /* Use hard-coded values appropriate for current Wh+ fw. */
3181 if (bp->parent->fid == 2)
3182 bp->parent->vnic = 0x100;
3184 bp->parent->vnic = 1;
3192 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3193 uint16_t *vnic_id, uint16_t *svif)
3195 struct hwrm_func_qcfg_input req = {0};
3196 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3200 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3201 req.fid = rte_cpu_to_le_16(fid);
3203 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3205 HWRM_CHECK_RESULT();
3208 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3210 svif_info = rte_le_to_cpu_16(resp->svif_info);
3211 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3212 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3219 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3221 struct hwrm_port_mac_qcfg_input req = {0};
3222 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3223 uint16_t port_svif_info;
3226 bp->port_svif = BNXT_SVIF_INVALID;
3228 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3231 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3233 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3235 HWRM_CHECK_RESULT_SILENT();
3237 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3238 if (port_svif_info &
3239 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3240 bp->port_svif = port_svif_info &
3241 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3248 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3249 struct hwrm_func_qcaps_output *qcaps)
3251 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3252 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3253 sizeof(qcaps->mac_address));
3254 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3255 qcaps->max_rx_rings = fcfg->num_rx_rings;
3256 qcaps->max_tx_rings = fcfg->num_tx_rings;
3257 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3258 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3260 qcaps->first_vf_id = 0;
3261 qcaps->max_vnics = fcfg->num_vnics;
3262 qcaps->max_decap_records = 0;
3263 qcaps->max_encap_records = 0;
3264 qcaps->max_tx_wm_flows = 0;
3265 qcaps->max_tx_em_flows = 0;
3266 qcaps->max_rx_wm_flows = 0;
3267 qcaps->max_rx_em_flows = 0;
3268 qcaps->max_flow_id = 0;
3269 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3270 qcaps->max_sp_tx_rings = 0;
3271 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3274 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3276 struct hwrm_func_cfg_input req = {0};
3277 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3281 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3282 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3283 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3284 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3285 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3286 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3287 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3288 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3289 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3291 if (BNXT_HAS_RING_GRPS(bp)) {
3292 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3293 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3294 } else if (BNXT_HAS_NQ(bp)) {
3295 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3296 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3299 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3300 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3301 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3302 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3303 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3304 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3305 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3306 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3307 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3308 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3309 req.fid = rte_cpu_to_le_16(0xffff);
3310 req.enables = rte_cpu_to_le_32(enables);
3312 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3314 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3316 HWRM_CHECK_RESULT();
3322 static void populate_vf_func_cfg_req(struct bnxt *bp,
3323 struct hwrm_func_cfg_input *req,
3326 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3327 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3328 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3329 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3330 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3331 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3332 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3333 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3334 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3335 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3337 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3338 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3340 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3341 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3343 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3344 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3346 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3347 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3348 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3349 /* TODO: For now, do not support VMDq/RFS on VFs. */
3350 req->num_vnics = rte_cpu_to_le_16(1);
3351 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3355 static void add_random_mac_if_needed(struct bnxt *bp,
3356 struct hwrm_func_cfg_input *cfg_req,
3359 struct rte_ether_addr mac;
3361 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3364 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3366 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3367 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3368 bp->pf->vf_info[vf].random_mac = true;
3370 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3371 RTE_ETHER_ADDR_LEN);
3375 static int reserve_resources_from_vf(struct bnxt *bp,
3376 struct hwrm_func_cfg_input *cfg_req,
3379 struct hwrm_func_qcaps_input req = {0};
3380 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3383 /* Get the actual allocated values now */
3384 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3385 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3386 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3389 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3390 copy_func_cfg_to_qcaps(cfg_req, resp);
3391 } else if (resp->error_code) {
3392 rc = rte_le_to_cpu_16(resp->error_code);
3393 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3394 copy_func_cfg_to_qcaps(cfg_req, resp);
3397 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3398 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3399 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3400 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3401 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3402 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3404 * TODO: While not supporting VMDq with VFs, max_vnics is always
3405 * forced to 1 in this case
3407 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3408 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3415 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3417 struct hwrm_func_qcfg_input req = {0};
3418 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3421 /* Check for zero MAC address */
3422 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3423 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3424 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3425 HWRM_CHECK_RESULT();
3426 rc = rte_le_to_cpu_16(resp->vlan);
3433 static int update_pf_resource_max(struct bnxt *bp)
3435 struct hwrm_func_qcfg_input req = {0};
3436 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3439 /* And copy the allocated numbers into the pf struct */
3440 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3441 req.fid = rte_cpu_to_le_16(0xffff);
3442 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3443 HWRM_CHECK_RESULT();
3445 /* Only TX ring value reflects actual allocation? TODO */
3446 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3447 bp->pf->evb_mode = resp->evb_mode;
3454 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3459 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3463 rc = bnxt_hwrm_func_qcaps(bp);
3467 bp->pf->func_cfg_flags &=
3468 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3469 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3470 bp->pf->func_cfg_flags |=
3471 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3472 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3473 rc = __bnxt_hwrm_func_qcaps(bp);
3477 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3479 struct hwrm_func_cfg_input req = {0};
3480 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3487 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3491 rc = bnxt_hwrm_func_qcaps(bp);
3496 bp->pf->active_vfs = num_vfs;
3499 * First, configure the PF to only use one TX ring. This ensures that
3500 * there are enough rings for all VFs.
3502 * If we don't do this, when we call func_alloc() later, we will lock
3503 * extra rings to the PF that won't be available during func_cfg() of
3506 * This has been fixed with firmware versions above 20.6.54
3508 bp->pf->func_cfg_flags &=
3509 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3510 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3511 bp->pf->func_cfg_flags |=
3512 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3513 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3518 * Now, create and register a buffer to hold forwarded VF requests
3520 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3521 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3522 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3523 if (bp->pf->vf_req_buf == NULL) {
3527 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3528 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3529 for (i = 0; i < num_vfs; i++)
3530 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3531 (i * HWRM_MAX_REQ_LEN);
3533 rc = bnxt_hwrm_func_buf_rgtr(bp);
3537 populate_vf_func_cfg_req(bp, &req, num_vfs);
3539 bp->pf->active_vfs = 0;
3540 for (i = 0; i < num_vfs; i++) {
3541 add_random_mac_if_needed(bp, &req, i);
3543 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3544 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3545 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3546 rc = bnxt_hwrm_send_message(bp,
3551 /* Clear enable flag for next pass */
3552 req.enables &= ~rte_cpu_to_le_32(
3553 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3555 if (rc || resp->error_code) {
3557 "Failed to initizlie VF %d\n", i);
3559 "Not all VFs available. (%d, %d)\n",
3560 rc, resp->error_code);
3567 reserve_resources_from_vf(bp, &req, i);
3568 bp->pf->active_vfs++;
3569 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3573 * Now configure the PF to use "the rest" of the resources
3574 * We're using STD_TX_RING_MODE here though which will limit the TX
3575 * rings. This will allow QoS to function properly. Not setting this
3576 * will cause PF rings to break bandwidth settings.
3578 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3582 rc = update_pf_resource_max(bp);
3589 bnxt_hwrm_func_buf_unrgtr(bp);
3593 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3595 struct hwrm_func_cfg_input req = {0};
3596 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3599 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3601 req.fid = rte_cpu_to_le_16(0xffff);
3602 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3603 req.evb_mode = bp->pf->evb_mode;
3605 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3606 HWRM_CHECK_RESULT();
3612 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3613 uint8_t tunnel_type)
3615 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3616 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3619 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3620 req.tunnel_type = tunnel_type;
3621 req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3622 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3623 HWRM_CHECK_RESULT();
3625 switch (tunnel_type) {
3626 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3627 bp->vxlan_fw_dst_port_id =
3628 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3629 bp->vxlan_port = port;
3631 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3632 bp->geneve_fw_dst_port_id =
3633 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3634 bp->geneve_port = port;
3645 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3646 uint8_t tunnel_type)
3648 struct hwrm_tunnel_dst_port_free_input req = {0};
3649 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3652 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3654 req.tunnel_type = tunnel_type;
3655 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3656 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3658 HWRM_CHECK_RESULT();
3664 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3667 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3668 struct hwrm_func_cfg_input req = {0};
3671 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3673 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3674 req.flags = rte_cpu_to_le_32(flags);
3675 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3677 HWRM_CHECK_RESULT();
3683 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3685 uint32_t *flag = flagp;
3687 vnic->flags = *flag;
3690 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3692 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3695 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3698 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3699 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3701 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3703 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3704 req.req_buf_page_size = rte_cpu_to_le_16(
3705 page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3706 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3707 req.req_buf_page_addr0 =
3708 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3709 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3711 "unable to map buffer address to physical memory\n");
3715 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3717 HWRM_CHECK_RESULT();
3723 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3726 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3727 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3729 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3732 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3734 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3736 HWRM_CHECK_RESULT();
3742 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3744 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3745 struct hwrm_func_cfg_input req = {0};
3748 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3750 req.fid = rte_cpu_to_le_16(0xffff);
3751 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3752 req.enables = rte_cpu_to_le_32(
3753 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3754 req.async_event_cr = rte_cpu_to_le_16(
3755 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3756 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3758 HWRM_CHECK_RESULT();
3764 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3766 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3767 struct hwrm_func_vf_cfg_input req = {0};
3770 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3772 req.enables = rte_cpu_to_le_32(
3773 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3774 req.async_event_cr = rte_cpu_to_le_16(
3775 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3776 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3778 HWRM_CHECK_RESULT();
3784 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3786 struct hwrm_func_cfg_input req = {0};
3787 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3788 uint16_t dflt_vlan, fid;
3789 uint32_t func_cfg_flags;
3792 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3795 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3796 fid = bp->pf->vf_info[vf].fid;
3797 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3799 fid = rte_cpu_to_le_16(0xffff);
3800 func_cfg_flags = bp->pf->func_cfg_flags;
3801 dflt_vlan = bp->vlan;
3804 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3805 req.fid = rte_cpu_to_le_16(fid);
3806 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3807 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3809 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3811 HWRM_CHECK_RESULT();
3817 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3818 uint16_t max_bw, uint16_t enables)
3820 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3821 struct hwrm_func_cfg_input req = {0};
3824 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3826 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3827 req.enables |= rte_cpu_to_le_32(enables);
3828 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3829 req.max_bw = rte_cpu_to_le_32(max_bw);
3830 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3832 HWRM_CHECK_RESULT();
3838 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3840 struct hwrm_func_cfg_input req = {0};
3841 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3844 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3846 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3847 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3848 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3849 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3853 HWRM_CHECK_RESULT();
3859 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3864 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3866 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3871 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3872 void *encaped, size_t ec_size)
3875 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3876 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3878 if (ec_size > sizeof(req.encap_request))
3881 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3883 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3884 memcpy(req.encap_request, encaped, ec_size);
3886 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3888 HWRM_CHECK_RESULT();
3894 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3895 struct rte_ether_addr *mac)
3897 struct hwrm_func_qcfg_input req = {0};
3898 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3901 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3903 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3904 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3906 HWRM_CHECK_RESULT();
3908 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3915 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3916 void *encaped, size_t ec_size)
3919 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3920 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3922 if (ec_size > sizeof(req.encap_request))
3925 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3927 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3928 memcpy(req.encap_request, encaped, ec_size);
3930 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3932 HWRM_CHECK_RESULT();
3938 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3939 struct rte_eth_stats *stats, uint8_t rx)
3942 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3943 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3945 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3947 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3949 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3951 HWRM_CHECK_RESULT();
3954 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3955 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3956 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3957 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3958 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3959 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3960 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3961 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3963 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3964 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3965 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3966 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3967 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3968 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3976 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3978 struct hwrm_port_qstats_input req = {0};
3979 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3980 struct bnxt_pf_info *pf = bp->pf;
3983 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3985 req.port_id = rte_cpu_to_le_16(pf->port_id);
3986 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3987 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3988 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3990 HWRM_CHECK_RESULT();
3996 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3998 struct hwrm_port_clr_stats_input req = {0};
3999 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4000 struct bnxt_pf_info *pf = bp->pf;
4003 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4004 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4005 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4008 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4010 req.port_id = rte_cpu_to_le_16(pf->port_id);
4011 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4013 HWRM_CHECK_RESULT();
4019 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4021 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4022 struct hwrm_port_led_qcaps_input req = {0};
4028 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4029 req.port_id = bp->pf->port_id;
4030 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4032 HWRM_CHECK_RESULT();
4034 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4037 bp->leds->num_leds = resp->num_leds;
4038 memcpy(bp->leds, &resp->led0_id,
4039 sizeof(bp->leds[0]) * bp->leds->num_leds);
4040 for (i = 0; i < bp->leds->num_leds; i++) {
4041 struct bnxt_led_info *led = &bp->leds[i];
4043 uint16_t caps = led->led_state_caps;
4045 if (!led->led_group_id ||
4046 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4047 bp->leds->num_leds = 0;
4058 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4060 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4061 struct hwrm_port_led_cfg_input req = {0};
4062 struct bnxt_led_cfg *led_cfg;
4063 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4064 uint16_t duration = 0;
4067 if (!bp->leds->num_leds || BNXT_VF(bp))
4070 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4073 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4074 duration = rte_cpu_to_le_16(500);
4076 req.port_id = bp->pf->port_id;
4077 req.num_leds = bp->leds->num_leds;
4078 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4079 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4080 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4081 led_cfg->led_id = bp->leds[i].led_id;
4082 led_cfg->led_state = led_state;
4083 led_cfg->led_blink_on = duration;
4084 led_cfg->led_blink_off = duration;
4085 led_cfg->led_group_id = bp->leds[i].led_group_id;
4088 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4090 HWRM_CHECK_RESULT();
4096 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4100 struct hwrm_nvm_get_dir_info_input req = {0};
4101 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4103 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4105 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4107 HWRM_CHECK_RESULT();
4109 *entries = rte_le_to_cpu_32(resp->entries);
4110 *length = rte_le_to_cpu_32(resp->entry_length);
4116 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4119 uint32_t dir_entries;
4120 uint32_t entry_length;
4123 rte_iova_t dma_handle;
4124 struct hwrm_nvm_get_dir_entries_input req = {0};
4125 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4127 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4131 *data++ = dir_entries;
4132 *data++ = entry_length;
4134 memset(data, 0xff, len);
4136 buflen = dir_entries * entry_length;
4137 buf = rte_malloc("nvm_dir", buflen, 0);
4140 dma_handle = rte_malloc_virt2iova(buf);
4141 if (dma_handle == RTE_BAD_IOVA) {
4143 "unable to map response address to physical memory\n");
4146 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4147 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4148 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4151 memcpy(data, buf, len > buflen ? buflen : len);
4154 HWRM_CHECK_RESULT();
4160 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4161 uint32_t offset, uint32_t length,
4166 rte_iova_t dma_handle;
4167 struct hwrm_nvm_read_input req = {0};
4168 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4170 buf = rte_malloc("nvm_item", length, 0);
4174 dma_handle = rte_malloc_virt2iova(buf);
4175 if (dma_handle == RTE_BAD_IOVA) {
4177 "unable to map response address to physical memory\n");
4180 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4181 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4182 req.dir_idx = rte_cpu_to_le_16(index);
4183 req.offset = rte_cpu_to_le_32(offset);
4184 req.len = rte_cpu_to_le_32(length);
4185 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4187 memcpy(data, buf, length);
4190 HWRM_CHECK_RESULT();
4196 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4199 struct hwrm_nvm_erase_dir_entry_input req = {0};
4200 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4202 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4203 req.dir_idx = rte_cpu_to_le_16(index);
4204 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4205 HWRM_CHECK_RESULT();
4212 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4213 uint16_t dir_ordinal, uint16_t dir_ext,
4214 uint16_t dir_attr, const uint8_t *data,
4218 struct hwrm_nvm_write_input req = {0};
4219 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4220 rte_iova_t dma_handle;
4223 buf = rte_malloc("nvm_write", data_len, 0);
4227 dma_handle = rte_malloc_virt2iova(buf);
4228 if (dma_handle == RTE_BAD_IOVA) {
4230 "unable to map response address to physical memory\n");
4233 memcpy(buf, data, data_len);
4235 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4237 req.dir_type = rte_cpu_to_le_16(dir_type);
4238 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4239 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4240 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4241 req.dir_data_length = rte_cpu_to_le_32(data_len);
4242 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4244 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4247 HWRM_CHECK_RESULT();
4254 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4256 uint32_t *count = cbdata;
4258 *count = *count + 1;
4261 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4262 struct bnxt_vnic_info *vnic __rte_unused)
4267 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4271 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4272 &count, bnxt_vnic_count_hwrm_stub);
4277 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4280 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4281 struct hwrm_func_vf_vnic_ids_query_output *resp =
4282 bp->hwrm_cmd_resp_addr;
4285 /* First query all VNIC ids */
4286 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4288 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4289 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4290 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4292 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4295 "unable to map VNIC ID table address to physical memory\n");
4298 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4299 HWRM_CHECK_RESULT();
4300 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4308 * This function queries the VNIC IDs for a specified VF. It then calls
4309 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4310 * Then it calls the hwrm_cb function to program this new vnic configuration.
4312 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4313 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4314 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4316 struct bnxt_vnic_info vnic;
4318 int i, num_vnic_ids;
4323 /* First query all VNIC ids */
4324 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4325 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4326 RTE_CACHE_LINE_SIZE);
4327 if (vnic_ids == NULL)
4330 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4331 rte_mem_lock_page(((char *)vnic_ids) + sz);
4333 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4335 if (num_vnic_ids < 0)
4336 return num_vnic_ids;
4338 /* Retrieve VNIC, update bd_stall then update */
4340 for (i = 0; i < num_vnic_ids; i++) {
4341 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4342 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4343 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4346 if (vnic.mru <= 4) /* Indicates unallocated */
4349 vnic_cb(&vnic, cbdata);
4351 rc = hwrm_cb(bp, &vnic);
4361 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4364 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4365 struct hwrm_func_cfg_input req = {0};
4368 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4370 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4371 req.enables |= rte_cpu_to_le_32(
4372 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4373 req.vlan_antispoof_mode = on ?
4374 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4375 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4376 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4378 HWRM_CHECK_RESULT();
4384 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4386 struct bnxt_vnic_info vnic;
4389 int num_vnic_ids, i;
4393 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4394 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4395 RTE_CACHE_LINE_SIZE);
4396 if (vnic_ids == NULL)
4399 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4400 rte_mem_lock_page(((char *)vnic_ids) + sz);
4402 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4408 * Loop through to find the default VNIC ID.
4409 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4410 * by sending the hwrm_func_qcfg command to the firmware.
4412 for (i = 0; i < num_vnic_ids; i++) {
4413 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4414 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4415 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4416 bp->pf->first_vf_id + vf);
4419 if (vnic.func_default) {
4421 return vnic.fw_vnic_id;
4424 /* Could not find a default VNIC. */
4425 PMD_DRV_LOG(ERR, "No default VNIC\n");
4431 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4433 struct bnxt_filter_info *filter)
4436 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4437 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4438 uint32_t enables = 0;
4440 if (filter->fw_em_filter_id != UINT64_MAX)
4441 bnxt_hwrm_clear_em_filter(bp, filter);
4443 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4445 req.flags = rte_cpu_to_le_32(filter->flags);
4447 enables = filter->enables |
4448 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4449 req.dst_id = rte_cpu_to_le_16(dst_id);
4451 if (filter->ip_addr_type) {
4452 req.ip_addr_type = filter->ip_addr_type;
4453 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4456 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4457 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4459 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4460 memcpy(req.src_macaddr, filter->src_macaddr,
4461 RTE_ETHER_ADDR_LEN);
4463 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4464 memcpy(req.dst_macaddr, filter->dst_macaddr,
4465 RTE_ETHER_ADDR_LEN);
4467 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4468 req.ovlan_vid = filter->l2_ovlan;
4470 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4471 req.ivlan_vid = filter->l2_ivlan;
4473 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4474 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4476 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4477 req.ip_protocol = filter->ip_protocol;
4479 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4480 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4482 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4483 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4485 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4486 req.src_port = rte_cpu_to_be_16(filter->src_port);
4488 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4489 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4491 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4492 req.mirror_vnic_id = filter->mirror_vnic_id;
4494 req.enables = rte_cpu_to_le_32(enables);
4496 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4498 HWRM_CHECK_RESULT();
4500 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4506 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4509 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4510 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4512 if (filter->fw_em_filter_id == UINT64_MAX)
4515 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4517 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4519 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4521 HWRM_CHECK_RESULT();
4524 filter->fw_em_filter_id = UINT64_MAX;
4525 filter->fw_l2_filter_id = UINT64_MAX;
4530 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4532 struct bnxt_filter_info *filter)
4535 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4536 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4537 bp->hwrm_cmd_resp_addr;
4538 uint32_t enables = 0;
4540 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4541 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4543 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4545 req.flags = rte_cpu_to_le_32(filter->flags);
4547 enables = filter->enables |
4548 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4549 req.dst_id = rte_cpu_to_le_16(dst_id);
4551 if (filter->ip_addr_type) {
4552 req.ip_addr_type = filter->ip_addr_type;
4554 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4557 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4558 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4560 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4561 memcpy(req.src_macaddr, filter->src_macaddr,
4562 RTE_ETHER_ADDR_LEN);
4564 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4565 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4567 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4568 req.ip_protocol = filter->ip_protocol;
4570 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4571 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4573 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4574 req.src_ipaddr_mask[0] =
4575 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4577 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4578 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4580 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4581 req.dst_ipaddr_mask[0] =
4582 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4584 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4585 req.src_port = rte_cpu_to_le_16(filter->src_port);
4587 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4588 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4590 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4591 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4593 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4594 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4596 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4597 req.mirror_vnic_id = filter->mirror_vnic_id;
4599 req.enables = rte_cpu_to_le_32(enables);
4601 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4603 HWRM_CHECK_RESULT();
4605 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4606 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4612 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4613 struct bnxt_filter_info *filter)
4616 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4617 struct hwrm_cfa_ntuple_filter_free_output *resp =
4618 bp->hwrm_cmd_resp_addr;
4620 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4623 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4625 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4627 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4629 HWRM_CHECK_RESULT();
4632 filter->fw_ntuple_filter_id = UINT64_MAX;
4638 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4640 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4641 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4642 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4643 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4644 uint16_t *ring_tbl = vnic->rss_table;
4645 int nr_ctxs = vnic->num_lb_ctxts;
4646 int max_rings = bp->rx_nr_rings;
4650 for (i = 0, k = 0; i < nr_ctxs; i++) {
4651 struct bnxt_rx_ring_info *rxr;
4652 struct bnxt_cp_ring_info *cpr;
4654 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4656 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4657 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4658 req.hash_mode_flags = vnic->hash_mode;
4660 req.ring_grp_tbl_addr =
4661 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4662 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4663 2 * sizeof(*ring_tbl));
4664 req.hash_key_tbl_addr =
4665 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4667 req.ring_table_pair_index = i;
4668 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4670 for (j = 0; j < 64; j++) {
4673 /* Find next active ring. */
4674 for (cnt = 0; cnt < max_rings; cnt++) {
4675 if (rx_queue_state[k] !=
4676 RTE_ETH_QUEUE_STATE_STOPPED)
4678 if (++k == max_rings)
4682 /* Return if no rings are active. */
4683 if (cnt == max_rings) {
4688 /* Add rx/cp ring pair to RSS table. */
4689 rxr = rxqs[k]->rx_ring;
4690 cpr = rxqs[k]->cp_ring;
4692 ring_id = rxr->rx_ring_struct->fw_ring_id;
4693 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4694 ring_id = cpr->cp_ring_struct->fw_ring_id;
4695 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4697 if (++k == max_rings)
4700 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4703 HWRM_CHECK_RESULT();
4710 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4712 unsigned int rss_idx, fw_idx, i;
4714 if (!(vnic->rss_table && vnic->hash_type))
4717 if (BNXT_CHIP_THOR(bp))
4718 return bnxt_vnic_rss_configure_thor(bp, vnic);
4720 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4723 if (vnic->rss_table && vnic->hash_type) {
4725 * Fill the RSS hash & redirection table with
4726 * ring group ids for all VNICs
4728 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4729 rss_idx++, fw_idx++) {
4730 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4731 fw_idx %= bp->rx_cp_nr_rings;
4732 if (vnic->fw_grp_ids[fw_idx] !=
4737 if (i == bp->rx_cp_nr_rings)
4739 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4741 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4747 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4748 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4752 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4754 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4755 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4757 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4758 req->num_cmpl_dma_aggr_during_int =
4759 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4761 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4763 /* min timer set to 1/2 of interrupt timer */
4764 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4766 /* buf timer set to 1/4 of interrupt timer */
4767 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4769 req->cmpl_aggr_dma_tmr_during_int =
4770 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4772 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4773 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4774 req->flags = rte_cpu_to_le_16(flags);
4777 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4778 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4780 struct hwrm_ring_aggint_qcaps_input req = {0};
4781 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4786 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4787 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4788 HWRM_CHECK_RESULT();
4790 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4791 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4793 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4794 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4795 agg_req->flags = rte_cpu_to_le_16(flags);
4797 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4798 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4799 agg_req->enables = rte_cpu_to_le_32(enables);
4805 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4806 struct bnxt_coal *coal, uint16_t ring_id)
4808 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4809 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4810 bp->hwrm_cmd_resp_addr;
4813 /* Set ring coalesce parameters only for 100G NICs */
4814 if (BNXT_CHIP_THOR(bp)) {
4815 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4817 } else if (bnxt_stratus_device(bp)) {
4818 bnxt_hwrm_set_coal_params(coal, &req);
4824 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4826 req.ring_id = rte_cpu_to_le_16(ring_id);
4827 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4828 HWRM_CHECK_RESULT();
4833 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4834 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4836 struct hwrm_func_backing_store_qcaps_input req = {0};
4837 struct hwrm_func_backing_store_qcaps_output *resp =
4838 bp->hwrm_cmd_resp_addr;
4839 struct bnxt_ctx_pg_info *ctx_pg;
4840 struct bnxt_ctx_mem_info *ctx;
4841 int total_alloc_len;
4842 int rc, i, tqm_rings;
4844 if (!BNXT_CHIP_THOR(bp) ||
4845 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4850 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4852 HWRM_CHECK_RESULT_SILENT();
4854 total_alloc_len = sizeof(*ctx);
4855 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4856 RTE_CACHE_LINE_SIZE);
4862 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4863 ctx->qp_min_qp1_entries =
4864 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4865 ctx->qp_max_l2_entries =
4866 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4867 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4868 ctx->srq_max_l2_entries =
4869 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4870 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4871 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4872 ctx->cq_max_l2_entries =
4873 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4874 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4875 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4876 ctx->vnic_max_vnic_entries =
4877 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4878 ctx->vnic_max_ring_table_entries =
4879 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4880 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4881 ctx->stat_max_entries =
4882 rte_le_to_cpu_32(resp->stat_max_entries);
4883 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4884 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4885 ctx->tqm_min_entries_per_ring =
4886 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4887 ctx->tqm_max_entries_per_ring =
4888 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4889 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4890 if (!ctx->tqm_entries_multiple)
4891 ctx->tqm_entries_multiple = 1;
4892 ctx->mrav_max_entries =
4893 rte_le_to_cpu_32(resp->mrav_max_entries);
4894 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4895 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4896 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4897 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4899 if (!ctx->tqm_fp_rings_count)
4900 ctx->tqm_fp_rings_count = bp->max_q;
4902 tqm_rings = ctx->tqm_fp_rings_count + 1;
4904 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4905 sizeof(*ctx_pg) * tqm_rings,
4906 RTE_CACHE_LINE_SIZE);
4911 for (i = 0; i < tqm_rings; i++, ctx_pg++)
4912 ctx->tqm_mem[i] = ctx_pg;
4920 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4922 struct hwrm_func_backing_store_cfg_input req = {0};
4923 struct hwrm_func_backing_store_cfg_output *resp =
4924 bp->hwrm_cmd_resp_addr;
4925 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4926 struct bnxt_ctx_pg_info *ctx_pg;
4927 uint32_t *num_entries;
4936 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4937 req.enables = rte_cpu_to_le_32(enables);
4939 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4940 ctx_pg = &ctx->qp_mem;
4941 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4942 req.qp_num_qp1_entries =
4943 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4944 req.qp_num_l2_entries =
4945 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4946 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4947 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4948 &req.qpc_pg_size_qpc_lvl,
4952 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4953 ctx_pg = &ctx->srq_mem;
4954 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4955 req.srq_num_l2_entries =
4956 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4957 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4958 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4959 &req.srq_pg_size_srq_lvl,
4963 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4964 ctx_pg = &ctx->cq_mem;
4965 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4966 req.cq_num_l2_entries =
4967 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4968 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4969 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4970 &req.cq_pg_size_cq_lvl,
4974 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4975 ctx_pg = &ctx->vnic_mem;
4976 req.vnic_num_vnic_entries =
4977 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4978 req.vnic_num_ring_table_entries =
4979 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4980 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4981 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4982 &req.vnic_pg_size_vnic_lvl,
4983 &req.vnic_page_dir);
4986 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4987 ctx_pg = &ctx->stat_mem;
4988 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4989 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4990 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4991 &req.stat_pg_size_stat_lvl,
4992 &req.stat_page_dir);
4995 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4996 num_entries = &req.tqm_sp_num_entries;
4997 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4998 pg_dir = &req.tqm_sp_page_dir;
4999 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5000 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5001 if (!(enables & ena))
5004 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5006 ctx_pg = ctx->tqm_mem[i];
5007 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5008 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5011 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5012 HWRM_CHECK_RESULT();
5018 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5020 struct hwrm_port_qstats_ext_input req = {0};
5021 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5022 struct bnxt_pf_info *pf = bp->pf;
5025 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5026 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5029 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5031 req.port_id = rte_cpu_to_le_16(pf->port_id);
5032 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5033 req.tx_stat_host_addr =
5034 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5036 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5038 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5039 req.rx_stat_host_addr =
5040 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5042 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5044 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5047 bp->fw_rx_port_stats_ext_size = 0;
5048 bp->fw_tx_port_stats_ext_size = 0;
5050 bp->fw_rx_port_stats_ext_size =
5051 rte_le_to_cpu_16(resp->rx_stat_size);
5052 bp->fw_tx_port_stats_ext_size =
5053 rte_le_to_cpu_16(resp->tx_stat_size);
5056 HWRM_CHECK_RESULT();
5063 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5065 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5066 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5067 bp->hwrm_cmd_resp_addr;
5070 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5071 req.tunnel_type = type;
5072 req.dest_fid = bp->fw_fid;
5073 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5074 HWRM_CHECK_RESULT();
5082 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5084 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5085 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5086 bp->hwrm_cmd_resp_addr;
5089 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5090 req.tunnel_type = type;
5091 req.dest_fid = bp->fw_fid;
5092 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5093 HWRM_CHECK_RESULT();
5100 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5102 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5103 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5104 bp->hwrm_cmd_resp_addr;
5107 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5108 req.src_fid = bp->fw_fid;
5109 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5110 HWRM_CHECK_RESULT();
5113 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5120 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5123 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5124 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5125 bp->hwrm_cmd_resp_addr;
5128 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5129 req.src_fid = bp->fw_fid;
5130 req.tunnel_type = tun_type;
5131 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5132 HWRM_CHECK_RESULT();
5135 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5137 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5144 int bnxt_hwrm_set_mac(struct bnxt *bp)
5146 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5147 struct hwrm_func_vf_cfg_input req = {0};
5153 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5156 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5157 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5159 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5161 HWRM_CHECK_RESULT();
5168 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5170 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5171 struct hwrm_func_drv_if_change_input req = {0};
5175 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5178 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5179 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5180 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5182 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5185 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5189 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5191 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5193 HWRM_CHECK_RESULT();
5194 flags = rte_le_to_cpu_32(resp->flags);
5200 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5201 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5202 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5208 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5210 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5211 struct bnxt_error_recovery_info *info = bp->recovery_info;
5212 struct hwrm_error_recovery_qcfg_input req = {0};
5217 /* Older FW does not have error recovery support */
5218 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5221 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5223 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5225 HWRM_CHECK_RESULT();
5227 flags = rte_le_to_cpu_32(resp->flags);
5228 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5229 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5230 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5231 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5233 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5234 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5239 /* FW returned values are in units of 100msec */
5240 info->driver_polling_freq =
5241 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5242 info->master_func_wait_period =
5243 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5244 info->normal_func_wait_period =
5245 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5246 info->master_func_wait_period_after_reset =
5247 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5248 info->max_bailout_time_after_reset =
5249 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5250 info->status_regs[BNXT_FW_STATUS_REG] =
5251 rte_le_to_cpu_32(resp->fw_health_status_reg);
5252 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5253 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5254 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5255 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5256 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5257 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5258 info->reg_array_cnt =
5259 rte_le_to_cpu_32(resp->reg_array_cnt);
5261 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5266 for (i = 0; i < info->reg_array_cnt; i++) {
5267 info->reset_reg[i] =
5268 rte_le_to_cpu_32(resp->reset_reg[i]);
5269 info->reset_reg_val[i] =
5270 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5271 info->delay_after_reset[i] =
5272 resp->delay_after_reset[i];
5277 /* Map the FW status registers */
5279 rc = bnxt_map_fw_health_status_regs(bp);
5282 rte_free(bp->recovery_info);
5283 bp->recovery_info = NULL;
5288 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5290 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5291 struct hwrm_fw_reset_input req = {0};
5297 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5299 req.embedded_proc_type =
5300 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5301 req.selfrst_status =
5302 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5303 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5305 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5308 HWRM_CHECK_RESULT();
5314 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5316 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5317 struct hwrm_port_ts_query_input req = {0};
5318 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5325 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5328 case BNXT_PTP_FLAGS_PATH_TX:
5329 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5331 case BNXT_PTP_FLAGS_PATH_RX:
5332 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5334 case BNXT_PTP_FLAGS_CURRENT_TIME:
5335 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5339 req.flags = rte_cpu_to_le_32(flags);
5340 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5342 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5344 HWRM_CHECK_RESULT();
5347 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5349 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5356 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5360 struct hwrm_cfa_counter_qcaps_input req = {0};
5361 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5363 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5365 "Not a PF or trusted VF. Command not supported\n");
5369 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5370 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5371 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5373 HWRM_CHECK_RESULT();
5375 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5381 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5384 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5385 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5387 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5389 "Not a PF or trusted VF. Command not supported\n");
5393 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5395 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5396 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5397 req.page_dir = rte_cpu_to_le_64(dma_addr);
5399 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5401 HWRM_CHECK_RESULT();
5403 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5404 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5411 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5414 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5415 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5417 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5419 "Not a PF or trusted VF. Command not supported\n");
5423 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5425 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5427 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5429 HWRM_CHECK_RESULT();
5435 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5436 uint16_t cntr, uint16_t ctx_id,
5437 uint32_t num_entries, bool enable)
5439 struct hwrm_cfa_counter_cfg_input req = {0};
5440 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5444 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5446 "Not a PF or trusted VF. Command not supported\n");
5450 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5452 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5453 req.counter_type = rte_cpu_to_le_16(cntr);
5454 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5455 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5456 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5457 if (dir == BNXT_DIR_RX)
5458 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5459 else if (dir == BNXT_DIR_TX)
5460 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5461 req.flags = rte_cpu_to_le_16(flags);
5462 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5463 req.num_entries = rte_cpu_to_le_32(num_entries);
5465 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5466 HWRM_CHECK_RESULT();
5472 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5473 enum bnxt_flow_dir dir,
5475 uint16_t num_entries)
5477 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5478 struct hwrm_cfa_counter_qstats_input req = {0};
5479 uint16_t flow_ctx_id = 0;
5483 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5485 "Not a PF or trusted VF. Command not supported\n");
5489 if (dir == BNXT_DIR_RX) {
5490 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5491 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5492 } else if (dir == BNXT_DIR_TX) {
5493 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5494 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5497 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5498 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5499 req.counter_type = rte_cpu_to_le_16(cntr);
5500 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5501 req.num_entries = rte_cpu_to_le_16(num_entries);
5502 req.flags = rte_cpu_to_le_16(flags);
5503 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5505 HWRM_CHECK_RESULT();
5511 int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx)
5513 struct hwrm_cfa_vfr_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5514 struct hwrm_cfa_vfr_alloc_input req = {0};
5517 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5519 "Not a PF or trusted VF. Command not supported\n");
5523 HWRM_PREP(&req, HWRM_CFA_VFR_ALLOC, BNXT_USE_CHIMP_MB);
5524 req.vf_id = rte_cpu_to_le_16(vf_idx);
5525 snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5526 bp->eth_dev->data->name, vf_idx);
5528 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5529 HWRM_CHECK_RESULT();
5532 PMD_DRV_LOG(DEBUG, "VFR %d allocated\n", vf_idx);
5536 int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx)
5538 struct hwrm_cfa_vfr_free_output *resp = bp->hwrm_cmd_resp_addr;
5539 struct hwrm_cfa_vfr_free_input req = {0};
5542 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5544 "Not a PF or trusted VF. Command not supported\n");
5548 HWRM_PREP(&req, HWRM_CFA_VFR_FREE, BNXT_USE_CHIMP_MB);
5549 req.vf_id = rte_cpu_to_le_16(vf_idx);
5550 snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5551 bp->eth_dev->data->name, vf_idx);
5553 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5554 HWRM_CHECK_RESULT();
5556 PMD_DRV_LOG(DEBUG, "VFR %d freed\n", vf_idx);