drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (BNXT_CHIP_P5(bp)) {
 754                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
 755                         return 0;
 756         } else {
 757                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 758                         return 0;
 759         }
 760
 761         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 762                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 763
 764         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 765         if (!ptp)
 766                 return -ENOMEM;
 767
 768         if (!BNXT_CHIP_P5(bp)) {
 769                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 771                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 773                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 775                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 776                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 777                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 778                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 779                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 781                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 783                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 784                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 785                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 786                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 787         }
 788
 789         ptp->bp = bp;
 790         bp->ptp_cfg = ptp;
 791
 792         return 0;
 793 }
 794
 795 void bnxt_free_vf_info(struct bnxt *bp)
 796 {
 797         int i;
 798
 799         if (bp->pf == NULL)
 800                 return;
 801
 802         if (bp->pf->vf_info == NULL)
 803                 return;
 804
 805         for (i = 0; i < bp->pf->max_vfs; i++) {
 806                 rte_free(bp->pf->vf_info[i].vlan_table);
 807                 bp->pf->vf_info[i].vlan_table = NULL;
 808                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 809                 bp->pf->vf_info[i].vlan_as_table = NULL;
 810         }
 811         rte_free(bp->pf->vf_info);
 812         bp->pf->vf_info = NULL;
 813 }
 814
 815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 816 {
 817         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 818         int i;
 819
 820         if (vf_info)
 821                 bnxt_free_vf_info(bp);
 822
 823         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 824         if (vf_info == NULL) {
 825                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 826                 return -ENOMEM;
 827         }
 828
 829         bp->pf->max_vfs = max_vfs;
 830         for (i = 0; i < max_vfs; i++) {
 831                 vf_info[i].fid = bp->pf->first_vf_id + i;
 832                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 833                                                     getpagesize(), getpagesize());
 834                 if (vf_info[i].vlan_table == NULL) {
 835                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 836                         goto err;
 837                 }
 838                 rte_mem_lock_page(vf_info[i].vlan_table);
 839
 840                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 841                                                        getpagesize(), getpagesize());
 842                 if (vf_info[i].vlan_as_table == NULL) {
 843                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 844                         goto err;
 845                 }
 846                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 847
 848                 STAILQ_INIT(&vf_info[i].filter);
 849         }
 850
 851         bp->pf->vf_info = vf_info;
 852
 853         return 0;
 854 err:
 855         bnxt_free_vf_info(bp);
 856         return -ENOMEM;
 857 }
 858
 859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 860 {
 861         int rc = 0;
 862         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 863         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 864         uint16_t new_max_vfs;
 865         uint32_t flags;
 866
 867         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 868
 869         req.fid = rte_cpu_to_le_16(0xffff);
 870
 871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 872
 873         HWRM_CHECK_RESULT();
 874
 875         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 876         flags = rte_le_to_cpu_32(resp->flags);
 877         if (BNXT_PF(bp)) {
 878                 bp->pf->port_id = resp->port_id;
 879                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 880                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 881                 new_max_vfs = bp->pdev->max_vfs;
 882                 if (new_max_vfs != bp->pf->max_vfs) {
 883                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 884                         if (rc)
 885                                 goto unlock;
 886                 }
 887         }
 888
 889         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 890         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 891                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 892                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 893         } else {
 894                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 895         }
 896         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 897         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 898         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 899         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 900         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 901         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 902         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 903         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 904                 bp->max_l2_ctx += bp->max_rx_em_flows;
 905         /* TODO: For now, do not support VMDq/RFS on VFs. */
 906         if (BNXT_PF(bp)) {
 907                 if (bp->pf->max_vfs)
 908                         bp->max_vnics = 1;
 909                 else
 910                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 911         } else {
 912                 bp->max_vnics = 1;
 913         }
 914         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 915                     bp->max_l2_ctx, bp->max_vnics);
 916         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 917         if (BNXT_PF(bp)) {
 918                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 919                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 920                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 921                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 922                         HWRM_UNLOCK();
 923                         bnxt_hwrm_ptp_qcfg(bp);
 924                 }
 925         }
 926
 927         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 928                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 929
 930         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 931                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 932                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 933         }
 934
 935         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 936                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 937
 938         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 939                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 940
 941         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 942                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 943
 944         if (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) {
 945                 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
 946                 PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n");
 947         }
 948 unlock:
 949         HWRM_UNLOCK();
 950
 951         return rc;
 952 }
 953
 954 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 955 {
 956         int rc;
 957
 958         rc = __bnxt_hwrm_func_qcaps(bp);
 959         if (rc == -ENOMEM)
 960                 return rc;
 961
 962         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 963                 rc = bnxt_alloc_ctx_mem(bp);
 964                 if (rc)
 965                         return rc;
 966
 967                 /* On older FW,
 968                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 969                  * But the error can be ignored. Return success.
 970                  */
 971                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 972                 if (!rc)
 973                         bp->flags |= BNXT_FLAG_NEW_RM;
 974         }
 975
 976         return 0;
 977 }
 978
 979 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 980 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 981 {
 982         int rc = 0;
 983         uint32_t flags;
 984         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 985         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 986
 987         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 988
 989         req.target_id = rte_cpu_to_le_16(0xffff);
 990
 991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 992
 993         HWRM_CHECK_RESULT();
 994
 995         flags = rte_le_to_cpu_32(resp->flags);
 996
 997         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 998                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 999                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
1000         }
1001
1002         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
1003                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1004
1005         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1006                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1007
1008         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP) {
1009                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_VLAN_RX_STRIP;
1010                 PMD_DRV_LOG(DEBUG, "Rx VLAN strip capability enabled\n");
1011         }
1012
1013         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1014
1015         HWRM_UNLOCK();
1016
1017         return rc;
1018 }
1019
1020 int bnxt_hwrm_func_reset(struct bnxt *bp)
1021 {
1022         int rc = 0;
1023         struct hwrm_func_reset_input req = {.req_type = 0 };
1024         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1025
1026         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1027
1028         req.enables = rte_cpu_to_le_32(0);
1029
1030         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1031
1032         HWRM_CHECK_RESULT();
1033         HWRM_UNLOCK();
1034
1035         return rc;
1036 }
1037
1038 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1039 {
1040         int rc;
1041         uint32_t flags = 0;
1042         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1043         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1044
1045         if (bp->flags & BNXT_FLAG_REGISTERED)
1046                 return 0;
1047
1048         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1049                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1050         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1051                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1052
1053         /* PFs and trusted VFs should indicate the support of the
1054          * Master capability on non Stingray platform
1055          */
1056         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1057                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1058
1059         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1060         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1061                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1062         req.ver_maj = RTE_VER_YEAR;
1063         req.ver_min = RTE_VER_MONTH;
1064         req.ver_upd = RTE_VER_MINOR;
1065
1066         if (BNXT_PF(bp)) {
1067                 req.enables |= rte_cpu_to_le_32(
1068                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1069                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1070                        RTE_MIN(sizeof(req.vf_req_fwd),
1071                                sizeof(bp->pf->vf_req_fwd)));
1072         }
1073
1074         req.flags = rte_cpu_to_le_32(flags);
1075
1076         req.async_event_fwd[0] |=
1077                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1078                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1079                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1080                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1081                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1082         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1083                 req.async_event_fwd[0] |=
1084                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1085         req.async_event_fwd[1] |=
1086                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1087                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1088         if (BNXT_PF(bp))
1089                 req.async_event_fwd[1] |=
1090                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1091
1092         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1093                 req.async_event_fwd[1] |=
1094                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1095
1096         req.async_event_fwd[2] |=
1097                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST |
1098                                  ASYNC_CMPL_EVENT_ID_ERROR_REPORT);
1099
1100         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1101
1102         HWRM_CHECK_RESULT();
1103
1104         flags = rte_le_to_cpu_32(resp->flags);
1105         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1106                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1107
1108         HWRM_UNLOCK();
1109
1110         bp->flags |= BNXT_FLAG_REGISTERED;
1111
1112         return rc;
1113 }
1114
1115 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1116 {
1117         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1118                 return 0;
1119
1120         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1121 }
1122
1123 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1124 {
1125         int rc;
1126         uint32_t flags = 0;
1127         uint32_t enables;
1128         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1129         struct hwrm_func_vf_cfg_input req = {0};
1130
1131         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1132
1133         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1134                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1135                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1136                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1137                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1138
1139         if (BNXT_HAS_RING_GRPS(bp)) {
1140                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1141                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1142         }
1143
1144         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1145         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1146                                             AGG_RING_MULTIPLIER);
1147         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1148         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1149                                               bp->tx_nr_rings +
1150                                               BNXT_NUM_ASYNC_CPR(bp));
1151         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1152         if (bp->vf_resv_strategy ==
1153             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1154                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1155                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1156                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1157                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1158                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1159                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1160         } else if (bp->vf_resv_strategy ==
1161                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1162                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1163                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1164         }
1165
1166         if (test)
1167                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1168                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1169                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1170                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1171                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1172                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1173
1174         if (test && BNXT_HAS_RING_GRPS(bp))
1175                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1176
1177         req.flags = rte_cpu_to_le_32(flags);
1178         req.enables |= rte_cpu_to_le_32(enables);
1179
1180         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1181
1182         if (test)
1183                 HWRM_CHECK_RESULT_SILENT();
1184         else
1185                 HWRM_CHECK_RESULT();
1186
1187         HWRM_UNLOCK();
1188         return rc;
1189 }
1190
1191 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1192 {
1193         int rc;
1194         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1195         struct hwrm_func_resource_qcaps_input req = {0};
1196
1197         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1198         req.fid = rte_cpu_to_le_16(0xffff);
1199
1200         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1201
1202         HWRM_CHECK_RESULT_SILENT();
1203
1204         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1205         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1206         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1207         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1208         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1209         /* func_resource_qcaps does not return max_rx_em_flows.
1210          * So use the value provided by func_qcaps.
1211          */
1212         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1213         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1214                 bp->max_l2_ctx += bp->max_rx_em_flows;
1215         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1216         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1217         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1218         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1219         if (bp->vf_resv_strategy >
1220             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1221                 bp->vf_resv_strategy =
1222                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1223
1224         HWRM_UNLOCK();
1225         return rc;
1226 }
1227
1228 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1229 {
1230         int rc = 0;
1231         struct hwrm_ver_get_input req = {.req_type = 0 };
1232         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1233         uint32_t fw_version;
1234         uint16_t max_resp_len;
1235         char type[RTE_MEMZONE_NAMESIZE];
1236         uint32_t dev_caps_cfg;
1237
1238         bp->max_req_len = HWRM_MAX_REQ_LEN;
1239         bp->hwrm_cmd_timeout = timeout;
1240         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1241
1242         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1243         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1244         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1245
1246         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1247
1248         if (bp->flags & BNXT_FLAG_FW_RESET)
1249                 HWRM_CHECK_RESULT_SILENT();
1250         else
1251                 HWRM_CHECK_RESULT();
1252
1253         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1254                 rc = -EAGAIN;
1255                 goto error;
1256         }
1257
1258         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1259                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1260                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1261                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1262                 resp->hwrm_fw_rsvd_8b);
1263         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1264                      (resp->hwrm_fw_min_8b << 16) |
1265                      (resp->hwrm_fw_bld_8b << 8) |
1266                      resp->hwrm_fw_rsvd_8b;
1267         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1268                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1269
1270         fw_version = resp->hwrm_intf_maj_8b << 16;
1271         fw_version |= resp->hwrm_intf_min_8b << 8;
1272         fw_version |= resp->hwrm_intf_upd_8b;
1273         bp->hwrm_spec_code = fw_version;
1274
1275         /* def_req_timeout value is in milliseconds */
1276         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1277         /* convert timeout to usec */
1278         bp->hwrm_cmd_timeout *= 1000;
1279         if (!bp->hwrm_cmd_timeout)
1280                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1281
1282         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1283                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1284                 rc = -EINVAL;
1285                 goto error;
1286         }
1287
1288         if (bp->max_req_len > resp->max_req_win_len) {
1289                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1290                 rc = -EINVAL;
1291                 goto error;
1292         }
1293
1294         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1295
1296         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1297         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1298         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1299                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1300
1301         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1302         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1303
1304         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1305         bp->max_resp_len = max_resp_len;
1306
1307         if ((dev_caps_cfg &
1308                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1309             (dev_caps_cfg &
1310              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1311                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1312                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1313         }
1314
1315         if (((dev_caps_cfg &
1316               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1317              (dev_caps_cfg &
1318               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1319             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1320                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1321                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1322                         bp->pdev->addr.devid, bp->pdev->addr.function);
1323
1324                 rte_free(bp->hwrm_short_cmd_req_addr);
1325
1326                 bp->hwrm_short_cmd_req_addr =
1327                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1328                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1329                         rc = -ENOMEM;
1330                         goto error;
1331                 }
1332                 bp->hwrm_short_cmd_req_dma_addr =
1333                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1334                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1335                         rte_free(bp->hwrm_short_cmd_req_addr);
1336                         PMD_DRV_LOG(ERR,
1337                                 "Unable to map buffer to physical memory.\n");
1338                         rc = -ENOMEM;
1339                         goto error;
1340                 }
1341         }
1342         if (dev_caps_cfg &
1343             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1344                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1345                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1346         }
1347         if (dev_caps_cfg &
1348             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1349                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1350         if (dev_caps_cfg &
1351             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1352                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1353                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1354         }
1355
1356         if (dev_caps_cfg &
1357             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1358                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1359                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1360         }
1361
1362         if (dev_caps_cfg &
1363             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
1364                 PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
1365                 bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
1366         }
1367
1368 error:
1369         HWRM_UNLOCK();
1370         return rc;
1371 }
1372
1373 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1374 {
1375         int rc;
1376         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1377         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1378
1379         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1380                 return 0;
1381
1382         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1383         req.flags = flags;
1384
1385         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1386
1387         HWRM_CHECK_RESULT();
1388         HWRM_UNLOCK();
1389
1390         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1391                     bp->eth_dev->data->port_id);
1392
1393         return rc;
1394 }
1395
1396 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1397 {
1398         int rc = 0;
1399         struct hwrm_port_phy_cfg_input req = {0};
1400         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1401         uint32_t enables = 0;
1402
1403         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1404
1405         if (conf->link_up) {
1406                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1407                 if (bp->link_info->auto_mode && conf->link_speed) {
1408                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1409                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1410                 }
1411
1412                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1413                 /*
1414                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1415                  * any auto mode, even "none".
1416                  */
1417                 if (!conf->link_speed) {
1418                         /* No speeds specified. Enable AutoNeg - all speeds */
1419                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1420                         req.auto_mode =
1421                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1422                 } else {
1423                         if (bp->link_info->link_signal_mode) {
1424                                 enables |=
1425                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1426                                 req.force_pam4_link_speed =
1427                                         rte_cpu_to_le_16(conf->link_speed);
1428                         } else {
1429                                 req.force_link_speed =
1430                                         rte_cpu_to_le_16(conf->link_speed);
1431                         }
1432                 }
1433                 /* AutoNeg - Advertise speeds specified. */
1434                 if (conf->auto_link_speed_mask &&
1435                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1436                         req.auto_mode =
1437                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1438                         req.auto_link_speed_mask =
1439                                 conf->auto_link_speed_mask;
1440                         if (conf->auto_pam4_link_speeds) {
1441                                 enables |=
1442                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1443                                 req.auto_link_pam4_speed_mask =
1444                                         conf->auto_pam4_link_speeds;
1445                         } else {
1446                                 enables |=
1447                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1448                         }
1449                 }
1450                 if (conf->auto_link_speed &&
1451                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1452                         enables |=
1453                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1454
1455                 req.auto_duplex = conf->duplex;
1456                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1457                 req.auto_pause = conf->auto_pause;
1458                 req.force_pause = conf->force_pause;
1459                 /* Set force_pause if there is no auto or if there is a force */
1460                 if (req.auto_pause && !req.force_pause)
1461                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1462                 else
1463                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1464
1465                 req.enables = rte_cpu_to_le_32(enables);
1466         } else {
1467                 req.flags =
1468                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1469                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1470         }
1471
1472         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1473
1474         HWRM_CHECK_RESULT();
1475         HWRM_UNLOCK();
1476
1477         return rc;
1478 }
1479
1480 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1481                                    struct bnxt_link_info *link_info)
1482 {
1483         int rc = 0;
1484         struct hwrm_port_phy_qcfg_input req = {0};
1485         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1486
1487         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1488
1489         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1490
1491         HWRM_CHECK_RESULT();
1492
1493         link_info->phy_link_status = resp->link;
1494         link_info->link_up =
1495                 (link_info->phy_link_status ==
1496                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1497         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1498         link_info->duplex = resp->duplex_cfg;
1499         link_info->pause = resp->pause;
1500         link_info->auto_pause = resp->auto_pause;
1501         link_info->force_pause = resp->force_pause;
1502         link_info->auto_mode = resp->auto_mode;
1503         link_info->phy_type = resp->phy_type;
1504         link_info->media_type = resp->media_type;
1505
1506         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1507         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1508         link_info->auto_link_speed_mask = rte_le_to_cpu_16(resp->auto_link_speed_mask);
1509         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1510         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1511         link_info->phy_ver[0] = resp->phy_maj;
1512         link_info->phy_ver[1] = resp->phy_min;
1513         link_info->phy_ver[2] = resp->phy_bld;
1514         link_info->link_signal_mode =
1515                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1516         link_info->force_pam4_link_speed =
1517                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1518         link_info->support_pam4_speeds =
1519                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1520         link_info->auto_pam4_link_speeds =
1521                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1522         link_info->module_status = resp->module_status;
1523         HWRM_UNLOCK();
1524
1525         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1526                     link_info->link_speed, link_info->auto_mode,
1527                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1528                     link_info->support_speeds, link_info->force_link_speed);
1529         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1530                     link_info->link_signal_mode,
1531                     link_info->auto_pam4_link_speeds,
1532                     link_info->support_pam4_speeds,
1533                     link_info->force_pam4_link_speed);
1534         return rc;
1535 }
1536
1537 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1538 {
1539         int rc = 0;
1540         struct hwrm_port_phy_qcaps_input req = {0};
1541         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1542         struct bnxt_link_info *link_info = bp->link_info;
1543
1544         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1545                 return 0;
1546
1547         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1548
1549         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1550
1551         HWRM_CHECK_RESULT_SILENT();
1552
1553         bp->port_cnt = resp->port_cnt;
1554         if (resp->supported_speeds_auto_mode)
1555                 link_info->support_auto_speeds =
1556                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1557         if (resp->supported_pam4_speeds_auto_mode)
1558                 link_info->support_pam4_auto_speeds =
1559                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1560
1561         HWRM_UNLOCK();
1562
1563         /* Older firmware does not have supported_auto_speeds, so assume
1564          * that all supported speeds can be autonegotiated.
1565          */
1566         if (link_info->auto_link_speed_mask && !link_info->support_auto_speeds)
1567                 link_info->support_auto_speeds = link_info->support_speeds;
1568
1569         return 0;
1570 }
1571
1572 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1573 {
1574         int i = 0;
1575
1576         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1577                 if (bp->tx_cos_queue[i].profile ==
1578                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1579                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1580                         return true;
1581                 }
1582         }
1583         return false;
1584 }
1585
1586 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1587 {
1588         int i = 0;
1589
1590         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1591                 if (bp->tx_cos_queue[i].profile !=
1592                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1593                     bp->tx_cos_queue[i].id !=
1594                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1595                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1596                         break;
1597                 }
1598         }
1599 }
1600
1601 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1602 {
1603         int rc = 0;
1604         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1605         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1606         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1607         int i;
1608
1609 get_rx_info:
1610         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1611
1612         req.flags = rte_cpu_to_le_32(dir);
1613         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1614         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1615             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1616                 req.drv_qmap_cap =
1617                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1618         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1619
1620         HWRM_CHECK_RESULT();
1621
1622         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1623                 GET_TX_QUEUE_INFO(0);
1624                 GET_TX_QUEUE_INFO(1);
1625                 GET_TX_QUEUE_INFO(2);
1626                 GET_TX_QUEUE_INFO(3);
1627                 GET_TX_QUEUE_INFO(4);
1628                 GET_TX_QUEUE_INFO(5);
1629                 GET_TX_QUEUE_INFO(6);
1630                 GET_TX_QUEUE_INFO(7);
1631         } else  {
1632                 GET_RX_QUEUE_INFO(0);
1633                 GET_RX_QUEUE_INFO(1);
1634                 GET_RX_QUEUE_INFO(2);
1635                 GET_RX_QUEUE_INFO(3);
1636                 GET_RX_QUEUE_INFO(4);
1637                 GET_RX_QUEUE_INFO(5);
1638                 GET_RX_QUEUE_INFO(6);
1639                 GET_RX_QUEUE_INFO(7);
1640         }
1641
1642         HWRM_UNLOCK();
1643
1644         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1645                 goto done;
1646
1647         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1648                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1649         } else {
1650                 int j;
1651
1652                 /* iterate and find the COSq profile to use for Tx */
1653                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1654                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1655                                 if (bp->tx_cos_queue[i].id != 0xff)
1656                                         bp->tx_cosq_id[j++] =
1657                                                 bp->tx_cos_queue[i].id;
1658                         }
1659                 } else {
1660                         /* When CoS classification is disabled, for normal NIC
1661                          * operations, ideally we should look to use LOSSY.
1662                          * If not found, fallback to the first valid profile
1663                          */
1664                         if (!bnxt_find_lossy_profile(bp))
1665                                 bnxt_find_first_valid_profile(bp);
1666
1667                 }
1668         }
1669
1670         bp->max_tc = resp->max_configurable_queues;
1671         bp->max_lltc = resp->max_configurable_lossless_queues;
1672         if (bp->max_tc > BNXT_MAX_QUEUE)
1673                 bp->max_tc = BNXT_MAX_QUEUE;
1674         bp->max_q = bp->max_tc;
1675
1676         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1677                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1678                 goto get_rx_info;
1679         }
1680
1681 done:
1682         return rc;
1683 }
1684
1685 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1686                          struct bnxt_ring *ring,
1687                          uint32_t ring_type, uint32_t map_index,
1688                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1689                          uint16_t tx_cosq_id)
1690 {
1691         int rc = 0;
1692         uint32_t enables = 0;
1693         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1694         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1695         struct rte_mempool *mb_pool;
1696         uint16_t rx_buf_size;
1697
1698         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1699
1700         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1701         req.fbo = rte_cpu_to_le_32(0);
1702         /* Association of ring index with doorbell index */
1703         req.logical_id = rte_cpu_to_le_16(map_index);
1704         req.length = rte_cpu_to_le_32(ring->ring_size);
1705
1706         switch (ring_type) {
1707         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1708                 req.ring_type = ring_type;
1709                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1710                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1711                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1712                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1713                         enables |=
1714                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1715                 break;
1716         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1717                 req.ring_type = ring_type;
1718                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1719                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1720                 if (BNXT_CHIP_P5(bp)) {
1721                         mb_pool = bp->rx_queues[0]->mb_pool;
1722                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1723                                       RTE_PKTMBUF_HEADROOM;
1724                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1725                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1726                         enables |=
1727                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1728                 }
1729                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1730                         enables |=
1731                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1732                 break;
1733         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1734                 req.ring_type = ring_type;
1735                 if (BNXT_HAS_NQ(bp)) {
1736                         /* Association of cp ring with nq */
1737                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1738                         enables |=
1739                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1740                 }
1741                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1742                 break;
1743         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1744                 req.ring_type = ring_type;
1745                 req.page_size = BNXT_PAGE_SHFT;
1746                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1747                 break;
1748         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1749                 req.ring_type = ring_type;
1750                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1751
1752                 mb_pool = bp->rx_queues[0]->mb_pool;
1753                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1754                               RTE_PKTMBUF_HEADROOM;
1755                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1756                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1757
1758                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1759                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1760                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1761                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1762                 break;
1763         default:
1764                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1765                         ring_type);
1766                 HWRM_UNLOCK();
1767                 return -EINVAL;
1768         }
1769         req.enables = rte_cpu_to_le_32(enables);
1770
1771         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1772
1773         if (rc || resp->error_code) {
1774                 if (rc == 0 && resp->error_code)
1775                         rc = rte_le_to_cpu_16(resp->error_code);
1776                 switch (ring_type) {
1777                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1778                         PMD_DRV_LOG(ERR,
1779                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1780                         HWRM_UNLOCK();
1781                         return rc;
1782                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1783                         PMD_DRV_LOG(ERR,
1784                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1785                         HWRM_UNLOCK();
1786                         return rc;
1787                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1788                         PMD_DRV_LOG(ERR,
1789                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1790                                     rc);
1791                         HWRM_UNLOCK();
1792                         return rc;
1793                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1794                         PMD_DRV_LOG(ERR,
1795                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1796                         HWRM_UNLOCK();
1797                         return rc;
1798                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1799                         PMD_DRV_LOG(ERR,
1800                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1801                         HWRM_UNLOCK();
1802                         return rc;
1803                 default:
1804                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1805                         HWRM_UNLOCK();
1806                         return rc;
1807                 }
1808         }
1809
1810         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1811         HWRM_UNLOCK();
1812         return rc;
1813 }
1814
1815 int bnxt_hwrm_ring_free(struct bnxt *bp,
1816                         struct bnxt_ring *ring, uint32_t ring_type,
1817                         uint16_t cp_ring_id)
1818 {
1819         int rc;
1820         struct hwrm_ring_free_input req = {.req_type = 0 };
1821         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1822
1823         if (ring->fw_ring_id == INVALID_HW_RING_ID)
1824                 return -EINVAL;
1825
1826         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1827
1828         req.ring_type = ring_type;
1829         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1830         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1831
1832         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1833         ring->fw_ring_id = INVALID_HW_RING_ID;
1834
1835         if (rc || resp->error_code) {
1836                 if (rc == 0 && resp->error_code)
1837                         rc = rte_le_to_cpu_16(resp->error_code);
1838                 HWRM_UNLOCK();
1839
1840                 switch (ring_type) {
1841                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1842                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1843                                 rc);
1844                         return rc;
1845                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1846                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1847                                 rc);
1848                         return rc;
1849                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1850                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1851                                 rc);
1852                         return rc;
1853                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1854                         PMD_DRV_LOG(ERR,
1855                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1856                         return rc;
1857                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1858                         PMD_DRV_LOG(ERR,
1859                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1860                         return rc;
1861                 default:
1862                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1863                         return rc;
1864                 }
1865         }
1866         HWRM_UNLOCK();
1867         return 0;
1868 }
1869
1870 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1871 {
1872         int rc = 0;
1873         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1874         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1875
1876         /* Don't attempt to re-create the ring group if it is already created */
1877         if (bp->grp_info[idx].fw_grp_id != INVALID_HW_RING_ID)
1878                 return 0;
1879
1880         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1881
1882         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1883         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1884         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1885         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1886
1887         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1888
1889         HWRM_CHECK_RESULT();
1890
1891         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1892
1893         HWRM_UNLOCK();
1894
1895         return rc;
1896 }
1897
1898 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1899 {
1900         int rc;
1901         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1902         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1903
1904         if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1905                 return 0;
1906
1907         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1908
1909         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1910
1911         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1912
1913         HWRM_CHECK_RESULT();
1914         HWRM_UNLOCK();
1915
1916         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1917         return rc;
1918 }
1919
1920 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1921 {
1922         int rc = 0;
1923         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1924         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1925
1926         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1927                 return rc;
1928
1929         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1930
1931         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1932
1933         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1934
1935         HWRM_CHECK_RESULT();
1936         HWRM_UNLOCK();
1937
1938         return rc;
1939 }
1940
1941 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1942 {
1943         int rc;
1944         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1945         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1946
1947         if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE)
1948                 return 0;
1949
1950         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1951
1952         req.update_period_ms = rte_cpu_to_le_32(0);
1953
1954         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1955
1956         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1957
1958         HWRM_CHECK_RESULT();
1959
1960         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1961
1962         HWRM_UNLOCK();
1963
1964         return rc;
1965 }
1966
1967 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1968 {
1969         int rc;
1970         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1971         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1972
1973         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1974                 return 0;
1975
1976         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1977
1978         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1979
1980         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1981
1982         HWRM_CHECK_RESULT();
1983         HWRM_UNLOCK();
1984
1985         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1986
1987         return rc;
1988 }
1989
1990 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1991 {
1992         int rc = 0, i, j;
1993         struct hwrm_vnic_alloc_input req = { 0 };
1994         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1995
1996         if (!BNXT_HAS_RING_GRPS(bp))
1997                 goto skip_ring_grps;
1998
1999         /* map ring groups to this vnic */
2000         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
2001                 vnic->start_grp_id, vnic->end_grp_id);
2002         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
2003                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
2004
2005         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
2006         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
2007         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
2008         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
2009
2010 skip_ring_grps:
2011         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
2012         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
2013
2014         if (vnic->func_default)
2015                 req.flags =
2016                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
2017         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2018
2019         HWRM_CHECK_RESULT();
2020
2021         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
2022         HWRM_UNLOCK();
2023         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2024         return rc;
2025 }
2026
2027 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
2028                                         struct bnxt_vnic_info *vnic,
2029                                         struct bnxt_plcmodes_cfg *pmode)
2030 {
2031         int rc = 0;
2032         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2033         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2034
2035         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2036
2037         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2038
2039         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2040
2041         HWRM_CHECK_RESULT();
2042
2043         pmode->flags = rte_le_to_cpu_32(resp->flags);
2044         /* dflt_vnic bit doesn't exist in the _cfg command */
2045         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2046         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2047         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2048         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2049
2050         HWRM_UNLOCK();
2051
2052         return rc;
2053 }
2054
2055 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2056                                        struct bnxt_vnic_info *vnic,
2057                                        struct bnxt_plcmodes_cfg *pmode)
2058 {
2059         int rc = 0;
2060         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2061         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2062
2063         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2064                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2065                 return rc;
2066         }
2067
2068         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2069
2070         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2071         req.flags = rte_cpu_to_le_32(pmode->flags);
2072         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2073         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2074         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2075         req.enables = rte_cpu_to_le_32(
2076             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2077             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2078             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2079         );
2080
2081         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2082
2083         HWRM_CHECK_RESULT();
2084         HWRM_UNLOCK();
2085
2086         return rc;
2087 }
2088
2089 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2090 {
2091         int rc = 0;
2092         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2093         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2094         struct bnxt_plcmodes_cfg pmodes = { 0 };
2095         uint32_t ctx_enable_flag = 0;
2096         uint32_t enables = 0;
2097
2098         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2099                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2100                 return rc;
2101         }
2102
2103         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2104         if (rc)
2105                 return rc;
2106
2107         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2108
2109         if (BNXT_CHIP_P5(bp)) {
2110                 int dflt_rxq = vnic->start_grp_id;
2111                 struct bnxt_rx_ring_info *rxr;
2112                 struct bnxt_cp_ring_info *cpr;
2113                 struct bnxt_rx_queue *rxq;
2114                 int i;
2115
2116                 /*
2117                  * The first active receive ring is used as the VNIC
2118                  * default receive ring. If there are no active receive
2119                  * rings (all corresponding receive queues are stopped),
2120                  * the first receive ring is used.
2121                  */
2122                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2123                         rxq = bp->eth_dev->data->rx_queues[i];
2124                         if (rxq->rx_started) {
2125                                 dflt_rxq = i;
2126                                 break;
2127                         }
2128                 }
2129
2130                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2131                 rxr = rxq->rx_ring;
2132                 cpr = rxq->cp_ring;
2133
2134                 req.default_rx_ring_id =
2135                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2136                 req.default_cmpl_ring_id =
2137                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2138                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2139                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2140                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2141                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2142                         req.rx_csum_v2_mode =
2143                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2144                 }
2145                 goto config_mru;
2146         }
2147
2148         /* Only RSS support for now TBD: COS & LB */
2149         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2150         if (vnic->lb_rule != 0xffff)
2151                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2152         if (vnic->cos_rule != 0xffff)
2153                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2154         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2155                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2156                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2157         }
2158         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2159                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2160                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2161         }
2162
2163         enables |= ctx_enable_flag;
2164         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2165         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2166         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2167         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2168
2169 config_mru:
2170         req.enables = rte_cpu_to_le_32(enables);
2171         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2172         req.mru = rte_cpu_to_le_16(vnic->mru);
2173         /* Configure default VNIC only once. */
2174         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2175                 req.flags |=
2176                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2177                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2178         }
2179         if (vnic->vlan_strip)
2180                 req.flags |=
2181                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2182         if (vnic->bd_stall)
2183                 req.flags |=
2184                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2185         if (vnic->rss_dflt_cr)
2186                 req.flags |= rte_cpu_to_le_32(
2187                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2188
2189         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2190
2191         HWRM_CHECK_RESULT();
2192         HWRM_UNLOCK();
2193
2194         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2195
2196         return rc;
2197 }
2198
2199 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2200                 int16_t fw_vf_id)
2201 {
2202         int rc = 0;
2203         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2204         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2205
2206         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2207                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2208                 return rc;
2209         }
2210         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2211
2212         req.enables =
2213                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2214         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2215         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2216
2217         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2218
2219         HWRM_CHECK_RESULT();
2220
2221         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2222         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2223         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2224         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2225         vnic->mru = rte_le_to_cpu_16(resp->mru);
2226         vnic->func_default = rte_le_to_cpu_32(
2227                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2228         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2229                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2230         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2231                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2232         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2233                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2234
2235         HWRM_UNLOCK();
2236
2237         return rc;
2238 }
2239
2240 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2241                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2242 {
2243         int rc = 0;
2244         uint16_t ctx_id;
2245         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2246         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2247                                                 bp->hwrm_cmd_resp_addr;
2248
2249         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2250
2251         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2252         HWRM_CHECK_RESULT();
2253
2254         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2255         if (!BNXT_HAS_RING_GRPS(bp))
2256                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2257         else if (ctx_idx == 0)
2258                 vnic->rss_rule = ctx_id;
2259
2260         HWRM_UNLOCK();
2261
2262         return rc;
2263 }
2264
2265 static
2266 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2267                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2268 {
2269         int rc = 0;
2270         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2271         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2272                                                 bp->hwrm_cmd_resp_addr;
2273
2274         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2275                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2276                 return rc;
2277         }
2278         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2279
2280         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2281
2282         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2283
2284         HWRM_CHECK_RESULT();
2285         HWRM_UNLOCK();
2286
2287         return rc;
2288 }
2289
2290 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2291 {
2292         int rc = 0;
2293
2294         if (BNXT_CHIP_P5(bp)) {
2295                 int j;
2296
2297                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2298                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2299                                                       vnic,
2300                                                       vnic->fw_grp_ids[j]);
2301                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2302                 }
2303                 vnic->num_lb_ctxts = 0;
2304         } else {
2305                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2306                 vnic->rss_rule = INVALID_HW_RING_ID;
2307         }
2308
2309         return rc;
2310 }
2311
2312 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2313 {
2314         int rc = 0;
2315         struct hwrm_vnic_free_input req = {.req_type = 0 };
2316         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2317
2318         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2319                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2320                 return rc;
2321         }
2322
2323         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2324
2325         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2326
2327         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2328
2329         HWRM_CHECK_RESULT();
2330         HWRM_UNLOCK();
2331
2332         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2333         /* Configure default VNIC again if necessary. */
2334         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2335                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2336
2337         return rc;
2338 }
2339
2340 static int
2341 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2342 {
2343         int i;
2344         int rc = 0;
2345         int nr_ctxs = vnic->num_lb_ctxts;
2346         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2347         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2348
2349         for (i = 0; i < nr_ctxs; i++) {
2350                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2351
2352                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2353                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2354                 req.hash_mode_flags = vnic->hash_mode;
2355
2356                 req.hash_key_tbl_addr =
2357                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2358
2359                 req.ring_grp_tbl_addr =
2360                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2361                                          i * HW_HASH_INDEX_SIZE);
2362                 req.ring_table_pair_index = i;
2363                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2364
2365                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2366                                             BNXT_USE_CHIMP_MB);
2367
2368                 HWRM_CHECK_RESULT();
2369                 HWRM_UNLOCK();
2370         }
2371
2372         return rc;
2373 }
2374
2375 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2376                            struct bnxt_vnic_info *vnic)
2377 {
2378         int rc = 0;
2379         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2380         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2381
2382         if (!vnic->rss_table)
2383                 return 0;
2384
2385         if (BNXT_CHIP_P5(bp))
2386                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2387
2388         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2389
2390         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2391         req.hash_mode_flags = vnic->hash_mode;
2392
2393         req.ring_grp_tbl_addr =
2394             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2395         req.hash_key_tbl_addr =
2396             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2397         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2398         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2399
2400         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2401
2402         HWRM_CHECK_RESULT();
2403         HWRM_UNLOCK();
2404
2405         return rc;
2406 }
2407
2408 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2409                         struct bnxt_vnic_info *vnic)
2410 {
2411         int rc = 0;
2412         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2413         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2414         uint16_t size;
2415
2416         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2417                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2418                 return rc;
2419         }
2420
2421         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2422
2423         req.flags = rte_cpu_to_le_32(
2424                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2425
2426         req.enables = rte_cpu_to_le_32(
2427                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2428
2429         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2430         size -= RTE_PKTMBUF_HEADROOM;
2431         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2432
2433         req.jumbo_thresh = rte_cpu_to_le_16(size);
2434         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2435
2436         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2437
2438         HWRM_CHECK_RESULT();
2439         HWRM_UNLOCK();
2440
2441         return rc;
2442 }
2443
2444 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2445                         struct bnxt_vnic_info *vnic, bool enable)
2446 {
2447         int rc = 0;
2448         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2449         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2450
2451         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2452                 if (enable)
2453                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2454                 return -ENOTSUP;
2455         }
2456
2457         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2458                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2459                 return 0;
2460         }
2461
2462         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2463
2464         if (enable) {
2465                 req.enables = rte_cpu_to_le_32(
2466                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2467                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2468                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2469                 req.flags = rte_cpu_to_le_32(
2470                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2471                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2472                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2473                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2474                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2475                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2476                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2477                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2478                 req.min_agg_len = rte_cpu_to_le_32(512);
2479         }
2480         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2481
2482         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2483
2484         HWRM_CHECK_RESULT();
2485         HWRM_UNLOCK();
2486
2487         return rc;
2488 }
2489
2490 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2491 {
2492         struct hwrm_func_cfg_input req = {0};
2493         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2494         int rc;
2495
2496         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2497         req.enables = rte_cpu_to_le_32(
2498                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2499         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2500         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2501
2502         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2503
2504         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2505         HWRM_CHECK_RESULT();
2506         HWRM_UNLOCK();
2507
2508         bp->pf->vf_info[vf].random_mac = false;
2509
2510         return rc;
2511 }
2512
2513 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2514                                   uint64_t *dropped)
2515 {
2516         int rc = 0;
2517         struct hwrm_func_qstats_input req = {.req_type = 0};
2518         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2519
2520         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2521
2522         req.fid = rte_cpu_to_le_16(fid);
2523
2524         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2525
2526         HWRM_CHECK_RESULT();
2527
2528         if (dropped)
2529                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2530
2531         HWRM_UNLOCK();
2532
2533         return rc;
2534 }
2535
2536 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2537                           struct rte_eth_stats *stats,
2538                           struct hwrm_func_qstats_output *func_qstats)
2539 {
2540         int rc = 0;
2541         struct hwrm_func_qstats_input req = {.req_type = 0};
2542         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2543
2544         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2545
2546         req.fid = rte_cpu_to_le_16(fid);
2547
2548         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2549
2550         HWRM_CHECK_RESULT();
2551         if (func_qstats)
2552                 memcpy(func_qstats, resp,
2553                        sizeof(struct hwrm_func_qstats_output));
2554
2555         if (!stats)
2556                 goto exit;
2557
2558         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2559         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2560         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2561         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2562         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2563         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2564
2565         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2566         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2567         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2568         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2569         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2570         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2571
2572         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2573         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2574         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2575
2576 exit:
2577         HWRM_UNLOCK();
2578
2579         return rc;
2580 }
2581
2582 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2583 {
2584         int rc = 0;
2585         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2586         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2587
2588         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2589
2590         req.fid = rte_cpu_to_le_16(fid);
2591
2592         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2593
2594         HWRM_CHECK_RESULT();
2595         HWRM_UNLOCK();
2596
2597         return rc;
2598 }
2599
2600 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2601 {
2602         unsigned int i;
2603         int rc = 0;
2604
2605         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2606                 struct bnxt_tx_queue *txq;
2607                 struct bnxt_rx_queue *rxq;
2608                 struct bnxt_cp_ring_info *cpr;
2609
2610                 if (i >= bp->rx_cp_nr_rings) {
2611                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2612                         cpr = txq->cp_ring;
2613                 } else {
2614                         rxq = bp->rx_queues[i];
2615                         cpr = rxq->cp_ring;
2616                 }
2617
2618                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2619                 if (rc)
2620                         return rc;
2621         }
2622         return 0;
2623 }
2624
2625 static int
2626 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2627 {
2628         int rc;
2629         unsigned int i;
2630         struct bnxt_cp_ring_info *cpr;
2631
2632         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2633
2634                 cpr = bp->rx_queues[i]->cp_ring;
2635                 if (BNXT_HAS_RING_GRPS(bp))
2636                         bp->grp_info[i].fw_stats_ctx = -1;
2637                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2638                 if (rc)
2639                         return rc;
2640         }
2641
2642         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2643                 cpr = bp->tx_queues[i]->cp_ring;
2644                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2645                 if (rc)
2646                         return rc;
2647         }
2648
2649         return 0;
2650 }
2651
2652 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2653 {
2654         struct bnxt_cp_ring_info *cpr;
2655         unsigned int i;
2656         int rc = 0;
2657
2658         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2659                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
2660
2661                 cpr = rxq->cp_ring;
2662                 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
2663                         rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2664                         if (rc)
2665                                 return rc;
2666                 }
2667         }
2668
2669         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2670                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2671
2672                 cpr = txq->cp_ring;
2673                 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
2674                         rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2675                         if (rc)
2676                                 return rc;
2677                 }
2678         }
2679
2680         return rc;
2681 }
2682
2683 static int
2684 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2685 {
2686         uint16_t idx;
2687         uint32_t rc = 0;
2688
2689         if (!BNXT_HAS_RING_GRPS(bp))
2690                 return 0;
2691
2692         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2693
2694                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2695                         continue;
2696
2697                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2698
2699                 if (rc)
2700                         return rc;
2701         }
2702         return rc;
2703 }
2704
2705 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2706 {
2707         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2708
2709         bnxt_hwrm_ring_free(bp, cp_ring,
2710                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2711                             INVALID_HW_RING_ID);
2712         memset(cpr->cp_desc_ring, 0,
2713                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2714         cpr->cp_raw_cons = 0;
2715 }
2716
2717 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2718 {
2719         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2720
2721         bnxt_hwrm_ring_free(bp, cp_ring,
2722                             HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2723                             INVALID_HW_RING_ID);
2724         memset(cpr->cp_desc_ring, 0,
2725                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2726         cpr->cp_raw_cons = 0;
2727 }
2728
2729 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2730 {
2731         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2732         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2733         struct bnxt_ring *ring = rxr->rx_ring_struct;
2734         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2735
2736         if (BNXT_HAS_RING_GRPS(bp))
2737                 bnxt_hwrm_ring_grp_free(bp, queue_index);
2738
2739         bnxt_hwrm_ring_free(bp, ring,
2740                             HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2741                             cpr->cp_ring_struct->fw_ring_id);
2742         if (BNXT_HAS_RING_GRPS(bp))
2743                 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2744
2745         ring = rxr->ag_ring_struct;
2746         bnxt_hwrm_ring_free(bp, ring,
2747                             BNXT_CHIP_P5(bp) ?
2748                             HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2749                             HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2750                             cpr->cp_ring_struct->fw_ring_id);
2751         if (BNXT_HAS_RING_GRPS(bp))
2752                 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2753
2754         bnxt_hwrm_stat_ctx_free(bp, cpr);
2755
2756         bnxt_free_cp_ring(bp, cpr);
2757
2758         if (BNXT_HAS_RING_GRPS(bp))
2759                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2760 }
2761
2762 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2763 {
2764         int rc;
2765         struct hwrm_ring_reset_input req = {.req_type = 0 };
2766         struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2767
2768         HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2769
2770         req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2771         req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2772         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2773
2774         HWRM_CHECK_RESULT();
2775
2776         HWRM_UNLOCK();
2777
2778         return rc;
2779 }
2780
2781 static int
2782 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2783 {
2784         unsigned int i;
2785
2786         for (i = 0; i < bp->tx_cp_nr_rings; i++)
2787                 bnxt_free_hwrm_tx_ring(bp, i);
2788
2789         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2790                 bnxt_free_hwrm_rx_ring(bp, i);
2791
2792         return 0;
2793 }
2794
2795 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2796 {
2797         uint16_t i;
2798         uint32_t rc = 0;
2799
2800         if (!BNXT_HAS_RING_GRPS(bp))
2801                 return 0;
2802
2803         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2804                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2805                 if (rc)
2806                         return rc;
2807         }
2808         return rc;
2809 }
2810
2811 /*
2812  * HWRM utility functions
2813  */
2814
2815 void bnxt_free_hwrm_resources(struct bnxt *bp)
2816 {
2817         /* Release memzone */
2818         rte_free(bp->hwrm_cmd_resp_addr);
2819         rte_free(bp->hwrm_short_cmd_req_addr);
2820         bp->hwrm_cmd_resp_addr = NULL;
2821         bp->hwrm_short_cmd_req_addr = NULL;
2822         bp->hwrm_cmd_resp_dma_addr = 0;
2823         bp->hwrm_short_cmd_req_dma_addr = 0;
2824 }
2825
2826 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2827 {
2828         struct rte_pci_device *pdev = bp->pdev;
2829         char type[RTE_MEMZONE_NAMESIZE];
2830
2831         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2832                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2833         bp->max_resp_len = BNXT_PAGE_SIZE;
2834         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2835         if (bp->hwrm_cmd_resp_addr == NULL)
2836                 return -ENOMEM;
2837         bp->hwrm_cmd_resp_dma_addr =
2838                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2839         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2840                 PMD_DRV_LOG(ERR,
2841                         "unable to map response address to physical memory\n");
2842                 return -ENOMEM;
2843         }
2844         rte_spinlock_init(&bp->hwrm_lock);
2845
2846         return 0;
2847 }
2848
2849 int
2850 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2851 {
2852         int rc = 0;
2853
2854         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2855                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2856                 if (rc)
2857                         return rc;
2858         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2859                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2860                 if (rc)
2861                         return rc;
2862         }
2863
2864         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2865         return rc;
2866 }
2867
2868 static int
2869 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2870 {
2871         struct bnxt_filter_info *filter;
2872         int rc = 0;
2873
2874         STAILQ_FOREACH(filter, &vnic->filter, next) {
2875                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2876                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2877                 bnxt_free_filter(bp, filter);
2878         }
2879         return rc;
2880 }
2881
2882 static int
2883 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2884 {
2885         struct bnxt_filter_info *filter;
2886         struct rte_flow *flow;
2887         int rc = 0;
2888
2889         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2890                 flow = STAILQ_FIRST(&vnic->flow_list);
2891                 filter = flow->filter;
2892                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2893                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2894
2895                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2896                 rte_free(flow);
2897         }
2898         return rc;
2899 }
2900
2901 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2902 {
2903         struct bnxt_filter_info *filter;
2904         int rc = 0;
2905
2906         STAILQ_FOREACH(filter, &vnic->filter, next) {
2907                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2908                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2909                                                      filter);
2910                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2911                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2912                                                          filter);
2913                 else
2914                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2915                                                      filter);
2916                 if (rc)
2917                         break;
2918         }
2919         return rc;
2920 }
2921
2922 static void
2923 bnxt_free_tunnel_ports(struct bnxt *bp)
2924 {
2925         if (bp->vxlan_port_cnt)
2926                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2927                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2928
2929         if (bp->geneve_port_cnt)
2930                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2931                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2932 }
2933
2934 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2935 {
2936         int i;
2937
2938         if (bp->vnic_info == NULL)
2939                 return;
2940
2941         /*
2942          * Cleanup VNICs in reverse order, to make sure the L2 filter
2943          * from vnic0 is last to be cleaned up.
2944          */
2945         for (i = bp->max_vnics - 1; i >= 0; i--) {
2946                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2947
2948                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2949                         continue;
2950
2951                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2952
2953                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2954
2955                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2956
2957                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2958
2959                 bnxt_hwrm_vnic_free(bp, vnic);
2960
2961                 rte_free(vnic->fw_grp_ids);
2962         }
2963         /* Ring resources */
2964         bnxt_free_all_hwrm_rings(bp);
2965         bnxt_free_all_hwrm_ring_grps(bp);
2966         bnxt_free_all_hwrm_stat_ctxs(bp);
2967         bnxt_free_tunnel_ports(bp);
2968 }
2969
2970 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2971 {
2972         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2973
2974         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2975                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2976
2977         switch (conf_link_speed) {
2978         case ETH_LINK_SPEED_10M_HD:
2979         case ETH_LINK_SPEED_100M_HD:
2980                 /* FALLTHROUGH */
2981                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2982         }
2983         return hw_link_duplex;
2984 }
2985
2986 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2987 {
2988         return !conf_link;
2989 }
2990
2991 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2992                                           uint16_t pam4_link)
2993 {
2994         uint16_t eth_link_speed = 0;
2995
2996         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2997                 return ETH_LINK_SPEED_AUTONEG;
2998
2999         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
3000         case ETH_LINK_SPEED_100M:
3001         case ETH_LINK_SPEED_100M_HD:
3002                 /* FALLTHROUGH */
3003                 eth_link_speed =
3004                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
3005                 break;
3006         case ETH_LINK_SPEED_1G:
3007                 eth_link_speed =
3008                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
3009                 break;
3010         case ETH_LINK_SPEED_2_5G:
3011                 eth_link_speed =
3012                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
3013                 break;
3014         case ETH_LINK_SPEED_10G:
3015                 eth_link_speed =
3016                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
3017                 break;
3018         case ETH_LINK_SPEED_20G:
3019                 eth_link_speed =
3020                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3021                 break;
3022         case ETH_LINK_SPEED_25G:
3023                 eth_link_speed =
3024                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3025                 break;
3026         case ETH_LINK_SPEED_40G:
3027                 eth_link_speed =
3028                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3029                 break;
3030         case ETH_LINK_SPEED_50G:
3031                 eth_link_speed = pam4_link ?
3032                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3033                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3034                 break;
3035         case ETH_LINK_SPEED_100G:
3036                 eth_link_speed = pam4_link ?
3037                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3038                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3039                 break;
3040         case ETH_LINK_SPEED_200G:
3041                 eth_link_speed =
3042                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3043                 break;
3044         default:
3045                 PMD_DRV_LOG(ERR,
3046                         "Unsupported link speed %d; default to AUTO\n",
3047                         conf_link_speed);
3048                 break;
3049         }
3050         return eth_link_speed;
3051 }
3052
3053 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3054                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3055                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3056                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3057                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3058
3059 static int bnxt_validate_link_speed(struct bnxt *bp)
3060 {
3061         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3062         uint16_t port_id = bp->eth_dev->data->port_id;
3063         uint32_t link_speed_capa;
3064         uint32_t one_speed;
3065
3066         if (link_speed == ETH_LINK_SPEED_AUTONEG)
3067                 return 0;
3068
3069         link_speed_capa = bnxt_get_speed_capabilities(bp);
3070
3071         if (link_speed & ETH_LINK_SPEED_FIXED) {
3072                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3073
3074                 if (one_speed & (one_speed - 1)) {
3075                         PMD_DRV_LOG(ERR,
3076                                 "Invalid advertised speeds (%u) for port %u\n",
3077                                 link_speed, port_id);
3078                         return -EINVAL;
3079                 }
3080                 if ((one_speed & link_speed_capa) != one_speed) {
3081                         PMD_DRV_LOG(ERR,
3082                                 "Unsupported advertised speed (%u) for port %u\n",
3083                                 link_speed, port_id);
3084                         return -EINVAL;
3085                 }
3086         } else {
3087                 if (!(link_speed & link_speed_capa)) {
3088                         PMD_DRV_LOG(ERR,
3089                                 "Unsupported advertised speeds (%u) for port %u\n",
3090                                 link_speed, port_id);
3091                         return -EINVAL;
3092                 }
3093         }
3094         return 0;
3095 }
3096
3097 static uint16_t
3098 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3099 {
3100         uint16_t ret = 0;
3101
3102         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3103                 if (bp->link_info->support_speeds)
3104                         return bp->link_info->support_speeds;
3105                 link_speed = BNXT_SUPPORTED_SPEEDS;
3106         }
3107
3108         if (link_speed & ETH_LINK_SPEED_100M)
3109                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3110         if (link_speed & ETH_LINK_SPEED_100M_HD)
3111                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3112         if (link_speed & ETH_LINK_SPEED_1G)
3113                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3114         if (link_speed & ETH_LINK_SPEED_2_5G)
3115                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3116         if (link_speed & ETH_LINK_SPEED_10G)
3117                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3118         if (link_speed & ETH_LINK_SPEED_20G)
3119                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3120         if (link_speed & ETH_LINK_SPEED_25G)
3121                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3122         if (link_speed & ETH_LINK_SPEED_40G)
3123                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3124         if (link_speed & ETH_LINK_SPEED_50G)
3125                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3126         if (link_speed & ETH_LINK_SPEED_100G)
3127                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3128         if (link_speed & ETH_LINK_SPEED_200G)
3129                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3130         return ret;
3131 }
3132
3133 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3134 {
3135         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3136
3137         switch (hw_link_speed) {
3138         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3139                 eth_link_speed = ETH_SPEED_NUM_100M;
3140                 break;
3141         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3142                 eth_link_speed = ETH_SPEED_NUM_1G;
3143                 break;
3144         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3145                 eth_link_speed = ETH_SPEED_NUM_2_5G;
3146                 break;
3147         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3148                 eth_link_speed = ETH_SPEED_NUM_10G;
3149                 break;
3150         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3151                 eth_link_speed = ETH_SPEED_NUM_20G;
3152                 break;
3153         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3154                 eth_link_speed = ETH_SPEED_NUM_25G;
3155                 break;
3156         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3157                 eth_link_speed = ETH_SPEED_NUM_40G;
3158                 break;
3159         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3160                 eth_link_speed = ETH_SPEED_NUM_50G;
3161                 break;
3162         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3163                 eth_link_speed = ETH_SPEED_NUM_100G;
3164                 break;
3165         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3166                 eth_link_speed = ETH_SPEED_NUM_200G;
3167                 break;
3168         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3169         default:
3170                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3171                         hw_link_speed);
3172                 break;
3173         }
3174         return eth_link_speed;
3175 }
3176
3177 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3178 {
3179         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3180
3181         switch (hw_link_duplex) {
3182         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3183         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3184                 /* FALLTHROUGH */
3185                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3186                 break;
3187         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3188                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3189                 break;
3190         default:
3191                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3192                         hw_link_duplex);
3193                 break;
3194         }
3195         return eth_link_duplex;
3196 }
3197
3198 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3199 {
3200         int rc = 0;
3201         struct bnxt_link_info *link_info = bp->link_info;
3202
3203         rc = bnxt_hwrm_port_phy_qcaps(bp);
3204         if (rc)
3205                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3206
3207         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3208         if (rc) {
3209                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3210                 goto exit;
3211         }
3212
3213         if (link_info->link_speed)
3214                 link->link_speed =
3215                         bnxt_parse_hw_link_speed(link_info->link_speed);
3216         else
3217                 link->link_speed = ETH_SPEED_NUM_NONE;
3218         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3219         link->link_status = link_info->link_up;
3220         link->link_autoneg = link_info->auto_mode ==
3221                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3222                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3223 exit:
3224         return rc;
3225 }
3226
3227 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3228 {
3229         int rc = 0;
3230         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3231         struct bnxt_link_info link_req;
3232         uint16_t speed, autoneg;
3233
3234         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3235                 return 0;
3236
3237         rc = bnxt_validate_link_speed(bp);
3238         if (rc)
3239                 goto error;
3240
3241         memset(&link_req, 0, sizeof(link_req));
3242         link_req.link_up = link_up;
3243         if (!link_up)
3244                 goto port_phy_cfg;
3245
3246         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3247         if (BNXT_CHIP_P5(bp) &&
3248             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3249                 /* 40G is not supported as part of media auto detect.
3250                  * The speed should be forced and autoneg disabled
3251                  * to configure 40G speed.
3252                  */
3253                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3254                 autoneg = 0;
3255         }
3256
3257         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3258         if (bp->link_info->auto_link_speed == 0 &&
3259             bp->link_info->link_signal_mode &&
3260             bp->link_info->auto_pam4_link_speeds == 0)
3261                 autoneg = 0;
3262
3263         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3264                                           bp->link_info->link_signal_mode);
3265         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3266         /* Autoneg can be done only when the FW allows. */
3267         if (autoneg == 1 && bp->link_info->support_auto_speeds) {
3268                 link_req.phy_flags |=
3269                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3270                 link_req.auto_link_speed_mask =
3271                         bnxt_parse_eth_link_speed_mask(bp,
3272                                                        dev_conf->link_speeds);
3273         } else {
3274                 if (bp->link_info->phy_type ==
3275                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3276                     bp->link_info->phy_type ==
3277                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3278                     bp->link_info->media_type ==
3279                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3280                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3281                         return -EINVAL;
3282                 }
3283
3284                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3285                 /* If user wants a particular speed try that first. */
3286                 if (speed)
3287                         link_req.link_speed = speed;
3288                 else if (bp->link_info->force_pam4_link_speed)
3289                         link_req.link_speed =
3290                                 bp->link_info->force_pam4_link_speed;
3291                 else if (bp->link_info->auto_pam4_link_speeds)
3292                         link_req.link_speed =
3293                                 bp->link_info->auto_pam4_link_speeds;
3294                 else if (bp->link_info->support_pam4_speeds)
3295                         link_req.link_speed =
3296                                 bp->link_info->support_pam4_speeds;
3297                 else if (bp->link_info->force_link_speed)
3298                         link_req.link_speed = bp->link_info->force_link_speed;
3299                 else
3300                         link_req.link_speed = bp->link_info->auto_link_speed;
3301                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3302                  * zero. Use the auto_link_speed.
3303                  */
3304                 if (bp->link_info->auto_link_speed != 0 &&
3305                     bp->link_info->auto_pam4_link_speeds == 0)
3306                         link_req.link_speed = bp->link_info->auto_link_speed;
3307         }
3308         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3309         link_req.auto_pause = bp->link_info->auto_pause;
3310         link_req.force_pause = bp->link_info->force_pause;
3311
3312 port_phy_cfg:
3313         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3314         if (rc) {
3315                 PMD_DRV_LOG(ERR,
3316                         "Set link config failed with rc %d\n", rc);
3317         }
3318
3319 error:
3320         return rc;
3321 }
3322
3323 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3324 {
3325         struct hwrm_func_qcfg_input req = {0};
3326         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3327         uint16_t flags;
3328         int rc = 0;
3329         bp->func_svif = BNXT_SVIF_INVALID;
3330         uint16_t svif_info;
3331
3332         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3333         req.fid = rte_cpu_to_le_16(0xffff);
3334
3335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3336
3337         HWRM_CHECK_RESULT();
3338
3339         bp->vlan = rte_le_to_cpu_16(resp->vlan) & ETH_VLAN_ID_MAX;
3340
3341         svif_info = rte_le_to_cpu_16(resp->svif_info);
3342         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3343                 bp->func_svif = svif_info &
3344                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3345
3346         flags = rte_le_to_cpu_16(resp->flags);
3347         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3348                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3349
3350         if (BNXT_VF(bp) &&
3351             !BNXT_VF_IS_TRUSTED(bp) &&
3352             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3353                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3354                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3355         } else if (BNXT_VF(bp) &&
3356                    BNXT_VF_IS_TRUSTED(bp) &&
3357                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3358                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3359                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3360         }
3361
3362         if (mtu)
3363                 *mtu = rte_le_to_cpu_16(resp->admin_mtu);
3364
3365         switch (resp->port_partition_type) {
3366         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3367         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3368         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3369                 /* FALLTHROUGH */
3370                 bp->flags |= BNXT_FLAG_NPAR_PF;
3371                 break;
3372         default:
3373                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3374                 break;
3375         }
3376
3377         bp->legacy_db_size =
3378                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3379
3380         HWRM_UNLOCK();
3381
3382         return rc;
3383 }
3384
3385 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3386 {
3387         struct hwrm_func_qcfg_input req = {0};
3388         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3389         int rc;
3390
3391         if (!BNXT_VF_IS_TRUSTED(bp))
3392                 return 0;
3393
3394         if (!bp->parent)
3395                 return -EINVAL;
3396
3397         bp->parent->fid = BNXT_PF_FID_INVALID;
3398
3399         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3400
3401         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3402
3403         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3404
3405         HWRM_CHECK_RESULT_SILENT();
3406
3407         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3408         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3409         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3410         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3411
3412         HWRM_UNLOCK();
3413
3414         return 0;
3415 }
3416
3417 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3418                                  uint16_t *vnic_id, uint16_t *svif)
3419 {
3420         struct hwrm_func_qcfg_input req = {0};
3421         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3422         uint16_t svif_info;
3423         int rc = 0;
3424
3425         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3426         req.fid = rte_cpu_to_le_16(fid);
3427
3428         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3429
3430         HWRM_CHECK_RESULT();
3431
3432         if (vnic_id)
3433                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3434
3435         svif_info = rte_le_to_cpu_16(resp->svif_info);
3436         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3437                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3438
3439         HWRM_UNLOCK();
3440
3441         return rc;
3442 }
3443
3444 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3445 {
3446         struct hwrm_port_mac_qcfg_input req = {0};
3447         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3448         uint16_t port_svif_info;
3449         int rc;
3450
3451         bp->port_svif = BNXT_SVIF_INVALID;
3452
3453         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3454                 return 0;
3455
3456         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3457
3458         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3459
3460         HWRM_CHECK_RESULT_SILENT();
3461
3462         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3463         if (port_svif_info &
3464             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3465                 bp->port_svif = port_svif_info &
3466                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3467
3468         HWRM_UNLOCK();
3469
3470         return 0;
3471 }
3472
3473 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3474                                  struct bnxt_pf_resource_info *pf_resc)
3475 {
3476         struct hwrm_func_cfg_input req = {0};
3477         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3478         uint32_t enables;
3479         int rc;
3480
3481         enables = HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3482                   HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU |
3483                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3484                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3485                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3486                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3487                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3488                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3489                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3490                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3491
3492         if (BNXT_HAS_RING_GRPS(bp)) {
3493                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3494                 req.num_hw_ring_grps =
3495                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3496         } else if (BNXT_HAS_NQ(bp)) {
3497                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3498                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3499         }
3500
3501         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3502         req.admin_mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3503         req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
3504         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3505         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3506         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3507         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3508         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3509         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3510         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3511         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3512         req.fid = rte_cpu_to_le_16(0xffff);
3513         req.enables = rte_cpu_to_le_32(enables);
3514
3515         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3516
3517         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3518
3519         HWRM_CHECK_RESULT();
3520         HWRM_UNLOCK();
3521
3522         return rc;
3523 }
3524
3525 /* min values are the guaranteed resources and max values are subject
3526  * to availability. The strategy for now is to keep both min & max
3527  * values the same.
3528  */
3529 static void
3530 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3531                               struct hwrm_func_vf_resource_cfg_input *req,
3532                               int num_vfs)
3533 {
3534         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3535                                                (num_vfs + 1));
3536         req->min_rsscos_ctx = req->max_rsscos_ctx;
3537         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3538         req->min_stat_ctx = req->max_stat_ctx;
3539         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3540                                                (num_vfs + 1));
3541         req->min_cmpl_rings = req->max_cmpl_rings;
3542         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3543         req->min_tx_rings = req->max_tx_rings;
3544         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3545         req->min_rx_rings = req->max_rx_rings;
3546         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3547         req->min_l2_ctxs = req->max_l2_ctxs;
3548         /* TODO: For now, do not support VMDq/RFS on VFs. */
3549         req->max_vnics = rte_cpu_to_le_16(1);
3550         req->min_vnics = req->max_vnics;
3551         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3552                                                  (num_vfs + 1));
3553         req->min_hw_ring_grps = req->max_hw_ring_grps;
3554         req->flags =
3555          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3556 }
3557
3558 static void
3559 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3560                               struct hwrm_func_cfg_input *req,
3561                               int num_vfs)
3562 {
3563         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3564                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3565                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3566                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3567                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3568                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3569                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3570                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3571                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3572                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3573
3574         req->admin_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3575                                           RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3576                                           BNXT_NUM_VLANS);
3577         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3578         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3579                                                 (num_vfs + 1));
3580         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3581         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3582                                                (num_vfs + 1));
3583         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3584         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3585         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3586         /* TODO: For now, do not support VMDq/RFS on VFs. */
3587         req->num_vnics = rte_cpu_to_le_16(1);
3588         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3589                                                  (num_vfs + 1));
3590 }
3591
3592 /* Update the port wide resource values based on how many resources
3593  * got allocated to the VF.
3594  */
3595 static int bnxt_update_max_resources(struct bnxt *bp,
3596                                      int vf)
3597 {
3598         struct hwrm_func_qcfg_input req = {0};
3599         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3600         int rc;
3601
3602         /* Get the actual allocated values now */
3603         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3604         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3605         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3606         HWRM_CHECK_RESULT();
3607
3608         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3609         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3610         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3611         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3612         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3613         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3614         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3615
3616         HWRM_UNLOCK();
3617
3618         return 0;
3619 }
3620
3621 /* Update the PF resource values based on how many resources
3622  * got allocated to it.
3623  */
3624 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3625 {
3626         struct hwrm_func_qcfg_input req = {0};
3627         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3628         int rc;
3629
3630         /* Get the actual allocated values now */
3631         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3632         req.fid = rte_cpu_to_le_16(0xffff);
3633         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3634         HWRM_CHECK_RESULT();
3635
3636         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3637         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3638         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3639         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3640         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3641         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3642         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3643         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3644
3645         HWRM_UNLOCK();
3646
3647         return 0;
3648 }
3649
3650 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3651 {
3652         struct hwrm_func_qcfg_input req = {0};
3653         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3654         int rc;
3655
3656         /* Check for zero MAC address */
3657         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3658         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3659         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3660         HWRM_CHECK_RESULT();
3661         rc = rte_le_to_cpu_16(resp->vlan);
3662
3663         HWRM_UNLOCK();
3664
3665         return rc;
3666 }
3667
3668 static int bnxt_query_pf_resources(struct bnxt *bp,
3669                                    struct bnxt_pf_resource_info *pf_resc)
3670 {
3671         struct hwrm_func_qcfg_input req = {0};
3672         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3673         int rc;
3674
3675         /* And copy the allocated numbers into the pf struct */
3676         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3677         req.fid = rte_cpu_to_le_16(0xffff);
3678         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3679         HWRM_CHECK_RESULT();
3680
3681         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3682         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3683         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3684         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3685         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3686         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3687         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3688         bp->pf->evb_mode = resp->evb_mode;
3689
3690         HWRM_UNLOCK();
3691
3692         return rc;
3693 }
3694
3695 static void
3696 bnxt_calculate_pf_resources(struct bnxt *bp,
3697                             struct bnxt_pf_resource_info *pf_resc,
3698                             int num_vfs)
3699 {
3700         if (!num_vfs) {
3701                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3702                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3703                 pf_resc->num_cp_rings = bp->max_cp_rings;
3704                 pf_resc->num_tx_rings = bp->max_tx_rings;
3705                 pf_resc->num_rx_rings = bp->max_rx_rings;
3706                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3707                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3708
3709                 return;
3710         }
3711
3712         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3713                                    bp->max_rsscos_ctx % (num_vfs + 1);
3714         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3715                                  bp->max_stat_ctx % (num_vfs + 1);
3716         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3717                                 bp->max_cp_rings % (num_vfs + 1);
3718         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3719                                 bp->max_tx_rings % (num_vfs + 1);
3720         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3721                                 bp->max_rx_rings % (num_vfs + 1);
3722         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3723                                bp->max_l2_ctx % (num_vfs + 1);
3724         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3725                                     bp->max_ring_grps % (num_vfs + 1);
3726 }
3727
3728 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3729 {
3730         struct bnxt_pf_resource_info pf_resc = { 0 };
3731         int rc;
3732
3733         if (!BNXT_PF(bp)) {
3734                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3735                 return -EINVAL;
3736         }
3737
3738         rc = bnxt_hwrm_func_qcaps(bp);
3739         if (rc)
3740                 return rc;
3741
3742         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3743
3744         bp->pf->func_cfg_flags &=
3745                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3746                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3747         bp->pf->func_cfg_flags |=
3748                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3749
3750         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3751         if (rc)
3752                 return rc;
3753
3754         rc = bnxt_update_max_resources_pf_only(bp);
3755
3756         return rc;
3757 }
3758
3759 static int
3760 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3761 {
3762         size_t req_buf_sz, sz;
3763         int i, rc;
3764
3765         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3766         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3767                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3768         if (bp->pf->vf_req_buf == NULL) {
3769                 return -ENOMEM;
3770         }
3771
3772         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3773                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3774
3775         for (i = 0; i < num_vfs; i++)
3776                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3777                                              (i * HWRM_MAX_REQ_LEN);
3778
3779         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3780         if (rc)
3781                 rte_free(bp->pf->vf_req_buf);
3782
3783         return rc;
3784 }
3785
3786 static int
3787 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3788 {
3789         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3790         struct hwrm_func_vf_resource_cfg_input req = {0};
3791         int i, rc = 0;
3792
3793         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3794         bp->pf->active_vfs = 0;
3795         for (i = 0; i < num_vfs; i++) {
3796                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3797                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3798                 rc = bnxt_hwrm_send_message(bp,
3799                                             &req,
3800                                             sizeof(req),
3801                                             BNXT_USE_CHIMP_MB);
3802                 if (rc || resp->error_code) {
3803                         PMD_DRV_LOG(ERR,
3804                                 "Failed to initialize VF %d\n", i);
3805                         PMD_DRV_LOG(ERR,
3806                                 "Not all VFs available. (%d, %d)\n",
3807                                 rc, resp->error_code);
3808                         HWRM_UNLOCK();
3809
3810                         /* If the first VF configuration itself fails,
3811                          * unregister the vf_fwd_request buffer.
3812                          */
3813                         if (i == 0)
3814                                 bnxt_hwrm_func_buf_unrgtr(bp);
3815                         break;
3816                 }
3817                 HWRM_UNLOCK();
3818
3819                 /* Update the max resource values based on the resource values
3820                  * allocated to the VF.
3821                  */
3822                 bnxt_update_max_resources(bp, i);
3823                 bp->pf->active_vfs++;
3824                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3825         }
3826
3827         return 0;
3828 }
3829
3830 static int
3831 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3832 {
3833         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3834         struct hwrm_func_cfg_input req = {0};
3835         int i, rc;
3836
3837         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3838
3839         bp->pf->active_vfs = 0;
3840         for (i = 0; i < num_vfs; i++) {
3841                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3842                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3843                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3844                 rc = bnxt_hwrm_send_message(bp,
3845                                             &req,
3846                                             sizeof(req),
3847                                             BNXT_USE_CHIMP_MB);
3848
3849                 /* Clear enable flag for next pass */
3850                 req.enables &= ~rte_cpu_to_le_32(
3851                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3852
3853                 if (rc || resp->error_code) {
3854                         PMD_DRV_LOG(ERR,
3855                                 "Failed to initialize VF %d\n", i);
3856                         PMD_DRV_LOG(ERR,
3857                                 "Not all VFs available. (%d, %d)\n",
3858                                 rc, resp->error_code);
3859                         HWRM_UNLOCK();
3860
3861                         /* If the first VF configuration itself fails,
3862                          * unregister the vf_fwd_request buffer.
3863                          */
3864                         if (i == 0)
3865                                 bnxt_hwrm_func_buf_unrgtr(bp);
3866                         break;
3867                 }
3868
3869                 HWRM_UNLOCK();
3870
3871                 /* Update the max resource values based on the resource values
3872                  * allocated to the VF.
3873                  */
3874                 bnxt_update_max_resources(bp, i);
3875                 bp->pf->active_vfs++;
3876                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3877         }
3878
3879         return 0;
3880 }
3881
3882 static void
3883 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3884 {
3885         if (bp->flags & BNXT_FLAG_NEW_RM)
3886                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3887         else
3888                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3889 }
3890
3891 static void
3892 bnxt_update_pf_resources(struct bnxt *bp,
3893                          struct bnxt_pf_resource_info *pf_resc)
3894 {
3895         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3896         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3897         bp->max_cp_rings = pf_resc->num_cp_rings;
3898         bp->max_tx_rings = pf_resc->num_tx_rings;
3899         bp->max_rx_rings = pf_resc->num_rx_rings;
3900         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3901 }
3902
3903 static int32_t
3904 bnxt_configure_pf_resources(struct bnxt *bp,
3905                             struct bnxt_pf_resource_info *pf_resc)
3906 {
3907         /*
3908          * We're using STD_TX_RING_MODE here which will limit the TX
3909          * rings. This will allow QoS to function properly. Not setting this
3910          * will cause PF rings to break bandwidth settings.
3911          */
3912         bp->pf->func_cfg_flags &=
3913                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3914                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3915         bp->pf->func_cfg_flags |=
3916                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3917         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3918 }
3919
3920 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3921 {
3922         struct bnxt_pf_resource_info pf_resc = { 0 };
3923         int rc;
3924
3925         if (!BNXT_PF(bp)) {
3926                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3927                 return -EINVAL;
3928         }
3929
3930         rc = bnxt_hwrm_func_qcaps(bp);
3931         if (rc)
3932                 return rc;
3933
3934         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3935
3936         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3937         if (rc)
3938                 return rc;
3939
3940         rc = bnxt_query_pf_resources(bp, &pf_resc);
3941         if (rc)
3942                 return rc;
3943
3944         /*
3945          * Now, create and register a buffer to hold forwarded VF requests
3946          */
3947         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3948         if (rc)
3949                 return rc;
3950
3951         bnxt_configure_vf_resources(bp, num_vfs);
3952
3953         bnxt_update_pf_resources(bp, &pf_resc);
3954
3955         return 0;
3956 }
3957
3958 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3959 {
3960         struct hwrm_func_cfg_input req = {0};
3961         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3962         int rc;
3963
3964         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3965
3966         req.fid = rte_cpu_to_le_16(0xffff);
3967         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3968         req.evb_mode = bp->pf->evb_mode;
3969
3970         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3971         HWRM_CHECK_RESULT();
3972         HWRM_UNLOCK();
3973
3974         return rc;
3975 }
3976
3977 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3978                                 uint8_t tunnel_type)
3979 {
3980         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3981         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3982         int rc = 0;
3983
3984         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3985         req.tunnel_type = tunnel_type;
3986         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3987         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3988         HWRM_CHECK_RESULT();
3989
3990         switch (tunnel_type) {
3991         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3992                 bp->vxlan_fw_dst_port_id =
3993                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3994                 bp->vxlan_port = port;
3995                 break;
3996         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3997                 bp->geneve_fw_dst_port_id =
3998                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3999                 bp->geneve_port = port;
4000                 break;
4001         default:
4002                 break;
4003         }
4004
4005         HWRM_UNLOCK();
4006
4007         return rc;
4008 }
4009
4010 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4011                                 uint8_t tunnel_type)
4012 {
4013         struct hwrm_tunnel_dst_port_free_input req = {0};
4014         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4015         int rc = 0;
4016
4017         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4018
4019         req.tunnel_type = tunnel_type;
4020         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4021         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4022
4023         HWRM_CHECK_RESULT();
4024         HWRM_UNLOCK();
4025
4026         if (tunnel_type ==
4027             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4028                 bp->vxlan_port = 0;
4029                 bp->vxlan_port_cnt = 0;
4030         }
4031
4032         if (tunnel_type ==
4033             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4034                 bp->geneve_port = 0;
4035                 bp->geneve_port_cnt = 0;
4036         }
4037
4038         return rc;
4039 }
4040
4041 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4042                                         uint32_t flags)
4043 {
4044         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4045         struct hwrm_func_cfg_input req = {0};
4046         int rc;
4047
4048         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4049
4050         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4051         req.flags = rte_cpu_to_le_32(flags);
4052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4053
4054         HWRM_CHECK_RESULT();
4055         HWRM_UNLOCK();
4056
4057         return rc;
4058 }
4059
4060 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4061 {
4062         uint32_t *flag = flagp;
4063
4064         vnic->flags = *flag;
4065 }
4066
4067 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4068 {
4069         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4070 }
4071
4072 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4073 {
4074         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4075         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4076         int rc;
4077
4078         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4079
4080         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4081         req.req_buf_page_size =
4082                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4083         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4084         req.req_buf_page_addr0 =
4085                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4086         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4087                 PMD_DRV_LOG(ERR,
4088                         "unable to map buffer address to physical memory\n");
4089                 HWRM_UNLOCK();
4090                 return -ENOMEM;
4091         }
4092
4093         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4094
4095         HWRM_CHECK_RESULT();
4096         HWRM_UNLOCK();
4097
4098         return rc;
4099 }
4100
4101 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4102 {
4103         int rc = 0;
4104         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4105         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4106
4107         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4108                 return 0;
4109
4110         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4111
4112         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4113
4114         HWRM_CHECK_RESULT();
4115         HWRM_UNLOCK();
4116
4117         return rc;
4118 }
4119
4120 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4121 {
4122         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4123         struct hwrm_func_cfg_input req = {0};
4124         int rc;
4125
4126         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4127
4128         req.fid = rte_cpu_to_le_16(0xffff);
4129         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4130         req.enables = rte_cpu_to_le_32(
4131                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4132         req.async_event_cr = rte_cpu_to_le_16(
4133                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4134         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4135
4136         HWRM_CHECK_RESULT();
4137         HWRM_UNLOCK();
4138
4139         return rc;
4140 }
4141
4142 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4143 {
4144         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4145         struct hwrm_func_vf_cfg_input req = {0};
4146         int rc;
4147
4148         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4149
4150         req.enables = rte_cpu_to_le_32(
4151                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4152         req.async_event_cr = rte_cpu_to_le_16(
4153                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4154         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4155
4156         HWRM_CHECK_RESULT();
4157         HWRM_UNLOCK();
4158
4159         return rc;
4160 }
4161
4162 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4163 {
4164         struct hwrm_func_cfg_input req = {0};
4165         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4166         uint16_t dflt_vlan, fid;
4167         uint32_t func_cfg_flags;
4168         int rc = 0;
4169
4170         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4171
4172         if (is_vf) {
4173                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4174                 fid = bp->pf->vf_info[vf].fid;
4175                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4176         } else {
4177                 fid = rte_cpu_to_le_16(0xffff);
4178                 func_cfg_flags = bp->pf->func_cfg_flags;
4179                 dflt_vlan = bp->vlan;
4180         }
4181
4182         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4183         req.fid = rte_cpu_to_le_16(fid);
4184         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4185         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4186
4187         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4188
4189         HWRM_CHECK_RESULT();
4190         HWRM_UNLOCK();
4191
4192         return rc;
4193 }
4194
4195 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4196                         uint16_t max_bw, uint16_t enables)
4197 {
4198         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4199         struct hwrm_func_cfg_input req = {0};
4200         int rc;
4201
4202         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4203
4204         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4205         req.enables |= rte_cpu_to_le_32(enables);
4206         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4207         req.max_bw = rte_cpu_to_le_32(max_bw);
4208         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4209
4210         HWRM_CHECK_RESULT();
4211         HWRM_UNLOCK();
4212
4213         return rc;
4214 }
4215
4216 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4217 {
4218         struct hwrm_func_cfg_input req = {0};
4219         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4220         int rc = 0;
4221
4222         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4223
4224         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4225         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4226         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4227         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4228
4229         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4230
4231         HWRM_CHECK_RESULT();
4232         HWRM_UNLOCK();
4233
4234         return rc;
4235 }
4236
4237 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4238 {
4239         int rc;
4240
4241         if (BNXT_PF(bp))
4242                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4243         else
4244                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4245
4246         return rc;
4247 }
4248
4249 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4250                               void *encaped, size_t ec_size)
4251 {
4252         int rc = 0;
4253         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4254         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4255
4256         if (ec_size > sizeof(req.encap_request))
4257                 return -1;
4258
4259         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4260
4261         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4262         memcpy(req.encap_request, encaped, ec_size);
4263
4264         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4265
4266         HWRM_CHECK_RESULT();
4267         HWRM_UNLOCK();
4268
4269         return rc;
4270 }
4271
4272 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4273                                        struct rte_ether_addr *mac)
4274 {
4275         struct hwrm_func_qcfg_input req = {0};
4276         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4277         int rc;
4278
4279         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4280
4281         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4282         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4283
4284         HWRM_CHECK_RESULT();
4285
4286         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4287
4288         HWRM_UNLOCK();
4289
4290         return rc;
4291 }
4292
4293 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4294                             void *encaped, size_t ec_size)
4295 {
4296         int rc = 0;
4297         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4298         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4299
4300         if (ec_size > sizeof(req.encap_request))
4301                 return -1;
4302
4303         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4304
4305         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4306         memcpy(req.encap_request, encaped, ec_size);
4307
4308         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4309
4310         HWRM_CHECK_RESULT();
4311         HWRM_UNLOCK();
4312
4313         return rc;
4314 }
4315
4316 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4317 {
4318         /* One of the HW stat values that make up this counter was zero as
4319          * returned by HW in this iteration, so use the previous
4320          * iteration's counter value
4321          */
4322         if (*prev_cntr && *cntr == 0)
4323                 *cntr = *prev_cntr;
4324         else
4325                 *prev_cntr = *cntr;
4326 }
4327
4328 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4329                          struct bnxt_ring_stats *ring_stats, bool rx)
4330 {
4331         int rc = 0;
4332         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4333         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4334
4335         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4336
4337         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4338
4339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4340
4341         HWRM_CHECK_RESULT();
4342
4343         if (rx) {
4344                 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4345
4346                 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4347                 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4348                                       &prev_stats->rx_ucast_pkts);
4349
4350                 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4351                 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4352                                       &prev_stats->rx_mcast_pkts);
4353
4354                 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4355                 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4356                                       &prev_stats->rx_bcast_pkts);
4357
4358                 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4359                 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4360                                       &prev_stats->rx_ucast_bytes);
4361
4362                 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4363                 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4364                                       &prev_stats->rx_mcast_bytes);
4365
4366                 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4367                 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4368                                       &prev_stats->rx_bcast_bytes);
4369
4370                 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4371                 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4372                                       &prev_stats->rx_discard_pkts);
4373
4374                 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4375                 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4376                                       &prev_stats->rx_error_pkts);
4377
4378                 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4379                 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4380                                       &prev_stats->rx_agg_pkts);
4381
4382                 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4383                 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4384                                       &prev_stats->rx_agg_bytes);
4385
4386                 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4387                 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4388                                       &prev_stats->rx_agg_events);
4389
4390                 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4391                 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4392                                       &prev_stats->rx_agg_aborts);
4393         } else {
4394                 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4395
4396                 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4397                 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4398                                       &prev_stats->tx_ucast_pkts);
4399
4400                 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4401                 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4402                                       &prev_stats->tx_mcast_pkts);
4403
4404                 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4405                 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4406                                       &prev_stats->tx_bcast_pkts);
4407
4408                 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4409                 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4410                                       &prev_stats->tx_ucast_bytes);
4411
4412                 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4413                 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4414                                       &prev_stats->tx_mcast_bytes);
4415
4416                 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4417                 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4418                                       &prev_stats->tx_bcast_bytes);
4419
4420                 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4421                 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4422                                       &prev_stats->tx_discard_pkts);
4423         }
4424
4425         HWRM_UNLOCK();
4426
4427         return rc;
4428 }
4429
4430 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4431 {
4432         struct hwrm_port_qstats_input req = {0};
4433         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4434         struct bnxt_pf_info *pf = bp->pf;
4435         int rc;
4436
4437         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4438
4439         req.port_id = rte_cpu_to_le_16(pf->port_id);
4440         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4441         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4442         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4443
4444         HWRM_CHECK_RESULT();
4445         HWRM_UNLOCK();
4446
4447         return rc;
4448 }
4449
4450 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4451 {
4452         struct hwrm_port_clr_stats_input req = {0};
4453         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4454         struct bnxt_pf_info *pf = bp->pf;
4455         int rc;
4456
4457         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4458         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4459             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4460                 return 0;
4461
4462         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4463
4464         req.port_id = rte_cpu_to_le_16(pf->port_id);
4465         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4466
4467         HWRM_CHECK_RESULT();
4468         HWRM_UNLOCK();
4469
4470         return rc;
4471 }
4472
4473 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4474 {
4475         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4476         struct hwrm_port_led_qcaps_input req = {0};
4477         int rc;
4478
4479         if (BNXT_VF(bp))
4480                 return 0;
4481
4482         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4483         req.port_id = bp->pf->port_id;
4484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4485
4486         HWRM_CHECK_RESULT_SILENT();
4487
4488         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4489                 unsigned int i;
4490
4491                 bp->leds->num_leds = resp->num_leds;
4492                 memcpy(bp->leds, &resp->led0_id,
4493                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4494                 for (i = 0; i < bp->leds->num_leds; i++) {
4495                         struct bnxt_led_info *led = &bp->leds[i];
4496
4497                         uint16_t caps = led->led_state_caps;
4498
4499                         if (!led->led_group_id ||
4500                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4501                                 bp->leds->num_leds = 0;
4502                                 break;
4503                         }
4504                 }
4505         }
4506
4507         HWRM_UNLOCK();
4508
4509         return rc;
4510 }
4511
4512 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4513 {
4514         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4515         struct hwrm_port_led_cfg_input req = {0};
4516         struct bnxt_led_cfg *led_cfg;
4517         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4518         uint16_t duration = 0;
4519         int rc, i;
4520
4521         if (!bp->leds->num_leds || BNXT_VF(bp))
4522                 return -EOPNOTSUPP;
4523
4524         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4525
4526         if (led_on) {
4527                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4528                 duration = rte_cpu_to_le_16(500);
4529         }
4530         req.port_id = bp->pf->port_id;
4531         req.num_leds = bp->leds->num_leds;
4532         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4533         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4534                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4535                 led_cfg->led_id = bp->leds[i].led_id;
4536                 led_cfg->led_state = led_state;
4537                 led_cfg->led_blink_on = duration;
4538                 led_cfg->led_blink_off = duration;
4539                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4540         }
4541
4542         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4543
4544         HWRM_CHECK_RESULT();
4545         HWRM_UNLOCK();
4546
4547         return rc;
4548 }
4549
4550 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4551                                uint32_t *length)
4552 {
4553         int rc;
4554         struct hwrm_nvm_get_dir_info_input req = {0};
4555         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4556
4557         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4558
4559         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4560
4561         HWRM_CHECK_RESULT();
4562
4563         *entries = rte_le_to_cpu_32(resp->entries);
4564         *length = rte_le_to_cpu_32(resp->entry_length);
4565
4566         HWRM_UNLOCK();
4567         return rc;
4568 }
4569
4570 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4571 {
4572         int rc;
4573         uint32_t dir_entries;
4574         uint32_t entry_length;
4575         uint8_t *buf;
4576         size_t buflen;
4577         rte_iova_t dma_handle;
4578         struct hwrm_nvm_get_dir_entries_input req = {0};
4579         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4580
4581         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4582         if (rc != 0)
4583                 return rc;
4584
4585         *data++ = dir_entries;
4586         *data++ = entry_length;
4587         len -= 2;
4588         memset(data, 0xff, len);
4589
4590         buflen = dir_entries * entry_length;
4591         buf = rte_malloc("nvm_dir", buflen, 0);
4592         if (buf == NULL)
4593                 return -ENOMEM;
4594         dma_handle = rte_malloc_virt2iova(buf);
4595         if (dma_handle == RTE_BAD_IOVA) {
4596                 rte_free(buf);
4597                 PMD_DRV_LOG(ERR,
4598                         "unable to map response address to physical memory\n");
4599                 return -ENOMEM;
4600         }
4601         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4602         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4603         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4604
4605         if (rc == 0)
4606                 memcpy(data, buf, len > buflen ? buflen : len);
4607
4608         rte_free(buf);
4609         HWRM_CHECK_RESULT();
4610         HWRM_UNLOCK();
4611
4612         return rc;
4613 }
4614
4615 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4616                              uint32_t offset, uint32_t length,
4617                              uint8_t *data)
4618 {
4619         int rc;
4620         uint8_t *buf;
4621         rte_iova_t dma_handle;
4622         struct hwrm_nvm_read_input req = {0};
4623         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4624
4625         buf = rte_malloc("nvm_item", length, 0);
4626         if (!buf)
4627                 return -ENOMEM;
4628
4629         dma_handle = rte_malloc_virt2iova(buf);
4630         if (dma_handle == RTE_BAD_IOVA) {
4631                 rte_free(buf);
4632                 PMD_DRV_LOG(ERR,
4633                         "unable to map response address to physical memory\n");
4634                 return -ENOMEM;
4635         }
4636         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4637         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4638         req.dir_idx = rte_cpu_to_le_16(index);
4639         req.offset = rte_cpu_to_le_32(offset);
4640         req.len = rte_cpu_to_le_32(length);
4641         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4642         if (rc == 0)
4643                 memcpy(data, buf, length);
4644
4645         rte_free(buf);
4646         HWRM_CHECK_RESULT();
4647         HWRM_UNLOCK();
4648
4649         return rc;
4650 }
4651
4652 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4653 {
4654         int rc;
4655         struct hwrm_nvm_erase_dir_entry_input req = {0};
4656         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4657
4658         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4659         req.dir_idx = rte_cpu_to_le_16(index);
4660         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4661         HWRM_CHECK_RESULT();
4662         HWRM_UNLOCK();
4663
4664         return rc;
4665 }
4666
4667 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4668                           uint16_t dir_ordinal, uint16_t dir_ext,
4669                           uint16_t dir_attr, const uint8_t *data,
4670                           size_t data_len)
4671 {
4672         int rc;
4673         struct hwrm_nvm_write_input req = {0};
4674         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4675         rte_iova_t dma_handle;
4676         uint8_t *buf;
4677
4678         buf = rte_malloc("nvm_write", data_len, 0);
4679         if (!buf)
4680                 return -ENOMEM;
4681
4682         dma_handle = rte_malloc_virt2iova(buf);
4683         if (dma_handle == RTE_BAD_IOVA) {
4684                 rte_free(buf);
4685                 PMD_DRV_LOG(ERR,
4686                         "unable to map response address to physical memory\n");
4687                 return -ENOMEM;
4688         }
4689         memcpy(buf, data, data_len);
4690
4691         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4692
4693         req.dir_type = rte_cpu_to_le_16(dir_type);
4694         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4695         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4696         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4697         req.dir_data_length = rte_cpu_to_le_32(data_len);
4698         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4699
4700         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4701
4702         rte_free(buf);
4703         HWRM_CHECK_RESULT();
4704         HWRM_UNLOCK();
4705
4706         return rc;
4707 }
4708
4709 static void
4710 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4711 {
4712         uint32_t *count = cbdata;
4713
4714         *count = *count + 1;
4715 }
4716
4717 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4718                                      struct bnxt_vnic_info *vnic __rte_unused)
4719 {
4720         return 0;
4721 }
4722
4723 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4724 {
4725         uint32_t count = 0;
4726
4727         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4728             &count, bnxt_vnic_count_hwrm_stub);
4729
4730         return count;
4731 }
4732
4733 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4734                                         uint16_t *vnic_ids)
4735 {
4736         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4737         struct hwrm_func_vf_vnic_ids_query_output *resp =
4738                                                 bp->hwrm_cmd_resp_addr;
4739         int rc;
4740
4741         /* First query all VNIC ids */
4742         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4743
4744         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4745         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4746         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4747
4748         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4749                 HWRM_UNLOCK();
4750                 PMD_DRV_LOG(ERR,
4751                 "unable to map VNIC ID table address to physical memory\n");
4752                 return -ENOMEM;
4753         }
4754         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4755         HWRM_CHECK_RESULT();
4756         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4757
4758         HWRM_UNLOCK();
4759
4760         return rc;
4761 }
4762
4763 /*
4764  * This function queries the VNIC IDs  for a specified VF. It then calls
4765  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4766  * Then it calls the hwrm_cb function to program this new vnic configuration.
4767  */
4768 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4769         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4770         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4771 {
4772         struct bnxt_vnic_info vnic;
4773         int rc = 0;
4774         int i, num_vnic_ids;
4775         uint16_t *vnic_ids;
4776         size_t vnic_id_sz;
4777         size_t sz;
4778
4779         /* First query all VNIC ids */
4780         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4781         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4782                         RTE_CACHE_LINE_SIZE);
4783         if (vnic_ids == NULL)
4784                 return -ENOMEM;
4785
4786         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4787                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4788
4789         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4790
4791         if (num_vnic_ids < 0)
4792                 return num_vnic_ids;
4793
4794         /* Retrieve VNIC, update bd_stall then update */
4795
4796         for (i = 0; i < num_vnic_ids; i++) {
4797                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4798                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4799                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4800                 if (rc)
4801                         break;
4802                 if (vnic.mru <= 4)      /* Indicates unallocated */
4803                         continue;
4804
4805                 vnic_cb(&vnic, cbdata);
4806
4807                 rc = hwrm_cb(bp, &vnic);
4808                 if (rc)
4809                         break;
4810         }
4811
4812         rte_free(vnic_ids);
4813
4814         return rc;
4815 }
4816
4817 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4818                                               bool on)
4819 {
4820         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4821         struct hwrm_func_cfg_input req = {0};
4822         int rc;
4823
4824         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4825
4826         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4827         req.enables |= rte_cpu_to_le_32(
4828                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4829         req.vlan_antispoof_mode = on ?
4830                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4831                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4832         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4833
4834         HWRM_CHECK_RESULT();
4835         HWRM_UNLOCK();
4836
4837         return rc;
4838 }
4839
4840 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4841 {
4842         struct bnxt_vnic_info vnic;
4843         uint16_t *vnic_ids;
4844         size_t vnic_id_sz;
4845         int num_vnic_ids, i;
4846         size_t sz;
4847         int rc;
4848
4849         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4850         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4851                         RTE_CACHE_LINE_SIZE);
4852         if (vnic_ids == NULL)
4853                 return -ENOMEM;
4854
4855         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4856                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4857
4858         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4859         if (rc <= 0)
4860                 goto exit;
4861         num_vnic_ids = rc;
4862
4863         /*
4864          * Loop through to find the default VNIC ID.
4865          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4866          * by sending the hwrm_func_qcfg command to the firmware.
4867          */
4868         for (i = 0; i < num_vnic_ids; i++) {
4869                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4870                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4871                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4872                                         bp->pf->first_vf_id + vf);
4873                 if (rc)
4874                         goto exit;
4875                 if (vnic.func_default) {
4876                         rte_free(vnic_ids);
4877                         return vnic.fw_vnic_id;
4878                 }
4879         }
4880         /* Could not find a default VNIC. */
4881         PMD_DRV_LOG(ERR, "No default VNIC\n");
4882 exit:
4883         rte_free(vnic_ids);
4884         return rc;
4885 }
4886
4887 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4888                          uint16_t dst_id,
4889                          struct bnxt_filter_info *filter)
4890 {
4891         int rc = 0;
4892         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4893         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4894         uint32_t enables = 0;
4895
4896         if (filter->fw_em_filter_id != UINT64_MAX)
4897                 bnxt_hwrm_clear_em_filter(bp, filter);
4898
4899         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4900
4901         req.flags = rte_cpu_to_le_32(filter->flags);
4902
4903         enables = filter->enables |
4904               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4905         req.dst_id = rte_cpu_to_le_16(dst_id);
4906
4907         if (filter->ip_addr_type) {
4908                 req.ip_addr_type = filter->ip_addr_type;
4909                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4910         }
4911         if (enables &
4912             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4913                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4914         if (enables &
4915             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4916                 memcpy(req.src_macaddr, filter->src_macaddr,
4917                        RTE_ETHER_ADDR_LEN);
4918         if (enables &
4919             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4920                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4921                        RTE_ETHER_ADDR_LEN);
4922         if (enables &
4923             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4924                 req.ovlan_vid = filter->l2_ovlan;
4925         if (enables &
4926             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4927                 req.ivlan_vid = filter->l2_ivlan;
4928         if (enables &
4929             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4930                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4931         if (enables &
4932             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4933                 req.ip_protocol = filter->ip_protocol;
4934         if (enables &
4935             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4936                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4937         if (enables &
4938             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4939                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4940         if (enables &
4941             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4942                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4943         if (enables &
4944             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4945                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4946         if (enables &
4947             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4948                 req.mirror_vnic_id = filter->mirror_vnic_id;
4949
4950         req.enables = rte_cpu_to_le_32(enables);
4951
4952         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4953
4954         HWRM_CHECK_RESULT();
4955
4956         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4957         HWRM_UNLOCK();
4958
4959         return rc;
4960 }
4961
4962 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4963 {
4964         int rc = 0;
4965         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4966         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4967
4968         if (filter->fw_em_filter_id == UINT64_MAX)
4969                 return 0;
4970
4971         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4972
4973         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4974
4975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4976
4977         HWRM_CHECK_RESULT();
4978         HWRM_UNLOCK();
4979
4980         filter->fw_em_filter_id = UINT64_MAX;
4981         filter->fw_l2_filter_id = UINT64_MAX;
4982
4983         return 0;
4984 }
4985
4986 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4987                          uint16_t dst_id,
4988                          struct bnxt_filter_info *filter)
4989 {
4990         int rc = 0;
4991         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4992         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4993                                                 bp->hwrm_cmd_resp_addr;
4994         uint32_t enables = 0;
4995
4996         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4997                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4998
4999         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
5000
5001         req.flags = rte_cpu_to_le_32(filter->flags);
5002
5003         enables = filter->enables |
5004               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
5005         req.dst_id = rte_cpu_to_le_16(dst_id);
5006
5007         if (filter->ip_addr_type) {
5008                 req.ip_addr_type = filter->ip_addr_type;
5009                 enables |=
5010                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
5011         }
5012         if (enables &
5013             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5014                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5015         if (enables &
5016             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5017                 memcpy(req.src_macaddr, filter->src_macaddr,
5018                        RTE_ETHER_ADDR_LEN);
5019         if (enables &
5020             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5021                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5022         if (enables &
5023             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5024                 req.ip_protocol = filter->ip_protocol;
5025         if (enables &
5026             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5027                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5028         if (enables &
5029             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5030                 req.src_ipaddr_mask[0] =
5031                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5032         if (enables &
5033             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5034                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5035         if (enables &
5036             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5037                 req.dst_ipaddr_mask[0] =
5038                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5039         if (enables &
5040             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5041                 req.src_port = rte_cpu_to_le_16(filter->src_port);
5042         if (enables &
5043             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5044                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5045         if (enables &
5046             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5047                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5048         if (enables &
5049             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5050                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5051         if (enables &
5052             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5053                 req.mirror_vnic_id = filter->mirror_vnic_id;
5054
5055         req.enables = rte_cpu_to_le_32(enables);
5056
5057         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5058
5059         HWRM_CHECK_RESULT();
5060
5061         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5062         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5063         HWRM_UNLOCK();
5064
5065         return rc;
5066 }
5067
5068 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5069                                 struct bnxt_filter_info *filter)
5070 {
5071         int rc = 0;
5072         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5073         struct hwrm_cfa_ntuple_filter_free_output *resp =
5074                                                 bp->hwrm_cmd_resp_addr;
5075
5076         if (filter->fw_ntuple_filter_id == UINT64_MAX)
5077                 return 0;
5078
5079         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5080
5081         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5082
5083         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5084
5085         HWRM_CHECK_RESULT();
5086         HWRM_UNLOCK();
5087
5088         filter->fw_ntuple_filter_id = UINT64_MAX;
5089
5090         return 0;
5091 }
5092
5093 static int
5094 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5095 {
5096         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5097         uint8_t *rxq_state = bp->eth_dev->data->rx_queue_state;
5098         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5099         struct bnxt_rx_queue **rxqs = bp->rx_queues;
5100         uint16_t *ring_tbl = vnic->rss_table;
5101         int nr_ctxs = vnic->num_lb_ctxts;
5102         int max_rings = bp->rx_nr_rings;
5103         int i, j, k, cnt;
5104         int rc = 0;
5105
5106         for (i = 0, k = 0; i < nr_ctxs; i++) {
5107                 struct bnxt_rx_ring_info *rxr;
5108                 struct bnxt_cp_ring_info *cpr;
5109
5110                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5111
5112                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5113                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5114                 req.hash_mode_flags = vnic->hash_mode;
5115
5116                 req.ring_grp_tbl_addr =
5117                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5118                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5119                                      2 * sizeof(*ring_tbl));
5120                 req.hash_key_tbl_addr =
5121                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5122
5123                 req.ring_table_pair_index = i;
5124                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5125
5126                 for (j = 0; j < 64; j++) {
5127                         uint16_t ring_id;
5128
5129                         /* Find next active ring. */
5130                         for (cnt = 0; cnt < max_rings; cnt++) {
5131                                 if (rxq_state[k] != RTE_ETH_QUEUE_STATE_STOPPED)
5132                                         break;
5133                                 if (++k == max_rings)
5134                                         k = 0;
5135                         }
5136
5137                         /* Return if no rings are active. */
5138                         if (cnt == max_rings) {
5139                                 HWRM_UNLOCK();
5140                                 return 0;
5141                         }
5142
5143                         /* Add rx/cp ring pair to RSS table. */
5144                         rxr = rxqs[k]->rx_ring;
5145                         cpr = rxqs[k]->cp_ring;
5146
5147                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5148                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5149                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5150                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5151
5152                         if (++k == max_rings)
5153                                 k = 0;
5154                 }
5155                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5156                                             BNXT_USE_CHIMP_MB);
5157
5158                 HWRM_CHECK_RESULT();
5159                 HWRM_UNLOCK();
5160         }
5161
5162         return rc;
5163 }
5164
5165 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5166 {
5167         unsigned int rss_idx, fw_idx, i;
5168
5169         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5170                 return 0;
5171
5172         if (!(vnic->rss_table && vnic->hash_type))
5173                 return 0;
5174
5175         if (BNXT_CHIP_P5(bp))
5176                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5177
5178         /*
5179          * Fill the RSS hash & redirection table with
5180          * ring group ids for all VNICs
5181          */
5182         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5183              rss_idx++, fw_idx++) {
5184                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5185                         fw_idx %= bp->rx_cp_nr_rings;
5186                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5187                                 break;
5188                         fw_idx++;
5189                 }
5190
5191                 if (i == bp->rx_cp_nr_rings)
5192                         return 0;
5193
5194                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5195         }
5196
5197         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5198 }
5199
5200 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5201         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5202 {
5203         uint16_t flags;
5204
5205         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5206
5207         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5208         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5209
5210         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5211         req->num_cmpl_dma_aggr_during_int =
5212                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5213
5214         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5215
5216         /* min timer set to 1/2 of interrupt timer */
5217         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5218
5219         /* buf timer set to 1/4 of interrupt timer */
5220         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5221
5222         req->cmpl_aggr_dma_tmr_during_int =
5223                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5224
5225         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5226                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5227         req->flags = rte_cpu_to_le_16(flags);
5228 }
5229
5230 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5231                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5232 {
5233         struct hwrm_ring_aggint_qcaps_input req = {0};
5234         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5235         uint32_t enables;
5236         uint16_t flags;
5237         int rc;
5238
5239         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5240         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5241         HWRM_CHECK_RESULT();
5242
5243         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5244         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5245
5246         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5247                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5248         agg_req->flags = rte_cpu_to_le_16(flags);
5249         enables =
5250          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5251          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5252         agg_req->enables = rte_cpu_to_le_32(enables);
5253
5254         HWRM_UNLOCK();
5255         return rc;
5256 }
5257
5258 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5259                         struct bnxt_coal *coal, uint16_t ring_id)
5260 {
5261         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5262         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5263                                                 bp->hwrm_cmd_resp_addr;
5264         int rc;
5265
5266         /* Set ring coalesce parameters only for 100G NICs */
5267         if (BNXT_CHIP_P5(bp)) {
5268                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5269                         return -1;
5270         } else if (bnxt_stratus_device(bp)) {
5271                 bnxt_hwrm_set_coal_params(coal, &req);
5272         } else {
5273                 return 0;
5274         }
5275
5276         HWRM_PREP(&req,
5277                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5278                   BNXT_USE_CHIMP_MB);
5279         req.ring_id = rte_cpu_to_le_16(ring_id);
5280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5281         HWRM_CHECK_RESULT();
5282         HWRM_UNLOCK();
5283         return 0;
5284 }
5285
5286 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5287 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5288 {
5289         struct hwrm_func_backing_store_qcaps_input req = {0};
5290         struct hwrm_func_backing_store_qcaps_output *resp =
5291                 bp->hwrm_cmd_resp_addr;
5292         struct bnxt_ctx_pg_info *ctx_pg;
5293         struct bnxt_ctx_mem_info *ctx;
5294         int total_alloc_len;
5295         int rc, i, tqm_rings;
5296
5297         if (!BNXT_CHIP_P5(bp) ||
5298             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5299             BNXT_VF(bp) ||
5300             bp->ctx)
5301                 return 0;
5302
5303         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5304         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5305         HWRM_CHECK_RESULT_SILENT();
5306
5307         total_alloc_len = sizeof(*ctx);
5308         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5309                           RTE_CACHE_LINE_SIZE);
5310         if (!ctx) {
5311                 rc = -ENOMEM;
5312                 goto ctx_err;
5313         }
5314
5315         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5316         ctx->qp_min_qp1_entries =
5317                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5318         ctx->qp_max_l2_entries =
5319                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5320         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5321         ctx->srq_max_l2_entries =
5322                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5323         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5324         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5325         ctx->cq_max_l2_entries =
5326                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5327         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5328         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5329         ctx->vnic_max_vnic_entries =
5330                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5331         ctx->vnic_max_ring_table_entries =
5332                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5333         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5334         ctx->stat_max_entries =
5335                 rte_le_to_cpu_32(resp->stat_max_entries);
5336         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5337         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5338         ctx->tqm_min_entries_per_ring =
5339                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5340         ctx->tqm_max_entries_per_ring =
5341                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5342         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5343         if (!ctx->tqm_entries_multiple)
5344                 ctx->tqm_entries_multiple = 1;
5345         ctx->mrav_max_entries =
5346                 rte_le_to_cpu_32(resp->mrav_max_entries);
5347         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5348         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5349         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5350         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5351
5352         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5353                                   RTE_MIN(ctx->tqm_fp_rings_count,
5354                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5355                                   bp->max_q;
5356
5357         /* Check if the ext ring count needs to be counted.
5358          * Ext ring count is available only with new FW so we should not
5359          * look at the field on older FW.
5360          */
5361         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5362             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5363                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5364                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5365                                                   ctx->tqm_fp_rings_count);
5366         }
5367
5368         tqm_rings = ctx->tqm_fp_rings_count + 1;
5369
5370         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5371                             sizeof(*ctx_pg) * tqm_rings,
5372                             RTE_CACHE_LINE_SIZE);
5373         if (!ctx_pg) {
5374                 rc = -ENOMEM;
5375                 goto ctx_err;
5376         }
5377         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5378                 ctx->tqm_mem[i] = ctx_pg;
5379
5380         bp->ctx = ctx;
5381 ctx_err:
5382         HWRM_UNLOCK();
5383         return rc;
5384 }
5385
5386 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5387 {
5388         struct hwrm_func_backing_store_cfg_input req = {0};
5389         struct hwrm_func_backing_store_cfg_output *resp =
5390                 bp->hwrm_cmd_resp_addr;
5391         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5392         struct bnxt_ctx_pg_info *ctx_pg;
5393         uint32_t *num_entries;
5394         uint64_t *pg_dir;
5395         uint8_t *pg_attr;
5396         uint32_t ena;
5397         int i, rc;
5398
5399         if (!ctx)
5400                 return 0;
5401
5402         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5403         req.enables = rte_cpu_to_le_32(enables);
5404
5405         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5406                 ctx_pg = &ctx->qp_mem;
5407                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5408                 req.qp_num_qp1_entries =
5409                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5410                 req.qp_num_l2_entries =
5411                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5412                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5413                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5414                                       &req.qpc_pg_size_qpc_lvl,
5415                                       &req.qpc_page_dir);
5416         }
5417
5418         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5419                 ctx_pg = &ctx->srq_mem;
5420                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5421                 req.srq_num_l2_entries =
5422                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5423                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5424                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5425                                       &req.srq_pg_size_srq_lvl,
5426                                       &req.srq_page_dir);
5427         }
5428
5429         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5430                 ctx_pg = &ctx->cq_mem;
5431                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5432                 req.cq_num_l2_entries =
5433                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5434                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5435                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5436                                       &req.cq_pg_size_cq_lvl,
5437                                       &req.cq_page_dir);
5438         }
5439
5440         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5441                 ctx_pg = &ctx->vnic_mem;
5442                 req.vnic_num_vnic_entries =
5443                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5444                 req.vnic_num_ring_table_entries =
5445                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5446                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5447                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5448                                       &req.vnic_pg_size_vnic_lvl,
5449                                       &req.vnic_page_dir);
5450         }
5451
5452         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5453                 ctx_pg = &ctx->stat_mem;
5454                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5455                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5456                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5457                                       &req.stat_pg_size_stat_lvl,
5458                                       &req.stat_page_dir);
5459         }
5460
5461         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5462         num_entries = &req.tqm_sp_num_entries;
5463         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5464         pg_dir = &req.tqm_sp_page_dir;
5465         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5466         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5467                 if (!(enables & ena))
5468                         continue;
5469
5470                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5471
5472                 ctx_pg = ctx->tqm_mem[i];
5473                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5474                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5475         }
5476
5477         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5478                 /* DPDK does not need to configure MRAV and TIM type.
5479                  * So we are skipping over MRAV and TIM. Skip to configure
5480                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5481                  */
5482                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5483                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5484                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5485                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5486                                       &req.tqm_ring8_page_dir);
5487         }
5488
5489         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5490         HWRM_CHECK_RESULT();
5491         HWRM_UNLOCK();
5492
5493         return rc;
5494 }
5495
5496 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5497 {
5498         struct hwrm_port_qstats_ext_input req = {0};
5499         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5500         struct bnxt_pf_info *pf = bp->pf;
5501         int rc;
5502
5503         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5504               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5505                 return 0;
5506
5507         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5508
5509         req.port_id = rte_cpu_to_le_16(pf->port_id);
5510         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5511                 req.tx_stat_host_addr =
5512                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5513                 req.tx_stat_size =
5514                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5515         }
5516         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5517                 req.rx_stat_host_addr =
5518                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5519                 req.rx_stat_size =
5520                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5521         }
5522         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5523
5524         if (rc) {
5525                 bp->fw_rx_port_stats_ext_size = 0;
5526                 bp->fw_tx_port_stats_ext_size = 0;
5527         } else {
5528                 bp->fw_rx_port_stats_ext_size =
5529                         rte_le_to_cpu_16(resp->rx_stat_size);
5530                 bp->fw_tx_port_stats_ext_size =
5531                         rte_le_to_cpu_16(resp->tx_stat_size);
5532         }
5533
5534         HWRM_CHECK_RESULT();
5535         HWRM_UNLOCK();
5536
5537         return rc;
5538 }
5539
5540 int
5541 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5542 {
5543         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5544         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5545                 bp->hwrm_cmd_resp_addr;
5546         int rc = 0;
5547
5548         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5549         req.tunnel_type = type;
5550         req.dest_fid = bp->fw_fid;
5551         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5552         HWRM_CHECK_RESULT();
5553
5554         HWRM_UNLOCK();
5555
5556         return rc;
5557 }
5558
5559 int
5560 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5561 {
5562         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5563         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5564                 bp->hwrm_cmd_resp_addr;
5565         int rc = 0;
5566
5567         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5568         req.tunnel_type = type;
5569         req.dest_fid = bp->fw_fid;
5570         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5571         HWRM_CHECK_RESULT();
5572
5573         HWRM_UNLOCK();
5574
5575         return rc;
5576 }
5577
5578 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5579 {
5580         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5581         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5582                 bp->hwrm_cmd_resp_addr;
5583         int rc = 0;
5584
5585         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5586         req.src_fid = bp->fw_fid;
5587         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5588         HWRM_CHECK_RESULT();
5589
5590         if (type)
5591                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5592
5593         HWRM_UNLOCK();
5594
5595         return rc;
5596 }
5597
5598 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5599                                    uint16_t *dst_fid)
5600 {
5601         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5602         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5603                 bp->hwrm_cmd_resp_addr;
5604         int rc = 0;
5605
5606         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5607         req.src_fid = bp->fw_fid;
5608         req.tunnel_type = tun_type;
5609         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5610         HWRM_CHECK_RESULT();
5611
5612         if (dst_fid)
5613                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5614
5615         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5616
5617         HWRM_UNLOCK();
5618
5619         return rc;
5620 }
5621
5622 int bnxt_hwrm_set_mac(struct bnxt *bp)
5623 {
5624         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5625         struct hwrm_func_vf_cfg_input req = {0};
5626         int rc = 0;
5627
5628         if (!BNXT_VF(bp))
5629                 return 0;
5630
5631         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5632
5633         req.enables =
5634                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5635         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5636
5637         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5638
5639         HWRM_CHECK_RESULT();
5640
5641         HWRM_UNLOCK();
5642
5643         return rc;
5644 }
5645
5646 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5647 {
5648         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5649         struct hwrm_func_drv_if_change_input req = {0};
5650         uint32_t flags;
5651         int rc;
5652
5653         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5654                 return 0;
5655
5656         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5657          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5658          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5659          */
5660         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5661                 return 0;
5662
5663         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5664
5665         if (up)
5666                 req.flags =
5667                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5668
5669         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5670
5671         HWRM_CHECK_RESULT();
5672         flags = rte_le_to_cpu_32(resp->flags);
5673         HWRM_UNLOCK();
5674
5675         if (!up)
5676                 return 0;
5677
5678         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5679                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5680                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5681         }
5682
5683         return 0;
5684 }
5685
5686 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5687 {
5688         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5689         struct bnxt_error_recovery_info *info = bp->recovery_info;
5690         struct hwrm_error_recovery_qcfg_input req = {0};
5691         uint32_t flags = 0;
5692         unsigned int i;
5693         int rc;
5694
5695         /* Older FW does not have error recovery support */
5696         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5697                 return 0;
5698
5699         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5700
5701         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5702
5703         HWRM_CHECK_RESULT();
5704
5705         flags = rte_le_to_cpu_32(resp->flags);
5706         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5707                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5708         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5709                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5710
5711         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5712             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5713                 rc = -EINVAL;
5714                 goto err;
5715         }
5716
5717         /* FW returned values are in units of 100msec */
5718         info->driver_polling_freq =
5719                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5720         info->master_func_wait_period =
5721                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5722         info->normal_func_wait_period =
5723                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5724         info->master_func_wait_period_after_reset =
5725                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5726         info->max_bailout_time_after_reset =
5727                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5728         info->status_regs[BNXT_FW_STATUS_REG] =
5729                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5730         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5731                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5732         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5733                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5734         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5735                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5736         info->reg_array_cnt =
5737                 rte_le_to_cpu_32(resp->reg_array_cnt);
5738
5739         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5740                 rc = -EINVAL;
5741                 goto err;
5742         }
5743
5744         for (i = 0; i < info->reg_array_cnt; i++) {
5745                 info->reset_reg[i] =
5746                         rte_le_to_cpu_32(resp->reset_reg[i]);
5747                 info->reset_reg_val[i] =
5748                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5749                 info->delay_after_reset[i] =
5750                         resp->delay_after_reset[i];
5751         }
5752 err:
5753         HWRM_UNLOCK();
5754
5755         /* Map the FW status registers */
5756         if (!rc)
5757                 rc = bnxt_map_fw_health_status_regs(bp);
5758
5759         if (rc) {
5760                 rte_free(bp->recovery_info);
5761                 bp->recovery_info = NULL;
5762         }
5763         return rc;
5764 }
5765
5766 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5767 {
5768         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5769         struct hwrm_fw_reset_input req = {0};
5770         int rc;
5771
5772         if (!BNXT_PF(bp))
5773                 return -EOPNOTSUPP;
5774
5775         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5776
5777         req.embedded_proc_type =
5778                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5779         req.selfrst_status =
5780                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5781         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5782
5783         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5784                                     BNXT_USE_KONG(bp));
5785
5786         HWRM_CHECK_RESULT();
5787         HWRM_UNLOCK();
5788
5789         return rc;
5790 }
5791
5792 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5793 {
5794         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5795         struct hwrm_port_ts_query_input req = {0};
5796         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5797         uint32_t flags = 0;
5798         int rc;
5799
5800         if (!ptp)
5801                 return 0;
5802
5803         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5804
5805         switch (path) {
5806         case BNXT_PTP_FLAGS_PATH_TX:
5807                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5808                 break;
5809         case BNXT_PTP_FLAGS_PATH_RX:
5810                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5811                 break;
5812         case BNXT_PTP_FLAGS_CURRENT_TIME:
5813                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5814                 break;
5815         }
5816
5817         req.flags = rte_cpu_to_le_32(flags);
5818         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5819
5820         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5821
5822         HWRM_CHECK_RESULT();
5823
5824         if (timestamp) {
5825                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5826                 *timestamp |=
5827                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5828         }
5829         HWRM_UNLOCK();
5830
5831         return rc;
5832 }
5833
5834 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5835 {
5836         int rc = 0;
5837
5838         struct hwrm_cfa_counter_qcaps_input req = {0};
5839         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5840
5841         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5842                 PMD_DRV_LOG(DEBUG,
5843                             "Not a PF or trusted VF. Command not supported\n");
5844                 return 0;
5845         }
5846
5847         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5848         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5849         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5850
5851         HWRM_CHECK_RESULT();
5852         if (max_fc)
5853                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5854         HWRM_UNLOCK();
5855
5856         return 0;
5857 }
5858
5859 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5860 {
5861         int rc = 0;
5862         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5863         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5864
5865         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5866                 PMD_DRV_LOG(DEBUG,
5867                             "Not a PF or trusted VF. Command not supported\n");
5868                 return 0;
5869         }
5870
5871         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5872
5873         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5874         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5875         req.page_dir = rte_cpu_to_le_64(dma_addr);
5876
5877         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5878
5879         HWRM_CHECK_RESULT();
5880         if (ctx_id) {
5881                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5882                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5883         }
5884         HWRM_UNLOCK();
5885
5886         return 0;
5887 }
5888
5889 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5890 {
5891         int rc = 0;
5892         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5893         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5894
5895         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5896                 PMD_DRV_LOG(DEBUG,
5897                             "Not a PF or trusted VF. Command not supported\n");
5898                 return 0;
5899         }
5900
5901         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5902
5903         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5904
5905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5906
5907         HWRM_CHECK_RESULT();
5908         HWRM_UNLOCK();
5909
5910         return rc;
5911 }
5912
5913 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5914                               uint16_t cntr, uint16_t ctx_id,
5915                               uint32_t num_entries, bool enable)
5916 {
5917         struct hwrm_cfa_counter_cfg_input req = {0};
5918         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5919         uint16_t flags = 0;
5920         int rc;
5921
5922         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5923                 PMD_DRV_LOG(DEBUG,
5924                             "Not a PF or trusted VF. Command not supported\n");
5925                 return 0;
5926         }
5927
5928         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5929
5930         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5931         req.counter_type = rte_cpu_to_le_16(cntr);
5932         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5933                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5934         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5935         if (dir == BNXT_DIR_RX)
5936                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5937         else if (dir == BNXT_DIR_TX)
5938                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5939         req.flags = rte_cpu_to_le_16(flags);
5940         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5941         req.num_entries = rte_cpu_to_le_32(num_entries);
5942
5943         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5944         HWRM_CHECK_RESULT();
5945         HWRM_UNLOCK();
5946
5947         return 0;
5948 }
5949
5950 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5951                                  enum bnxt_flow_dir dir,
5952                                  uint16_t cntr,
5953                                  uint16_t num_entries)
5954 {
5955         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5956         struct hwrm_cfa_counter_qstats_input req = {0};
5957         uint16_t flow_ctx_id = 0;
5958         uint16_t flags = 0;
5959         int rc = 0;
5960
5961         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5962                 PMD_DRV_LOG(DEBUG,
5963                             "Not a PF or trusted VF. Command not supported\n");
5964                 return 0;
5965         }
5966
5967         if (dir == BNXT_DIR_RX) {
5968                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5969                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5970         } else if (dir == BNXT_DIR_TX) {
5971                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5972                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5973         }
5974
5975         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5976         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5977         req.counter_type = rte_cpu_to_le_16(cntr);
5978         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5979         req.num_entries = rte_cpu_to_le_16(num_entries);
5980         req.flags = rte_cpu_to_le_16(flags);
5981         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5982
5983         HWRM_CHECK_RESULT();
5984         HWRM_UNLOCK();
5985
5986         return 0;
5987 }
5988
5989 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5990                                 uint16_t *first_vf_id)
5991 {
5992         int rc = 0;
5993         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5994         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5995
5996         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5997
5998         req.fid = rte_cpu_to_le_16(fid);
5999
6000         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6001
6002         HWRM_CHECK_RESULT();
6003
6004         if (first_vf_id)
6005                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
6006
6007         HWRM_UNLOCK();
6008
6009         return rc;
6010 }
6011
6012 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6013 {
6014         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6015         struct hwrm_cfa_pair_alloc_input req = {0};
6016         int rc;
6017
6018         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6019                 PMD_DRV_LOG(DEBUG,
6020                             "Not a PF or trusted VF. Command not supported\n");
6021                 return 0;
6022         }
6023
6024         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6025         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6026         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6027                  bp->eth_dev->data->name, rep_bp->vf_id);
6028
6029         req.pf_b_id = rep_bp->parent_pf_idx;
6030         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6031                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6032         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6033         req.host_b_id = 1; /* TBD - Confirm if this is OK */
6034
6035         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6036                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6037         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6038                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6039         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6040                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6041         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6042                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6043
6044         req.q_ab = rep_bp->rep_q_r2f;
6045         req.q_ba = rep_bp->rep_q_f2r;
6046         req.fc_ab = rep_bp->rep_fc_r2f;
6047         req.fc_ba = rep_bp->rep_fc_f2r;
6048
6049         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6050         HWRM_CHECK_RESULT();
6051
6052         HWRM_UNLOCK();
6053         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6054                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6055         return rc;
6056 }
6057
6058 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6059 {
6060         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6061         struct hwrm_cfa_pair_free_input req = {0};
6062         int rc;
6063
6064         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6065                 PMD_DRV_LOG(DEBUG,
6066                             "Not a PF or trusted VF. Command not supported\n");
6067                 return 0;
6068         }
6069
6070         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6071         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6072                  bp->eth_dev->data->name, rep_bp->vf_id);
6073         req.pf_b_id = rep_bp->parent_pf_idx;
6074         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6075         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6076                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6077         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6078         HWRM_CHECK_RESULT();
6079         HWRM_UNLOCK();
6080         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6081                     rep_bp->vf_id);
6082         return rc;
6083 }
6084
6085 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6086 {
6087         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6088                                         bp->hwrm_cmd_resp_addr;
6089         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6090         uint32_t flags = 0;
6091         int rc = 0;
6092
6093         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6094                 return 0;
6095
6096         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6097                 PMD_DRV_LOG(DEBUG,
6098                             "Not a PF or trusted VF. Command not supported\n");
6099                 return 0;
6100         }
6101
6102         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6103         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6104
6105         HWRM_CHECK_RESULT();
6106         flags = rte_le_to_cpu_32(resp->flags);
6107         HWRM_UNLOCK();
6108
6109         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6110                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6111         else
6112                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6113
6114         return rc;
6115 }
6116
6117 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6118                             uint32_t echo_req_data2)
6119 {
6120         struct hwrm_func_echo_response_input req = {0};
6121         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6122         int rc;
6123
6124         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6125         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6126         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6127
6128         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6129
6130         HWRM_CHECK_RESULT();
6131         HWRM_UNLOCK();
6132
6133         return rc;
6134 }
6135
6136 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6137 {
6138         struct hwrm_ver_get_input req = {.req_type = 0 };
6139         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6140         int rc = 0;
6141
6142         bp->max_req_len = HWRM_MAX_REQ_LEN;
6143         bp->max_resp_len = BNXT_PAGE_SIZE;
6144         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6145
6146         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6147         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6148         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6149         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6150
6151         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6152
6153         HWRM_CHECK_RESULT_SILENT();
6154
6155         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6156                 rc = -EAGAIN;
6157
6158         HWRM_UNLOCK();
6159
6160         return rc;
6161 }
6162
6163 int bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt *bp, uint16_t i2c_addr,
6164                                           uint16_t page_number, uint16_t start_addr,
6165                                           uint16_t data_length, uint8_t *buf)
6166 {
6167         struct hwrm_port_phy_i2c_read_output *resp = bp->hwrm_cmd_resp_addr;
6168         struct hwrm_port_phy_i2c_read_input req = {0};
6169         uint32_t enables = HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET;
6170         int rc, byte_offset = 0;
6171
6172         do {
6173                 uint16_t xfer_size;
6174
6175                 HWRM_PREP(&req, HWRM_PORT_PHY_I2C_READ, BNXT_USE_CHIMP_MB);
6176                 req.i2c_slave_addr = i2c_addr;
6177                 req.page_number = rte_cpu_to_le_16(page_number);
6178                 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
6179
6180                 xfer_size = RTE_MIN(data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
6181                 req.page_offset = rte_cpu_to_le_16(start_addr + byte_offset);
6182                 req.data_length = xfer_size;
6183                 req.enables = rte_cpu_to_le_32(start_addr + byte_offset ? enables : 0);
6184                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6185                 HWRM_CHECK_RESULT();
6186
6187                 memcpy(buf + byte_offset, resp->data, xfer_size);
6188
6189                 data_length -= xfer_size;
6190                 byte_offset += xfer_size;
6191
6192                 HWRM_UNLOCK();
6193         } while (data_length > 0);
6194
6195         return rc;
6196 }
6197
6198 void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index)
6199 {
6200         struct bnxt_tx_queue *txq = bp->tx_queues[queue_index];
6201         struct bnxt_tx_ring_info *txr = txq->tx_ring;
6202         struct bnxt_ring *ring = txr->tx_ring_struct;
6203         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
6204
6205         bnxt_hwrm_ring_free(bp, ring,
6206                             HWRM_RING_FREE_INPUT_RING_TYPE_TX,
6207                             cpr->cp_ring_struct->fw_ring_id);
6208         txr->tx_raw_prod = 0;
6209         txr->tx_raw_cons = 0;
6210         memset(txr->tx_desc_ring, 0,
6211                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_desc_ring));
6212         memset(txr->tx_buf_ring, 0,
6213                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_buf_ring));
6214
6215         bnxt_hwrm_stat_ctx_free(bp, cpr);
6216
6217         bnxt_free_cp_ring(bp, cpr);
6218 }
6219
6220 int bnxt_hwrm_config_host_mtu(struct bnxt *bp)
6221 {
6222         struct hwrm_func_cfg_input req = {0};
6223         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
6224         int rc;
6225
6226         if (!BNXT_PF(bp))
6227                 return 0;
6228
6229         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
6230
6231         req.fid = rte_cpu_to_le_16(0xffff);
6232         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU);
6233         req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
6234
6235         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6236         HWRM_CHECK_RESULT();
6237         HWRM_UNLOCK();
6238
6239         return rc;
6240 }