4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_byteorder.h>
35 #include <rte_common.h>
36 #include <rte_cycles.h>
37 #include <rte_malloc.h>
38 #include <rte_memzone.h>
39 #include <rte_version.h>
43 #include "bnxt_filter.h"
44 #include "bnxt_hwrm.h"
47 #include "bnxt_vnic.h"
48 #include "hsi_struct_def_dpdk.h"
50 #define HWRM_CMD_TIMEOUT 2000
53 * HWRM Functions (sent to HWRM)
54 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
55 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
56 * command was failed by the ChiMP.
59 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
63 struct input *req = msg;
64 struct output *resp = bp->hwrm_cmd_resp_addr;
69 /* Write request msg to hwrm channel */
70 for (i = 0; i < msg_len; i += 4) {
71 bar = (uint8_t *)bp->bar0 + i;
72 *(volatile uint32_t *)bar = *data;
76 /* Zero the rest of the request space */
77 for (; i < bp->max_req_len; i += 4) {
78 bar = (uint8_t *)bp->bar0 + i;
79 *(volatile uint32_t *)bar = 0;
82 /* Ring channel doorbell */
83 bar = (uint8_t *)bp->bar0 + 0x100;
84 *(volatile uint32_t *)bar = 1;
86 /* Poll for the valid bit */
87 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
88 /* Sanity check on the resp->resp_len */
90 if (resp->resp_len && resp->resp_len <=
92 /* Last byte of resp contains the valid key */
93 valid = (uint8_t *)resp + resp->resp_len - 1;
94 if (*valid == HWRM_RESP_VALID_KEY)
100 if (i >= HWRM_CMD_TIMEOUT) {
101 RTE_LOG(ERR, PMD, "Error sending msg %x\n",
111 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
115 rte_spinlock_lock(&bp->hwrm_lock);
116 rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
117 rte_spinlock_unlock(&bp->hwrm_lock);
121 #define HWRM_PREP(req, type, cr, resp) \
122 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
123 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
124 req.cmpl_ring = rte_cpu_to_le_16(cr); \
125 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
126 req.target_id = rte_cpu_to_le_16(0xffff); \
127 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
129 #define HWRM_CHECK_RESULT \
132 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
136 if (resp->error_code) { \
137 rc = rte_le_to_cpu_16(resp->error_code); \
138 RTE_LOG(ERR, PMD, "%s error %d\n", __func__, rc); \
143 int bnxt_hwrm_clear_filter(struct bnxt *bp,
144 struct bnxt_filter_info *filter)
147 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
148 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
150 HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
152 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
154 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
158 filter->fw_l2_filter_id = -1;
163 int bnxt_hwrm_set_filter(struct bnxt *bp,
164 struct bnxt_vnic_info *vnic,
165 struct bnxt_filter_info *filter)
168 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
169 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
170 uint32_t enables = 0;
172 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
174 req.flags = rte_cpu_to_le_32(filter->flags);
176 enables = filter->enables |
177 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
178 req.dst_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
181 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
182 memcpy(req.l2_addr, filter->l2_addr,
185 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
186 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
189 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
190 req.l2_ovlan = filter->l2_ovlan;
192 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
193 req.l2_ovlan_mask = filter->l2_ovlan_mask;
195 req.enables = rte_cpu_to_le_32(enables);
197 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
201 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
206 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, void *fwd_cmd)
209 struct hwrm_exec_fwd_resp_input req = {.req_type = 0 };
210 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
212 HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
214 memcpy(req.encap_request, fwd_cmd,
215 sizeof(req.encap_request));
217 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
224 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
227 struct hwrm_func_qcaps_input req = {.req_type = 0 };
228 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
230 HWRM_PREP(req, FUNC_QCAPS, -1, resp);
232 req.fid = rte_cpu_to_le_16(0xffff);
234 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
239 struct bnxt_pf_info *pf = &bp->pf;
241 pf->fw_fid = rte_le_to_cpu_32(resp->fid);
242 pf->port_id = resp->port_id;
243 memcpy(pf->mac_addr, resp->perm_mac_address, ETHER_ADDR_LEN);
244 pf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
245 pf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
246 pf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
247 pf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
248 pf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
249 pf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
250 pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
251 pf->max_vfs = rte_le_to_cpu_16(resp->max_vfs);
253 struct bnxt_vf_info *vf = &bp->vf;
255 vf->fw_fid = rte_le_to_cpu_32(resp->fid);
256 memcpy(vf->mac_addr, &resp->perm_mac_address, ETHER_ADDR_LEN);
257 vf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
258 vf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
259 vf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
260 vf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
261 vf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
262 vf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
268 int bnxt_hwrm_func_driver_register(struct bnxt *bp, uint32_t flags,
269 uint32_t *vf_req_fwd)
272 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
273 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
275 if (bp->flags & BNXT_FLAG_REGISTERED)
278 HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
280 req.enables = HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER;
281 req.ver_maj = RTE_VER_YEAR;
282 req.ver_min = RTE_VER_MONTH;
283 req.ver_upd = RTE_VER_MINOR;
285 memcpy(req.vf_req_fwd, vf_req_fwd, sizeof(req.vf_req_fwd));
287 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
291 bp->flags |= BNXT_FLAG_REGISTERED;
296 int bnxt_hwrm_ver_get(struct bnxt *bp)
299 struct hwrm_ver_get_input req = {.req_type = 0 };
300 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
303 uint16_t max_resp_len;
304 char type[RTE_MEMZONE_NAMESIZE];
306 HWRM_PREP(req, VER_GET, -1, resp);
308 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
309 req.hwrm_intf_min = HWRM_VERSION_MINOR;
310 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
313 * Hold the lock since we may be adjusting the response pointers.
315 rte_spinlock_lock(&bp->hwrm_lock);
316 rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
320 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
321 resp->hwrm_intf_maj, resp->hwrm_intf_min,
323 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
325 my_version = HWRM_VERSION_MAJOR << 16;
326 my_version |= HWRM_VERSION_MINOR << 8;
327 my_version |= HWRM_VERSION_UPDATE;
329 fw_version = resp->hwrm_intf_maj << 16;
330 fw_version |= resp->hwrm_intf_min << 8;
331 fw_version |= resp->hwrm_intf_upd;
333 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
334 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
339 if (my_version != fw_version) {
340 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
341 if (my_version < fw_version) {
343 "Firmware API version is newer than driver.\n");
345 "The driver may be missing features.\n");
348 "Firmware API version is older than driver.\n");
350 "Not all driver features may be functional.\n");
354 if (bp->max_req_len > resp->max_req_win_len) {
355 RTE_LOG(ERR, PMD, "Unsupported request length\n");
358 bp->max_req_len = resp->max_req_win_len;
359 max_resp_len = resp->max_resp_len;
360 if (bp->max_resp_len != max_resp_len) {
361 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
362 bp->pdev->addr.domain, bp->pdev->addr.bus,
363 bp->pdev->addr.devid, bp->pdev->addr.function);
365 rte_free(bp->hwrm_cmd_resp_addr);
367 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
368 if (bp->hwrm_cmd_resp_addr == NULL) {
372 bp->hwrm_cmd_resp_dma_addr =
373 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
374 bp->max_resp_len = max_resp_len;
378 rte_spinlock_unlock(&bp->hwrm_lock);
382 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
385 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
386 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
388 if (!(bp->flags & BNXT_FLAG_REGISTERED))
391 HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
394 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
398 bp->flags &= ~BNXT_FLAG_REGISTERED;
403 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
406 struct hwrm_port_phy_cfg_input req = {.req_type = 0};
407 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
409 HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
411 req.flags = conf->phy_flags;
413 req.force_link_speed = conf->link_speed;
415 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
416 * any auto mode, even "none".
418 if (req.auto_mode == HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE) {
419 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
421 req.auto_mode = conf->auto_mode;
423 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
424 req.auto_link_speed_mask = conf->auto_link_speed_mask;
426 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
427 req.auto_link_speed = conf->auto_link_speed;
429 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
431 req.auto_duplex = conf->duplex;
432 req.enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
433 req.auto_pause = conf->auto_pause;
434 /* Set force_pause if there is no auto or if there is a force */
437 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
440 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
441 req.force_pause = conf->force_pause;
444 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
446 req.flags &= ~HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
447 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN;
448 req.force_link_speed = 0;
451 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
458 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
461 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
462 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
464 HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
466 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
470 #define GET_QUEUE_INFO(x) \
471 bp->cos_queue[x].id = resp->queue_id##x; \
472 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
486 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
489 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
490 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
492 HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
494 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
497 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
498 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
500 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
508 * HWRM utility functions
511 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
516 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
517 struct bnxt_tx_queue *txq;
518 struct bnxt_rx_queue *rxq;
519 struct bnxt_cp_ring_info *cpr;
521 if (i >= bp->rx_cp_nr_rings) {
522 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
525 rxq = bp->rx_queues[i];
529 rc = bnxt_hwrm_stat_clear(bp, cpr);
536 void bnxt_free_hwrm_resources(struct bnxt *bp)
538 /* Release memzone */
539 rte_free(bp->hwrm_cmd_resp_addr);
540 bp->hwrm_cmd_resp_addr = NULL;
541 bp->hwrm_cmd_resp_dma_addr = 0;
544 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
546 struct rte_pci_device *pdev = bp->pdev;
547 char type[RTE_MEMZONE_NAMESIZE];
549 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
550 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
551 bp->max_req_len = HWRM_MAX_REQ_LEN;
552 bp->max_resp_len = HWRM_MAX_RESP_LEN;
553 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
554 if (bp->hwrm_cmd_resp_addr == NULL)
556 bp->hwrm_cmd_resp_dma_addr =
557 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
558 rte_spinlock_init(&bp->hwrm_lock);
563 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
565 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
567 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
568 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
570 switch (conf_link_speed) {
571 case ETH_LINK_SPEED_10M_HD:
572 case ETH_LINK_SPEED_100M_HD:
573 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
575 return hw_link_duplex;
578 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
580 uint16_t eth_link_speed = 0;
582 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
583 return ETH_LINK_SPEED_AUTONEG;
585 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
586 case ETH_LINK_SPEED_100M:
587 case ETH_LINK_SPEED_100M_HD:
589 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB;
591 case ETH_LINK_SPEED_1G:
593 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
595 case ETH_LINK_SPEED_2_5G:
597 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
599 case ETH_LINK_SPEED_10G:
601 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
603 case ETH_LINK_SPEED_20G:
605 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
607 case ETH_LINK_SPEED_25G:
609 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
611 case ETH_LINK_SPEED_40G:
613 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
615 case ETH_LINK_SPEED_50G:
617 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
621 "Unsupported link speed %d; default to AUTO\n",
625 return eth_link_speed;
628 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
629 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
630 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
631 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
633 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
637 if (link_speed == ETH_LINK_SPEED_AUTONEG)
640 if (link_speed & ETH_LINK_SPEED_FIXED) {
641 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
643 if (one_speed & (one_speed - 1)) {
645 "Invalid advertised speeds (%u) for port %u\n",
646 link_speed, port_id);
649 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
651 "Unsupported advertised speed (%u) for port %u\n",
652 link_speed, port_id);
656 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
658 "Unsupported advertised speeds (%u) for port %u\n",
659 link_speed, port_id);
666 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
670 if (link_speed == ETH_LINK_SPEED_AUTONEG)
671 link_speed = BNXT_SUPPORTED_SPEEDS;
673 if (link_speed & ETH_LINK_SPEED_100M)
674 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
675 if (link_speed & ETH_LINK_SPEED_100M_HD)
676 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
677 if (link_speed & ETH_LINK_SPEED_1G)
678 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
679 if (link_speed & ETH_LINK_SPEED_2_5G)
680 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
681 if (link_speed & ETH_LINK_SPEED_10G)
682 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
683 if (link_speed & ETH_LINK_SPEED_20G)
684 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
685 if (link_speed & ETH_LINK_SPEED_25G)
686 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
687 if (link_speed & ETH_LINK_SPEED_40G)
688 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
689 if (link_speed & ETH_LINK_SPEED_50G)
690 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
694 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
697 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
698 struct bnxt_link_info link_req;
701 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
702 bp->eth_dev->data->port_id);
706 memset(&link_req, 0, sizeof(link_req));
707 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
708 link_req.link_up = link_up;
711 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
713 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW;
714 link_req.auto_link_speed_mask =
715 bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
716 link_req.auto_link_speed =
717 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB;
719 link_req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
720 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE |
721 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
722 link_req.link_speed = speed;
724 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
725 link_req.auto_pause = bp->link_info.auto_pause;
726 link_req.force_pause = bp->link_info.force_pause;
728 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
731 "Set link config failed with rc %d\n", rc);