4 * Copyright(c) Broadcom Limited.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
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19 * from this software without specific prior written permission.
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_byteorder.h>
35 #include <rte_common.h>
36 #include <rte_cycles.h>
37 #include <rte_malloc.h>
38 #include <rte_memzone.h>
39 #include <rte_version.h>
42 #include "bnxt_filter.h"
43 #include "bnxt_hwrm.h"
44 #include "bnxt_vnic.h"
45 #include "hsi_struct_def_dpdk.h"
47 #define HWRM_CMD_TIMEOUT 2000
50 * HWRM Functions (sent to HWRM)
51 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
52 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
53 * command was failed by the ChiMP.
56 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
60 struct input *req = msg;
61 struct output *resp = bp->hwrm_cmd_resp_addr;
66 /* Write request msg to hwrm channel */
67 for (i = 0; i < msg_len; i += 4) {
68 bar = (uint8_t *)bp->bar0 + i;
69 *(volatile uint32_t *)bar = *data;
73 /* Zero the rest of the request space */
74 for (; i < bp->max_req_len; i += 4) {
75 bar = (uint8_t *)bp->bar0 + i;
76 *(volatile uint32_t *)bar = 0;
79 /* Ring channel doorbell */
80 bar = (uint8_t *)bp->bar0 + 0x100;
81 *(volatile uint32_t *)bar = 1;
83 /* Poll for the valid bit */
84 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
85 /* Sanity check on the resp->resp_len */
87 if (resp->resp_len && resp->resp_len <=
89 /* Last byte of resp contains the valid key */
90 valid = (uint8_t *)resp + resp->resp_len - 1;
91 if (*valid == HWRM_RESP_VALID_KEY)
97 if (i >= HWRM_CMD_TIMEOUT) {
98 RTE_LOG(ERR, PMD, "Error sending msg %x\n",
108 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
112 rte_spinlock_lock(&bp->hwrm_lock);
113 rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
114 rte_spinlock_unlock(&bp->hwrm_lock);
118 #define HWRM_PREP(req, type, cr, resp) \
119 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
120 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
121 req.cmpl_ring = rte_cpu_to_le_16(cr); \
122 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
123 req.target_id = rte_cpu_to_le_16(0xffff); \
124 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
126 #define HWRM_CHECK_RESULT \
129 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
133 if (resp->error_code) { \
134 rc = rte_le_to_cpu_16(resp->error_code); \
135 RTE_LOG(ERR, PMD, "%s error %d\n", __func__, rc); \
140 int bnxt_hwrm_clear_filter(struct bnxt *bp,
141 struct bnxt_filter_info *filter)
144 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
145 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
147 HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
149 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
151 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
155 filter->fw_l2_filter_id = -1;
160 int bnxt_hwrm_set_filter(struct bnxt *bp,
161 struct bnxt_vnic_info *vnic,
162 struct bnxt_filter_info *filter)
165 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
166 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
167 uint32_t enables = 0;
169 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
171 req.flags = rte_cpu_to_le_32(filter->flags);
173 enables = filter->enables |
174 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
175 req.dst_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
178 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
179 memcpy(req.l2_addr, filter->l2_addr,
182 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
183 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
186 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
187 req.l2_ovlan = filter->l2_ovlan;
189 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
190 req.l2_ovlan_mask = filter->l2_ovlan_mask;
192 req.enables = rte_cpu_to_le_32(enables);
194 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
198 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
203 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, void *fwd_cmd)
206 struct hwrm_exec_fwd_resp_input req = {.req_type = 0 };
207 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
209 HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
211 memcpy(req.encap_request, fwd_cmd,
212 sizeof(req.encap_request));
214 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
221 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
224 struct hwrm_func_qcaps_input req = {.req_type = 0 };
225 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
227 HWRM_PREP(req, FUNC_QCAPS, -1, resp);
229 req.fid = rte_cpu_to_le_16(0xffff);
231 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
236 struct bnxt_pf_info *pf = &bp->pf;
238 pf->fw_fid = rte_le_to_cpu_32(resp->fid);
239 pf->port_id = resp->port_id;
240 memcpy(pf->mac_addr, resp->perm_mac_address, ETHER_ADDR_LEN);
241 pf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
242 pf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
243 pf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
244 pf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
245 pf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
246 pf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
247 pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
248 pf->max_vfs = rte_le_to_cpu_16(resp->max_vfs);
250 struct bnxt_vf_info *vf = &bp->vf;
252 vf->fw_fid = rte_le_to_cpu_32(resp->fid);
253 memcpy(vf->mac_addr, &resp->perm_mac_address, ETHER_ADDR_LEN);
254 vf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
255 vf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
256 vf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
257 vf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
258 vf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
259 vf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
265 int bnxt_hwrm_func_driver_register(struct bnxt *bp, uint32_t flags,
266 uint32_t *vf_req_fwd)
269 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
270 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
272 if (bp->flags & BNXT_FLAG_REGISTERED)
275 HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
277 req.enables = HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER;
278 req.ver_maj = RTE_VER_YEAR;
279 req.ver_min = RTE_VER_MONTH;
280 req.ver_upd = RTE_VER_MINOR;
282 memcpy(req.vf_req_fwd, vf_req_fwd, sizeof(req.vf_req_fwd));
284 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
288 bp->flags |= BNXT_FLAG_REGISTERED;
293 int bnxt_hwrm_ver_get(struct bnxt *bp)
296 struct hwrm_ver_get_input req = {.req_type = 0 };
297 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
300 uint16_t max_resp_len;
301 char type[RTE_MEMZONE_NAMESIZE];
303 HWRM_PREP(req, VER_GET, -1, resp);
305 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
306 req.hwrm_intf_min = HWRM_VERSION_MINOR;
307 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
310 * Hold the lock since we may be adjusting the response pointers.
312 rte_spinlock_lock(&bp->hwrm_lock);
313 rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
317 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
318 resp->hwrm_intf_maj, resp->hwrm_intf_min,
320 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
322 my_version = HWRM_VERSION_MAJOR << 16;
323 my_version |= HWRM_VERSION_MINOR << 8;
324 my_version |= HWRM_VERSION_UPDATE;
326 fw_version = resp->hwrm_intf_maj << 16;
327 fw_version |= resp->hwrm_intf_min << 8;
328 fw_version |= resp->hwrm_intf_upd;
330 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
331 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
336 if (my_version != fw_version) {
337 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
338 if (my_version < fw_version) {
340 "Firmware API version is newer than driver.\n");
342 "The driver may be missing features.\n");
345 "Firmware API version is older than driver.\n");
347 "Not all driver features may be functional.\n");
351 if (bp->max_req_len > resp->max_req_win_len) {
352 RTE_LOG(ERR, PMD, "Unsupported request length\n");
355 bp->max_req_len = resp->max_req_win_len;
356 max_resp_len = resp->max_resp_len;
357 if (bp->max_resp_len != max_resp_len) {
358 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
359 bp->pdev->addr.domain, bp->pdev->addr.bus,
360 bp->pdev->addr.devid, bp->pdev->addr.function);
362 rte_free(bp->hwrm_cmd_resp_addr);
364 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
365 if (bp->hwrm_cmd_resp_addr == NULL) {
369 bp->hwrm_cmd_resp_dma_addr =
370 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
371 bp->max_resp_len = max_resp_len;
375 rte_spinlock_unlock(&bp->hwrm_lock);
379 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
382 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
383 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
385 if (!(bp->flags & BNXT_FLAG_REGISTERED))
388 HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
391 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
395 bp->flags &= ~BNXT_FLAG_REGISTERED;
400 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
403 struct hwrm_port_phy_cfg_input req = {.req_type = 0};
404 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
406 HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
408 req.flags = conf->phy_flags;
410 req.force_link_speed = conf->link_speed;
412 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
413 * any auto mode, even "none".
415 if (req.auto_mode == HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE) {
416 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
418 req.auto_mode = conf->auto_mode;
420 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
421 req.auto_link_speed_mask = conf->auto_link_speed_mask;
423 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
424 req.auto_link_speed = conf->auto_link_speed;
426 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
428 req.auto_duplex = conf->duplex;
429 req.enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
430 req.auto_pause = conf->auto_pause;
431 /* Set force_pause if there is no auto or if there is a force */
434 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
437 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
438 req.force_pause = conf->force_pause;
441 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
443 req.flags &= ~HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
444 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN;
445 req.force_link_speed = 0;
448 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
455 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
458 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
459 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
461 HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
463 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
467 #define GET_QUEUE_INFO(x) \
468 bp->cos_queue[x].id = resp->queue_id##x; \
469 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
484 * HWRM utility functions
487 void bnxt_free_hwrm_resources(struct bnxt *bp)
489 /* Release memzone */
490 rte_free(bp->hwrm_cmd_resp_addr);
491 bp->hwrm_cmd_resp_addr = NULL;
492 bp->hwrm_cmd_resp_dma_addr = 0;
495 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
497 struct rte_pci_device *pdev = bp->pdev;
498 char type[RTE_MEMZONE_NAMESIZE];
500 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
501 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
502 bp->max_req_len = HWRM_MAX_REQ_LEN;
503 bp->max_resp_len = HWRM_MAX_RESP_LEN;
504 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
505 if (bp->hwrm_cmd_resp_addr == NULL)
507 bp->hwrm_cmd_resp_dma_addr =
508 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
509 rte_spinlock_init(&bp->hwrm_lock);
514 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
516 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
518 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
519 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
521 switch (conf_link_speed) {
522 case ETH_LINK_SPEED_10M_HD:
523 case ETH_LINK_SPEED_100M_HD:
524 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
526 return hw_link_duplex;
529 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
531 uint16_t eth_link_speed = 0;
533 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
534 return ETH_LINK_SPEED_AUTONEG;
536 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
537 case ETH_LINK_SPEED_100M:
538 case ETH_LINK_SPEED_100M_HD:
540 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB;
542 case ETH_LINK_SPEED_1G:
544 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
546 case ETH_LINK_SPEED_2_5G:
548 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
550 case ETH_LINK_SPEED_10G:
552 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
554 case ETH_LINK_SPEED_20G:
556 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
558 case ETH_LINK_SPEED_25G:
560 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
562 case ETH_LINK_SPEED_40G:
564 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
566 case ETH_LINK_SPEED_50G:
568 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
572 "Unsupported link speed %d; default to AUTO\n",
576 return eth_link_speed;
579 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
580 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
581 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
582 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
584 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
588 if (link_speed == ETH_LINK_SPEED_AUTONEG)
591 if (link_speed & ETH_LINK_SPEED_FIXED) {
592 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
594 if (one_speed & (one_speed - 1)) {
596 "Invalid advertised speeds (%u) for port %u\n",
597 link_speed, port_id);
600 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
602 "Unsupported advertised speed (%u) for port %u\n",
603 link_speed, port_id);
607 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
609 "Unsupported advertised speeds (%u) for port %u\n",
610 link_speed, port_id);
617 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
621 if (link_speed == ETH_LINK_SPEED_AUTONEG)
622 link_speed = BNXT_SUPPORTED_SPEEDS;
624 if (link_speed & ETH_LINK_SPEED_100M)
625 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
626 if (link_speed & ETH_LINK_SPEED_100M_HD)
627 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
628 if (link_speed & ETH_LINK_SPEED_1G)
629 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
630 if (link_speed & ETH_LINK_SPEED_2_5G)
631 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
632 if (link_speed & ETH_LINK_SPEED_10G)
633 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
634 if (link_speed & ETH_LINK_SPEED_20G)
635 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
636 if (link_speed & ETH_LINK_SPEED_25G)
637 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
638 if (link_speed & ETH_LINK_SPEED_40G)
639 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
640 if (link_speed & ETH_LINK_SPEED_50G)
641 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
645 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
648 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
649 struct bnxt_link_info link_req;
652 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
653 bp->eth_dev->data->port_id);
657 memset(&link_req, 0, sizeof(link_req));
658 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
659 link_req.link_up = link_up;
662 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
664 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW;
665 link_req.auto_link_speed_mask =
666 bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
667 link_req.auto_link_speed =
668 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB;
670 link_req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
671 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE |
672 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
673 link_req.link_speed = speed;
675 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
676 link_req.auto_pause = bp->link_info.auto_pause;
677 link_req.force_pause = bp->link_info.force_pause;
679 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
682 "Set link config failed with rc %d\n", rc);