1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(void *) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages > 1) {
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
103 timeout = bp->hwrm_cmd_timeout;
105 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
106 msg_len > bp->max_req_len) {
107 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
109 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
110 memcpy(short_cmd_req, req, msg_len);
112 short_input.req_type = rte_cpu_to_le_16(req->req_type);
113 short_input.signature = rte_cpu_to_le_16(
114 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
115 short_input.size = rte_cpu_to_le_16(msg_len);
116 short_input.req_addr =
117 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
119 data = (uint32_t *)&short_input;
120 msg_len = sizeof(short_input);
122 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
125 /* Write request msg to hwrm channel */
126 for (i = 0; i < msg_len; i += 4) {
127 bar = (uint8_t *)bp->bar0 + bar_offset + i;
128 rte_write32(*data, bar);
132 /* Zero the rest of the request space */
133 for (; i < max_req_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + bar_offset + i;
138 /* Ring channel doorbell */
139 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
142 * Make sure the channel doorbell ring command complete before
143 * reading the response to avoid getting stale or invalid
148 /* Poll for the valid bit */
149 for (i = 0; i < timeout; i++) {
150 /* Sanity check on the resp->resp_len */
152 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
153 /* Last byte of resp contains the valid key */
154 valid = (uint8_t *)resp + resp->resp_len - 1;
155 if (*valid == HWRM_RESP_VALID_KEY)
162 /* Suppress VER_GET timeout messages during reset recovery */
163 if (bp->flags & BNXT_FLAG_FW_RESET &&
164 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
168 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
169 req->req_type, req->seq_id);
176 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
177 * spinlock, and does initial processing.
179 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
180 * releases the spinlock only if it returns. If the regular int return codes
181 * are not used by the function, HWRM_CHECK_RESULT() should not be used
182 * directly, rather it should be copied and modified to suit the function.
184 * HWRM_UNLOCK() must be called after all response processing is completed.
186 #define HWRM_PREP(req, type, kong) do { \
187 rte_spinlock_lock(&bp->hwrm_lock); \
188 if (bp->hwrm_cmd_resp_addr == NULL) { \
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 (req)->req_type = rte_cpu_to_le_16(type); \
194 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
195 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
197 (req)->target_id = rte_cpu_to_le_16(0xffff); \
198 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
219 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
221 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
223 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
225 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
231 if (resp->error_code) { \
232 rc = rte_le_to_cpu_16(resp->error_code); \
233 if (resp->resp_len >= 16) { \
234 struct hwrm_err_output *tmp_hwrm_err_op = \
237 "error %d:%d:%08x:%04x\n", \
238 rc, tmp_hwrm_err_op->cmd_err, \
240 tmp_hwrm_err_op->opaque_0), \
242 tmp_hwrm_err_op->opaque_1)); \
244 PMD_DRV_LOG(ERR, "error %d\n", rc); \
246 rte_spinlock_unlock(&bp->hwrm_lock); \
247 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
249 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
251 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
253 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
255 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
263 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
274 bool mailbox = BNXT_USE_CHIMP_MB;
275 struct input *req = msg;
276 struct output *resp = bp->hwrm_cmd_resp_addr;
279 mailbox = BNXT_USE_KONG(bp);
281 HWRM_PREP(req, msg_type, mailbox);
283 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
288 memcpy(resp_msg, resp, resp_len);
295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
299 uint32_t *tf_response_code,
303 uint32_t response_len)
306 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
307 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
308 bool mailbox = BNXT_USE_CHIMP_MB;
310 if (msg_len > sizeof(req.tf_req))
314 mailbox = BNXT_USE_KONG(bp);
316 HWRM_PREP(&req, HWRM_TF, mailbox);
317 /* Build request using the user supplied request payload.
318 * TLV request size is checked at build time against HWRM
319 * request max size, thus no checking required.
321 req.tf_type = tf_type;
322 req.tf_subtype = tf_subtype;
323 memcpy(req.tf_req, msg, msg_len);
325 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
328 /* Copy the resp to user provided response buffer */
329 if (response != NULL)
330 /* Post process response data. We need to copy only
331 * the 'payload' as the HWRM data structure really is
332 * HWRM header + msg header + payload and the TFLIB
333 * only provided a payload place holder.
335 if (response_len != 0) {
341 /* Extract the internal tflib response code */
342 *tf_response_code = resp->tf_resp_code;
348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
351 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
352 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
354 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
355 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
358 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
367 struct bnxt_vnic_info *vnic,
369 struct bnxt_vlan_table_entry *vlan_table)
372 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
376 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
379 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
380 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
382 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
383 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
384 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
385 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
387 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
388 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
390 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
391 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
392 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
393 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
394 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
395 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
398 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
399 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
400 req.vlan_tag_tbl_addr =
401 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
402 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
404 req.mask = rte_cpu_to_le_32(mask);
406 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
416 struct bnxt_vlan_antispoof_table_entry *vlan_table)
419 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
420 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
421 bp->hwrm_cmd_resp_addr;
424 * Older HWRM versions did not support this command, and the set_rx_mask
425 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
426 * removed from set_rx_mask call, and this command was added.
428 * This command is also present from 1.7.8.11 and higher,
431 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
432 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
433 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
438 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
439 req.fid = rte_cpu_to_le_16(fid);
441 req.vlan_tag_mask_tbl_addr =
442 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
443 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
445 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
454 struct bnxt_filter_info *filter)
457 struct bnxt_filter_info *l2_filter = filter;
458 struct bnxt_vnic_info *vnic = NULL;
459 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
460 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
462 if (filter->fw_l2_filter_id == UINT64_MAX)
465 if (filter->matching_l2_fltr_ptr)
466 l2_filter = filter->matching_l2_fltr_ptr;
468 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
469 filter, l2_filter, l2_filter->l2_ref_cnt);
471 if (l2_filter->l2_ref_cnt == 0)
474 if (l2_filter->l2_ref_cnt > 0)
475 l2_filter->l2_ref_cnt--;
477 if (l2_filter->l2_ref_cnt > 0)
480 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
482 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
489 filter->fw_l2_filter_id = UINT64_MAX;
490 if (l2_filter->l2_ref_cnt == 0) {
491 vnic = l2_filter->vnic;
493 STAILQ_REMOVE(&vnic->filter, l2_filter,
494 bnxt_filter_info, next);
495 bnxt_free_filter(bp, l2_filter);
502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
504 struct bnxt_filter_info *filter)
507 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
508 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
509 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
510 const struct rte_eth_vmdq_rx_conf *conf =
511 &dev_conf->rx_adv_conf.vmdq_rx_conf;
512 uint32_t enables = 0;
513 uint16_t j = dst_id - 1;
515 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
516 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
517 conf->pool_map[j].pools & (1UL << j)) {
519 "Add vlan %u to vmdq pool %u\n",
520 conf->pool_map[j].vlan_id, j);
522 filter->l2_ivlan = conf->pool_map[j].vlan_id;
524 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
525 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
528 if (filter->fw_l2_filter_id != UINT64_MAX)
529 bnxt_hwrm_clear_l2_filter(bp, filter);
531 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
533 req.flags = rte_cpu_to_le_32(filter->flags);
535 enables = filter->enables |
536 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
537 req.dst_id = rte_cpu_to_le_16(dst_id);
540 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
541 memcpy(req.l2_addr, filter->l2_addr,
544 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
545 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
548 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
549 req.l2_ovlan = filter->l2_ovlan;
551 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
552 req.l2_ivlan = filter->l2_ivlan;
554 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
555 req.l2_ovlan_mask = filter->l2_ovlan_mask;
557 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
558 req.l2_ivlan_mask = filter->l2_ivlan_mask;
559 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
560 req.src_id = rte_cpu_to_le_32(filter->src_id);
561 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
562 req.src_type = filter->src_type;
563 if (filter->pri_hint) {
564 req.pri_hint = filter->pri_hint;
565 req.l2_filter_id_hint =
566 rte_cpu_to_le_64(filter->l2_filter_id_hint);
569 req.enables = rte_cpu_to_le_32(enables);
571 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
575 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
576 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
579 filter->l2_ref_cnt++;
584 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
586 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
587 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
594 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
597 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
600 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
601 if (ptp->tx_tstamp_en)
602 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
605 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
606 req.flags = rte_cpu_to_le_32(flags);
607 req.enables = rte_cpu_to_le_32
608 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
609 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
611 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
617 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
620 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
621 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
622 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
627 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
629 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
631 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
635 if (!BNXT_CHIP_THOR(bp) &&
636 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
639 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
640 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
642 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
646 if (!BNXT_CHIP_THOR(bp)) {
647 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
648 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
649 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
650 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
651 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
652 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
653 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
654 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
655 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
656 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
657 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
658 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
659 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
660 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
661 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
662 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
663 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
664 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
673 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
676 struct hwrm_func_qcaps_input req = {.req_type = 0 };
677 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
678 uint16_t new_max_vfs;
682 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
684 req.fid = rte_cpu_to_le_16(0xffff);
686 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
690 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
691 flags = rte_le_to_cpu_32(resp->flags);
693 bp->pf->port_id = resp->port_id;
694 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
695 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
696 new_max_vfs = bp->pdev->max_vfs;
697 if (new_max_vfs != bp->pf->max_vfs) {
699 rte_free(bp->pf->vf_info);
700 bp->pf->vf_info = rte_malloc("bnxt_vf_info",
701 sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
702 bp->pf->max_vfs = new_max_vfs;
703 for (i = 0; i < new_max_vfs; i++) {
704 bp->pf->vf_info[i].fid =
705 bp->pf->first_vf_id + i;
706 bp->pf->vf_info[i].vlan_table =
707 rte_zmalloc("VF VLAN table",
710 if (bp->pf->vf_info[i].vlan_table == NULL)
712 "Fail to alloc VLAN table for VF %d\n",
716 bp->pf->vf_info[i].vlan_table);
717 bp->pf->vf_info[i].vlan_as_table =
718 rte_zmalloc("VF VLAN AS table",
721 if (bp->pf->vf_info[i].vlan_as_table == NULL)
723 "Alloc VLAN AS table for VF %d fail\n",
727 bp->pf->vf_info[i].vlan_as_table);
728 STAILQ_INIT(&bp->pf->vf_info[i].filter);
733 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
734 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
735 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
736 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
738 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
740 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
741 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
742 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
743 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
744 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
745 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
746 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
747 if (!BNXT_CHIP_THOR(bp))
748 bp->max_l2_ctx += bp->max_rx_em_flows;
749 /* TODO: For now, do not support VMDq/RFS on VFs. */
754 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
758 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
759 bp->max_l2_ctx, bp->max_vnics);
760 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
762 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
763 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
764 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
765 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
767 bnxt_hwrm_ptp_qcfg(bp);
771 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
772 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
774 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
775 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
776 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
779 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
780 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
782 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
783 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
790 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
794 rc = __bnxt_hwrm_func_qcaps(bp);
795 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
796 rc = bnxt_alloc_ctx_mem(bp);
800 rc = bnxt_hwrm_func_resc_qcaps(bp);
802 bp->flags |= BNXT_FLAG_NEW_RM;
806 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
807 * But the error can be ignored. Return success.
813 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
814 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
817 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
818 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
820 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
822 req.target_id = rte_cpu_to_le_16(0xffff);
824 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
828 if (rte_le_to_cpu_32(resp->flags) &
829 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
830 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
831 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
834 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
841 int bnxt_hwrm_func_reset(struct bnxt *bp)
844 struct hwrm_func_reset_input req = {.req_type = 0 };
845 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
847 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
849 req.enables = rte_cpu_to_le_32(0);
851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
859 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
863 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
864 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
866 if (bp->flags & BNXT_FLAG_REGISTERED)
869 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
870 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
871 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
872 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
874 /* PFs and trusted VFs should indicate the support of the
875 * Master capability on non Stingray platform
877 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
878 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
880 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
881 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
882 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
883 req.ver_maj = RTE_VER_YEAR;
884 req.ver_min = RTE_VER_MONTH;
885 req.ver_upd = RTE_VER_MINOR;
888 req.enables |= rte_cpu_to_le_32(
889 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
890 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
891 RTE_MIN(sizeof(req.vf_req_fwd),
892 sizeof(bp->pf->vf_req_fwd)));
895 * PF can sniff HWRM API issued by VF. This can be set up by
896 * linux driver and inherited by the DPDK PF driver. Clear
897 * this HWRM sniffer list in FW because DPDK PF driver does
900 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
903 req.flags = rte_cpu_to_le_32(flags);
905 req.async_event_fwd[0] |=
906 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
907 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
908 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
909 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
910 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
911 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
912 req.async_event_fwd[0] |=
913 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
914 req.async_event_fwd[1] |=
915 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
916 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
918 req.async_event_fwd[1] |=
919 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
921 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
925 flags = rte_le_to_cpu_32(resp->flags);
926 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
927 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
931 bp->flags |= BNXT_FLAG_REGISTERED;
936 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
938 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
941 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
944 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
949 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
950 struct hwrm_func_vf_cfg_input req = {0};
952 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
954 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
955 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
956 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
957 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
958 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
960 if (BNXT_HAS_RING_GRPS(bp)) {
961 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
962 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
965 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
966 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
967 AGG_RING_MULTIPLIER);
968 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
969 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
971 BNXT_NUM_ASYNC_CPR(bp));
972 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
973 if (bp->vf_resv_strategy ==
974 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
975 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
976 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
977 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
978 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
979 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
980 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
981 } else if (bp->vf_resv_strategy ==
982 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
983 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
984 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
988 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
989 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
990 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
991 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
992 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
993 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
995 if (test && BNXT_HAS_RING_GRPS(bp))
996 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
998 req.flags = rte_cpu_to_le_32(flags);
999 req.enables |= rte_cpu_to_le_32(enables);
1001 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1004 HWRM_CHECK_RESULT_SILENT();
1006 HWRM_CHECK_RESULT();
1012 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1015 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1016 struct hwrm_func_resource_qcaps_input req = {0};
1018 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1019 req.fid = rte_cpu_to_le_16(0xffff);
1021 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1023 HWRM_CHECK_RESULT_SILENT();
1026 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1027 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1028 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1029 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1030 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1031 /* func_resource_qcaps does not return max_rx_em_flows.
1032 * So use the value provided by func_qcaps.
1034 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1035 if (!BNXT_CHIP_THOR(bp))
1036 bp->max_l2_ctx += bp->max_rx_em_flows;
1037 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1038 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1040 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1041 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1042 if (bp->vf_resv_strategy >
1043 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1044 bp->vf_resv_strategy =
1045 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1051 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1054 struct hwrm_ver_get_input req = {.req_type = 0 };
1055 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1056 uint32_t fw_version;
1057 uint16_t max_resp_len;
1058 char type[RTE_MEMZONE_NAMESIZE];
1059 uint32_t dev_caps_cfg;
1061 bp->max_req_len = HWRM_MAX_REQ_LEN;
1062 bp->hwrm_cmd_timeout = timeout;
1063 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1065 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1066 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1067 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1069 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1071 if (bp->flags & BNXT_FLAG_FW_RESET)
1072 HWRM_CHECK_RESULT_SILENT();
1074 HWRM_CHECK_RESULT();
1076 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1077 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1078 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1079 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1080 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1081 (resp->hwrm_fw_min_8b << 16) |
1082 (resp->hwrm_fw_bld_8b << 8) |
1083 resp->hwrm_fw_rsvd_8b;
1084 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1085 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1087 fw_version = resp->hwrm_intf_maj_8b << 16;
1088 fw_version |= resp->hwrm_intf_min_8b << 8;
1089 fw_version |= resp->hwrm_intf_upd_8b;
1090 bp->hwrm_spec_code = fw_version;
1092 /* def_req_timeout value is in milliseconds */
1093 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1094 /* convert timeout to usec */
1095 bp->hwrm_cmd_timeout *= 1000;
1096 if (!bp->hwrm_cmd_timeout)
1097 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1099 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1100 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1105 if (bp->max_req_len > resp->max_req_win_len) {
1106 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1109 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1110 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1111 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1112 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1114 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1115 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1117 if (bp->max_resp_len != max_resp_len) {
1118 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1119 bp->pdev->addr.domain, bp->pdev->addr.bus,
1120 bp->pdev->addr.devid, bp->pdev->addr.function);
1122 rte_free(bp->hwrm_cmd_resp_addr);
1124 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1125 if (bp->hwrm_cmd_resp_addr == NULL) {
1129 bp->hwrm_cmd_resp_dma_addr =
1130 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1131 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1133 "Unable to map response buffer to physical memory.\n");
1137 bp->max_resp_len = max_resp_len;
1141 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1143 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1144 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1145 bp->flags |= BNXT_FLAG_SHORT_CMD;
1148 if (((dev_caps_cfg &
1149 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1151 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1152 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1153 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1154 bp->pdev->addr.domain, bp->pdev->addr.bus,
1155 bp->pdev->addr.devid, bp->pdev->addr.function);
1157 rte_free(bp->hwrm_short_cmd_req_addr);
1159 bp->hwrm_short_cmd_req_addr =
1160 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1161 if (bp->hwrm_short_cmd_req_addr == NULL) {
1165 bp->hwrm_short_cmd_req_dma_addr =
1166 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1167 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1168 rte_free(bp->hwrm_short_cmd_req_addr);
1170 "Unable to map buffer to physical memory.\n");
1176 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1177 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1178 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1181 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1182 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1184 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1185 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1186 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1190 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1191 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1192 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1201 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1204 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1205 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1207 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1210 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1213 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1215 HWRM_CHECK_RESULT();
1221 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1224 struct hwrm_port_phy_cfg_input req = {0};
1225 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1226 uint32_t enables = 0;
1228 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1230 if (conf->link_up) {
1231 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1232 if (bp->link_info->auto_mode && conf->link_speed) {
1233 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1234 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1237 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1238 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1239 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1241 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1242 * any auto mode, even "none".
1244 if (!conf->link_speed) {
1245 /* No speeds specified. Enable AutoNeg - all speeds */
1247 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1249 /* AutoNeg - Advertise speeds specified. */
1250 if (conf->auto_link_speed_mask &&
1251 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1253 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1254 req.auto_link_speed_mask =
1255 conf->auto_link_speed_mask;
1257 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1260 req.auto_duplex = conf->duplex;
1261 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1262 req.auto_pause = conf->auto_pause;
1263 req.force_pause = conf->force_pause;
1264 /* Set force_pause if there is no auto or if there is a force */
1265 if (req.auto_pause && !req.force_pause)
1266 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1268 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1270 req.enables = rte_cpu_to_le_32(enables);
1273 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1274 PMD_DRV_LOG(INFO, "Force Link Down\n");
1277 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1279 HWRM_CHECK_RESULT();
1285 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1286 struct bnxt_link_info *link_info)
1289 struct hwrm_port_phy_qcfg_input req = {0};
1290 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1292 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1294 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1296 HWRM_CHECK_RESULT();
1298 link_info->phy_link_status = resp->link;
1299 link_info->link_up =
1300 (link_info->phy_link_status ==
1301 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1302 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1303 link_info->duplex = resp->duplex_cfg;
1304 link_info->pause = resp->pause;
1305 link_info->auto_pause = resp->auto_pause;
1306 link_info->force_pause = resp->force_pause;
1307 link_info->auto_mode = resp->auto_mode;
1308 link_info->phy_type = resp->phy_type;
1309 link_info->media_type = resp->media_type;
1311 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1312 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1313 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1314 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1315 link_info->phy_ver[0] = resp->phy_maj;
1316 link_info->phy_ver[1] = resp->phy_min;
1317 link_info->phy_ver[2] = resp->phy_bld;
1321 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1322 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1323 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1324 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1325 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1326 link_info->auto_link_speed_mask);
1327 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1328 link_info->force_link_speed);
1333 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1336 struct hwrm_port_phy_qcaps_input req = {0};
1337 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1339 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1342 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1344 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1346 HWRM_CHECK_RESULT();
1348 bp->port_cnt = resp->port_cnt;
1355 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1359 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1360 if (bp->tx_cos_queue[i].profile ==
1361 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1362 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1369 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1373 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1374 if (bp->tx_cos_queue[i].profile !=
1375 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1376 bp->tx_cos_queue[i].id !=
1377 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1378 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1384 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1387 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1388 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1389 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1393 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1395 req.flags = rte_cpu_to_le_32(dir);
1396 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1397 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1398 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1400 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1401 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1403 HWRM_CHECK_RESULT();
1405 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1406 GET_TX_QUEUE_INFO(0);
1407 GET_TX_QUEUE_INFO(1);
1408 GET_TX_QUEUE_INFO(2);
1409 GET_TX_QUEUE_INFO(3);
1410 GET_TX_QUEUE_INFO(4);
1411 GET_TX_QUEUE_INFO(5);
1412 GET_TX_QUEUE_INFO(6);
1413 GET_TX_QUEUE_INFO(7);
1415 GET_RX_QUEUE_INFO(0);
1416 GET_RX_QUEUE_INFO(1);
1417 GET_RX_QUEUE_INFO(2);
1418 GET_RX_QUEUE_INFO(3);
1419 GET_RX_QUEUE_INFO(4);
1420 GET_RX_QUEUE_INFO(5);
1421 GET_RX_QUEUE_INFO(6);
1422 GET_RX_QUEUE_INFO(7);
1427 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1430 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1431 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1435 /* iterate and find the COSq profile to use for Tx */
1436 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1437 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1438 if (bp->tx_cos_queue[i].id != 0xff)
1439 bp->tx_cosq_id[j++] =
1440 bp->tx_cos_queue[i].id;
1443 /* When CoS classification is disabled, for normal NIC
1444 * operations, ideally we should look to use LOSSY.
1445 * If not found, fallback to the first valid profile
1447 if (!bnxt_find_lossy_profile(bp))
1448 bnxt_find_first_valid_profile(bp);
1453 bp->max_tc = resp->max_configurable_queues;
1454 bp->max_lltc = resp->max_configurable_lossless_queues;
1455 if (bp->max_tc > BNXT_MAX_QUEUE)
1456 bp->max_tc = BNXT_MAX_QUEUE;
1457 bp->max_q = bp->max_tc;
1459 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1460 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1468 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1469 struct bnxt_ring *ring,
1470 uint32_t ring_type, uint32_t map_index,
1471 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1472 uint16_t tx_cosq_id)
1475 uint32_t enables = 0;
1476 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1477 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1478 struct rte_mempool *mb_pool;
1479 uint16_t rx_buf_size;
1481 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1483 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1484 req.fbo = rte_cpu_to_le_32(0);
1485 /* Association of ring index with doorbell index */
1486 req.logical_id = rte_cpu_to_le_16(map_index);
1487 req.length = rte_cpu_to_le_32(ring->ring_size);
1489 switch (ring_type) {
1490 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1491 req.ring_type = ring_type;
1492 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1493 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1494 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1495 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1497 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1499 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1500 req.ring_type = ring_type;
1501 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1502 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1503 if (BNXT_CHIP_THOR(bp)) {
1504 mb_pool = bp->rx_queues[0]->mb_pool;
1505 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1506 RTE_PKTMBUF_HEADROOM;
1507 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1508 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1510 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1512 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1514 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1516 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1517 req.ring_type = ring_type;
1518 if (BNXT_HAS_NQ(bp)) {
1519 /* Association of cp ring with nq */
1520 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1522 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1524 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1526 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1527 req.ring_type = ring_type;
1528 req.page_size = BNXT_PAGE_SHFT;
1529 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1531 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1532 req.ring_type = ring_type;
1533 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1535 mb_pool = bp->rx_queues[0]->mb_pool;
1536 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1537 RTE_PKTMBUF_HEADROOM;
1538 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1539 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1541 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1542 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1543 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1544 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1547 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1552 req.enables = rte_cpu_to_le_32(enables);
1554 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1556 if (rc || resp->error_code) {
1557 if (rc == 0 && resp->error_code)
1558 rc = rte_le_to_cpu_16(resp->error_code);
1559 switch (ring_type) {
1560 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1562 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1565 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1567 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1570 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1572 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1576 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1578 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1581 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1583 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1587 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1593 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1598 int bnxt_hwrm_ring_free(struct bnxt *bp,
1599 struct bnxt_ring *ring, uint32_t ring_type)
1602 struct hwrm_ring_free_input req = {.req_type = 0 };
1603 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1605 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1607 req.ring_type = ring_type;
1608 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1610 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1612 if (rc || resp->error_code) {
1613 if (rc == 0 && resp->error_code)
1614 rc = rte_le_to_cpu_16(resp->error_code);
1617 switch (ring_type) {
1618 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1619 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1622 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1623 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1626 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1627 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1630 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1632 "hwrm_ring_free nq failed. rc:%d\n", rc);
1634 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1636 "hwrm_ring_free agg failed. rc:%d\n", rc);
1639 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1647 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1650 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1651 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1653 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1655 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1656 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1657 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1658 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1660 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1662 HWRM_CHECK_RESULT();
1664 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1671 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1674 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1675 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1677 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1679 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1681 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1683 HWRM_CHECK_RESULT();
1686 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1690 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1693 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1694 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1696 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1699 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1701 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1703 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1705 HWRM_CHECK_RESULT();
1711 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1712 unsigned int idx __rte_unused)
1715 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1716 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1718 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1720 req.update_period_ms = rte_cpu_to_le_32(0);
1722 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1724 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1726 HWRM_CHECK_RESULT();
1728 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1735 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1736 unsigned int idx __rte_unused)
1739 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1740 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1742 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1744 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1746 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1748 HWRM_CHECK_RESULT();
1754 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1757 struct hwrm_vnic_alloc_input req = { 0 };
1758 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1760 if (!BNXT_HAS_RING_GRPS(bp))
1761 goto skip_ring_grps;
1763 /* map ring groups to this vnic */
1764 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1765 vnic->start_grp_id, vnic->end_grp_id);
1766 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1767 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1769 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1770 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1771 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1772 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1775 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1776 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1778 if (vnic->func_default)
1780 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1781 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1783 HWRM_CHECK_RESULT();
1785 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1787 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1791 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1792 struct bnxt_vnic_info *vnic,
1793 struct bnxt_plcmodes_cfg *pmode)
1796 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1797 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1799 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1801 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1803 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1805 HWRM_CHECK_RESULT();
1807 pmode->flags = rte_le_to_cpu_32(resp->flags);
1808 /* dflt_vnic bit doesn't exist in the _cfg command */
1809 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1810 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1811 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1812 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1819 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1820 struct bnxt_vnic_info *vnic,
1821 struct bnxt_plcmodes_cfg *pmode)
1824 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1825 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1827 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1828 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1832 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1834 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1835 req.flags = rte_cpu_to_le_32(pmode->flags);
1836 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1837 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1838 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1839 req.enables = rte_cpu_to_le_32(
1840 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1841 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1842 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1845 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1847 HWRM_CHECK_RESULT();
1853 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1856 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1857 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1858 struct bnxt_plcmodes_cfg pmodes = { 0 };
1859 uint32_t ctx_enable_flag = 0;
1860 uint32_t enables = 0;
1862 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1863 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1867 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1871 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1873 if (BNXT_CHIP_THOR(bp)) {
1874 int dflt_rxq = vnic->start_grp_id;
1875 struct bnxt_rx_ring_info *rxr;
1876 struct bnxt_cp_ring_info *cpr;
1877 struct bnxt_rx_queue *rxq;
1881 * The first active receive ring is used as the VNIC
1882 * default receive ring. If there are no active receive
1883 * rings (all corresponding receive queues are stopped),
1884 * the first receive ring is used.
1886 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1887 rxq = bp->eth_dev->data->rx_queues[i];
1888 if (rxq->rx_started) {
1894 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1898 req.default_rx_ring_id =
1899 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1900 req.default_cmpl_ring_id =
1901 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1902 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1903 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1907 /* Only RSS support for now TBD: COS & LB */
1908 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1909 if (vnic->lb_rule != 0xffff)
1910 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1911 if (vnic->cos_rule != 0xffff)
1912 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1913 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1914 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1915 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1917 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1918 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1919 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1922 enables |= ctx_enable_flag;
1923 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1924 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1925 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1926 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1929 req.enables = rte_cpu_to_le_32(enables);
1930 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1931 req.mru = rte_cpu_to_le_16(vnic->mru);
1932 /* Configure default VNIC only once. */
1933 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1935 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1936 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1938 if (vnic->vlan_strip)
1940 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1943 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1944 if (vnic->roce_dual)
1945 req.flags |= rte_cpu_to_le_32(
1946 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1947 if (vnic->roce_only)
1948 req.flags |= rte_cpu_to_le_32(
1949 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1950 if (vnic->rss_dflt_cr)
1951 req.flags |= rte_cpu_to_le_32(
1952 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1954 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1956 HWRM_CHECK_RESULT();
1959 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1964 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1968 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1969 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1971 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1972 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1975 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1978 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1979 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1980 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1982 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1984 HWRM_CHECK_RESULT();
1986 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1987 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1988 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1989 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1990 vnic->mru = rte_le_to_cpu_16(resp->mru);
1991 vnic->func_default = rte_le_to_cpu_32(
1992 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1993 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1994 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1995 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1996 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1997 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1998 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1999 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
2000 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
2001 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2002 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2009 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2010 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2014 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2015 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2016 bp->hwrm_cmd_resp_addr;
2018 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2020 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2021 HWRM_CHECK_RESULT();
2023 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2024 if (!BNXT_HAS_RING_GRPS(bp))
2025 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2026 else if (ctx_idx == 0)
2027 vnic->rss_rule = ctx_id;
2035 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2036 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2039 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2040 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2041 bp->hwrm_cmd_resp_addr;
2043 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2044 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2047 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2049 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2051 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2053 HWRM_CHECK_RESULT();
2059 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2063 if (BNXT_CHIP_THOR(bp)) {
2066 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2067 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2069 vnic->fw_grp_ids[j]);
2070 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2072 vnic->num_lb_ctxts = 0;
2074 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2075 vnic->rss_rule = INVALID_HW_RING_ID;
2081 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2084 struct hwrm_vnic_free_input req = {.req_type = 0 };
2085 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2087 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2088 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2092 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2094 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2096 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2098 HWRM_CHECK_RESULT();
2101 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2102 /* Configure default VNIC again if necessary. */
2103 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2104 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2110 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2114 int nr_ctxs = vnic->num_lb_ctxts;
2115 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2116 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2118 for (i = 0; i < nr_ctxs; i++) {
2119 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2121 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2122 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2123 req.hash_mode_flags = vnic->hash_mode;
2125 req.hash_key_tbl_addr =
2126 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2128 req.ring_grp_tbl_addr =
2129 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2130 i * HW_HASH_INDEX_SIZE);
2131 req.ring_table_pair_index = i;
2132 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2134 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2137 HWRM_CHECK_RESULT();
2144 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2145 struct bnxt_vnic_info *vnic)
2148 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2149 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2151 if (!vnic->rss_table)
2154 if (BNXT_CHIP_THOR(bp))
2155 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2157 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2159 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2160 req.hash_mode_flags = vnic->hash_mode;
2162 req.ring_grp_tbl_addr =
2163 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2164 req.hash_key_tbl_addr =
2165 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2166 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2167 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2169 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2171 HWRM_CHECK_RESULT();
2177 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2178 struct bnxt_vnic_info *vnic)
2181 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2182 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2185 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2186 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2190 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2192 req.flags = rte_cpu_to_le_32(
2193 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2195 req.enables = rte_cpu_to_le_32(
2196 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2198 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2199 size -= RTE_PKTMBUF_HEADROOM;
2200 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2202 req.jumbo_thresh = rte_cpu_to_le_16(size);
2203 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2205 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2207 HWRM_CHECK_RESULT();
2213 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2214 struct bnxt_vnic_info *vnic, bool enable)
2217 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2218 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2220 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2222 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2226 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2227 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2231 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2234 req.enables = rte_cpu_to_le_32(
2235 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2236 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2237 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2238 req.flags = rte_cpu_to_le_32(
2239 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2240 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2241 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2242 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2243 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2244 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2245 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2246 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2247 req.min_agg_len = rte_cpu_to_le_32(512);
2249 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2251 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2253 HWRM_CHECK_RESULT();
2259 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2261 struct hwrm_func_cfg_input req = {0};
2262 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2265 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2266 req.enables = rte_cpu_to_le_32(
2267 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2268 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2269 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2271 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2273 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2274 HWRM_CHECK_RESULT();
2277 bp->pf->vf_info[vf].random_mac = false;
2282 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2286 struct hwrm_func_qstats_input req = {.req_type = 0};
2287 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2289 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2291 req.fid = rte_cpu_to_le_16(fid);
2293 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2295 HWRM_CHECK_RESULT();
2298 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2305 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2306 struct rte_eth_stats *stats,
2307 struct hwrm_func_qstats_output *func_qstats)
2310 struct hwrm_func_qstats_input req = {.req_type = 0};
2311 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2313 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2315 req.fid = rte_cpu_to_le_16(fid);
2317 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2319 HWRM_CHECK_RESULT();
2321 memcpy(func_qstats, resp,
2322 sizeof(struct hwrm_func_qstats_output));
2327 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2328 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2329 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2330 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2331 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2332 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2334 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2335 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2336 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2337 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2338 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2339 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2341 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2342 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2343 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2351 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2354 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2355 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2357 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2359 req.fid = rte_cpu_to_le_16(fid);
2361 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2363 HWRM_CHECK_RESULT();
2369 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2374 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2375 struct bnxt_tx_queue *txq;
2376 struct bnxt_rx_queue *rxq;
2377 struct bnxt_cp_ring_info *cpr;
2379 if (i >= bp->rx_cp_nr_rings) {
2380 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2383 rxq = bp->rx_queues[i];
2387 rc = bnxt_hwrm_stat_clear(bp, cpr);
2395 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2399 struct bnxt_cp_ring_info *cpr;
2401 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2403 if (i >= bp->rx_cp_nr_rings) {
2404 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2406 cpr = bp->rx_queues[i]->cp_ring;
2407 if (BNXT_HAS_RING_GRPS(bp))
2408 bp->grp_info[i].fw_stats_ctx = -1;
2410 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2411 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2412 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2420 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2425 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2426 struct bnxt_tx_queue *txq;
2427 struct bnxt_rx_queue *rxq;
2428 struct bnxt_cp_ring_info *cpr;
2430 if (i >= bp->rx_cp_nr_rings) {
2431 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2434 rxq = bp->rx_queues[i];
2438 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2447 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2452 if (!BNXT_HAS_RING_GRPS(bp))
2455 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2457 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2460 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2468 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2470 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2472 bnxt_hwrm_ring_free(bp, cp_ring,
2473 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2474 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2475 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2476 sizeof(*cpr->cp_desc_ring));
2477 cpr->cp_raw_cons = 0;
2481 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2483 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2485 bnxt_hwrm_ring_free(bp, cp_ring,
2486 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2487 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2488 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2489 sizeof(*cpr->cp_desc_ring));
2490 cpr->cp_raw_cons = 0;
2494 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2496 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2497 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2498 struct bnxt_ring *ring = rxr->rx_ring_struct;
2499 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2501 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2502 bnxt_hwrm_ring_free(bp, ring,
2503 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2504 ring->fw_ring_id = INVALID_HW_RING_ID;
2505 if (BNXT_HAS_RING_GRPS(bp))
2506 bp->grp_info[queue_index].rx_fw_ring_id =
2509 ring = rxr->ag_ring_struct;
2510 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2511 bnxt_hwrm_ring_free(bp, ring,
2512 BNXT_CHIP_THOR(bp) ?
2513 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2514 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2515 if (BNXT_HAS_RING_GRPS(bp))
2516 bp->grp_info[queue_index].ag_fw_ring_id =
2519 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2520 bnxt_free_cp_ring(bp, cpr);
2522 if (BNXT_HAS_RING_GRPS(bp))
2523 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2527 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2531 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2532 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2533 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2534 struct bnxt_ring *ring = txr->tx_ring_struct;
2535 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2537 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2538 bnxt_hwrm_ring_free(bp, ring,
2539 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2540 ring->fw_ring_id = INVALID_HW_RING_ID;
2541 memset(txr->tx_desc_ring, 0,
2542 txr->tx_ring_struct->ring_size *
2543 sizeof(*txr->tx_desc_ring));
2544 memset(txr->tx_buf_ring, 0,
2545 txr->tx_ring_struct->ring_size *
2546 sizeof(*txr->tx_buf_ring));
2550 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2551 bnxt_free_cp_ring(bp, cpr);
2552 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2556 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2557 bnxt_free_hwrm_rx_ring(bp, i);
2562 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2567 if (!BNXT_HAS_RING_GRPS(bp))
2570 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2571 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2579 * HWRM utility functions
2582 void bnxt_free_hwrm_resources(struct bnxt *bp)
2584 /* Release memzone */
2585 rte_free(bp->hwrm_cmd_resp_addr);
2586 rte_free(bp->hwrm_short_cmd_req_addr);
2587 bp->hwrm_cmd_resp_addr = NULL;
2588 bp->hwrm_short_cmd_req_addr = NULL;
2589 bp->hwrm_cmd_resp_dma_addr = 0;
2590 bp->hwrm_short_cmd_req_dma_addr = 0;
2593 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2595 struct rte_pci_device *pdev = bp->pdev;
2596 char type[RTE_MEMZONE_NAMESIZE];
2598 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2599 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2600 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2601 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2602 if (bp->hwrm_cmd_resp_addr == NULL)
2604 bp->hwrm_cmd_resp_dma_addr =
2605 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2606 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2608 "unable to map response address to physical memory\n");
2611 rte_spinlock_init(&bp->hwrm_lock);
2617 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2619 struct bnxt_filter_info *filter;
2622 STAILQ_FOREACH(filter, &vnic->filter, next) {
2623 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2624 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2625 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2626 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2627 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2628 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2629 bnxt_free_filter(bp, filter);
2635 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2637 struct bnxt_filter_info *filter;
2638 struct rte_flow *flow;
2641 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2642 flow = STAILQ_FIRST(&vnic->flow_list);
2643 filter = flow->filter;
2644 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2645 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2646 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2647 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2648 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2649 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2651 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2657 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2659 struct bnxt_filter_info *filter;
2662 STAILQ_FOREACH(filter, &vnic->filter, next) {
2663 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2664 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2666 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2667 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2670 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2679 bnxt_free_tunnel_ports(struct bnxt *bp)
2681 if (bp->vxlan_port_cnt)
2682 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2683 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2685 if (bp->geneve_port_cnt)
2686 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2687 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2688 bp->geneve_port = 0;
2691 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2695 if (bp->vnic_info == NULL)
2699 * Cleanup VNICs in reverse order, to make sure the L2 filter
2700 * from vnic0 is last to be cleaned up.
2702 for (i = bp->max_vnics - 1; i >= 0; i--) {
2703 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2705 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2708 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2710 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2712 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2714 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2716 bnxt_hwrm_vnic_free(bp, vnic);
2718 rte_free(vnic->fw_grp_ids);
2720 /* Ring resources */
2721 bnxt_free_all_hwrm_rings(bp);
2722 bnxt_free_all_hwrm_ring_grps(bp);
2723 bnxt_free_all_hwrm_stat_ctxs(bp);
2724 bnxt_free_tunnel_ports(bp);
2727 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2729 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2731 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2732 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2734 switch (conf_link_speed) {
2735 case ETH_LINK_SPEED_10M_HD:
2736 case ETH_LINK_SPEED_100M_HD:
2738 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2740 return hw_link_duplex;
2743 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2745 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2748 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2750 uint16_t eth_link_speed = 0;
2752 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2753 return ETH_LINK_SPEED_AUTONEG;
2755 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2756 case ETH_LINK_SPEED_100M:
2757 case ETH_LINK_SPEED_100M_HD:
2760 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2762 case ETH_LINK_SPEED_1G:
2764 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2766 case ETH_LINK_SPEED_2_5G:
2768 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2770 case ETH_LINK_SPEED_10G:
2772 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2774 case ETH_LINK_SPEED_20G:
2776 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2778 case ETH_LINK_SPEED_25G:
2780 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2782 case ETH_LINK_SPEED_40G:
2784 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2786 case ETH_LINK_SPEED_50G:
2788 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2790 case ETH_LINK_SPEED_100G:
2792 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2794 case ETH_LINK_SPEED_200G:
2796 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2800 "Unsupported link speed %d; default to AUTO\n",
2804 return eth_link_speed;
2807 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2808 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2809 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2810 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2811 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2813 static int bnxt_validate_link_speed(struct bnxt *bp)
2815 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2816 uint16_t port_id = bp->eth_dev->data->port_id;
2817 uint32_t link_speed_capa;
2820 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2823 link_speed_capa = bnxt_get_speed_capabilities(bp);
2825 if (link_speed & ETH_LINK_SPEED_FIXED) {
2826 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2828 if (one_speed & (one_speed - 1)) {
2830 "Invalid advertised speeds (%u) for port %u\n",
2831 link_speed, port_id);
2834 if ((one_speed & link_speed_capa) != one_speed) {
2836 "Unsupported advertised speed (%u) for port %u\n",
2837 link_speed, port_id);
2841 if (!(link_speed & link_speed_capa)) {
2843 "Unsupported advertised speeds (%u) for port %u\n",
2844 link_speed, port_id);
2852 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2856 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2857 if (bp->link_info->support_speeds)
2858 return bp->link_info->support_speeds;
2859 link_speed = BNXT_SUPPORTED_SPEEDS;
2862 if (link_speed & ETH_LINK_SPEED_100M)
2863 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2864 if (link_speed & ETH_LINK_SPEED_100M_HD)
2865 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2866 if (link_speed & ETH_LINK_SPEED_1G)
2867 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2868 if (link_speed & ETH_LINK_SPEED_2_5G)
2869 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2870 if (link_speed & ETH_LINK_SPEED_10G)
2871 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2872 if (link_speed & ETH_LINK_SPEED_20G)
2873 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2874 if (link_speed & ETH_LINK_SPEED_25G)
2875 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2876 if (link_speed & ETH_LINK_SPEED_40G)
2877 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2878 if (link_speed & ETH_LINK_SPEED_50G)
2879 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2880 if (link_speed & ETH_LINK_SPEED_100G)
2881 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2882 if (link_speed & ETH_LINK_SPEED_200G)
2883 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2887 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2889 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2891 switch (hw_link_speed) {
2892 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2893 eth_link_speed = ETH_SPEED_NUM_100M;
2895 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2896 eth_link_speed = ETH_SPEED_NUM_1G;
2898 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2899 eth_link_speed = ETH_SPEED_NUM_2_5G;
2901 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2902 eth_link_speed = ETH_SPEED_NUM_10G;
2904 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2905 eth_link_speed = ETH_SPEED_NUM_20G;
2907 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2908 eth_link_speed = ETH_SPEED_NUM_25G;
2910 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2911 eth_link_speed = ETH_SPEED_NUM_40G;
2913 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2914 eth_link_speed = ETH_SPEED_NUM_50G;
2916 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2917 eth_link_speed = ETH_SPEED_NUM_100G;
2919 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2920 eth_link_speed = ETH_SPEED_NUM_200G;
2922 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2924 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2928 return eth_link_speed;
2931 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2933 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2935 switch (hw_link_duplex) {
2936 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2937 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2939 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2941 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2942 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2945 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2949 return eth_link_duplex;
2952 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2955 struct bnxt_link_info *link_info = bp->link_info;
2957 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2960 "Get link config failed with rc %d\n", rc);
2963 if (link_info->link_speed)
2965 bnxt_parse_hw_link_speed(link_info->link_speed);
2967 link->link_speed = ETH_SPEED_NUM_NONE;
2968 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2969 link->link_status = link_info->link_up;
2970 link->link_autoneg = link_info->auto_mode ==
2971 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2972 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2977 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2980 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2981 struct bnxt_link_info link_req;
2982 uint16_t speed, autoneg;
2984 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2987 rc = bnxt_validate_link_speed(bp);
2991 memset(&link_req, 0, sizeof(link_req));
2992 link_req.link_up = link_up;
2996 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2997 if (BNXT_CHIP_THOR(bp) &&
2998 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2999 /* 40G is not supported as part of media auto detect.
3000 * The speed should be forced and autoneg disabled
3001 * to configure 40G speed.
3003 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3007 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
3008 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3009 /* Autoneg can be done only when the FW allows.
3010 * When user configures fixed speed of 40G and later changes to
3011 * any other speed, auto_link_speed/force_link_speed is still set
3012 * to 40G until link comes up at new speed.
3015 !(!BNXT_CHIP_THOR(bp) &&
3016 (bp->link_info->auto_link_speed ||
3017 bp->link_info->force_link_speed))) {
3018 link_req.phy_flags |=
3019 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3020 link_req.auto_link_speed_mask =
3021 bnxt_parse_eth_link_speed_mask(bp,
3022 dev_conf->link_speeds);
3024 if (bp->link_info->phy_type ==
3025 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3026 bp->link_info->phy_type ==
3027 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3028 bp->link_info->media_type ==
3029 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3030 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3034 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3035 /* If user wants a particular speed try that first. */
3037 link_req.link_speed = speed;
3038 else if (bp->link_info->force_link_speed)
3039 link_req.link_speed = bp->link_info->force_link_speed;
3041 link_req.link_speed = bp->link_info->auto_link_speed;
3043 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3044 link_req.auto_pause = bp->link_info->auto_pause;
3045 link_req.force_pause = bp->link_info->force_pause;
3048 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3051 "Set link config failed with rc %d\n", rc);
3059 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3061 struct hwrm_func_qcfg_input req = {0};
3062 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3065 bp->func_svif = BNXT_SVIF_INVALID;
3068 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3069 req.fid = rte_cpu_to_le_16(0xffff);
3071 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3073 HWRM_CHECK_RESULT();
3075 /* Hard Coded.. 0xfff VLAN ID mask */
3076 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3078 svif_info = rte_le_to_cpu_16(resp->svif_info);
3079 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3080 bp->func_svif = svif_info &
3081 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3083 flags = rte_le_to_cpu_16(resp->flags);
3084 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3085 bp->flags |= BNXT_FLAG_MULTI_HOST;
3088 !BNXT_VF_IS_TRUSTED(bp) &&
3089 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3090 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3091 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3092 } else if (BNXT_VF(bp) &&
3093 BNXT_VF_IS_TRUSTED(bp) &&
3094 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3095 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3096 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3100 *mtu = rte_le_to_cpu_16(resp->mtu);
3102 switch (resp->port_partition_type) {
3103 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3104 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3105 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3107 bp->flags |= BNXT_FLAG_NPAR_PF;
3110 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3119 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3121 struct hwrm_func_qcfg_input req = {0};
3122 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3125 if (!BNXT_VF_IS_TRUSTED(bp))
3131 bp->parent->fid = BNXT_PF_FID_INVALID;
3133 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3135 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3137 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3139 HWRM_CHECK_RESULT();
3141 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3142 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3143 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3144 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3146 /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3147 if (bp->parent->vnic == 0) {
3148 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3149 /* Use hard-coded values appropriate for current Wh+ fw. */
3150 if (bp->parent->fid == 2)
3151 bp->parent->vnic = 0x100;
3153 bp->parent->vnic = 1;
3161 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3162 uint16_t *vnic_id, uint16_t *svif)
3164 struct hwrm_func_qcfg_input req = {0};
3165 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3169 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3170 req.fid = rte_cpu_to_le_16(fid);
3172 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3174 HWRM_CHECK_RESULT();
3177 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3179 svif_info = rte_le_to_cpu_16(resp->svif_info);
3180 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3181 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3188 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3190 struct hwrm_port_mac_qcfg_input req = {0};
3191 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3192 uint16_t port_svif_info;
3195 bp->port_svif = BNXT_SVIF_INVALID;
3197 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3200 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3202 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3204 HWRM_CHECK_RESULT_SILENT();
3206 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3207 if (port_svif_info &
3208 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3209 bp->port_svif = port_svif_info &
3210 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3217 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3218 struct hwrm_func_qcaps_output *qcaps)
3220 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3221 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3222 sizeof(qcaps->mac_address));
3223 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3224 qcaps->max_rx_rings = fcfg->num_rx_rings;
3225 qcaps->max_tx_rings = fcfg->num_tx_rings;
3226 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3227 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3229 qcaps->first_vf_id = 0;
3230 qcaps->max_vnics = fcfg->num_vnics;
3231 qcaps->max_decap_records = 0;
3232 qcaps->max_encap_records = 0;
3233 qcaps->max_tx_wm_flows = 0;
3234 qcaps->max_tx_em_flows = 0;
3235 qcaps->max_rx_wm_flows = 0;
3236 qcaps->max_rx_em_flows = 0;
3237 qcaps->max_flow_id = 0;
3238 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3239 qcaps->max_sp_tx_rings = 0;
3240 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3243 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3245 struct hwrm_func_cfg_input req = {0};
3246 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3250 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3251 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3252 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3253 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3254 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3255 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3256 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3257 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3258 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3260 if (BNXT_HAS_RING_GRPS(bp)) {
3261 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3262 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3263 } else if (BNXT_HAS_NQ(bp)) {
3264 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3265 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3268 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3269 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3270 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3271 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3272 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3273 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3274 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3275 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3276 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3277 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3278 req.fid = rte_cpu_to_le_16(0xffff);
3279 req.enables = rte_cpu_to_le_32(enables);
3281 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3283 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3285 HWRM_CHECK_RESULT();
3291 static void populate_vf_func_cfg_req(struct bnxt *bp,
3292 struct hwrm_func_cfg_input *req,
3295 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3296 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3297 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3298 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3299 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3300 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3301 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3302 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3303 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3304 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3306 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3307 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3309 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3310 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3312 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3313 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3315 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3316 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3317 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3318 /* TODO: For now, do not support VMDq/RFS on VFs. */
3319 req->num_vnics = rte_cpu_to_le_16(1);
3320 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3324 static void add_random_mac_if_needed(struct bnxt *bp,
3325 struct hwrm_func_cfg_input *cfg_req,
3328 struct rte_ether_addr mac;
3330 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3333 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3335 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3336 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3337 bp->pf->vf_info[vf].random_mac = true;
3339 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3340 RTE_ETHER_ADDR_LEN);
3344 static int reserve_resources_from_vf(struct bnxt *bp,
3345 struct hwrm_func_cfg_input *cfg_req,
3348 struct hwrm_func_qcaps_input req = {0};
3349 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3352 /* Get the actual allocated values now */
3353 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3354 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3355 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3358 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3359 copy_func_cfg_to_qcaps(cfg_req, resp);
3360 } else if (resp->error_code) {
3361 rc = rte_le_to_cpu_16(resp->error_code);
3362 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3363 copy_func_cfg_to_qcaps(cfg_req, resp);
3366 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3367 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3368 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3369 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3370 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3371 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3373 * TODO: While not supporting VMDq with VFs, max_vnics is always
3374 * forced to 1 in this case
3376 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3377 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3384 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3386 struct hwrm_func_qcfg_input req = {0};
3387 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3390 /* Check for zero MAC address */
3391 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3392 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3393 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3394 HWRM_CHECK_RESULT();
3395 rc = rte_le_to_cpu_16(resp->vlan);
3402 static int update_pf_resource_max(struct bnxt *bp)
3404 struct hwrm_func_qcfg_input req = {0};
3405 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3408 /* And copy the allocated numbers into the pf struct */
3409 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3410 req.fid = rte_cpu_to_le_16(0xffff);
3411 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3412 HWRM_CHECK_RESULT();
3414 /* Only TX ring value reflects actual allocation? TODO */
3415 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3416 bp->pf->evb_mode = resp->evb_mode;
3423 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3428 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3432 rc = bnxt_hwrm_func_qcaps(bp);
3436 bp->pf->func_cfg_flags &=
3437 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3438 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3439 bp->pf->func_cfg_flags |=
3440 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3441 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3442 rc = __bnxt_hwrm_func_qcaps(bp);
3446 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3448 struct hwrm_func_cfg_input req = {0};
3449 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3456 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3460 rc = bnxt_hwrm_func_qcaps(bp);
3465 bp->pf->active_vfs = num_vfs;
3468 * First, configure the PF to only use one TX ring. This ensures that
3469 * there are enough rings for all VFs.
3471 * If we don't do this, when we call func_alloc() later, we will lock
3472 * extra rings to the PF that won't be available during func_cfg() of
3475 * This has been fixed with firmware versions above 20.6.54
3477 bp->pf->func_cfg_flags &=
3478 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3479 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3480 bp->pf->func_cfg_flags |=
3481 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3482 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3487 * Now, create and register a buffer to hold forwarded VF requests
3489 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3490 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3491 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3492 if (bp->pf->vf_req_buf == NULL) {
3496 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3497 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3498 for (i = 0; i < num_vfs; i++)
3499 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3500 (i * HWRM_MAX_REQ_LEN);
3502 rc = bnxt_hwrm_func_buf_rgtr(bp);
3506 populate_vf_func_cfg_req(bp, &req, num_vfs);
3508 bp->pf->active_vfs = 0;
3509 for (i = 0; i < num_vfs; i++) {
3510 add_random_mac_if_needed(bp, &req, i);
3512 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3513 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3514 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3515 rc = bnxt_hwrm_send_message(bp,
3520 /* Clear enable flag for next pass */
3521 req.enables &= ~rte_cpu_to_le_32(
3522 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3524 if (rc || resp->error_code) {
3526 "Failed to initizlie VF %d\n", i);
3528 "Not all VFs available. (%d, %d)\n",
3529 rc, resp->error_code);
3536 reserve_resources_from_vf(bp, &req, i);
3537 bp->pf->active_vfs++;
3538 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3542 * Now configure the PF to use "the rest" of the resources
3543 * We're using STD_TX_RING_MODE here though which will limit the TX
3544 * rings. This will allow QoS to function properly. Not setting this
3545 * will cause PF rings to break bandwidth settings.
3547 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3551 rc = update_pf_resource_max(bp);
3558 bnxt_hwrm_func_buf_unrgtr(bp);
3562 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3564 struct hwrm_func_cfg_input req = {0};
3565 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3568 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3570 req.fid = rte_cpu_to_le_16(0xffff);
3571 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3572 req.evb_mode = bp->pf->evb_mode;
3574 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3575 HWRM_CHECK_RESULT();
3581 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3582 uint8_t tunnel_type)
3584 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3585 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3588 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3589 req.tunnel_type = tunnel_type;
3590 req.tunnel_dst_port_val = port;
3591 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3592 HWRM_CHECK_RESULT();
3594 switch (tunnel_type) {
3595 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3596 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3597 bp->vxlan_port = port;
3599 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3600 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3601 bp->geneve_port = port;
3612 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3613 uint8_t tunnel_type)
3615 struct hwrm_tunnel_dst_port_free_input req = {0};
3616 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3619 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3621 req.tunnel_type = tunnel_type;
3622 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3623 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3625 HWRM_CHECK_RESULT();
3631 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3634 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3635 struct hwrm_func_cfg_input req = {0};
3638 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3640 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3641 req.flags = rte_cpu_to_le_32(flags);
3642 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3644 HWRM_CHECK_RESULT();
3650 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3652 uint32_t *flag = flagp;
3654 vnic->flags = *flag;
3657 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3659 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3662 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3665 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3666 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3668 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3670 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3671 req.req_buf_page_size = rte_cpu_to_le_16(
3672 page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3673 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3674 req.req_buf_page_addr0 =
3675 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3676 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3678 "unable to map buffer address to physical memory\n");
3682 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3684 HWRM_CHECK_RESULT();
3690 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3693 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3694 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3696 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3699 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3701 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3703 HWRM_CHECK_RESULT();
3709 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3711 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3712 struct hwrm_func_cfg_input req = {0};
3715 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3717 req.fid = rte_cpu_to_le_16(0xffff);
3718 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3719 req.enables = rte_cpu_to_le_32(
3720 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3721 req.async_event_cr = rte_cpu_to_le_16(
3722 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3723 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3725 HWRM_CHECK_RESULT();
3731 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3733 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3734 struct hwrm_func_vf_cfg_input req = {0};
3737 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3739 req.enables = rte_cpu_to_le_32(
3740 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3741 req.async_event_cr = rte_cpu_to_le_16(
3742 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3743 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3745 HWRM_CHECK_RESULT();
3751 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3753 struct hwrm_func_cfg_input req = {0};
3754 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3755 uint16_t dflt_vlan, fid;
3756 uint32_t func_cfg_flags;
3759 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3762 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3763 fid = bp->pf->vf_info[vf].fid;
3764 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3766 fid = rte_cpu_to_le_16(0xffff);
3767 func_cfg_flags = bp->pf->func_cfg_flags;
3768 dflt_vlan = bp->vlan;
3771 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3772 req.fid = rte_cpu_to_le_16(fid);
3773 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3774 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3776 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3778 HWRM_CHECK_RESULT();
3784 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3785 uint16_t max_bw, uint16_t enables)
3787 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3788 struct hwrm_func_cfg_input req = {0};
3791 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3793 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3794 req.enables |= rte_cpu_to_le_32(enables);
3795 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3796 req.max_bw = rte_cpu_to_le_32(max_bw);
3797 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3799 HWRM_CHECK_RESULT();
3805 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3807 struct hwrm_func_cfg_input req = {0};
3808 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3811 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3813 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3814 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3815 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3816 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3818 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3820 HWRM_CHECK_RESULT();
3826 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3831 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3833 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3838 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3839 void *encaped, size_t ec_size)
3842 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3843 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3845 if (ec_size > sizeof(req.encap_request))
3848 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3850 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3851 memcpy(req.encap_request, encaped, ec_size);
3853 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3855 HWRM_CHECK_RESULT();
3861 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3862 struct rte_ether_addr *mac)
3864 struct hwrm_func_qcfg_input req = {0};
3865 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3868 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3870 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3871 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3873 HWRM_CHECK_RESULT();
3875 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3882 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3883 void *encaped, size_t ec_size)
3886 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3887 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3889 if (ec_size > sizeof(req.encap_request))
3892 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3894 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3895 memcpy(req.encap_request, encaped, ec_size);
3897 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3899 HWRM_CHECK_RESULT();
3905 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3906 struct rte_eth_stats *stats, uint8_t rx)
3909 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3910 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3912 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3914 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3916 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3918 HWRM_CHECK_RESULT();
3921 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3922 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3923 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3924 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3925 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3926 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3927 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3928 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3930 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3931 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3932 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3933 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3934 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3935 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3943 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3945 struct hwrm_port_qstats_input req = {0};
3946 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3947 struct bnxt_pf_info *pf = bp->pf;
3950 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3952 req.port_id = rte_cpu_to_le_16(pf->port_id);
3953 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3954 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3955 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3957 HWRM_CHECK_RESULT();
3963 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3965 struct hwrm_port_clr_stats_input req = {0};
3966 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3967 struct bnxt_pf_info *pf = bp->pf;
3970 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3971 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3972 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3975 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3977 req.port_id = rte_cpu_to_le_16(pf->port_id);
3978 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3980 HWRM_CHECK_RESULT();
3986 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3988 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3989 struct hwrm_port_led_qcaps_input req = {0};
3995 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3996 req.port_id = bp->pf->port_id;
3997 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3999 HWRM_CHECK_RESULT();
4001 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4004 bp->leds->num_leds = resp->num_leds;
4005 memcpy(bp->leds, &resp->led0_id,
4006 sizeof(bp->leds[0]) * bp->leds->num_leds);
4007 for (i = 0; i < bp->leds->num_leds; i++) {
4008 struct bnxt_led_info *led = &bp->leds[i];
4010 uint16_t caps = led->led_state_caps;
4012 if (!led->led_group_id ||
4013 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4014 bp->leds->num_leds = 0;
4025 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4027 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4028 struct hwrm_port_led_cfg_input req = {0};
4029 struct bnxt_led_cfg *led_cfg;
4030 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4031 uint16_t duration = 0;
4034 if (!bp->leds->num_leds || BNXT_VF(bp))
4037 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4040 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4041 duration = rte_cpu_to_le_16(500);
4043 req.port_id = bp->pf->port_id;
4044 req.num_leds = bp->leds->num_leds;
4045 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4046 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4047 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4048 led_cfg->led_id = bp->leds[i].led_id;
4049 led_cfg->led_state = led_state;
4050 led_cfg->led_blink_on = duration;
4051 led_cfg->led_blink_off = duration;
4052 led_cfg->led_group_id = bp->leds[i].led_group_id;
4055 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4057 HWRM_CHECK_RESULT();
4063 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4067 struct hwrm_nvm_get_dir_info_input req = {0};
4068 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4070 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4072 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4074 HWRM_CHECK_RESULT();
4076 *entries = rte_le_to_cpu_32(resp->entries);
4077 *length = rte_le_to_cpu_32(resp->entry_length);
4083 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4086 uint32_t dir_entries;
4087 uint32_t entry_length;
4090 rte_iova_t dma_handle;
4091 struct hwrm_nvm_get_dir_entries_input req = {0};
4092 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4094 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4098 *data++ = dir_entries;
4099 *data++ = entry_length;
4101 memset(data, 0xff, len);
4103 buflen = dir_entries * entry_length;
4104 buf = rte_malloc("nvm_dir", buflen, 0);
4107 dma_handle = rte_malloc_virt2iova(buf);
4108 if (dma_handle == RTE_BAD_IOVA) {
4110 "unable to map response address to physical memory\n");
4113 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4114 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4115 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4118 memcpy(data, buf, len > buflen ? buflen : len);
4121 HWRM_CHECK_RESULT();
4127 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4128 uint32_t offset, uint32_t length,
4133 rte_iova_t dma_handle;
4134 struct hwrm_nvm_read_input req = {0};
4135 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4137 buf = rte_malloc("nvm_item", length, 0);
4141 dma_handle = rte_malloc_virt2iova(buf);
4142 if (dma_handle == RTE_BAD_IOVA) {
4144 "unable to map response address to physical memory\n");
4147 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4148 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4149 req.dir_idx = rte_cpu_to_le_16(index);
4150 req.offset = rte_cpu_to_le_32(offset);
4151 req.len = rte_cpu_to_le_32(length);
4152 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4154 memcpy(data, buf, length);
4157 HWRM_CHECK_RESULT();
4163 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4166 struct hwrm_nvm_erase_dir_entry_input req = {0};
4167 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4169 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4170 req.dir_idx = rte_cpu_to_le_16(index);
4171 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4172 HWRM_CHECK_RESULT();
4179 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4180 uint16_t dir_ordinal, uint16_t dir_ext,
4181 uint16_t dir_attr, const uint8_t *data,
4185 struct hwrm_nvm_write_input req = {0};
4186 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4187 rte_iova_t dma_handle;
4190 buf = rte_malloc("nvm_write", data_len, 0);
4194 dma_handle = rte_malloc_virt2iova(buf);
4195 if (dma_handle == RTE_BAD_IOVA) {
4197 "unable to map response address to physical memory\n");
4200 memcpy(buf, data, data_len);
4202 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4204 req.dir_type = rte_cpu_to_le_16(dir_type);
4205 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4206 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4207 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4208 req.dir_data_length = rte_cpu_to_le_32(data_len);
4209 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4211 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4214 HWRM_CHECK_RESULT();
4221 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4223 uint32_t *count = cbdata;
4225 *count = *count + 1;
4228 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4229 struct bnxt_vnic_info *vnic __rte_unused)
4234 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4238 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4239 &count, bnxt_vnic_count_hwrm_stub);
4244 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4247 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4248 struct hwrm_func_vf_vnic_ids_query_output *resp =
4249 bp->hwrm_cmd_resp_addr;
4252 /* First query all VNIC ids */
4253 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4255 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4256 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4257 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4259 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4262 "unable to map VNIC ID table address to physical memory\n");
4265 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4266 HWRM_CHECK_RESULT();
4267 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4275 * This function queries the VNIC IDs for a specified VF. It then calls
4276 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4277 * Then it calls the hwrm_cb function to program this new vnic configuration.
4279 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4280 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4281 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4283 struct bnxt_vnic_info vnic;
4285 int i, num_vnic_ids;
4290 /* First query all VNIC ids */
4291 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4292 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4293 RTE_CACHE_LINE_SIZE);
4294 if (vnic_ids == NULL)
4297 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4298 rte_mem_lock_page(((char *)vnic_ids) + sz);
4300 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4302 if (num_vnic_ids < 0)
4303 return num_vnic_ids;
4305 /* Retrieve VNIC, update bd_stall then update */
4307 for (i = 0; i < num_vnic_ids; i++) {
4308 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4309 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4310 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4313 if (vnic.mru <= 4) /* Indicates unallocated */
4316 vnic_cb(&vnic, cbdata);
4318 rc = hwrm_cb(bp, &vnic);
4328 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4331 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4332 struct hwrm_func_cfg_input req = {0};
4335 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4337 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4338 req.enables |= rte_cpu_to_le_32(
4339 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4340 req.vlan_antispoof_mode = on ?
4341 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4342 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4343 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4345 HWRM_CHECK_RESULT();
4351 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4353 struct bnxt_vnic_info vnic;
4356 int num_vnic_ids, i;
4360 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4361 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4362 RTE_CACHE_LINE_SIZE);
4363 if (vnic_ids == NULL)
4366 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4367 rte_mem_lock_page(((char *)vnic_ids) + sz);
4369 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4375 * Loop through to find the default VNIC ID.
4376 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4377 * by sending the hwrm_func_qcfg command to the firmware.
4379 for (i = 0; i < num_vnic_ids; i++) {
4380 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4381 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4382 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4383 bp->pf->first_vf_id + vf);
4386 if (vnic.func_default) {
4388 return vnic.fw_vnic_id;
4391 /* Could not find a default VNIC. */
4392 PMD_DRV_LOG(ERR, "No default VNIC\n");
4398 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4400 struct bnxt_filter_info *filter)
4403 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4404 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4405 uint32_t enables = 0;
4407 if (filter->fw_em_filter_id != UINT64_MAX)
4408 bnxt_hwrm_clear_em_filter(bp, filter);
4410 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4412 req.flags = rte_cpu_to_le_32(filter->flags);
4414 enables = filter->enables |
4415 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4416 req.dst_id = rte_cpu_to_le_16(dst_id);
4418 if (filter->ip_addr_type) {
4419 req.ip_addr_type = filter->ip_addr_type;
4420 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4423 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4424 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4426 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4427 memcpy(req.src_macaddr, filter->src_macaddr,
4428 RTE_ETHER_ADDR_LEN);
4430 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4431 memcpy(req.dst_macaddr, filter->dst_macaddr,
4432 RTE_ETHER_ADDR_LEN);
4434 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4435 req.ovlan_vid = filter->l2_ovlan;
4437 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4438 req.ivlan_vid = filter->l2_ivlan;
4440 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4441 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4443 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4444 req.ip_protocol = filter->ip_protocol;
4446 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4447 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4449 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4450 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4452 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4453 req.src_port = rte_cpu_to_be_16(filter->src_port);
4455 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4456 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4458 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4459 req.mirror_vnic_id = filter->mirror_vnic_id;
4461 req.enables = rte_cpu_to_le_32(enables);
4463 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4465 HWRM_CHECK_RESULT();
4467 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4473 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4476 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4477 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4479 if (filter->fw_em_filter_id == UINT64_MAX)
4482 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4484 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4486 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4488 HWRM_CHECK_RESULT();
4491 filter->fw_em_filter_id = UINT64_MAX;
4492 filter->fw_l2_filter_id = UINT64_MAX;
4497 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4499 struct bnxt_filter_info *filter)
4502 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4503 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4504 bp->hwrm_cmd_resp_addr;
4505 uint32_t enables = 0;
4507 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4508 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4510 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4512 req.flags = rte_cpu_to_le_32(filter->flags);
4514 enables = filter->enables |
4515 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4516 req.dst_id = rte_cpu_to_le_16(dst_id);
4518 if (filter->ip_addr_type) {
4519 req.ip_addr_type = filter->ip_addr_type;
4521 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4524 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4525 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4527 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4528 memcpy(req.src_macaddr, filter->src_macaddr,
4529 RTE_ETHER_ADDR_LEN);
4531 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4532 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4534 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4535 req.ip_protocol = filter->ip_protocol;
4537 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4538 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4540 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4541 req.src_ipaddr_mask[0] =
4542 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4544 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4545 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4547 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4548 req.dst_ipaddr_mask[0] =
4549 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4551 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4552 req.src_port = rte_cpu_to_le_16(filter->src_port);
4554 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4555 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4557 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4558 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4560 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4561 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4563 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4564 req.mirror_vnic_id = filter->mirror_vnic_id;
4566 req.enables = rte_cpu_to_le_32(enables);
4568 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4570 HWRM_CHECK_RESULT();
4572 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4573 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4579 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4580 struct bnxt_filter_info *filter)
4583 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4584 struct hwrm_cfa_ntuple_filter_free_output *resp =
4585 bp->hwrm_cmd_resp_addr;
4587 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4590 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4592 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4594 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4596 HWRM_CHECK_RESULT();
4599 filter->fw_ntuple_filter_id = UINT64_MAX;
4605 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4607 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4608 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4609 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4610 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4611 uint16_t *ring_tbl = vnic->rss_table;
4612 int nr_ctxs = vnic->num_lb_ctxts;
4613 int max_rings = bp->rx_nr_rings;
4617 for (i = 0, k = 0; i < nr_ctxs; i++) {
4618 struct bnxt_rx_ring_info *rxr;
4619 struct bnxt_cp_ring_info *cpr;
4621 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4623 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4624 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4625 req.hash_mode_flags = vnic->hash_mode;
4627 req.ring_grp_tbl_addr =
4628 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4629 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4630 2 * sizeof(*ring_tbl));
4631 req.hash_key_tbl_addr =
4632 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4634 req.ring_table_pair_index = i;
4635 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4637 for (j = 0; j < 64; j++) {
4640 /* Find next active ring. */
4641 for (cnt = 0; cnt < max_rings; cnt++) {
4642 if (rx_queue_state[k] !=
4643 RTE_ETH_QUEUE_STATE_STOPPED)
4645 if (++k == max_rings)
4649 /* Return if no rings are active. */
4650 if (cnt == max_rings) {
4655 /* Add rx/cp ring pair to RSS table. */
4656 rxr = rxqs[k]->rx_ring;
4657 cpr = rxqs[k]->cp_ring;
4659 ring_id = rxr->rx_ring_struct->fw_ring_id;
4660 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4661 ring_id = cpr->cp_ring_struct->fw_ring_id;
4662 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4664 if (++k == max_rings)
4667 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4670 HWRM_CHECK_RESULT();
4677 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4679 unsigned int rss_idx, fw_idx, i;
4681 if (!(vnic->rss_table && vnic->hash_type))
4684 if (BNXT_CHIP_THOR(bp))
4685 return bnxt_vnic_rss_configure_thor(bp, vnic);
4687 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4690 if (vnic->rss_table && vnic->hash_type) {
4692 * Fill the RSS hash & redirection table with
4693 * ring group ids for all VNICs
4695 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4696 rss_idx++, fw_idx++) {
4697 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4698 fw_idx %= bp->rx_cp_nr_rings;
4699 if (vnic->fw_grp_ids[fw_idx] !=
4704 if (i == bp->rx_cp_nr_rings)
4706 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4708 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4714 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4715 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4719 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4721 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4722 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4724 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4725 req->num_cmpl_dma_aggr_during_int =
4726 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4728 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4730 /* min timer set to 1/2 of interrupt timer */
4731 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4733 /* buf timer set to 1/4 of interrupt timer */
4734 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4736 req->cmpl_aggr_dma_tmr_during_int =
4737 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4739 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4740 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4741 req->flags = rte_cpu_to_le_16(flags);
4744 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4745 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4747 struct hwrm_ring_aggint_qcaps_input req = {0};
4748 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4753 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4754 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4755 HWRM_CHECK_RESULT();
4757 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4758 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4760 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4761 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4762 agg_req->flags = rte_cpu_to_le_16(flags);
4764 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4765 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4766 agg_req->enables = rte_cpu_to_le_32(enables);
4772 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4773 struct bnxt_coal *coal, uint16_t ring_id)
4775 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4776 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4777 bp->hwrm_cmd_resp_addr;
4780 /* Set ring coalesce parameters only for 100G NICs */
4781 if (BNXT_CHIP_THOR(bp)) {
4782 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4784 } else if (bnxt_stratus_device(bp)) {
4785 bnxt_hwrm_set_coal_params(coal, &req);
4791 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4793 req.ring_id = rte_cpu_to_le_16(ring_id);
4794 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4795 HWRM_CHECK_RESULT();
4800 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4801 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4803 struct hwrm_func_backing_store_qcaps_input req = {0};
4804 struct hwrm_func_backing_store_qcaps_output *resp =
4805 bp->hwrm_cmd_resp_addr;
4806 struct bnxt_ctx_pg_info *ctx_pg;
4807 struct bnxt_ctx_mem_info *ctx;
4808 int total_alloc_len;
4809 int rc, i, tqm_rings;
4811 if (!BNXT_CHIP_THOR(bp) ||
4812 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4817 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4818 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4819 HWRM_CHECK_RESULT_SILENT();
4821 total_alloc_len = sizeof(*ctx);
4822 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4823 RTE_CACHE_LINE_SIZE);
4829 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4830 ctx->qp_min_qp1_entries =
4831 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4832 ctx->qp_max_l2_entries =
4833 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4834 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4835 ctx->srq_max_l2_entries =
4836 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4837 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4838 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4839 ctx->cq_max_l2_entries =
4840 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4841 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4842 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4843 ctx->vnic_max_vnic_entries =
4844 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4845 ctx->vnic_max_ring_table_entries =
4846 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4847 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4848 ctx->stat_max_entries =
4849 rte_le_to_cpu_32(resp->stat_max_entries);
4850 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4851 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4852 ctx->tqm_min_entries_per_ring =
4853 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4854 ctx->tqm_max_entries_per_ring =
4855 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4856 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4857 if (!ctx->tqm_entries_multiple)
4858 ctx->tqm_entries_multiple = 1;
4859 ctx->mrav_max_entries =
4860 rte_le_to_cpu_32(resp->mrav_max_entries);
4861 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4862 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4863 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4864 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4866 if (!ctx->tqm_fp_rings_count)
4867 ctx->tqm_fp_rings_count = bp->max_q;
4869 tqm_rings = ctx->tqm_fp_rings_count + 1;
4871 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4872 sizeof(*ctx_pg) * tqm_rings,
4873 RTE_CACHE_LINE_SIZE);
4878 for (i = 0; i < tqm_rings; i++, ctx_pg++)
4879 ctx->tqm_mem[i] = ctx_pg;
4887 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4889 struct hwrm_func_backing_store_cfg_input req = {0};
4890 struct hwrm_func_backing_store_cfg_output *resp =
4891 bp->hwrm_cmd_resp_addr;
4892 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4893 struct bnxt_ctx_pg_info *ctx_pg;
4894 uint32_t *num_entries;
4903 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4904 req.enables = rte_cpu_to_le_32(enables);
4906 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4907 ctx_pg = &ctx->qp_mem;
4908 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4909 req.qp_num_qp1_entries =
4910 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4911 req.qp_num_l2_entries =
4912 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4913 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4914 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4915 &req.qpc_pg_size_qpc_lvl,
4919 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4920 ctx_pg = &ctx->srq_mem;
4921 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4922 req.srq_num_l2_entries =
4923 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4924 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4925 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4926 &req.srq_pg_size_srq_lvl,
4930 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4931 ctx_pg = &ctx->cq_mem;
4932 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4933 req.cq_num_l2_entries =
4934 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4935 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4936 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4937 &req.cq_pg_size_cq_lvl,
4941 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4942 ctx_pg = &ctx->vnic_mem;
4943 req.vnic_num_vnic_entries =
4944 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4945 req.vnic_num_ring_table_entries =
4946 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4947 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4948 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4949 &req.vnic_pg_size_vnic_lvl,
4950 &req.vnic_page_dir);
4953 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4954 ctx_pg = &ctx->stat_mem;
4955 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4956 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4957 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4958 &req.stat_pg_size_stat_lvl,
4959 &req.stat_page_dir);
4962 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4963 num_entries = &req.tqm_sp_num_entries;
4964 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4965 pg_dir = &req.tqm_sp_page_dir;
4966 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4967 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4968 if (!(enables & ena))
4971 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4973 ctx_pg = ctx->tqm_mem[i];
4974 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4975 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4978 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4979 HWRM_CHECK_RESULT();
4985 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4987 struct hwrm_port_qstats_ext_input req = {0};
4988 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4989 struct bnxt_pf_info *pf = bp->pf;
4992 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4993 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4996 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4998 req.port_id = rte_cpu_to_le_16(pf->port_id);
4999 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5000 req.tx_stat_host_addr =
5001 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5003 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5005 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5006 req.rx_stat_host_addr =
5007 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5009 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5011 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5014 bp->fw_rx_port_stats_ext_size = 0;
5015 bp->fw_tx_port_stats_ext_size = 0;
5017 bp->fw_rx_port_stats_ext_size =
5018 rte_le_to_cpu_16(resp->rx_stat_size);
5019 bp->fw_tx_port_stats_ext_size =
5020 rte_le_to_cpu_16(resp->tx_stat_size);
5023 HWRM_CHECK_RESULT();
5030 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5032 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5033 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5034 bp->hwrm_cmd_resp_addr;
5037 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5038 req.tunnel_type = type;
5039 req.dest_fid = bp->fw_fid;
5040 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5041 HWRM_CHECK_RESULT();
5049 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5051 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5052 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5053 bp->hwrm_cmd_resp_addr;
5056 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5057 req.tunnel_type = type;
5058 req.dest_fid = bp->fw_fid;
5059 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5060 HWRM_CHECK_RESULT();
5067 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5069 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5070 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5071 bp->hwrm_cmd_resp_addr;
5074 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5075 req.src_fid = bp->fw_fid;
5076 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5077 HWRM_CHECK_RESULT();
5080 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5087 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5090 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5091 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5092 bp->hwrm_cmd_resp_addr;
5095 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5096 req.src_fid = bp->fw_fid;
5097 req.tunnel_type = tun_type;
5098 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5099 HWRM_CHECK_RESULT();
5102 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5104 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5111 int bnxt_hwrm_set_mac(struct bnxt *bp)
5113 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5114 struct hwrm_func_vf_cfg_input req = {0};
5120 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5123 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5124 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5126 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5128 HWRM_CHECK_RESULT();
5135 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5137 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5138 struct hwrm_func_drv_if_change_input req = {0};
5142 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5145 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5146 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5147 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5149 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5152 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5156 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5158 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5160 HWRM_CHECK_RESULT();
5161 flags = rte_le_to_cpu_32(resp->flags);
5167 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5168 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5169 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5175 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5177 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5178 struct bnxt_error_recovery_info *info = bp->recovery_info;
5179 struct hwrm_error_recovery_qcfg_input req = {0};
5184 /* Older FW does not have error recovery support */
5185 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5188 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5190 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5192 HWRM_CHECK_RESULT();
5194 flags = rte_le_to_cpu_32(resp->flags);
5195 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5196 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5197 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5198 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5200 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5201 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5206 /* FW returned values are in units of 100msec */
5207 info->driver_polling_freq =
5208 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5209 info->master_func_wait_period =
5210 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5211 info->normal_func_wait_period =
5212 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5213 info->master_func_wait_period_after_reset =
5214 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5215 info->max_bailout_time_after_reset =
5216 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5217 info->status_regs[BNXT_FW_STATUS_REG] =
5218 rte_le_to_cpu_32(resp->fw_health_status_reg);
5219 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5220 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5221 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5222 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5223 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5224 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5225 info->reg_array_cnt =
5226 rte_le_to_cpu_32(resp->reg_array_cnt);
5228 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5233 for (i = 0; i < info->reg_array_cnt; i++) {
5234 info->reset_reg[i] =
5235 rte_le_to_cpu_32(resp->reset_reg[i]);
5236 info->reset_reg_val[i] =
5237 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5238 info->delay_after_reset[i] =
5239 resp->delay_after_reset[i];
5244 /* Map the FW status registers */
5246 rc = bnxt_map_fw_health_status_regs(bp);
5249 rte_free(bp->recovery_info);
5250 bp->recovery_info = NULL;
5255 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5257 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5258 struct hwrm_fw_reset_input req = {0};
5264 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5266 req.embedded_proc_type =
5267 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5268 req.selfrst_status =
5269 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5270 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5272 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5275 HWRM_CHECK_RESULT();
5281 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5283 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5284 struct hwrm_port_ts_query_input req = {0};
5285 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5292 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5295 case BNXT_PTP_FLAGS_PATH_TX:
5296 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5298 case BNXT_PTP_FLAGS_PATH_RX:
5299 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5301 case BNXT_PTP_FLAGS_CURRENT_TIME:
5302 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5306 req.flags = rte_cpu_to_le_32(flags);
5307 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5309 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5311 HWRM_CHECK_RESULT();
5314 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5316 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5323 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5325 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5326 bp->hwrm_cmd_resp_addr;
5327 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5331 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5334 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5336 "Not a PF or trusted VF. Command not supported\n");
5340 HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5341 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5343 HWRM_CHECK_RESULT();
5344 flags = rte_le_to_cpu_32(resp->flags);
5347 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5348 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5349 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5355 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5359 struct hwrm_cfa_counter_qcaps_input req = {0};
5360 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5362 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5364 "Not a PF or trusted VF. Command not supported\n");
5368 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5369 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5370 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5372 HWRM_CHECK_RESULT();
5374 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5380 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5383 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5384 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5386 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5388 "Not a PF or trusted VF. Command not supported\n");
5392 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5394 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5395 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5396 req.page_dir = rte_cpu_to_le_64(dma_addr);
5398 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5400 HWRM_CHECK_RESULT();
5402 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5403 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5410 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5413 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5414 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5416 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5418 "Not a PF or trusted VF. Command not supported\n");
5422 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5424 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5426 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5428 HWRM_CHECK_RESULT();
5434 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5435 uint16_t cntr, uint16_t ctx_id,
5436 uint32_t num_entries, bool enable)
5438 struct hwrm_cfa_counter_cfg_input req = {0};
5439 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5443 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5445 "Not a PF or trusted VF. Command not supported\n");
5449 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5451 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5452 req.counter_type = rte_cpu_to_le_16(cntr);
5453 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5454 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5455 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5456 if (dir == BNXT_DIR_RX)
5457 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5458 else if (dir == BNXT_DIR_TX)
5459 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5460 req.flags = rte_cpu_to_le_16(flags);
5461 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5462 req.num_entries = rte_cpu_to_le_32(num_entries);
5464 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5465 HWRM_CHECK_RESULT();
5471 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5472 enum bnxt_flow_dir dir,
5474 uint16_t num_entries)
5476 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5477 struct hwrm_cfa_counter_qstats_input req = {0};
5478 uint16_t flow_ctx_id = 0;
5482 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5484 "Not a PF or trusted VF. Command not supported\n");
5488 if (dir == BNXT_DIR_RX) {
5489 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5490 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5491 } else if (dir == BNXT_DIR_TX) {
5492 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5493 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5496 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5497 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5498 req.counter_type = rte_cpu_to_le_16(cntr);
5499 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5500 req.num_entries = rte_cpu_to_le_16(num_entries);
5501 req.flags = rte_cpu_to_le_16(flags);
5502 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5504 HWRM_CHECK_RESULT();
5510 #ifdef RTE_LIBRTE_BNXT_PMD_SYSTEM
5512 bnxt_hwrm_oem_cmd(struct bnxt *bp, uint32_t entry_num)
5514 struct hwrm_oem_cmd_input req = {0};
5515 struct hwrm_oem_cmd_output *resp = bp->hwrm_cmd_resp_addr;
5516 struct bnxt_dmabuf_info oem_data;
5519 HWRM_PREP(&req, HWRM_OEM_CMD, BNXT_USE_CHIMP_MB);
5522 memset(&oem_data, 0, sizeof(struct bnxt_dmabuf_info));
5523 oem_data.entry_num = (entry_num);
5524 memcpy(&req.oem_data[0], &oem_data, sizeof(struct bnxt_dmabuf_info));
5526 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5527 HWRM_CHECK_RESULT();
5529 bp->dmabuf.entry_num = entry_num;
5535 #endif /* RTE_LIBRTE_BNXT_PMD_SYSTEM */