drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (BNXT_CHIP_P5(bp)) {
 754                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
 755                         return 0;
 756         } else {
 757                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 758                         return 0;
 759         }
 760
 761         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 762                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 763
 764         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 765         if (!ptp)
 766                 return -ENOMEM;
 767
 768         if (!BNXT_CHIP_P5(bp)) {
 769                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 771                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 773                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 775                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 776                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 777                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 778                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 779                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 781                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 783                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 784                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 785                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 786                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 787         }
 788
 789         ptp->bp = bp;
 790         bp->ptp_cfg = ptp;
 791
 792         return 0;
 793 }
 794
 795 void bnxt_free_vf_info(struct bnxt *bp)
 796 {
 797         int i;
 798
 799         if (bp->pf == NULL)
 800                 return;
 801
 802         if (bp->pf->vf_info == NULL)
 803                 return;
 804
 805         for (i = 0; i < bp->pf->max_vfs; i++) {
 806                 rte_free(bp->pf->vf_info[i].vlan_table);
 807                 bp->pf->vf_info[i].vlan_table = NULL;
 808                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 809                 bp->pf->vf_info[i].vlan_as_table = NULL;
 810         }
 811         rte_free(bp->pf->vf_info);
 812         bp->pf->vf_info = NULL;
 813 }
 814
 815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 816 {
 817         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 818         int i;
 819
 820         if (vf_info)
 821                 bnxt_free_vf_info(bp);
 822
 823         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 824         if (vf_info == NULL) {
 825                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 826                 return -ENOMEM;
 827         }
 828
 829         bp->pf->max_vfs = max_vfs;
 830         for (i = 0; i < max_vfs; i++) {
 831                 vf_info[i].fid = bp->pf->first_vf_id + i;
 832                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 833                                                     getpagesize(), getpagesize());
 834                 if (vf_info[i].vlan_table == NULL) {
 835                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 836                         goto err;
 837                 }
 838                 rte_mem_lock_page(vf_info[i].vlan_table);
 839
 840                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 841                                                        getpagesize(), getpagesize());
 842                 if (vf_info[i].vlan_as_table == NULL) {
 843                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 844                         goto err;
 845                 }
 846                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 847
 848                 STAILQ_INIT(&vf_info[i].filter);
 849         }
 850
 851         bp->pf->vf_info = vf_info;
 852
 853         return 0;
 854 err:
 855         bnxt_free_vf_info(bp);
 856         return -ENOMEM;
 857 }
 858
 859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 860 {
 861         int rc = 0;
 862         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 863         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 864         uint16_t new_max_vfs;
 865         uint32_t flags;
 866
 867         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 868
 869         req.fid = rte_cpu_to_le_16(0xffff);
 870
 871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 872
 873         HWRM_CHECK_RESULT();
 874
 875         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 876         flags = rte_le_to_cpu_32(resp->flags);
 877         if (BNXT_PF(bp)) {
 878                 bp->pf->port_id = resp->port_id;
 879                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 880                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 881                 new_max_vfs = bp->pdev->max_vfs;
 882                 if (new_max_vfs != bp->pf->max_vfs) {
 883                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 884                         if (rc)
 885                                 goto unlock;
 886                 }
 887         }
 888
 889         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 890         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 891                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 892                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 893         } else {
 894                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 895         }
 896         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 897         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 898         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 899         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 900         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 901         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 902         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 903         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 904                 bp->max_l2_ctx += bp->max_rx_em_flows;
 905         /* TODO: For now, do not support VMDq/RFS on VFs. */
 906         if (BNXT_PF(bp)) {
 907                 if (bp->pf->max_vfs)
 908                         bp->max_vnics = 1;
 909                 else
 910                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 911         } else {
 912                 bp->max_vnics = 1;
 913         }
 914         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 915                     bp->max_l2_ctx, bp->max_vnics);
 916         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 917         if (BNXT_PF(bp)) {
 918                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 919                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 920                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 921                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 922                         HWRM_UNLOCK();
 923                         bnxt_hwrm_ptp_qcfg(bp);
 924                 }
 925         }
 926
 927         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 928                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 929
 930         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 931                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 932                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 933         }
 934
 935         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 936                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 937
 938         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 939                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 940
 941         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 942                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 943
 944 unlock:
 945         HWRM_UNLOCK();
 946
 947         return rc;
 948 }
 949
 950 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 951 {
 952         int rc;
 953
 954         rc = __bnxt_hwrm_func_qcaps(bp);
 955         if (rc == -ENOMEM)
 956                 return rc;
 957
 958         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 959                 rc = bnxt_alloc_ctx_mem(bp);
 960                 if (rc)
 961                         return rc;
 962
 963                 /* On older FW,
 964                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 965                  * But the error can be ignored. Return success.
 966                  */
 967                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 968                 if (!rc)
 969                         bp->flags |= BNXT_FLAG_NEW_RM;
 970         }
 971
 972         return 0;
 973 }
 974
 975 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 976 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 977 {
 978         int rc = 0;
 979         uint32_t flags;
 980         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 981         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 982
 983         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 984
 985         req.target_id = rte_cpu_to_le_16(0xffff);
 986
 987         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 988
 989         HWRM_CHECK_RESULT();
 990
 991         flags = rte_le_to_cpu_32(resp->flags);
 992
 993         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 994                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 995                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 996         }
 997
 998         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 999                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1000
1001         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1002                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1003
1004         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1005
1006         HWRM_UNLOCK();
1007
1008         return rc;
1009 }
1010
1011 int bnxt_hwrm_func_reset(struct bnxt *bp)
1012 {
1013         int rc = 0;
1014         struct hwrm_func_reset_input req = {.req_type = 0 };
1015         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1016
1017         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1018
1019         req.enables = rte_cpu_to_le_32(0);
1020
1021         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1022
1023         HWRM_CHECK_RESULT();
1024         HWRM_UNLOCK();
1025
1026         return rc;
1027 }
1028
1029 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1030 {
1031         int rc;
1032         uint32_t flags = 0;
1033         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1034         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1035
1036         if (bp->flags & BNXT_FLAG_REGISTERED)
1037                 return 0;
1038
1039         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1040                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1041         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1042                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1043
1044         /* PFs and trusted VFs should indicate the support of the
1045          * Master capability on non Stingray platform
1046          */
1047         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1048                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1049
1050         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1051         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1052                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1053         req.ver_maj = RTE_VER_YEAR;
1054         req.ver_min = RTE_VER_MONTH;
1055         req.ver_upd = RTE_VER_MINOR;
1056
1057         if (BNXT_PF(bp)) {
1058                 req.enables |= rte_cpu_to_le_32(
1059                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1060                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1061                        RTE_MIN(sizeof(req.vf_req_fwd),
1062                                sizeof(bp->pf->vf_req_fwd)));
1063         }
1064
1065         req.flags = rte_cpu_to_le_32(flags);
1066
1067         req.async_event_fwd[0] |=
1068                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1069                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1070                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1071                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1072                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1073         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1074                 req.async_event_fwd[0] |=
1075                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1076         req.async_event_fwd[1] |=
1077                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1078                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1079         if (BNXT_PF(bp))
1080                 req.async_event_fwd[1] |=
1081                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1082
1083         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1084                 req.async_event_fwd[1] |=
1085                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1086
1087         req.async_event_fwd[2] |=
1088                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
1089
1090         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1091
1092         HWRM_CHECK_RESULT();
1093
1094         flags = rte_le_to_cpu_32(resp->flags);
1095         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1096                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1097
1098         HWRM_UNLOCK();
1099
1100         bp->flags |= BNXT_FLAG_REGISTERED;
1101
1102         return rc;
1103 }
1104
1105 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1106 {
1107         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1108                 return 0;
1109
1110         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1111 }
1112
1113 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1114 {
1115         int rc;
1116         uint32_t flags = 0;
1117         uint32_t enables;
1118         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1119         struct hwrm_func_vf_cfg_input req = {0};
1120
1121         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1122
1123         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1124                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1125                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1126                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1127                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1128
1129         if (BNXT_HAS_RING_GRPS(bp)) {
1130                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1131                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1132         }
1133
1134         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1135         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1136                                             AGG_RING_MULTIPLIER);
1137         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1138         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1139                                               bp->tx_nr_rings +
1140                                               BNXT_NUM_ASYNC_CPR(bp));
1141         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1142         if (bp->vf_resv_strategy ==
1143             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1144                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1145                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1146                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1147                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1148                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1149                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1150         } else if (bp->vf_resv_strategy ==
1151                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1152                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1153                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1154         }
1155
1156         if (test)
1157                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1158                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1159                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1160                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1161                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1162                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1163
1164         if (test && BNXT_HAS_RING_GRPS(bp))
1165                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1166
1167         req.flags = rte_cpu_to_le_32(flags);
1168         req.enables |= rte_cpu_to_le_32(enables);
1169
1170         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1171
1172         if (test)
1173                 HWRM_CHECK_RESULT_SILENT();
1174         else
1175                 HWRM_CHECK_RESULT();
1176
1177         HWRM_UNLOCK();
1178         return rc;
1179 }
1180
1181 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1182 {
1183         int rc;
1184         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1185         struct hwrm_func_resource_qcaps_input req = {0};
1186
1187         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1188         req.fid = rte_cpu_to_le_16(0xffff);
1189
1190         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1191
1192         HWRM_CHECK_RESULT_SILENT();
1193
1194         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1195         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1196         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1197         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1198         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1199         /* func_resource_qcaps does not return max_rx_em_flows.
1200          * So use the value provided by func_qcaps.
1201          */
1202         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1203         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1204                 bp->max_l2_ctx += bp->max_rx_em_flows;
1205         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1206         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1207         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1208         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1209         if (bp->vf_resv_strategy >
1210             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1211                 bp->vf_resv_strategy =
1212                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1213
1214         HWRM_UNLOCK();
1215         return rc;
1216 }
1217
1218 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1219 {
1220         int rc = 0;
1221         struct hwrm_ver_get_input req = {.req_type = 0 };
1222         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1223         uint32_t fw_version;
1224         uint16_t max_resp_len;
1225         char type[RTE_MEMZONE_NAMESIZE];
1226         uint32_t dev_caps_cfg;
1227
1228         bp->max_req_len = HWRM_MAX_REQ_LEN;
1229         bp->hwrm_cmd_timeout = timeout;
1230         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1231
1232         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1233         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1234         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1235
1236         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1237
1238         if (bp->flags & BNXT_FLAG_FW_RESET)
1239                 HWRM_CHECK_RESULT_SILENT();
1240         else
1241                 HWRM_CHECK_RESULT();
1242
1243         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1244                 rc = -EAGAIN;
1245                 goto error;
1246         }
1247
1248         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1249                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1250                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1251                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1252                 resp->hwrm_fw_rsvd_8b);
1253         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1254                      (resp->hwrm_fw_min_8b << 16) |
1255                      (resp->hwrm_fw_bld_8b << 8) |
1256                      resp->hwrm_fw_rsvd_8b;
1257         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1258                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1259
1260         fw_version = resp->hwrm_intf_maj_8b << 16;
1261         fw_version |= resp->hwrm_intf_min_8b << 8;
1262         fw_version |= resp->hwrm_intf_upd_8b;
1263         bp->hwrm_spec_code = fw_version;
1264
1265         /* def_req_timeout value is in milliseconds */
1266         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1267         /* convert timeout to usec */
1268         bp->hwrm_cmd_timeout *= 1000;
1269         if (!bp->hwrm_cmd_timeout)
1270                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1271
1272         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1273                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1274                 rc = -EINVAL;
1275                 goto error;
1276         }
1277
1278         if (bp->max_req_len > resp->max_req_win_len) {
1279                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1280                 rc = -EINVAL;
1281                 goto error;
1282         }
1283
1284         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1285
1286         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1287         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1288         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1289                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1290
1291         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1292         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1293
1294         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1295         bp->max_resp_len = max_resp_len;
1296
1297         if ((dev_caps_cfg &
1298                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1299             (dev_caps_cfg &
1300              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1301                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1302                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1303         }
1304
1305         if (((dev_caps_cfg &
1306               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1307              (dev_caps_cfg &
1308               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1309             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1310                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1311                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1312                         bp->pdev->addr.devid, bp->pdev->addr.function);
1313
1314                 rte_free(bp->hwrm_short_cmd_req_addr);
1315
1316                 bp->hwrm_short_cmd_req_addr =
1317                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1318                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1319                         rc = -ENOMEM;
1320                         goto error;
1321                 }
1322                 bp->hwrm_short_cmd_req_dma_addr =
1323                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1324                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1325                         rte_free(bp->hwrm_short_cmd_req_addr);
1326                         PMD_DRV_LOG(ERR,
1327                                 "Unable to map buffer to physical memory.\n");
1328                         rc = -ENOMEM;
1329                         goto error;
1330                 }
1331         }
1332         if (dev_caps_cfg &
1333             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1334                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1335                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1336         }
1337         if (dev_caps_cfg &
1338             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1339                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1340         if (dev_caps_cfg &
1341             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1342                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1343                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1344         }
1345
1346         if (dev_caps_cfg &
1347             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1348                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1349                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1350         }
1351
1352         if (dev_caps_cfg &
1353             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
1354                 PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
1355                 bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
1356         }
1357
1358 error:
1359         HWRM_UNLOCK();
1360         return rc;
1361 }
1362
1363 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1364 {
1365         int rc;
1366         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1367         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1368
1369         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1370                 return 0;
1371
1372         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1373         req.flags = flags;
1374
1375         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1376
1377         HWRM_CHECK_RESULT();
1378         HWRM_UNLOCK();
1379
1380         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1381                     bp->eth_dev->data->port_id);
1382
1383         return rc;
1384 }
1385
1386 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1387 {
1388         int rc = 0;
1389         struct hwrm_port_phy_cfg_input req = {0};
1390         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1391         uint32_t enables = 0;
1392
1393         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1394
1395         if (conf->link_up) {
1396                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1397                 if (bp->link_info->auto_mode && conf->link_speed) {
1398                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1399                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1400                 }
1401
1402                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1403                 /*
1404                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1405                  * any auto mode, even "none".
1406                  */
1407                 if (!conf->link_speed) {
1408                         /* No speeds specified. Enable AutoNeg - all speeds */
1409                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1410                         req.auto_mode =
1411                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1412                 } else {
1413                         if (bp->link_info->link_signal_mode) {
1414                                 enables |=
1415                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1416                                 req.force_pam4_link_speed =
1417                                         rte_cpu_to_le_16(conf->link_speed);
1418                         } else {
1419                                 req.force_link_speed =
1420                                         rte_cpu_to_le_16(conf->link_speed);
1421                         }
1422                 }
1423                 /* AutoNeg - Advertise speeds specified. */
1424                 if (conf->auto_link_speed_mask &&
1425                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1426                         req.auto_mode =
1427                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1428                         req.auto_link_speed_mask =
1429                                 conf->auto_link_speed_mask;
1430                         if (conf->auto_pam4_link_speeds) {
1431                                 enables |=
1432                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1433                                 req.auto_link_pam4_speed_mask =
1434                                         conf->auto_pam4_link_speeds;
1435                         } else {
1436                                 enables |=
1437                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1438                         }
1439                 }
1440                 if (conf->auto_link_speed &&
1441                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1442                         enables |=
1443                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1444
1445                 req.auto_duplex = conf->duplex;
1446                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1447                 req.auto_pause = conf->auto_pause;
1448                 req.force_pause = conf->force_pause;
1449                 /* Set force_pause if there is no auto or if there is a force */
1450                 if (req.auto_pause && !req.force_pause)
1451                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1452                 else
1453                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1454
1455                 req.enables = rte_cpu_to_le_32(enables);
1456         } else {
1457                 req.flags =
1458                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1459                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1460         }
1461
1462         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1463
1464         HWRM_CHECK_RESULT();
1465         HWRM_UNLOCK();
1466
1467         return rc;
1468 }
1469
1470 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1471                                    struct bnxt_link_info *link_info)
1472 {
1473         int rc = 0;
1474         struct hwrm_port_phy_qcfg_input req = {0};
1475         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1476
1477         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1478
1479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1480
1481         HWRM_CHECK_RESULT();
1482
1483         link_info->phy_link_status = resp->link;
1484         link_info->link_up =
1485                 (link_info->phy_link_status ==
1486                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1487         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1488         link_info->duplex = resp->duplex_cfg;
1489         link_info->pause = resp->pause;
1490         link_info->auto_pause = resp->auto_pause;
1491         link_info->force_pause = resp->force_pause;
1492         link_info->auto_mode = resp->auto_mode;
1493         link_info->phy_type = resp->phy_type;
1494         link_info->media_type = resp->media_type;
1495
1496         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1497         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1498         link_info->auto_link_speed_mask = rte_le_to_cpu_16(resp->auto_link_speed_mask);
1499         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1500         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1501         link_info->phy_ver[0] = resp->phy_maj;
1502         link_info->phy_ver[1] = resp->phy_min;
1503         link_info->phy_ver[2] = resp->phy_bld;
1504         link_info->link_signal_mode =
1505                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1506         link_info->force_pam4_link_speed =
1507                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1508         link_info->support_pam4_speeds =
1509                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1510         link_info->auto_pam4_link_speeds =
1511                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1512         link_info->module_status = resp->module_status;
1513         HWRM_UNLOCK();
1514
1515         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1516                     link_info->link_speed, link_info->auto_mode,
1517                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1518                     link_info->support_speeds, link_info->force_link_speed);
1519         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1520                     link_info->link_signal_mode,
1521                     link_info->auto_pam4_link_speeds,
1522                     link_info->support_pam4_speeds,
1523                     link_info->force_pam4_link_speed);
1524         return rc;
1525 }
1526
1527 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1528 {
1529         int rc = 0;
1530         struct hwrm_port_phy_qcaps_input req = {0};
1531         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1532         struct bnxt_link_info *link_info = bp->link_info;
1533
1534         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1535                 return 0;
1536
1537         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1538
1539         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1540
1541         HWRM_CHECK_RESULT_SILENT();
1542
1543         bp->port_cnt = resp->port_cnt;
1544         if (resp->supported_speeds_auto_mode)
1545                 link_info->support_auto_speeds =
1546                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1547         if (resp->supported_pam4_speeds_auto_mode)
1548                 link_info->support_pam4_auto_speeds =
1549                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1550
1551         HWRM_UNLOCK();
1552
1553         /* Older firmware does not have supported_auto_speeds, so assume
1554          * that all supported speeds can be autonegotiated.
1555          */
1556         if (link_info->auto_link_speed_mask && !link_info->support_auto_speeds)
1557                 link_info->support_auto_speeds = link_info->support_speeds;
1558
1559         return 0;
1560 }
1561
1562 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1563 {
1564         int i = 0;
1565
1566         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1567                 if (bp->tx_cos_queue[i].profile ==
1568                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1569                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1570                         return true;
1571                 }
1572         }
1573         return false;
1574 }
1575
1576 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1577 {
1578         int i = 0;
1579
1580         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1581                 if (bp->tx_cos_queue[i].profile !=
1582                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1583                     bp->tx_cos_queue[i].id !=
1584                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1585                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1586                         break;
1587                 }
1588         }
1589 }
1590
1591 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1592 {
1593         int rc = 0;
1594         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1595         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1596         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1597         int i;
1598
1599 get_rx_info:
1600         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1601
1602         req.flags = rte_cpu_to_le_32(dir);
1603         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1604         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1605             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1606                 req.drv_qmap_cap =
1607                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1608         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1609
1610         HWRM_CHECK_RESULT();
1611
1612         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1613                 GET_TX_QUEUE_INFO(0);
1614                 GET_TX_QUEUE_INFO(1);
1615                 GET_TX_QUEUE_INFO(2);
1616                 GET_TX_QUEUE_INFO(3);
1617                 GET_TX_QUEUE_INFO(4);
1618                 GET_TX_QUEUE_INFO(5);
1619                 GET_TX_QUEUE_INFO(6);
1620                 GET_TX_QUEUE_INFO(7);
1621         } else  {
1622                 GET_RX_QUEUE_INFO(0);
1623                 GET_RX_QUEUE_INFO(1);
1624                 GET_RX_QUEUE_INFO(2);
1625                 GET_RX_QUEUE_INFO(3);
1626                 GET_RX_QUEUE_INFO(4);
1627                 GET_RX_QUEUE_INFO(5);
1628                 GET_RX_QUEUE_INFO(6);
1629                 GET_RX_QUEUE_INFO(7);
1630         }
1631
1632         HWRM_UNLOCK();
1633
1634         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1635                 goto done;
1636
1637         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1638                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1639         } else {
1640                 int j;
1641
1642                 /* iterate and find the COSq profile to use for Tx */
1643                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1644                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1645                                 if (bp->tx_cos_queue[i].id != 0xff)
1646                                         bp->tx_cosq_id[j++] =
1647                                                 bp->tx_cos_queue[i].id;
1648                         }
1649                 } else {
1650                         /* When CoS classification is disabled, for normal NIC
1651                          * operations, ideally we should look to use LOSSY.
1652                          * If not found, fallback to the first valid profile
1653                          */
1654                         if (!bnxt_find_lossy_profile(bp))
1655                                 bnxt_find_first_valid_profile(bp);
1656
1657                 }
1658         }
1659
1660         bp->max_tc = resp->max_configurable_queues;
1661         bp->max_lltc = resp->max_configurable_lossless_queues;
1662         if (bp->max_tc > BNXT_MAX_QUEUE)
1663                 bp->max_tc = BNXT_MAX_QUEUE;
1664         bp->max_q = bp->max_tc;
1665
1666         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1667                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1668                 goto get_rx_info;
1669         }
1670
1671 done:
1672         return rc;
1673 }
1674
1675 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1676                          struct bnxt_ring *ring,
1677                          uint32_t ring_type, uint32_t map_index,
1678                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1679                          uint16_t tx_cosq_id)
1680 {
1681         int rc = 0;
1682         uint32_t enables = 0;
1683         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1684         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1685         struct rte_mempool *mb_pool;
1686         uint16_t rx_buf_size;
1687
1688         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1689
1690         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1691         req.fbo = rte_cpu_to_le_32(0);
1692         /* Association of ring index with doorbell index */
1693         req.logical_id = rte_cpu_to_le_16(map_index);
1694         req.length = rte_cpu_to_le_32(ring->ring_size);
1695
1696         switch (ring_type) {
1697         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1698                 req.ring_type = ring_type;
1699                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1700                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1701                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1702                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1703                         enables |=
1704                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1705                 break;
1706         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1707                 req.ring_type = ring_type;
1708                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1709                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1710                 if (BNXT_CHIP_P5(bp)) {
1711                         mb_pool = bp->rx_queues[0]->mb_pool;
1712                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1713                                       RTE_PKTMBUF_HEADROOM;
1714                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1715                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1716                         enables |=
1717                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1718                 }
1719                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1720                         enables |=
1721                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1722                 break;
1723         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1724                 req.ring_type = ring_type;
1725                 if (BNXT_HAS_NQ(bp)) {
1726                         /* Association of cp ring with nq */
1727                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1728                         enables |=
1729                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1730                 }
1731                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1732                 break;
1733         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1734                 req.ring_type = ring_type;
1735                 req.page_size = BNXT_PAGE_SHFT;
1736                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1737                 break;
1738         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1739                 req.ring_type = ring_type;
1740                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1741
1742                 mb_pool = bp->rx_queues[0]->mb_pool;
1743                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1744                               RTE_PKTMBUF_HEADROOM;
1745                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1746                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1747
1748                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1749                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1750                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1751                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1752                 break;
1753         default:
1754                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1755                         ring_type);
1756                 HWRM_UNLOCK();
1757                 return -EINVAL;
1758         }
1759         req.enables = rte_cpu_to_le_32(enables);
1760
1761         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1762
1763         if (rc || resp->error_code) {
1764                 if (rc == 0 && resp->error_code)
1765                         rc = rte_le_to_cpu_16(resp->error_code);
1766                 switch (ring_type) {
1767                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1768                         PMD_DRV_LOG(ERR,
1769                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1770                         HWRM_UNLOCK();
1771                         return rc;
1772                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1773                         PMD_DRV_LOG(ERR,
1774                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1775                         HWRM_UNLOCK();
1776                         return rc;
1777                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1778                         PMD_DRV_LOG(ERR,
1779                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1780                                     rc);
1781                         HWRM_UNLOCK();
1782                         return rc;
1783                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1784                         PMD_DRV_LOG(ERR,
1785                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1786                         HWRM_UNLOCK();
1787                         return rc;
1788                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1789                         PMD_DRV_LOG(ERR,
1790                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1791                         HWRM_UNLOCK();
1792                         return rc;
1793                 default:
1794                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1795                         HWRM_UNLOCK();
1796                         return rc;
1797                 }
1798         }
1799
1800         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1801         HWRM_UNLOCK();
1802         return rc;
1803 }
1804
1805 int bnxt_hwrm_ring_free(struct bnxt *bp,
1806                         struct bnxt_ring *ring, uint32_t ring_type,
1807                         uint16_t cp_ring_id)
1808 {
1809         int rc;
1810         struct hwrm_ring_free_input req = {.req_type = 0 };
1811         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1812
1813         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1814
1815         req.ring_type = ring_type;
1816         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1817         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1818
1819         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1820
1821         if (rc || resp->error_code) {
1822                 if (rc == 0 && resp->error_code)
1823                         rc = rte_le_to_cpu_16(resp->error_code);
1824                 HWRM_UNLOCK();
1825
1826                 switch (ring_type) {
1827                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1828                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1829                                 rc);
1830                         return rc;
1831                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1832                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1833                                 rc);
1834                         return rc;
1835                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1836                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1837                                 rc);
1838                         return rc;
1839                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1840                         PMD_DRV_LOG(ERR,
1841                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1842                         return rc;
1843                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1844                         PMD_DRV_LOG(ERR,
1845                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1846                         return rc;
1847                 default:
1848                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1849                         return rc;
1850                 }
1851         }
1852         HWRM_UNLOCK();
1853         return 0;
1854 }
1855
1856 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1857 {
1858         int rc = 0;
1859         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1860         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1861
1862         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1863
1864         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1865         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1866         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1867         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1868
1869         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1870
1871         HWRM_CHECK_RESULT();
1872
1873         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1874
1875         HWRM_UNLOCK();
1876
1877         return rc;
1878 }
1879
1880 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1881 {
1882         int rc;
1883         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1884         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1885
1886         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1887
1888         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1889
1890         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1891
1892         HWRM_CHECK_RESULT();
1893         HWRM_UNLOCK();
1894
1895         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1896         return rc;
1897 }
1898
1899 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1900 {
1901         int rc = 0;
1902         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1903         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1904
1905         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1906                 return rc;
1907
1908         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1909
1910         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1911
1912         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1913
1914         HWRM_CHECK_RESULT();
1915         HWRM_UNLOCK();
1916
1917         return rc;
1918 }
1919
1920 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1921 {
1922         int rc;
1923         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1924         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1925
1926         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1927
1928         req.update_period_ms = rte_cpu_to_le_32(0);
1929
1930         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1931
1932         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933
1934         HWRM_CHECK_RESULT();
1935
1936         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1937
1938         HWRM_UNLOCK();
1939
1940         return rc;
1941 }
1942
1943 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1944 {
1945         int rc;
1946         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1947         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1948
1949         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1950
1951         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1952
1953         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1954
1955         HWRM_CHECK_RESULT();
1956         HWRM_UNLOCK();
1957
1958         return rc;
1959 }
1960
1961 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1962 {
1963         int rc = 0, i, j;
1964         struct hwrm_vnic_alloc_input req = { 0 };
1965         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1966
1967         if (!BNXT_HAS_RING_GRPS(bp))
1968                 goto skip_ring_grps;
1969
1970         /* map ring groups to this vnic */
1971         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1972                 vnic->start_grp_id, vnic->end_grp_id);
1973         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1974                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1975
1976         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1977         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1978         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1979         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1980
1981 skip_ring_grps:
1982         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1983         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1984
1985         if (vnic->func_default)
1986                 req.flags =
1987                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1988         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1989
1990         HWRM_CHECK_RESULT();
1991
1992         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1993         HWRM_UNLOCK();
1994         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1995         return rc;
1996 }
1997
1998 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1999                                         struct bnxt_vnic_info *vnic,
2000                                         struct bnxt_plcmodes_cfg *pmode)
2001 {
2002         int rc = 0;
2003         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2004         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2005
2006         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2007
2008         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2009
2010         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2011
2012         HWRM_CHECK_RESULT();
2013
2014         pmode->flags = rte_le_to_cpu_32(resp->flags);
2015         /* dflt_vnic bit doesn't exist in the _cfg command */
2016         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2017         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2018         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2019         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2020
2021         HWRM_UNLOCK();
2022
2023         return rc;
2024 }
2025
2026 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2027                                        struct bnxt_vnic_info *vnic,
2028                                        struct bnxt_plcmodes_cfg *pmode)
2029 {
2030         int rc = 0;
2031         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2032         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2033
2034         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2035                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2036                 return rc;
2037         }
2038
2039         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2040
2041         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2042         req.flags = rte_cpu_to_le_32(pmode->flags);
2043         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2044         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2045         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2046         req.enables = rte_cpu_to_le_32(
2047             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2048             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2049             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2050         );
2051
2052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2053
2054         HWRM_CHECK_RESULT();
2055         HWRM_UNLOCK();
2056
2057         return rc;
2058 }
2059
2060 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2061 {
2062         int rc = 0;
2063         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2064         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2065         struct bnxt_plcmodes_cfg pmodes = { 0 };
2066         uint32_t ctx_enable_flag = 0;
2067         uint32_t enables = 0;
2068
2069         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2070                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2071                 return rc;
2072         }
2073
2074         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2075         if (rc)
2076                 return rc;
2077
2078         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2079
2080         if (BNXT_CHIP_P5(bp)) {
2081                 int dflt_rxq = vnic->start_grp_id;
2082                 struct bnxt_rx_ring_info *rxr;
2083                 struct bnxt_cp_ring_info *cpr;
2084                 struct bnxt_rx_queue *rxq;
2085                 int i;
2086
2087                 /*
2088                  * The first active receive ring is used as the VNIC
2089                  * default receive ring. If there are no active receive
2090                  * rings (all corresponding receive queues are stopped),
2091                  * the first receive ring is used.
2092                  */
2093                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2094                         rxq = bp->eth_dev->data->rx_queues[i];
2095                         if (rxq->rx_started) {
2096                                 dflt_rxq = i;
2097                                 break;
2098                         }
2099                 }
2100
2101                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2102                 rxr = rxq->rx_ring;
2103                 cpr = rxq->cp_ring;
2104
2105                 req.default_rx_ring_id =
2106                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2107                 req.default_cmpl_ring_id =
2108                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2109                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2110                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2111                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2112                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2113                         req.rx_csum_v2_mode =
2114                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2115                 }
2116                 goto config_mru;
2117         }
2118
2119         /* Only RSS support for now TBD: COS & LB */
2120         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2121         if (vnic->lb_rule != 0xffff)
2122                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2123         if (vnic->cos_rule != 0xffff)
2124                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2125         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2126                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2127                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2128         }
2129         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2130                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2131                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2132         }
2133
2134         enables |= ctx_enable_flag;
2135         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2136         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2137         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2138         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2139
2140 config_mru:
2141         req.enables = rte_cpu_to_le_32(enables);
2142         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2143         req.mru = rte_cpu_to_le_16(vnic->mru);
2144         /* Configure default VNIC only once. */
2145         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2146                 req.flags |=
2147                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2148                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2149         }
2150         if (vnic->vlan_strip)
2151                 req.flags |=
2152                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2153         if (vnic->bd_stall)
2154                 req.flags |=
2155                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2156         if (vnic->rss_dflt_cr)
2157                 req.flags |= rte_cpu_to_le_32(
2158                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2159
2160         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2161
2162         HWRM_CHECK_RESULT();
2163         HWRM_UNLOCK();
2164
2165         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2166
2167         return rc;
2168 }
2169
2170 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2171                 int16_t fw_vf_id)
2172 {
2173         int rc = 0;
2174         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2175         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2176
2177         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2178                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2179                 return rc;
2180         }
2181         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2182
2183         req.enables =
2184                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2185         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2186         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2187
2188         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2189
2190         HWRM_CHECK_RESULT();
2191
2192         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2193         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2194         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2195         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2196         vnic->mru = rte_le_to_cpu_16(resp->mru);
2197         vnic->func_default = rte_le_to_cpu_32(
2198                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2199         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2200                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2201         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2202                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2203         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2204                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2205
2206         HWRM_UNLOCK();
2207
2208         return rc;
2209 }
2210
2211 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2212                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2213 {
2214         int rc = 0;
2215         uint16_t ctx_id;
2216         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2217         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2218                                                 bp->hwrm_cmd_resp_addr;
2219
2220         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2221
2222         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2223         HWRM_CHECK_RESULT();
2224
2225         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2226         if (!BNXT_HAS_RING_GRPS(bp))
2227                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2228         else if (ctx_idx == 0)
2229                 vnic->rss_rule = ctx_id;
2230
2231         HWRM_UNLOCK();
2232
2233         return rc;
2234 }
2235
2236 static
2237 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2238                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2239 {
2240         int rc = 0;
2241         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2242         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2243                                                 bp->hwrm_cmd_resp_addr;
2244
2245         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2246                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2247                 return rc;
2248         }
2249         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2250
2251         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2252
2253         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2254
2255         HWRM_CHECK_RESULT();
2256         HWRM_UNLOCK();
2257
2258         return rc;
2259 }
2260
2261 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2262 {
2263         int rc = 0;
2264
2265         if (BNXT_CHIP_P5(bp)) {
2266                 int j;
2267
2268                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2269                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2270                                                       vnic,
2271                                                       vnic->fw_grp_ids[j]);
2272                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2273                 }
2274                 vnic->num_lb_ctxts = 0;
2275         } else {
2276                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2277                 vnic->rss_rule = INVALID_HW_RING_ID;
2278         }
2279
2280         return rc;
2281 }
2282
2283 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2284 {
2285         int rc = 0;
2286         struct hwrm_vnic_free_input req = {.req_type = 0 };
2287         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2288
2289         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2290                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2291                 return rc;
2292         }
2293
2294         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2295
2296         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2297
2298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2299
2300         HWRM_CHECK_RESULT();
2301         HWRM_UNLOCK();
2302
2303         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2304         /* Configure default VNIC again if necessary. */
2305         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2306                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2307
2308         return rc;
2309 }
2310
2311 static int
2312 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2313 {
2314         int i;
2315         int rc = 0;
2316         int nr_ctxs = vnic->num_lb_ctxts;
2317         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2318         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2319
2320         for (i = 0; i < nr_ctxs; i++) {
2321                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2322
2323                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2324                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2325                 req.hash_mode_flags = vnic->hash_mode;
2326
2327                 req.hash_key_tbl_addr =
2328                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2329
2330                 req.ring_grp_tbl_addr =
2331                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2332                                          i * HW_HASH_INDEX_SIZE);
2333                 req.ring_table_pair_index = i;
2334                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2335
2336                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2337                                             BNXT_USE_CHIMP_MB);
2338
2339                 HWRM_CHECK_RESULT();
2340                 HWRM_UNLOCK();
2341         }
2342
2343         return rc;
2344 }
2345
2346 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2347                            struct bnxt_vnic_info *vnic)
2348 {
2349         int rc = 0;
2350         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2351         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2352
2353         if (!vnic->rss_table)
2354                 return 0;
2355
2356         if (BNXT_CHIP_P5(bp))
2357                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2358
2359         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2360
2361         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2362         req.hash_mode_flags = vnic->hash_mode;
2363
2364         req.ring_grp_tbl_addr =
2365             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2366         req.hash_key_tbl_addr =
2367             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2368         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2369         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2370
2371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2372
2373         HWRM_CHECK_RESULT();
2374         HWRM_UNLOCK();
2375
2376         return rc;
2377 }
2378
2379 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2380                         struct bnxt_vnic_info *vnic)
2381 {
2382         int rc = 0;
2383         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2384         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2385         uint16_t size;
2386
2387         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2388                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2389                 return rc;
2390         }
2391
2392         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2393
2394         req.flags = rte_cpu_to_le_32(
2395                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2396
2397         req.enables = rte_cpu_to_le_32(
2398                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2399
2400         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2401         size -= RTE_PKTMBUF_HEADROOM;
2402         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2403
2404         req.jumbo_thresh = rte_cpu_to_le_16(size);
2405         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2406
2407         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2408
2409         HWRM_CHECK_RESULT();
2410         HWRM_UNLOCK();
2411
2412         return rc;
2413 }
2414
2415 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2416                         struct bnxt_vnic_info *vnic, bool enable)
2417 {
2418         int rc = 0;
2419         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2420         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2421
2422         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2423                 if (enable)
2424                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2425                 return -ENOTSUP;
2426         }
2427
2428         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2429                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2430                 return 0;
2431         }
2432
2433         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2434
2435         if (enable) {
2436                 req.enables = rte_cpu_to_le_32(
2437                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2438                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2439                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2440                 req.flags = rte_cpu_to_le_32(
2441                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2442                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2443                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2444                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2445                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2446                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2447                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2448                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2449                 req.min_agg_len = rte_cpu_to_le_32(512);
2450         }
2451         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2452
2453         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2454
2455         HWRM_CHECK_RESULT();
2456         HWRM_UNLOCK();
2457
2458         return rc;
2459 }
2460
2461 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2462 {
2463         struct hwrm_func_cfg_input req = {0};
2464         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2465         int rc;
2466
2467         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2468         req.enables = rte_cpu_to_le_32(
2469                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2470         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2471         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2472
2473         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2474
2475         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2476         HWRM_CHECK_RESULT();
2477         HWRM_UNLOCK();
2478
2479         bp->pf->vf_info[vf].random_mac = false;
2480
2481         return rc;
2482 }
2483
2484 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2485                                   uint64_t *dropped)
2486 {
2487         int rc = 0;
2488         struct hwrm_func_qstats_input req = {.req_type = 0};
2489         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2490
2491         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2492
2493         req.fid = rte_cpu_to_le_16(fid);
2494
2495         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2496
2497         HWRM_CHECK_RESULT();
2498
2499         if (dropped)
2500                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2501
2502         HWRM_UNLOCK();
2503
2504         return rc;
2505 }
2506
2507 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2508                           struct rte_eth_stats *stats,
2509                           struct hwrm_func_qstats_output *func_qstats)
2510 {
2511         int rc = 0;
2512         struct hwrm_func_qstats_input req = {.req_type = 0};
2513         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2514
2515         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2516
2517         req.fid = rte_cpu_to_le_16(fid);
2518
2519         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2520
2521         HWRM_CHECK_RESULT();
2522         if (func_qstats)
2523                 memcpy(func_qstats, resp,
2524                        sizeof(struct hwrm_func_qstats_output));
2525
2526         if (!stats)
2527                 goto exit;
2528
2529         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2530         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2531         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2532         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2533         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2534         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2535
2536         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2537         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2538         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2539         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2540         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2541         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2542
2543         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2544         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2545         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2546
2547 exit:
2548         HWRM_UNLOCK();
2549
2550         return rc;
2551 }
2552
2553 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2554 {
2555         int rc = 0;
2556         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2557         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2558
2559         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2560
2561         req.fid = rte_cpu_to_le_16(fid);
2562
2563         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2564
2565         HWRM_CHECK_RESULT();
2566         HWRM_UNLOCK();
2567
2568         return rc;
2569 }
2570
2571 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2572 {
2573         unsigned int i;
2574         int rc = 0;
2575
2576         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2577                 struct bnxt_tx_queue *txq;
2578                 struct bnxt_rx_queue *rxq;
2579                 struct bnxt_cp_ring_info *cpr;
2580
2581                 if (i >= bp->rx_cp_nr_rings) {
2582                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2583                         cpr = txq->cp_ring;
2584                 } else {
2585                         rxq = bp->rx_queues[i];
2586                         cpr = rxq->cp_ring;
2587                 }
2588
2589                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2590                 if (rc)
2591                         return rc;
2592         }
2593         return 0;
2594 }
2595
2596 static int
2597 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2598 {
2599         int rc;
2600         unsigned int i;
2601         struct bnxt_cp_ring_info *cpr;
2602
2603         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2604
2605                 if (i >= bp->rx_cp_nr_rings) {
2606                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2607                 } else {
2608                         cpr = bp->rx_queues[i]->cp_ring;
2609                         if (BNXT_HAS_RING_GRPS(bp))
2610                                 bp->grp_info[i].fw_stats_ctx = -1;
2611                 }
2612                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2613                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2614                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2615                         if (rc)
2616                                 return rc;
2617                 }
2618         }
2619         return 0;
2620 }
2621
2622 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2623 {
2624         unsigned int i;
2625         int rc = 0;
2626
2627         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2628                 struct bnxt_tx_queue *txq;
2629                 struct bnxt_rx_queue *rxq;
2630                 struct bnxt_cp_ring_info *cpr;
2631
2632                 if (i >= bp->rx_cp_nr_rings) {
2633                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2634                         cpr = txq->cp_ring;
2635                 } else {
2636                         rxq = bp->rx_queues[i];
2637                         cpr = rxq->cp_ring;
2638                 }
2639
2640                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2641
2642                 if (rc)
2643                         return rc;
2644         }
2645         return rc;
2646 }
2647
2648 static int
2649 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2650 {
2651         uint16_t idx;
2652         uint32_t rc = 0;
2653
2654         if (!BNXT_HAS_RING_GRPS(bp))
2655                 return 0;
2656
2657         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2658
2659                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2660                         continue;
2661
2662                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2663
2664                 if (rc)
2665                         return rc;
2666         }
2667         return rc;
2668 }
2669
2670 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2671 {
2672         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2673
2674         bnxt_hwrm_ring_free(bp, cp_ring,
2675                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2676                             INVALID_HW_RING_ID);
2677         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2678         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2679                                      sizeof(*cpr->cp_desc_ring));
2680         cpr->cp_raw_cons = 0;
2681 }
2682
2683 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2684 {
2685         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2686
2687         bnxt_hwrm_ring_free(bp, cp_ring,
2688                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2689                         INVALID_HW_RING_ID);
2690         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2691         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2692                         sizeof(*cpr->cp_desc_ring));
2693         cpr->cp_raw_cons = 0;
2694 }
2695
2696 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2697 {
2698         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2699         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2700         struct bnxt_ring *ring = rxr->rx_ring_struct;
2701         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2702
2703         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2704                 bnxt_hwrm_ring_free(bp, ring,
2705                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2706                                     cpr->cp_ring_struct->fw_ring_id);
2707                 ring->fw_ring_id = INVALID_HW_RING_ID;
2708                 if (BNXT_HAS_RING_GRPS(bp))
2709                         bp->grp_info[queue_index].rx_fw_ring_id =
2710                                                         INVALID_HW_RING_ID;
2711         }
2712         ring = rxr->ag_ring_struct;
2713         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2714                 bnxt_hwrm_ring_free(bp, ring,
2715                                     BNXT_CHIP_P5(bp) ?
2716                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2717                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2718                                     cpr->cp_ring_struct->fw_ring_id);
2719                 if (BNXT_HAS_RING_GRPS(bp))
2720                         bp->grp_info[queue_index].ag_fw_ring_id =
2721                                                         INVALID_HW_RING_ID;
2722         }
2723         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2724                 bnxt_free_cp_ring(bp, cpr);
2725
2726         if (BNXT_HAS_RING_GRPS(bp))
2727                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2728 }
2729
2730 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2731 {
2732         int rc;
2733         struct hwrm_ring_reset_input req = {.req_type = 0 };
2734         struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2735
2736         HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2737
2738         req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2739         req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2740         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2741
2742         HWRM_CHECK_RESULT();
2743
2744         HWRM_UNLOCK();
2745
2746         return rc;
2747 }
2748
2749 static int
2750 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2751 {
2752         unsigned int i;
2753
2754         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2755                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2756                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2757                 struct bnxt_ring *ring = txr->tx_ring_struct;
2758                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2759
2760                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2761                         bnxt_hwrm_ring_free(bp, ring,
2762                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX,
2763                                         cpr->cp_ring_struct->fw_ring_id);
2764                         ring->fw_ring_id = INVALID_HW_RING_ID;
2765                         memset(txr->tx_desc_ring, 0,
2766                                         txr->tx_ring_struct->ring_size *
2767                                         sizeof(*txr->tx_desc_ring));
2768                         memset(txr->tx_buf_ring, 0,
2769                                         txr->tx_ring_struct->ring_size *
2770                                         sizeof(*txr->tx_buf_ring));
2771                         txr->tx_raw_prod = 0;
2772                         txr->tx_raw_cons = 0;
2773                 }
2774                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2775                         bnxt_free_cp_ring(bp, cpr);
2776                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2777                 }
2778         }
2779
2780         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2781                 bnxt_free_hwrm_rx_ring(bp, i);
2782
2783         return 0;
2784 }
2785
2786 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2787 {
2788         uint16_t i;
2789         uint32_t rc = 0;
2790
2791         if (!BNXT_HAS_RING_GRPS(bp))
2792                 return 0;
2793
2794         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2795                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2796                 if (rc)
2797                         return rc;
2798         }
2799         return rc;
2800 }
2801
2802 /*
2803  * HWRM utility functions
2804  */
2805
2806 void bnxt_free_hwrm_resources(struct bnxt *bp)
2807 {
2808         /* Release memzone */
2809         rte_free(bp->hwrm_cmd_resp_addr);
2810         rte_free(bp->hwrm_short_cmd_req_addr);
2811         bp->hwrm_cmd_resp_addr = NULL;
2812         bp->hwrm_short_cmd_req_addr = NULL;
2813         bp->hwrm_cmd_resp_dma_addr = 0;
2814         bp->hwrm_short_cmd_req_dma_addr = 0;
2815 }
2816
2817 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2818 {
2819         struct rte_pci_device *pdev = bp->pdev;
2820         char type[RTE_MEMZONE_NAMESIZE];
2821
2822         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2823                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2824         bp->max_resp_len = BNXT_PAGE_SIZE;
2825         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2826         if (bp->hwrm_cmd_resp_addr == NULL)
2827                 return -ENOMEM;
2828         bp->hwrm_cmd_resp_dma_addr =
2829                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2830         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2831                 PMD_DRV_LOG(ERR,
2832                         "unable to map response address to physical memory\n");
2833                 return -ENOMEM;
2834         }
2835         rte_spinlock_init(&bp->hwrm_lock);
2836
2837         return 0;
2838 }
2839
2840 int
2841 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2842 {
2843         int rc = 0;
2844
2845         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2846                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2847                 if (rc)
2848                         return rc;
2849         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2850                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2851                 if (rc)
2852                         return rc;
2853         }
2854
2855         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2856         return rc;
2857 }
2858
2859 static int
2860 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2861 {
2862         struct bnxt_filter_info *filter;
2863         int rc = 0;
2864
2865         STAILQ_FOREACH(filter, &vnic->filter, next) {
2866                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2867                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2868                 bnxt_free_filter(bp, filter);
2869         }
2870         return rc;
2871 }
2872
2873 static int
2874 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2875 {
2876         struct bnxt_filter_info *filter;
2877         struct rte_flow *flow;
2878         int rc = 0;
2879
2880         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2881                 flow = STAILQ_FIRST(&vnic->flow_list);
2882                 filter = flow->filter;
2883                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2884                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2885
2886                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2887                 rte_free(flow);
2888         }
2889         return rc;
2890 }
2891
2892 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2893 {
2894         struct bnxt_filter_info *filter;
2895         int rc = 0;
2896
2897         STAILQ_FOREACH(filter, &vnic->filter, next) {
2898                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2899                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2900                                                      filter);
2901                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2902                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2903                                                          filter);
2904                 else
2905                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2906                                                      filter);
2907                 if (rc)
2908                         break;
2909         }
2910         return rc;
2911 }
2912
2913 static void
2914 bnxt_free_tunnel_ports(struct bnxt *bp)
2915 {
2916         if (bp->vxlan_port_cnt)
2917                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2918                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2919
2920         if (bp->geneve_port_cnt)
2921                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2922                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2923 }
2924
2925 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2926 {
2927         int i;
2928
2929         if (bp->vnic_info == NULL)
2930                 return;
2931
2932         /*
2933          * Cleanup VNICs in reverse order, to make sure the L2 filter
2934          * from vnic0 is last to be cleaned up.
2935          */
2936         for (i = bp->max_vnics - 1; i >= 0; i--) {
2937                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2938
2939                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2940                         continue;
2941
2942                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2943
2944                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2945
2946                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2947
2948                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2949
2950                 bnxt_hwrm_vnic_free(bp, vnic);
2951
2952                 rte_free(vnic->fw_grp_ids);
2953         }
2954         /* Ring resources */
2955         bnxt_free_all_hwrm_rings(bp);
2956         bnxt_free_all_hwrm_ring_grps(bp);
2957         bnxt_free_all_hwrm_stat_ctxs(bp);
2958         bnxt_free_tunnel_ports(bp);
2959 }
2960
2961 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2962 {
2963         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2964
2965         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2966                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2967
2968         switch (conf_link_speed) {
2969         case ETH_LINK_SPEED_10M_HD:
2970         case ETH_LINK_SPEED_100M_HD:
2971                 /* FALLTHROUGH */
2972                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2973         }
2974         return hw_link_duplex;
2975 }
2976
2977 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2978 {
2979         return !conf_link;
2980 }
2981
2982 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2983                                           uint16_t pam4_link)
2984 {
2985         uint16_t eth_link_speed = 0;
2986
2987         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2988                 return ETH_LINK_SPEED_AUTONEG;
2989
2990         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2991         case ETH_LINK_SPEED_100M:
2992         case ETH_LINK_SPEED_100M_HD:
2993                 /* FALLTHROUGH */
2994                 eth_link_speed =
2995                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2996                 break;
2997         case ETH_LINK_SPEED_1G:
2998                 eth_link_speed =
2999                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
3000                 break;
3001         case ETH_LINK_SPEED_2_5G:
3002                 eth_link_speed =
3003                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
3004                 break;
3005         case ETH_LINK_SPEED_10G:
3006                 eth_link_speed =
3007                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
3008                 break;
3009         case ETH_LINK_SPEED_20G:
3010                 eth_link_speed =
3011                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3012                 break;
3013         case ETH_LINK_SPEED_25G:
3014                 eth_link_speed =
3015                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3016                 break;
3017         case ETH_LINK_SPEED_40G:
3018                 eth_link_speed =
3019                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3020                 break;
3021         case ETH_LINK_SPEED_50G:
3022                 eth_link_speed = pam4_link ?
3023                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3024                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3025                 break;
3026         case ETH_LINK_SPEED_100G:
3027                 eth_link_speed = pam4_link ?
3028                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3029                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3030                 break;
3031         case ETH_LINK_SPEED_200G:
3032                 eth_link_speed =
3033                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3034                 break;
3035         default:
3036                 PMD_DRV_LOG(ERR,
3037                         "Unsupported link speed %d; default to AUTO\n",
3038                         conf_link_speed);
3039                 break;
3040         }
3041         return eth_link_speed;
3042 }
3043
3044 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3045                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3046                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3047                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3048                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3049
3050 static int bnxt_validate_link_speed(struct bnxt *bp)
3051 {
3052         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3053         uint16_t port_id = bp->eth_dev->data->port_id;
3054         uint32_t link_speed_capa;
3055         uint32_t one_speed;
3056
3057         if (link_speed == ETH_LINK_SPEED_AUTONEG)
3058                 return 0;
3059
3060         link_speed_capa = bnxt_get_speed_capabilities(bp);
3061
3062         if (link_speed & ETH_LINK_SPEED_FIXED) {
3063                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3064
3065                 if (one_speed & (one_speed - 1)) {
3066                         PMD_DRV_LOG(ERR,
3067                                 "Invalid advertised speeds (%u) for port %u\n",
3068                                 link_speed, port_id);
3069                         return -EINVAL;
3070                 }
3071                 if ((one_speed & link_speed_capa) != one_speed) {
3072                         PMD_DRV_LOG(ERR,
3073                                 "Unsupported advertised speed (%u) for port %u\n",
3074                                 link_speed, port_id);
3075                         return -EINVAL;
3076                 }
3077         } else {
3078                 if (!(link_speed & link_speed_capa)) {
3079                         PMD_DRV_LOG(ERR,
3080                                 "Unsupported advertised speeds (%u) for port %u\n",
3081                                 link_speed, port_id);
3082                         return -EINVAL;
3083                 }
3084         }
3085         return 0;
3086 }
3087
3088 static uint16_t
3089 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3090 {
3091         uint16_t ret = 0;
3092
3093         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3094                 if (bp->link_info->support_speeds)
3095                         return bp->link_info->support_speeds;
3096                 link_speed = BNXT_SUPPORTED_SPEEDS;
3097         }
3098
3099         if (link_speed & ETH_LINK_SPEED_100M)
3100                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3101         if (link_speed & ETH_LINK_SPEED_100M_HD)
3102                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3103         if (link_speed & ETH_LINK_SPEED_1G)
3104                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3105         if (link_speed & ETH_LINK_SPEED_2_5G)
3106                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3107         if (link_speed & ETH_LINK_SPEED_10G)
3108                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3109         if (link_speed & ETH_LINK_SPEED_20G)
3110                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3111         if (link_speed & ETH_LINK_SPEED_25G)
3112                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3113         if (link_speed & ETH_LINK_SPEED_40G)
3114                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3115         if (link_speed & ETH_LINK_SPEED_50G)
3116                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3117         if (link_speed & ETH_LINK_SPEED_100G)
3118                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3119         if (link_speed & ETH_LINK_SPEED_200G)
3120                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3121         return ret;
3122 }
3123
3124 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3125 {
3126         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3127
3128         switch (hw_link_speed) {
3129         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3130                 eth_link_speed = ETH_SPEED_NUM_100M;
3131                 break;
3132         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3133                 eth_link_speed = ETH_SPEED_NUM_1G;
3134                 break;
3135         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3136                 eth_link_speed = ETH_SPEED_NUM_2_5G;
3137                 break;
3138         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3139                 eth_link_speed = ETH_SPEED_NUM_10G;
3140                 break;
3141         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3142                 eth_link_speed = ETH_SPEED_NUM_20G;
3143                 break;
3144         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3145                 eth_link_speed = ETH_SPEED_NUM_25G;
3146                 break;
3147         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3148                 eth_link_speed = ETH_SPEED_NUM_40G;
3149                 break;
3150         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3151                 eth_link_speed = ETH_SPEED_NUM_50G;
3152                 break;
3153         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3154                 eth_link_speed = ETH_SPEED_NUM_100G;
3155                 break;
3156         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3157                 eth_link_speed = ETH_SPEED_NUM_200G;
3158                 break;
3159         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3160         default:
3161                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3162                         hw_link_speed);
3163                 break;
3164         }
3165         return eth_link_speed;
3166 }
3167
3168 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3169 {
3170         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3171
3172         switch (hw_link_duplex) {
3173         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3174         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3175                 /* FALLTHROUGH */
3176                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3177                 break;
3178         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3179                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3180                 break;
3181         default:
3182                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3183                         hw_link_duplex);
3184                 break;
3185         }
3186         return eth_link_duplex;
3187 }
3188
3189 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3190 {
3191         int rc = 0;
3192         struct bnxt_link_info *link_info = bp->link_info;
3193
3194         rc = bnxt_hwrm_port_phy_qcaps(bp);
3195         if (rc)
3196                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3197
3198         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3199         if (rc) {
3200                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3201                 goto exit;
3202         }
3203
3204         if (link_info->link_speed)
3205                 link->link_speed =
3206                         bnxt_parse_hw_link_speed(link_info->link_speed);
3207         else
3208                 link->link_speed = ETH_SPEED_NUM_NONE;
3209         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3210         link->link_status = link_info->link_up;
3211         link->link_autoneg = link_info->auto_mode ==
3212                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3213                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3214 exit:
3215         return rc;
3216 }
3217
3218 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3219 {
3220         int rc = 0;
3221         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3222         struct bnxt_link_info link_req;
3223         uint16_t speed, autoneg;
3224
3225         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3226                 return 0;
3227
3228         rc = bnxt_validate_link_speed(bp);
3229         if (rc)
3230                 goto error;
3231
3232         memset(&link_req, 0, sizeof(link_req));
3233         link_req.link_up = link_up;
3234         if (!link_up)
3235                 goto port_phy_cfg;
3236
3237         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3238         if (BNXT_CHIP_P5(bp) &&
3239             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3240                 /* 40G is not supported as part of media auto detect.
3241                  * The speed should be forced and autoneg disabled
3242                  * to configure 40G speed.
3243                  */
3244                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3245                 autoneg = 0;
3246         }
3247
3248         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3249         if (bp->link_info->auto_link_speed == 0 &&
3250             bp->link_info->link_signal_mode &&
3251             bp->link_info->auto_pam4_link_speeds == 0)
3252                 autoneg = 0;
3253
3254         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3255                                           bp->link_info->link_signal_mode);
3256         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3257         /* Autoneg can be done only when the FW allows. */
3258         if (autoneg == 1 && bp->link_info->support_auto_speeds) {
3259                 link_req.phy_flags |=
3260                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3261                 link_req.auto_link_speed_mask =
3262                         bnxt_parse_eth_link_speed_mask(bp,
3263                                                        dev_conf->link_speeds);
3264         } else {
3265                 if (bp->link_info->phy_type ==
3266                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3267                     bp->link_info->phy_type ==
3268                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3269                     bp->link_info->media_type ==
3270                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3271                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3272                         return -EINVAL;
3273                 }
3274
3275                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3276                 /* If user wants a particular speed try that first. */
3277                 if (speed)
3278                         link_req.link_speed = speed;
3279                 else if (bp->link_info->force_pam4_link_speed)
3280                         link_req.link_speed =
3281                                 bp->link_info->force_pam4_link_speed;
3282                 else if (bp->link_info->auto_pam4_link_speeds)
3283                         link_req.link_speed =
3284                                 bp->link_info->auto_pam4_link_speeds;
3285                 else if (bp->link_info->support_pam4_speeds)
3286                         link_req.link_speed =
3287                                 bp->link_info->support_pam4_speeds;
3288                 else if (bp->link_info->force_link_speed)
3289                         link_req.link_speed = bp->link_info->force_link_speed;
3290                 else
3291                         link_req.link_speed = bp->link_info->auto_link_speed;
3292                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3293                  * zero. Use the auto_link_speed.
3294                  */
3295                 if (bp->link_info->auto_link_speed != 0 &&
3296                     bp->link_info->auto_pam4_link_speeds == 0)
3297                         link_req.link_speed = bp->link_info->auto_link_speed;
3298         }
3299         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3300         link_req.auto_pause = bp->link_info->auto_pause;
3301         link_req.force_pause = bp->link_info->force_pause;
3302
3303 port_phy_cfg:
3304         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3305         if (rc) {
3306                 PMD_DRV_LOG(ERR,
3307                         "Set link config failed with rc %d\n", rc);
3308         }
3309
3310 error:
3311         return rc;
3312 }
3313
3314 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3315 {
3316         struct hwrm_func_qcfg_input req = {0};
3317         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3318         uint16_t flags;
3319         int rc = 0;
3320         bp->func_svif = BNXT_SVIF_INVALID;
3321         uint16_t svif_info;
3322
3323         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3324         req.fid = rte_cpu_to_le_16(0xffff);
3325
3326         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3327
3328         HWRM_CHECK_RESULT();
3329
3330         bp->vlan = rte_le_to_cpu_16(resp->vlan) & ETH_VLAN_ID_MAX;
3331
3332         svif_info = rte_le_to_cpu_16(resp->svif_info);
3333         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3334                 bp->func_svif = svif_info &
3335                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3336
3337         flags = rte_le_to_cpu_16(resp->flags);
3338         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3339                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3340
3341         if (BNXT_VF(bp) &&
3342             !BNXT_VF_IS_TRUSTED(bp) &&
3343             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3344                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3345                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3346         } else if (BNXT_VF(bp) &&
3347                    BNXT_VF_IS_TRUSTED(bp) &&
3348                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3349                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3350                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3351         }
3352
3353         if (mtu)
3354                 *mtu = rte_le_to_cpu_16(resp->mtu);
3355
3356         switch (resp->port_partition_type) {
3357         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3358         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3359         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3360                 /* FALLTHROUGH */
3361                 bp->flags |= BNXT_FLAG_NPAR_PF;
3362                 break;
3363         default:
3364                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3365                 break;
3366         }
3367
3368         bp->legacy_db_size =
3369                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3370
3371         HWRM_UNLOCK();
3372
3373         return rc;
3374 }
3375
3376 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3377 {
3378         struct hwrm_func_qcfg_input req = {0};
3379         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3380         int rc;
3381
3382         if (!BNXT_VF_IS_TRUSTED(bp))
3383                 return 0;
3384
3385         if (!bp->parent)
3386                 return -EINVAL;
3387
3388         bp->parent->fid = BNXT_PF_FID_INVALID;
3389
3390         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3391
3392         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3393
3394         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3395
3396         HWRM_CHECK_RESULT_SILENT();
3397
3398         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3399         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3400         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3401         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3402
3403         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3404         if (bp->parent->vnic == 0) {
3405                 PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
3406                 /* Use hard-coded values appropriate for current Wh+ fw. */
3407                 if (bp->parent->fid == 2)
3408                         bp->parent->vnic = 0x100;
3409                 else
3410                         bp->parent->vnic = 1;
3411         }
3412
3413         HWRM_UNLOCK();
3414
3415         return 0;
3416 }
3417
3418 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3419                                  uint16_t *vnic_id, uint16_t *svif)
3420 {
3421         struct hwrm_func_qcfg_input req = {0};
3422         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3423         uint16_t svif_info;
3424         int rc = 0;
3425
3426         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3427         req.fid = rte_cpu_to_le_16(fid);
3428
3429         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3430
3431         HWRM_CHECK_RESULT();
3432
3433         if (vnic_id)
3434                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3435
3436         svif_info = rte_le_to_cpu_16(resp->svif_info);
3437         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3438                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3439
3440         HWRM_UNLOCK();
3441
3442         return rc;
3443 }
3444
3445 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3446 {
3447         struct hwrm_port_mac_qcfg_input req = {0};
3448         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3449         uint16_t port_svif_info;
3450         int rc;
3451
3452         bp->port_svif = BNXT_SVIF_INVALID;
3453
3454         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3455                 return 0;
3456
3457         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3458
3459         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3460
3461         HWRM_CHECK_RESULT_SILENT();
3462
3463         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3464         if (port_svif_info &
3465             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3466                 bp->port_svif = port_svif_info &
3467                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3468
3469         HWRM_UNLOCK();
3470
3471         return 0;
3472 }
3473
3474 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3475                                  struct bnxt_pf_resource_info *pf_resc)
3476 {
3477         struct hwrm_func_cfg_input req = {0};
3478         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3479         uint32_t enables;
3480         int rc;
3481
3482         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3483                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3484                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3485                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3486                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3487                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3488                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3489                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3490                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3491
3492         if (BNXT_HAS_RING_GRPS(bp)) {
3493                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3494                 req.num_hw_ring_grps =
3495                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3496         } else if (BNXT_HAS_NQ(bp)) {
3497                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3498                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3499         }
3500
3501         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3502         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3503         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3504         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3505         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3506         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3507         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3508         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3509         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3510         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3511         req.fid = rte_cpu_to_le_16(0xffff);
3512         req.enables = rte_cpu_to_le_32(enables);
3513
3514         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3515
3516         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3517
3518         HWRM_CHECK_RESULT();
3519         HWRM_UNLOCK();
3520
3521         return rc;
3522 }
3523
3524 /* min values are the guaranteed resources and max values are subject
3525  * to availability. The strategy for now is to keep both min & max
3526  * values the same.
3527  */
3528 static void
3529 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3530                               struct hwrm_func_vf_resource_cfg_input *req,
3531                               int num_vfs)
3532 {
3533         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3534                                                (num_vfs + 1));
3535         req->min_rsscos_ctx = req->max_rsscos_ctx;
3536         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3537         req->min_stat_ctx = req->max_stat_ctx;
3538         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3539                                                (num_vfs + 1));
3540         req->min_cmpl_rings = req->max_cmpl_rings;
3541         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3542         req->min_tx_rings = req->max_tx_rings;
3543         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3544         req->min_rx_rings = req->max_rx_rings;
3545         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3546         req->min_l2_ctxs = req->max_l2_ctxs;
3547         /* TODO: For now, do not support VMDq/RFS on VFs. */
3548         req->max_vnics = rte_cpu_to_le_16(1);
3549         req->min_vnics = req->max_vnics;
3550         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3551                                                  (num_vfs + 1));
3552         req->min_hw_ring_grps = req->max_hw_ring_grps;
3553         req->flags =
3554          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3555 }
3556
3557 static void
3558 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3559                               struct hwrm_func_cfg_input *req,
3560                               int num_vfs)
3561 {
3562         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3563                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3564                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3565                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3566                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3567                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3568                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3569                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3570                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3571                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3572
3573         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3574                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3575                                     BNXT_NUM_VLANS);
3576         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3577         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3578                                                 (num_vfs + 1));
3579         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3580         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3581                                                (num_vfs + 1));
3582         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3583         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3584         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3585         /* TODO: For now, do not support VMDq/RFS on VFs. */
3586         req->num_vnics = rte_cpu_to_le_16(1);
3587         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3588                                                  (num_vfs + 1));
3589 }
3590
3591 /* Update the port wide resource values based on how many resources
3592  * got allocated to the VF.
3593  */
3594 static int bnxt_update_max_resources(struct bnxt *bp,
3595                                      int vf)
3596 {
3597         struct hwrm_func_qcfg_input req = {0};
3598         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3599         int rc;
3600
3601         /* Get the actual allocated values now */
3602         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3603         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3604         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3605         HWRM_CHECK_RESULT();
3606
3607         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3608         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3609         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3610         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3611         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3612         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3613         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3614
3615         HWRM_UNLOCK();
3616
3617         return 0;
3618 }
3619
3620 /* Update the PF resource values based on how many resources
3621  * got allocated to it.
3622  */
3623 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3624 {
3625         struct hwrm_func_qcfg_input req = {0};
3626         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3627         int rc;
3628
3629         /* Get the actual allocated values now */
3630         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3631         req.fid = rte_cpu_to_le_16(0xffff);
3632         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3633         HWRM_CHECK_RESULT();
3634
3635         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3636         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3637         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3638         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3639         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3640         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3641         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3642         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3643
3644         HWRM_UNLOCK();
3645
3646         return 0;
3647 }
3648
3649 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3650 {
3651         struct hwrm_func_qcfg_input req = {0};
3652         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3653         int rc;
3654
3655         /* Check for zero MAC address */
3656         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3657         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3658         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3659         HWRM_CHECK_RESULT();
3660         rc = rte_le_to_cpu_16(resp->vlan);
3661
3662         HWRM_UNLOCK();
3663
3664         return rc;
3665 }
3666
3667 static int bnxt_query_pf_resources(struct bnxt *bp,
3668                                    struct bnxt_pf_resource_info *pf_resc)
3669 {
3670         struct hwrm_func_qcfg_input req = {0};
3671         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3672         int rc;
3673
3674         /* And copy the allocated numbers into the pf struct */
3675         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3676         req.fid = rte_cpu_to_le_16(0xffff);
3677         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3678         HWRM_CHECK_RESULT();
3679
3680         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3681         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3682         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3683         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3684         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3685         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3686         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3687         bp->pf->evb_mode = resp->evb_mode;
3688
3689         HWRM_UNLOCK();
3690
3691         return rc;
3692 }
3693
3694 static void
3695 bnxt_calculate_pf_resources(struct bnxt *bp,
3696                             struct bnxt_pf_resource_info *pf_resc,
3697                             int num_vfs)
3698 {
3699         if (!num_vfs) {
3700                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3701                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3702                 pf_resc->num_cp_rings = bp->max_cp_rings;
3703                 pf_resc->num_tx_rings = bp->max_tx_rings;
3704                 pf_resc->num_rx_rings = bp->max_rx_rings;
3705                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3706                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3707
3708                 return;
3709         }
3710
3711         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3712                                    bp->max_rsscos_ctx % (num_vfs + 1);
3713         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3714                                  bp->max_stat_ctx % (num_vfs + 1);
3715         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3716                                 bp->max_cp_rings % (num_vfs + 1);
3717         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3718                                 bp->max_tx_rings % (num_vfs + 1);
3719         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3720                                 bp->max_rx_rings % (num_vfs + 1);
3721         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3722                                bp->max_l2_ctx % (num_vfs + 1);
3723         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3724                                     bp->max_ring_grps % (num_vfs + 1);
3725 }
3726
3727 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3728 {
3729         struct bnxt_pf_resource_info pf_resc = { 0 };
3730         int rc;
3731
3732         if (!BNXT_PF(bp)) {
3733                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3734                 return -EINVAL;
3735         }
3736
3737         rc = bnxt_hwrm_func_qcaps(bp);
3738         if (rc)
3739                 return rc;
3740
3741         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3742
3743         bp->pf->func_cfg_flags &=
3744                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3745                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3746         bp->pf->func_cfg_flags |=
3747                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3748
3749         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3750         if (rc)
3751                 return rc;
3752
3753         rc = bnxt_update_max_resources_pf_only(bp);
3754
3755         return rc;
3756 }
3757
3758 static int
3759 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3760 {
3761         size_t req_buf_sz, sz;
3762         int i, rc;
3763
3764         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3765         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3766                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3767         if (bp->pf->vf_req_buf == NULL) {
3768                 return -ENOMEM;
3769         }
3770
3771         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3772                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3773
3774         for (i = 0; i < num_vfs; i++)
3775                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3776                                              (i * HWRM_MAX_REQ_LEN);
3777
3778         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3779         if (rc)
3780                 rte_free(bp->pf->vf_req_buf);
3781
3782         return rc;
3783 }
3784
3785 static int
3786 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3787 {
3788         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3789         struct hwrm_func_vf_resource_cfg_input req = {0};
3790         int i, rc = 0;
3791
3792         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3793         bp->pf->active_vfs = 0;
3794         for (i = 0; i < num_vfs; i++) {
3795                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3796                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3797                 rc = bnxt_hwrm_send_message(bp,
3798                                             &req,
3799                                             sizeof(req),
3800                                             BNXT_USE_CHIMP_MB);
3801                 if (rc || resp->error_code) {
3802                         PMD_DRV_LOG(ERR,
3803                                 "Failed to initialize VF %d\n", i);
3804                         PMD_DRV_LOG(ERR,
3805                                 "Not all VFs available. (%d, %d)\n",
3806                                 rc, resp->error_code);
3807                         HWRM_UNLOCK();
3808
3809                         /* If the first VF configuration itself fails,
3810                          * unregister the vf_fwd_request buffer.
3811                          */
3812                         if (i == 0)
3813                                 bnxt_hwrm_func_buf_unrgtr(bp);
3814                         break;
3815                 }
3816                 HWRM_UNLOCK();
3817
3818                 /* Update the max resource values based on the resource values
3819                  * allocated to the VF.
3820                  */
3821                 bnxt_update_max_resources(bp, i);
3822                 bp->pf->active_vfs++;
3823                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3824         }
3825
3826         return 0;
3827 }
3828
3829 static int
3830 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3831 {
3832         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3833         struct hwrm_func_cfg_input req = {0};
3834         int i, rc;
3835
3836         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3837
3838         bp->pf->active_vfs = 0;
3839         for (i = 0; i < num_vfs; i++) {
3840                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3841                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3842                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3843                 rc = bnxt_hwrm_send_message(bp,
3844                                             &req,
3845                                             sizeof(req),
3846                                             BNXT_USE_CHIMP_MB);
3847
3848                 /* Clear enable flag for next pass */
3849                 req.enables &= ~rte_cpu_to_le_32(
3850                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3851
3852                 if (rc || resp->error_code) {
3853                         PMD_DRV_LOG(ERR,
3854                                 "Failed to initialize VF %d\n", i);
3855                         PMD_DRV_LOG(ERR,
3856                                 "Not all VFs available. (%d, %d)\n",
3857                                 rc, resp->error_code);
3858                         HWRM_UNLOCK();
3859
3860                         /* If the first VF configuration itself fails,
3861                          * unregister the vf_fwd_request buffer.
3862                          */
3863                         if (i == 0)
3864                                 bnxt_hwrm_func_buf_unrgtr(bp);
3865                         break;
3866                 }
3867
3868                 HWRM_UNLOCK();
3869
3870                 /* Update the max resource values based on the resource values
3871                  * allocated to the VF.
3872                  */
3873                 bnxt_update_max_resources(bp, i);
3874                 bp->pf->active_vfs++;
3875                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3876         }
3877
3878         return 0;
3879 }
3880
3881 static void
3882 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3883 {
3884         if (bp->flags & BNXT_FLAG_NEW_RM)
3885                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3886         else
3887                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3888 }
3889
3890 static void
3891 bnxt_update_pf_resources(struct bnxt *bp,
3892                          struct bnxt_pf_resource_info *pf_resc)
3893 {
3894         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3895         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3896         bp->max_cp_rings = pf_resc->num_cp_rings;
3897         bp->max_tx_rings = pf_resc->num_tx_rings;
3898         bp->max_rx_rings = pf_resc->num_rx_rings;
3899         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3900 }
3901
3902 static int32_t
3903 bnxt_configure_pf_resources(struct bnxt *bp,
3904                             struct bnxt_pf_resource_info *pf_resc)
3905 {
3906         /*
3907          * We're using STD_TX_RING_MODE here which will limit the TX
3908          * rings. This will allow QoS to function properly. Not setting this
3909          * will cause PF rings to break bandwidth settings.
3910          */
3911         bp->pf->func_cfg_flags &=
3912                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3913                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3914         bp->pf->func_cfg_flags |=
3915                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3916         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3917 }
3918
3919 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3920 {
3921         struct bnxt_pf_resource_info pf_resc = { 0 };
3922         int rc;
3923
3924         if (!BNXT_PF(bp)) {
3925                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3926                 return -EINVAL;
3927         }
3928
3929         rc = bnxt_hwrm_func_qcaps(bp);
3930         if (rc)
3931                 return rc;
3932
3933         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3934
3935         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3936         if (rc)
3937                 return rc;
3938
3939         rc = bnxt_query_pf_resources(bp, &pf_resc);
3940         if (rc)
3941                 return rc;
3942
3943         /*
3944          * Now, create and register a buffer to hold forwarded VF requests
3945          */
3946         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3947         if (rc)
3948                 return rc;
3949
3950         bnxt_configure_vf_resources(bp, num_vfs);
3951
3952         bnxt_update_pf_resources(bp, &pf_resc);
3953
3954         return 0;
3955 }
3956
3957 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3958 {
3959         struct hwrm_func_cfg_input req = {0};
3960         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3961         int rc;
3962
3963         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3964
3965         req.fid = rte_cpu_to_le_16(0xffff);
3966         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3967         req.evb_mode = bp->pf->evb_mode;
3968
3969         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3970         HWRM_CHECK_RESULT();
3971         HWRM_UNLOCK();
3972
3973         return rc;
3974 }
3975
3976 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3977                                 uint8_t tunnel_type)
3978 {
3979         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3980         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3981         int rc = 0;
3982
3983         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3984         req.tunnel_type = tunnel_type;
3985         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3986         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3987         HWRM_CHECK_RESULT();
3988
3989         switch (tunnel_type) {
3990         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3991                 bp->vxlan_fw_dst_port_id =
3992                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3993                 bp->vxlan_port = port;
3994                 break;
3995         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3996                 bp->geneve_fw_dst_port_id =
3997                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3998                 bp->geneve_port = port;
3999                 break;
4000         default:
4001                 break;
4002         }
4003
4004         HWRM_UNLOCK();
4005
4006         return rc;
4007 }
4008
4009 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4010                                 uint8_t tunnel_type)
4011 {
4012         struct hwrm_tunnel_dst_port_free_input req = {0};
4013         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4014         int rc = 0;
4015
4016         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4017
4018         req.tunnel_type = tunnel_type;
4019         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4020         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4021
4022         HWRM_CHECK_RESULT();
4023         HWRM_UNLOCK();
4024
4025         if (tunnel_type ==
4026             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4027                 bp->vxlan_port = 0;
4028                 bp->vxlan_port_cnt = 0;
4029         }
4030
4031         if (tunnel_type ==
4032             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4033                 bp->geneve_port = 0;
4034                 bp->geneve_port_cnt = 0;
4035         }
4036
4037         return rc;
4038 }
4039
4040 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4041                                         uint32_t flags)
4042 {
4043         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4044         struct hwrm_func_cfg_input req = {0};
4045         int rc;
4046
4047         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4048
4049         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4050         req.flags = rte_cpu_to_le_32(flags);
4051         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4052
4053         HWRM_CHECK_RESULT();
4054         HWRM_UNLOCK();
4055
4056         return rc;
4057 }
4058
4059 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4060 {
4061         uint32_t *flag = flagp;
4062
4063         vnic->flags = *flag;
4064 }
4065
4066 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4067 {
4068         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4069 }
4070
4071 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4072 {
4073         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4074         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4075         int rc;
4076
4077         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4078
4079         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4080         req.req_buf_page_size =
4081                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4082         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4083         req.req_buf_page_addr0 =
4084                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4085         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4086                 PMD_DRV_LOG(ERR,
4087                         "unable to map buffer address to physical memory\n");
4088                 HWRM_UNLOCK();
4089                 return -ENOMEM;
4090         }
4091
4092         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4093
4094         HWRM_CHECK_RESULT();
4095         HWRM_UNLOCK();
4096
4097         return rc;
4098 }
4099
4100 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4101 {
4102         int rc = 0;
4103         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4104         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4105
4106         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4107                 return 0;
4108
4109         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4110
4111         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4112
4113         HWRM_CHECK_RESULT();
4114         HWRM_UNLOCK();
4115
4116         return rc;
4117 }
4118
4119 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4120 {
4121         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4122         struct hwrm_func_cfg_input req = {0};
4123         int rc;
4124
4125         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4126
4127         req.fid = rte_cpu_to_le_16(0xffff);
4128         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4129         req.enables = rte_cpu_to_le_32(
4130                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4131         req.async_event_cr = rte_cpu_to_le_16(
4132                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4133         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4134
4135         HWRM_CHECK_RESULT();
4136         HWRM_UNLOCK();
4137
4138         return rc;
4139 }
4140
4141 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4142 {
4143         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4144         struct hwrm_func_vf_cfg_input req = {0};
4145         int rc;
4146
4147         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4148
4149         req.enables = rte_cpu_to_le_32(
4150                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4151         req.async_event_cr = rte_cpu_to_le_16(
4152                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4153         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4154
4155         HWRM_CHECK_RESULT();
4156         HWRM_UNLOCK();
4157
4158         return rc;
4159 }
4160
4161 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4162 {
4163         struct hwrm_func_cfg_input req = {0};
4164         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4165         uint16_t dflt_vlan, fid;
4166         uint32_t func_cfg_flags;
4167         int rc = 0;
4168
4169         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4170
4171         if (is_vf) {
4172                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4173                 fid = bp->pf->vf_info[vf].fid;
4174                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4175         } else {
4176                 fid = rte_cpu_to_le_16(0xffff);
4177                 func_cfg_flags = bp->pf->func_cfg_flags;
4178                 dflt_vlan = bp->vlan;
4179         }
4180
4181         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4182         req.fid = rte_cpu_to_le_16(fid);
4183         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4184         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4185
4186         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4187
4188         HWRM_CHECK_RESULT();
4189         HWRM_UNLOCK();
4190
4191         return rc;
4192 }
4193
4194 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4195                         uint16_t max_bw, uint16_t enables)
4196 {
4197         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4198         struct hwrm_func_cfg_input req = {0};
4199         int rc;
4200
4201         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4202
4203         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4204         req.enables |= rte_cpu_to_le_32(enables);
4205         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4206         req.max_bw = rte_cpu_to_le_32(max_bw);
4207         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4208
4209         HWRM_CHECK_RESULT();
4210         HWRM_UNLOCK();
4211
4212         return rc;
4213 }
4214
4215 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4216 {
4217         struct hwrm_func_cfg_input req = {0};
4218         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4219         int rc = 0;
4220
4221         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4222
4223         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4224         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4225         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4226         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4227
4228         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4229
4230         HWRM_CHECK_RESULT();
4231         HWRM_UNLOCK();
4232
4233         return rc;
4234 }
4235
4236 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4237 {
4238         int rc;
4239
4240         if (BNXT_PF(bp))
4241                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4242         else
4243                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4244
4245         return rc;
4246 }
4247
4248 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4249                               void *encaped, size_t ec_size)
4250 {
4251         int rc = 0;
4252         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4253         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4254
4255         if (ec_size > sizeof(req.encap_request))
4256                 return -1;
4257
4258         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4259
4260         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4261         memcpy(req.encap_request, encaped, ec_size);
4262
4263         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4264
4265         HWRM_CHECK_RESULT();
4266         HWRM_UNLOCK();
4267
4268         return rc;
4269 }
4270
4271 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4272                                        struct rte_ether_addr *mac)
4273 {
4274         struct hwrm_func_qcfg_input req = {0};
4275         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4276         int rc;
4277
4278         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4279
4280         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4281         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4282
4283         HWRM_CHECK_RESULT();
4284
4285         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4286
4287         HWRM_UNLOCK();
4288
4289         return rc;
4290 }
4291
4292 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4293                             void *encaped, size_t ec_size)
4294 {
4295         int rc = 0;
4296         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4297         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4298
4299         if (ec_size > sizeof(req.encap_request))
4300                 return -1;
4301
4302         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4303
4304         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4305         memcpy(req.encap_request, encaped, ec_size);
4306
4307         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4308
4309         HWRM_CHECK_RESULT();
4310         HWRM_UNLOCK();
4311
4312         return rc;
4313 }
4314
4315 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4316 {
4317         /* One of the HW stat values that make up this counter was zero as
4318          * returned by HW in this iteration, so use the previous
4319          * iteration's counter value
4320          */
4321         if (*prev_cntr && *cntr == 0)
4322                 *cntr = *prev_cntr;
4323         else
4324                 *prev_cntr = *cntr;
4325 }
4326
4327 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4328                          struct bnxt_ring_stats *ring_stats, bool rx)
4329 {
4330         int rc = 0;
4331         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4332         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4333
4334         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4335
4336         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4337
4338         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4339
4340         HWRM_CHECK_RESULT();
4341
4342         if (rx) {
4343                 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4344
4345                 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4346                 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4347                                       &prev_stats->rx_ucast_pkts);
4348
4349                 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4350                 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4351                                       &prev_stats->rx_mcast_pkts);
4352
4353                 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4354                 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4355                                       &prev_stats->rx_bcast_pkts);
4356
4357                 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4358                 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4359                                       &prev_stats->rx_ucast_bytes);
4360
4361                 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4362                 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4363                                       &prev_stats->rx_mcast_bytes);
4364
4365                 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4366                 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4367                                       &prev_stats->rx_bcast_bytes);
4368
4369                 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4370                 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4371                                       &prev_stats->rx_discard_pkts);
4372
4373                 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4374                 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4375                                       &prev_stats->rx_error_pkts);
4376
4377                 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4378                 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4379                                       &prev_stats->rx_agg_pkts);
4380
4381                 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4382                 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4383                                       &prev_stats->rx_agg_bytes);
4384
4385                 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4386                 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4387                                       &prev_stats->rx_agg_events);
4388
4389                 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4390                 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4391                                       &prev_stats->rx_agg_aborts);
4392         } else {
4393                 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4394
4395                 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4396                 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4397                                       &prev_stats->tx_ucast_pkts);
4398
4399                 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4400                 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4401                                       &prev_stats->tx_mcast_pkts);
4402
4403                 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4404                 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4405                                       &prev_stats->tx_bcast_pkts);
4406
4407                 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4408                 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4409                                       &prev_stats->tx_ucast_bytes);
4410
4411                 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4412                 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4413                                       &prev_stats->tx_mcast_bytes);
4414
4415                 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4416                 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4417                                       &prev_stats->tx_bcast_bytes);
4418
4419                 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4420                 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4421                                       &prev_stats->tx_discard_pkts);
4422         }
4423
4424         HWRM_UNLOCK();
4425
4426         return rc;
4427 }
4428
4429 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4430 {
4431         struct hwrm_port_qstats_input req = {0};
4432         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4433         struct bnxt_pf_info *pf = bp->pf;
4434         int rc;
4435
4436         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4437
4438         req.port_id = rte_cpu_to_le_16(pf->port_id);
4439         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4440         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4441         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4442
4443         HWRM_CHECK_RESULT();
4444         HWRM_UNLOCK();
4445
4446         return rc;
4447 }
4448
4449 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4450 {
4451         struct hwrm_port_clr_stats_input req = {0};
4452         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4453         struct bnxt_pf_info *pf = bp->pf;
4454         int rc;
4455
4456         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4457         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4458             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4459                 return 0;
4460
4461         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4462
4463         req.port_id = rte_cpu_to_le_16(pf->port_id);
4464         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4465
4466         HWRM_CHECK_RESULT();
4467         HWRM_UNLOCK();
4468
4469         return rc;
4470 }
4471
4472 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4473 {
4474         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4475         struct hwrm_port_led_qcaps_input req = {0};
4476         int rc;
4477
4478         if (BNXT_VF(bp))
4479                 return 0;
4480
4481         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4482         req.port_id = bp->pf->port_id;
4483         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4484
4485         HWRM_CHECK_RESULT_SILENT();
4486
4487         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4488                 unsigned int i;
4489
4490                 bp->leds->num_leds = resp->num_leds;
4491                 memcpy(bp->leds, &resp->led0_id,
4492                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4493                 for (i = 0; i < bp->leds->num_leds; i++) {
4494                         struct bnxt_led_info *led = &bp->leds[i];
4495
4496                         uint16_t caps = led->led_state_caps;
4497
4498                         if (!led->led_group_id ||
4499                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4500                                 bp->leds->num_leds = 0;
4501                                 break;
4502                         }
4503                 }
4504         }
4505
4506         HWRM_UNLOCK();
4507
4508         return rc;
4509 }
4510
4511 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4512 {
4513         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4514         struct hwrm_port_led_cfg_input req = {0};
4515         struct bnxt_led_cfg *led_cfg;
4516         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4517         uint16_t duration = 0;
4518         int rc, i;
4519
4520         if (!bp->leds->num_leds || BNXT_VF(bp))
4521                 return -EOPNOTSUPP;
4522
4523         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4524
4525         if (led_on) {
4526                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4527                 duration = rte_cpu_to_le_16(500);
4528         }
4529         req.port_id = bp->pf->port_id;
4530         req.num_leds = bp->leds->num_leds;
4531         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4532         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4533                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4534                 led_cfg->led_id = bp->leds[i].led_id;
4535                 led_cfg->led_state = led_state;
4536                 led_cfg->led_blink_on = duration;
4537                 led_cfg->led_blink_off = duration;
4538                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4539         }
4540
4541         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4542
4543         HWRM_CHECK_RESULT();
4544         HWRM_UNLOCK();
4545
4546         return rc;
4547 }
4548
4549 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4550                                uint32_t *length)
4551 {
4552         int rc;
4553         struct hwrm_nvm_get_dir_info_input req = {0};
4554         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4555
4556         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4557
4558         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4559
4560         HWRM_CHECK_RESULT();
4561
4562         *entries = rte_le_to_cpu_32(resp->entries);
4563         *length = rte_le_to_cpu_32(resp->entry_length);
4564
4565         HWRM_UNLOCK();
4566         return rc;
4567 }
4568
4569 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4570 {
4571         int rc;
4572         uint32_t dir_entries;
4573         uint32_t entry_length;
4574         uint8_t *buf;
4575         size_t buflen;
4576         rte_iova_t dma_handle;
4577         struct hwrm_nvm_get_dir_entries_input req = {0};
4578         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4579
4580         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4581         if (rc != 0)
4582                 return rc;
4583
4584         *data++ = dir_entries;
4585         *data++ = entry_length;
4586         len -= 2;
4587         memset(data, 0xff, len);
4588
4589         buflen = dir_entries * entry_length;
4590         buf = rte_malloc("nvm_dir", buflen, 0);
4591         if (buf == NULL)
4592                 return -ENOMEM;
4593         dma_handle = rte_malloc_virt2iova(buf);
4594         if (dma_handle == RTE_BAD_IOVA) {
4595                 rte_free(buf);
4596                 PMD_DRV_LOG(ERR,
4597                         "unable to map response address to physical memory\n");
4598                 return -ENOMEM;
4599         }
4600         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4601         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4602         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4603
4604         if (rc == 0)
4605                 memcpy(data, buf, len > buflen ? buflen : len);
4606
4607         rte_free(buf);
4608         HWRM_CHECK_RESULT();
4609         HWRM_UNLOCK();
4610
4611         return rc;
4612 }
4613
4614 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4615                              uint32_t offset, uint32_t length,
4616                              uint8_t *data)
4617 {
4618         int rc;
4619         uint8_t *buf;
4620         rte_iova_t dma_handle;
4621         struct hwrm_nvm_read_input req = {0};
4622         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4623
4624         buf = rte_malloc("nvm_item", length, 0);
4625         if (!buf)
4626                 return -ENOMEM;
4627
4628         dma_handle = rte_malloc_virt2iova(buf);
4629         if (dma_handle == RTE_BAD_IOVA) {
4630                 rte_free(buf);
4631                 PMD_DRV_LOG(ERR,
4632                         "unable to map response address to physical memory\n");
4633                 return -ENOMEM;
4634         }
4635         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4636         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4637         req.dir_idx = rte_cpu_to_le_16(index);
4638         req.offset = rte_cpu_to_le_32(offset);
4639         req.len = rte_cpu_to_le_32(length);
4640         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4641         if (rc == 0)
4642                 memcpy(data, buf, length);
4643
4644         rte_free(buf);
4645         HWRM_CHECK_RESULT();
4646         HWRM_UNLOCK();
4647
4648         return rc;
4649 }
4650
4651 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4652 {
4653         int rc;
4654         struct hwrm_nvm_erase_dir_entry_input req = {0};
4655         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4656
4657         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4658         req.dir_idx = rte_cpu_to_le_16(index);
4659         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4660         HWRM_CHECK_RESULT();
4661         HWRM_UNLOCK();
4662
4663         return rc;
4664 }
4665
4666 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4667                           uint16_t dir_ordinal, uint16_t dir_ext,
4668                           uint16_t dir_attr, const uint8_t *data,
4669                           size_t data_len)
4670 {
4671         int rc;
4672         struct hwrm_nvm_write_input req = {0};
4673         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4674         rte_iova_t dma_handle;
4675         uint8_t *buf;
4676
4677         buf = rte_malloc("nvm_write", data_len, 0);
4678         if (!buf)
4679                 return -ENOMEM;
4680
4681         dma_handle = rte_malloc_virt2iova(buf);
4682         if (dma_handle == RTE_BAD_IOVA) {
4683                 rte_free(buf);
4684                 PMD_DRV_LOG(ERR,
4685                         "unable to map response address to physical memory\n");
4686                 return -ENOMEM;
4687         }
4688         memcpy(buf, data, data_len);
4689
4690         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4691
4692         req.dir_type = rte_cpu_to_le_16(dir_type);
4693         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4694         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4695         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4696         req.dir_data_length = rte_cpu_to_le_32(data_len);
4697         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4698
4699         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4700
4701         rte_free(buf);
4702         HWRM_CHECK_RESULT();
4703         HWRM_UNLOCK();
4704
4705         return rc;
4706 }
4707
4708 static void
4709 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4710 {
4711         uint32_t *count = cbdata;
4712
4713         *count = *count + 1;
4714 }
4715
4716 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4717                                      struct bnxt_vnic_info *vnic __rte_unused)
4718 {
4719         return 0;
4720 }
4721
4722 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4723 {
4724         uint32_t count = 0;
4725
4726         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4727             &count, bnxt_vnic_count_hwrm_stub);
4728
4729         return count;
4730 }
4731
4732 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4733                                         uint16_t *vnic_ids)
4734 {
4735         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4736         struct hwrm_func_vf_vnic_ids_query_output *resp =
4737                                                 bp->hwrm_cmd_resp_addr;
4738         int rc;
4739
4740         /* First query all VNIC ids */
4741         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4742
4743         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4744         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4745         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4746
4747         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4748                 HWRM_UNLOCK();
4749                 PMD_DRV_LOG(ERR,
4750                 "unable to map VNIC ID table address to physical memory\n");
4751                 return -ENOMEM;
4752         }
4753         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4754         HWRM_CHECK_RESULT();
4755         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4756
4757         HWRM_UNLOCK();
4758
4759         return rc;
4760 }
4761
4762 /*
4763  * This function queries the VNIC IDs  for a specified VF. It then calls
4764  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4765  * Then it calls the hwrm_cb function to program this new vnic configuration.
4766  */
4767 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4768         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4769         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4770 {
4771         struct bnxt_vnic_info vnic;
4772         int rc = 0;
4773         int i, num_vnic_ids;
4774         uint16_t *vnic_ids;
4775         size_t vnic_id_sz;
4776         size_t sz;
4777
4778         /* First query all VNIC ids */
4779         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4780         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4781                         RTE_CACHE_LINE_SIZE);
4782         if (vnic_ids == NULL)
4783                 return -ENOMEM;
4784
4785         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4786                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4787
4788         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4789
4790         if (num_vnic_ids < 0)
4791                 return num_vnic_ids;
4792
4793         /* Retrieve VNIC, update bd_stall then update */
4794
4795         for (i = 0; i < num_vnic_ids; i++) {
4796                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4797                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4798                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4799                 if (rc)
4800                         break;
4801                 if (vnic.mru <= 4)      /* Indicates unallocated */
4802                         continue;
4803
4804                 vnic_cb(&vnic, cbdata);
4805
4806                 rc = hwrm_cb(bp, &vnic);
4807                 if (rc)
4808                         break;
4809         }
4810
4811         rte_free(vnic_ids);
4812
4813         return rc;
4814 }
4815
4816 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4817                                               bool on)
4818 {
4819         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4820         struct hwrm_func_cfg_input req = {0};
4821         int rc;
4822
4823         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4824
4825         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4826         req.enables |= rte_cpu_to_le_32(
4827                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4828         req.vlan_antispoof_mode = on ?
4829                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4830                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4831         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4832
4833         HWRM_CHECK_RESULT();
4834         HWRM_UNLOCK();
4835
4836         return rc;
4837 }
4838
4839 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4840 {
4841         struct bnxt_vnic_info vnic;
4842         uint16_t *vnic_ids;
4843         size_t vnic_id_sz;
4844         int num_vnic_ids, i;
4845         size_t sz;
4846         int rc;
4847
4848         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4849         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4850                         RTE_CACHE_LINE_SIZE);
4851         if (vnic_ids == NULL)
4852                 return -ENOMEM;
4853
4854         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4855                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4856
4857         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4858         if (rc <= 0)
4859                 goto exit;
4860         num_vnic_ids = rc;
4861
4862         /*
4863          * Loop through to find the default VNIC ID.
4864          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4865          * by sending the hwrm_func_qcfg command to the firmware.
4866          */
4867         for (i = 0; i < num_vnic_ids; i++) {
4868                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4869                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4870                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4871                                         bp->pf->first_vf_id + vf);
4872                 if (rc)
4873                         goto exit;
4874                 if (vnic.func_default) {
4875                         rte_free(vnic_ids);
4876                         return vnic.fw_vnic_id;
4877                 }
4878         }
4879         /* Could not find a default VNIC. */
4880         PMD_DRV_LOG(ERR, "No default VNIC\n");
4881 exit:
4882         rte_free(vnic_ids);
4883         return rc;
4884 }
4885
4886 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4887                          uint16_t dst_id,
4888                          struct bnxt_filter_info *filter)
4889 {
4890         int rc = 0;
4891         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4892         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4893         uint32_t enables = 0;
4894
4895         if (filter->fw_em_filter_id != UINT64_MAX)
4896                 bnxt_hwrm_clear_em_filter(bp, filter);
4897
4898         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4899
4900         req.flags = rte_cpu_to_le_32(filter->flags);
4901
4902         enables = filter->enables |
4903               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4904         req.dst_id = rte_cpu_to_le_16(dst_id);
4905
4906         if (filter->ip_addr_type) {
4907                 req.ip_addr_type = filter->ip_addr_type;
4908                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4909         }
4910         if (enables &
4911             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4912                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4913         if (enables &
4914             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4915                 memcpy(req.src_macaddr, filter->src_macaddr,
4916                        RTE_ETHER_ADDR_LEN);
4917         if (enables &
4918             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4919                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4920                        RTE_ETHER_ADDR_LEN);
4921         if (enables &
4922             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4923                 req.ovlan_vid = filter->l2_ovlan;
4924         if (enables &
4925             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4926                 req.ivlan_vid = filter->l2_ivlan;
4927         if (enables &
4928             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4929                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4930         if (enables &
4931             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4932                 req.ip_protocol = filter->ip_protocol;
4933         if (enables &
4934             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4935                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4936         if (enables &
4937             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4938                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4939         if (enables &
4940             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4941                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4942         if (enables &
4943             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4944                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4945         if (enables &
4946             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4947                 req.mirror_vnic_id = filter->mirror_vnic_id;
4948
4949         req.enables = rte_cpu_to_le_32(enables);
4950
4951         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4952
4953         HWRM_CHECK_RESULT();
4954
4955         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4956         HWRM_UNLOCK();
4957
4958         return rc;
4959 }
4960
4961 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4962 {
4963         int rc = 0;
4964         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4965         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4966
4967         if (filter->fw_em_filter_id == UINT64_MAX)
4968                 return 0;
4969
4970         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4971
4972         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4973
4974         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4975
4976         HWRM_CHECK_RESULT();
4977         HWRM_UNLOCK();
4978
4979         filter->fw_em_filter_id = UINT64_MAX;
4980         filter->fw_l2_filter_id = UINT64_MAX;
4981
4982         return 0;
4983 }
4984
4985 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4986                          uint16_t dst_id,
4987                          struct bnxt_filter_info *filter)
4988 {
4989         int rc = 0;
4990         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4991         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4992                                                 bp->hwrm_cmd_resp_addr;
4993         uint32_t enables = 0;
4994
4995         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4996                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4997
4998         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4999
5000         req.flags = rte_cpu_to_le_32(filter->flags);
5001
5002         enables = filter->enables |
5003               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
5004         req.dst_id = rte_cpu_to_le_16(dst_id);
5005
5006         if (filter->ip_addr_type) {
5007                 req.ip_addr_type = filter->ip_addr_type;
5008                 enables |=
5009                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
5010         }
5011         if (enables &
5012             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5013                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5014         if (enables &
5015             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5016                 memcpy(req.src_macaddr, filter->src_macaddr,
5017                        RTE_ETHER_ADDR_LEN);
5018         if (enables &
5019             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5020                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5021         if (enables &
5022             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5023                 req.ip_protocol = filter->ip_protocol;
5024         if (enables &
5025             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5026                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5027         if (enables &
5028             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5029                 req.src_ipaddr_mask[0] =
5030                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5031         if (enables &
5032             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5033                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5034         if (enables &
5035             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5036                 req.dst_ipaddr_mask[0] =
5037                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5038         if (enables &
5039             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5040                 req.src_port = rte_cpu_to_le_16(filter->src_port);
5041         if (enables &
5042             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5043                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5044         if (enables &
5045             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5046                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5047         if (enables &
5048             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5049                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5050         if (enables &
5051             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5052                 req.mirror_vnic_id = filter->mirror_vnic_id;
5053
5054         req.enables = rte_cpu_to_le_32(enables);
5055
5056         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5057
5058         HWRM_CHECK_RESULT();
5059
5060         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5061         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5062         HWRM_UNLOCK();
5063
5064         return rc;
5065 }
5066
5067 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5068                                 struct bnxt_filter_info *filter)
5069 {
5070         int rc = 0;
5071         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5072         struct hwrm_cfa_ntuple_filter_free_output *resp =
5073                                                 bp->hwrm_cmd_resp_addr;
5074
5075         if (filter->fw_ntuple_filter_id == UINT64_MAX)
5076                 return 0;
5077
5078         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5079
5080         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5081
5082         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5083
5084         HWRM_CHECK_RESULT();
5085         HWRM_UNLOCK();
5086
5087         filter->fw_ntuple_filter_id = UINT64_MAX;
5088
5089         return 0;
5090 }
5091
5092 static int
5093 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5094 {
5095         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5096         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
5097         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5098         struct bnxt_rx_queue **rxqs = bp->rx_queues;
5099         uint16_t *ring_tbl = vnic->rss_table;
5100         int nr_ctxs = vnic->num_lb_ctxts;
5101         int max_rings = bp->rx_nr_rings;
5102         int i, j, k, cnt;
5103         int rc = 0;
5104
5105         for (i = 0, k = 0; i < nr_ctxs; i++) {
5106                 struct bnxt_rx_ring_info *rxr;
5107                 struct bnxt_cp_ring_info *cpr;
5108
5109                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5110
5111                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5112                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5113                 req.hash_mode_flags = vnic->hash_mode;
5114
5115                 req.ring_grp_tbl_addr =
5116                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5117                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5118                                      2 * sizeof(*ring_tbl));
5119                 req.hash_key_tbl_addr =
5120                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5121
5122                 req.ring_table_pair_index = i;
5123                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5124
5125                 for (j = 0; j < 64; j++) {
5126                         uint16_t ring_id;
5127
5128                         /* Find next active ring. */
5129                         for (cnt = 0; cnt < max_rings; cnt++) {
5130                                 if (rx_queue_state[k] !=
5131                                                 RTE_ETH_QUEUE_STATE_STOPPED)
5132                                         break;
5133                                 if (++k == max_rings)
5134                                         k = 0;
5135                         }
5136
5137                         /* Return if no rings are active. */
5138                         if (cnt == max_rings) {
5139                                 HWRM_UNLOCK();
5140                                 return 0;
5141                         }
5142
5143                         /* Add rx/cp ring pair to RSS table. */
5144                         rxr = rxqs[k]->rx_ring;
5145                         cpr = rxqs[k]->cp_ring;
5146
5147                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5148                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5149                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5150                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5151
5152                         if (++k == max_rings)
5153                                 k = 0;
5154                 }
5155                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5156                                             BNXT_USE_CHIMP_MB);
5157
5158                 HWRM_CHECK_RESULT();
5159                 HWRM_UNLOCK();
5160         }
5161
5162         return rc;
5163 }
5164
5165 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5166 {
5167         unsigned int rss_idx, fw_idx, i;
5168
5169         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5170                 return 0;
5171
5172         if (!(vnic->rss_table && vnic->hash_type))
5173                 return 0;
5174
5175         if (BNXT_CHIP_P5(bp))
5176                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5177
5178         /*
5179          * Fill the RSS hash & redirection table with
5180          * ring group ids for all VNICs
5181          */
5182         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5183              rss_idx++, fw_idx++) {
5184                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5185                         fw_idx %= bp->rx_cp_nr_rings;
5186                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5187                                 break;
5188                         fw_idx++;
5189                 }
5190
5191                 if (i == bp->rx_cp_nr_rings)
5192                         return 0;
5193
5194                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5195         }
5196
5197         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5198 }
5199
5200 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5201         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5202 {
5203         uint16_t flags;
5204
5205         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5206
5207         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5208         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5209
5210         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5211         req->num_cmpl_dma_aggr_during_int =
5212                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5213
5214         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5215
5216         /* min timer set to 1/2 of interrupt timer */
5217         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5218
5219         /* buf timer set to 1/4 of interrupt timer */
5220         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5221
5222         req->cmpl_aggr_dma_tmr_during_int =
5223                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5224
5225         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5226                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5227         req->flags = rte_cpu_to_le_16(flags);
5228 }
5229
5230 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5231                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5232 {
5233         struct hwrm_ring_aggint_qcaps_input req = {0};
5234         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5235         uint32_t enables;
5236         uint16_t flags;
5237         int rc;
5238
5239         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5240         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5241         HWRM_CHECK_RESULT();
5242
5243         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5244         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5245
5246         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5247                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5248         agg_req->flags = rte_cpu_to_le_16(flags);
5249         enables =
5250          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5251          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5252         agg_req->enables = rte_cpu_to_le_32(enables);
5253
5254         HWRM_UNLOCK();
5255         return rc;
5256 }
5257
5258 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5259                         struct bnxt_coal *coal, uint16_t ring_id)
5260 {
5261         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5262         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5263                                                 bp->hwrm_cmd_resp_addr;
5264         int rc;
5265
5266         /* Set ring coalesce parameters only for 100G NICs */
5267         if (BNXT_CHIP_P5(bp)) {
5268                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5269                         return -1;
5270         } else if (bnxt_stratus_device(bp)) {
5271                 bnxt_hwrm_set_coal_params(coal, &req);
5272         } else {
5273                 return 0;
5274         }
5275
5276         HWRM_PREP(&req,
5277                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5278                   BNXT_USE_CHIMP_MB);
5279         req.ring_id = rte_cpu_to_le_16(ring_id);
5280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5281         HWRM_CHECK_RESULT();
5282         HWRM_UNLOCK();
5283         return 0;
5284 }
5285
5286 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5287 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5288 {
5289         struct hwrm_func_backing_store_qcaps_input req = {0};
5290         struct hwrm_func_backing_store_qcaps_output *resp =
5291                 bp->hwrm_cmd_resp_addr;
5292         struct bnxt_ctx_pg_info *ctx_pg;
5293         struct bnxt_ctx_mem_info *ctx;
5294         int total_alloc_len;
5295         int rc, i, tqm_rings;
5296
5297         if (!BNXT_CHIP_P5(bp) ||
5298             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5299             BNXT_VF(bp) ||
5300             bp->ctx)
5301                 return 0;
5302
5303         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5304         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5305         HWRM_CHECK_RESULT_SILENT();
5306
5307         total_alloc_len = sizeof(*ctx);
5308         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5309                           RTE_CACHE_LINE_SIZE);
5310         if (!ctx) {
5311                 rc = -ENOMEM;
5312                 goto ctx_err;
5313         }
5314
5315         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5316         ctx->qp_min_qp1_entries =
5317                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5318         ctx->qp_max_l2_entries =
5319                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5320         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5321         ctx->srq_max_l2_entries =
5322                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5323         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5324         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5325         ctx->cq_max_l2_entries =
5326                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5327         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5328         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5329         ctx->vnic_max_vnic_entries =
5330                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5331         ctx->vnic_max_ring_table_entries =
5332                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5333         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5334         ctx->stat_max_entries =
5335                 rte_le_to_cpu_32(resp->stat_max_entries);
5336         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5337         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5338         ctx->tqm_min_entries_per_ring =
5339                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5340         ctx->tqm_max_entries_per_ring =
5341                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5342         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5343         if (!ctx->tqm_entries_multiple)
5344                 ctx->tqm_entries_multiple = 1;
5345         ctx->mrav_max_entries =
5346                 rte_le_to_cpu_32(resp->mrav_max_entries);
5347         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5348         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5349         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5350         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5351
5352         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5353                                   RTE_MIN(ctx->tqm_fp_rings_count,
5354                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5355                                   bp->max_q;
5356
5357         /* Check if the ext ring count needs to be counted.
5358          * Ext ring count is available only with new FW so we should not
5359          * look at the field on older FW.
5360          */
5361         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5362             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5363                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5364                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5365                                                   ctx->tqm_fp_rings_count);
5366         }
5367
5368         tqm_rings = ctx->tqm_fp_rings_count + 1;
5369
5370         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5371                             sizeof(*ctx_pg) * tqm_rings,
5372                             RTE_CACHE_LINE_SIZE);
5373         if (!ctx_pg) {
5374                 rc = -ENOMEM;
5375                 goto ctx_err;
5376         }
5377         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5378                 ctx->tqm_mem[i] = ctx_pg;
5379
5380         bp->ctx = ctx;
5381 ctx_err:
5382         HWRM_UNLOCK();
5383         return rc;
5384 }
5385
5386 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5387 {
5388         struct hwrm_func_backing_store_cfg_input req = {0};
5389         struct hwrm_func_backing_store_cfg_output *resp =
5390                 bp->hwrm_cmd_resp_addr;
5391         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5392         struct bnxt_ctx_pg_info *ctx_pg;
5393         uint32_t *num_entries;
5394         uint64_t *pg_dir;
5395         uint8_t *pg_attr;
5396         uint32_t ena;
5397         int i, rc;
5398
5399         if (!ctx)
5400                 return 0;
5401
5402         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5403         req.enables = rte_cpu_to_le_32(enables);
5404
5405         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5406                 ctx_pg = &ctx->qp_mem;
5407                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5408                 req.qp_num_qp1_entries =
5409                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5410                 req.qp_num_l2_entries =
5411                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5412                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5413                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5414                                       &req.qpc_pg_size_qpc_lvl,
5415                                       &req.qpc_page_dir);
5416         }
5417
5418         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5419                 ctx_pg = &ctx->srq_mem;
5420                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5421                 req.srq_num_l2_entries =
5422                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5423                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5424                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5425                                       &req.srq_pg_size_srq_lvl,
5426                                       &req.srq_page_dir);
5427         }
5428
5429         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5430                 ctx_pg = &ctx->cq_mem;
5431                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5432                 req.cq_num_l2_entries =
5433                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5434                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5435                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5436                                       &req.cq_pg_size_cq_lvl,
5437                                       &req.cq_page_dir);
5438         }
5439
5440         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5441                 ctx_pg = &ctx->vnic_mem;
5442                 req.vnic_num_vnic_entries =
5443                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5444                 req.vnic_num_ring_table_entries =
5445                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5446                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5447                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5448                                       &req.vnic_pg_size_vnic_lvl,
5449                                       &req.vnic_page_dir);
5450         }
5451
5452         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5453                 ctx_pg = &ctx->stat_mem;
5454                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5455                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5456                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5457                                       &req.stat_pg_size_stat_lvl,
5458                                       &req.stat_page_dir);
5459         }
5460
5461         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5462         num_entries = &req.tqm_sp_num_entries;
5463         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5464         pg_dir = &req.tqm_sp_page_dir;
5465         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5466         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5467                 if (!(enables & ena))
5468                         continue;
5469
5470                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5471
5472                 ctx_pg = ctx->tqm_mem[i];
5473                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5474                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5475         }
5476
5477         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5478                 /* DPDK does not need to configure MRAV and TIM type.
5479                  * So we are skipping over MRAV and TIM. Skip to configure
5480                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5481                  */
5482                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5483                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5484                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5485                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5486                                       &req.tqm_ring8_page_dir);
5487         }
5488
5489         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5490         HWRM_CHECK_RESULT();
5491         HWRM_UNLOCK();
5492
5493         return rc;
5494 }
5495
5496 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5497 {
5498         struct hwrm_port_qstats_ext_input req = {0};
5499         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5500         struct bnxt_pf_info *pf = bp->pf;
5501         int rc;
5502
5503         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5504               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5505                 return 0;
5506
5507         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5508
5509         req.port_id = rte_cpu_to_le_16(pf->port_id);
5510         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5511                 req.tx_stat_host_addr =
5512                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5513                 req.tx_stat_size =
5514                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5515         }
5516         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5517                 req.rx_stat_host_addr =
5518                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5519                 req.rx_stat_size =
5520                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5521         }
5522         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5523
5524         if (rc) {
5525                 bp->fw_rx_port_stats_ext_size = 0;
5526                 bp->fw_tx_port_stats_ext_size = 0;
5527         } else {
5528                 bp->fw_rx_port_stats_ext_size =
5529                         rte_le_to_cpu_16(resp->rx_stat_size);
5530                 bp->fw_tx_port_stats_ext_size =
5531                         rte_le_to_cpu_16(resp->tx_stat_size);
5532         }
5533
5534         HWRM_CHECK_RESULT();
5535         HWRM_UNLOCK();
5536
5537         return rc;
5538 }
5539
5540 int
5541 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5542 {
5543         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5544         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5545                 bp->hwrm_cmd_resp_addr;
5546         int rc = 0;
5547
5548         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5549         req.tunnel_type = type;
5550         req.dest_fid = bp->fw_fid;
5551         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5552         HWRM_CHECK_RESULT();
5553
5554         HWRM_UNLOCK();
5555
5556         return rc;
5557 }
5558
5559 int
5560 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5561 {
5562         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5563         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5564                 bp->hwrm_cmd_resp_addr;
5565         int rc = 0;
5566
5567         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5568         req.tunnel_type = type;
5569         req.dest_fid = bp->fw_fid;
5570         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5571         HWRM_CHECK_RESULT();
5572
5573         HWRM_UNLOCK();
5574
5575         return rc;
5576 }
5577
5578 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5579 {
5580         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5581         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5582                 bp->hwrm_cmd_resp_addr;
5583         int rc = 0;
5584
5585         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5586         req.src_fid = bp->fw_fid;
5587         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5588         HWRM_CHECK_RESULT();
5589
5590         if (type)
5591                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5592
5593         HWRM_UNLOCK();
5594
5595         return rc;
5596 }
5597
5598 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5599                                    uint16_t *dst_fid)
5600 {
5601         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5602         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5603                 bp->hwrm_cmd_resp_addr;
5604         int rc = 0;
5605
5606         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5607         req.src_fid = bp->fw_fid;
5608         req.tunnel_type = tun_type;
5609         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5610         HWRM_CHECK_RESULT();
5611
5612         if (dst_fid)
5613                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5614
5615         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5616
5617         HWRM_UNLOCK();
5618
5619         return rc;
5620 }
5621
5622 int bnxt_hwrm_set_mac(struct bnxt *bp)
5623 {
5624         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5625         struct hwrm_func_vf_cfg_input req = {0};
5626         int rc = 0;
5627
5628         if (!BNXT_VF(bp))
5629                 return 0;
5630
5631         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5632
5633         req.enables =
5634                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5635         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5636
5637         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5638
5639         HWRM_CHECK_RESULT();
5640
5641         HWRM_UNLOCK();
5642
5643         return rc;
5644 }
5645
5646 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5647 {
5648         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5649         struct hwrm_func_drv_if_change_input req = {0};
5650         uint32_t flags;
5651         int rc;
5652
5653         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5654                 return 0;
5655
5656         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5657          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5658          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5659          */
5660         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5661                 return 0;
5662
5663         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5664
5665         if (up)
5666                 req.flags =
5667                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5668
5669         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5670
5671         HWRM_CHECK_RESULT();
5672         flags = rte_le_to_cpu_32(resp->flags);
5673         HWRM_UNLOCK();
5674
5675         if (!up)
5676                 return 0;
5677
5678         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5679                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5680                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5681         }
5682
5683         return 0;
5684 }
5685
5686 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5687 {
5688         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5689         struct bnxt_error_recovery_info *info = bp->recovery_info;
5690         struct hwrm_error_recovery_qcfg_input req = {0};
5691         uint32_t flags = 0;
5692         unsigned int i;
5693         int rc;
5694
5695         /* Older FW does not have error recovery support */
5696         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5697                 return 0;
5698
5699         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5700
5701         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5702
5703         HWRM_CHECK_RESULT();
5704
5705         flags = rte_le_to_cpu_32(resp->flags);
5706         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5707                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5708         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5709                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5710
5711         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5712             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5713                 rc = -EINVAL;
5714                 goto err;
5715         }
5716
5717         /* FW returned values are in units of 100msec */
5718         info->driver_polling_freq =
5719                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5720         info->master_func_wait_period =
5721                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5722         info->normal_func_wait_period =
5723                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5724         info->master_func_wait_period_after_reset =
5725                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5726         info->max_bailout_time_after_reset =
5727                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5728         info->status_regs[BNXT_FW_STATUS_REG] =
5729                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5730         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5731                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5732         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5733                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5734         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5735                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5736         info->reg_array_cnt =
5737                 rte_le_to_cpu_32(resp->reg_array_cnt);
5738
5739         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5740                 rc = -EINVAL;
5741                 goto err;
5742         }
5743
5744         for (i = 0; i < info->reg_array_cnt; i++) {
5745                 info->reset_reg[i] =
5746                         rte_le_to_cpu_32(resp->reset_reg[i]);
5747                 info->reset_reg_val[i] =
5748                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5749                 info->delay_after_reset[i] =
5750                         resp->delay_after_reset[i];
5751         }
5752 err:
5753         HWRM_UNLOCK();
5754
5755         /* Map the FW status registers */
5756         if (!rc)
5757                 rc = bnxt_map_fw_health_status_regs(bp);
5758
5759         if (rc) {
5760                 rte_free(bp->recovery_info);
5761                 bp->recovery_info = NULL;
5762         }
5763         return rc;
5764 }
5765
5766 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5767 {
5768         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5769         struct hwrm_fw_reset_input req = {0};
5770         int rc;
5771
5772         if (!BNXT_PF(bp))
5773                 return -EOPNOTSUPP;
5774
5775         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5776
5777         req.embedded_proc_type =
5778                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5779         req.selfrst_status =
5780                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5781         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5782
5783         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5784                                     BNXT_USE_KONG(bp));
5785
5786         HWRM_CHECK_RESULT();
5787         HWRM_UNLOCK();
5788
5789         return rc;
5790 }
5791
5792 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5793 {
5794         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5795         struct hwrm_port_ts_query_input req = {0};
5796         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5797         uint32_t flags = 0;
5798         int rc;
5799
5800         if (!ptp)
5801                 return 0;
5802
5803         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5804
5805         switch (path) {
5806         case BNXT_PTP_FLAGS_PATH_TX:
5807                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5808                 break;
5809         case BNXT_PTP_FLAGS_PATH_RX:
5810                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5811                 break;
5812         case BNXT_PTP_FLAGS_CURRENT_TIME:
5813                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5814                 break;
5815         }
5816
5817         req.flags = rte_cpu_to_le_32(flags);
5818         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5819
5820         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5821
5822         HWRM_CHECK_RESULT();
5823
5824         if (timestamp) {
5825                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5826                 *timestamp |=
5827                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5828         }
5829         HWRM_UNLOCK();
5830
5831         return rc;
5832 }
5833
5834 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5835 {
5836         int rc = 0;
5837
5838         struct hwrm_cfa_counter_qcaps_input req = {0};
5839         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5840
5841         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5842                 PMD_DRV_LOG(DEBUG,
5843                             "Not a PF or trusted VF. Command not supported\n");
5844                 return 0;
5845         }
5846
5847         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5848         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5849         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5850
5851         HWRM_CHECK_RESULT();
5852         if (max_fc)
5853                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5854         HWRM_UNLOCK();
5855
5856         return 0;
5857 }
5858
5859 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5860 {
5861         int rc = 0;
5862         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5863         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5864
5865         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5866                 PMD_DRV_LOG(DEBUG,
5867                             "Not a PF or trusted VF. Command not supported\n");
5868                 return 0;
5869         }
5870
5871         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5872
5873         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5874         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5875         req.page_dir = rte_cpu_to_le_64(dma_addr);
5876
5877         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5878
5879         HWRM_CHECK_RESULT();
5880         if (ctx_id) {
5881                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5882                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5883         }
5884         HWRM_UNLOCK();
5885
5886         return 0;
5887 }
5888
5889 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5890 {
5891         int rc = 0;
5892         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5893         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5894
5895         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5896                 PMD_DRV_LOG(DEBUG,
5897                             "Not a PF or trusted VF. Command not supported\n");
5898                 return 0;
5899         }
5900
5901         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5902
5903         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5904
5905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5906
5907         HWRM_CHECK_RESULT();
5908         HWRM_UNLOCK();
5909
5910         return rc;
5911 }
5912
5913 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5914                               uint16_t cntr, uint16_t ctx_id,
5915                               uint32_t num_entries, bool enable)
5916 {
5917         struct hwrm_cfa_counter_cfg_input req = {0};
5918         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5919         uint16_t flags = 0;
5920         int rc;
5921
5922         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5923                 PMD_DRV_LOG(DEBUG,
5924                             "Not a PF or trusted VF. Command not supported\n");
5925                 return 0;
5926         }
5927
5928         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5929
5930         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5931         req.counter_type = rte_cpu_to_le_16(cntr);
5932         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5933                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5934         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5935         if (dir == BNXT_DIR_RX)
5936                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5937         else if (dir == BNXT_DIR_TX)
5938                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5939         req.flags = rte_cpu_to_le_16(flags);
5940         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5941         req.num_entries = rte_cpu_to_le_32(num_entries);
5942
5943         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5944         HWRM_CHECK_RESULT();
5945         HWRM_UNLOCK();
5946
5947         return 0;
5948 }
5949
5950 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5951                                  enum bnxt_flow_dir dir,
5952                                  uint16_t cntr,
5953                                  uint16_t num_entries)
5954 {
5955         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5956         struct hwrm_cfa_counter_qstats_input req = {0};
5957         uint16_t flow_ctx_id = 0;
5958         uint16_t flags = 0;
5959         int rc = 0;
5960
5961         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5962                 PMD_DRV_LOG(DEBUG,
5963                             "Not a PF or trusted VF. Command not supported\n");
5964                 return 0;
5965         }
5966
5967         if (dir == BNXT_DIR_RX) {
5968                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5969                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5970         } else if (dir == BNXT_DIR_TX) {
5971                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5972                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5973         }
5974
5975         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5976         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5977         req.counter_type = rte_cpu_to_le_16(cntr);
5978         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5979         req.num_entries = rte_cpu_to_le_16(num_entries);
5980         req.flags = rte_cpu_to_le_16(flags);
5981         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5982
5983         HWRM_CHECK_RESULT();
5984         HWRM_UNLOCK();
5985
5986         return 0;
5987 }
5988
5989 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5990                                 uint16_t *first_vf_id)
5991 {
5992         int rc = 0;
5993         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5994         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5995
5996         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5997
5998         req.fid = rte_cpu_to_le_16(fid);
5999
6000         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6001
6002         HWRM_CHECK_RESULT();
6003
6004         if (first_vf_id)
6005                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
6006
6007         HWRM_UNLOCK();
6008
6009         return rc;
6010 }
6011
6012 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6013 {
6014         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6015         struct hwrm_cfa_pair_alloc_input req = {0};
6016         int rc;
6017
6018         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6019                 PMD_DRV_LOG(DEBUG,
6020                             "Not a PF or trusted VF. Command not supported\n");
6021                 return 0;
6022         }
6023
6024         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6025         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6026         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6027                  bp->eth_dev->data->name, rep_bp->vf_id);
6028
6029         req.pf_b_id = rep_bp->parent_pf_idx;
6030         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6031                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6032         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6033         req.host_b_id = 1; /* TBD - Confirm if this is OK */
6034
6035         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6036                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6037         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6038                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6039         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6040                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6041         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6042                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6043
6044         req.q_ab = rep_bp->rep_q_r2f;
6045         req.q_ba = rep_bp->rep_q_f2r;
6046         req.fc_ab = rep_bp->rep_fc_r2f;
6047         req.fc_ba = rep_bp->rep_fc_f2r;
6048
6049         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6050         HWRM_CHECK_RESULT();
6051
6052         HWRM_UNLOCK();
6053         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6054                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6055         return rc;
6056 }
6057
6058 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6059 {
6060         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6061         struct hwrm_cfa_pair_free_input req = {0};
6062         int rc;
6063
6064         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6065                 PMD_DRV_LOG(DEBUG,
6066                             "Not a PF or trusted VF. Command not supported\n");
6067                 return 0;
6068         }
6069
6070         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6071         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6072                  bp->eth_dev->data->name, rep_bp->vf_id);
6073         req.pf_b_id = rep_bp->parent_pf_idx;
6074         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6075         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6076                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6077         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6078         HWRM_CHECK_RESULT();
6079         HWRM_UNLOCK();
6080         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6081                     rep_bp->vf_id);
6082         return rc;
6083 }
6084
6085 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6086 {
6087         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6088                                         bp->hwrm_cmd_resp_addr;
6089         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6090         uint32_t flags = 0;
6091         int rc = 0;
6092
6093         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6094                 return 0;
6095
6096         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6097                 PMD_DRV_LOG(DEBUG,
6098                             "Not a PF or trusted VF. Command not supported\n");
6099                 return 0;
6100         }
6101
6102         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6103         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6104
6105         HWRM_CHECK_RESULT();
6106         flags = rte_le_to_cpu_32(resp->flags);
6107         HWRM_UNLOCK();
6108
6109         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6110                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6111         else
6112                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6113
6114         return rc;
6115 }
6116
6117 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6118                             uint32_t echo_req_data2)
6119 {
6120         struct hwrm_func_echo_response_input req = {0};
6121         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6122         int rc;
6123
6124         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6125         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6126         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6127
6128         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6129
6130         HWRM_CHECK_RESULT();
6131         HWRM_UNLOCK();
6132
6133         return rc;
6134 }
6135
6136 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6137 {
6138         struct hwrm_ver_get_input req = {.req_type = 0 };
6139         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6140         int rc = 0;
6141
6142         bp->max_req_len = HWRM_MAX_REQ_LEN;
6143         bp->max_resp_len = BNXT_PAGE_SIZE;
6144         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6145
6146         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6147         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6148         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6149         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6150
6151         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6152
6153         HWRM_CHECK_RESULT_SILENT();
6154
6155         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6156                 rc = -EAGAIN;
6157
6158         HWRM_UNLOCK();
6159
6160         return rc;
6161 }
6162
6163 int bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt *bp, uint16_t i2c_addr,
6164                                           uint16_t page_number, uint16_t start_addr,
6165                                           uint16_t data_length, uint8_t *buf)
6166 {
6167         struct hwrm_port_phy_i2c_read_output *resp = bp->hwrm_cmd_resp_addr;
6168         struct hwrm_port_phy_i2c_read_input req = {0};
6169         uint32_t enables = HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET;
6170         int rc, byte_offset = 0;
6171
6172         do {
6173                 uint16_t xfer_size;
6174
6175                 HWRM_PREP(&req, HWRM_PORT_PHY_I2C_READ, BNXT_USE_CHIMP_MB);
6176                 req.i2c_slave_addr = i2c_addr;
6177                 req.page_number = rte_cpu_to_le_16(page_number);
6178                 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
6179
6180                 xfer_size = RTE_MIN(data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
6181                 req.page_offset = rte_cpu_to_le_16(start_addr + byte_offset);
6182                 req.data_length = xfer_size;
6183                 req.enables = rte_cpu_to_le_32(start_addr + byte_offset ? enables : 0);
6184                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6185                 HWRM_CHECK_RESULT();
6186
6187                 memcpy(buf + byte_offset, resp->data, xfer_size);
6188
6189                 data_length -= xfer_size;
6190                 byte_offset += xfer_size;
6191
6192                 HWRM_UNLOCK();
6193         } while (data_length > 0);
6194
6195         return rc;
6196 }