1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(int) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages == 0)
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
79 * HWRM Functions (sent to HWRM)
80 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
81 * HWRM command times out, or a negative error code if the HWRM
82 * command was failed by the FW.
85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
86 uint32_t msg_len, bool use_kong_mb)
89 struct input *req = msg;
90 struct output *resp = bp->hwrm_cmd_resp_addr;
94 uint16_t max_req_len = bp->max_req_len;
95 struct hwrm_short_input short_input = { 0 };
96 uint16_t bar_offset = use_kong_mb ?
97 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
98 uint16_t mb_trigger_offset = use_kong_mb ?
99 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
102 /* Do not send HWRM commands to firmware in error state */
103 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
106 timeout = bp->hwrm_cmd_timeout;
108 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
109 msg_len > bp->max_req_len) {
110 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
112 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
113 memcpy(short_cmd_req, req, msg_len);
115 short_input.req_type = rte_cpu_to_le_16(req->req_type);
116 short_input.signature = rte_cpu_to_le_16(
117 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
118 short_input.size = rte_cpu_to_le_16(msg_len);
119 short_input.req_addr =
120 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
122 data = (uint32_t *)&short_input;
123 msg_len = sizeof(short_input);
125 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
128 /* Write request msg to hwrm channel */
129 for (i = 0; i < msg_len; i += 4) {
130 bar = (uint8_t *)bp->bar0 + bar_offset + i;
131 rte_write32(*data, bar);
135 /* Zero the rest of the request space */
136 for (; i < max_req_len; i += 4) {
137 bar = (uint8_t *)bp->bar0 + bar_offset + i;
141 /* Ring channel doorbell */
142 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
145 * Make sure the channel doorbell ring command complete before
146 * reading the response to avoid getting stale or invalid
151 /* Poll for the valid bit */
152 for (i = 0; i < timeout; i++) {
153 /* Sanity check on the resp->resp_len */
155 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
156 /* Last byte of resp contains the valid key */
157 valid = (uint8_t *)resp + resp->resp_len - 1;
158 if (*valid == HWRM_RESP_VALID_KEY)
165 /* Suppress VER_GET timeout messages during reset recovery */
166 if (bp->flags & BNXT_FLAG_FW_RESET &&
167 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
171 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
172 req->req_type, req->seq_id);
179 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
180 * spinlock, and does initial processing.
182 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
183 * releases the spinlock only if it returns. If the regular int return codes
184 * are not used by the function, HWRM_CHECK_RESULT() should not be used
185 * directly, rather it should be copied and modified to suit the function.
187 * HWRM_UNLOCK() must be called after all response processing is completed.
189 #define HWRM_PREP(req, type, kong) do { \
190 rte_spinlock_lock(&bp->hwrm_lock); \
191 if (bp->hwrm_cmd_resp_addr == NULL) { \
192 rte_spinlock_unlock(&bp->hwrm_lock); \
195 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
196 (req)->req_type = rte_cpu_to_le_16(type); \
197 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
198 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
199 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
200 (req)->target_id = rte_cpu_to_le_16(0xffff); \
201 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
204 #define HWRM_CHECK_RESULT_SILENT() do {\
206 rte_spinlock_unlock(&bp->hwrm_lock); \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 rte_spinlock_unlock(&bp->hwrm_lock); \
216 #define HWRM_CHECK_RESULT() do {\
218 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
219 rte_spinlock_unlock(&bp->hwrm_lock); \
220 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
222 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
224 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
226 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
228 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
234 if (resp->error_code) { \
235 rc = rte_le_to_cpu_16(resp->error_code); \
236 if (resp->resp_len >= 16) { \
237 struct hwrm_err_output *tmp_hwrm_err_op = \
240 "error %d:%d:%08x:%04x\n", \
241 rc, tmp_hwrm_err_op->cmd_err, \
243 tmp_hwrm_err_op->opaque_0), \
245 tmp_hwrm_err_op->opaque_1)); \
247 PMD_DRV_LOG(ERR, "error %d\n", rc); \
249 rte_spinlock_unlock(&bp->hwrm_lock); \
250 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
252 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
254 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
256 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
258 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
266 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
268 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
277 bool mailbox = BNXT_USE_CHIMP_MB;
278 struct input *req = msg;
279 struct output *resp = bp->hwrm_cmd_resp_addr;
282 mailbox = BNXT_USE_KONG(bp);
284 HWRM_PREP(req, msg_type, mailbox);
286 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
291 memcpy(resp_msg, resp, resp_len);
298 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
302 uint32_t *tf_response_code,
306 uint32_t response_len)
309 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
310 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
311 bool mailbox = BNXT_USE_CHIMP_MB;
313 if (msg_len > sizeof(req.tf_req))
317 mailbox = BNXT_USE_KONG(bp);
319 HWRM_PREP(&req, HWRM_TF, mailbox);
320 /* Build request using the user supplied request payload.
321 * TLV request size is checked at build time against HWRM
322 * request max size, thus no checking required.
324 req.tf_type = tf_type;
325 req.tf_subtype = tf_subtype;
326 memcpy(req.tf_req, msg, msg_len);
328 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
331 /* Copy the resp to user provided response buffer */
332 if (response != NULL)
333 /* Post process response data. We need to copy only
334 * the 'payload' as the HWRM data structure really is
335 * HWRM header + msg header + payload and the TFLIB
336 * only provided a payload place holder.
338 if (response_len != 0) {
344 /* Extract the internal tflib response code */
345 *tf_response_code = resp->tf_resp_code;
351 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
354 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
355 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
357 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
358 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
361 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
369 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
370 struct bnxt_vnic_info *vnic,
372 struct bnxt_vlan_table_entry *vlan_table)
375 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
376 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
379 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
382 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
383 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
385 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
386 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
387 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
388 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
390 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
391 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
393 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
394 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
395 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
396 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
397 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
398 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
401 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
402 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
403 req.vlan_tag_tbl_addr =
404 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
405 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
407 req.mask = rte_cpu_to_le_32(mask);
409 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
417 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
419 struct bnxt_vlan_antispoof_table_entry *vlan_table)
422 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
423 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
424 bp->hwrm_cmd_resp_addr;
427 * Older HWRM versions did not support this command, and the set_rx_mask
428 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
429 * removed from set_rx_mask call, and this command was added.
431 * This command is also present from 1.7.8.11 and higher,
434 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
435 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
436 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
441 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
442 req.fid = rte_cpu_to_le_16(fid);
444 req.vlan_tag_mask_tbl_addr =
445 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
446 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
448 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
456 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
457 struct bnxt_filter_info *filter)
460 struct bnxt_filter_info *l2_filter = filter;
461 struct bnxt_vnic_info *vnic = NULL;
462 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
463 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
465 if (filter->fw_l2_filter_id == UINT64_MAX)
468 if (filter->matching_l2_fltr_ptr)
469 l2_filter = filter->matching_l2_fltr_ptr;
471 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
472 filter, l2_filter, l2_filter->l2_ref_cnt);
474 if (l2_filter->l2_ref_cnt == 0)
477 if (l2_filter->l2_ref_cnt > 0)
478 l2_filter->l2_ref_cnt--;
480 if (l2_filter->l2_ref_cnt > 0)
483 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
485 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
487 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
492 filter->fw_l2_filter_id = UINT64_MAX;
493 if (l2_filter->l2_ref_cnt == 0) {
494 vnic = l2_filter->vnic;
496 STAILQ_REMOVE(&vnic->filter, l2_filter,
497 bnxt_filter_info, next);
498 bnxt_free_filter(bp, l2_filter);
505 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
507 struct bnxt_filter_info *filter)
510 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
511 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
512 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
513 const struct rte_eth_vmdq_rx_conf *conf =
514 &dev_conf->rx_adv_conf.vmdq_rx_conf;
515 uint32_t enables = 0;
516 uint16_t j = dst_id - 1;
518 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
519 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
520 conf->pool_map[j].pools & (1UL << j)) {
522 "Add vlan %u to vmdq pool %u\n",
523 conf->pool_map[j].vlan_id, j);
525 filter->l2_ivlan = conf->pool_map[j].vlan_id;
527 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
528 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
531 if (filter->fw_l2_filter_id != UINT64_MAX)
532 bnxt_hwrm_clear_l2_filter(bp, filter);
534 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
536 /* PMD does not support XDP and RoCE */
537 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
538 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
539 req.flags = rte_cpu_to_le_32(filter->flags);
541 enables = filter->enables |
542 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
543 req.dst_id = rte_cpu_to_le_16(dst_id);
546 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
547 memcpy(req.l2_addr, filter->l2_addr,
550 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
551 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
554 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
555 req.l2_ovlan = filter->l2_ovlan;
557 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
558 req.l2_ivlan = filter->l2_ivlan;
560 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
561 req.l2_ovlan_mask = filter->l2_ovlan_mask;
563 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
564 req.l2_ivlan_mask = filter->l2_ivlan_mask;
565 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
566 req.src_id = rte_cpu_to_le_32(filter->src_id);
567 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
568 req.src_type = filter->src_type;
569 if (filter->pri_hint) {
570 req.pri_hint = filter->pri_hint;
571 req.l2_filter_id_hint =
572 rte_cpu_to_le_64(filter->l2_filter_id_hint);
575 req.enables = rte_cpu_to_le_32(enables);
577 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
581 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
582 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
585 filter->l2_ref_cnt++;
590 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
592 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
593 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
600 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
603 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
606 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
607 if (ptp->tx_tstamp_en)
608 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
611 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
612 req.flags = rte_cpu_to_le_32(flags);
613 req.enables = rte_cpu_to_le_32
614 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
615 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
617 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
623 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
626 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
627 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
628 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
633 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
635 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
637 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
641 if (!BNXT_CHIP_P5(bp) &&
642 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
645 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
646 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
648 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
652 if (!BNXT_CHIP_P5(bp)) {
653 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
654 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
655 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
656 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
657 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
658 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
659 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
660 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
661 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
662 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
663 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
664 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
665 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
666 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
667 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
668 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
669 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
670 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
679 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
683 for (i = 0; i < bp->pf->max_vfs; i++) {
684 rte_free(bp->pf->vf_info[i].vlan_table);
685 bp->pf->vf_info[i].vlan_table = NULL;
686 rte_free(bp->pf->vf_info[i].vlan_as_table);
687 bp->pf->vf_info[i].vlan_as_table = NULL;
689 rte_free(bp->pf->vf_info);
690 bp->pf->vf_info = NULL;
693 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
696 struct hwrm_func_qcaps_input req = {.req_type = 0 };
697 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
698 uint16_t new_max_vfs;
702 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
704 req.fid = rte_cpu_to_le_16(0xffff);
706 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
710 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
711 flags = rte_le_to_cpu_32(resp->flags);
713 bp->pf->port_id = resp->port_id;
714 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
715 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
716 new_max_vfs = bp->pdev->max_vfs;
717 if (new_max_vfs != bp->pf->max_vfs) {
719 bnxt_hwrm_free_vf_info(bp);
720 bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
721 sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
722 if (bp->pf->vf_info == NULL) {
723 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
727 bp->pf->max_vfs = new_max_vfs;
728 for (i = 0; i < new_max_vfs; i++) {
729 bp->pf->vf_info[i].fid =
730 bp->pf->first_vf_id + i;
731 bp->pf->vf_info[i].vlan_table =
732 rte_zmalloc("VF VLAN table",
735 if (bp->pf->vf_info[i].vlan_table == NULL)
737 "Fail to alloc VLAN table for VF %d\n",
741 bp->pf->vf_info[i].vlan_table);
742 bp->pf->vf_info[i].vlan_as_table =
743 rte_zmalloc("VF VLAN AS table",
746 if (bp->pf->vf_info[i].vlan_as_table == NULL)
748 "Alloc VLAN AS table for VF %d fail\n",
752 bp->pf->vf_info[i].vlan_as_table);
753 STAILQ_INIT(&bp->pf->vf_info[i].filter);
758 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
759 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
760 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
761 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
763 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
765 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
766 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
767 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
768 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
769 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
770 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
771 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
772 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
773 bp->max_l2_ctx += bp->max_rx_em_flows;
774 /* TODO: For now, do not support VMDq/RFS on VFs. */
779 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
783 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
784 bp->max_l2_ctx, bp->max_vnics);
785 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
787 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
788 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
789 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
790 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
792 bnxt_hwrm_ptp_qcfg(bp);
796 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
797 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
799 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
800 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
801 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
804 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
805 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
807 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
808 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
810 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
811 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
818 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
822 rc = __bnxt_hwrm_func_qcaps(bp);
823 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
824 rc = bnxt_alloc_ctx_mem(bp);
829 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
830 * But the error can be ignored. Return success.
832 rc = bnxt_hwrm_func_resc_qcaps(bp);
834 bp->flags |= BNXT_FLAG_NEW_RM;
840 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
841 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
845 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
846 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
848 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
850 req.target_id = rte_cpu_to_le_16(0xffff);
852 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
856 flags = rte_le_to_cpu_32(resp->flags);
858 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
859 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
860 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
863 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
864 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
866 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
867 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
869 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
876 int bnxt_hwrm_func_reset(struct bnxt *bp)
879 struct hwrm_func_reset_input req = {.req_type = 0 };
880 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
882 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
884 req.enables = rte_cpu_to_le_32(0);
886 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
894 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
898 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
899 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
901 if (bp->flags & BNXT_FLAG_REGISTERED)
904 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
905 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
906 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
907 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
909 /* PFs and trusted VFs should indicate the support of the
910 * Master capability on non Stingray platform
912 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
913 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
915 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
916 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
917 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
918 req.ver_maj = RTE_VER_YEAR;
919 req.ver_min = RTE_VER_MONTH;
920 req.ver_upd = RTE_VER_MINOR;
923 req.enables |= rte_cpu_to_le_32(
924 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
925 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
926 RTE_MIN(sizeof(req.vf_req_fwd),
927 sizeof(bp->pf->vf_req_fwd)));
930 req.flags = rte_cpu_to_le_32(flags);
932 req.async_event_fwd[0] |=
933 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
934 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
935 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
936 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
937 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
938 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
939 req.async_event_fwd[0] |=
940 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
941 req.async_event_fwd[1] |=
942 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
943 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
945 req.async_event_fwd[1] |=
946 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
948 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
949 req.async_event_fwd[1] |=
950 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
952 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
956 flags = rte_le_to_cpu_32(resp->flags);
957 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
958 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
962 bp->flags |= BNXT_FLAG_REGISTERED;
967 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
969 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
972 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
975 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
980 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
981 struct hwrm_func_vf_cfg_input req = {0};
983 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
985 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
986 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
987 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
988 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
989 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
991 if (BNXT_HAS_RING_GRPS(bp)) {
992 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
993 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
996 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
997 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
998 AGG_RING_MULTIPLIER);
999 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1000 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1002 BNXT_NUM_ASYNC_CPR(bp));
1003 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1004 if (bp->vf_resv_strategy ==
1005 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1006 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1007 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1008 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1009 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1010 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1011 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1012 } else if (bp->vf_resv_strategy ==
1013 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1014 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1015 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1019 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1020 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1021 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1022 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1023 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1024 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1026 if (test && BNXT_HAS_RING_GRPS(bp))
1027 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1029 req.flags = rte_cpu_to_le_32(flags);
1030 req.enables |= rte_cpu_to_le_32(enables);
1032 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1035 HWRM_CHECK_RESULT_SILENT();
1037 HWRM_CHECK_RESULT();
1043 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1046 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1047 struct hwrm_func_resource_qcaps_input req = {0};
1049 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1050 req.fid = rte_cpu_to_le_16(0xffff);
1052 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1054 HWRM_CHECK_RESULT_SILENT();
1056 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1057 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1058 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1059 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1060 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1061 /* func_resource_qcaps does not return max_rx_em_flows.
1062 * So use the value provided by func_qcaps.
1064 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1065 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1066 bp->max_l2_ctx += bp->max_rx_em_flows;
1067 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1068 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1069 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1070 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1071 if (bp->vf_resv_strategy >
1072 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1073 bp->vf_resv_strategy =
1074 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1080 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1083 struct hwrm_ver_get_input req = {.req_type = 0 };
1084 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1085 uint32_t fw_version;
1086 uint16_t max_resp_len;
1087 char type[RTE_MEMZONE_NAMESIZE];
1088 uint32_t dev_caps_cfg;
1090 bp->max_req_len = HWRM_MAX_REQ_LEN;
1091 bp->hwrm_cmd_timeout = timeout;
1092 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1094 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1095 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1096 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1098 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1100 if (bp->flags & BNXT_FLAG_FW_RESET)
1101 HWRM_CHECK_RESULT_SILENT();
1103 HWRM_CHECK_RESULT();
1105 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1106 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1107 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1108 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1109 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1110 (resp->hwrm_fw_min_8b << 16) |
1111 (resp->hwrm_fw_bld_8b << 8) |
1112 resp->hwrm_fw_rsvd_8b;
1113 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1114 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1116 fw_version = resp->hwrm_intf_maj_8b << 16;
1117 fw_version |= resp->hwrm_intf_min_8b << 8;
1118 fw_version |= resp->hwrm_intf_upd_8b;
1119 bp->hwrm_spec_code = fw_version;
1121 /* def_req_timeout value is in milliseconds */
1122 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1123 /* convert timeout to usec */
1124 bp->hwrm_cmd_timeout *= 1000;
1125 if (!bp->hwrm_cmd_timeout)
1126 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1128 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1129 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1134 if (bp->max_req_len > resp->max_req_win_len) {
1135 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1139 bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1141 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1142 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1143 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1144 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1146 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1147 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1149 if (bp->max_resp_len != max_resp_len) {
1150 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1151 bp->pdev->addr.domain, bp->pdev->addr.bus,
1152 bp->pdev->addr.devid, bp->pdev->addr.function);
1154 rte_free(bp->hwrm_cmd_resp_addr);
1156 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1157 if (bp->hwrm_cmd_resp_addr == NULL) {
1161 bp->hwrm_cmd_resp_dma_addr =
1162 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1163 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1165 "Unable to map response buffer to physical memory.\n");
1169 bp->max_resp_len = max_resp_len;
1173 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1175 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1176 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1177 bp->flags |= BNXT_FLAG_SHORT_CMD;
1180 if (((dev_caps_cfg &
1181 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1183 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1184 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1185 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1186 bp->pdev->addr.domain, bp->pdev->addr.bus,
1187 bp->pdev->addr.devid, bp->pdev->addr.function);
1189 rte_free(bp->hwrm_short_cmd_req_addr);
1191 bp->hwrm_short_cmd_req_addr =
1192 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1193 if (bp->hwrm_short_cmd_req_addr == NULL) {
1197 bp->hwrm_short_cmd_req_dma_addr =
1198 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1199 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1200 rte_free(bp->hwrm_short_cmd_req_addr);
1202 "Unable to map buffer to physical memory.\n");
1208 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1209 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1210 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1213 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1214 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1216 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1217 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1218 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1222 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1223 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1224 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1233 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1236 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1237 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1239 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1242 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1247 HWRM_CHECK_RESULT();
1253 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1256 struct hwrm_port_phy_cfg_input req = {0};
1257 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1258 uint32_t enables = 0;
1260 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1262 if (conf->link_up) {
1263 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1264 if (bp->link_info->auto_mode && conf->link_speed) {
1265 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1266 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1269 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1271 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1272 * any auto mode, even "none".
1274 if (!conf->link_speed) {
1275 /* No speeds specified. Enable AutoNeg - all speeds */
1276 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1278 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1280 if (bp->link_info->link_signal_mode) {
1282 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1283 req.force_pam4_link_speed =
1284 rte_cpu_to_le_16(conf->link_speed);
1286 req.force_link_speed =
1287 rte_cpu_to_le_16(conf->link_speed);
1290 /* AutoNeg - Advertise speeds specified. */
1291 if (conf->auto_link_speed_mask &&
1292 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1294 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1295 req.auto_link_speed_mask =
1296 conf->auto_link_speed_mask;
1297 if (conf->auto_pam4_link_speeds) {
1299 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1300 req.auto_link_pam4_speed_mask =
1301 conf->auto_pam4_link_speeds;
1304 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1307 if (conf->auto_link_speed &&
1308 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1310 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1312 req.auto_duplex = conf->duplex;
1313 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1314 req.auto_pause = conf->auto_pause;
1315 req.force_pause = conf->force_pause;
1316 /* Set force_pause if there is no auto or if there is a force */
1317 if (req.auto_pause && !req.force_pause)
1318 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1320 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1322 req.enables = rte_cpu_to_le_32(enables);
1325 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1326 PMD_DRV_LOG(INFO, "Force Link Down\n");
1329 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1331 HWRM_CHECK_RESULT();
1337 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1338 struct bnxt_link_info *link_info)
1341 struct hwrm_port_phy_qcfg_input req = {0};
1342 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1344 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1346 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1348 HWRM_CHECK_RESULT();
1350 link_info->phy_link_status = resp->link;
1351 link_info->link_up =
1352 (link_info->phy_link_status ==
1353 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1354 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1355 link_info->duplex = resp->duplex_cfg;
1356 link_info->pause = resp->pause;
1357 link_info->auto_pause = resp->auto_pause;
1358 link_info->force_pause = resp->force_pause;
1359 link_info->auto_mode = resp->auto_mode;
1360 link_info->phy_type = resp->phy_type;
1361 link_info->media_type = resp->media_type;
1363 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1364 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1365 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1366 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1367 link_info->phy_ver[0] = resp->phy_maj;
1368 link_info->phy_ver[1] = resp->phy_min;
1369 link_info->phy_ver[2] = resp->phy_bld;
1370 link_info->link_signal_mode =
1371 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1372 link_info->force_pam4_link_speed =
1373 rte_le_to_cpu_16(resp->force_pam4_link_speed);
1374 link_info->support_pam4_speeds =
1375 rte_le_to_cpu_16(resp->support_pam4_speeds);
1376 link_info->auto_pam4_link_speeds =
1377 rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1380 PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1381 link_info->link_speed, link_info->auto_mode,
1382 link_info->auto_link_speed, link_info->auto_link_speed_mask,
1383 link_info->support_speeds, link_info->force_link_speed);
1384 PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1385 link_info->link_signal_mode,
1386 link_info->auto_pam4_link_speeds,
1387 link_info->support_pam4_speeds,
1388 link_info->force_pam4_link_speed);
1392 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1395 struct hwrm_port_phy_qcaps_input req = {0};
1396 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1397 struct bnxt_link_info *link_info = bp->link_info;
1399 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1402 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1404 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1406 HWRM_CHECK_RESULT();
1408 bp->port_cnt = resp->port_cnt;
1409 if (resp->supported_speeds_auto_mode)
1410 link_info->support_auto_speeds =
1411 rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1412 if (resp->supported_pam4_speeds_auto_mode)
1413 link_info->support_pam4_auto_speeds =
1414 rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1421 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1425 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1426 if (bp->tx_cos_queue[i].profile ==
1427 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1428 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1435 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1439 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1440 if (bp->tx_cos_queue[i].profile !=
1441 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1442 bp->tx_cos_queue[i].id !=
1443 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1444 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1450 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1453 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1454 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1455 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1459 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1461 req.flags = rte_cpu_to_le_32(dir);
1462 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1463 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1464 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1466 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1467 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1469 HWRM_CHECK_RESULT();
1471 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1472 GET_TX_QUEUE_INFO(0);
1473 GET_TX_QUEUE_INFO(1);
1474 GET_TX_QUEUE_INFO(2);
1475 GET_TX_QUEUE_INFO(3);
1476 GET_TX_QUEUE_INFO(4);
1477 GET_TX_QUEUE_INFO(5);
1478 GET_TX_QUEUE_INFO(6);
1479 GET_TX_QUEUE_INFO(7);
1481 GET_RX_QUEUE_INFO(0);
1482 GET_RX_QUEUE_INFO(1);
1483 GET_RX_QUEUE_INFO(2);
1484 GET_RX_QUEUE_INFO(3);
1485 GET_RX_QUEUE_INFO(4);
1486 GET_RX_QUEUE_INFO(5);
1487 GET_RX_QUEUE_INFO(6);
1488 GET_RX_QUEUE_INFO(7);
1493 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1496 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1497 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1501 /* iterate and find the COSq profile to use for Tx */
1502 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1503 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1504 if (bp->tx_cos_queue[i].id != 0xff)
1505 bp->tx_cosq_id[j++] =
1506 bp->tx_cos_queue[i].id;
1509 /* When CoS classification is disabled, for normal NIC
1510 * operations, ideally we should look to use LOSSY.
1511 * If not found, fallback to the first valid profile
1513 if (!bnxt_find_lossy_profile(bp))
1514 bnxt_find_first_valid_profile(bp);
1519 bp->max_tc = resp->max_configurable_queues;
1520 bp->max_lltc = resp->max_configurable_lossless_queues;
1521 if (bp->max_tc > BNXT_MAX_QUEUE)
1522 bp->max_tc = BNXT_MAX_QUEUE;
1523 bp->max_q = bp->max_tc;
1525 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1526 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1534 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1535 struct bnxt_ring *ring,
1536 uint32_t ring_type, uint32_t map_index,
1537 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1538 uint16_t tx_cosq_id)
1541 uint32_t enables = 0;
1542 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1543 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1544 struct rte_mempool *mb_pool;
1545 uint16_t rx_buf_size;
1547 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1549 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1550 req.fbo = rte_cpu_to_le_32(0);
1551 /* Association of ring index with doorbell index */
1552 req.logical_id = rte_cpu_to_le_16(map_index);
1553 req.length = rte_cpu_to_le_32(ring->ring_size);
1555 switch (ring_type) {
1556 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1557 req.ring_type = ring_type;
1558 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1559 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1560 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1561 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1563 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1565 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1566 req.ring_type = ring_type;
1567 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1568 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1569 if (BNXT_CHIP_P5(bp)) {
1570 mb_pool = bp->rx_queues[0]->mb_pool;
1571 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1572 RTE_PKTMBUF_HEADROOM;
1573 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1574 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1576 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1578 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1580 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1582 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1583 req.ring_type = ring_type;
1584 if (BNXT_HAS_NQ(bp)) {
1585 /* Association of cp ring with nq */
1586 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1588 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1590 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1592 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1593 req.ring_type = ring_type;
1594 req.page_size = BNXT_PAGE_SHFT;
1595 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1597 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1598 req.ring_type = ring_type;
1599 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1601 mb_pool = bp->rx_queues[0]->mb_pool;
1602 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1603 RTE_PKTMBUF_HEADROOM;
1604 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1605 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1607 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1608 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1609 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1610 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1613 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1618 req.enables = rte_cpu_to_le_32(enables);
1620 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1622 if (rc || resp->error_code) {
1623 if (rc == 0 && resp->error_code)
1624 rc = rte_le_to_cpu_16(resp->error_code);
1625 switch (ring_type) {
1626 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1628 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1631 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1633 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1636 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1638 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1642 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1644 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1647 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1649 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1653 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1659 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1664 int bnxt_hwrm_ring_free(struct bnxt *bp,
1665 struct bnxt_ring *ring, uint32_t ring_type)
1668 struct hwrm_ring_free_input req = {.req_type = 0 };
1669 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1671 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1673 req.ring_type = ring_type;
1674 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1676 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1678 if (rc || resp->error_code) {
1679 if (rc == 0 && resp->error_code)
1680 rc = rte_le_to_cpu_16(resp->error_code);
1683 switch (ring_type) {
1684 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1685 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1688 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1689 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1692 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1693 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1696 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1698 "hwrm_ring_free nq failed. rc:%d\n", rc);
1700 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1702 "hwrm_ring_free agg failed. rc:%d\n", rc);
1705 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1713 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1716 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1717 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1719 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1721 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1722 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1723 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1724 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1726 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1728 HWRM_CHECK_RESULT();
1730 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1737 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1740 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1741 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1743 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1745 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1747 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1749 HWRM_CHECK_RESULT();
1752 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1756 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1759 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1760 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1762 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1765 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1767 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1769 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1771 HWRM_CHECK_RESULT();
1777 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1778 unsigned int idx __rte_unused)
1781 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1782 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1784 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1786 req.update_period_ms = rte_cpu_to_le_32(0);
1788 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1790 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1792 HWRM_CHECK_RESULT();
1794 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1801 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1802 unsigned int idx __rte_unused)
1805 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1806 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1808 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1810 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1812 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1814 HWRM_CHECK_RESULT();
1820 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1823 struct hwrm_vnic_alloc_input req = { 0 };
1824 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1826 if (!BNXT_HAS_RING_GRPS(bp))
1827 goto skip_ring_grps;
1829 /* map ring groups to this vnic */
1830 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1831 vnic->start_grp_id, vnic->end_grp_id);
1832 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1833 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1835 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1836 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1837 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1838 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1841 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1842 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1844 if (vnic->func_default)
1846 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1847 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1849 HWRM_CHECK_RESULT();
1851 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1853 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1857 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1858 struct bnxt_vnic_info *vnic,
1859 struct bnxt_plcmodes_cfg *pmode)
1862 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1863 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1865 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1867 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1869 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1871 HWRM_CHECK_RESULT();
1873 pmode->flags = rte_le_to_cpu_32(resp->flags);
1874 /* dflt_vnic bit doesn't exist in the _cfg command */
1875 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1876 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1877 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1878 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1885 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1886 struct bnxt_vnic_info *vnic,
1887 struct bnxt_plcmodes_cfg *pmode)
1890 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1891 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1893 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1894 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1898 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1900 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1901 req.flags = rte_cpu_to_le_32(pmode->flags);
1902 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1903 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1904 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1905 req.enables = rte_cpu_to_le_32(
1906 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1907 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1908 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1911 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1913 HWRM_CHECK_RESULT();
1919 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1922 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1923 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1924 struct bnxt_plcmodes_cfg pmodes = { 0 };
1925 uint32_t ctx_enable_flag = 0;
1926 uint32_t enables = 0;
1928 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1929 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1933 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1937 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1939 if (BNXT_CHIP_P5(bp)) {
1940 int dflt_rxq = vnic->start_grp_id;
1941 struct bnxt_rx_ring_info *rxr;
1942 struct bnxt_cp_ring_info *cpr;
1943 struct bnxt_rx_queue *rxq;
1947 * The first active receive ring is used as the VNIC
1948 * default receive ring. If there are no active receive
1949 * rings (all corresponding receive queues are stopped),
1950 * the first receive ring is used.
1952 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1953 rxq = bp->eth_dev->data->rx_queues[i];
1954 if (rxq->rx_started) {
1960 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1964 req.default_rx_ring_id =
1965 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1966 req.default_cmpl_ring_id =
1967 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1968 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1969 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1970 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
1971 enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
1972 req.rx_csum_v2_mode =
1973 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
1978 /* Only RSS support for now TBD: COS & LB */
1979 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1980 if (vnic->lb_rule != 0xffff)
1981 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1982 if (vnic->cos_rule != 0xffff)
1983 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1984 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1985 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1986 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1988 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1989 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1990 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1993 enables |= ctx_enable_flag;
1994 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1995 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1996 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1997 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2000 req.enables = rte_cpu_to_le_32(enables);
2001 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2002 req.mru = rte_cpu_to_le_16(vnic->mru);
2003 /* Configure default VNIC only once. */
2004 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2006 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2007 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2009 if (vnic->vlan_strip)
2011 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2014 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2015 if (vnic->roce_dual)
2016 req.flags |= rte_cpu_to_le_32(
2017 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
2018 if (vnic->roce_only)
2019 req.flags |= rte_cpu_to_le_32(
2020 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
2021 if (vnic->rss_dflt_cr)
2022 req.flags |= rte_cpu_to_le_32(
2023 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2025 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2027 HWRM_CHECK_RESULT();
2030 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2035 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2039 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2040 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2042 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2043 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2046 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2049 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2050 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2051 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2053 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2055 HWRM_CHECK_RESULT();
2057 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2058 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2059 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2060 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2061 vnic->mru = rte_le_to_cpu_16(resp->mru);
2062 vnic->func_default = rte_le_to_cpu_32(
2063 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2064 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2065 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2066 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2067 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2068 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
2069 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
2070 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
2071 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
2072 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2073 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2080 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2081 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2085 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2086 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2087 bp->hwrm_cmd_resp_addr;
2089 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2091 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2092 HWRM_CHECK_RESULT();
2094 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2095 if (!BNXT_HAS_RING_GRPS(bp))
2096 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2097 else if (ctx_idx == 0)
2098 vnic->rss_rule = ctx_id;
2106 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2107 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2110 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2111 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2112 bp->hwrm_cmd_resp_addr;
2114 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2115 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2118 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2120 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2122 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2124 HWRM_CHECK_RESULT();
2130 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2134 if (BNXT_CHIP_P5(bp)) {
2137 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2138 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2140 vnic->fw_grp_ids[j]);
2141 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2143 vnic->num_lb_ctxts = 0;
2145 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2146 vnic->rss_rule = INVALID_HW_RING_ID;
2152 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2155 struct hwrm_vnic_free_input req = {.req_type = 0 };
2156 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2158 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2159 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2163 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2165 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2167 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2169 HWRM_CHECK_RESULT();
2172 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2173 /* Configure default VNIC again if necessary. */
2174 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2175 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2181 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2185 int nr_ctxs = vnic->num_lb_ctxts;
2186 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2187 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2189 for (i = 0; i < nr_ctxs; i++) {
2190 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2192 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2193 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2194 req.hash_mode_flags = vnic->hash_mode;
2196 req.hash_key_tbl_addr =
2197 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2199 req.ring_grp_tbl_addr =
2200 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2201 i * HW_HASH_INDEX_SIZE);
2202 req.ring_table_pair_index = i;
2203 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2205 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2208 HWRM_CHECK_RESULT();
2215 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2216 struct bnxt_vnic_info *vnic)
2219 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2220 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2222 if (!vnic->rss_table)
2225 if (BNXT_CHIP_P5(bp))
2226 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2228 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2230 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2231 req.hash_mode_flags = vnic->hash_mode;
2233 req.ring_grp_tbl_addr =
2234 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2235 req.hash_key_tbl_addr =
2236 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2237 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2238 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2240 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2242 HWRM_CHECK_RESULT();
2248 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2249 struct bnxt_vnic_info *vnic)
2252 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2253 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2256 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2257 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2261 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2263 req.flags = rte_cpu_to_le_32(
2264 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2266 req.enables = rte_cpu_to_le_32(
2267 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2269 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2270 size -= RTE_PKTMBUF_HEADROOM;
2271 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2273 req.jumbo_thresh = rte_cpu_to_le_16(size);
2274 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2276 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2278 HWRM_CHECK_RESULT();
2284 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2285 struct bnxt_vnic_info *vnic, bool enable)
2288 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2289 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2291 if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2293 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2297 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2298 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2302 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2305 req.enables = rte_cpu_to_le_32(
2306 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2307 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2308 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2309 req.flags = rte_cpu_to_le_32(
2310 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2311 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2312 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2313 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2314 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2315 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2316 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2317 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2318 req.min_agg_len = rte_cpu_to_le_32(512);
2320 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2322 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2324 HWRM_CHECK_RESULT();
2330 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2332 struct hwrm_func_cfg_input req = {0};
2333 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2336 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2337 req.enables = rte_cpu_to_le_32(
2338 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2339 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2340 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2342 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2344 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2345 HWRM_CHECK_RESULT();
2348 bp->pf->vf_info[vf].random_mac = false;
2353 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2357 struct hwrm_func_qstats_input req = {.req_type = 0};
2358 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2360 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2362 req.fid = rte_cpu_to_le_16(fid);
2364 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2366 HWRM_CHECK_RESULT();
2369 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2376 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2377 struct rte_eth_stats *stats,
2378 struct hwrm_func_qstats_output *func_qstats)
2381 struct hwrm_func_qstats_input req = {.req_type = 0};
2382 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2384 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2386 req.fid = rte_cpu_to_le_16(fid);
2388 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2390 HWRM_CHECK_RESULT();
2392 memcpy(func_qstats, resp,
2393 sizeof(struct hwrm_func_qstats_output));
2398 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2399 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2400 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2401 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2402 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2403 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2405 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2406 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2407 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2408 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2409 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2410 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2412 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2413 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2414 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2422 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2425 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2426 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2428 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2430 req.fid = rte_cpu_to_le_16(fid);
2432 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2434 HWRM_CHECK_RESULT();
2440 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2445 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2446 struct bnxt_tx_queue *txq;
2447 struct bnxt_rx_queue *rxq;
2448 struct bnxt_cp_ring_info *cpr;
2450 if (i >= bp->rx_cp_nr_rings) {
2451 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2454 rxq = bp->rx_queues[i];
2458 rc = bnxt_hwrm_stat_clear(bp, cpr);
2466 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2470 struct bnxt_cp_ring_info *cpr;
2472 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2474 if (i >= bp->rx_cp_nr_rings) {
2475 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2477 cpr = bp->rx_queues[i]->cp_ring;
2478 if (BNXT_HAS_RING_GRPS(bp))
2479 bp->grp_info[i].fw_stats_ctx = -1;
2481 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2482 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2483 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2491 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2496 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2497 struct bnxt_tx_queue *txq;
2498 struct bnxt_rx_queue *rxq;
2499 struct bnxt_cp_ring_info *cpr;
2501 if (i >= bp->rx_cp_nr_rings) {
2502 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2505 rxq = bp->rx_queues[i];
2509 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2518 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2523 if (!BNXT_HAS_RING_GRPS(bp))
2526 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2528 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2531 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2539 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2541 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2543 bnxt_hwrm_ring_free(bp, cp_ring,
2544 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2545 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2546 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2547 sizeof(*cpr->cp_desc_ring));
2548 cpr->cp_raw_cons = 0;
2552 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2554 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2556 bnxt_hwrm_ring_free(bp, cp_ring,
2557 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2558 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2559 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2560 sizeof(*cpr->cp_desc_ring));
2561 cpr->cp_raw_cons = 0;
2565 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2567 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2568 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2569 struct bnxt_ring *ring = rxr->rx_ring_struct;
2570 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2572 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2573 bnxt_hwrm_ring_free(bp, ring,
2574 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2575 ring->fw_ring_id = INVALID_HW_RING_ID;
2576 if (BNXT_HAS_RING_GRPS(bp))
2577 bp->grp_info[queue_index].rx_fw_ring_id =
2580 ring = rxr->ag_ring_struct;
2581 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2582 bnxt_hwrm_ring_free(bp, ring,
2584 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2585 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2586 if (BNXT_HAS_RING_GRPS(bp))
2587 bp->grp_info[queue_index].ag_fw_ring_id =
2590 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2591 bnxt_free_cp_ring(bp, cpr);
2593 if (BNXT_HAS_RING_GRPS(bp))
2594 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2598 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2602 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2603 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2604 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2605 struct bnxt_ring *ring = txr->tx_ring_struct;
2606 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2608 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2609 bnxt_hwrm_ring_free(bp, ring,
2610 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2611 ring->fw_ring_id = INVALID_HW_RING_ID;
2612 memset(txr->tx_desc_ring, 0,
2613 txr->tx_ring_struct->ring_size *
2614 sizeof(*txr->tx_desc_ring));
2615 memset(txr->tx_buf_ring, 0,
2616 txr->tx_ring_struct->ring_size *
2617 sizeof(*txr->tx_buf_ring));
2618 txr->tx_raw_prod = 0;
2619 txr->tx_raw_cons = 0;
2621 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2622 bnxt_free_cp_ring(bp, cpr);
2623 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2627 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2628 bnxt_free_hwrm_rx_ring(bp, i);
2633 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2638 if (!BNXT_HAS_RING_GRPS(bp))
2641 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2642 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2650 * HWRM utility functions
2653 void bnxt_free_hwrm_resources(struct bnxt *bp)
2655 /* Release memzone */
2656 rte_free(bp->hwrm_cmd_resp_addr);
2657 rte_free(bp->hwrm_short_cmd_req_addr);
2658 bp->hwrm_cmd_resp_addr = NULL;
2659 bp->hwrm_short_cmd_req_addr = NULL;
2660 bp->hwrm_cmd_resp_dma_addr = 0;
2661 bp->hwrm_short_cmd_req_dma_addr = 0;
2664 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2666 struct rte_pci_device *pdev = bp->pdev;
2667 char type[RTE_MEMZONE_NAMESIZE];
2669 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2670 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2671 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2672 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2673 if (bp->hwrm_cmd_resp_addr == NULL)
2675 bp->hwrm_cmd_resp_dma_addr =
2676 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2677 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2679 "unable to map response address to physical memory\n");
2682 rte_spinlock_init(&bp->hwrm_lock);
2688 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2692 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2693 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2696 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2697 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2702 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2707 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2709 struct bnxt_filter_info *filter;
2712 STAILQ_FOREACH(filter, &vnic->filter, next) {
2713 rc = bnxt_clear_one_vnic_filter(bp, filter);
2714 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2715 bnxt_free_filter(bp, filter);
2721 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2723 struct bnxt_filter_info *filter;
2724 struct rte_flow *flow;
2727 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2728 flow = STAILQ_FIRST(&vnic->flow_list);
2729 filter = flow->filter;
2730 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2731 rc = bnxt_clear_one_vnic_filter(bp, filter);
2733 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2739 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2741 struct bnxt_filter_info *filter;
2744 STAILQ_FOREACH(filter, &vnic->filter, next) {
2745 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2746 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2748 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2749 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2752 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2761 bnxt_free_tunnel_ports(struct bnxt *bp)
2763 if (bp->vxlan_port_cnt)
2764 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2765 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2767 if (bp->geneve_port_cnt)
2768 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2769 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2772 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2776 if (bp->vnic_info == NULL)
2780 * Cleanup VNICs in reverse order, to make sure the L2 filter
2781 * from vnic0 is last to be cleaned up.
2783 for (i = bp->max_vnics - 1; i >= 0; i--) {
2784 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2786 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2789 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2791 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2793 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2795 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2797 bnxt_hwrm_vnic_free(bp, vnic);
2799 rte_free(vnic->fw_grp_ids);
2801 /* Ring resources */
2802 bnxt_free_all_hwrm_rings(bp);
2803 bnxt_free_all_hwrm_ring_grps(bp);
2804 bnxt_free_all_hwrm_stat_ctxs(bp);
2805 bnxt_free_tunnel_ports(bp);
2808 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2810 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2812 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2813 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2815 switch (conf_link_speed) {
2816 case ETH_LINK_SPEED_10M_HD:
2817 case ETH_LINK_SPEED_100M_HD:
2819 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2821 return hw_link_duplex;
2824 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2829 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2832 uint16_t eth_link_speed = 0;
2834 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2835 return ETH_LINK_SPEED_AUTONEG;
2837 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2838 case ETH_LINK_SPEED_100M:
2839 case ETH_LINK_SPEED_100M_HD:
2842 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2844 case ETH_LINK_SPEED_1G:
2846 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2848 case ETH_LINK_SPEED_2_5G:
2850 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2852 case ETH_LINK_SPEED_10G:
2854 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2856 case ETH_LINK_SPEED_20G:
2858 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2860 case ETH_LINK_SPEED_25G:
2862 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2864 case ETH_LINK_SPEED_40G:
2866 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2868 case ETH_LINK_SPEED_50G:
2869 eth_link_speed = pam4_link ?
2870 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
2871 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2873 case ETH_LINK_SPEED_100G:
2874 eth_link_speed = pam4_link ?
2875 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
2876 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2878 case ETH_LINK_SPEED_200G:
2880 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2884 "Unsupported link speed %d; default to AUTO\n",
2888 return eth_link_speed;
2891 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2892 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2893 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2894 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2895 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2897 static int bnxt_validate_link_speed(struct bnxt *bp)
2899 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2900 uint16_t port_id = bp->eth_dev->data->port_id;
2901 uint32_t link_speed_capa;
2904 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2907 link_speed_capa = bnxt_get_speed_capabilities(bp);
2909 if (link_speed & ETH_LINK_SPEED_FIXED) {
2910 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2912 if (one_speed & (one_speed - 1)) {
2914 "Invalid advertised speeds (%u) for port %u\n",
2915 link_speed, port_id);
2918 if ((one_speed & link_speed_capa) != one_speed) {
2920 "Unsupported advertised speed (%u) for port %u\n",
2921 link_speed, port_id);
2925 if (!(link_speed & link_speed_capa)) {
2927 "Unsupported advertised speeds (%u) for port %u\n",
2928 link_speed, port_id);
2936 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2940 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2941 if (bp->link_info->support_speeds)
2942 return bp->link_info->support_speeds;
2943 link_speed = BNXT_SUPPORTED_SPEEDS;
2946 if (link_speed & ETH_LINK_SPEED_100M)
2947 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2948 if (link_speed & ETH_LINK_SPEED_100M_HD)
2949 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2950 if (link_speed & ETH_LINK_SPEED_1G)
2951 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2952 if (link_speed & ETH_LINK_SPEED_2_5G)
2953 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2954 if (link_speed & ETH_LINK_SPEED_10G)
2955 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2956 if (link_speed & ETH_LINK_SPEED_20G)
2957 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2958 if (link_speed & ETH_LINK_SPEED_25G)
2959 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2960 if (link_speed & ETH_LINK_SPEED_40G)
2961 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2962 if (link_speed & ETH_LINK_SPEED_50G)
2963 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2964 if (link_speed & ETH_LINK_SPEED_100G)
2965 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2966 if (link_speed & ETH_LINK_SPEED_200G)
2967 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2971 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2973 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2975 switch (hw_link_speed) {
2976 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2977 eth_link_speed = ETH_SPEED_NUM_100M;
2979 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2980 eth_link_speed = ETH_SPEED_NUM_1G;
2982 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2983 eth_link_speed = ETH_SPEED_NUM_2_5G;
2985 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2986 eth_link_speed = ETH_SPEED_NUM_10G;
2988 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2989 eth_link_speed = ETH_SPEED_NUM_20G;
2991 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2992 eth_link_speed = ETH_SPEED_NUM_25G;
2994 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2995 eth_link_speed = ETH_SPEED_NUM_40G;
2997 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2998 eth_link_speed = ETH_SPEED_NUM_50G;
3000 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3001 eth_link_speed = ETH_SPEED_NUM_100G;
3003 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3004 eth_link_speed = ETH_SPEED_NUM_200G;
3006 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3008 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3012 return eth_link_speed;
3015 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3017 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3019 switch (hw_link_duplex) {
3020 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3021 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3023 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3025 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3026 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3029 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3033 return eth_link_duplex;
3036 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3039 struct bnxt_link_info *link_info = bp->link_info;
3041 rc = bnxt_hwrm_port_phy_qcaps(bp);
3043 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3045 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3047 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3051 if (link_info->link_speed)
3053 bnxt_parse_hw_link_speed(link_info->link_speed);
3055 link->link_speed = ETH_SPEED_NUM_NONE;
3056 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3057 link->link_status = link_info->link_up;
3058 link->link_autoneg = link_info->auto_mode ==
3059 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3060 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3065 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3068 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3069 struct bnxt_link_info link_req;
3070 uint16_t speed, autoneg;
3072 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3075 rc = bnxt_validate_link_speed(bp);
3079 memset(&link_req, 0, sizeof(link_req));
3080 link_req.link_up = link_up;
3084 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3085 if (BNXT_CHIP_P5(bp) &&
3086 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3087 /* 40G is not supported as part of media auto detect.
3088 * The speed should be forced and autoneg disabled
3089 * to configure 40G speed.
3091 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3095 /* No auto speeds and no auto_pam4_link. Disable autoneg */
3096 if (bp->link_info->auto_link_speed == 0 &&
3097 bp->link_info->link_signal_mode &&
3098 bp->link_info->auto_pam4_link_speeds == 0)
3101 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3102 bp->link_info->link_signal_mode);
3103 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3104 /* Autoneg can be done only when the FW allows.
3105 * When user configures fixed speed of 40G and later changes to
3106 * any other speed, auto_link_speed/force_link_speed is still set
3107 * to 40G until link comes up at new speed.
3110 !(!BNXT_CHIP_P5(bp) &&
3111 (bp->link_info->auto_link_speed ||
3112 bp->link_info->force_link_speed))) {
3113 link_req.phy_flags |=
3114 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3115 link_req.auto_link_speed_mask =
3116 bnxt_parse_eth_link_speed_mask(bp,
3117 dev_conf->link_speeds);
3119 if (bp->link_info->phy_type ==
3120 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3121 bp->link_info->phy_type ==
3122 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3123 bp->link_info->media_type ==
3124 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3125 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3129 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3130 /* If user wants a particular speed try that first. */
3132 link_req.link_speed = speed;
3133 else if (bp->link_info->force_pam4_link_speed)
3134 link_req.link_speed =
3135 bp->link_info->force_pam4_link_speed;
3136 else if (bp->link_info->auto_pam4_link_speeds)
3137 link_req.link_speed =
3138 bp->link_info->auto_pam4_link_speeds;
3139 else if (bp->link_info->support_pam4_speeds)
3140 link_req.link_speed =
3141 bp->link_info->support_pam4_speeds;
3142 else if (bp->link_info->force_link_speed)
3143 link_req.link_speed = bp->link_info->force_link_speed;
3145 link_req.link_speed = bp->link_info->auto_link_speed;
3146 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3147 * zero. Use the auto_link_speed.
3149 if (bp->link_info->auto_link_speed != 0 &&
3150 bp->link_info->auto_pam4_link_speeds == 0)
3151 link_req.link_speed = bp->link_info->auto_link_speed;
3153 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3154 link_req.auto_pause = bp->link_info->auto_pause;
3155 link_req.force_pause = bp->link_info->force_pause;
3158 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3161 "Set link config failed with rc %d\n", rc);
3169 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3171 struct hwrm_func_qcfg_input req = {0};
3172 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3175 bp->func_svif = BNXT_SVIF_INVALID;
3178 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3179 req.fid = rte_cpu_to_le_16(0xffff);
3181 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3183 HWRM_CHECK_RESULT();
3185 /* Hard Coded.. 0xfff VLAN ID mask */
3186 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3188 svif_info = rte_le_to_cpu_16(resp->svif_info);
3189 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3190 bp->func_svif = svif_info &
3191 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3193 flags = rte_le_to_cpu_16(resp->flags);
3194 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3195 bp->flags |= BNXT_FLAG_MULTI_HOST;
3198 !BNXT_VF_IS_TRUSTED(bp) &&
3199 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3200 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3201 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3202 } else if (BNXT_VF(bp) &&
3203 BNXT_VF_IS_TRUSTED(bp) &&
3204 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3205 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3206 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3210 *mtu = rte_le_to_cpu_16(resp->mtu);
3212 switch (resp->port_partition_type) {
3213 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3214 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3215 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3217 bp->flags |= BNXT_FLAG_NPAR_PF;
3220 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3224 bp->legacy_db_size =
3225 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3232 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3234 struct hwrm_func_qcfg_input req = {0};
3235 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3238 if (!BNXT_VF_IS_TRUSTED(bp))
3244 bp->parent->fid = BNXT_PF_FID_INVALID;
3246 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3248 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3250 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3252 HWRM_CHECK_RESULT();
3254 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3255 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3256 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3257 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3259 /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3260 if (bp->parent->vnic == 0) {
3261 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3262 /* Use hard-coded values appropriate for current Wh+ fw. */
3263 if (bp->parent->fid == 2)
3264 bp->parent->vnic = 0x100;
3266 bp->parent->vnic = 1;
3274 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3275 uint16_t *vnic_id, uint16_t *svif)
3277 struct hwrm_func_qcfg_input req = {0};
3278 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3282 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3283 req.fid = rte_cpu_to_le_16(fid);
3285 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3287 HWRM_CHECK_RESULT();
3290 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3292 svif_info = rte_le_to_cpu_16(resp->svif_info);
3293 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3294 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3301 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3303 struct hwrm_port_mac_qcfg_input req = {0};
3304 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3305 uint16_t port_svif_info;
3308 bp->port_svif = BNXT_SVIF_INVALID;
3310 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3313 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3315 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3317 HWRM_CHECK_RESULT_SILENT();
3319 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3320 if (port_svif_info &
3321 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3322 bp->port_svif = port_svif_info &
3323 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3330 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3331 struct bnxt_pf_resource_info *pf_resc)
3333 struct hwrm_func_cfg_input req = {0};
3334 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3338 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3339 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3340 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3341 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3342 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3343 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3344 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3345 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3346 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3348 if (BNXT_HAS_RING_GRPS(bp)) {
3349 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3350 req.num_hw_ring_grps =
3351 rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3352 } else if (BNXT_HAS_NQ(bp)) {
3353 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3354 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3357 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3358 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3359 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3360 req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3361 req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3362 req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3363 req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3364 req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3365 req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3366 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3367 req.fid = rte_cpu_to_le_16(0xffff);
3368 req.enables = rte_cpu_to_le_32(enables);
3370 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3372 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3374 HWRM_CHECK_RESULT();
3380 /* min values are the guaranteed resources and max values are subject
3381 * to availability. The strategy for now is to keep both min & max
3385 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3386 struct hwrm_func_vf_resource_cfg_input *req,
3389 req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3391 req->min_rsscos_ctx = req->max_rsscos_ctx;
3392 req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3393 req->min_stat_ctx = req->max_stat_ctx;
3394 req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3396 req->min_cmpl_rings = req->max_cmpl_rings;
3397 req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3398 req->min_tx_rings = req->max_tx_rings;
3399 req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3400 req->min_rx_rings = req->max_rx_rings;
3401 req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3402 req->min_l2_ctxs = req->max_l2_ctxs;
3403 /* TODO: For now, do not support VMDq/RFS on VFs. */
3404 req->max_vnics = rte_cpu_to_le_16(1);
3405 req->min_vnics = req->max_vnics;
3406 req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3408 req->min_hw_ring_grps = req->max_hw_ring_grps;
3410 rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3414 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3415 struct hwrm_func_cfg_input *req,
3418 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3419 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3420 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3421 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3422 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3423 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3424 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3425 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3426 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3427 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3429 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3430 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3432 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3433 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3435 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3436 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3438 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3439 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3440 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3441 /* TODO: For now, do not support VMDq/RFS on VFs. */
3442 req->num_vnics = rte_cpu_to_le_16(1);
3443 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3447 /* Update the port wide resource values based on how many resources
3448 * got allocated to the VF.
3450 static int bnxt_update_max_resources(struct bnxt *bp,
3453 struct hwrm_func_qcfg_input req = {0};
3454 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3457 /* Get the actual allocated values now */
3458 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3459 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3460 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3461 HWRM_CHECK_RESULT();
3463 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3464 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3465 bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3466 bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3467 bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3468 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3469 bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3476 /* Update the PF resource values based on how many resources
3477 * got allocated to it.
3479 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3481 struct hwrm_func_qcfg_input req = {0};
3482 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3485 /* Get the actual allocated values now */
3486 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3487 req.fid = rte_cpu_to_le_16(0xffff);
3488 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3489 HWRM_CHECK_RESULT();
3491 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3492 bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3493 bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3494 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3495 bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3496 bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3497 bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3498 bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3505 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3507 struct hwrm_func_qcfg_input req = {0};
3508 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3511 /* Check for zero MAC address */
3512 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3513 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3514 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3515 HWRM_CHECK_RESULT();
3516 rc = rte_le_to_cpu_16(resp->vlan);
3523 static int bnxt_query_pf_resources(struct bnxt *bp,
3524 struct bnxt_pf_resource_info *pf_resc)
3526 struct hwrm_func_qcfg_input req = {0};
3527 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3530 /* And copy the allocated numbers into the pf struct */
3531 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3532 req.fid = rte_cpu_to_le_16(0xffff);
3533 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3534 HWRM_CHECK_RESULT();
3536 pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3537 pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3538 pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3539 pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3540 pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3541 pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3542 pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3543 bp->pf->evb_mode = resp->evb_mode;
3551 bnxt_calculate_pf_resources(struct bnxt *bp,
3552 struct bnxt_pf_resource_info *pf_resc,
3556 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3557 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3558 pf_resc->num_cp_rings = bp->max_cp_rings;
3559 pf_resc->num_tx_rings = bp->max_tx_rings;
3560 pf_resc->num_rx_rings = bp->max_rx_rings;
3561 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3562 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3567 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3568 bp->max_rsscos_ctx % (num_vfs + 1);
3569 pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3570 bp->max_stat_ctx % (num_vfs + 1);
3571 pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3572 bp->max_cp_rings % (num_vfs + 1);
3573 pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3574 bp->max_tx_rings % (num_vfs + 1);
3575 pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3576 bp->max_rx_rings % (num_vfs + 1);
3577 pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3578 bp->max_l2_ctx % (num_vfs + 1);
3579 pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3580 bp->max_ring_grps % (num_vfs + 1);
3583 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3585 struct bnxt_pf_resource_info pf_resc = { 0 };
3589 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3593 rc = bnxt_hwrm_func_qcaps(bp);
3597 bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3599 bp->pf->func_cfg_flags &=
3600 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3601 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3602 bp->pf->func_cfg_flags |=
3603 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3605 rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3609 rc = bnxt_update_max_resources_pf_only(bp);
3615 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3617 size_t req_buf_sz, sz;
3620 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3621 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3622 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3623 if (bp->pf->vf_req_buf == NULL) {
3627 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3628 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3630 for (i = 0; i < num_vfs; i++)
3631 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3632 (i * HWRM_MAX_REQ_LEN);
3634 rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3636 rte_free(bp->pf->vf_req_buf);
3642 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3644 struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3645 struct hwrm_func_vf_resource_cfg_input req = {0};
3648 bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3649 bp->pf->active_vfs = 0;
3650 for (i = 0; i < num_vfs; i++) {
3651 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3652 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3653 rc = bnxt_hwrm_send_message(bp,
3657 if (rc || resp->error_code) {
3659 "Failed to initialize VF %d\n", i);
3661 "Not all VFs available. (%d, %d)\n",
3662 rc, resp->error_code);
3665 /* If the first VF configuration itself fails,
3666 * unregister the vf_fwd_request buffer.
3669 bnxt_hwrm_func_buf_unrgtr(bp);
3674 /* Update the max resource values based on the resource values
3675 * allocated to the VF.
3677 bnxt_update_max_resources(bp, i);
3678 bp->pf->active_vfs++;
3679 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3686 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3688 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3689 struct hwrm_func_cfg_input req = {0};
3692 bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3694 bp->pf->active_vfs = 0;
3695 for (i = 0; i < num_vfs; i++) {
3696 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3697 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3698 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3699 rc = bnxt_hwrm_send_message(bp,
3704 /* Clear enable flag for next pass */
3705 req.enables &= ~rte_cpu_to_le_32(
3706 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3708 if (rc || resp->error_code) {
3710 "Failed to initialize VF %d\n", i);
3712 "Not all VFs available. (%d, %d)\n",
3713 rc, resp->error_code);
3716 /* If the first VF configuration itself fails,
3717 * unregister the vf_fwd_request buffer.
3720 bnxt_hwrm_func_buf_unrgtr(bp);
3726 /* Update the max resource values based on the resource values
3727 * allocated to the VF.
3729 bnxt_update_max_resources(bp, i);
3730 bp->pf->active_vfs++;
3731 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3738 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3740 if (bp->flags & BNXT_FLAG_NEW_RM)
3741 bnxt_process_vf_resc_config_new(bp, num_vfs);
3743 bnxt_process_vf_resc_config_old(bp, num_vfs);
3747 bnxt_update_pf_resources(struct bnxt *bp,
3748 struct bnxt_pf_resource_info *pf_resc)
3750 bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3751 bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3752 bp->max_cp_rings = pf_resc->num_cp_rings;
3753 bp->max_tx_rings = pf_resc->num_tx_rings;
3754 bp->max_rx_rings = pf_resc->num_rx_rings;
3755 bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3759 bnxt_configure_pf_resources(struct bnxt *bp,
3760 struct bnxt_pf_resource_info *pf_resc)
3763 * We're using STD_TX_RING_MODE here which will limit the TX
3764 * rings. This will allow QoS to function properly. Not setting this
3765 * will cause PF rings to break bandwidth settings.
3767 bp->pf->func_cfg_flags &=
3768 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3769 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3770 bp->pf->func_cfg_flags |=
3771 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3772 return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3775 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3777 struct bnxt_pf_resource_info pf_resc = { 0 };
3781 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3785 rc = bnxt_hwrm_func_qcaps(bp);
3789 bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3791 rc = bnxt_configure_pf_resources(bp, &pf_resc);
3795 rc = bnxt_query_pf_resources(bp, &pf_resc);
3800 * Now, create and register a buffer to hold forwarded VF requests
3802 rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3806 bnxt_configure_vf_resources(bp, num_vfs);
3808 bnxt_update_pf_resources(bp, &pf_resc);
3813 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3815 struct hwrm_func_cfg_input req = {0};
3816 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3819 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3821 req.fid = rte_cpu_to_le_16(0xffff);
3822 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3823 req.evb_mode = bp->pf->evb_mode;
3825 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3826 HWRM_CHECK_RESULT();
3832 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3833 uint8_t tunnel_type)
3835 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3836 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3839 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3840 req.tunnel_type = tunnel_type;
3841 req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3842 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3843 HWRM_CHECK_RESULT();
3845 switch (tunnel_type) {
3846 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3847 bp->vxlan_fw_dst_port_id =
3848 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3849 bp->vxlan_port = port;
3851 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3852 bp->geneve_fw_dst_port_id =
3853 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3854 bp->geneve_port = port;
3865 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3866 uint8_t tunnel_type)
3868 struct hwrm_tunnel_dst_port_free_input req = {0};
3869 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3872 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3874 req.tunnel_type = tunnel_type;
3875 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3876 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3878 HWRM_CHECK_RESULT();
3882 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
3884 bp->vxlan_port_cnt = 0;
3888 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
3889 bp->geneve_port = 0;
3890 bp->geneve_port_cnt = 0;
3896 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3899 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3900 struct hwrm_func_cfg_input req = {0};
3903 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3905 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3906 req.flags = rte_cpu_to_le_32(flags);
3907 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3909 HWRM_CHECK_RESULT();
3915 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3917 uint32_t *flag = flagp;
3919 vnic->flags = *flag;
3922 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3924 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3927 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
3929 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3930 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3933 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3935 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3936 req.req_buf_page_size =
3937 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
3938 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3939 req.req_buf_page_addr0 =
3940 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3941 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3943 "unable to map buffer address to physical memory\n");
3948 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3950 HWRM_CHECK_RESULT();
3956 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3959 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3960 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3962 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3965 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3967 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3969 HWRM_CHECK_RESULT();
3975 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3977 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3978 struct hwrm_func_cfg_input req = {0};
3981 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3983 req.fid = rte_cpu_to_le_16(0xffff);
3984 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3985 req.enables = rte_cpu_to_le_32(
3986 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3987 req.async_event_cr = rte_cpu_to_le_16(
3988 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3989 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3991 HWRM_CHECK_RESULT();
3997 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3999 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4000 struct hwrm_func_vf_cfg_input req = {0};
4003 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4005 req.enables = rte_cpu_to_le_32(
4006 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4007 req.async_event_cr = rte_cpu_to_le_16(
4008 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4009 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4011 HWRM_CHECK_RESULT();
4017 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4019 struct hwrm_func_cfg_input req = {0};
4020 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4021 uint16_t dflt_vlan, fid;
4022 uint32_t func_cfg_flags;
4025 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4028 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4029 fid = bp->pf->vf_info[vf].fid;
4030 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4032 fid = rte_cpu_to_le_16(0xffff);
4033 func_cfg_flags = bp->pf->func_cfg_flags;
4034 dflt_vlan = bp->vlan;
4037 req.flags = rte_cpu_to_le_32(func_cfg_flags);
4038 req.fid = rte_cpu_to_le_16(fid);
4039 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4040 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4042 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4044 HWRM_CHECK_RESULT();
4050 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4051 uint16_t max_bw, uint16_t enables)
4053 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4054 struct hwrm_func_cfg_input req = {0};
4057 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4059 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4060 req.enables |= rte_cpu_to_le_32(enables);
4061 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4062 req.max_bw = rte_cpu_to_le_32(max_bw);
4063 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4065 HWRM_CHECK_RESULT();
4071 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4073 struct hwrm_func_cfg_input req = {0};
4074 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4077 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4079 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4080 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4081 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4082 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4084 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4086 HWRM_CHECK_RESULT();
4092 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4097 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4099 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4104 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4105 void *encaped, size_t ec_size)
4108 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4109 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4111 if (ec_size > sizeof(req.encap_request))
4114 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4116 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4117 memcpy(req.encap_request, encaped, ec_size);
4119 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4121 HWRM_CHECK_RESULT();
4127 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4128 struct rte_ether_addr *mac)
4130 struct hwrm_func_qcfg_input req = {0};
4131 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4134 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4136 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4137 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4139 HWRM_CHECK_RESULT();
4141 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4148 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4149 void *encaped, size_t ec_size)
4152 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4153 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4155 if (ec_size > sizeof(req.encap_request))
4158 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4160 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4161 memcpy(req.encap_request, encaped, ec_size);
4163 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4165 HWRM_CHECK_RESULT();
4171 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
4172 struct rte_eth_stats *stats, uint8_t rx)
4175 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4176 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4178 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4180 req.stat_ctx_id = rte_cpu_to_le_32(cid);
4182 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4184 HWRM_CHECK_RESULT();
4187 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4188 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4189 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4190 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4191 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4192 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4193 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4194 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4196 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4197 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4198 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4199 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4200 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4201 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4209 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4211 struct hwrm_port_qstats_input req = {0};
4212 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4213 struct bnxt_pf_info *pf = bp->pf;
4216 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4218 req.port_id = rte_cpu_to_le_16(pf->port_id);
4219 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4220 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4221 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4223 HWRM_CHECK_RESULT();
4229 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4231 struct hwrm_port_clr_stats_input req = {0};
4232 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4233 struct bnxt_pf_info *pf = bp->pf;
4236 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4237 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4238 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4241 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4243 req.port_id = rte_cpu_to_le_16(pf->port_id);
4244 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4246 HWRM_CHECK_RESULT();
4252 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4254 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4255 struct hwrm_port_led_qcaps_input req = {0};
4261 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4262 req.port_id = bp->pf->port_id;
4263 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4265 HWRM_CHECK_RESULT();
4267 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4270 bp->leds->num_leds = resp->num_leds;
4271 memcpy(bp->leds, &resp->led0_id,
4272 sizeof(bp->leds[0]) * bp->leds->num_leds);
4273 for (i = 0; i < bp->leds->num_leds; i++) {
4274 struct bnxt_led_info *led = &bp->leds[i];
4276 uint16_t caps = led->led_state_caps;
4278 if (!led->led_group_id ||
4279 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4280 bp->leds->num_leds = 0;
4291 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4293 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4294 struct hwrm_port_led_cfg_input req = {0};
4295 struct bnxt_led_cfg *led_cfg;
4296 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4297 uint16_t duration = 0;
4300 if (!bp->leds->num_leds || BNXT_VF(bp))
4303 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4306 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4307 duration = rte_cpu_to_le_16(500);
4309 req.port_id = bp->pf->port_id;
4310 req.num_leds = bp->leds->num_leds;
4311 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4312 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4313 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4314 led_cfg->led_id = bp->leds[i].led_id;
4315 led_cfg->led_state = led_state;
4316 led_cfg->led_blink_on = duration;
4317 led_cfg->led_blink_off = duration;
4318 led_cfg->led_group_id = bp->leds[i].led_group_id;
4321 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4323 HWRM_CHECK_RESULT();
4329 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4333 struct hwrm_nvm_get_dir_info_input req = {0};
4334 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4336 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4338 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4340 HWRM_CHECK_RESULT();
4342 *entries = rte_le_to_cpu_32(resp->entries);
4343 *length = rte_le_to_cpu_32(resp->entry_length);
4349 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4352 uint32_t dir_entries;
4353 uint32_t entry_length;
4356 rte_iova_t dma_handle;
4357 struct hwrm_nvm_get_dir_entries_input req = {0};
4358 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4360 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4364 *data++ = dir_entries;
4365 *data++ = entry_length;
4367 memset(data, 0xff, len);
4369 buflen = dir_entries * entry_length;
4370 buf = rte_malloc("nvm_dir", buflen, 0);
4373 dma_handle = rte_malloc_virt2iova(buf);
4374 if (dma_handle == RTE_BAD_IOVA) {
4377 "unable to map response address to physical memory\n");
4380 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4381 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4382 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4385 memcpy(data, buf, len > buflen ? buflen : len);
4388 HWRM_CHECK_RESULT();
4394 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4395 uint32_t offset, uint32_t length,
4400 rte_iova_t dma_handle;
4401 struct hwrm_nvm_read_input req = {0};
4402 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4404 buf = rte_malloc("nvm_item", length, 0);
4408 dma_handle = rte_malloc_virt2iova(buf);
4409 if (dma_handle == RTE_BAD_IOVA) {
4412 "unable to map response address to physical memory\n");
4415 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4416 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4417 req.dir_idx = rte_cpu_to_le_16(index);
4418 req.offset = rte_cpu_to_le_32(offset);
4419 req.len = rte_cpu_to_le_32(length);
4420 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4422 memcpy(data, buf, length);
4425 HWRM_CHECK_RESULT();
4431 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4434 struct hwrm_nvm_erase_dir_entry_input req = {0};
4435 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4437 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4438 req.dir_idx = rte_cpu_to_le_16(index);
4439 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4440 HWRM_CHECK_RESULT();
4447 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4448 uint16_t dir_ordinal, uint16_t dir_ext,
4449 uint16_t dir_attr, const uint8_t *data,
4453 struct hwrm_nvm_write_input req = {0};
4454 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4455 rte_iova_t dma_handle;
4458 buf = rte_malloc("nvm_write", data_len, 0);
4462 dma_handle = rte_malloc_virt2iova(buf);
4463 if (dma_handle == RTE_BAD_IOVA) {
4466 "unable to map response address to physical memory\n");
4469 memcpy(buf, data, data_len);
4471 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4473 req.dir_type = rte_cpu_to_le_16(dir_type);
4474 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4475 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4476 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4477 req.dir_data_length = rte_cpu_to_le_32(data_len);
4478 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4480 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4483 HWRM_CHECK_RESULT();
4490 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4492 uint32_t *count = cbdata;
4494 *count = *count + 1;
4497 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4498 struct bnxt_vnic_info *vnic __rte_unused)
4503 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4507 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4508 &count, bnxt_vnic_count_hwrm_stub);
4513 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4516 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4517 struct hwrm_func_vf_vnic_ids_query_output *resp =
4518 bp->hwrm_cmd_resp_addr;
4521 /* First query all VNIC ids */
4522 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4524 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4525 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4526 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4528 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4531 "unable to map VNIC ID table address to physical memory\n");
4534 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4535 HWRM_CHECK_RESULT();
4536 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4544 * This function queries the VNIC IDs for a specified VF. It then calls
4545 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4546 * Then it calls the hwrm_cb function to program this new vnic configuration.
4548 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4549 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4550 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4552 struct bnxt_vnic_info vnic;
4554 int i, num_vnic_ids;
4559 /* First query all VNIC ids */
4560 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4561 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4562 RTE_CACHE_LINE_SIZE);
4563 if (vnic_ids == NULL)
4566 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4567 rte_mem_lock_page(((char *)vnic_ids) + sz);
4569 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4571 if (num_vnic_ids < 0)
4572 return num_vnic_ids;
4574 /* Retrieve VNIC, update bd_stall then update */
4576 for (i = 0; i < num_vnic_ids; i++) {
4577 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4578 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4579 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4582 if (vnic.mru <= 4) /* Indicates unallocated */
4585 vnic_cb(&vnic, cbdata);
4587 rc = hwrm_cb(bp, &vnic);
4597 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4600 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4601 struct hwrm_func_cfg_input req = {0};
4604 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4606 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4607 req.enables |= rte_cpu_to_le_32(
4608 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4609 req.vlan_antispoof_mode = on ?
4610 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4611 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4612 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4614 HWRM_CHECK_RESULT();
4620 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4622 struct bnxt_vnic_info vnic;
4625 int num_vnic_ids, i;
4629 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4630 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4631 RTE_CACHE_LINE_SIZE);
4632 if (vnic_ids == NULL)
4635 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4636 rte_mem_lock_page(((char *)vnic_ids) + sz);
4638 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4644 * Loop through to find the default VNIC ID.
4645 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4646 * by sending the hwrm_func_qcfg command to the firmware.
4648 for (i = 0; i < num_vnic_ids; i++) {
4649 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4650 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4651 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4652 bp->pf->first_vf_id + vf);
4655 if (vnic.func_default) {
4657 return vnic.fw_vnic_id;
4660 /* Could not find a default VNIC. */
4661 PMD_DRV_LOG(ERR, "No default VNIC\n");
4667 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4669 struct bnxt_filter_info *filter)
4672 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4673 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4674 uint32_t enables = 0;
4676 if (filter->fw_em_filter_id != UINT64_MAX)
4677 bnxt_hwrm_clear_em_filter(bp, filter);
4679 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4681 req.flags = rte_cpu_to_le_32(filter->flags);
4683 enables = filter->enables |
4684 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4685 req.dst_id = rte_cpu_to_le_16(dst_id);
4687 if (filter->ip_addr_type) {
4688 req.ip_addr_type = filter->ip_addr_type;
4689 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4692 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4693 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4695 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4696 memcpy(req.src_macaddr, filter->src_macaddr,
4697 RTE_ETHER_ADDR_LEN);
4699 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4700 memcpy(req.dst_macaddr, filter->dst_macaddr,
4701 RTE_ETHER_ADDR_LEN);
4703 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4704 req.ovlan_vid = filter->l2_ovlan;
4706 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4707 req.ivlan_vid = filter->l2_ivlan;
4709 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4710 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4712 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4713 req.ip_protocol = filter->ip_protocol;
4715 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4716 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4718 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4719 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4721 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4722 req.src_port = rte_cpu_to_be_16(filter->src_port);
4724 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4725 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4727 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4728 req.mirror_vnic_id = filter->mirror_vnic_id;
4730 req.enables = rte_cpu_to_le_32(enables);
4732 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4734 HWRM_CHECK_RESULT();
4736 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4742 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4745 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4746 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4748 if (filter->fw_em_filter_id == UINT64_MAX)
4751 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4753 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4755 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4757 HWRM_CHECK_RESULT();
4760 filter->fw_em_filter_id = UINT64_MAX;
4761 filter->fw_l2_filter_id = UINT64_MAX;
4766 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4768 struct bnxt_filter_info *filter)
4771 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4772 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4773 bp->hwrm_cmd_resp_addr;
4774 uint32_t enables = 0;
4776 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4777 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4779 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4781 req.flags = rte_cpu_to_le_32(filter->flags);
4783 enables = filter->enables |
4784 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4785 req.dst_id = rte_cpu_to_le_16(dst_id);
4787 if (filter->ip_addr_type) {
4788 req.ip_addr_type = filter->ip_addr_type;
4790 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4793 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4794 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4796 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4797 memcpy(req.src_macaddr, filter->src_macaddr,
4798 RTE_ETHER_ADDR_LEN);
4800 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4801 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4803 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4804 req.ip_protocol = filter->ip_protocol;
4806 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4807 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4809 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4810 req.src_ipaddr_mask[0] =
4811 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4813 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4814 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4816 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4817 req.dst_ipaddr_mask[0] =
4818 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4820 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4821 req.src_port = rte_cpu_to_le_16(filter->src_port);
4823 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4824 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4826 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4827 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4829 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4830 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4832 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4833 req.mirror_vnic_id = filter->mirror_vnic_id;
4835 req.enables = rte_cpu_to_le_32(enables);
4837 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4839 HWRM_CHECK_RESULT();
4841 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4842 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4848 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4849 struct bnxt_filter_info *filter)
4852 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4853 struct hwrm_cfa_ntuple_filter_free_output *resp =
4854 bp->hwrm_cmd_resp_addr;
4856 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4859 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4861 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4863 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4865 HWRM_CHECK_RESULT();
4868 filter->fw_ntuple_filter_id = UINT64_MAX;
4874 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4876 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4877 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4878 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4879 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4880 uint16_t *ring_tbl = vnic->rss_table;
4881 int nr_ctxs = vnic->num_lb_ctxts;
4882 int max_rings = bp->rx_nr_rings;
4886 for (i = 0, k = 0; i < nr_ctxs; i++) {
4887 struct bnxt_rx_ring_info *rxr;
4888 struct bnxt_cp_ring_info *cpr;
4890 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4892 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4893 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4894 req.hash_mode_flags = vnic->hash_mode;
4896 req.ring_grp_tbl_addr =
4897 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4898 i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
4899 2 * sizeof(*ring_tbl));
4900 req.hash_key_tbl_addr =
4901 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4903 req.ring_table_pair_index = i;
4904 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4906 for (j = 0; j < 64; j++) {
4909 /* Find next active ring. */
4910 for (cnt = 0; cnt < max_rings; cnt++) {
4911 if (rx_queue_state[k] !=
4912 RTE_ETH_QUEUE_STATE_STOPPED)
4914 if (++k == max_rings)
4918 /* Return if no rings are active. */
4919 if (cnt == max_rings) {
4924 /* Add rx/cp ring pair to RSS table. */
4925 rxr = rxqs[k]->rx_ring;
4926 cpr = rxqs[k]->cp_ring;
4928 ring_id = rxr->rx_ring_struct->fw_ring_id;
4929 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4930 ring_id = cpr->cp_ring_struct->fw_ring_id;
4931 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4933 if (++k == max_rings)
4936 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4939 HWRM_CHECK_RESULT();
4946 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4948 unsigned int rss_idx, fw_idx, i;
4950 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4953 if (!(vnic->rss_table && vnic->hash_type))
4956 if (BNXT_CHIP_P5(bp))
4957 return bnxt_vnic_rss_configure_p5(bp, vnic);
4960 * Fill the RSS hash & redirection table with
4961 * ring group ids for all VNICs
4963 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4964 rss_idx++, fw_idx++) {
4965 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4966 fw_idx %= bp->rx_cp_nr_rings;
4967 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4972 if (i == bp->rx_cp_nr_rings)
4975 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4978 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4981 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4982 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4986 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4988 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4989 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4991 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4992 req->num_cmpl_dma_aggr_during_int =
4993 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4995 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4997 /* min timer set to 1/2 of interrupt timer */
4998 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5000 /* buf timer set to 1/4 of interrupt timer */
5001 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5003 req->cmpl_aggr_dma_tmr_during_int =
5004 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5006 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5007 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5008 req->flags = rte_cpu_to_le_16(flags);
5011 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5012 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5014 struct hwrm_ring_aggint_qcaps_input req = {0};
5015 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5020 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5021 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5022 HWRM_CHECK_RESULT();
5024 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5025 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5027 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5028 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5029 agg_req->flags = rte_cpu_to_le_16(flags);
5031 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5032 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5033 agg_req->enables = rte_cpu_to_le_32(enables);
5039 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5040 struct bnxt_coal *coal, uint16_t ring_id)
5042 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5043 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5044 bp->hwrm_cmd_resp_addr;
5047 /* Set ring coalesce parameters only for 100G NICs */
5048 if (BNXT_CHIP_P5(bp)) {
5049 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5051 } else if (bnxt_stratus_device(bp)) {
5052 bnxt_hwrm_set_coal_params(coal, &req);
5058 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5060 req.ring_id = rte_cpu_to_le_16(ring_id);
5061 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5062 HWRM_CHECK_RESULT();
5067 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5068 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5070 struct hwrm_func_backing_store_qcaps_input req = {0};
5071 struct hwrm_func_backing_store_qcaps_output *resp =
5072 bp->hwrm_cmd_resp_addr;
5073 struct bnxt_ctx_pg_info *ctx_pg;
5074 struct bnxt_ctx_mem_info *ctx;
5075 int total_alloc_len;
5076 int rc, i, tqm_rings;
5078 if (!BNXT_CHIP_P5(bp) ||
5079 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5084 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5085 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5086 HWRM_CHECK_RESULT_SILENT();
5088 total_alloc_len = sizeof(*ctx);
5089 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5090 RTE_CACHE_LINE_SIZE);
5096 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5097 ctx->qp_min_qp1_entries =
5098 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5099 ctx->qp_max_l2_entries =
5100 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5101 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5102 ctx->srq_max_l2_entries =
5103 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5104 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5105 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5106 ctx->cq_max_l2_entries =
5107 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5108 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5109 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5110 ctx->vnic_max_vnic_entries =
5111 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5112 ctx->vnic_max_ring_table_entries =
5113 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5114 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5115 ctx->stat_max_entries =
5116 rte_le_to_cpu_32(resp->stat_max_entries);
5117 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5118 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5119 ctx->tqm_min_entries_per_ring =
5120 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5121 ctx->tqm_max_entries_per_ring =
5122 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5123 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5124 if (!ctx->tqm_entries_multiple)
5125 ctx->tqm_entries_multiple = 1;
5126 ctx->mrav_max_entries =
5127 rte_le_to_cpu_32(resp->mrav_max_entries);
5128 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5129 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5130 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5131 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5133 if (!ctx->tqm_fp_rings_count)
5134 ctx->tqm_fp_rings_count = bp->max_q;
5136 tqm_rings = ctx->tqm_fp_rings_count + 1;
5138 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5139 sizeof(*ctx_pg) * tqm_rings,
5140 RTE_CACHE_LINE_SIZE);
5145 for (i = 0; i < tqm_rings; i++, ctx_pg++)
5146 ctx->tqm_mem[i] = ctx_pg;
5154 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5156 struct hwrm_func_backing_store_cfg_input req = {0};
5157 struct hwrm_func_backing_store_cfg_output *resp =
5158 bp->hwrm_cmd_resp_addr;
5159 struct bnxt_ctx_mem_info *ctx = bp->ctx;
5160 struct bnxt_ctx_pg_info *ctx_pg;
5161 uint32_t *num_entries;
5170 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5171 req.enables = rte_cpu_to_le_32(enables);
5173 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5174 ctx_pg = &ctx->qp_mem;
5175 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5176 req.qp_num_qp1_entries =
5177 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5178 req.qp_num_l2_entries =
5179 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5180 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5181 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5182 &req.qpc_pg_size_qpc_lvl,
5186 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5187 ctx_pg = &ctx->srq_mem;
5188 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5189 req.srq_num_l2_entries =
5190 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5191 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5192 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5193 &req.srq_pg_size_srq_lvl,
5197 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5198 ctx_pg = &ctx->cq_mem;
5199 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5200 req.cq_num_l2_entries =
5201 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5202 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5203 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5204 &req.cq_pg_size_cq_lvl,
5208 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5209 ctx_pg = &ctx->vnic_mem;
5210 req.vnic_num_vnic_entries =
5211 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5212 req.vnic_num_ring_table_entries =
5213 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5214 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5215 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5216 &req.vnic_pg_size_vnic_lvl,
5217 &req.vnic_page_dir);
5220 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5221 ctx_pg = &ctx->stat_mem;
5222 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5223 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5224 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5225 &req.stat_pg_size_stat_lvl,
5226 &req.stat_page_dir);
5229 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5230 num_entries = &req.tqm_sp_num_entries;
5231 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5232 pg_dir = &req.tqm_sp_page_dir;
5233 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5234 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5235 if (!(enables & ena))
5238 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5240 ctx_pg = ctx->tqm_mem[i];
5241 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5242 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5246 HWRM_CHECK_RESULT();
5252 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5254 struct hwrm_port_qstats_ext_input req = {0};
5255 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5256 struct bnxt_pf_info *pf = bp->pf;
5259 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5260 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5263 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5265 req.port_id = rte_cpu_to_le_16(pf->port_id);
5266 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5267 req.tx_stat_host_addr =
5268 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5270 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5272 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5273 req.rx_stat_host_addr =
5274 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5276 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5278 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5281 bp->fw_rx_port_stats_ext_size = 0;
5282 bp->fw_tx_port_stats_ext_size = 0;
5284 bp->fw_rx_port_stats_ext_size =
5285 rte_le_to_cpu_16(resp->rx_stat_size);
5286 bp->fw_tx_port_stats_ext_size =
5287 rte_le_to_cpu_16(resp->tx_stat_size);
5290 HWRM_CHECK_RESULT();
5297 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5299 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5300 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5301 bp->hwrm_cmd_resp_addr;
5304 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5305 req.tunnel_type = type;
5306 req.dest_fid = bp->fw_fid;
5307 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5308 HWRM_CHECK_RESULT();
5316 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5318 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5319 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5320 bp->hwrm_cmd_resp_addr;
5323 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5324 req.tunnel_type = type;
5325 req.dest_fid = bp->fw_fid;
5326 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5327 HWRM_CHECK_RESULT();
5334 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5336 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5337 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5338 bp->hwrm_cmd_resp_addr;
5341 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5342 req.src_fid = bp->fw_fid;
5343 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5344 HWRM_CHECK_RESULT();
5347 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5354 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5357 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5358 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5359 bp->hwrm_cmd_resp_addr;
5362 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5363 req.src_fid = bp->fw_fid;
5364 req.tunnel_type = tun_type;
5365 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5366 HWRM_CHECK_RESULT();
5369 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5371 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5378 int bnxt_hwrm_set_mac(struct bnxt *bp)
5380 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5381 struct hwrm_func_vf_cfg_input req = {0};
5387 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5390 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5391 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5393 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5395 HWRM_CHECK_RESULT();
5402 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5404 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5405 struct hwrm_func_drv_if_change_input req = {0};
5409 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5412 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5413 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5414 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5416 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5419 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5423 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5425 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5427 HWRM_CHECK_RESULT();
5428 flags = rte_le_to_cpu_32(resp->flags);
5434 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5435 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5436 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5442 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5444 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5445 struct bnxt_error_recovery_info *info = bp->recovery_info;
5446 struct hwrm_error_recovery_qcfg_input req = {0};
5451 /* Older FW does not have error recovery support */
5452 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5455 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5457 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5459 HWRM_CHECK_RESULT();
5461 flags = rte_le_to_cpu_32(resp->flags);
5462 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5463 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5464 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5465 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5467 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5468 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5473 /* FW returned values are in units of 100msec */
5474 info->driver_polling_freq =
5475 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5476 info->master_func_wait_period =
5477 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5478 info->normal_func_wait_period =
5479 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5480 info->master_func_wait_period_after_reset =
5481 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5482 info->max_bailout_time_after_reset =
5483 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5484 info->status_regs[BNXT_FW_STATUS_REG] =
5485 rte_le_to_cpu_32(resp->fw_health_status_reg);
5486 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5487 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5488 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5489 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5490 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5491 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5492 info->reg_array_cnt =
5493 rte_le_to_cpu_32(resp->reg_array_cnt);
5495 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5500 for (i = 0; i < info->reg_array_cnt; i++) {
5501 info->reset_reg[i] =
5502 rte_le_to_cpu_32(resp->reset_reg[i]);
5503 info->reset_reg_val[i] =
5504 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5505 info->delay_after_reset[i] =
5506 resp->delay_after_reset[i];
5511 /* Map the FW status registers */
5513 rc = bnxt_map_fw_health_status_regs(bp);
5516 rte_free(bp->recovery_info);
5517 bp->recovery_info = NULL;
5522 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5524 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5525 struct hwrm_fw_reset_input req = {0};
5531 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5533 req.embedded_proc_type =
5534 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5535 req.selfrst_status =
5536 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5537 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5539 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5542 HWRM_CHECK_RESULT();
5548 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5550 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5551 struct hwrm_port_ts_query_input req = {0};
5552 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5559 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5562 case BNXT_PTP_FLAGS_PATH_TX:
5563 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5565 case BNXT_PTP_FLAGS_PATH_RX:
5566 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5568 case BNXT_PTP_FLAGS_CURRENT_TIME:
5569 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5573 req.flags = rte_cpu_to_le_32(flags);
5574 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5576 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5578 HWRM_CHECK_RESULT();
5581 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5583 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5590 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5594 struct hwrm_cfa_counter_qcaps_input req = {0};
5595 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5597 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5599 "Not a PF or trusted VF. Command not supported\n");
5603 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5604 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5605 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5607 HWRM_CHECK_RESULT();
5609 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5615 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5618 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5619 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5621 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5623 "Not a PF or trusted VF. Command not supported\n");
5627 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5629 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5630 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5631 req.page_dir = rte_cpu_to_le_64(dma_addr);
5633 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5635 HWRM_CHECK_RESULT();
5637 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5638 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5645 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5648 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5649 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5651 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5653 "Not a PF or trusted VF. Command not supported\n");
5657 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5659 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5661 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5663 HWRM_CHECK_RESULT();
5669 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5670 uint16_t cntr, uint16_t ctx_id,
5671 uint32_t num_entries, bool enable)
5673 struct hwrm_cfa_counter_cfg_input req = {0};
5674 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5678 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5680 "Not a PF or trusted VF. Command not supported\n");
5684 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5686 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5687 req.counter_type = rte_cpu_to_le_16(cntr);
5688 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5689 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5690 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5691 if (dir == BNXT_DIR_RX)
5692 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5693 else if (dir == BNXT_DIR_TX)
5694 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5695 req.flags = rte_cpu_to_le_16(flags);
5696 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5697 req.num_entries = rte_cpu_to_le_32(num_entries);
5699 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5700 HWRM_CHECK_RESULT();
5706 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5707 enum bnxt_flow_dir dir,
5709 uint16_t num_entries)
5711 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5712 struct hwrm_cfa_counter_qstats_input req = {0};
5713 uint16_t flow_ctx_id = 0;
5717 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5719 "Not a PF or trusted VF. Command not supported\n");
5723 if (dir == BNXT_DIR_RX) {
5724 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5725 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5726 } else if (dir == BNXT_DIR_TX) {
5727 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5728 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5731 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5732 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5733 req.counter_type = rte_cpu_to_le_16(cntr);
5734 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5735 req.num_entries = rte_cpu_to_le_16(num_entries);
5736 req.flags = rte_cpu_to_le_16(flags);
5737 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5739 HWRM_CHECK_RESULT();
5745 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5746 uint16_t *first_vf_id)
5749 struct hwrm_func_qcaps_input req = {.req_type = 0 };
5750 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5752 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5754 req.fid = rte_cpu_to_le_16(fid);
5756 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5758 HWRM_CHECK_RESULT();
5761 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5768 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5770 struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5771 struct hwrm_cfa_pair_alloc_input req = {0};
5774 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5776 "Not a PF or trusted VF. Command not supported\n");
5780 HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5781 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5782 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5783 bp->eth_dev->data->name, rep_bp->vf_id);
5785 req.pf_b_id = rep_bp->parent_pf_idx;
5786 req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5787 rte_cpu_to_le_16(rep_bp->vf_id);
5788 req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5789 req.host_b_id = 1; /* TBD - Confirm if this is OK */
5791 req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5792 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5793 req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5794 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5795 req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5796 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5797 req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5798 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5800 req.q_ab = rep_bp->rep_q_r2f;
5801 req.q_ba = rep_bp->rep_q_f2r;
5802 req.fc_ab = rep_bp->rep_fc_r2f;
5803 req.fc_ba = rep_bp->rep_fc_f2r;
5805 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5806 HWRM_CHECK_RESULT();
5809 PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5810 BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5814 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5816 struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5817 struct hwrm_cfa_pair_free_input req = {0};
5820 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5822 "Not a PF or trusted VF. Command not supported\n");
5826 HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5827 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5828 bp->eth_dev->data->name, rep_bp->vf_id);
5829 req.pf_b_id = rep_bp->parent_pf_idx;
5830 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5831 req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5832 rte_cpu_to_le_16(rep_bp->vf_id);
5833 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5834 HWRM_CHECK_RESULT();
5836 PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
5841 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5843 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5844 bp->hwrm_cmd_resp_addr;
5845 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5849 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5852 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5854 "Not a PF or trusted VF. Command not supported\n");
5858 HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
5859 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5861 HWRM_CHECK_RESULT();
5862 flags = rte_le_to_cpu_32(resp->flags);
5865 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
5866 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
5868 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;