drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (BNXT_CHIP_P5(bp)) {
 754                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
 755                         return 0;
 756         } else {
 757                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 758                         return 0;
 759         }
 760
 761         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 762                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 763
 764         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 765         if (!ptp)
 766                 return -ENOMEM;
 767
 768         if (!BNXT_CHIP_P5(bp)) {
 769                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 771                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 773                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 775                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 776                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 777                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 778                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 779                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 781                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 783                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 784                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 785                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 786                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 787         }
 788
 789         ptp->bp = bp;
 790         bp->ptp_cfg = ptp;
 791
 792         return 0;
 793 }
 794
 795 void bnxt_free_vf_info(struct bnxt *bp)
 796 {
 797         int i;
 798
 799         if (bp->pf == NULL)
 800                 return;
 801
 802         if (bp->pf->vf_info == NULL)
 803                 return;
 804
 805         for (i = 0; i < bp->pf->max_vfs; i++) {
 806                 rte_free(bp->pf->vf_info[i].vlan_table);
 807                 bp->pf->vf_info[i].vlan_table = NULL;
 808                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 809                 bp->pf->vf_info[i].vlan_as_table = NULL;
 810         }
 811         rte_free(bp->pf->vf_info);
 812         bp->pf->vf_info = NULL;
 813 }
 814
 815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 816 {
 817         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 818         int i;
 819
 820         if (vf_info)
 821                 bnxt_free_vf_info(bp);
 822
 823         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 824         if (vf_info == NULL) {
 825                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 826                 return -ENOMEM;
 827         }
 828
 829         bp->pf->max_vfs = max_vfs;
 830         for (i = 0; i < max_vfs; i++) {
 831                 vf_info[i].fid = bp->pf->first_vf_id + i;
 832                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 833                                                     getpagesize(), getpagesize());
 834                 if (vf_info[i].vlan_table == NULL) {
 835                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 836                         goto err;
 837                 }
 838                 rte_mem_lock_page(vf_info[i].vlan_table);
 839
 840                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 841                                                        getpagesize(), getpagesize());
 842                 if (vf_info[i].vlan_as_table == NULL) {
 843                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 844                         goto err;
 845                 }
 846                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 847
 848                 STAILQ_INIT(&vf_info[i].filter);
 849         }
 850
 851         bp->pf->vf_info = vf_info;
 852
 853         return 0;
 854 err:
 855         bnxt_free_vf_info(bp);
 856         return -ENOMEM;
 857 }
 858
 859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 860 {
 861         int rc = 0;
 862         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 863         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 864         uint16_t new_max_vfs;
 865         uint32_t flags;
 866
 867         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 868
 869         req.fid = rte_cpu_to_le_16(0xffff);
 870
 871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 872
 873         HWRM_CHECK_RESULT();
 874
 875         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 876         flags = rte_le_to_cpu_32(resp->flags);
 877         if (BNXT_PF(bp)) {
 878                 bp->pf->port_id = resp->port_id;
 879                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 880                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 881                 new_max_vfs = bp->pdev->max_vfs;
 882                 if (new_max_vfs != bp->pf->max_vfs) {
 883                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 884                         if (rc)
 885                                 goto unlock;
 886                 }
 887         }
 888
 889         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 890         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 891                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 892                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 893         } else {
 894                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 895         }
 896         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 897         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 898         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 899         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 900         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 901         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 902         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 903         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 904                 bp->max_l2_ctx += bp->max_rx_em_flows;
 905         /* TODO: For now, do not support VMDq/RFS on VFs. */
 906         if (BNXT_PF(bp)) {
 907                 if (bp->pf->max_vfs)
 908                         bp->max_vnics = 1;
 909                 else
 910                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 911         } else {
 912                 bp->max_vnics = 1;
 913         }
 914         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 915                     bp->max_l2_ctx, bp->max_vnics);
 916         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 917         if (BNXT_PF(bp)) {
 918                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 919                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 920                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 921                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 922                         HWRM_UNLOCK();
 923                         bnxt_hwrm_ptp_qcfg(bp);
 924                 }
 925         }
 926
 927         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 928                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 929
 930         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 931                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 932                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 933         }
 934
 935         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 936                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 937
 938         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 939                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 940
 941         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 942                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 943
 944 unlock:
 945         HWRM_UNLOCK();
 946
 947         return rc;
 948 }
 949
 950 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 951 {
 952         int rc;
 953
 954         rc = __bnxt_hwrm_func_qcaps(bp);
 955         if (rc == -ENOMEM)
 956                 return rc;
 957
 958         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 959                 rc = bnxt_alloc_ctx_mem(bp);
 960                 if (rc)
 961                         return rc;
 962
 963                 /* On older FW,
 964                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 965                  * But the error can be ignored. Return success.
 966                  */
 967                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 968                 if (!rc)
 969                         bp->flags |= BNXT_FLAG_NEW_RM;
 970         }
 971
 972         return 0;
 973 }
 974
 975 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 976 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 977 {
 978         int rc = 0;
 979         uint32_t flags;
 980         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 981         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 982
 983         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 984
 985         req.target_id = rte_cpu_to_le_16(0xffff);
 986
 987         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 988
 989         HWRM_CHECK_RESULT();
 990
 991         flags = rte_le_to_cpu_32(resp->flags);
 992
 993         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 994                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 995                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 996         }
 997
 998         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 999                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1000
1001         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1002                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1003
1004         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1005
1006         HWRM_UNLOCK();
1007
1008         return rc;
1009 }
1010
1011 int bnxt_hwrm_func_reset(struct bnxt *bp)
1012 {
1013         int rc = 0;
1014         struct hwrm_func_reset_input req = {.req_type = 0 };
1015         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1016
1017         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1018
1019         req.enables = rte_cpu_to_le_32(0);
1020
1021         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1022
1023         HWRM_CHECK_RESULT();
1024         HWRM_UNLOCK();
1025
1026         return rc;
1027 }
1028
1029 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1030 {
1031         int rc;
1032         uint32_t flags = 0;
1033         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1034         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1035
1036         if (bp->flags & BNXT_FLAG_REGISTERED)
1037                 return 0;
1038
1039         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1040                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1041         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1042                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1043
1044         /* PFs and trusted VFs should indicate the support of the
1045          * Master capability on non Stingray platform
1046          */
1047         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1048                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1049
1050         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1051         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1052                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1053         req.ver_maj = RTE_VER_YEAR;
1054         req.ver_min = RTE_VER_MONTH;
1055         req.ver_upd = RTE_VER_MINOR;
1056
1057         if (BNXT_PF(bp)) {
1058                 req.enables |= rte_cpu_to_le_32(
1059                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1060                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1061                        RTE_MIN(sizeof(req.vf_req_fwd),
1062                                sizeof(bp->pf->vf_req_fwd)));
1063         }
1064
1065         req.flags = rte_cpu_to_le_32(flags);
1066
1067         req.async_event_fwd[0] |=
1068                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1069                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1070                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1071                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1072                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1073         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1074                 req.async_event_fwd[0] |=
1075                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1076         req.async_event_fwd[1] |=
1077                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1078                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1079         if (BNXT_PF(bp))
1080                 req.async_event_fwd[1] |=
1081                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1082
1083         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1084                 req.async_event_fwd[1] |=
1085                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1086
1087         req.async_event_fwd[2] |=
1088                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
1089
1090         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1091
1092         HWRM_CHECK_RESULT();
1093
1094         flags = rte_le_to_cpu_32(resp->flags);
1095         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1096                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1097
1098         HWRM_UNLOCK();
1099
1100         bp->flags |= BNXT_FLAG_REGISTERED;
1101
1102         return rc;
1103 }
1104
1105 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1106 {
1107         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1108                 return 0;
1109
1110         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1111 }
1112
1113 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1114 {
1115         int rc;
1116         uint32_t flags = 0;
1117         uint32_t enables;
1118         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1119         struct hwrm_func_vf_cfg_input req = {0};
1120
1121         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1122
1123         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1124                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1125                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1126                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1127                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1128
1129         if (BNXT_HAS_RING_GRPS(bp)) {
1130                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1131                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1132         }
1133
1134         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1135         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1136                                             AGG_RING_MULTIPLIER);
1137         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1138         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1139                                               bp->tx_nr_rings +
1140                                               BNXT_NUM_ASYNC_CPR(bp));
1141         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1142         if (bp->vf_resv_strategy ==
1143             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1144                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1145                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1146                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1147                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1148                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1149                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1150         } else if (bp->vf_resv_strategy ==
1151                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1152                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1153                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1154         }
1155
1156         if (test)
1157                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1158                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1159                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1160                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1161                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1162                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1163
1164         if (test && BNXT_HAS_RING_GRPS(bp))
1165                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1166
1167         req.flags = rte_cpu_to_le_32(flags);
1168         req.enables |= rte_cpu_to_le_32(enables);
1169
1170         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1171
1172         if (test)
1173                 HWRM_CHECK_RESULT_SILENT();
1174         else
1175                 HWRM_CHECK_RESULT();
1176
1177         HWRM_UNLOCK();
1178         return rc;
1179 }
1180
1181 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1182 {
1183         int rc;
1184         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1185         struct hwrm_func_resource_qcaps_input req = {0};
1186
1187         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1188         req.fid = rte_cpu_to_le_16(0xffff);
1189
1190         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1191
1192         HWRM_CHECK_RESULT_SILENT();
1193
1194         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1195         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1196         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1197         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1198         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1199         /* func_resource_qcaps does not return max_rx_em_flows.
1200          * So use the value provided by func_qcaps.
1201          */
1202         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1203         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1204                 bp->max_l2_ctx += bp->max_rx_em_flows;
1205         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1206         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1207         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1208         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1209         if (bp->vf_resv_strategy >
1210             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1211                 bp->vf_resv_strategy =
1212                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1213
1214         HWRM_UNLOCK();
1215         return rc;
1216 }
1217
1218 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1219 {
1220         int rc = 0;
1221         struct hwrm_ver_get_input req = {.req_type = 0 };
1222         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1223         uint32_t fw_version;
1224         uint16_t max_resp_len;
1225         char type[RTE_MEMZONE_NAMESIZE];
1226         uint32_t dev_caps_cfg;
1227
1228         bp->max_req_len = HWRM_MAX_REQ_LEN;
1229         bp->hwrm_cmd_timeout = timeout;
1230         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1231
1232         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1233         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1234         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1235
1236         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1237
1238         if (bp->flags & BNXT_FLAG_FW_RESET)
1239                 HWRM_CHECK_RESULT_SILENT();
1240         else
1241                 HWRM_CHECK_RESULT();
1242
1243         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1244                 rc = -EAGAIN;
1245                 goto error;
1246         }
1247
1248         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1249                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1250                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1251                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1252                 resp->hwrm_fw_rsvd_8b);
1253         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1254                      (resp->hwrm_fw_min_8b << 16) |
1255                      (resp->hwrm_fw_bld_8b << 8) |
1256                      resp->hwrm_fw_rsvd_8b;
1257         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1258                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1259
1260         fw_version = resp->hwrm_intf_maj_8b << 16;
1261         fw_version |= resp->hwrm_intf_min_8b << 8;
1262         fw_version |= resp->hwrm_intf_upd_8b;
1263         bp->hwrm_spec_code = fw_version;
1264
1265         /* def_req_timeout value is in milliseconds */
1266         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1267         /* convert timeout to usec */
1268         bp->hwrm_cmd_timeout *= 1000;
1269         if (!bp->hwrm_cmd_timeout)
1270                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1271
1272         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1273                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1274                 rc = -EINVAL;
1275                 goto error;
1276         }
1277
1278         if (bp->max_req_len > resp->max_req_win_len) {
1279                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1280                 rc = -EINVAL;
1281                 goto error;
1282         }
1283
1284         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1285
1286         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1287         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1288         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1289                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1290
1291         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1292         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1293
1294         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1295         bp->max_resp_len = max_resp_len;
1296
1297         if ((dev_caps_cfg &
1298                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1299             (dev_caps_cfg &
1300              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1301                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1302                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1303         }
1304
1305         if (((dev_caps_cfg &
1306               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1307              (dev_caps_cfg &
1308               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1309             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1310                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1311                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1312                         bp->pdev->addr.devid, bp->pdev->addr.function);
1313
1314                 rte_free(bp->hwrm_short_cmd_req_addr);
1315
1316                 bp->hwrm_short_cmd_req_addr =
1317                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1318                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1319                         rc = -ENOMEM;
1320                         goto error;
1321                 }
1322                 bp->hwrm_short_cmd_req_dma_addr =
1323                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1324                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1325                         rte_free(bp->hwrm_short_cmd_req_addr);
1326                         PMD_DRV_LOG(ERR,
1327                                 "Unable to map buffer to physical memory.\n");
1328                         rc = -ENOMEM;
1329                         goto error;
1330                 }
1331         }
1332         if (dev_caps_cfg &
1333             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1334                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1335                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1336         }
1337         if (dev_caps_cfg &
1338             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1339                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1340         if (dev_caps_cfg &
1341             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1342                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1343                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1344         }
1345
1346         if (dev_caps_cfg &
1347             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1348                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1349                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1350         }
1351
1352         if (dev_caps_cfg &
1353             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
1354                 PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
1355                 bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
1356         }
1357
1358 error:
1359         HWRM_UNLOCK();
1360         return rc;
1361 }
1362
1363 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1364 {
1365         int rc;
1366         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1367         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1368
1369         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1370                 return 0;
1371
1372         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1373         req.flags = flags;
1374
1375         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1376
1377         HWRM_CHECK_RESULT();
1378         HWRM_UNLOCK();
1379
1380         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1381                     bp->eth_dev->data->port_id);
1382
1383         return rc;
1384 }
1385
1386 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1387 {
1388         int rc = 0;
1389         struct hwrm_port_phy_cfg_input req = {0};
1390         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1391         uint32_t enables = 0;
1392
1393         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1394
1395         if (conf->link_up) {
1396                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1397                 if (bp->link_info->auto_mode && conf->link_speed) {
1398                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1399                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1400                 }
1401
1402                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1403                 /*
1404                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1405                  * any auto mode, even "none".
1406                  */
1407                 if (!conf->link_speed) {
1408                         /* No speeds specified. Enable AutoNeg - all speeds */
1409                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1410                         req.auto_mode =
1411                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1412                 } else {
1413                         if (bp->link_info->link_signal_mode) {
1414                                 enables |=
1415                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1416                                 req.force_pam4_link_speed =
1417                                         rte_cpu_to_le_16(conf->link_speed);
1418                         } else {
1419                                 req.force_link_speed =
1420                                         rte_cpu_to_le_16(conf->link_speed);
1421                         }
1422                 }
1423                 /* AutoNeg - Advertise speeds specified. */
1424                 if (conf->auto_link_speed_mask &&
1425                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1426                         req.auto_mode =
1427                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1428                         req.auto_link_speed_mask =
1429                                 conf->auto_link_speed_mask;
1430                         if (conf->auto_pam4_link_speeds) {
1431                                 enables |=
1432                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1433                                 req.auto_link_pam4_speed_mask =
1434                                         conf->auto_pam4_link_speeds;
1435                         } else {
1436                                 enables |=
1437                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1438                         }
1439                 }
1440                 if (conf->auto_link_speed &&
1441                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1442                         enables |=
1443                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1444
1445                 req.auto_duplex = conf->duplex;
1446                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1447                 req.auto_pause = conf->auto_pause;
1448                 req.force_pause = conf->force_pause;
1449                 /* Set force_pause if there is no auto or if there is a force */
1450                 if (req.auto_pause && !req.force_pause)
1451                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1452                 else
1453                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1454
1455                 req.enables = rte_cpu_to_le_32(enables);
1456         } else {
1457                 req.flags =
1458                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1459                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1460         }
1461
1462         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1463
1464         HWRM_CHECK_RESULT();
1465         HWRM_UNLOCK();
1466
1467         return rc;
1468 }
1469
1470 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1471                                    struct bnxt_link_info *link_info)
1472 {
1473         int rc = 0;
1474         struct hwrm_port_phy_qcfg_input req = {0};
1475         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1476
1477         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1478
1479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1480
1481         HWRM_CHECK_RESULT();
1482
1483         link_info->phy_link_status = resp->link;
1484         link_info->link_up =
1485                 (link_info->phy_link_status ==
1486                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1487         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1488         link_info->duplex = resp->duplex_cfg;
1489         link_info->pause = resp->pause;
1490         link_info->auto_pause = resp->auto_pause;
1491         link_info->force_pause = resp->force_pause;
1492         link_info->auto_mode = resp->auto_mode;
1493         link_info->phy_type = resp->phy_type;
1494         link_info->media_type = resp->media_type;
1495
1496         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1497         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1498         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1499         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1500         link_info->phy_ver[0] = resp->phy_maj;
1501         link_info->phy_ver[1] = resp->phy_min;
1502         link_info->phy_ver[2] = resp->phy_bld;
1503         link_info->link_signal_mode =
1504                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1505         link_info->force_pam4_link_speed =
1506                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1507         link_info->support_pam4_speeds =
1508                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1509         link_info->auto_pam4_link_speeds =
1510                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1511         HWRM_UNLOCK();
1512
1513         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1514                     link_info->link_speed, link_info->auto_mode,
1515                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1516                     link_info->support_speeds, link_info->force_link_speed);
1517         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1518                     link_info->link_signal_mode,
1519                     link_info->auto_pam4_link_speeds,
1520                     link_info->support_pam4_speeds,
1521                     link_info->force_pam4_link_speed);
1522         return rc;
1523 }
1524
1525 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1526 {
1527         int rc = 0;
1528         struct hwrm_port_phy_qcaps_input req = {0};
1529         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1530         struct bnxt_link_info *link_info = bp->link_info;
1531
1532         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1533                 return 0;
1534
1535         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1536
1537         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1538
1539         HWRM_CHECK_RESULT_SILENT();
1540
1541         bp->port_cnt = resp->port_cnt;
1542         if (resp->supported_speeds_auto_mode)
1543                 link_info->support_auto_speeds =
1544                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1545         if (resp->supported_pam4_speeds_auto_mode)
1546                 link_info->support_pam4_auto_speeds =
1547                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1548
1549         HWRM_UNLOCK();
1550
1551         return 0;
1552 }
1553
1554 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1555 {
1556         int i = 0;
1557
1558         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1559                 if (bp->tx_cos_queue[i].profile ==
1560                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1561                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1562                         return true;
1563                 }
1564         }
1565         return false;
1566 }
1567
1568 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1569 {
1570         int i = 0;
1571
1572         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1573                 if (bp->tx_cos_queue[i].profile !=
1574                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1575                     bp->tx_cos_queue[i].id !=
1576                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1577                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1578                         break;
1579                 }
1580         }
1581 }
1582
1583 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1584 {
1585         int rc = 0;
1586         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1587         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1588         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1589         int i;
1590
1591 get_rx_info:
1592         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1593
1594         req.flags = rte_cpu_to_le_32(dir);
1595         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1596         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1597             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1598                 req.drv_qmap_cap =
1599                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1600         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1601
1602         HWRM_CHECK_RESULT();
1603
1604         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1605                 GET_TX_QUEUE_INFO(0);
1606                 GET_TX_QUEUE_INFO(1);
1607                 GET_TX_QUEUE_INFO(2);
1608                 GET_TX_QUEUE_INFO(3);
1609                 GET_TX_QUEUE_INFO(4);
1610                 GET_TX_QUEUE_INFO(5);
1611                 GET_TX_QUEUE_INFO(6);
1612                 GET_TX_QUEUE_INFO(7);
1613         } else  {
1614                 GET_RX_QUEUE_INFO(0);
1615                 GET_RX_QUEUE_INFO(1);
1616                 GET_RX_QUEUE_INFO(2);
1617                 GET_RX_QUEUE_INFO(3);
1618                 GET_RX_QUEUE_INFO(4);
1619                 GET_RX_QUEUE_INFO(5);
1620                 GET_RX_QUEUE_INFO(6);
1621                 GET_RX_QUEUE_INFO(7);
1622         }
1623
1624         HWRM_UNLOCK();
1625
1626         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1627                 goto done;
1628
1629         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1630                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1631         } else {
1632                 int j;
1633
1634                 /* iterate and find the COSq profile to use for Tx */
1635                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1636                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1637                                 if (bp->tx_cos_queue[i].id != 0xff)
1638                                         bp->tx_cosq_id[j++] =
1639                                                 bp->tx_cos_queue[i].id;
1640                         }
1641                 } else {
1642                         /* When CoS classification is disabled, for normal NIC
1643                          * operations, ideally we should look to use LOSSY.
1644                          * If not found, fallback to the first valid profile
1645                          */
1646                         if (!bnxt_find_lossy_profile(bp))
1647                                 bnxt_find_first_valid_profile(bp);
1648
1649                 }
1650         }
1651
1652         bp->max_tc = resp->max_configurable_queues;
1653         bp->max_lltc = resp->max_configurable_lossless_queues;
1654         if (bp->max_tc > BNXT_MAX_QUEUE)
1655                 bp->max_tc = BNXT_MAX_QUEUE;
1656         bp->max_q = bp->max_tc;
1657
1658         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1659                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1660                 goto get_rx_info;
1661         }
1662
1663 done:
1664         return rc;
1665 }
1666
1667 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1668                          struct bnxt_ring *ring,
1669                          uint32_t ring_type, uint32_t map_index,
1670                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1671                          uint16_t tx_cosq_id)
1672 {
1673         int rc = 0;
1674         uint32_t enables = 0;
1675         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1676         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1677         struct rte_mempool *mb_pool;
1678         uint16_t rx_buf_size;
1679
1680         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1681
1682         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1683         req.fbo = rte_cpu_to_le_32(0);
1684         /* Association of ring index with doorbell index */
1685         req.logical_id = rte_cpu_to_le_16(map_index);
1686         req.length = rte_cpu_to_le_32(ring->ring_size);
1687
1688         switch (ring_type) {
1689         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1690                 req.ring_type = ring_type;
1691                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1692                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1693                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1694                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1695                         enables |=
1696                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1697                 break;
1698         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1699                 req.ring_type = ring_type;
1700                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1701                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1702                 if (BNXT_CHIP_P5(bp)) {
1703                         mb_pool = bp->rx_queues[0]->mb_pool;
1704                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1705                                       RTE_PKTMBUF_HEADROOM;
1706                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1707                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1708                         enables |=
1709                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1710                 }
1711                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1712                         enables |=
1713                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1714                 break;
1715         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1716                 req.ring_type = ring_type;
1717                 if (BNXT_HAS_NQ(bp)) {
1718                         /* Association of cp ring with nq */
1719                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1720                         enables |=
1721                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1722                 }
1723                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1724                 break;
1725         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1726                 req.ring_type = ring_type;
1727                 req.page_size = BNXT_PAGE_SHFT;
1728                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1729                 break;
1730         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1731                 req.ring_type = ring_type;
1732                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1733
1734                 mb_pool = bp->rx_queues[0]->mb_pool;
1735                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1736                               RTE_PKTMBUF_HEADROOM;
1737                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1738                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1739
1740                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1741                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1742                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1743                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1744                 break;
1745         default:
1746                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1747                         ring_type);
1748                 HWRM_UNLOCK();
1749                 return -EINVAL;
1750         }
1751         req.enables = rte_cpu_to_le_32(enables);
1752
1753         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1754
1755         if (rc || resp->error_code) {
1756                 if (rc == 0 && resp->error_code)
1757                         rc = rte_le_to_cpu_16(resp->error_code);
1758                 switch (ring_type) {
1759                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1760                         PMD_DRV_LOG(ERR,
1761                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1762                         HWRM_UNLOCK();
1763                         return rc;
1764                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1765                         PMD_DRV_LOG(ERR,
1766                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1767                         HWRM_UNLOCK();
1768                         return rc;
1769                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1770                         PMD_DRV_LOG(ERR,
1771                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1772                                     rc);
1773                         HWRM_UNLOCK();
1774                         return rc;
1775                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1776                         PMD_DRV_LOG(ERR,
1777                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1778                         HWRM_UNLOCK();
1779                         return rc;
1780                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1781                         PMD_DRV_LOG(ERR,
1782                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1783                         HWRM_UNLOCK();
1784                         return rc;
1785                 default:
1786                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1787                         HWRM_UNLOCK();
1788                         return rc;
1789                 }
1790         }
1791
1792         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1793         HWRM_UNLOCK();
1794         return rc;
1795 }
1796
1797 int bnxt_hwrm_ring_free(struct bnxt *bp,
1798                         struct bnxt_ring *ring, uint32_t ring_type,
1799                         uint16_t cp_ring_id)
1800 {
1801         int rc;
1802         struct hwrm_ring_free_input req = {.req_type = 0 };
1803         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1804
1805         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1806
1807         req.ring_type = ring_type;
1808         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1809         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1810
1811         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1812
1813         if (rc || resp->error_code) {
1814                 if (rc == 0 && resp->error_code)
1815                         rc = rte_le_to_cpu_16(resp->error_code);
1816                 HWRM_UNLOCK();
1817
1818                 switch (ring_type) {
1819                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1820                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1821                                 rc);
1822                         return rc;
1823                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1824                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1825                                 rc);
1826                         return rc;
1827                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1828                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1829                                 rc);
1830                         return rc;
1831                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1832                         PMD_DRV_LOG(ERR,
1833                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1834                         return rc;
1835                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1836                         PMD_DRV_LOG(ERR,
1837                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1838                         return rc;
1839                 default:
1840                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1841                         return rc;
1842                 }
1843         }
1844         HWRM_UNLOCK();
1845         return 0;
1846 }
1847
1848 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1849 {
1850         int rc = 0;
1851         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1852         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1853
1854         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1855
1856         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1857         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1858         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1859         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1860
1861         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1862
1863         HWRM_CHECK_RESULT();
1864
1865         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1866
1867         HWRM_UNLOCK();
1868
1869         return rc;
1870 }
1871
1872 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1873 {
1874         int rc;
1875         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1876         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1877
1878         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1879
1880         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1881
1882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1883
1884         HWRM_CHECK_RESULT();
1885         HWRM_UNLOCK();
1886
1887         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1888         return rc;
1889 }
1890
1891 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1892 {
1893         int rc = 0;
1894         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1895         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1896
1897         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1898                 return rc;
1899
1900         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1901
1902         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1903
1904         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1905
1906         HWRM_CHECK_RESULT();
1907         HWRM_UNLOCK();
1908
1909         return rc;
1910 }
1911
1912 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1913 {
1914         int rc;
1915         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1916         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1917
1918         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1919
1920         req.update_period_ms = rte_cpu_to_le_32(0);
1921
1922         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1923
1924         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1925
1926         HWRM_CHECK_RESULT();
1927
1928         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1929
1930         HWRM_UNLOCK();
1931
1932         return rc;
1933 }
1934
1935 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1936 {
1937         int rc;
1938         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1939         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1940
1941         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1942
1943         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1944
1945         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1946
1947         HWRM_CHECK_RESULT();
1948         HWRM_UNLOCK();
1949
1950         return rc;
1951 }
1952
1953 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1954 {
1955         int rc = 0, i, j;
1956         struct hwrm_vnic_alloc_input req = { 0 };
1957         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1958
1959         if (!BNXT_HAS_RING_GRPS(bp))
1960                 goto skip_ring_grps;
1961
1962         /* map ring groups to this vnic */
1963         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1964                 vnic->start_grp_id, vnic->end_grp_id);
1965         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1966                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1967
1968         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1969         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1970         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1971         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1972
1973 skip_ring_grps:
1974         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1975         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1976
1977         if (vnic->func_default)
1978                 req.flags =
1979                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1980         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1981
1982         HWRM_CHECK_RESULT();
1983
1984         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1985         HWRM_UNLOCK();
1986         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1987         return rc;
1988 }
1989
1990 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1991                                         struct bnxt_vnic_info *vnic,
1992                                         struct bnxt_plcmodes_cfg *pmode)
1993 {
1994         int rc = 0;
1995         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1996         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1997
1998         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1999
2000         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2001
2002         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2003
2004         HWRM_CHECK_RESULT();
2005
2006         pmode->flags = rte_le_to_cpu_32(resp->flags);
2007         /* dflt_vnic bit doesn't exist in the _cfg command */
2008         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2009         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2010         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2011         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2012
2013         HWRM_UNLOCK();
2014
2015         return rc;
2016 }
2017
2018 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2019                                        struct bnxt_vnic_info *vnic,
2020                                        struct bnxt_plcmodes_cfg *pmode)
2021 {
2022         int rc = 0;
2023         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2024         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2025
2026         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2027                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2028                 return rc;
2029         }
2030
2031         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2032
2033         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2034         req.flags = rte_cpu_to_le_32(pmode->flags);
2035         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2036         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2037         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2038         req.enables = rte_cpu_to_le_32(
2039             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2040             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2041             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2042         );
2043
2044         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2045
2046         HWRM_CHECK_RESULT();
2047         HWRM_UNLOCK();
2048
2049         return rc;
2050 }
2051
2052 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2053 {
2054         int rc = 0;
2055         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2056         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2057         struct bnxt_plcmodes_cfg pmodes = { 0 };
2058         uint32_t ctx_enable_flag = 0;
2059         uint32_t enables = 0;
2060
2061         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2062                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2063                 return rc;
2064         }
2065
2066         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2067         if (rc)
2068                 return rc;
2069
2070         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2071
2072         if (BNXT_CHIP_P5(bp)) {
2073                 int dflt_rxq = vnic->start_grp_id;
2074                 struct bnxt_rx_ring_info *rxr;
2075                 struct bnxt_cp_ring_info *cpr;
2076                 struct bnxt_rx_queue *rxq;
2077                 int i;
2078
2079                 /*
2080                  * The first active receive ring is used as the VNIC
2081                  * default receive ring. If there are no active receive
2082                  * rings (all corresponding receive queues are stopped),
2083                  * the first receive ring is used.
2084                  */
2085                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2086                         rxq = bp->eth_dev->data->rx_queues[i];
2087                         if (rxq->rx_started) {
2088                                 dflt_rxq = i;
2089                                 break;
2090                         }
2091                 }
2092
2093                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2094                 rxr = rxq->rx_ring;
2095                 cpr = rxq->cp_ring;
2096
2097                 req.default_rx_ring_id =
2098                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2099                 req.default_cmpl_ring_id =
2100                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2101                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2102                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2103                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2104                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2105                         req.rx_csum_v2_mode =
2106                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2107                 }
2108                 goto config_mru;
2109         }
2110
2111         /* Only RSS support for now TBD: COS & LB */
2112         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2113         if (vnic->lb_rule != 0xffff)
2114                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2115         if (vnic->cos_rule != 0xffff)
2116                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2117         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2118                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2119                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2120         }
2121         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2122                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2123                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2124         }
2125
2126         enables |= ctx_enable_flag;
2127         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2128         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2129         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2130         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2131
2132 config_mru:
2133         req.enables = rte_cpu_to_le_32(enables);
2134         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2135         req.mru = rte_cpu_to_le_16(vnic->mru);
2136         /* Configure default VNIC only once. */
2137         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2138                 req.flags |=
2139                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2140                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2141         }
2142         if (vnic->vlan_strip)
2143                 req.flags |=
2144                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2145         if (vnic->bd_stall)
2146                 req.flags |=
2147                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2148         if (vnic->rss_dflt_cr)
2149                 req.flags |= rte_cpu_to_le_32(
2150                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2151
2152         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2153
2154         HWRM_CHECK_RESULT();
2155         HWRM_UNLOCK();
2156
2157         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2158
2159         return rc;
2160 }
2161
2162 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2163                 int16_t fw_vf_id)
2164 {
2165         int rc = 0;
2166         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2167         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2168
2169         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2170                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2171                 return rc;
2172         }
2173         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2174
2175         req.enables =
2176                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2177         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2178         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2179
2180         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2181
2182         HWRM_CHECK_RESULT();
2183
2184         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2185         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2186         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2187         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2188         vnic->mru = rte_le_to_cpu_16(resp->mru);
2189         vnic->func_default = rte_le_to_cpu_32(
2190                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2191         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2192                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2193         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2194                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2195         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2196                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2197
2198         HWRM_UNLOCK();
2199
2200         return rc;
2201 }
2202
2203 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2204                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2205 {
2206         int rc = 0;
2207         uint16_t ctx_id;
2208         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2209         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2210                                                 bp->hwrm_cmd_resp_addr;
2211
2212         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2213
2214         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2215         HWRM_CHECK_RESULT();
2216
2217         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2218         if (!BNXT_HAS_RING_GRPS(bp))
2219                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2220         else if (ctx_idx == 0)
2221                 vnic->rss_rule = ctx_id;
2222
2223         HWRM_UNLOCK();
2224
2225         return rc;
2226 }
2227
2228 static
2229 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2230                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2231 {
2232         int rc = 0;
2233         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2234         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2235                                                 bp->hwrm_cmd_resp_addr;
2236
2237         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2238                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2239                 return rc;
2240         }
2241         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2242
2243         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2244
2245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2246
2247         HWRM_CHECK_RESULT();
2248         HWRM_UNLOCK();
2249
2250         return rc;
2251 }
2252
2253 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2254 {
2255         int rc = 0;
2256
2257         if (BNXT_CHIP_P5(bp)) {
2258                 int j;
2259
2260                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2261                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2262                                                       vnic,
2263                                                       vnic->fw_grp_ids[j]);
2264                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2265                 }
2266                 vnic->num_lb_ctxts = 0;
2267         } else {
2268                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2269                 vnic->rss_rule = INVALID_HW_RING_ID;
2270         }
2271
2272         return rc;
2273 }
2274
2275 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2276 {
2277         int rc = 0;
2278         struct hwrm_vnic_free_input req = {.req_type = 0 };
2279         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2280
2281         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2282                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2283                 return rc;
2284         }
2285
2286         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2287
2288         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2289
2290         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2291
2292         HWRM_CHECK_RESULT();
2293         HWRM_UNLOCK();
2294
2295         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2296         /* Configure default VNIC again if necessary. */
2297         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2298                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2299
2300         return rc;
2301 }
2302
2303 static int
2304 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2305 {
2306         int i;
2307         int rc = 0;
2308         int nr_ctxs = vnic->num_lb_ctxts;
2309         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2310         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2311
2312         for (i = 0; i < nr_ctxs; i++) {
2313                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2314
2315                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2316                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2317                 req.hash_mode_flags = vnic->hash_mode;
2318
2319                 req.hash_key_tbl_addr =
2320                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2321
2322                 req.ring_grp_tbl_addr =
2323                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2324                                          i * HW_HASH_INDEX_SIZE);
2325                 req.ring_table_pair_index = i;
2326                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2327
2328                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2329                                             BNXT_USE_CHIMP_MB);
2330
2331                 HWRM_CHECK_RESULT();
2332                 HWRM_UNLOCK();
2333         }
2334
2335         return rc;
2336 }
2337
2338 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2339                            struct bnxt_vnic_info *vnic)
2340 {
2341         int rc = 0;
2342         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2343         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2344
2345         if (!vnic->rss_table)
2346                 return 0;
2347
2348         if (BNXT_CHIP_P5(bp))
2349                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2350
2351         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2352
2353         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2354         req.hash_mode_flags = vnic->hash_mode;
2355
2356         req.ring_grp_tbl_addr =
2357             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2358         req.hash_key_tbl_addr =
2359             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2360         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2361         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2362
2363         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2364
2365         HWRM_CHECK_RESULT();
2366         HWRM_UNLOCK();
2367
2368         return rc;
2369 }
2370
2371 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2372                         struct bnxt_vnic_info *vnic)
2373 {
2374         int rc = 0;
2375         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2376         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2377         uint16_t size;
2378
2379         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2380                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2381                 return rc;
2382         }
2383
2384         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2385
2386         req.flags = rte_cpu_to_le_32(
2387                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2388
2389         req.enables = rte_cpu_to_le_32(
2390                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2391
2392         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2393         size -= RTE_PKTMBUF_HEADROOM;
2394         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2395
2396         req.jumbo_thresh = rte_cpu_to_le_16(size);
2397         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2398
2399         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2400
2401         HWRM_CHECK_RESULT();
2402         HWRM_UNLOCK();
2403
2404         return rc;
2405 }
2406
2407 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2408                         struct bnxt_vnic_info *vnic, bool enable)
2409 {
2410         int rc = 0;
2411         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2412         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2413
2414         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2415                 if (enable)
2416                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2417                 return -ENOTSUP;
2418         }
2419
2420         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2421                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2422                 return 0;
2423         }
2424
2425         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2426
2427         if (enable) {
2428                 req.enables = rte_cpu_to_le_32(
2429                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2430                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2431                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2432                 req.flags = rte_cpu_to_le_32(
2433                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2434                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2435                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2436                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2437                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2438                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2439                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2440                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2441                 req.min_agg_len = rte_cpu_to_le_32(512);
2442         }
2443         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2444
2445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2446
2447         HWRM_CHECK_RESULT();
2448         HWRM_UNLOCK();
2449
2450         return rc;
2451 }
2452
2453 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2454 {
2455         struct hwrm_func_cfg_input req = {0};
2456         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2457         int rc;
2458
2459         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2460         req.enables = rte_cpu_to_le_32(
2461                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2462         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2463         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2464
2465         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2466
2467         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2468         HWRM_CHECK_RESULT();
2469         HWRM_UNLOCK();
2470
2471         bp->pf->vf_info[vf].random_mac = false;
2472
2473         return rc;
2474 }
2475
2476 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2477                                   uint64_t *dropped)
2478 {
2479         int rc = 0;
2480         struct hwrm_func_qstats_input req = {.req_type = 0};
2481         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2482
2483         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2484
2485         req.fid = rte_cpu_to_le_16(fid);
2486
2487         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2488
2489         HWRM_CHECK_RESULT();
2490
2491         if (dropped)
2492                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2493
2494         HWRM_UNLOCK();
2495
2496         return rc;
2497 }
2498
2499 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2500                           struct rte_eth_stats *stats,
2501                           struct hwrm_func_qstats_output *func_qstats)
2502 {
2503         int rc = 0;
2504         struct hwrm_func_qstats_input req = {.req_type = 0};
2505         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2506
2507         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2508
2509         req.fid = rte_cpu_to_le_16(fid);
2510
2511         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2512
2513         HWRM_CHECK_RESULT();
2514         if (func_qstats)
2515                 memcpy(func_qstats, resp,
2516                        sizeof(struct hwrm_func_qstats_output));
2517
2518         if (!stats)
2519                 goto exit;
2520
2521         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2522         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2523         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2524         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2525         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2526         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2527
2528         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2529         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2530         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2531         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2532         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2533         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2534
2535         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2536         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2537         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2538
2539 exit:
2540         HWRM_UNLOCK();
2541
2542         return rc;
2543 }
2544
2545 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2546 {
2547         int rc = 0;
2548         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2549         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2550
2551         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2552
2553         req.fid = rte_cpu_to_le_16(fid);
2554
2555         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2556
2557         HWRM_CHECK_RESULT();
2558         HWRM_UNLOCK();
2559
2560         return rc;
2561 }
2562
2563 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2564 {
2565         unsigned int i;
2566         int rc = 0;
2567
2568         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2569                 struct bnxt_tx_queue *txq;
2570                 struct bnxt_rx_queue *rxq;
2571                 struct bnxt_cp_ring_info *cpr;
2572
2573                 if (i >= bp->rx_cp_nr_rings) {
2574                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2575                         cpr = txq->cp_ring;
2576                 } else {
2577                         rxq = bp->rx_queues[i];
2578                         cpr = rxq->cp_ring;
2579                 }
2580
2581                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2582                 if (rc)
2583                         return rc;
2584         }
2585         return 0;
2586 }
2587
2588 static int
2589 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2590 {
2591         int rc;
2592         unsigned int i;
2593         struct bnxt_cp_ring_info *cpr;
2594
2595         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2596
2597                 if (i >= bp->rx_cp_nr_rings) {
2598                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2599                 } else {
2600                         cpr = bp->rx_queues[i]->cp_ring;
2601                         if (BNXT_HAS_RING_GRPS(bp))
2602                                 bp->grp_info[i].fw_stats_ctx = -1;
2603                 }
2604                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2605                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2606                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2607                         if (rc)
2608                                 return rc;
2609                 }
2610         }
2611         return 0;
2612 }
2613
2614 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2615 {
2616         unsigned int i;
2617         int rc = 0;
2618
2619         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2620                 struct bnxt_tx_queue *txq;
2621                 struct bnxt_rx_queue *rxq;
2622                 struct bnxt_cp_ring_info *cpr;
2623
2624                 if (i >= bp->rx_cp_nr_rings) {
2625                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2626                         cpr = txq->cp_ring;
2627                 } else {
2628                         rxq = bp->rx_queues[i];
2629                         cpr = rxq->cp_ring;
2630                 }
2631
2632                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2633
2634                 if (rc)
2635                         return rc;
2636         }
2637         return rc;
2638 }
2639
2640 static int
2641 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2642 {
2643         uint16_t idx;
2644         uint32_t rc = 0;
2645
2646         if (!BNXT_HAS_RING_GRPS(bp))
2647                 return 0;
2648
2649         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2650
2651                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2652                         continue;
2653
2654                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2655
2656                 if (rc)
2657                         return rc;
2658         }
2659         return rc;
2660 }
2661
2662 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2663 {
2664         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2665
2666         bnxt_hwrm_ring_free(bp, cp_ring,
2667                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2668                             INVALID_HW_RING_ID);
2669         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2670         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2671                                      sizeof(*cpr->cp_desc_ring));
2672         cpr->cp_raw_cons = 0;
2673         cpr->valid = 0;
2674 }
2675
2676 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2677 {
2678         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2679
2680         bnxt_hwrm_ring_free(bp, cp_ring,
2681                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2682                         INVALID_HW_RING_ID);
2683         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2684         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2685                         sizeof(*cpr->cp_desc_ring));
2686         cpr->cp_raw_cons = 0;
2687         cpr->valid = 0;
2688 }
2689
2690 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2691 {
2692         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2693         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2694         struct bnxt_ring *ring = rxr->rx_ring_struct;
2695         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2696
2697         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2698                 bnxt_hwrm_ring_free(bp, ring,
2699                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2700                                     cpr->cp_ring_struct->fw_ring_id);
2701                 ring->fw_ring_id = INVALID_HW_RING_ID;
2702                 if (BNXT_HAS_RING_GRPS(bp))
2703                         bp->grp_info[queue_index].rx_fw_ring_id =
2704                                                         INVALID_HW_RING_ID;
2705         }
2706         ring = rxr->ag_ring_struct;
2707         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2708                 bnxt_hwrm_ring_free(bp, ring,
2709                                     BNXT_CHIP_P5(bp) ?
2710                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2711                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2712                                     cpr->cp_ring_struct->fw_ring_id);
2713                 if (BNXT_HAS_RING_GRPS(bp))
2714                         bp->grp_info[queue_index].ag_fw_ring_id =
2715                                                         INVALID_HW_RING_ID;
2716         }
2717         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2718                 bnxt_free_cp_ring(bp, cpr);
2719
2720         if (BNXT_HAS_RING_GRPS(bp))
2721                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2722 }
2723
2724 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2725 {
2726         int rc;
2727         struct hwrm_ring_reset_input req = {.req_type = 0 };
2728         struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2729
2730         HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2731
2732         req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2733         req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2734         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2735
2736         HWRM_CHECK_RESULT();
2737
2738         HWRM_UNLOCK();
2739
2740         return rc;
2741 }
2742
2743 static int
2744 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2745 {
2746         unsigned int i;
2747
2748         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2749                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2750                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2751                 struct bnxt_ring *ring = txr->tx_ring_struct;
2752                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2753
2754                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2755                         bnxt_hwrm_ring_free(bp, ring,
2756                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX,
2757                                         cpr->cp_ring_struct->fw_ring_id);
2758                         ring->fw_ring_id = INVALID_HW_RING_ID;
2759                         memset(txr->tx_desc_ring, 0,
2760                                         txr->tx_ring_struct->ring_size *
2761                                         sizeof(*txr->tx_desc_ring));
2762                         memset(txr->tx_buf_ring, 0,
2763                                         txr->tx_ring_struct->ring_size *
2764                                         sizeof(*txr->tx_buf_ring));
2765                         txr->tx_raw_prod = 0;
2766                         txr->tx_raw_cons = 0;
2767                 }
2768                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2769                         bnxt_free_cp_ring(bp, cpr);
2770                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2771                 }
2772         }
2773
2774         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2775                 bnxt_free_hwrm_rx_ring(bp, i);
2776
2777         return 0;
2778 }
2779
2780 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2781 {
2782         uint16_t i;
2783         uint32_t rc = 0;
2784
2785         if (!BNXT_HAS_RING_GRPS(bp))
2786                 return 0;
2787
2788         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2789                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2790                 if (rc)
2791                         return rc;
2792         }
2793         return rc;
2794 }
2795
2796 /*
2797  * HWRM utility functions
2798  */
2799
2800 void bnxt_free_hwrm_resources(struct bnxt *bp)
2801 {
2802         /* Release memzone */
2803         rte_free(bp->hwrm_cmd_resp_addr);
2804         rte_free(bp->hwrm_short_cmd_req_addr);
2805         bp->hwrm_cmd_resp_addr = NULL;
2806         bp->hwrm_short_cmd_req_addr = NULL;
2807         bp->hwrm_cmd_resp_dma_addr = 0;
2808         bp->hwrm_short_cmd_req_dma_addr = 0;
2809 }
2810
2811 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2812 {
2813         struct rte_pci_device *pdev = bp->pdev;
2814         char type[RTE_MEMZONE_NAMESIZE];
2815
2816         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2817                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2818         bp->max_resp_len = BNXT_PAGE_SIZE;
2819         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2820         if (bp->hwrm_cmd_resp_addr == NULL)
2821                 return -ENOMEM;
2822         bp->hwrm_cmd_resp_dma_addr =
2823                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2824         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2825                 PMD_DRV_LOG(ERR,
2826                         "unable to map response address to physical memory\n");
2827                 return -ENOMEM;
2828         }
2829         rte_spinlock_init(&bp->hwrm_lock);
2830
2831         return 0;
2832 }
2833
2834 int
2835 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2836 {
2837         int rc = 0;
2838
2839         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2840                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2841                 if (rc)
2842                         return rc;
2843         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2844                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2845                 if (rc)
2846                         return rc;
2847         }
2848
2849         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2850         return rc;
2851 }
2852
2853 static int
2854 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2855 {
2856         struct bnxt_filter_info *filter;
2857         int rc = 0;
2858
2859         STAILQ_FOREACH(filter, &vnic->filter, next) {
2860                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2861                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2862                 bnxt_free_filter(bp, filter);
2863         }
2864         return rc;
2865 }
2866
2867 static int
2868 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2869 {
2870         struct bnxt_filter_info *filter;
2871         struct rte_flow *flow;
2872         int rc = 0;
2873
2874         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2875                 flow = STAILQ_FIRST(&vnic->flow_list);
2876                 filter = flow->filter;
2877                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2878                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2879
2880                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2881                 rte_free(flow);
2882         }
2883         return rc;
2884 }
2885
2886 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2887 {
2888         struct bnxt_filter_info *filter;
2889         int rc = 0;
2890
2891         STAILQ_FOREACH(filter, &vnic->filter, next) {
2892                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2893                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2894                                                      filter);
2895                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2896                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2897                                                          filter);
2898                 else
2899                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2900                                                      filter);
2901                 if (rc)
2902                         break;
2903         }
2904         return rc;
2905 }
2906
2907 static void
2908 bnxt_free_tunnel_ports(struct bnxt *bp)
2909 {
2910         if (bp->vxlan_port_cnt)
2911                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2912                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2913
2914         if (bp->geneve_port_cnt)
2915                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2916                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2917 }
2918
2919 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2920 {
2921         int i;
2922
2923         if (bp->vnic_info == NULL)
2924                 return;
2925
2926         /*
2927          * Cleanup VNICs in reverse order, to make sure the L2 filter
2928          * from vnic0 is last to be cleaned up.
2929          */
2930         for (i = bp->max_vnics - 1; i >= 0; i--) {
2931                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2932
2933                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2934                         continue;
2935
2936                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2937
2938                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2939
2940                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2941
2942                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2943
2944                 bnxt_hwrm_vnic_free(bp, vnic);
2945
2946                 rte_free(vnic->fw_grp_ids);
2947         }
2948         /* Ring resources */
2949         bnxt_free_all_hwrm_rings(bp);
2950         bnxt_free_all_hwrm_ring_grps(bp);
2951         bnxt_free_all_hwrm_stat_ctxs(bp);
2952         bnxt_free_tunnel_ports(bp);
2953 }
2954
2955 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2956 {
2957         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2958
2959         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2960                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2961
2962         switch (conf_link_speed) {
2963         case ETH_LINK_SPEED_10M_HD:
2964         case ETH_LINK_SPEED_100M_HD:
2965                 /* FALLTHROUGH */
2966                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2967         }
2968         return hw_link_duplex;
2969 }
2970
2971 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2972 {
2973         return !conf_link;
2974 }
2975
2976 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2977                                           uint16_t pam4_link)
2978 {
2979         uint16_t eth_link_speed = 0;
2980
2981         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2982                 return ETH_LINK_SPEED_AUTONEG;
2983
2984         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2985         case ETH_LINK_SPEED_100M:
2986         case ETH_LINK_SPEED_100M_HD:
2987                 /* FALLTHROUGH */
2988                 eth_link_speed =
2989                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2990                 break;
2991         case ETH_LINK_SPEED_1G:
2992                 eth_link_speed =
2993                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2994                 break;
2995         case ETH_LINK_SPEED_2_5G:
2996                 eth_link_speed =
2997                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2998                 break;
2999         case ETH_LINK_SPEED_10G:
3000                 eth_link_speed =
3001                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
3002                 break;
3003         case ETH_LINK_SPEED_20G:
3004                 eth_link_speed =
3005                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3006                 break;
3007         case ETH_LINK_SPEED_25G:
3008                 eth_link_speed =
3009                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3010                 break;
3011         case ETH_LINK_SPEED_40G:
3012                 eth_link_speed =
3013                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3014                 break;
3015         case ETH_LINK_SPEED_50G:
3016                 eth_link_speed = pam4_link ?
3017                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3018                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3019                 break;
3020         case ETH_LINK_SPEED_100G:
3021                 eth_link_speed = pam4_link ?
3022                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3023                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3024                 break;
3025         case ETH_LINK_SPEED_200G:
3026                 eth_link_speed =
3027                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3028                 break;
3029         default:
3030                 PMD_DRV_LOG(ERR,
3031                         "Unsupported link speed %d; default to AUTO\n",
3032                         conf_link_speed);
3033                 break;
3034         }
3035         return eth_link_speed;
3036 }
3037
3038 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3039                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3040                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3041                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3042                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3043
3044 static int bnxt_validate_link_speed(struct bnxt *bp)
3045 {
3046         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3047         uint16_t port_id = bp->eth_dev->data->port_id;
3048         uint32_t link_speed_capa;
3049         uint32_t one_speed;
3050
3051         if (link_speed == ETH_LINK_SPEED_AUTONEG)
3052                 return 0;
3053
3054         link_speed_capa = bnxt_get_speed_capabilities(bp);
3055
3056         if (link_speed & ETH_LINK_SPEED_FIXED) {
3057                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3058
3059                 if (one_speed & (one_speed - 1)) {
3060                         PMD_DRV_LOG(ERR,
3061                                 "Invalid advertised speeds (%u) for port %u\n",
3062                                 link_speed, port_id);
3063                         return -EINVAL;
3064                 }
3065                 if ((one_speed & link_speed_capa) != one_speed) {
3066                         PMD_DRV_LOG(ERR,
3067                                 "Unsupported advertised speed (%u) for port %u\n",
3068                                 link_speed, port_id);
3069                         return -EINVAL;
3070                 }
3071         } else {
3072                 if (!(link_speed & link_speed_capa)) {
3073                         PMD_DRV_LOG(ERR,
3074                                 "Unsupported advertised speeds (%u) for port %u\n",
3075                                 link_speed, port_id);
3076                         return -EINVAL;
3077                 }
3078         }
3079         return 0;
3080 }
3081
3082 static uint16_t
3083 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3084 {
3085         uint16_t ret = 0;
3086
3087         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3088                 if (bp->link_info->support_speeds)
3089                         return bp->link_info->support_speeds;
3090                 link_speed = BNXT_SUPPORTED_SPEEDS;
3091         }
3092
3093         if (link_speed & ETH_LINK_SPEED_100M)
3094                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3095         if (link_speed & ETH_LINK_SPEED_100M_HD)
3096                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3097         if (link_speed & ETH_LINK_SPEED_1G)
3098                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3099         if (link_speed & ETH_LINK_SPEED_2_5G)
3100                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3101         if (link_speed & ETH_LINK_SPEED_10G)
3102                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3103         if (link_speed & ETH_LINK_SPEED_20G)
3104                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3105         if (link_speed & ETH_LINK_SPEED_25G)
3106                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3107         if (link_speed & ETH_LINK_SPEED_40G)
3108                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3109         if (link_speed & ETH_LINK_SPEED_50G)
3110                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3111         if (link_speed & ETH_LINK_SPEED_100G)
3112                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3113         if (link_speed & ETH_LINK_SPEED_200G)
3114                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3115         return ret;
3116 }
3117
3118 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3119 {
3120         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3121
3122         switch (hw_link_speed) {
3123         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3124                 eth_link_speed = ETH_SPEED_NUM_100M;
3125                 break;
3126         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3127                 eth_link_speed = ETH_SPEED_NUM_1G;
3128                 break;
3129         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3130                 eth_link_speed = ETH_SPEED_NUM_2_5G;
3131                 break;
3132         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3133                 eth_link_speed = ETH_SPEED_NUM_10G;
3134                 break;
3135         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3136                 eth_link_speed = ETH_SPEED_NUM_20G;
3137                 break;
3138         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3139                 eth_link_speed = ETH_SPEED_NUM_25G;
3140                 break;
3141         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3142                 eth_link_speed = ETH_SPEED_NUM_40G;
3143                 break;
3144         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3145                 eth_link_speed = ETH_SPEED_NUM_50G;
3146                 break;
3147         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3148                 eth_link_speed = ETH_SPEED_NUM_100G;
3149                 break;
3150         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3151                 eth_link_speed = ETH_SPEED_NUM_200G;
3152                 break;
3153         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3154         default:
3155                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3156                         hw_link_speed);
3157                 break;
3158         }
3159         return eth_link_speed;
3160 }
3161
3162 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3163 {
3164         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3165
3166         switch (hw_link_duplex) {
3167         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3168         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3169                 /* FALLTHROUGH */
3170                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3171                 break;
3172         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3173                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3174                 break;
3175         default:
3176                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3177                         hw_link_duplex);
3178                 break;
3179         }
3180         return eth_link_duplex;
3181 }
3182
3183 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3184 {
3185         int rc = 0;
3186         struct bnxt_link_info *link_info = bp->link_info;
3187
3188         rc = bnxt_hwrm_port_phy_qcaps(bp);
3189         if (rc)
3190                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3191
3192         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3193         if (rc) {
3194                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3195                 goto exit;
3196         }
3197
3198         if (link_info->link_speed)
3199                 link->link_speed =
3200                         bnxt_parse_hw_link_speed(link_info->link_speed);
3201         else
3202                 link->link_speed = ETH_SPEED_NUM_NONE;
3203         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3204         link->link_status = link_info->link_up;
3205         link->link_autoneg = link_info->auto_mode ==
3206                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3207                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3208 exit:
3209         return rc;
3210 }
3211
3212 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3213 {
3214         int rc = 0;
3215         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3216         struct bnxt_link_info link_req;
3217         uint16_t speed, autoneg;
3218
3219         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3220                 return 0;
3221
3222         rc = bnxt_validate_link_speed(bp);
3223         if (rc)
3224                 goto error;
3225
3226         memset(&link_req, 0, sizeof(link_req));
3227         link_req.link_up = link_up;
3228         if (!link_up)
3229                 goto port_phy_cfg;
3230
3231         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3232         if (BNXT_CHIP_P5(bp) &&
3233             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3234                 /* 40G is not supported as part of media auto detect.
3235                  * The speed should be forced and autoneg disabled
3236                  * to configure 40G speed.
3237                  */
3238                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3239                 autoneg = 0;
3240         }
3241
3242         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3243         if (bp->link_info->auto_link_speed == 0 &&
3244             bp->link_info->link_signal_mode &&
3245             bp->link_info->auto_pam4_link_speeds == 0)
3246                 autoneg = 0;
3247
3248         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3249                                           bp->link_info->link_signal_mode);
3250         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3251         /* Autoneg can be done only when the FW allows.
3252          * When user configures fixed speed of 40G and later changes to
3253          * any other speed, auto_link_speed/force_link_speed is still set
3254          * to 40G until link comes up at new speed.
3255          */
3256         if (autoneg == 1 &&
3257             !(!BNXT_CHIP_P5(bp) &&
3258               (bp->link_info->auto_link_speed ||
3259                bp->link_info->force_link_speed))) {
3260                 link_req.phy_flags |=
3261                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3262                 link_req.auto_link_speed_mask =
3263                         bnxt_parse_eth_link_speed_mask(bp,
3264                                                        dev_conf->link_speeds);
3265         } else {
3266                 if (bp->link_info->phy_type ==
3267                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3268                     bp->link_info->phy_type ==
3269                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3270                     bp->link_info->media_type ==
3271                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3272                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3273                         return -EINVAL;
3274                 }
3275
3276                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3277                 /* If user wants a particular speed try that first. */
3278                 if (speed)
3279                         link_req.link_speed = speed;
3280                 else if (bp->link_info->force_pam4_link_speed)
3281                         link_req.link_speed =
3282                                 bp->link_info->force_pam4_link_speed;
3283                 else if (bp->link_info->auto_pam4_link_speeds)
3284                         link_req.link_speed =
3285                                 bp->link_info->auto_pam4_link_speeds;
3286                 else if (bp->link_info->support_pam4_speeds)
3287                         link_req.link_speed =
3288                                 bp->link_info->support_pam4_speeds;
3289                 else if (bp->link_info->force_link_speed)
3290                         link_req.link_speed = bp->link_info->force_link_speed;
3291                 else
3292                         link_req.link_speed = bp->link_info->auto_link_speed;
3293                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3294                  * zero. Use the auto_link_speed.
3295                  */
3296                 if (bp->link_info->auto_link_speed != 0 &&
3297                     bp->link_info->auto_pam4_link_speeds == 0)
3298                         link_req.link_speed = bp->link_info->auto_link_speed;
3299         }
3300         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3301         link_req.auto_pause = bp->link_info->auto_pause;
3302         link_req.force_pause = bp->link_info->force_pause;
3303
3304 port_phy_cfg:
3305         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3306         if (rc) {
3307                 PMD_DRV_LOG(ERR,
3308                         "Set link config failed with rc %d\n", rc);
3309         }
3310
3311 error:
3312         return rc;
3313 }
3314
3315 /* JIRA 22088 */
3316 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3317 {
3318         struct hwrm_func_qcfg_input req = {0};
3319         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3320         uint16_t flags;
3321         int rc = 0;
3322         bp->func_svif = BNXT_SVIF_INVALID;
3323         uint16_t svif_info;
3324
3325         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3326         req.fid = rte_cpu_to_le_16(0xffff);
3327
3328         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3329
3330         HWRM_CHECK_RESULT();
3331
3332         /* Hard Coded.. 0xfff VLAN ID mask */
3333         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3334
3335         svif_info = rte_le_to_cpu_16(resp->svif_info);
3336         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3337                 bp->func_svif = svif_info &
3338                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3339
3340         flags = rte_le_to_cpu_16(resp->flags);
3341         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3342                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3343
3344         if (BNXT_VF(bp) &&
3345             !BNXT_VF_IS_TRUSTED(bp) &&
3346             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3347                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3348                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3349         } else if (BNXT_VF(bp) &&
3350                    BNXT_VF_IS_TRUSTED(bp) &&
3351                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3352                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3353                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3354         }
3355
3356         if (mtu)
3357                 *mtu = rte_le_to_cpu_16(resp->mtu);
3358
3359         switch (resp->port_partition_type) {
3360         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3361         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3362         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3363                 /* FALLTHROUGH */
3364                 bp->flags |= BNXT_FLAG_NPAR_PF;
3365                 break;
3366         default:
3367                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3368                 break;
3369         }
3370
3371         bp->legacy_db_size =
3372                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3373
3374         HWRM_UNLOCK();
3375
3376         return rc;
3377 }
3378
3379 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3380 {
3381         struct hwrm_func_qcfg_input req = {0};
3382         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3383         int rc;
3384
3385         if (!BNXT_VF_IS_TRUSTED(bp))
3386                 return 0;
3387
3388         if (!bp->parent)
3389                 return -EINVAL;
3390
3391         bp->parent->fid = BNXT_PF_FID_INVALID;
3392
3393         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3394
3395         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3396
3397         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3398
3399         HWRM_CHECK_RESULT_SILENT();
3400
3401         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3402         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3403         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3404         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3405
3406         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3407         if (bp->parent->vnic == 0) {
3408                 PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
3409                 /* Use hard-coded values appropriate for current Wh+ fw. */
3410                 if (bp->parent->fid == 2)
3411                         bp->parent->vnic = 0x100;
3412                 else
3413                         bp->parent->vnic = 1;
3414         }
3415
3416         HWRM_UNLOCK();
3417
3418         return 0;
3419 }
3420
3421 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3422                                  uint16_t *vnic_id, uint16_t *svif)
3423 {
3424         struct hwrm_func_qcfg_input req = {0};
3425         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3426         uint16_t svif_info;
3427         int rc = 0;
3428
3429         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3430         req.fid = rte_cpu_to_le_16(fid);
3431
3432         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3433
3434         HWRM_CHECK_RESULT();
3435
3436         if (vnic_id)
3437                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3438
3439         svif_info = rte_le_to_cpu_16(resp->svif_info);
3440         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3441                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3442
3443         HWRM_UNLOCK();
3444
3445         return rc;
3446 }
3447
3448 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3449 {
3450         struct hwrm_port_mac_qcfg_input req = {0};
3451         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3452         uint16_t port_svif_info;
3453         int rc;
3454
3455         bp->port_svif = BNXT_SVIF_INVALID;
3456
3457         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3458                 return 0;
3459
3460         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3461
3462         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3463
3464         HWRM_CHECK_RESULT_SILENT();
3465
3466         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3467         if (port_svif_info &
3468             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3469                 bp->port_svif = port_svif_info &
3470                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3471
3472         HWRM_UNLOCK();
3473
3474         return 0;
3475 }
3476
3477 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3478                                  struct bnxt_pf_resource_info *pf_resc)
3479 {
3480         struct hwrm_func_cfg_input req = {0};
3481         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3482         uint32_t enables;
3483         int rc;
3484
3485         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3486                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3487                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3488                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3489                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3490                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3491                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3492                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3493                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3494
3495         if (BNXT_HAS_RING_GRPS(bp)) {
3496                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3497                 req.num_hw_ring_grps =
3498                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3499         } else if (BNXT_HAS_NQ(bp)) {
3500                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3501                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3502         }
3503
3504         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3505         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3506         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3507         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3508         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3509         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3510         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3511         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3512         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3513         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3514         req.fid = rte_cpu_to_le_16(0xffff);
3515         req.enables = rte_cpu_to_le_32(enables);
3516
3517         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3518
3519         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3520
3521         HWRM_CHECK_RESULT();
3522         HWRM_UNLOCK();
3523
3524         return rc;
3525 }
3526
3527 /* min values are the guaranteed resources and max values are subject
3528  * to availability. The strategy for now is to keep both min & max
3529  * values the same.
3530  */
3531 static void
3532 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3533                               struct hwrm_func_vf_resource_cfg_input *req,
3534                               int num_vfs)
3535 {
3536         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3537                                                (num_vfs + 1));
3538         req->min_rsscos_ctx = req->max_rsscos_ctx;
3539         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3540         req->min_stat_ctx = req->max_stat_ctx;
3541         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3542                                                (num_vfs + 1));
3543         req->min_cmpl_rings = req->max_cmpl_rings;
3544         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3545         req->min_tx_rings = req->max_tx_rings;
3546         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3547         req->min_rx_rings = req->max_rx_rings;
3548         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3549         req->min_l2_ctxs = req->max_l2_ctxs;
3550         /* TODO: For now, do not support VMDq/RFS on VFs. */
3551         req->max_vnics = rte_cpu_to_le_16(1);
3552         req->min_vnics = req->max_vnics;
3553         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3554                                                  (num_vfs + 1));
3555         req->min_hw_ring_grps = req->max_hw_ring_grps;
3556         req->flags =
3557          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3558 }
3559
3560 static void
3561 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3562                               struct hwrm_func_cfg_input *req,
3563                               int num_vfs)
3564 {
3565         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3566                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3567                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3568                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3569                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3570                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3571                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3572                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3573                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3574                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3575
3576         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3577                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3578                                     BNXT_NUM_VLANS);
3579         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3580         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3581                                                 (num_vfs + 1));
3582         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3583         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3584                                                (num_vfs + 1));
3585         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3586         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3587         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3588         /* TODO: For now, do not support VMDq/RFS on VFs. */
3589         req->num_vnics = rte_cpu_to_le_16(1);
3590         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3591                                                  (num_vfs + 1));
3592 }
3593
3594 /* Update the port wide resource values based on how many resources
3595  * got allocated to the VF.
3596  */
3597 static int bnxt_update_max_resources(struct bnxt *bp,
3598                                      int vf)
3599 {
3600         struct hwrm_func_qcfg_input req = {0};
3601         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3602         int rc;
3603
3604         /* Get the actual allocated values now */
3605         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3606         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3607         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3608         HWRM_CHECK_RESULT();
3609
3610         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3611         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3612         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3613         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3614         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3615         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3616         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3617
3618         HWRM_UNLOCK();
3619
3620         return 0;
3621 }
3622
3623 /* Update the PF resource values based on how many resources
3624  * got allocated to it.
3625  */
3626 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3627 {
3628         struct hwrm_func_qcfg_input req = {0};
3629         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3630         int rc;
3631
3632         /* Get the actual allocated values now */
3633         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3634         req.fid = rte_cpu_to_le_16(0xffff);
3635         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3636         HWRM_CHECK_RESULT();
3637
3638         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3639         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3640         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3641         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3642         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3643         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3644         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3645         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3646
3647         HWRM_UNLOCK();
3648
3649         return 0;
3650 }
3651
3652 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3653 {
3654         struct hwrm_func_qcfg_input req = {0};
3655         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3656         int rc;
3657
3658         /* Check for zero MAC address */
3659         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3660         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3661         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3662         HWRM_CHECK_RESULT();
3663         rc = rte_le_to_cpu_16(resp->vlan);
3664
3665         HWRM_UNLOCK();
3666
3667         return rc;
3668 }
3669
3670 static int bnxt_query_pf_resources(struct bnxt *bp,
3671                                    struct bnxt_pf_resource_info *pf_resc)
3672 {
3673         struct hwrm_func_qcfg_input req = {0};
3674         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3675         int rc;
3676
3677         /* And copy the allocated numbers into the pf struct */
3678         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3679         req.fid = rte_cpu_to_le_16(0xffff);
3680         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3681         HWRM_CHECK_RESULT();
3682
3683         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3684         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3685         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3686         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3687         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3688         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3689         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3690         bp->pf->evb_mode = resp->evb_mode;
3691
3692         HWRM_UNLOCK();
3693
3694         return rc;
3695 }
3696
3697 static void
3698 bnxt_calculate_pf_resources(struct bnxt *bp,
3699                             struct bnxt_pf_resource_info *pf_resc,
3700                             int num_vfs)
3701 {
3702         if (!num_vfs) {
3703                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3704                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3705                 pf_resc->num_cp_rings = bp->max_cp_rings;
3706                 pf_resc->num_tx_rings = bp->max_tx_rings;
3707                 pf_resc->num_rx_rings = bp->max_rx_rings;
3708                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3709                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3710
3711                 return;
3712         }
3713
3714         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3715                                    bp->max_rsscos_ctx % (num_vfs + 1);
3716         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3717                                  bp->max_stat_ctx % (num_vfs + 1);
3718         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3719                                 bp->max_cp_rings % (num_vfs + 1);
3720         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3721                                 bp->max_tx_rings % (num_vfs + 1);
3722         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3723                                 bp->max_rx_rings % (num_vfs + 1);
3724         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3725                                bp->max_l2_ctx % (num_vfs + 1);
3726         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3727                                     bp->max_ring_grps % (num_vfs + 1);
3728 }
3729
3730 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3731 {
3732         struct bnxt_pf_resource_info pf_resc = { 0 };
3733         int rc;
3734
3735         if (!BNXT_PF(bp)) {
3736                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3737                 return -EINVAL;
3738         }
3739
3740         rc = bnxt_hwrm_func_qcaps(bp);
3741         if (rc)
3742                 return rc;
3743
3744         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3745
3746         bp->pf->func_cfg_flags &=
3747                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3748                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3749         bp->pf->func_cfg_flags |=
3750                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3751
3752         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3753         if (rc)
3754                 return rc;
3755
3756         rc = bnxt_update_max_resources_pf_only(bp);
3757
3758         return rc;
3759 }
3760
3761 static int
3762 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3763 {
3764         size_t req_buf_sz, sz;
3765         int i, rc;
3766
3767         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3768         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3769                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3770         if (bp->pf->vf_req_buf == NULL) {
3771                 return -ENOMEM;
3772         }
3773
3774         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3775                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3776
3777         for (i = 0; i < num_vfs; i++)
3778                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3779                                              (i * HWRM_MAX_REQ_LEN);
3780
3781         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3782         if (rc)
3783                 rte_free(bp->pf->vf_req_buf);
3784
3785         return rc;
3786 }
3787
3788 static int
3789 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3790 {
3791         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3792         struct hwrm_func_vf_resource_cfg_input req = {0};
3793         int i, rc = 0;
3794
3795         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3796         bp->pf->active_vfs = 0;
3797         for (i = 0; i < num_vfs; i++) {
3798                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3799                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3800                 rc = bnxt_hwrm_send_message(bp,
3801                                             &req,
3802                                             sizeof(req),
3803                                             BNXT_USE_CHIMP_MB);
3804                 if (rc || resp->error_code) {
3805                         PMD_DRV_LOG(ERR,
3806                                 "Failed to initialize VF %d\n", i);
3807                         PMD_DRV_LOG(ERR,
3808                                 "Not all VFs available. (%d, %d)\n",
3809                                 rc, resp->error_code);
3810                         HWRM_UNLOCK();
3811
3812                         /* If the first VF configuration itself fails,
3813                          * unregister the vf_fwd_request buffer.
3814                          */
3815                         if (i == 0)
3816                                 bnxt_hwrm_func_buf_unrgtr(bp);
3817                         break;
3818                 }
3819                 HWRM_UNLOCK();
3820
3821                 /* Update the max resource values based on the resource values
3822                  * allocated to the VF.
3823                  */
3824                 bnxt_update_max_resources(bp, i);
3825                 bp->pf->active_vfs++;
3826                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3827         }
3828
3829         return 0;
3830 }
3831
3832 static int
3833 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3834 {
3835         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3836         struct hwrm_func_cfg_input req = {0};
3837         int i, rc;
3838
3839         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3840
3841         bp->pf->active_vfs = 0;
3842         for (i = 0; i < num_vfs; i++) {
3843                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3844                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3845                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3846                 rc = bnxt_hwrm_send_message(bp,
3847                                             &req,
3848                                             sizeof(req),
3849                                             BNXT_USE_CHIMP_MB);
3850
3851                 /* Clear enable flag for next pass */
3852                 req.enables &= ~rte_cpu_to_le_32(
3853                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3854
3855                 if (rc || resp->error_code) {
3856                         PMD_DRV_LOG(ERR,
3857                                 "Failed to initialize VF %d\n", i);
3858                         PMD_DRV_LOG(ERR,
3859                                 "Not all VFs available. (%d, %d)\n",
3860                                 rc, resp->error_code);
3861                         HWRM_UNLOCK();
3862
3863                         /* If the first VF configuration itself fails,
3864                          * unregister the vf_fwd_request buffer.
3865                          */
3866                         if (i == 0)
3867                                 bnxt_hwrm_func_buf_unrgtr(bp);
3868                         break;
3869                 }
3870
3871                 HWRM_UNLOCK();
3872
3873                 /* Update the max resource values based on the resource values
3874                  * allocated to the VF.
3875                  */
3876                 bnxt_update_max_resources(bp, i);
3877                 bp->pf->active_vfs++;
3878                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3879         }
3880
3881         return 0;
3882 }
3883
3884 static void
3885 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3886 {
3887         if (bp->flags & BNXT_FLAG_NEW_RM)
3888                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3889         else
3890                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3891 }
3892
3893 static void
3894 bnxt_update_pf_resources(struct bnxt *bp,
3895                          struct bnxt_pf_resource_info *pf_resc)
3896 {
3897         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3898         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3899         bp->max_cp_rings = pf_resc->num_cp_rings;
3900         bp->max_tx_rings = pf_resc->num_tx_rings;
3901         bp->max_rx_rings = pf_resc->num_rx_rings;
3902         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3903 }
3904
3905 static int32_t
3906 bnxt_configure_pf_resources(struct bnxt *bp,
3907                             struct bnxt_pf_resource_info *pf_resc)
3908 {
3909         /*
3910          * We're using STD_TX_RING_MODE here which will limit the TX
3911          * rings. This will allow QoS to function properly. Not setting this
3912          * will cause PF rings to break bandwidth settings.
3913          */
3914         bp->pf->func_cfg_flags &=
3915                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3916                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3917         bp->pf->func_cfg_flags |=
3918                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3919         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3920 }
3921
3922 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3923 {
3924         struct bnxt_pf_resource_info pf_resc = { 0 };
3925         int rc;
3926
3927         if (!BNXT_PF(bp)) {
3928                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3929                 return -EINVAL;
3930         }
3931
3932         rc = bnxt_hwrm_func_qcaps(bp);
3933         if (rc)
3934                 return rc;
3935
3936         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3937
3938         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3939         if (rc)
3940                 return rc;
3941
3942         rc = bnxt_query_pf_resources(bp, &pf_resc);
3943         if (rc)
3944                 return rc;
3945
3946         /*
3947          * Now, create and register a buffer to hold forwarded VF requests
3948          */
3949         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3950         if (rc)
3951                 return rc;
3952
3953         bnxt_configure_vf_resources(bp, num_vfs);
3954
3955         bnxt_update_pf_resources(bp, &pf_resc);
3956
3957         return 0;
3958 }
3959
3960 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3961 {
3962         struct hwrm_func_cfg_input req = {0};
3963         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3964         int rc;
3965
3966         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3967
3968         req.fid = rte_cpu_to_le_16(0xffff);
3969         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3970         req.evb_mode = bp->pf->evb_mode;
3971
3972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3973         HWRM_CHECK_RESULT();
3974         HWRM_UNLOCK();
3975
3976         return rc;
3977 }
3978
3979 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3980                                 uint8_t tunnel_type)
3981 {
3982         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3983         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3984         int rc = 0;
3985
3986         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3987         req.tunnel_type = tunnel_type;
3988         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3989         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3990         HWRM_CHECK_RESULT();
3991
3992         switch (tunnel_type) {
3993         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3994                 bp->vxlan_fw_dst_port_id =
3995                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3996                 bp->vxlan_port = port;
3997                 break;
3998         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3999                 bp->geneve_fw_dst_port_id =
4000                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
4001                 bp->geneve_port = port;
4002                 break;
4003         default:
4004                 break;
4005         }
4006
4007         HWRM_UNLOCK();
4008
4009         return rc;
4010 }
4011
4012 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4013                                 uint8_t tunnel_type)
4014 {
4015         struct hwrm_tunnel_dst_port_free_input req = {0};
4016         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4017         int rc = 0;
4018
4019         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4020
4021         req.tunnel_type = tunnel_type;
4022         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4023         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4024
4025         HWRM_CHECK_RESULT();
4026         HWRM_UNLOCK();
4027
4028         if (tunnel_type ==
4029             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4030                 bp->vxlan_port = 0;
4031                 bp->vxlan_port_cnt = 0;
4032         }
4033
4034         if (tunnel_type ==
4035             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4036                 bp->geneve_port = 0;
4037                 bp->geneve_port_cnt = 0;
4038         }
4039
4040         return rc;
4041 }
4042
4043 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4044                                         uint32_t flags)
4045 {
4046         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4047         struct hwrm_func_cfg_input req = {0};
4048         int rc;
4049
4050         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4051
4052         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4053         req.flags = rte_cpu_to_le_32(flags);
4054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4055
4056         HWRM_CHECK_RESULT();
4057         HWRM_UNLOCK();
4058
4059         return rc;
4060 }
4061
4062 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4063 {
4064         uint32_t *flag = flagp;
4065
4066         vnic->flags = *flag;
4067 }
4068
4069 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4070 {
4071         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4072 }
4073
4074 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4075 {
4076         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4077         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4078         int rc;
4079
4080         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4081
4082         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4083         req.req_buf_page_size =
4084                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4085         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4086         req.req_buf_page_addr0 =
4087                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4088         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4089                 PMD_DRV_LOG(ERR,
4090                         "unable to map buffer address to physical memory\n");
4091                 HWRM_UNLOCK();
4092                 return -ENOMEM;
4093         }
4094
4095         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4096
4097         HWRM_CHECK_RESULT();
4098         HWRM_UNLOCK();
4099
4100         return rc;
4101 }
4102
4103 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4104 {
4105         int rc = 0;
4106         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4107         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4108
4109         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4110                 return 0;
4111
4112         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4113
4114         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4115
4116         HWRM_CHECK_RESULT();
4117         HWRM_UNLOCK();
4118
4119         return rc;
4120 }
4121
4122 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4123 {
4124         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4125         struct hwrm_func_cfg_input req = {0};
4126         int rc;
4127
4128         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4129
4130         req.fid = rte_cpu_to_le_16(0xffff);
4131         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4132         req.enables = rte_cpu_to_le_32(
4133                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4134         req.async_event_cr = rte_cpu_to_le_16(
4135                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4136         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4137
4138         HWRM_CHECK_RESULT();
4139         HWRM_UNLOCK();
4140
4141         return rc;
4142 }
4143
4144 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4145 {
4146         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4147         struct hwrm_func_vf_cfg_input req = {0};
4148         int rc;
4149
4150         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4151
4152         req.enables = rte_cpu_to_le_32(
4153                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4154         req.async_event_cr = rte_cpu_to_le_16(
4155                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4157
4158         HWRM_CHECK_RESULT();
4159         HWRM_UNLOCK();
4160
4161         return rc;
4162 }
4163
4164 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4165 {
4166         struct hwrm_func_cfg_input req = {0};
4167         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4168         uint16_t dflt_vlan, fid;
4169         uint32_t func_cfg_flags;
4170         int rc = 0;
4171
4172         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4173
4174         if (is_vf) {
4175                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4176                 fid = bp->pf->vf_info[vf].fid;
4177                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4178         } else {
4179                 fid = rte_cpu_to_le_16(0xffff);
4180                 func_cfg_flags = bp->pf->func_cfg_flags;
4181                 dflt_vlan = bp->vlan;
4182         }
4183
4184         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4185         req.fid = rte_cpu_to_le_16(fid);
4186         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4187         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4188
4189         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4190
4191         HWRM_CHECK_RESULT();
4192         HWRM_UNLOCK();
4193
4194         return rc;
4195 }
4196
4197 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4198                         uint16_t max_bw, uint16_t enables)
4199 {
4200         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4201         struct hwrm_func_cfg_input req = {0};
4202         int rc;
4203
4204         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4205
4206         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4207         req.enables |= rte_cpu_to_le_32(enables);
4208         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4209         req.max_bw = rte_cpu_to_le_32(max_bw);
4210         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4211
4212         HWRM_CHECK_RESULT();
4213         HWRM_UNLOCK();
4214
4215         return rc;
4216 }
4217
4218 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4219 {
4220         struct hwrm_func_cfg_input req = {0};
4221         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4222         int rc = 0;
4223
4224         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4225
4226         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4227         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4228         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4229         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4230
4231         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4232
4233         HWRM_CHECK_RESULT();
4234         HWRM_UNLOCK();
4235
4236         return rc;
4237 }
4238
4239 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4240 {
4241         int rc;
4242
4243         if (BNXT_PF(bp))
4244                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4245         else
4246                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4247
4248         return rc;
4249 }
4250
4251 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4252                               void *encaped, size_t ec_size)
4253 {
4254         int rc = 0;
4255         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4256         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4257
4258         if (ec_size > sizeof(req.encap_request))
4259                 return -1;
4260
4261         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4262
4263         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4264         memcpy(req.encap_request, encaped, ec_size);
4265
4266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4267
4268         HWRM_CHECK_RESULT();
4269         HWRM_UNLOCK();
4270
4271         return rc;
4272 }
4273
4274 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4275                                        struct rte_ether_addr *mac)
4276 {
4277         struct hwrm_func_qcfg_input req = {0};
4278         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4279         int rc;
4280
4281         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4282
4283         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4284         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4285
4286         HWRM_CHECK_RESULT();
4287
4288         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4289
4290         HWRM_UNLOCK();
4291
4292         return rc;
4293 }
4294
4295 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4296                             void *encaped, size_t ec_size)
4297 {
4298         int rc = 0;
4299         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4300         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4301
4302         if (ec_size > sizeof(req.encap_request))
4303                 return -1;
4304
4305         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4306
4307         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4308         memcpy(req.encap_request, encaped, ec_size);
4309
4310         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4311
4312         HWRM_CHECK_RESULT();
4313         HWRM_UNLOCK();
4314
4315         return rc;
4316 }
4317
4318 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4319 {
4320         /* One of the HW stat values that make up this counter was zero as
4321          * returned by HW in this iteration, so use the previous
4322          * iteration's counter value
4323          */
4324         if (*prev_cntr && *cntr == 0)
4325                 *cntr = *prev_cntr;
4326         else
4327                 *prev_cntr = *cntr;
4328 }
4329
4330 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4331                          struct bnxt_ring_stats *ring_stats, bool rx)
4332 {
4333         int rc = 0;
4334         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4335         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4336
4337         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4338
4339         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4340
4341         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4342
4343         HWRM_CHECK_RESULT();
4344
4345         if (rx) {
4346                 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4347
4348                 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4349                 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4350                                       &prev_stats->rx_ucast_pkts);
4351
4352                 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4353                 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4354                                       &prev_stats->rx_mcast_pkts);
4355
4356                 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4357                 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4358                                       &prev_stats->rx_bcast_pkts);
4359
4360                 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4361                 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4362                                       &prev_stats->rx_ucast_bytes);
4363
4364                 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4365                 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4366                                       &prev_stats->rx_mcast_bytes);
4367
4368                 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4369                 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4370                                       &prev_stats->rx_bcast_bytes);
4371
4372                 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4373                 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4374                                       &prev_stats->rx_discard_pkts);
4375
4376                 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4377                 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4378                                       &prev_stats->rx_error_pkts);
4379
4380                 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4381                 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4382                                       &prev_stats->rx_agg_pkts);
4383
4384                 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4385                 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4386                                       &prev_stats->rx_agg_bytes);
4387
4388                 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4389                 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4390                                       &prev_stats->rx_agg_events);
4391
4392                 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4393                 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4394                                       &prev_stats->rx_agg_aborts);
4395         } else {
4396                 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4397
4398                 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4399                 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4400                                       &prev_stats->tx_ucast_pkts);
4401
4402                 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4403                 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4404                                       &prev_stats->tx_mcast_pkts);
4405
4406                 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4407                 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4408                                       &prev_stats->tx_bcast_pkts);
4409
4410                 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4411                 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4412                                       &prev_stats->tx_ucast_bytes);
4413
4414                 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4415                 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4416                                       &prev_stats->tx_mcast_bytes);
4417
4418                 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4419                 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4420                                       &prev_stats->tx_bcast_bytes);
4421
4422                 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4423                 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4424                                       &prev_stats->tx_discard_pkts);
4425         }
4426
4427         HWRM_UNLOCK();
4428
4429         return rc;
4430 }
4431
4432 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4433 {
4434         struct hwrm_port_qstats_input req = {0};
4435         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4436         struct bnxt_pf_info *pf = bp->pf;
4437         int rc;
4438
4439         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4440
4441         req.port_id = rte_cpu_to_le_16(pf->port_id);
4442         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4443         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4444         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4445
4446         HWRM_CHECK_RESULT();
4447         HWRM_UNLOCK();
4448
4449         return rc;
4450 }
4451
4452 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4453 {
4454         struct hwrm_port_clr_stats_input req = {0};
4455         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4456         struct bnxt_pf_info *pf = bp->pf;
4457         int rc;
4458
4459         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4460         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4461             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4462                 return 0;
4463
4464         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4465
4466         req.port_id = rte_cpu_to_le_16(pf->port_id);
4467         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4468
4469         HWRM_CHECK_RESULT();
4470         HWRM_UNLOCK();
4471
4472         return rc;
4473 }
4474
4475 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4476 {
4477         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4478         struct hwrm_port_led_qcaps_input req = {0};
4479         int rc;
4480
4481         if (BNXT_VF(bp))
4482                 return 0;
4483
4484         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4485         req.port_id = bp->pf->port_id;
4486         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4487
4488         HWRM_CHECK_RESULT_SILENT();
4489
4490         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4491                 unsigned int i;
4492
4493                 bp->leds->num_leds = resp->num_leds;
4494                 memcpy(bp->leds, &resp->led0_id,
4495                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4496                 for (i = 0; i < bp->leds->num_leds; i++) {
4497                         struct bnxt_led_info *led = &bp->leds[i];
4498
4499                         uint16_t caps = led->led_state_caps;
4500
4501                         if (!led->led_group_id ||
4502                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4503                                 bp->leds->num_leds = 0;
4504                                 break;
4505                         }
4506                 }
4507         }
4508
4509         HWRM_UNLOCK();
4510
4511         return rc;
4512 }
4513
4514 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4515 {
4516         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4517         struct hwrm_port_led_cfg_input req = {0};
4518         struct bnxt_led_cfg *led_cfg;
4519         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4520         uint16_t duration = 0;
4521         int rc, i;
4522
4523         if (!bp->leds->num_leds || BNXT_VF(bp))
4524                 return -EOPNOTSUPP;
4525
4526         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4527
4528         if (led_on) {
4529                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4530                 duration = rte_cpu_to_le_16(500);
4531         }
4532         req.port_id = bp->pf->port_id;
4533         req.num_leds = bp->leds->num_leds;
4534         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4535         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4536                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4537                 led_cfg->led_id = bp->leds[i].led_id;
4538                 led_cfg->led_state = led_state;
4539                 led_cfg->led_blink_on = duration;
4540                 led_cfg->led_blink_off = duration;
4541                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4542         }
4543
4544         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4545
4546         HWRM_CHECK_RESULT();
4547         HWRM_UNLOCK();
4548
4549         return rc;
4550 }
4551
4552 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4553                                uint32_t *length)
4554 {
4555         int rc;
4556         struct hwrm_nvm_get_dir_info_input req = {0};
4557         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4558
4559         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4560
4561         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4562
4563         HWRM_CHECK_RESULT();
4564
4565         *entries = rte_le_to_cpu_32(resp->entries);
4566         *length = rte_le_to_cpu_32(resp->entry_length);
4567
4568         HWRM_UNLOCK();
4569         return rc;
4570 }
4571
4572 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4573 {
4574         int rc;
4575         uint32_t dir_entries;
4576         uint32_t entry_length;
4577         uint8_t *buf;
4578         size_t buflen;
4579         rte_iova_t dma_handle;
4580         struct hwrm_nvm_get_dir_entries_input req = {0};
4581         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4582
4583         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4584         if (rc != 0)
4585                 return rc;
4586
4587         *data++ = dir_entries;
4588         *data++ = entry_length;
4589         len -= 2;
4590         memset(data, 0xff, len);
4591
4592         buflen = dir_entries * entry_length;
4593         buf = rte_malloc("nvm_dir", buflen, 0);
4594         if (buf == NULL)
4595                 return -ENOMEM;
4596         dma_handle = rte_malloc_virt2iova(buf);
4597         if (dma_handle == RTE_BAD_IOVA) {
4598                 rte_free(buf);
4599                 PMD_DRV_LOG(ERR,
4600                         "unable to map response address to physical memory\n");
4601                 return -ENOMEM;
4602         }
4603         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4604         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4605         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4606
4607         if (rc == 0)
4608                 memcpy(data, buf, len > buflen ? buflen : len);
4609
4610         rte_free(buf);
4611         HWRM_CHECK_RESULT();
4612         HWRM_UNLOCK();
4613
4614         return rc;
4615 }
4616
4617 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4618                              uint32_t offset, uint32_t length,
4619                              uint8_t *data)
4620 {
4621         int rc;
4622         uint8_t *buf;
4623         rte_iova_t dma_handle;
4624         struct hwrm_nvm_read_input req = {0};
4625         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4626
4627         buf = rte_malloc("nvm_item", length, 0);
4628         if (!buf)
4629                 return -ENOMEM;
4630
4631         dma_handle = rte_malloc_virt2iova(buf);
4632         if (dma_handle == RTE_BAD_IOVA) {
4633                 rte_free(buf);
4634                 PMD_DRV_LOG(ERR,
4635                         "unable to map response address to physical memory\n");
4636                 return -ENOMEM;
4637         }
4638         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4639         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4640         req.dir_idx = rte_cpu_to_le_16(index);
4641         req.offset = rte_cpu_to_le_32(offset);
4642         req.len = rte_cpu_to_le_32(length);
4643         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4644         if (rc == 0)
4645                 memcpy(data, buf, length);
4646
4647         rte_free(buf);
4648         HWRM_CHECK_RESULT();
4649         HWRM_UNLOCK();
4650
4651         return rc;
4652 }
4653
4654 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4655 {
4656         int rc;
4657         struct hwrm_nvm_erase_dir_entry_input req = {0};
4658         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4659
4660         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4661         req.dir_idx = rte_cpu_to_le_16(index);
4662         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4663         HWRM_CHECK_RESULT();
4664         HWRM_UNLOCK();
4665
4666         return rc;
4667 }
4668
4669 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4670                           uint16_t dir_ordinal, uint16_t dir_ext,
4671                           uint16_t dir_attr, const uint8_t *data,
4672                           size_t data_len)
4673 {
4674         int rc;
4675         struct hwrm_nvm_write_input req = {0};
4676         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4677         rte_iova_t dma_handle;
4678         uint8_t *buf;
4679
4680         buf = rte_malloc("nvm_write", data_len, 0);
4681         if (!buf)
4682                 return -ENOMEM;
4683
4684         dma_handle = rte_malloc_virt2iova(buf);
4685         if (dma_handle == RTE_BAD_IOVA) {
4686                 rte_free(buf);
4687                 PMD_DRV_LOG(ERR,
4688                         "unable to map response address to physical memory\n");
4689                 return -ENOMEM;
4690         }
4691         memcpy(buf, data, data_len);
4692
4693         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4694
4695         req.dir_type = rte_cpu_to_le_16(dir_type);
4696         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4697         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4698         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4699         req.dir_data_length = rte_cpu_to_le_32(data_len);
4700         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4701
4702         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4703
4704         rte_free(buf);
4705         HWRM_CHECK_RESULT();
4706         HWRM_UNLOCK();
4707
4708         return rc;
4709 }
4710
4711 static void
4712 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4713 {
4714         uint32_t *count = cbdata;
4715
4716         *count = *count + 1;
4717 }
4718
4719 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4720                                      struct bnxt_vnic_info *vnic __rte_unused)
4721 {
4722         return 0;
4723 }
4724
4725 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4726 {
4727         uint32_t count = 0;
4728
4729         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4730             &count, bnxt_vnic_count_hwrm_stub);
4731
4732         return count;
4733 }
4734
4735 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4736                                         uint16_t *vnic_ids)
4737 {
4738         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4739         struct hwrm_func_vf_vnic_ids_query_output *resp =
4740                                                 bp->hwrm_cmd_resp_addr;
4741         int rc;
4742
4743         /* First query all VNIC ids */
4744         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4745
4746         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4747         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4748         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4749
4750         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4751                 HWRM_UNLOCK();
4752                 PMD_DRV_LOG(ERR,
4753                 "unable to map VNIC ID table address to physical memory\n");
4754                 return -ENOMEM;
4755         }
4756         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4757         HWRM_CHECK_RESULT();
4758         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4759
4760         HWRM_UNLOCK();
4761
4762         return rc;
4763 }
4764
4765 /*
4766  * This function queries the VNIC IDs  for a specified VF. It then calls
4767  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4768  * Then it calls the hwrm_cb function to program this new vnic configuration.
4769  */
4770 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4771         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4772         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4773 {
4774         struct bnxt_vnic_info vnic;
4775         int rc = 0;
4776         int i, num_vnic_ids;
4777         uint16_t *vnic_ids;
4778         size_t vnic_id_sz;
4779         size_t sz;
4780
4781         /* First query all VNIC ids */
4782         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4783         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4784                         RTE_CACHE_LINE_SIZE);
4785         if (vnic_ids == NULL)
4786                 return -ENOMEM;
4787
4788         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4789                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4790
4791         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4792
4793         if (num_vnic_ids < 0)
4794                 return num_vnic_ids;
4795
4796         /* Retrieve VNIC, update bd_stall then update */
4797
4798         for (i = 0; i < num_vnic_ids; i++) {
4799                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4800                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4801                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4802                 if (rc)
4803                         break;
4804                 if (vnic.mru <= 4)      /* Indicates unallocated */
4805                         continue;
4806
4807                 vnic_cb(&vnic, cbdata);
4808
4809                 rc = hwrm_cb(bp, &vnic);
4810                 if (rc)
4811                         break;
4812         }
4813
4814         rte_free(vnic_ids);
4815
4816         return rc;
4817 }
4818
4819 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4820                                               bool on)
4821 {
4822         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4823         struct hwrm_func_cfg_input req = {0};
4824         int rc;
4825
4826         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4827
4828         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4829         req.enables |= rte_cpu_to_le_32(
4830                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4831         req.vlan_antispoof_mode = on ?
4832                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4833                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4834         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4835
4836         HWRM_CHECK_RESULT();
4837         HWRM_UNLOCK();
4838
4839         return rc;
4840 }
4841
4842 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4843 {
4844         struct bnxt_vnic_info vnic;
4845         uint16_t *vnic_ids;
4846         size_t vnic_id_sz;
4847         int num_vnic_ids, i;
4848         size_t sz;
4849         int rc;
4850
4851         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4852         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4853                         RTE_CACHE_LINE_SIZE);
4854         if (vnic_ids == NULL)
4855                 return -ENOMEM;
4856
4857         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4858                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4859
4860         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4861         if (rc <= 0)
4862                 goto exit;
4863         num_vnic_ids = rc;
4864
4865         /*
4866          * Loop through to find the default VNIC ID.
4867          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4868          * by sending the hwrm_func_qcfg command to the firmware.
4869          */
4870         for (i = 0; i < num_vnic_ids; i++) {
4871                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4872                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4873                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4874                                         bp->pf->first_vf_id + vf);
4875                 if (rc)
4876                         goto exit;
4877                 if (vnic.func_default) {
4878                         rte_free(vnic_ids);
4879                         return vnic.fw_vnic_id;
4880                 }
4881         }
4882         /* Could not find a default VNIC. */
4883         PMD_DRV_LOG(ERR, "No default VNIC\n");
4884 exit:
4885         rte_free(vnic_ids);
4886         return rc;
4887 }
4888
4889 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4890                          uint16_t dst_id,
4891                          struct bnxt_filter_info *filter)
4892 {
4893         int rc = 0;
4894         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4895         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4896         uint32_t enables = 0;
4897
4898         if (filter->fw_em_filter_id != UINT64_MAX)
4899                 bnxt_hwrm_clear_em_filter(bp, filter);
4900
4901         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4902
4903         req.flags = rte_cpu_to_le_32(filter->flags);
4904
4905         enables = filter->enables |
4906               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4907         req.dst_id = rte_cpu_to_le_16(dst_id);
4908
4909         if (filter->ip_addr_type) {
4910                 req.ip_addr_type = filter->ip_addr_type;
4911                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4912         }
4913         if (enables &
4914             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4915                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4916         if (enables &
4917             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4918                 memcpy(req.src_macaddr, filter->src_macaddr,
4919                        RTE_ETHER_ADDR_LEN);
4920         if (enables &
4921             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4922                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4923                        RTE_ETHER_ADDR_LEN);
4924         if (enables &
4925             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4926                 req.ovlan_vid = filter->l2_ovlan;
4927         if (enables &
4928             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4929                 req.ivlan_vid = filter->l2_ivlan;
4930         if (enables &
4931             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4932                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4933         if (enables &
4934             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4935                 req.ip_protocol = filter->ip_protocol;
4936         if (enables &
4937             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4938                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4939         if (enables &
4940             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4941                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4942         if (enables &
4943             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4944                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4945         if (enables &
4946             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4947                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4948         if (enables &
4949             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4950                 req.mirror_vnic_id = filter->mirror_vnic_id;
4951
4952         req.enables = rte_cpu_to_le_32(enables);
4953
4954         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4955
4956         HWRM_CHECK_RESULT();
4957
4958         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4959         HWRM_UNLOCK();
4960
4961         return rc;
4962 }
4963
4964 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4965 {
4966         int rc = 0;
4967         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4968         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4969
4970         if (filter->fw_em_filter_id == UINT64_MAX)
4971                 return 0;
4972
4973         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4974
4975         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4976
4977         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4978
4979         HWRM_CHECK_RESULT();
4980         HWRM_UNLOCK();
4981
4982         filter->fw_em_filter_id = UINT64_MAX;
4983         filter->fw_l2_filter_id = UINT64_MAX;
4984
4985         return 0;
4986 }
4987
4988 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4989                          uint16_t dst_id,
4990                          struct bnxt_filter_info *filter)
4991 {
4992         int rc = 0;
4993         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4994         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4995                                                 bp->hwrm_cmd_resp_addr;
4996         uint32_t enables = 0;
4997
4998         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4999                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
5000
5001         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
5002
5003         req.flags = rte_cpu_to_le_32(filter->flags);
5004
5005         enables = filter->enables |
5006               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
5007         req.dst_id = rte_cpu_to_le_16(dst_id);
5008
5009         if (filter->ip_addr_type) {
5010                 req.ip_addr_type = filter->ip_addr_type;
5011                 enables |=
5012                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
5013         }
5014         if (enables &
5015             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5016                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5017         if (enables &
5018             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5019                 memcpy(req.src_macaddr, filter->src_macaddr,
5020                        RTE_ETHER_ADDR_LEN);
5021         if (enables &
5022             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5023                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5024         if (enables &
5025             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5026                 req.ip_protocol = filter->ip_protocol;
5027         if (enables &
5028             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5029                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5030         if (enables &
5031             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5032                 req.src_ipaddr_mask[0] =
5033                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5034         if (enables &
5035             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5036                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5037         if (enables &
5038             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5039                 req.dst_ipaddr_mask[0] =
5040                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5041         if (enables &
5042             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5043                 req.src_port = rte_cpu_to_le_16(filter->src_port);
5044         if (enables &
5045             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5046                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5047         if (enables &
5048             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5049                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5050         if (enables &
5051             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5052                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5053         if (enables &
5054             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5055                 req.mirror_vnic_id = filter->mirror_vnic_id;
5056
5057         req.enables = rte_cpu_to_le_32(enables);
5058
5059         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5060
5061         HWRM_CHECK_RESULT();
5062
5063         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5064         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5065         HWRM_UNLOCK();
5066
5067         return rc;
5068 }
5069
5070 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5071                                 struct bnxt_filter_info *filter)
5072 {
5073         int rc = 0;
5074         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5075         struct hwrm_cfa_ntuple_filter_free_output *resp =
5076                                                 bp->hwrm_cmd_resp_addr;
5077
5078         if (filter->fw_ntuple_filter_id == UINT64_MAX)
5079                 return 0;
5080
5081         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5082
5083         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5084
5085         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5086
5087         HWRM_CHECK_RESULT();
5088         HWRM_UNLOCK();
5089
5090         filter->fw_ntuple_filter_id = UINT64_MAX;
5091
5092         return 0;
5093 }
5094
5095 static int
5096 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5097 {
5098         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5099         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
5100         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5101         struct bnxt_rx_queue **rxqs = bp->rx_queues;
5102         uint16_t *ring_tbl = vnic->rss_table;
5103         int nr_ctxs = vnic->num_lb_ctxts;
5104         int max_rings = bp->rx_nr_rings;
5105         int i, j, k, cnt;
5106         int rc = 0;
5107
5108         for (i = 0, k = 0; i < nr_ctxs; i++) {
5109                 struct bnxt_rx_ring_info *rxr;
5110                 struct bnxt_cp_ring_info *cpr;
5111
5112                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5113
5114                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5115                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5116                 req.hash_mode_flags = vnic->hash_mode;
5117
5118                 req.ring_grp_tbl_addr =
5119                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5120                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5121                                      2 * sizeof(*ring_tbl));
5122                 req.hash_key_tbl_addr =
5123                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5124
5125                 req.ring_table_pair_index = i;
5126                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5127
5128                 for (j = 0; j < 64; j++) {
5129                         uint16_t ring_id;
5130
5131                         /* Find next active ring. */
5132                         for (cnt = 0; cnt < max_rings; cnt++) {
5133                                 if (rx_queue_state[k] !=
5134                                                 RTE_ETH_QUEUE_STATE_STOPPED)
5135                                         break;
5136                                 if (++k == max_rings)
5137                                         k = 0;
5138                         }
5139
5140                         /* Return if no rings are active. */
5141                         if (cnt == max_rings) {
5142                                 HWRM_UNLOCK();
5143                                 return 0;
5144                         }
5145
5146                         /* Add rx/cp ring pair to RSS table. */
5147                         rxr = rxqs[k]->rx_ring;
5148                         cpr = rxqs[k]->cp_ring;
5149
5150                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5151                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5152                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5153                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5154
5155                         if (++k == max_rings)
5156                                 k = 0;
5157                 }
5158                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5159                                             BNXT_USE_CHIMP_MB);
5160
5161                 HWRM_CHECK_RESULT();
5162                 HWRM_UNLOCK();
5163         }
5164
5165         return rc;
5166 }
5167
5168 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5169 {
5170         unsigned int rss_idx, fw_idx, i;
5171
5172         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5173                 return 0;
5174
5175         if (!(vnic->rss_table && vnic->hash_type))
5176                 return 0;
5177
5178         if (BNXT_CHIP_P5(bp))
5179                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5180
5181         /*
5182          * Fill the RSS hash & redirection table with
5183          * ring group ids for all VNICs
5184          */
5185         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5186              rss_idx++, fw_idx++) {
5187                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5188                         fw_idx %= bp->rx_cp_nr_rings;
5189                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5190                                 break;
5191                         fw_idx++;
5192                 }
5193
5194                 if (i == bp->rx_cp_nr_rings)
5195                         return 0;
5196
5197                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5198         }
5199
5200         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5201 }
5202
5203 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5204         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5205 {
5206         uint16_t flags;
5207
5208         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5209
5210         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5211         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5212
5213         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5214         req->num_cmpl_dma_aggr_during_int =
5215                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5216
5217         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5218
5219         /* min timer set to 1/2 of interrupt timer */
5220         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5221
5222         /* buf timer set to 1/4 of interrupt timer */
5223         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5224
5225         req->cmpl_aggr_dma_tmr_during_int =
5226                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5227
5228         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5229                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5230         req->flags = rte_cpu_to_le_16(flags);
5231 }
5232
5233 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5234                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5235 {
5236         struct hwrm_ring_aggint_qcaps_input req = {0};
5237         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5238         uint32_t enables;
5239         uint16_t flags;
5240         int rc;
5241
5242         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5243         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5244         HWRM_CHECK_RESULT();
5245
5246         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5247         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5248
5249         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5250                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5251         agg_req->flags = rte_cpu_to_le_16(flags);
5252         enables =
5253          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5254          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5255         agg_req->enables = rte_cpu_to_le_32(enables);
5256
5257         HWRM_UNLOCK();
5258         return rc;
5259 }
5260
5261 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5262                         struct bnxt_coal *coal, uint16_t ring_id)
5263 {
5264         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5265         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5266                                                 bp->hwrm_cmd_resp_addr;
5267         int rc;
5268
5269         /* Set ring coalesce parameters only for 100G NICs */
5270         if (BNXT_CHIP_P5(bp)) {
5271                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5272                         return -1;
5273         } else if (bnxt_stratus_device(bp)) {
5274                 bnxt_hwrm_set_coal_params(coal, &req);
5275         } else {
5276                 return 0;
5277         }
5278
5279         HWRM_PREP(&req,
5280                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5281                   BNXT_USE_CHIMP_MB);
5282         req.ring_id = rte_cpu_to_le_16(ring_id);
5283         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5284         HWRM_CHECK_RESULT();
5285         HWRM_UNLOCK();
5286         return 0;
5287 }
5288
5289 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5290 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5291 {
5292         struct hwrm_func_backing_store_qcaps_input req = {0};
5293         struct hwrm_func_backing_store_qcaps_output *resp =
5294                 bp->hwrm_cmd_resp_addr;
5295         struct bnxt_ctx_pg_info *ctx_pg;
5296         struct bnxt_ctx_mem_info *ctx;
5297         int total_alloc_len;
5298         int rc, i, tqm_rings;
5299
5300         if (!BNXT_CHIP_P5(bp) ||
5301             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5302             BNXT_VF(bp) ||
5303             bp->ctx)
5304                 return 0;
5305
5306         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5307         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5308         HWRM_CHECK_RESULT_SILENT();
5309
5310         total_alloc_len = sizeof(*ctx);
5311         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5312                           RTE_CACHE_LINE_SIZE);
5313         if (!ctx) {
5314                 rc = -ENOMEM;
5315                 goto ctx_err;
5316         }
5317
5318         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5319         ctx->qp_min_qp1_entries =
5320                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5321         ctx->qp_max_l2_entries =
5322                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5323         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5324         ctx->srq_max_l2_entries =
5325                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5326         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5327         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5328         ctx->cq_max_l2_entries =
5329                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5330         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5331         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5332         ctx->vnic_max_vnic_entries =
5333                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5334         ctx->vnic_max_ring_table_entries =
5335                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5336         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5337         ctx->stat_max_entries =
5338                 rte_le_to_cpu_32(resp->stat_max_entries);
5339         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5340         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5341         ctx->tqm_min_entries_per_ring =
5342                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5343         ctx->tqm_max_entries_per_ring =
5344                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5345         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5346         if (!ctx->tqm_entries_multiple)
5347                 ctx->tqm_entries_multiple = 1;
5348         ctx->mrav_max_entries =
5349                 rte_le_to_cpu_32(resp->mrav_max_entries);
5350         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5351         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5352         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5353         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5354
5355         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5356                                   RTE_MIN(ctx->tqm_fp_rings_count,
5357                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5358                                   bp->max_q;
5359
5360         /* Check if the ext ring count needs to be counted.
5361          * Ext ring count is available only with new FW so we should not
5362          * look at the field on older FW.
5363          */
5364         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5365             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5366                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5367                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5368                                                   ctx->tqm_fp_rings_count);
5369         }
5370
5371         tqm_rings = ctx->tqm_fp_rings_count + 1;
5372
5373         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5374                             sizeof(*ctx_pg) * tqm_rings,
5375                             RTE_CACHE_LINE_SIZE);
5376         if (!ctx_pg) {
5377                 rc = -ENOMEM;
5378                 goto ctx_err;
5379         }
5380         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5381                 ctx->tqm_mem[i] = ctx_pg;
5382
5383         bp->ctx = ctx;
5384 ctx_err:
5385         HWRM_UNLOCK();
5386         return rc;
5387 }
5388
5389 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5390 {
5391         struct hwrm_func_backing_store_cfg_input req = {0};
5392         struct hwrm_func_backing_store_cfg_output *resp =
5393                 bp->hwrm_cmd_resp_addr;
5394         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5395         struct bnxt_ctx_pg_info *ctx_pg;
5396         uint32_t *num_entries;
5397         uint64_t *pg_dir;
5398         uint8_t *pg_attr;
5399         uint32_t ena;
5400         int i, rc;
5401
5402         if (!ctx)
5403                 return 0;
5404
5405         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5406         req.enables = rte_cpu_to_le_32(enables);
5407
5408         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5409                 ctx_pg = &ctx->qp_mem;
5410                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5411                 req.qp_num_qp1_entries =
5412                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5413                 req.qp_num_l2_entries =
5414                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5415                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5416                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5417                                       &req.qpc_pg_size_qpc_lvl,
5418                                       &req.qpc_page_dir);
5419         }
5420
5421         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5422                 ctx_pg = &ctx->srq_mem;
5423                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5424                 req.srq_num_l2_entries =
5425                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5426                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5427                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5428                                       &req.srq_pg_size_srq_lvl,
5429                                       &req.srq_page_dir);
5430         }
5431
5432         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5433                 ctx_pg = &ctx->cq_mem;
5434                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5435                 req.cq_num_l2_entries =
5436                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5437                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5438                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5439                                       &req.cq_pg_size_cq_lvl,
5440                                       &req.cq_page_dir);
5441         }
5442
5443         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5444                 ctx_pg = &ctx->vnic_mem;
5445                 req.vnic_num_vnic_entries =
5446                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5447                 req.vnic_num_ring_table_entries =
5448                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5449                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5450                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5451                                       &req.vnic_pg_size_vnic_lvl,
5452                                       &req.vnic_page_dir);
5453         }
5454
5455         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5456                 ctx_pg = &ctx->stat_mem;
5457                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5458                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5459                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5460                                       &req.stat_pg_size_stat_lvl,
5461                                       &req.stat_page_dir);
5462         }
5463
5464         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5465         num_entries = &req.tqm_sp_num_entries;
5466         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5467         pg_dir = &req.tqm_sp_page_dir;
5468         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5469         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5470                 if (!(enables & ena))
5471                         continue;
5472
5473                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5474
5475                 ctx_pg = ctx->tqm_mem[i];
5476                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5477                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5478         }
5479
5480         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5481                 /* DPDK does not need to configure MRAV and TIM type.
5482                  * So we are skipping over MRAV and TIM. Skip to configure
5483                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5484                  */
5485                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5486                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5487                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5488                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5489                                       &req.tqm_ring8_page_dir);
5490         }
5491
5492         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5493         HWRM_CHECK_RESULT();
5494         HWRM_UNLOCK();
5495
5496         return rc;
5497 }
5498
5499 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5500 {
5501         struct hwrm_port_qstats_ext_input req = {0};
5502         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5503         struct bnxt_pf_info *pf = bp->pf;
5504         int rc;
5505
5506         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5507               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5508                 return 0;
5509
5510         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5511
5512         req.port_id = rte_cpu_to_le_16(pf->port_id);
5513         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5514                 req.tx_stat_host_addr =
5515                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5516                 req.tx_stat_size =
5517                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5518         }
5519         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5520                 req.rx_stat_host_addr =
5521                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5522                 req.rx_stat_size =
5523                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5524         }
5525         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5526
5527         if (rc) {
5528                 bp->fw_rx_port_stats_ext_size = 0;
5529                 bp->fw_tx_port_stats_ext_size = 0;
5530         } else {
5531                 bp->fw_rx_port_stats_ext_size =
5532                         rte_le_to_cpu_16(resp->rx_stat_size);
5533                 bp->fw_tx_port_stats_ext_size =
5534                         rte_le_to_cpu_16(resp->tx_stat_size);
5535         }
5536
5537         HWRM_CHECK_RESULT();
5538         HWRM_UNLOCK();
5539
5540         return rc;
5541 }
5542
5543 int
5544 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5545 {
5546         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5547         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5548                 bp->hwrm_cmd_resp_addr;
5549         int rc = 0;
5550
5551         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5552         req.tunnel_type = type;
5553         req.dest_fid = bp->fw_fid;
5554         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5555         HWRM_CHECK_RESULT();
5556
5557         HWRM_UNLOCK();
5558
5559         return rc;
5560 }
5561
5562 int
5563 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5564 {
5565         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5566         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5567                 bp->hwrm_cmd_resp_addr;
5568         int rc = 0;
5569
5570         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5571         req.tunnel_type = type;
5572         req.dest_fid = bp->fw_fid;
5573         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5574         HWRM_CHECK_RESULT();
5575
5576         HWRM_UNLOCK();
5577
5578         return rc;
5579 }
5580
5581 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5582 {
5583         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5584         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5585                 bp->hwrm_cmd_resp_addr;
5586         int rc = 0;
5587
5588         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5589         req.src_fid = bp->fw_fid;
5590         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5591         HWRM_CHECK_RESULT();
5592
5593         if (type)
5594                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5595
5596         HWRM_UNLOCK();
5597
5598         return rc;
5599 }
5600
5601 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5602                                    uint16_t *dst_fid)
5603 {
5604         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5605         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5606                 bp->hwrm_cmd_resp_addr;
5607         int rc = 0;
5608
5609         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5610         req.src_fid = bp->fw_fid;
5611         req.tunnel_type = tun_type;
5612         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5613         HWRM_CHECK_RESULT();
5614
5615         if (dst_fid)
5616                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5617
5618         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5619
5620         HWRM_UNLOCK();
5621
5622         return rc;
5623 }
5624
5625 int bnxt_hwrm_set_mac(struct bnxt *bp)
5626 {
5627         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5628         struct hwrm_func_vf_cfg_input req = {0};
5629         int rc = 0;
5630
5631         if (!BNXT_VF(bp))
5632                 return 0;
5633
5634         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5635
5636         req.enables =
5637                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5638         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5639
5640         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5641
5642         HWRM_CHECK_RESULT();
5643
5644         HWRM_UNLOCK();
5645
5646         return rc;
5647 }
5648
5649 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5650 {
5651         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5652         struct hwrm_func_drv_if_change_input req = {0};
5653         uint32_t flags;
5654         int rc;
5655
5656         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5657                 return 0;
5658
5659         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5660          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5661          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5662          */
5663         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5664                 return 0;
5665
5666         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5667
5668         if (up)
5669                 req.flags =
5670                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5671
5672         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5673
5674         HWRM_CHECK_RESULT();
5675         flags = rte_le_to_cpu_32(resp->flags);
5676         HWRM_UNLOCK();
5677
5678         if (!up)
5679                 return 0;
5680
5681         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5682                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5683                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5684         }
5685
5686         return 0;
5687 }
5688
5689 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5690 {
5691         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5692         struct bnxt_error_recovery_info *info = bp->recovery_info;
5693         struct hwrm_error_recovery_qcfg_input req = {0};
5694         uint32_t flags = 0;
5695         unsigned int i;
5696         int rc;
5697
5698         /* Older FW does not have error recovery support */
5699         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5700                 return 0;
5701
5702         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5703
5704         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5705
5706         HWRM_CHECK_RESULT();
5707
5708         flags = rte_le_to_cpu_32(resp->flags);
5709         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5710                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5711         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5712                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5713
5714         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5715             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5716                 rc = -EINVAL;
5717                 goto err;
5718         }
5719
5720         /* FW returned values are in units of 100msec */
5721         info->driver_polling_freq =
5722                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5723         info->master_func_wait_period =
5724                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5725         info->normal_func_wait_period =
5726                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5727         info->master_func_wait_period_after_reset =
5728                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5729         info->max_bailout_time_after_reset =
5730                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5731         info->status_regs[BNXT_FW_STATUS_REG] =
5732                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5733         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5734                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5735         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5736                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5737         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5738                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5739         info->reg_array_cnt =
5740                 rte_le_to_cpu_32(resp->reg_array_cnt);
5741
5742         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5743                 rc = -EINVAL;
5744                 goto err;
5745         }
5746
5747         for (i = 0; i < info->reg_array_cnt; i++) {
5748                 info->reset_reg[i] =
5749                         rte_le_to_cpu_32(resp->reset_reg[i]);
5750                 info->reset_reg_val[i] =
5751                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5752                 info->delay_after_reset[i] =
5753                         resp->delay_after_reset[i];
5754         }
5755 err:
5756         HWRM_UNLOCK();
5757
5758         /* Map the FW status registers */
5759         if (!rc)
5760                 rc = bnxt_map_fw_health_status_regs(bp);
5761
5762         if (rc) {
5763                 rte_free(bp->recovery_info);
5764                 bp->recovery_info = NULL;
5765         }
5766         return rc;
5767 }
5768
5769 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5770 {
5771         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5772         struct hwrm_fw_reset_input req = {0};
5773         int rc;
5774
5775         if (!BNXT_PF(bp))
5776                 return -EOPNOTSUPP;
5777
5778         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5779
5780         req.embedded_proc_type =
5781                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5782         req.selfrst_status =
5783                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5784         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5785
5786         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5787                                     BNXT_USE_KONG(bp));
5788
5789         HWRM_CHECK_RESULT();
5790         HWRM_UNLOCK();
5791
5792         return rc;
5793 }
5794
5795 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5796 {
5797         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5798         struct hwrm_port_ts_query_input req = {0};
5799         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5800         uint32_t flags = 0;
5801         int rc;
5802
5803         if (!ptp)
5804                 return 0;
5805
5806         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5807
5808         switch (path) {
5809         case BNXT_PTP_FLAGS_PATH_TX:
5810                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5811                 break;
5812         case BNXT_PTP_FLAGS_PATH_RX:
5813                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5814                 break;
5815         case BNXT_PTP_FLAGS_CURRENT_TIME:
5816                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5817                 break;
5818         }
5819
5820         req.flags = rte_cpu_to_le_32(flags);
5821         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5822
5823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5824
5825         HWRM_CHECK_RESULT();
5826
5827         if (timestamp) {
5828                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5829                 *timestamp |=
5830                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5831         }
5832         HWRM_UNLOCK();
5833
5834         return rc;
5835 }
5836
5837 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5838 {
5839         int rc = 0;
5840
5841         struct hwrm_cfa_counter_qcaps_input req = {0};
5842         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5843
5844         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5845                 PMD_DRV_LOG(DEBUG,
5846                             "Not a PF or trusted VF. Command not supported\n");
5847                 return 0;
5848         }
5849
5850         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5851         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5852         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5853
5854         HWRM_CHECK_RESULT();
5855         if (max_fc)
5856                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5857         HWRM_UNLOCK();
5858
5859         return 0;
5860 }
5861
5862 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5863 {
5864         int rc = 0;
5865         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5866         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5867
5868         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5869                 PMD_DRV_LOG(DEBUG,
5870                             "Not a PF or trusted VF. Command not supported\n");
5871                 return 0;
5872         }
5873
5874         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5875
5876         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5877         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5878         req.page_dir = rte_cpu_to_le_64(dma_addr);
5879
5880         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5881
5882         HWRM_CHECK_RESULT();
5883         if (ctx_id) {
5884                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5885                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5886         }
5887         HWRM_UNLOCK();
5888
5889         return 0;
5890 }
5891
5892 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5893 {
5894         int rc = 0;
5895         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5896         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5897
5898         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5899                 PMD_DRV_LOG(DEBUG,
5900                             "Not a PF or trusted VF. Command not supported\n");
5901                 return 0;
5902         }
5903
5904         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5905
5906         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5907
5908         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5909
5910         HWRM_CHECK_RESULT();
5911         HWRM_UNLOCK();
5912
5913         return rc;
5914 }
5915
5916 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5917                               uint16_t cntr, uint16_t ctx_id,
5918                               uint32_t num_entries, bool enable)
5919 {
5920         struct hwrm_cfa_counter_cfg_input req = {0};
5921         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5922         uint16_t flags = 0;
5923         int rc;
5924
5925         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5926                 PMD_DRV_LOG(DEBUG,
5927                             "Not a PF or trusted VF. Command not supported\n");
5928                 return 0;
5929         }
5930
5931         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5932
5933         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5934         req.counter_type = rte_cpu_to_le_16(cntr);
5935         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5936                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5937         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5938         if (dir == BNXT_DIR_RX)
5939                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5940         else if (dir == BNXT_DIR_TX)
5941                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5942         req.flags = rte_cpu_to_le_16(flags);
5943         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5944         req.num_entries = rte_cpu_to_le_32(num_entries);
5945
5946         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5947         HWRM_CHECK_RESULT();
5948         HWRM_UNLOCK();
5949
5950         return 0;
5951 }
5952
5953 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5954                                  enum bnxt_flow_dir dir,
5955                                  uint16_t cntr,
5956                                  uint16_t num_entries)
5957 {
5958         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5959         struct hwrm_cfa_counter_qstats_input req = {0};
5960         uint16_t flow_ctx_id = 0;
5961         uint16_t flags = 0;
5962         int rc = 0;
5963
5964         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5965                 PMD_DRV_LOG(DEBUG,
5966                             "Not a PF or trusted VF. Command not supported\n");
5967                 return 0;
5968         }
5969
5970         if (dir == BNXT_DIR_RX) {
5971                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5972                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5973         } else if (dir == BNXT_DIR_TX) {
5974                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5975                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5976         }
5977
5978         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5979         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5980         req.counter_type = rte_cpu_to_le_16(cntr);
5981         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5982         req.num_entries = rte_cpu_to_le_16(num_entries);
5983         req.flags = rte_cpu_to_le_16(flags);
5984         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5985
5986         HWRM_CHECK_RESULT();
5987         HWRM_UNLOCK();
5988
5989         return 0;
5990 }
5991
5992 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5993                                 uint16_t *first_vf_id)
5994 {
5995         int rc = 0;
5996         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5997         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5998
5999         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
6000
6001         req.fid = rte_cpu_to_le_16(fid);
6002
6003         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6004
6005         HWRM_CHECK_RESULT();
6006
6007         if (first_vf_id)
6008                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
6009
6010         HWRM_UNLOCK();
6011
6012         return rc;
6013 }
6014
6015 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6016 {
6017         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6018         struct hwrm_cfa_pair_alloc_input req = {0};
6019         int rc;
6020
6021         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6022                 PMD_DRV_LOG(DEBUG,
6023                             "Not a PF or trusted VF. Command not supported\n");
6024                 return 0;
6025         }
6026
6027         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6028         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6029         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6030                  bp->eth_dev->data->name, rep_bp->vf_id);
6031
6032         req.pf_b_id = rep_bp->parent_pf_idx;
6033         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6034                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6035         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6036         req.host_b_id = 1; /* TBD - Confirm if this is OK */
6037
6038         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6039                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6040         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6041                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6042         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6043                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6044         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6045                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6046
6047         req.q_ab = rep_bp->rep_q_r2f;
6048         req.q_ba = rep_bp->rep_q_f2r;
6049         req.fc_ab = rep_bp->rep_fc_r2f;
6050         req.fc_ba = rep_bp->rep_fc_f2r;
6051
6052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6053         HWRM_CHECK_RESULT();
6054
6055         HWRM_UNLOCK();
6056         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6057                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6058         return rc;
6059 }
6060
6061 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6062 {
6063         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6064         struct hwrm_cfa_pair_free_input req = {0};
6065         int rc;
6066
6067         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6068                 PMD_DRV_LOG(DEBUG,
6069                             "Not a PF or trusted VF. Command not supported\n");
6070                 return 0;
6071         }
6072
6073         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6074         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6075                  bp->eth_dev->data->name, rep_bp->vf_id);
6076         req.pf_b_id = rep_bp->parent_pf_idx;
6077         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6078         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6079                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6080         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6081         HWRM_CHECK_RESULT();
6082         HWRM_UNLOCK();
6083         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6084                     rep_bp->vf_id);
6085         return rc;
6086 }
6087
6088 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6089 {
6090         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6091                                         bp->hwrm_cmd_resp_addr;
6092         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6093         uint32_t flags = 0;
6094         int rc = 0;
6095
6096         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6097                 return 0;
6098
6099         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6100                 PMD_DRV_LOG(DEBUG,
6101                             "Not a PF or trusted VF. Command not supported\n");
6102                 return 0;
6103         }
6104
6105         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6106         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6107
6108         HWRM_CHECK_RESULT();
6109         flags = rte_le_to_cpu_32(resp->flags);
6110         HWRM_UNLOCK();
6111
6112         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6113                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6114         else
6115                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6116
6117         return rc;
6118 }
6119
6120 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6121                             uint32_t echo_req_data2)
6122 {
6123         struct hwrm_func_echo_response_input req = {0};
6124         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6125         int rc;
6126
6127         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6128         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6129         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6130
6131         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6132
6133         HWRM_CHECK_RESULT();
6134         HWRM_UNLOCK();
6135
6136         return rc;
6137 }
6138
6139 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6140 {
6141         struct hwrm_ver_get_input req = {.req_type = 0 };
6142         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6143         int rc = 0;
6144
6145         bp->max_req_len = HWRM_MAX_REQ_LEN;
6146         bp->max_resp_len = BNXT_PAGE_SIZE;
6147         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6148
6149         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6150         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6151         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6152         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6153
6154         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6155
6156         HWRM_CHECK_RESULT_SILENT();
6157
6158         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6159                 rc = -EAGAIN;
6160
6161         HWRM_UNLOCK();
6162
6163         return rc;
6164 }