1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SHORT_CMD_TIMEOUT 50000
31 #define HWRM_SPEC_CODE_1_8_3 0x10803
32 #define HWRM_VERSION_1_9_1 0x10901
33 #define HWRM_VERSION_1_9_2 0x10903
35 struct bnxt_plcmodes_cfg {
37 uint16_t jumbo_thresh;
39 uint16_t hds_threshold;
42 static int page_getenum(size_t size)
58 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
59 return sizeof(void *) * 8 - 1;
62 static int page_roundup(size_t size)
64 return 1 << page_getenum(size);
67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
71 if (rmem->nr_pages > 1) {
73 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
75 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
80 * HWRM Functions (sent to HWRM)
81 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
82 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
83 * command was failed by the ChiMP.
86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
87 uint32_t msg_len, bool use_kong_mb)
90 struct input *req = msg;
91 struct output *resp = bp->hwrm_cmd_resp_addr;
95 uint16_t max_req_len = bp->max_req_len;
96 struct hwrm_short_input short_input = { 0 };
97 uint16_t bar_offset = use_kong_mb ?
98 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
99 uint16_t mb_trigger_offset = use_kong_mb ?
100 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
103 /* Do not send HWRM commands to firmware in error state */
104 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
107 /* For VER_GET command, set timeout as 50ms */
108 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
109 timeout = HWRM_SHORT_CMD_TIMEOUT;
111 timeout = HWRM_CMD_TIMEOUT;
113 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
114 msg_len > bp->max_req_len) {
115 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
117 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
118 memcpy(short_cmd_req, req, msg_len);
120 short_input.req_type = rte_cpu_to_le_16(req->req_type);
121 short_input.signature = rte_cpu_to_le_16(
122 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
123 short_input.size = rte_cpu_to_le_16(msg_len);
124 short_input.req_addr =
125 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
127 data = (uint32_t *)&short_input;
128 msg_len = sizeof(short_input);
130 /* Sync memory write before updating doorbell */
133 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
136 /* Write request msg to hwrm channel */
137 for (i = 0; i < msg_len; i += 4) {
138 bar = (uint8_t *)bp->bar0 + bar_offset + i;
139 rte_write32(*data, bar);
143 /* Zero the rest of the request space */
144 for (; i < max_req_len; i += 4) {
145 bar = (uint8_t *)bp->bar0 + bar_offset + i;
149 /* Ring channel doorbell */
150 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
153 /* Poll for the valid bit */
154 for (i = 0; i < timeout; i++) {
155 /* Sanity check on the resp->resp_len */
157 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
158 /* Last byte of resp contains the valid key */
159 valid = (uint8_t *)resp + resp->resp_len - 1;
160 if (*valid == HWRM_RESP_VALID_KEY)
167 /* Suppress VER_GET timeout messages during reset recovery */
168 if (bp->flags & BNXT_FLAG_FW_RESET &&
169 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
172 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
180 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
181 * spinlock, and does initial processing.
183 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
184 * releases the spinlock only if it returns. If the regular int return codes
185 * are not used by the function, HWRM_CHECK_RESULT() should not be used
186 * directly, rather it should be copied and modified to suit the function.
188 * HWRM_UNLOCK() must be called after all response processing is completed.
190 #define HWRM_PREP(req, type, kong) do { \
191 rte_spinlock_lock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
194 req.cmpl_ring = rte_cpu_to_le_16(-1); \
195 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
197 req.target_id = rte_cpu_to_le_16(0xffff); \
198 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
223 if (resp->error_code) { \
224 rc = rte_le_to_cpu_16(resp->error_code); \
225 if (resp->resp_len >= 16) { \
226 struct hwrm_err_output *tmp_hwrm_err_op = \
229 "error %d:%d:%08x:%04x\n", \
230 rc, tmp_hwrm_err_op->cmd_err, \
232 tmp_hwrm_err_op->opaque_0), \
234 tmp_hwrm_err_op->opaque_1)); \
236 PMD_DRV_LOG(ERR, "error %d\n", rc); \
238 rte_spinlock_unlock(&bp->hwrm_lock); \
239 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
247 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
249 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
252 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
253 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
255 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
256 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
259 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
267 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
268 struct bnxt_vnic_info *vnic,
270 struct bnxt_vlan_table_entry *vlan_table)
273 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
274 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
277 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
280 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
281 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
283 /* FIXME add multicast flag, when multicast adding options is supported
286 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
287 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
288 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
290 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
291 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
292 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
293 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
294 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
295 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
296 if (vnic->mc_addr_cnt) {
297 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
298 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
299 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
302 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
303 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
304 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
305 rte_mem_virt2iova(vlan_table));
306 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
308 req.mask = rte_cpu_to_le_32(mask);
310 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
318 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
320 struct bnxt_vlan_antispoof_table_entry *vlan_table)
323 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
324 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
325 bp->hwrm_cmd_resp_addr;
328 * Older HWRM versions did not support this command, and the set_rx_mask
329 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
330 * removed from set_rx_mask call, and this command was added.
332 * This command is also present from 1.7.8.11 and higher,
335 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
336 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
337 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
342 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
343 req.fid = rte_cpu_to_le_16(fid);
345 req.vlan_tag_mask_tbl_addr =
346 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
347 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
349 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
357 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
358 struct bnxt_filter_info *filter)
361 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
362 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
364 if (filter->fw_l2_filter_id == UINT64_MAX)
367 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
369 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
371 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
376 filter->fw_l2_filter_id = UINT64_MAX;
381 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
383 struct bnxt_filter_info *filter)
386 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
387 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
388 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
389 const struct rte_eth_vmdq_rx_conf *conf =
390 &dev_conf->rx_adv_conf.vmdq_rx_conf;
391 uint32_t enables = 0;
392 uint16_t j = dst_id - 1;
394 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
395 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
396 conf->pool_map[j].pools & (1UL << j)) {
398 "Add vlan %u to vmdq pool %u\n",
399 conf->pool_map[j].vlan_id, j);
401 filter->l2_ivlan = conf->pool_map[j].vlan_id;
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
404 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
407 if (filter->fw_l2_filter_id != UINT64_MAX)
408 bnxt_hwrm_clear_l2_filter(bp, filter);
410 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
412 req.flags = rte_cpu_to_le_32(filter->flags);
414 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
416 enables = filter->enables |
417 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
418 req.dst_id = rte_cpu_to_le_16(dst_id);
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
422 memcpy(req.l2_addr, filter->l2_addr,
425 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
426 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
429 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
430 req.l2_ovlan = filter->l2_ovlan;
432 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
433 req.l2_ivlan = filter->l2_ivlan;
435 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
436 req.l2_ovlan_mask = filter->l2_ovlan_mask;
438 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
439 req.l2_ivlan_mask = filter->l2_ivlan_mask;
440 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
441 req.src_id = rte_cpu_to_le_32(filter->src_id);
442 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
443 req.src_type = filter->src_type;
445 req.enables = rte_cpu_to_le_32(enables);
447 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
451 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
457 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
459 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
460 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
467 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
470 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
473 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
474 if (ptp->tx_tstamp_en)
475 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
478 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
479 req.flags = rte_cpu_to_le_32(flags);
480 req.enables = rte_cpu_to_le_32
481 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
482 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
490 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
493 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
494 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
495 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
497 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
501 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
503 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
509 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
512 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
516 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
517 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
518 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
519 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
520 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
521 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
522 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
523 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
524 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
525 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
526 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
527 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
528 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
529 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
530 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
531 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
532 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
533 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
541 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
544 struct hwrm_func_qcaps_input req = {.req_type = 0 };
545 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
546 uint16_t new_max_vfs;
550 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
552 req.fid = rte_cpu_to_le_16(0xffff);
554 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
558 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
559 flags = rte_le_to_cpu_32(resp->flags);
561 bp->pf.port_id = resp->port_id;
562 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
563 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
564 new_max_vfs = bp->pdev->max_vfs;
565 if (new_max_vfs != bp->pf.max_vfs) {
567 rte_free(bp->pf.vf_info);
568 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
569 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
570 bp->pf.max_vfs = new_max_vfs;
571 for (i = 0; i < new_max_vfs; i++) {
572 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
573 bp->pf.vf_info[i].vlan_table =
574 rte_zmalloc("VF VLAN table",
577 if (bp->pf.vf_info[i].vlan_table == NULL)
579 "Fail to alloc VLAN table for VF %d\n",
583 bp->pf.vf_info[i].vlan_table);
584 bp->pf.vf_info[i].vlan_as_table =
585 rte_zmalloc("VF VLAN AS table",
588 if (bp->pf.vf_info[i].vlan_as_table == NULL)
590 "Alloc VLAN AS table for VF %d fail\n",
594 bp->pf.vf_info[i].vlan_as_table);
595 STAILQ_INIT(&bp->pf.vf_info[i].filter);
600 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
601 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
602 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
603 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
604 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
605 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
606 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
607 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
609 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
610 /* TODO: For now, do not support VMDq/RFS on VFs. */
615 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
619 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
621 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
622 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
623 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
624 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
626 bnxt_hwrm_ptp_qcfg(bp);
630 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
631 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
633 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
634 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
635 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
637 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
640 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
641 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
643 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
650 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
654 rc = __bnxt_hwrm_func_qcaps(bp);
655 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
656 rc = bnxt_alloc_ctx_mem(bp);
660 rc = bnxt_hwrm_func_resc_qcaps(bp);
662 bp->flags |= BNXT_FLAG_NEW_RM;
668 int bnxt_hwrm_func_reset(struct bnxt *bp)
671 struct hwrm_func_reset_input req = {.req_type = 0 };
672 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
674 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
676 req.enables = rte_cpu_to_le_32(0);
678 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
686 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
690 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
691 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
693 if (bp->flags & BNXT_FLAG_REGISTERED)
696 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
697 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
698 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
700 /* PFs and trusted VFs should indicate the support of the
701 * Master capability on non Stingray platform
703 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
704 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
706 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
707 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
708 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
709 req.ver_maj = RTE_VER_YEAR;
710 req.ver_min = RTE_VER_MONTH;
711 req.ver_upd = RTE_VER_MINOR;
714 req.enables |= rte_cpu_to_le_32(
715 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
716 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
717 RTE_MIN(sizeof(req.vf_req_fwd),
718 sizeof(bp->pf.vf_req_fwd)));
721 * PF can sniff HWRM API issued by VF. This can be set up by
722 * linux driver and inherited by the DPDK PF driver. Clear
723 * this HWRM sniffer list in FW because DPDK PF driver does
726 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
729 req.flags = rte_cpu_to_le_32(flags);
731 req.async_event_fwd[0] |=
732 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
733 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
734 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
735 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
736 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
737 req.async_event_fwd[0] |=
738 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
739 req.async_event_fwd[1] |=
740 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
741 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
743 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
747 flags = rte_le_to_cpu_32(resp->flags);
748 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
749 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
753 bp->flags |= BNXT_FLAG_REGISTERED;
758 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
760 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
763 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
766 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
771 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
772 struct hwrm_func_vf_cfg_input req = {0};
774 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
776 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
777 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
778 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
779 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
780 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
782 if (BNXT_HAS_RING_GRPS(bp)) {
783 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
784 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
787 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
788 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
789 AGG_RING_MULTIPLIER);
790 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
792 BNXT_NUM_ASYNC_CPR(bp));
793 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
795 BNXT_NUM_ASYNC_CPR(bp));
796 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
797 if (bp->vf_resv_strategy ==
798 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
799 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
800 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
801 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
802 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
803 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
804 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
808 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
809 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
810 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
811 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
812 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
813 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
815 if (test && BNXT_HAS_RING_GRPS(bp))
816 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
818 req.flags = rte_cpu_to_le_32(flags);
819 req.enables |= rte_cpu_to_le_32(enables);
821 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
824 HWRM_CHECK_RESULT_SILENT();
832 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
835 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
836 struct hwrm_func_resource_qcaps_input req = {0};
838 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
839 req.fid = rte_cpu_to_le_16(0xffff);
841 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
846 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
847 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
848 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
849 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
850 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
851 /* func_resource_qcaps does not return max_rx_em_flows.
852 * So use the value provided by func_qcaps.
855 rte_le_to_cpu_16(resp->max_l2_ctxs) +
857 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
858 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
860 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
861 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
862 if (bp->vf_resv_strategy >
863 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
864 bp->vf_resv_strategy =
865 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
871 int bnxt_hwrm_ver_get(struct bnxt *bp)
874 struct hwrm_ver_get_input req = {.req_type = 0 };
875 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
877 uint16_t max_resp_len;
878 char type[RTE_MEMZONE_NAMESIZE];
879 uint32_t dev_caps_cfg;
881 bp->max_req_len = HWRM_MAX_REQ_LEN;
882 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
884 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
885 req.hwrm_intf_min = HWRM_VERSION_MINOR;
886 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
888 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
890 if (bp->flags & BNXT_FLAG_FW_RESET)
891 HWRM_CHECK_RESULT_SILENT();
895 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
896 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
897 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
898 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
899 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
900 (resp->hwrm_fw_min_8b << 16) |
901 (resp->hwrm_fw_bld_8b << 8) |
902 resp->hwrm_fw_rsvd_8b;
903 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
904 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
906 fw_version = resp->hwrm_intf_maj_8b << 16;
907 fw_version |= resp->hwrm_intf_min_8b << 8;
908 fw_version |= resp->hwrm_intf_upd_8b;
909 bp->hwrm_spec_code = fw_version;
911 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
912 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
917 if (bp->max_req_len > resp->max_req_win_len) {
918 PMD_DRV_LOG(ERR, "Unsupported request length\n");
921 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
922 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
923 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
924 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
926 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
927 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
929 if (bp->max_resp_len != max_resp_len) {
930 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
931 bp->pdev->addr.domain, bp->pdev->addr.bus,
932 bp->pdev->addr.devid, bp->pdev->addr.function);
934 rte_free(bp->hwrm_cmd_resp_addr);
936 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
937 if (bp->hwrm_cmd_resp_addr == NULL) {
941 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
942 bp->hwrm_cmd_resp_dma_addr =
943 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
944 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
946 "Unable to map response buffer to physical memory.\n");
950 bp->max_resp_len = max_resp_len;
954 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
956 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
957 PMD_DRV_LOG(DEBUG, "Short command supported\n");
958 bp->flags |= BNXT_FLAG_SHORT_CMD;
962 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
964 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
965 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
966 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
967 bp->pdev->addr.domain, bp->pdev->addr.bus,
968 bp->pdev->addr.devid, bp->pdev->addr.function);
970 rte_free(bp->hwrm_short_cmd_req_addr);
972 bp->hwrm_short_cmd_req_addr =
973 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
974 if (bp->hwrm_short_cmd_req_addr == NULL) {
978 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
979 bp->hwrm_short_cmd_req_dma_addr =
980 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
981 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
982 rte_free(bp->hwrm_short_cmd_req_addr);
984 "Unable to map buffer to physical memory.\n");
990 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
991 bp->flags |= BNXT_FLAG_KONG_MB_EN;
992 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
995 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
996 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1003 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1006 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1007 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1009 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1012 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1015 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1017 HWRM_CHECK_RESULT();
1023 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1026 struct hwrm_port_phy_cfg_input req = {0};
1027 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1028 uint32_t enables = 0;
1030 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1032 if (conf->link_up) {
1033 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1034 if (bp->link_info.auto_mode && conf->link_speed) {
1035 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1036 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1039 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1040 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1041 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1043 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1044 * any auto mode, even "none".
1046 if (!conf->link_speed) {
1047 /* No speeds specified. Enable AutoNeg - all speeds */
1049 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1051 /* AutoNeg - Advertise speeds specified. */
1052 if (conf->auto_link_speed_mask &&
1053 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1055 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1056 req.auto_link_speed_mask =
1057 conf->auto_link_speed_mask;
1059 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1062 req.auto_duplex = conf->duplex;
1063 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1064 req.auto_pause = conf->auto_pause;
1065 req.force_pause = conf->force_pause;
1066 /* Set force_pause if there is no auto or if there is a force */
1067 if (req.auto_pause && !req.force_pause)
1068 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1070 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1072 req.enables = rte_cpu_to_le_32(enables);
1075 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1076 PMD_DRV_LOG(INFO, "Force Link Down\n");
1079 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1081 HWRM_CHECK_RESULT();
1087 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1088 struct bnxt_link_info *link_info)
1091 struct hwrm_port_phy_qcfg_input req = {0};
1092 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1094 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1096 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1098 HWRM_CHECK_RESULT();
1100 link_info->phy_link_status = resp->link;
1101 link_info->link_up =
1102 (link_info->phy_link_status ==
1103 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1104 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1105 link_info->duplex = resp->duplex_cfg;
1106 link_info->pause = resp->pause;
1107 link_info->auto_pause = resp->auto_pause;
1108 link_info->force_pause = resp->force_pause;
1109 link_info->auto_mode = resp->auto_mode;
1110 link_info->phy_type = resp->phy_type;
1111 link_info->media_type = resp->media_type;
1113 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1114 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1115 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1116 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1117 link_info->phy_ver[0] = resp->phy_maj;
1118 link_info->phy_ver[1] = resp->phy_min;
1119 link_info->phy_ver[2] = resp->phy_bld;
1123 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1124 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1125 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1126 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1127 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1128 link_info->auto_link_speed_mask);
1129 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1130 link_info->force_link_speed);
1135 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1138 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1139 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1142 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1144 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1145 /* HWRM Version >= 1.9.1 */
1146 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1148 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1149 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1151 HWRM_CHECK_RESULT();
1153 #define GET_QUEUE_INFO(x) \
1154 bp->cos_queue[x].id = resp->queue_id##x; \
1155 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1168 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1169 bp->tx_cosq_id = bp->cos_queue[0].id;
1171 /* iterate and find the COSq profile to use for Tx */
1172 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1173 if (bp->cos_queue[i].profile ==
1174 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1175 bp->tx_cosq_id = bp->cos_queue[i].id;
1181 bp->max_tc = resp->max_configurable_queues;
1182 bp->max_lltc = resp->max_configurable_lossless_queues;
1183 if (bp->max_tc > BNXT_MAX_QUEUE)
1184 bp->max_tc = BNXT_MAX_QUEUE;
1185 bp->max_q = bp->max_tc;
1187 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1192 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1193 struct bnxt_ring *ring,
1194 uint32_t ring_type, uint32_t map_index,
1195 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1198 uint32_t enables = 0;
1199 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1200 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1201 struct rte_mempool *mb_pool;
1202 uint16_t rx_buf_size;
1204 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1206 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1207 req.fbo = rte_cpu_to_le_32(0);
1208 /* Association of ring index with doorbell index */
1209 req.logical_id = rte_cpu_to_le_16(map_index);
1210 req.length = rte_cpu_to_le_32(ring->ring_size);
1212 switch (ring_type) {
1213 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1214 req.ring_type = ring_type;
1215 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1216 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1217 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1218 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1220 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1222 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1223 req.ring_type = ring_type;
1224 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1225 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1226 if (BNXT_CHIP_THOR(bp)) {
1227 mb_pool = bp->rx_queues[0]->mb_pool;
1228 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1229 RTE_PKTMBUF_HEADROOM;
1230 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1232 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1234 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1236 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1238 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1239 req.ring_type = ring_type;
1240 if (BNXT_HAS_NQ(bp)) {
1241 /* Association of cp ring with nq */
1242 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1244 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1246 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1248 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1249 req.ring_type = ring_type;
1250 req.page_size = BNXT_PAGE_SHFT;
1251 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1253 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1254 req.ring_type = ring_type;
1255 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1257 mb_pool = bp->rx_queues[0]->mb_pool;
1258 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1259 RTE_PKTMBUF_HEADROOM;
1260 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1262 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1263 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1264 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1265 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1268 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1273 req.enables = rte_cpu_to_le_32(enables);
1275 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1277 if (rc || resp->error_code) {
1278 if (rc == 0 && resp->error_code)
1279 rc = rte_le_to_cpu_16(resp->error_code);
1280 switch (ring_type) {
1281 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1283 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1286 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1288 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1291 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1293 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1297 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1299 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1302 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1304 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1308 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1314 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1319 int bnxt_hwrm_ring_free(struct bnxt *bp,
1320 struct bnxt_ring *ring, uint32_t ring_type)
1323 struct hwrm_ring_free_input req = {.req_type = 0 };
1324 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1326 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1328 req.ring_type = ring_type;
1329 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1331 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1333 if (rc || resp->error_code) {
1334 if (rc == 0 && resp->error_code)
1335 rc = rte_le_to_cpu_16(resp->error_code);
1338 switch (ring_type) {
1339 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1340 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1343 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1344 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1347 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1348 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1351 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1353 "hwrm_ring_free nq failed. rc:%d\n", rc);
1355 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1357 "hwrm_ring_free agg failed. rc:%d\n", rc);
1360 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1368 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1371 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1372 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1374 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1376 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1377 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1378 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1379 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1381 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1383 HWRM_CHECK_RESULT();
1385 bp->grp_info[idx].fw_grp_id =
1386 rte_le_to_cpu_16(resp->ring_group_id);
1393 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1396 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1397 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1399 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1401 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1403 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1405 HWRM_CHECK_RESULT();
1408 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1412 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1415 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1416 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1418 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1421 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1423 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1425 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1427 HWRM_CHECK_RESULT();
1433 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1434 unsigned int idx __rte_unused)
1437 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1438 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1440 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1442 req.update_period_ms = rte_cpu_to_le_32(0);
1444 req.stats_dma_addr =
1445 rte_cpu_to_le_64(cpr->hw_stats_map);
1447 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1449 HWRM_CHECK_RESULT();
1451 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1458 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1459 unsigned int idx __rte_unused)
1462 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1463 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1465 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1467 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1469 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1471 HWRM_CHECK_RESULT();
1477 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1480 struct hwrm_vnic_alloc_input req = { 0 };
1481 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1483 if (!BNXT_HAS_RING_GRPS(bp))
1484 goto skip_ring_grps;
1486 /* map ring groups to this vnic */
1487 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1488 vnic->start_grp_id, vnic->end_grp_id);
1489 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1490 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1492 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1493 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1494 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1495 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1498 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1499 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1500 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1502 if (vnic->func_default)
1504 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1507 HWRM_CHECK_RESULT();
1509 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1511 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1515 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1516 struct bnxt_vnic_info *vnic,
1517 struct bnxt_plcmodes_cfg *pmode)
1520 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1521 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1523 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1525 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1527 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1529 HWRM_CHECK_RESULT();
1531 pmode->flags = rte_le_to_cpu_32(resp->flags);
1532 /* dflt_vnic bit doesn't exist in the _cfg command */
1533 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1534 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1535 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1536 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1543 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1544 struct bnxt_vnic_info *vnic,
1545 struct bnxt_plcmodes_cfg *pmode)
1548 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1549 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1551 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1552 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1556 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1558 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1559 req.flags = rte_cpu_to_le_32(pmode->flags);
1560 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1561 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1562 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1563 req.enables = rte_cpu_to_le_32(
1564 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1565 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1566 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1569 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1571 HWRM_CHECK_RESULT();
1577 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1580 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1581 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1582 struct bnxt_plcmodes_cfg pmodes = { 0 };
1583 uint32_t ctx_enable_flag = 0;
1584 uint32_t enables = 0;
1586 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1587 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1591 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1595 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1597 if (BNXT_CHIP_THOR(bp)) {
1598 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1599 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1600 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1602 req.default_rx_ring_id =
1603 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1604 req.default_cmpl_ring_id =
1605 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1606 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1607 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1611 /* Only RSS support for now TBD: COS & LB */
1612 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1613 if (vnic->lb_rule != 0xffff)
1614 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1615 if (vnic->cos_rule != 0xffff)
1616 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1617 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1618 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1619 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1621 enables |= ctx_enable_flag;
1622 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1623 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1624 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1625 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1628 req.enables = rte_cpu_to_le_32(enables);
1629 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1630 req.mru = rte_cpu_to_le_16(vnic->mru);
1631 /* Configure default VNIC only once. */
1632 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1634 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1635 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1637 if (vnic->vlan_strip)
1639 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1642 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1643 if (vnic->roce_dual)
1644 req.flags |= rte_cpu_to_le_32(
1645 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1646 if (vnic->roce_only)
1647 req.flags |= rte_cpu_to_le_32(
1648 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1649 if (vnic->rss_dflt_cr)
1650 req.flags |= rte_cpu_to_le_32(
1651 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1653 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1655 HWRM_CHECK_RESULT();
1658 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1663 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1667 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1668 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1670 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1671 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1674 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1677 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1678 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1679 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1681 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1683 HWRM_CHECK_RESULT();
1685 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1686 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1687 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1688 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1689 vnic->mru = rte_le_to_cpu_16(resp->mru);
1690 vnic->func_default = rte_le_to_cpu_32(
1691 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1692 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1693 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1694 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1695 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1696 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1697 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1698 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1699 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1700 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1701 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1708 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1709 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1713 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1714 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1715 bp->hwrm_cmd_resp_addr;
1717 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1719 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1720 HWRM_CHECK_RESULT();
1722 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1723 if (!BNXT_HAS_RING_GRPS(bp))
1724 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1725 else if (ctx_idx == 0)
1726 vnic->rss_rule = ctx_id;
1733 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1734 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1737 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1738 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1739 bp->hwrm_cmd_resp_addr;
1741 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1742 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1745 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1747 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1749 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1751 HWRM_CHECK_RESULT();
1757 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1760 struct hwrm_vnic_free_input req = {.req_type = 0 };
1761 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1763 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1764 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1768 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1770 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1772 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1774 HWRM_CHECK_RESULT();
1777 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1778 /* Configure default VNIC again if necessary. */
1779 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1780 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1786 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1790 int nr_ctxs = vnic->num_lb_ctxts;
1791 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1792 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1794 for (i = 0; i < nr_ctxs; i++) {
1795 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1797 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1798 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1799 req.hash_mode_flags = vnic->hash_mode;
1801 req.hash_key_tbl_addr =
1802 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1804 req.ring_grp_tbl_addr =
1805 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1806 i * HW_HASH_INDEX_SIZE);
1807 req.ring_table_pair_index = i;
1808 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1810 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1813 HWRM_CHECK_RESULT();
1820 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1821 struct bnxt_vnic_info *vnic)
1824 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1825 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1827 if (!vnic->rss_table)
1830 if (BNXT_CHIP_THOR(bp))
1831 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1833 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1835 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1836 req.hash_mode_flags = vnic->hash_mode;
1838 req.ring_grp_tbl_addr =
1839 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1840 req.hash_key_tbl_addr =
1841 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1842 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1843 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1845 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1847 HWRM_CHECK_RESULT();
1853 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1854 struct bnxt_vnic_info *vnic)
1857 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1858 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1861 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1862 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1866 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1868 req.flags = rte_cpu_to_le_32(
1869 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1871 req.enables = rte_cpu_to_le_32(
1872 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1874 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1875 size -= RTE_PKTMBUF_HEADROOM;
1877 req.jumbo_thresh = rte_cpu_to_le_16(size);
1878 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1880 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1882 HWRM_CHECK_RESULT();
1888 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1889 struct bnxt_vnic_info *vnic, bool enable)
1892 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1893 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1895 if (BNXT_CHIP_THOR(bp))
1898 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1901 req.enables = rte_cpu_to_le_32(
1902 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1903 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1904 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1905 req.flags = rte_cpu_to_le_32(
1906 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1907 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1908 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1909 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1910 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1911 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1912 req.max_agg_segs = rte_cpu_to_le_16(5);
1914 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1915 req.min_agg_len = rte_cpu_to_le_32(512);
1917 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1919 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1921 HWRM_CHECK_RESULT();
1927 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1929 struct hwrm_func_cfg_input req = {0};
1930 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1933 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1934 req.enables = rte_cpu_to_le_32(
1935 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1936 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1937 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1939 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1941 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1942 HWRM_CHECK_RESULT();
1945 bp->pf.vf_info[vf].random_mac = false;
1950 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1954 struct hwrm_func_qstats_input req = {.req_type = 0};
1955 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1957 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1959 req.fid = rte_cpu_to_le_16(fid);
1961 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1963 HWRM_CHECK_RESULT();
1966 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1973 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1974 struct rte_eth_stats *stats)
1977 struct hwrm_func_qstats_input req = {.req_type = 0};
1978 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1980 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1982 req.fid = rte_cpu_to_le_16(fid);
1984 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1986 HWRM_CHECK_RESULT();
1988 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1989 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1990 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1991 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1992 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1993 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1995 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1996 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1997 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1998 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1999 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2000 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2002 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2003 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2004 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2011 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2014 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2015 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2017 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2019 req.fid = rte_cpu_to_le_16(fid);
2021 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2023 HWRM_CHECK_RESULT();
2030 * HWRM utility functions
2033 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2038 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2039 struct bnxt_tx_queue *txq;
2040 struct bnxt_rx_queue *rxq;
2041 struct bnxt_cp_ring_info *cpr;
2043 if (i >= bp->rx_cp_nr_rings) {
2044 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2047 rxq = bp->rx_queues[i];
2051 rc = bnxt_hwrm_stat_clear(bp, cpr);
2058 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2062 struct bnxt_cp_ring_info *cpr;
2064 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2066 if (i >= bp->rx_cp_nr_rings) {
2067 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2069 cpr = bp->rx_queues[i]->cp_ring;
2070 if (BNXT_HAS_RING_GRPS(bp))
2071 bp->grp_info[i].fw_stats_ctx = -1;
2073 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2074 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2075 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2083 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2088 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2089 struct bnxt_tx_queue *txq;
2090 struct bnxt_rx_queue *rxq;
2091 struct bnxt_cp_ring_info *cpr;
2093 if (i >= bp->rx_cp_nr_rings) {
2094 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2097 rxq = bp->rx_queues[i];
2101 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2109 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2114 if (!BNXT_HAS_RING_GRPS(bp))
2117 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2119 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2122 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2130 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2132 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2134 bnxt_hwrm_ring_free(bp, cp_ring,
2135 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2136 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2137 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2138 sizeof(*cpr->cp_desc_ring));
2139 cpr->cp_raw_cons = 0;
2143 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2145 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2147 bnxt_hwrm_ring_free(bp, cp_ring,
2148 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2149 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2150 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2151 sizeof(*cpr->cp_desc_ring));
2152 cpr->cp_raw_cons = 0;
2156 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2158 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2159 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2160 struct bnxt_ring *ring = rxr->rx_ring_struct;
2161 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2163 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2164 bnxt_hwrm_ring_free(bp, ring,
2165 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2166 ring->fw_ring_id = INVALID_HW_RING_ID;
2167 if (BNXT_HAS_RING_GRPS(bp))
2168 bp->grp_info[queue_index].rx_fw_ring_id =
2170 memset(rxr->rx_desc_ring, 0,
2171 rxr->rx_ring_struct->ring_size *
2172 sizeof(*rxr->rx_desc_ring));
2173 memset(rxr->rx_buf_ring, 0,
2174 rxr->rx_ring_struct->ring_size *
2175 sizeof(*rxr->rx_buf_ring));
2178 ring = rxr->ag_ring_struct;
2179 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2180 bnxt_hwrm_ring_free(bp, ring,
2181 BNXT_CHIP_THOR(bp) ?
2182 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2183 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2184 ring->fw_ring_id = INVALID_HW_RING_ID;
2185 memset(rxr->ag_buf_ring, 0,
2186 rxr->ag_ring_struct->ring_size *
2187 sizeof(*rxr->ag_buf_ring));
2189 if (BNXT_HAS_RING_GRPS(bp))
2190 bp->grp_info[queue_index].ag_fw_ring_id =
2193 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2194 bnxt_free_cp_ring(bp, cpr);
2196 bnxt_free_nq_ring(bp, rxq->nq_ring);
2199 if (BNXT_HAS_RING_GRPS(bp))
2200 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2203 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2207 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2208 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2209 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2210 struct bnxt_ring *ring = txr->tx_ring_struct;
2211 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2213 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2214 bnxt_hwrm_ring_free(bp, ring,
2215 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2216 ring->fw_ring_id = INVALID_HW_RING_ID;
2217 memset(txr->tx_desc_ring, 0,
2218 txr->tx_ring_struct->ring_size *
2219 sizeof(*txr->tx_desc_ring));
2220 memset(txr->tx_buf_ring, 0,
2221 txr->tx_ring_struct->ring_size *
2222 sizeof(*txr->tx_buf_ring));
2226 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2227 bnxt_free_cp_ring(bp, cpr);
2228 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2230 bnxt_free_nq_ring(bp, txq->nq_ring);
2234 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2235 bnxt_free_hwrm_rx_ring(bp, i);
2240 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2245 if (!BNXT_HAS_RING_GRPS(bp))
2248 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2249 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2256 void bnxt_free_hwrm_resources(struct bnxt *bp)
2258 /* Release memzone */
2259 rte_free(bp->hwrm_cmd_resp_addr);
2260 rte_free(bp->hwrm_short_cmd_req_addr);
2261 bp->hwrm_cmd_resp_addr = NULL;
2262 bp->hwrm_short_cmd_req_addr = NULL;
2263 bp->hwrm_cmd_resp_dma_addr = 0;
2264 bp->hwrm_short_cmd_req_dma_addr = 0;
2267 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2269 struct rte_pci_device *pdev = bp->pdev;
2270 char type[RTE_MEMZONE_NAMESIZE];
2272 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2273 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2274 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2275 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2276 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2277 if (bp->hwrm_cmd_resp_addr == NULL)
2279 bp->hwrm_cmd_resp_dma_addr =
2280 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2281 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2283 "unable to map response address to physical memory\n");
2286 rte_spinlock_init(&bp->hwrm_lock);
2291 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2293 struct bnxt_filter_info *filter;
2296 STAILQ_FOREACH(filter, &vnic->filter, next) {
2297 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2298 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2299 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2300 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2302 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2303 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2311 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2313 struct bnxt_filter_info *filter;
2314 struct rte_flow *flow;
2317 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2318 filter = flow->filter;
2319 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2320 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2321 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2322 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2323 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2325 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2327 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2335 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2337 struct bnxt_filter_info *filter;
2340 STAILQ_FOREACH(filter, &vnic->filter, next) {
2341 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2342 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2344 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2345 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2348 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2356 void bnxt_free_tunnel_ports(struct bnxt *bp)
2358 if (bp->vxlan_port_cnt)
2359 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2360 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2362 if (bp->geneve_port_cnt)
2363 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2364 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2365 bp->geneve_port = 0;
2368 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2372 if (bp->vnic_info == NULL)
2376 * Cleanup VNICs in reverse order, to make sure the L2 filter
2377 * from vnic0 is last to be cleaned up.
2379 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2380 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2382 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2383 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2387 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2389 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2391 if (BNXT_CHIP_THOR(bp)) {
2392 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2393 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2394 vnic->fw_grp_ids[j]);
2395 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2397 vnic->num_lb_ctxts = 0;
2399 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2400 vnic->rss_rule = INVALID_HW_RING_ID;
2403 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2405 bnxt_hwrm_vnic_free(bp, vnic);
2407 rte_free(vnic->fw_grp_ids);
2409 /* Ring resources */
2410 bnxt_free_all_hwrm_rings(bp);
2411 bnxt_free_all_hwrm_ring_grps(bp);
2412 bnxt_free_all_hwrm_stat_ctxs(bp);
2413 bnxt_free_tunnel_ports(bp);
2416 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2418 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2420 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2421 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2423 switch (conf_link_speed) {
2424 case ETH_LINK_SPEED_10M_HD:
2425 case ETH_LINK_SPEED_100M_HD:
2427 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2429 return hw_link_duplex;
2432 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2434 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2437 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2439 uint16_t eth_link_speed = 0;
2441 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2442 return ETH_LINK_SPEED_AUTONEG;
2444 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2445 case ETH_LINK_SPEED_100M:
2446 case ETH_LINK_SPEED_100M_HD:
2449 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2451 case ETH_LINK_SPEED_1G:
2453 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2455 case ETH_LINK_SPEED_2_5G:
2457 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2459 case ETH_LINK_SPEED_10G:
2461 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2463 case ETH_LINK_SPEED_20G:
2465 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2467 case ETH_LINK_SPEED_25G:
2469 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2471 case ETH_LINK_SPEED_40G:
2473 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2475 case ETH_LINK_SPEED_50G:
2477 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2479 case ETH_LINK_SPEED_100G:
2481 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2485 "Unsupported link speed %d; default to AUTO\n",
2489 return eth_link_speed;
2492 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2493 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2494 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2495 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2497 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2501 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2504 if (link_speed & ETH_LINK_SPEED_FIXED) {
2505 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2507 if (one_speed & (one_speed - 1)) {
2509 "Invalid advertised speeds (%u) for port %u\n",
2510 link_speed, port_id);
2513 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2515 "Unsupported advertised speed (%u) for port %u\n",
2516 link_speed, port_id);
2520 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2522 "Unsupported advertised speeds (%u) for port %u\n",
2523 link_speed, port_id);
2531 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2535 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2536 if (bp->link_info.support_speeds)
2537 return bp->link_info.support_speeds;
2538 link_speed = BNXT_SUPPORTED_SPEEDS;
2541 if (link_speed & ETH_LINK_SPEED_100M)
2542 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2543 if (link_speed & ETH_LINK_SPEED_100M_HD)
2544 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2545 if (link_speed & ETH_LINK_SPEED_1G)
2546 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2547 if (link_speed & ETH_LINK_SPEED_2_5G)
2548 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2549 if (link_speed & ETH_LINK_SPEED_10G)
2550 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2551 if (link_speed & ETH_LINK_SPEED_20G)
2552 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2553 if (link_speed & ETH_LINK_SPEED_25G)
2554 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2555 if (link_speed & ETH_LINK_SPEED_40G)
2556 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2557 if (link_speed & ETH_LINK_SPEED_50G)
2558 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2559 if (link_speed & ETH_LINK_SPEED_100G)
2560 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2564 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2566 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2568 switch (hw_link_speed) {
2569 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2570 eth_link_speed = ETH_SPEED_NUM_100M;
2572 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2573 eth_link_speed = ETH_SPEED_NUM_1G;
2575 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2576 eth_link_speed = ETH_SPEED_NUM_2_5G;
2578 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2579 eth_link_speed = ETH_SPEED_NUM_10G;
2581 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2582 eth_link_speed = ETH_SPEED_NUM_20G;
2584 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2585 eth_link_speed = ETH_SPEED_NUM_25G;
2587 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2588 eth_link_speed = ETH_SPEED_NUM_40G;
2590 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2591 eth_link_speed = ETH_SPEED_NUM_50G;
2593 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2594 eth_link_speed = ETH_SPEED_NUM_100G;
2596 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2598 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2602 return eth_link_speed;
2605 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2607 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2609 switch (hw_link_duplex) {
2610 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2611 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2613 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2615 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2616 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2619 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2623 return eth_link_duplex;
2626 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2629 struct bnxt_link_info *link_info = &bp->link_info;
2631 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2634 "Get link config failed with rc %d\n", rc);
2637 if (link_info->link_speed)
2639 bnxt_parse_hw_link_speed(link_info->link_speed);
2641 link->link_speed = ETH_SPEED_NUM_NONE;
2642 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2643 link->link_status = link_info->link_up;
2644 link->link_autoneg = link_info->auto_mode ==
2645 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2646 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2651 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2654 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2655 struct bnxt_link_info link_req;
2656 uint16_t speed, autoneg;
2658 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2661 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2662 bp->eth_dev->data->port_id);
2666 memset(&link_req, 0, sizeof(link_req));
2667 link_req.link_up = link_up;
2671 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2672 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2673 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2674 /* Autoneg can be done only when the FW allows */
2675 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2676 bp->link_info.force_link_speed)) {
2677 link_req.phy_flags |=
2678 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2679 link_req.auto_link_speed_mask =
2680 bnxt_parse_eth_link_speed_mask(bp,
2681 dev_conf->link_speeds);
2683 if (bp->link_info.phy_type ==
2684 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2685 bp->link_info.phy_type ==
2686 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2687 bp->link_info.media_type ==
2688 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2689 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2693 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2694 /* If user wants a particular speed try that first. */
2696 link_req.link_speed = speed;
2697 else if (bp->link_info.force_link_speed)
2698 link_req.link_speed = bp->link_info.force_link_speed;
2700 link_req.link_speed = bp->link_info.auto_link_speed;
2702 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2703 link_req.auto_pause = bp->link_info.auto_pause;
2704 link_req.force_pause = bp->link_info.force_pause;
2707 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2710 "Set link config failed with rc %d\n", rc);
2718 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2720 struct hwrm_func_qcfg_input req = {0};
2721 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2725 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2726 req.fid = rte_cpu_to_le_16(0xffff);
2728 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2730 HWRM_CHECK_RESULT();
2732 /* Hard Coded.. 0xfff VLAN ID mask */
2733 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2734 flags = rte_le_to_cpu_16(resp->flags);
2735 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2736 bp->flags |= BNXT_FLAG_MULTI_HOST;
2738 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2739 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2740 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2741 } else if (BNXT_VF(bp) &&
2742 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2743 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2744 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2750 switch (resp->port_partition_type) {
2751 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2752 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2753 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2755 bp->port_partition_type = resp->port_partition_type;
2758 bp->port_partition_type = 0;
2767 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2768 struct hwrm_func_qcaps_output *qcaps)
2770 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2771 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2772 sizeof(qcaps->mac_address));
2773 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2774 qcaps->max_rx_rings = fcfg->num_rx_rings;
2775 qcaps->max_tx_rings = fcfg->num_tx_rings;
2776 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2777 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2779 qcaps->first_vf_id = 0;
2780 qcaps->max_vnics = fcfg->num_vnics;
2781 qcaps->max_decap_records = 0;
2782 qcaps->max_encap_records = 0;
2783 qcaps->max_tx_wm_flows = 0;
2784 qcaps->max_tx_em_flows = 0;
2785 qcaps->max_rx_wm_flows = 0;
2786 qcaps->max_rx_em_flows = 0;
2787 qcaps->max_flow_id = 0;
2788 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2789 qcaps->max_sp_tx_rings = 0;
2790 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2793 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2795 struct hwrm_func_cfg_input req = {0};
2796 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2800 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2801 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2802 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2803 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2804 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2805 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2806 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2807 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2808 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2810 if (BNXT_HAS_RING_GRPS(bp)) {
2811 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2812 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2813 } else if (BNXT_HAS_NQ(bp)) {
2814 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2815 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2818 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2819 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2820 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2821 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2823 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2824 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2825 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2826 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2827 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2828 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2829 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2830 req.fid = rte_cpu_to_le_16(0xffff);
2831 req.enables = rte_cpu_to_le_32(enables);
2833 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2835 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2837 HWRM_CHECK_RESULT();
2843 static void populate_vf_func_cfg_req(struct bnxt *bp,
2844 struct hwrm_func_cfg_input *req,
2847 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2848 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2849 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2850 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2851 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2852 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2853 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2854 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2855 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2856 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2858 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2859 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2861 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2862 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2864 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2866 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2867 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2869 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2870 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2871 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2872 /* TODO: For now, do not support VMDq/RFS on VFs. */
2873 req->num_vnics = rte_cpu_to_le_16(1);
2874 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2878 static void add_random_mac_if_needed(struct bnxt *bp,
2879 struct hwrm_func_cfg_input *cfg_req,
2882 struct rte_ether_addr mac;
2884 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2887 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2889 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2890 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2891 bp->pf.vf_info[vf].random_mac = true;
2893 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2894 RTE_ETHER_ADDR_LEN);
2898 static void reserve_resources_from_vf(struct bnxt *bp,
2899 struct hwrm_func_cfg_input *cfg_req,
2902 struct hwrm_func_qcaps_input req = {0};
2903 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2906 /* Get the actual allocated values now */
2907 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2908 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2909 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2912 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2913 copy_func_cfg_to_qcaps(cfg_req, resp);
2914 } else if (resp->error_code) {
2915 rc = rte_le_to_cpu_16(resp->error_code);
2916 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2917 copy_func_cfg_to_qcaps(cfg_req, resp);
2920 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2921 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2922 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2923 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2924 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2925 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2927 * TODO: While not supporting VMDq with VFs, max_vnics is always
2928 * forced to 1 in this case
2930 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2931 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2936 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2938 struct hwrm_func_qcfg_input req = {0};
2939 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2942 /* Check for zero MAC address */
2943 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2944 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2945 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2946 HWRM_CHECK_RESULT();
2947 rc = rte_le_to_cpu_16(resp->vlan);
2954 static int update_pf_resource_max(struct bnxt *bp)
2956 struct hwrm_func_qcfg_input req = {0};
2957 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2960 /* And copy the allocated numbers into the pf struct */
2961 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2962 req.fid = rte_cpu_to_le_16(0xffff);
2963 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2964 HWRM_CHECK_RESULT();
2966 /* Only TX ring value reflects actual allocation? TODO */
2967 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2968 bp->pf.evb_mode = resp->evb_mode;
2975 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2980 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2984 rc = bnxt_hwrm_func_qcaps(bp);
2988 bp->pf.func_cfg_flags &=
2989 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2990 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2991 bp->pf.func_cfg_flags |=
2992 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2993 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2994 rc = __bnxt_hwrm_func_qcaps(bp);
2998 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3000 struct hwrm_func_cfg_input req = {0};
3001 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3008 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3012 rc = bnxt_hwrm_func_qcaps(bp);
3017 bp->pf.active_vfs = num_vfs;
3020 * First, configure the PF to only use one TX ring. This ensures that
3021 * there are enough rings for all VFs.
3023 * If we don't do this, when we call func_alloc() later, we will lock
3024 * extra rings to the PF that won't be available during func_cfg() of
3027 * This has been fixed with firmware versions above 20.6.54
3029 bp->pf.func_cfg_flags &=
3030 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3031 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3032 bp->pf.func_cfg_flags |=
3033 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3034 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3039 * Now, create and register a buffer to hold forwarded VF requests
3041 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3042 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3043 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3044 if (bp->pf.vf_req_buf == NULL) {
3048 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3049 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3050 for (i = 0; i < num_vfs; i++)
3051 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3052 (i * HWRM_MAX_REQ_LEN);
3054 rc = bnxt_hwrm_func_buf_rgtr(bp);
3058 populate_vf_func_cfg_req(bp, &req, num_vfs);
3060 bp->pf.active_vfs = 0;
3061 for (i = 0; i < num_vfs; i++) {
3062 add_random_mac_if_needed(bp, &req, i);
3064 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3065 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3066 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3067 rc = bnxt_hwrm_send_message(bp,
3072 /* Clear enable flag for next pass */
3073 req.enables &= ~rte_cpu_to_le_32(
3074 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3076 if (rc || resp->error_code) {
3078 "Failed to initizlie VF %d\n", i);
3080 "Not all VFs available. (%d, %d)\n",
3081 rc, resp->error_code);
3088 reserve_resources_from_vf(bp, &req, i);
3089 bp->pf.active_vfs++;
3090 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3094 * Now configure the PF to use "the rest" of the resources
3095 * We're using STD_TX_RING_MODE here though which will limit the TX
3096 * rings. This will allow QoS to function properly. Not setting this
3097 * will cause PF rings to break bandwidth settings.
3099 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3103 rc = update_pf_resource_max(bp);
3110 bnxt_hwrm_func_buf_unrgtr(bp);
3114 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3116 struct hwrm_func_cfg_input req = {0};
3117 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3120 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3122 req.fid = rte_cpu_to_le_16(0xffff);
3123 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3124 req.evb_mode = bp->pf.evb_mode;
3126 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3127 HWRM_CHECK_RESULT();
3133 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3134 uint8_t tunnel_type)
3136 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3137 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3140 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3141 req.tunnel_type = tunnel_type;
3142 req.tunnel_dst_port_val = port;
3143 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3144 HWRM_CHECK_RESULT();
3146 switch (tunnel_type) {
3147 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3148 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3149 bp->vxlan_port = port;
3151 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3152 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3153 bp->geneve_port = port;
3164 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3165 uint8_t tunnel_type)
3167 struct hwrm_tunnel_dst_port_free_input req = {0};
3168 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3171 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3173 req.tunnel_type = tunnel_type;
3174 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3175 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3177 HWRM_CHECK_RESULT();
3183 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3186 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3187 struct hwrm_func_cfg_input req = {0};
3190 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3192 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3193 req.flags = rte_cpu_to_le_32(flags);
3194 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3196 HWRM_CHECK_RESULT();
3202 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3204 uint32_t *flag = flagp;
3206 vnic->flags = *flag;
3209 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3211 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3214 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3217 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3218 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3220 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3222 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3223 req.req_buf_page_size = rte_cpu_to_le_16(
3224 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3225 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3226 req.req_buf_page_addr0 =
3227 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3228 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3230 "unable to map buffer address to physical memory\n");
3234 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3236 HWRM_CHECK_RESULT();
3242 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3245 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3246 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3248 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3251 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3253 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3255 HWRM_CHECK_RESULT();
3261 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3263 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3264 struct hwrm_func_cfg_input req = {0};
3267 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3269 req.fid = rte_cpu_to_le_16(0xffff);
3270 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3271 req.enables = rte_cpu_to_le_32(
3272 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3273 req.async_event_cr = rte_cpu_to_le_16(
3274 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3275 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3277 HWRM_CHECK_RESULT();
3283 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3285 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3286 struct hwrm_func_vf_cfg_input req = {0};
3289 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3291 req.enables = rte_cpu_to_le_32(
3292 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3293 req.async_event_cr = rte_cpu_to_le_16(
3294 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3295 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3297 HWRM_CHECK_RESULT();
3303 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3305 struct hwrm_func_cfg_input req = {0};
3306 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3307 uint16_t dflt_vlan, fid;
3308 uint32_t func_cfg_flags;
3311 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3314 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3315 fid = bp->pf.vf_info[vf].fid;
3316 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3318 fid = rte_cpu_to_le_16(0xffff);
3319 func_cfg_flags = bp->pf.func_cfg_flags;
3320 dflt_vlan = bp->vlan;
3323 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3324 req.fid = rte_cpu_to_le_16(fid);
3325 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3326 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3328 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3330 HWRM_CHECK_RESULT();
3336 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3337 uint16_t max_bw, uint16_t enables)
3339 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3340 struct hwrm_func_cfg_input req = {0};
3343 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3345 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3346 req.enables |= rte_cpu_to_le_32(enables);
3347 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3348 req.max_bw = rte_cpu_to_le_32(max_bw);
3349 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3351 HWRM_CHECK_RESULT();
3357 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3359 struct hwrm_func_cfg_input req = {0};
3360 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3363 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3365 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3366 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3367 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3368 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3370 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3372 HWRM_CHECK_RESULT();
3378 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3383 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3385 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3390 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3391 void *encaped, size_t ec_size)
3394 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3395 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3397 if (ec_size > sizeof(req.encap_request))
3400 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3402 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3403 memcpy(req.encap_request, encaped, ec_size);
3405 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3407 HWRM_CHECK_RESULT();
3413 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3414 struct rte_ether_addr *mac)
3416 struct hwrm_func_qcfg_input req = {0};
3417 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3420 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3422 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3423 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3425 HWRM_CHECK_RESULT();
3427 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3434 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3435 void *encaped, size_t ec_size)
3438 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3439 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3441 if (ec_size > sizeof(req.encap_request))
3444 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3446 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3447 memcpy(req.encap_request, encaped, ec_size);
3449 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3451 HWRM_CHECK_RESULT();
3457 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3458 struct rte_eth_stats *stats, uint8_t rx)
3461 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3462 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3464 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3466 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3468 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3470 HWRM_CHECK_RESULT();
3473 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3474 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3475 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3476 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3477 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3478 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3479 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3480 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3482 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3483 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3484 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3485 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3486 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3487 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3496 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3498 struct hwrm_port_qstats_input req = {0};
3499 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3500 struct bnxt_pf_info *pf = &bp->pf;
3503 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3505 req.port_id = rte_cpu_to_le_16(pf->port_id);
3506 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3507 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3508 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3510 HWRM_CHECK_RESULT();
3516 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3518 struct hwrm_port_clr_stats_input req = {0};
3519 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3520 struct bnxt_pf_info *pf = &bp->pf;
3523 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3524 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3525 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3528 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3530 req.port_id = rte_cpu_to_le_16(pf->port_id);
3531 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3533 HWRM_CHECK_RESULT();
3539 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3541 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3542 struct hwrm_port_led_qcaps_input req = {0};
3548 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3549 req.port_id = bp->pf.port_id;
3550 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3552 HWRM_CHECK_RESULT();
3554 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3557 bp->num_leds = resp->num_leds;
3558 memcpy(bp->leds, &resp->led0_id,
3559 sizeof(bp->leds[0]) * bp->num_leds);
3560 for (i = 0; i < bp->num_leds; i++) {
3561 struct bnxt_led_info *led = &bp->leds[i];
3563 uint16_t caps = led->led_state_caps;
3565 if (!led->led_group_id ||
3566 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3578 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3580 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3581 struct hwrm_port_led_cfg_input req = {0};
3582 struct bnxt_led_cfg *led_cfg;
3583 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3584 uint16_t duration = 0;
3587 if (!bp->num_leds || BNXT_VF(bp))
3590 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3593 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3594 duration = rte_cpu_to_le_16(500);
3596 req.port_id = bp->pf.port_id;
3597 req.num_leds = bp->num_leds;
3598 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3599 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3600 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3601 led_cfg->led_id = bp->leds[i].led_id;
3602 led_cfg->led_state = led_state;
3603 led_cfg->led_blink_on = duration;
3604 led_cfg->led_blink_off = duration;
3605 led_cfg->led_group_id = bp->leds[i].led_group_id;
3608 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3610 HWRM_CHECK_RESULT();
3616 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3620 struct hwrm_nvm_get_dir_info_input req = {0};
3621 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3623 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3625 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3627 HWRM_CHECK_RESULT();
3629 *entries = rte_le_to_cpu_32(resp->entries);
3630 *length = rte_le_to_cpu_32(resp->entry_length);
3636 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3639 uint32_t dir_entries;
3640 uint32_t entry_length;
3643 rte_iova_t dma_handle;
3644 struct hwrm_nvm_get_dir_entries_input req = {0};
3645 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3647 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3651 *data++ = dir_entries;
3652 *data++ = entry_length;
3654 memset(data, 0xff, len);
3656 buflen = dir_entries * entry_length;
3657 buf = rte_malloc("nvm_dir", buflen, 0);
3658 rte_mem_lock_page(buf);
3661 dma_handle = rte_mem_virt2iova(buf);
3662 if (dma_handle == RTE_BAD_IOVA) {
3664 "unable to map response address to physical memory\n");
3667 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3668 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3669 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3672 memcpy(data, buf, len > buflen ? buflen : len);
3675 HWRM_CHECK_RESULT();
3681 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3682 uint32_t offset, uint32_t length,
3687 rte_iova_t dma_handle;
3688 struct hwrm_nvm_read_input req = {0};
3689 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3691 buf = rte_malloc("nvm_item", length, 0);
3692 rte_mem_lock_page(buf);
3696 dma_handle = rte_mem_virt2iova(buf);
3697 if (dma_handle == RTE_BAD_IOVA) {
3699 "unable to map response address to physical memory\n");
3702 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3703 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3704 req.dir_idx = rte_cpu_to_le_16(index);
3705 req.offset = rte_cpu_to_le_32(offset);
3706 req.len = rte_cpu_to_le_32(length);
3707 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3709 memcpy(data, buf, length);
3712 HWRM_CHECK_RESULT();
3718 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3721 struct hwrm_nvm_erase_dir_entry_input req = {0};
3722 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3724 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3725 req.dir_idx = rte_cpu_to_le_16(index);
3726 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3727 HWRM_CHECK_RESULT();
3734 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3735 uint16_t dir_ordinal, uint16_t dir_ext,
3736 uint16_t dir_attr, const uint8_t *data,
3740 struct hwrm_nvm_write_input req = {0};
3741 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3742 rte_iova_t dma_handle;
3745 buf = rte_malloc("nvm_write", data_len, 0);
3746 rte_mem_lock_page(buf);
3750 dma_handle = rte_mem_virt2iova(buf);
3751 if (dma_handle == RTE_BAD_IOVA) {
3753 "unable to map response address to physical memory\n");
3756 memcpy(buf, data, data_len);
3758 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3760 req.dir_type = rte_cpu_to_le_16(dir_type);
3761 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3762 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3763 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3764 req.dir_data_length = rte_cpu_to_le_32(data_len);
3765 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3767 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3770 HWRM_CHECK_RESULT();
3777 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3779 uint32_t *count = cbdata;
3781 *count = *count + 1;
3784 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3785 struct bnxt_vnic_info *vnic __rte_unused)
3790 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3794 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3795 &count, bnxt_vnic_count_hwrm_stub);
3800 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3803 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3804 struct hwrm_func_vf_vnic_ids_query_output *resp =
3805 bp->hwrm_cmd_resp_addr;
3808 /* First query all VNIC ids */
3809 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3811 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3812 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3813 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3815 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3818 "unable to map VNIC ID table address to physical memory\n");
3821 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3822 HWRM_CHECK_RESULT();
3823 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3831 * This function queries the VNIC IDs for a specified VF. It then calls
3832 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3833 * Then it calls the hwrm_cb function to program this new vnic configuration.
3835 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3836 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3837 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3839 struct bnxt_vnic_info vnic;
3841 int i, num_vnic_ids;
3846 /* First query all VNIC ids */
3847 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3848 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3849 RTE_CACHE_LINE_SIZE);
3850 if (vnic_ids == NULL)
3853 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3854 rte_mem_lock_page(((char *)vnic_ids) + sz);
3856 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3858 if (num_vnic_ids < 0)
3859 return num_vnic_ids;
3861 /* Retrieve VNIC, update bd_stall then update */
3863 for (i = 0; i < num_vnic_ids; i++) {
3864 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3865 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3866 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3869 if (vnic.mru <= 4) /* Indicates unallocated */
3872 vnic_cb(&vnic, cbdata);
3874 rc = hwrm_cb(bp, &vnic);
3884 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3887 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3888 struct hwrm_func_cfg_input req = {0};
3891 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3893 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3894 req.enables |= rte_cpu_to_le_32(
3895 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3896 req.vlan_antispoof_mode = on ?
3897 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3898 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3899 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3901 HWRM_CHECK_RESULT();
3907 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3909 struct bnxt_vnic_info vnic;
3912 int num_vnic_ids, i;
3916 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3917 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3918 RTE_CACHE_LINE_SIZE);
3919 if (vnic_ids == NULL)
3922 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3923 rte_mem_lock_page(((char *)vnic_ids) + sz);
3925 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3931 * Loop through to find the default VNIC ID.
3932 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3933 * by sending the hwrm_func_qcfg command to the firmware.
3935 for (i = 0; i < num_vnic_ids; i++) {
3936 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3937 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3938 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3939 bp->pf.first_vf_id + vf);
3942 if (vnic.func_default) {
3944 return vnic.fw_vnic_id;
3947 /* Could not find a default VNIC. */
3948 PMD_DRV_LOG(ERR, "No default VNIC\n");
3954 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3956 struct bnxt_filter_info *filter)
3959 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3960 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3961 uint32_t enables = 0;
3963 if (filter->fw_em_filter_id != UINT64_MAX)
3964 bnxt_hwrm_clear_em_filter(bp, filter);
3966 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3968 req.flags = rte_cpu_to_le_32(filter->flags);
3970 enables = filter->enables |
3971 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3972 req.dst_id = rte_cpu_to_le_16(dst_id);
3974 if (filter->ip_addr_type) {
3975 req.ip_addr_type = filter->ip_addr_type;
3976 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3979 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3980 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3982 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3983 memcpy(req.src_macaddr, filter->src_macaddr,
3984 RTE_ETHER_ADDR_LEN);
3986 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3987 memcpy(req.dst_macaddr, filter->dst_macaddr,
3988 RTE_ETHER_ADDR_LEN);
3990 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3991 req.ovlan_vid = filter->l2_ovlan;
3993 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3994 req.ivlan_vid = filter->l2_ivlan;
3996 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3997 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3999 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4000 req.ip_protocol = filter->ip_protocol;
4002 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4003 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4005 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4006 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4008 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4009 req.src_port = rte_cpu_to_be_16(filter->src_port);
4011 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4012 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4014 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4015 req.mirror_vnic_id = filter->mirror_vnic_id;
4017 req.enables = rte_cpu_to_le_32(enables);
4019 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4021 HWRM_CHECK_RESULT();
4023 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4029 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4032 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4033 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4035 if (filter->fw_em_filter_id == UINT64_MAX)
4038 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4039 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4041 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4043 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4045 HWRM_CHECK_RESULT();
4048 filter->fw_em_filter_id = UINT64_MAX;
4049 filter->fw_l2_filter_id = UINT64_MAX;
4054 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4056 struct bnxt_filter_info *filter)
4059 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4060 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4061 bp->hwrm_cmd_resp_addr;
4062 uint32_t enables = 0;
4064 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4065 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4067 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4069 req.flags = rte_cpu_to_le_32(filter->flags);
4071 enables = filter->enables |
4072 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4073 req.dst_id = rte_cpu_to_le_16(dst_id);
4076 if (filter->ip_addr_type) {
4077 req.ip_addr_type = filter->ip_addr_type;
4079 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4082 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4083 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4085 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4086 memcpy(req.src_macaddr, filter->src_macaddr,
4087 RTE_ETHER_ADDR_LEN);
4089 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4090 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4091 //RTE_ETHER_ADDR_LEN);
4093 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4094 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4096 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4097 req.ip_protocol = filter->ip_protocol;
4099 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4100 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4102 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4103 req.src_ipaddr_mask[0] =
4104 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4106 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4107 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4109 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4110 req.dst_ipaddr_mask[0] =
4111 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4113 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4114 req.src_port = rte_cpu_to_le_16(filter->src_port);
4116 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4117 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4119 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4120 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4122 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4123 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4125 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4126 req.mirror_vnic_id = filter->mirror_vnic_id;
4128 req.enables = rte_cpu_to_le_32(enables);
4130 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4132 HWRM_CHECK_RESULT();
4134 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4140 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4141 struct bnxt_filter_info *filter)
4144 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4145 struct hwrm_cfa_ntuple_filter_free_output *resp =
4146 bp->hwrm_cmd_resp_addr;
4148 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4151 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4153 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4155 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4157 HWRM_CHECK_RESULT();
4160 filter->fw_ntuple_filter_id = UINT64_MAX;
4166 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4168 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4169 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4170 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4171 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4172 uint16_t *ring_tbl = vnic->rss_table;
4173 int nr_ctxs = vnic->num_lb_ctxts;
4174 int max_rings = bp->rx_nr_rings;
4178 for (i = 0, k = 0; i < nr_ctxs; i++) {
4179 struct bnxt_rx_ring_info *rxr;
4180 struct bnxt_cp_ring_info *cpr;
4182 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4184 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4185 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4186 req.hash_mode_flags = vnic->hash_mode;
4188 req.ring_grp_tbl_addr =
4189 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4190 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4191 2 * sizeof(*ring_tbl));
4192 req.hash_key_tbl_addr =
4193 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4195 req.ring_table_pair_index = i;
4196 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4198 for (j = 0; j < 64; j++) {
4201 /* Find next active ring. */
4202 for (cnt = 0; cnt < max_rings; cnt++) {
4203 if (rx_queue_state[k] !=
4204 RTE_ETH_QUEUE_STATE_STOPPED)
4206 if (++k == max_rings)
4210 /* Return if no rings are active. */
4211 if (cnt == max_rings)
4214 /* Add rx/cp ring pair to RSS table. */
4215 rxr = rxqs[k]->rx_ring;
4216 cpr = rxqs[k]->cp_ring;
4218 ring_id = rxr->rx_ring_struct->fw_ring_id;
4219 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4220 ring_id = cpr->cp_ring_struct->fw_ring_id;
4221 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4223 if (++k == max_rings)
4226 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4229 HWRM_CHECK_RESULT();
4236 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4238 unsigned int rss_idx, fw_idx, i;
4240 if (!(vnic->rss_table && vnic->hash_type))
4243 if (BNXT_CHIP_THOR(bp))
4244 return bnxt_vnic_rss_configure_thor(bp, vnic);
4247 * Fill the RSS hash & redirection table with
4248 * ring group ids for all VNICs
4250 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4251 rss_idx++, fw_idx++) {
4252 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4253 fw_idx %= bp->rx_cp_nr_rings;
4254 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4258 if (i == bp->rx_cp_nr_rings)
4260 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4262 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4265 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4266 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4270 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4272 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4273 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4275 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4276 req->num_cmpl_dma_aggr_during_int =
4277 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4279 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4281 /* min timer set to 1/2 of interrupt timer */
4282 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4284 /* buf timer set to 1/4 of interrupt timer */
4285 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4287 req->cmpl_aggr_dma_tmr_during_int =
4288 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4290 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4291 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4292 req->flags = rte_cpu_to_le_16(flags);
4295 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4296 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4298 struct hwrm_ring_aggint_qcaps_input req = {0};
4299 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4304 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4305 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4306 HWRM_CHECK_RESULT();
4308 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4309 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4311 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4312 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4313 agg_req->flags = rte_cpu_to_le_16(flags);
4315 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4316 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4317 agg_req->enables = rte_cpu_to_le_32(enables);
4323 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4324 struct bnxt_coal *coal, uint16_t ring_id)
4326 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4327 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4328 bp->hwrm_cmd_resp_addr;
4331 /* Set ring coalesce parameters only for 100G NICs */
4332 if (BNXT_CHIP_THOR(bp)) {
4333 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4335 } else if (bnxt_stratus_device(bp)) {
4336 bnxt_hwrm_set_coal_params(coal, &req);
4341 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4342 req.ring_id = rte_cpu_to_le_16(ring_id);
4343 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4344 HWRM_CHECK_RESULT();
4349 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4350 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4352 struct hwrm_func_backing_store_qcaps_input req = {0};
4353 struct hwrm_func_backing_store_qcaps_output *resp =
4354 bp->hwrm_cmd_resp_addr;
4357 if (!BNXT_CHIP_THOR(bp) ||
4358 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4363 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4364 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4365 HWRM_CHECK_RESULT_SILENT();
4368 struct bnxt_ctx_pg_info *ctx_pg;
4369 struct bnxt_ctx_mem_info *ctx;
4370 int total_alloc_len;
4373 total_alloc_len = sizeof(*ctx);
4374 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4375 RTE_CACHE_LINE_SIZE);
4380 memset(ctx, 0, total_alloc_len);
4382 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4383 sizeof(*ctx_pg) * BNXT_MAX_Q,
4384 RTE_CACHE_LINE_SIZE);
4389 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4390 ctx->tqm_mem[i] = ctx_pg;
4393 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4394 ctx->qp_min_qp1_entries =
4395 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4396 ctx->qp_max_l2_entries =
4397 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4398 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4399 ctx->srq_max_l2_entries =
4400 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4401 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4402 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4403 ctx->cq_max_l2_entries =
4404 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4405 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4406 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4407 ctx->vnic_max_vnic_entries =
4408 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4409 ctx->vnic_max_ring_table_entries =
4410 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4411 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4412 ctx->stat_max_entries =
4413 rte_le_to_cpu_32(resp->stat_max_entries);
4414 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4415 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4416 ctx->tqm_min_entries_per_ring =
4417 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4418 ctx->tqm_max_entries_per_ring =
4419 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4420 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4421 if (!ctx->tqm_entries_multiple)
4422 ctx->tqm_entries_multiple = 1;
4423 ctx->mrav_max_entries =
4424 rte_le_to_cpu_32(resp->mrav_max_entries);
4425 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4426 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4427 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4436 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4438 struct hwrm_func_backing_store_cfg_input req = {0};
4439 struct hwrm_func_backing_store_cfg_output *resp =
4440 bp->hwrm_cmd_resp_addr;
4441 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4442 struct bnxt_ctx_pg_info *ctx_pg;
4443 uint32_t *num_entries;
4452 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4453 req.enables = rte_cpu_to_le_32(enables);
4455 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4456 ctx_pg = &ctx->qp_mem;
4457 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4458 req.qp_num_qp1_entries =
4459 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4460 req.qp_num_l2_entries =
4461 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4462 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4463 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4464 &req.qpc_pg_size_qpc_lvl,
4468 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4469 ctx_pg = &ctx->srq_mem;
4470 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4471 req.srq_num_l2_entries =
4472 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4473 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4474 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4475 &req.srq_pg_size_srq_lvl,
4479 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4480 ctx_pg = &ctx->cq_mem;
4481 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4482 req.cq_num_l2_entries =
4483 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4484 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4485 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4486 &req.cq_pg_size_cq_lvl,
4490 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4491 ctx_pg = &ctx->vnic_mem;
4492 req.vnic_num_vnic_entries =
4493 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4494 req.vnic_num_ring_table_entries =
4495 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4496 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4497 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4498 &req.vnic_pg_size_vnic_lvl,
4499 &req.vnic_page_dir);
4502 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4503 ctx_pg = &ctx->stat_mem;
4504 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4505 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4506 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4507 &req.stat_pg_size_stat_lvl,
4508 &req.stat_page_dir);
4511 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4512 num_entries = &req.tqm_sp_num_entries;
4513 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4514 pg_dir = &req.tqm_sp_page_dir;
4515 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4516 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4517 if (!(enables & ena))
4520 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4522 ctx_pg = ctx->tqm_mem[i];
4523 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4524 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4527 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4528 HWRM_CHECK_RESULT();
4534 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4536 struct hwrm_port_qstats_ext_input req = {0};
4537 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4538 struct bnxt_pf_info *pf = &bp->pf;
4541 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4542 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4545 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4547 req.port_id = rte_cpu_to_le_16(pf->port_id);
4548 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4549 req.tx_stat_host_addr =
4550 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4552 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4554 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4555 req.rx_stat_host_addr =
4556 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4558 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4563 bp->fw_rx_port_stats_ext_size = 0;
4564 bp->fw_tx_port_stats_ext_size = 0;
4566 bp->fw_rx_port_stats_ext_size =
4567 rte_le_to_cpu_16(resp->rx_stat_size);
4568 bp->fw_tx_port_stats_ext_size =
4569 rte_le_to_cpu_16(resp->tx_stat_size);
4572 HWRM_CHECK_RESULT();
4579 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4581 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4582 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4583 bp->hwrm_cmd_resp_addr;
4586 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4587 req.tunnel_type = type;
4588 req.dest_fid = bp->fw_fid;
4589 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4590 HWRM_CHECK_RESULT();
4598 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4600 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4601 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4602 bp->hwrm_cmd_resp_addr;
4605 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4606 req.tunnel_type = type;
4607 req.dest_fid = bp->fw_fid;
4608 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4609 HWRM_CHECK_RESULT();
4616 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4618 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4619 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4620 bp->hwrm_cmd_resp_addr;
4623 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4624 req.src_fid = bp->fw_fid;
4625 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4626 HWRM_CHECK_RESULT();
4629 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4636 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4639 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4640 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4641 bp->hwrm_cmd_resp_addr;
4644 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4645 req.src_fid = bp->fw_fid;
4646 req.tunnel_type = tun_type;
4647 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4648 HWRM_CHECK_RESULT();
4651 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4653 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4660 int bnxt_hwrm_set_mac(struct bnxt *bp)
4662 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4663 struct hwrm_func_vf_cfg_input req = {0};
4669 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4672 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4673 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4675 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4677 HWRM_CHECK_RESULT();
4679 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4685 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4687 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4688 struct hwrm_func_drv_if_change_input req = {0};
4692 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4695 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4696 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4697 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4699 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4702 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4706 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4708 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4710 HWRM_CHECK_RESULT();
4711 flags = rte_le_to_cpu_32(resp->flags);
4714 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4715 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4716 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4722 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4724 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4725 struct bnxt_error_recovery_info *info = bp->recovery_info;
4726 struct hwrm_error_recovery_qcfg_input req = {0};
4731 /* Older FW does not have error recovery support */
4732 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4736 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4738 bp->recovery_info = info;
4742 memset(info, 0, sizeof(*info));
4745 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4747 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4749 HWRM_CHECK_RESULT();
4751 flags = rte_le_to_cpu_32(resp->flags);
4752 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4753 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4754 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4755 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4757 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4758 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4763 /* FW returned values are in units of 100msec */
4764 info->driver_polling_freq =
4765 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4766 info->master_func_wait_period =
4767 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4768 info->normal_func_wait_period =
4769 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4770 info->master_func_wait_period_after_reset =
4771 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4772 info->max_bailout_time_after_reset =
4773 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4774 info->status_regs[BNXT_FW_STATUS_REG] =
4775 rte_le_to_cpu_32(resp->fw_health_status_reg);
4776 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4777 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4778 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4779 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4780 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4781 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4782 info->reg_array_cnt =
4783 rte_le_to_cpu_32(resp->reg_array_cnt);
4785 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4790 for (i = 0; i < info->reg_array_cnt; i++) {
4791 info->reset_reg[i] =
4792 rte_le_to_cpu_32(resp->reset_reg[i]);
4793 info->reset_reg_val[i] =
4794 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4795 info->delay_after_reset[i] =
4796 resp->delay_after_reset[i];
4801 /* Map the FW status registers */
4803 rc = bnxt_map_fw_health_status_regs(bp);
4806 rte_free(bp->recovery_info);
4807 bp->recovery_info = NULL;
4812 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4814 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4815 struct hwrm_fw_reset_input req = {0};
4821 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4823 req.embedded_proc_type =
4824 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4825 req.selfrst_status =
4826 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4827 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4829 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4832 HWRM_CHECK_RESULT();