1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(void *) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages > 1) {
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
103 /* For VER_GET command, set timeout as 50ms */
104 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
105 timeout = HWRM_CMD_TIMEOUT;
107 timeout = bp->hwrm_cmd_timeout;
109 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
110 msg_len > bp->max_req_len) {
111 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
113 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
114 memcpy(short_cmd_req, req, msg_len);
116 short_input.req_type = rte_cpu_to_le_16(req->req_type);
117 short_input.signature = rte_cpu_to_le_16(
118 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
119 short_input.size = rte_cpu_to_le_16(msg_len);
120 short_input.req_addr =
121 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
123 data = (uint32_t *)&short_input;
124 msg_len = sizeof(short_input);
126 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
129 /* Write request msg to hwrm channel */
130 for (i = 0; i < msg_len; i += 4) {
131 bar = (uint8_t *)bp->bar0 + bar_offset + i;
132 rte_write32(*data, bar);
136 /* Zero the rest of the request space */
137 for (; i < max_req_len; i += 4) {
138 bar = (uint8_t *)bp->bar0 + bar_offset + i;
142 /* Ring channel doorbell */
143 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
146 * Make sure the channel doorbell ring command complete before
147 * reading the response to avoid getting stale or invalid
152 /* Poll for the valid bit */
153 for (i = 0; i < timeout; i++) {
154 /* Sanity check on the resp->resp_len */
156 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
157 /* Last byte of resp contains the valid key */
158 valid = (uint8_t *)resp + resp->resp_len - 1;
159 if (*valid == HWRM_RESP_VALID_KEY)
166 /* Suppress VER_GET timeout messages during reset recovery */
167 if (bp->flags & BNXT_FLAG_FW_RESET &&
168 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
171 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
179 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
180 * spinlock, and does initial processing.
182 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
183 * releases the spinlock only if it returns. If the regular int return codes
184 * are not used by the function, HWRM_CHECK_RESULT() should not be used
185 * directly, rather it should be copied and modified to suit the function.
187 * HWRM_UNLOCK() must be called after all response processing is completed.
189 #define HWRM_PREP(req, type, kong) do { \
190 rte_spinlock_lock(&bp->hwrm_lock); \
191 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
192 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
193 req.cmpl_ring = rte_cpu_to_le_16(-1); \
194 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
195 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
196 req.target_id = rte_cpu_to_le_16(0xffff); \
197 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
200 #define HWRM_CHECK_RESULT_SILENT() do {\
202 rte_spinlock_unlock(&bp->hwrm_lock); \
205 if (resp->error_code) { \
206 rc = rte_le_to_cpu_16(resp->error_code); \
207 rte_spinlock_unlock(&bp->hwrm_lock); \
212 #define HWRM_CHECK_RESULT() do {\
214 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
215 rte_spinlock_unlock(&bp->hwrm_lock); \
216 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
218 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
220 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
222 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
228 if (resp->error_code) { \
229 rc = rte_le_to_cpu_16(resp->error_code); \
230 if (resp->resp_len >= 16) { \
231 struct hwrm_err_output *tmp_hwrm_err_op = \
234 "error %d:%d:%08x:%04x\n", \
235 rc, tmp_hwrm_err_op->cmd_err, \
237 tmp_hwrm_err_op->opaque_0), \
239 tmp_hwrm_err_op->opaque_1)); \
241 PMD_DRV_LOG(ERR, "error %d\n", rc); \
243 rte_spinlock_unlock(&bp->hwrm_lock); \
244 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
246 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
248 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
250 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
258 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
263 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
264 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
270 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
279 struct bnxt_vnic_info *vnic,
281 struct bnxt_vlan_table_entry *vlan_table)
284 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
285 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
288 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
291 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
292 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
294 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
295 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
296 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
297 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
299 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
300 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
302 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
303 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
304 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
305 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
306 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
307 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
310 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
311 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
312 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
313 rte_mem_virt2iova(vlan_table));
314 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
316 req.mask = rte_cpu_to_le_32(mask);
318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
328 struct bnxt_vlan_antispoof_table_entry *vlan_table)
331 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
332 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
333 bp->hwrm_cmd_resp_addr;
336 * Older HWRM versions did not support this command, and the set_rx_mask
337 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
338 * removed from set_rx_mask call, and this command was added.
340 * This command is also present from 1.7.8.11 and higher,
343 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
344 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
345 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
350 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
351 req.fid = rte_cpu_to_le_16(fid);
353 req.vlan_tag_mask_tbl_addr =
354 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
355 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
366 struct bnxt_filter_info *filter)
369 struct bnxt_filter_info *l2_filter = filter;
370 struct bnxt_vnic_info *vnic = NULL;
371 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
372 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
374 if (filter->fw_l2_filter_id == UINT64_MAX)
377 if (filter->matching_l2_fltr_ptr)
378 l2_filter = filter->matching_l2_fltr_ptr;
380 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
381 filter, l2_filter, l2_filter->l2_ref_cnt);
383 if (l2_filter->l2_ref_cnt == 0)
386 if (l2_filter->l2_ref_cnt > 0)
387 l2_filter->l2_ref_cnt--;
389 if (l2_filter->l2_ref_cnt > 0)
392 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
394 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
396 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
401 filter->fw_l2_filter_id = UINT64_MAX;
402 if (l2_filter->l2_ref_cnt == 0) {
403 vnic = l2_filter->vnic;
405 STAILQ_REMOVE(&vnic->filter, l2_filter,
406 bnxt_filter_info, next);
407 bnxt_free_filter(bp, l2_filter);
414 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
416 struct bnxt_filter_info *filter)
419 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
420 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
421 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
422 const struct rte_eth_vmdq_rx_conf *conf =
423 &dev_conf->rx_adv_conf.vmdq_rx_conf;
424 uint32_t enables = 0;
425 uint16_t j = dst_id - 1;
427 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
428 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
429 conf->pool_map[j].pools & (1UL << j)) {
431 "Add vlan %u to vmdq pool %u\n",
432 conf->pool_map[j].vlan_id, j);
434 filter->l2_ivlan = conf->pool_map[j].vlan_id;
436 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
437 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
440 if (filter->fw_l2_filter_id != UINT64_MAX)
441 bnxt_hwrm_clear_l2_filter(bp, filter);
443 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
445 req.flags = rte_cpu_to_le_32(filter->flags);
447 enables = filter->enables |
448 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
449 req.dst_id = rte_cpu_to_le_16(dst_id);
452 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
453 memcpy(req.l2_addr, filter->l2_addr,
456 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
457 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
460 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
461 req.l2_ovlan = filter->l2_ovlan;
463 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
464 req.l2_ivlan = filter->l2_ivlan;
466 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
467 req.l2_ovlan_mask = filter->l2_ovlan_mask;
469 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
470 req.l2_ivlan_mask = filter->l2_ivlan_mask;
471 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
472 req.src_id = rte_cpu_to_le_32(filter->src_id);
473 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
474 req.src_type = filter->src_type;
475 if (filter->pri_hint) {
476 req.pri_hint = filter->pri_hint;
477 req.l2_filter_id_hint =
478 rte_cpu_to_le_64(filter->l2_filter_id_hint);
481 req.enables = rte_cpu_to_le_32(enables);
483 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
487 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
493 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
495 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
496 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
503 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
506 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
509 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
510 if (ptp->tx_tstamp_en)
511 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
514 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
515 req.flags = rte_cpu_to_le_32(flags);
516 req.enables = rte_cpu_to_le_32
517 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
518 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
520 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
526 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
529 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
530 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
531 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
536 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
538 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
540 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
544 if (!BNXT_CHIP_THOR(bp) &&
545 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
548 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
549 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
551 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
555 if (!BNXT_CHIP_THOR(bp)) {
556 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
557 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
558 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
559 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
560 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
561 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
562 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
563 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
564 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
565 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
566 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
567 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
568 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
569 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
570 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
571 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
572 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
573 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
582 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
585 struct hwrm_func_qcaps_input req = {.req_type = 0 };
586 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
587 uint16_t new_max_vfs;
591 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
593 req.fid = rte_cpu_to_le_16(0xffff);
595 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
599 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
600 flags = rte_le_to_cpu_32(resp->flags);
602 bp->pf.port_id = resp->port_id;
603 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
604 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
605 new_max_vfs = bp->pdev->max_vfs;
606 if (new_max_vfs != bp->pf.max_vfs) {
608 rte_free(bp->pf.vf_info);
609 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
610 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
611 bp->pf.max_vfs = new_max_vfs;
612 for (i = 0; i < new_max_vfs; i++) {
613 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
614 bp->pf.vf_info[i].vlan_table =
615 rte_zmalloc("VF VLAN table",
618 if (bp->pf.vf_info[i].vlan_table == NULL)
620 "Fail to alloc VLAN table for VF %d\n",
624 bp->pf.vf_info[i].vlan_table);
625 bp->pf.vf_info[i].vlan_as_table =
626 rte_zmalloc("VF VLAN AS table",
629 if (bp->pf.vf_info[i].vlan_as_table == NULL)
631 "Alloc VLAN AS table for VF %d fail\n",
635 bp->pf.vf_info[i].vlan_as_table);
636 STAILQ_INIT(&bp->pf.vf_info[i].filter);
641 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
642 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
643 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
644 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
645 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
646 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
647 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
648 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
649 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
650 if (!BNXT_CHIP_THOR(bp))
651 bp->max_l2_ctx += bp->max_rx_em_flows;
652 /* TODO: For now, do not support VMDq/RFS on VFs. */
657 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
661 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
663 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
664 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
665 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
666 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
668 bnxt_hwrm_ptp_qcfg(bp);
672 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
673 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
675 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
676 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
677 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
680 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
681 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
683 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
684 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
691 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
695 rc = __bnxt_hwrm_func_qcaps(bp);
696 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
697 rc = bnxt_alloc_ctx_mem(bp);
701 rc = bnxt_hwrm_func_resc_qcaps(bp);
703 bp->flags |= BNXT_FLAG_NEW_RM;
707 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
708 * But the error can be ignored. Return success.
714 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
715 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
718 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
719 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
721 HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
723 req.target_id = rte_cpu_to_le_16(0xffff);
725 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
729 if (rte_le_to_cpu_32(resp->flags) &
730 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
731 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
732 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
735 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
742 int bnxt_hwrm_func_reset(struct bnxt *bp)
745 struct hwrm_func_reset_input req = {.req_type = 0 };
746 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
748 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
750 req.enables = rte_cpu_to_le_32(0);
752 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
760 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
764 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
765 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
767 if (bp->flags & BNXT_FLAG_REGISTERED)
770 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
771 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
772 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
773 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
775 /* PFs and trusted VFs should indicate the support of the
776 * Master capability on non Stingray platform
778 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
779 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
781 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
782 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
783 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
784 req.ver_maj = RTE_VER_YEAR;
785 req.ver_min = RTE_VER_MONTH;
786 req.ver_upd = RTE_VER_MINOR;
789 req.enables |= rte_cpu_to_le_32(
790 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
791 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
792 RTE_MIN(sizeof(req.vf_req_fwd),
793 sizeof(bp->pf.vf_req_fwd)));
796 * PF can sniff HWRM API issued by VF. This can be set up by
797 * linux driver and inherited by the DPDK PF driver. Clear
798 * this HWRM sniffer list in FW because DPDK PF driver does
801 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
804 req.flags = rte_cpu_to_le_32(flags);
806 req.async_event_fwd[0] |=
807 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
808 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
809 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
810 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
811 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
812 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
813 req.async_event_fwd[0] |=
814 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
815 req.async_event_fwd[1] |=
816 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
817 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
819 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
823 flags = rte_le_to_cpu_32(resp->flags);
824 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
825 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
829 bp->flags |= BNXT_FLAG_REGISTERED;
834 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
836 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
839 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
842 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
847 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
848 struct hwrm_func_vf_cfg_input req = {0};
850 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
852 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
853 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
854 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
855 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
856 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
858 if (BNXT_HAS_RING_GRPS(bp)) {
859 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
860 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
863 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
864 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
865 AGG_RING_MULTIPLIER);
866 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
867 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
869 BNXT_NUM_ASYNC_CPR(bp));
870 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
871 if (bp->vf_resv_strategy ==
872 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
873 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
874 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
875 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
876 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
877 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
878 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
879 } else if (bp->vf_resv_strategy ==
880 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
881 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
882 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
886 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
887 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
888 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
889 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
890 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
891 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
893 if (test && BNXT_HAS_RING_GRPS(bp))
894 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
896 req.flags = rte_cpu_to_le_32(flags);
897 req.enables |= rte_cpu_to_le_32(enables);
899 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
902 HWRM_CHECK_RESULT_SILENT();
910 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
913 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
914 struct hwrm_func_resource_qcaps_input req = {0};
916 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
917 req.fid = rte_cpu_to_le_16(0xffff);
919 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
921 HWRM_CHECK_RESULT_SILENT();
924 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
925 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
926 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
927 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
928 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
929 /* func_resource_qcaps does not return max_rx_em_flows.
930 * So use the value provided by func_qcaps.
932 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
933 if (!BNXT_CHIP_THOR(bp))
934 bp->max_l2_ctx += bp->max_rx_em_flows;
935 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
936 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
938 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
939 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
940 if (bp->vf_resv_strategy >
941 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
942 bp->vf_resv_strategy =
943 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
949 int bnxt_hwrm_ver_get(struct bnxt *bp)
952 struct hwrm_ver_get_input req = {.req_type = 0 };
953 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
955 uint16_t max_resp_len;
956 char type[RTE_MEMZONE_NAMESIZE];
957 uint32_t dev_caps_cfg;
959 bp->max_req_len = HWRM_MAX_REQ_LEN;
960 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
962 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
963 req.hwrm_intf_min = HWRM_VERSION_MINOR;
964 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
966 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
968 if (bp->flags & BNXT_FLAG_FW_RESET)
969 HWRM_CHECK_RESULT_SILENT();
973 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
974 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
975 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
976 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
977 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
978 (resp->hwrm_fw_min_8b << 16) |
979 (resp->hwrm_fw_bld_8b << 8) |
980 resp->hwrm_fw_rsvd_8b;
981 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
982 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
984 fw_version = resp->hwrm_intf_maj_8b << 16;
985 fw_version |= resp->hwrm_intf_min_8b << 8;
986 fw_version |= resp->hwrm_intf_upd_8b;
987 bp->hwrm_spec_code = fw_version;
989 /* def_req_timeout value is in milliseconds */
990 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
991 /* convert timeout to usec */
992 bp->hwrm_cmd_timeout *= 1000;
993 if (!bp->hwrm_cmd_timeout)
994 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
996 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
997 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1002 if (bp->max_req_len > resp->max_req_win_len) {
1003 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1006 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1007 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1008 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1009 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1011 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1012 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1014 if (bp->max_resp_len != max_resp_len) {
1015 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1016 bp->pdev->addr.domain, bp->pdev->addr.bus,
1017 bp->pdev->addr.devid, bp->pdev->addr.function);
1019 rte_free(bp->hwrm_cmd_resp_addr);
1021 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1022 if (bp->hwrm_cmd_resp_addr == NULL) {
1026 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1027 bp->hwrm_cmd_resp_dma_addr =
1028 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1029 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1031 "Unable to map response buffer to physical memory.\n");
1035 bp->max_resp_len = max_resp_len;
1039 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1041 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1042 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1043 bp->flags |= BNXT_FLAG_SHORT_CMD;
1046 if (((dev_caps_cfg &
1047 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1049 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1050 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1051 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1052 bp->pdev->addr.domain, bp->pdev->addr.bus,
1053 bp->pdev->addr.devid, bp->pdev->addr.function);
1055 rte_free(bp->hwrm_short_cmd_req_addr);
1057 bp->hwrm_short_cmd_req_addr =
1058 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1059 if (bp->hwrm_short_cmd_req_addr == NULL) {
1063 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1064 bp->hwrm_short_cmd_req_dma_addr =
1065 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1066 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1067 rte_free(bp->hwrm_short_cmd_req_addr);
1069 "Unable to map buffer to physical memory.\n");
1075 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1076 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1077 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1080 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1081 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1083 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1084 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1085 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1093 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1096 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1097 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1099 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1102 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1105 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1107 HWRM_CHECK_RESULT();
1113 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1116 struct hwrm_port_phy_cfg_input req = {0};
1117 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1118 uint32_t enables = 0;
1120 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1122 if (conf->link_up) {
1123 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1124 if (bp->link_info.auto_mode && conf->link_speed) {
1125 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1126 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1129 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1130 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1131 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1133 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1134 * any auto mode, even "none".
1136 if (!conf->link_speed) {
1137 /* No speeds specified. Enable AutoNeg - all speeds */
1139 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1141 /* AutoNeg - Advertise speeds specified. */
1142 if (conf->auto_link_speed_mask &&
1143 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1145 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1146 req.auto_link_speed_mask =
1147 conf->auto_link_speed_mask;
1149 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1152 req.auto_duplex = conf->duplex;
1153 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1154 req.auto_pause = conf->auto_pause;
1155 req.force_pause = conf->force_pause;
1156 /* Set force_pause if there is no auto or if there is a force */
1157 if (req.auto_pause && !req.force_pause)
1158 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1160 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1162 req.enables = rte_cpu_to_le_32(enables);
1165 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1166 PMD_DRV_LOG(INFO, "Force Link Down\n");
1169 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1171 HWRM_CHECK_RESULT();
1177 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1178 struct bnxt_link_info *link_info)
1181 struct hwrm_port_phy_qcfg_input req = {0};
1182 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1184 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1186 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1188 HWRM_CHECK_RESULT();
1190 link_info->phy_link_status = resp->link;
1191 link_info->link_up =
1192 (link_info->phy_link_status ==
1193 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1194 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1195 link_info->duplex = resp->duplex_cfg;
1196 link_info->pause = resp->pause;
1197 link_info->auto_pause = resp->auto_pause;
1198 link_info->force_pause = resp->force_pause;
1199 link_info->auto_mode = resp->auto_mode;
1200 link_info->phy_type = resp->phy_type;
1201 link_info->media_type = resp->media_type;
1203 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1204 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1205 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1206 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1207 link_info->phy_ver[0] = resp->phy_maj;
1208 link_info->phy_ver[1] = resp->phy_min;
1209 link_info->phy_ver[2] = resp->phy_bld;
1213 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1214 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1215 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1216 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1217 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1218 link_info->auto_link_speed_mask);
1219 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1220 link_info->force_link_speed);
1225 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1229 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1230 if (bp->tx_cos_queue[i].profile ==
1231 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1232 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1239 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1243 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1244 if (bp->tx_cos_queue[i].profile !=
1245 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1246 bp->tx_cos_queue[i].id !=
1247 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1248 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1254 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1257 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1258 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1259 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1263 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1265 req.flags = rte_cpu_to_le_32(dir);
1266 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1267 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1268 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1270 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1271 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1273 HWRM_CHECK_RESULT();
1275 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1276 GET_TX_QUEUE_INFO(0);
1277 GET_TX_QUEUE_INFO(1);
1278 GET_TX_QUEUE_INFO(2);
1279 GET_TX_QUEUE_INFO(3);
1280 GET_TX_QUEUE_INFO(4);
1281 GET_TX_QUEUE_INFO(5);
1282 GET_TX_QUEUE_INFO(6);
1283 GET_TX_QUEUE_INFO(7);
1285 GET_RX_QUEUE_INFO(0);
1286 GET_RX_QUEUE_INFO(1);
1287 GET_RX_QUEUE_INFO(2);
1288 GET_RX_QUEUE_INFO(3);
1289 GET_RX_QUEUE_INFO(4);
1290 GET_RX_QUEUE_INFO(5);
1291 GET_RX_QUEUE_INFO(6);
1292 GET_RX_QUEUE_INFO(7);
1297 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1300 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1301 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1305 /* iterate and find the COSq profile to use for Tx */
1306 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1307 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1308 if (bp->tx_cos_queue[i].id != 0xff)
1309 bp->tx_cosq_id[j++] =
1310 bp->tx_cos_queue[i].id;
1313 /* When CoS classification is disabled, for normal NIC
1314 * operations, ideally we should look to use LOSSY.
1315 * If not found, fallback to the first valid profile
1317 if (!bnxt_find_lossy_profile(bp))
1318 bnxt_find_first_valid_profile(bp);
1323 bp->max_tc = resp->max_configurable_queues;
1324 bp->max_lltc = resp->max_configurable_lossless_queues;
1325 if (bp->max_tc > BNXT_MAX_QUEUE)
1326 bp->max_tc = BNXT_MAX_QUEUE;
1327 bp->max_q = bp->max_tc;
1329 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1330 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1338 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1339 struct bnxt_ring *ring,
1340 uint32_t ring_type, uint32_t map_index,
1341 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1342 uint16_t tx_cosq_id)
1345 uint32_t enables = 0;
1346 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1347 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1348 struct rte_mempool *mb_pool;
1349 uint16_t rx_buf_size;
1351 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1353 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1354 req.fbo = rte_cpu_to_le_32(0);
1355 /* Association of ring index with doorbell index */
1356 req.logical_id = rte_cpu_to_le_16(map_index);
1357 req.length = rte_cpu_to_le_32(ring->ring_size);
1359 switch (ring_type) {
1360 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1361 req.ring_type = ring_type;
1362 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1363 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1364 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1365 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1367 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1369 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1370 req.ring_type = ring_type;
1371 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1372 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1373 if (BNXT_CHIP_THOR(bp)) {
1374 mb_pool = bp->rx_queues[0]->mb_pool;
1375 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1376 RTE_PKTMBUF_HEADROOM;
1377 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1378 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1380 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1382 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1384 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1386 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1387 req.ring_type = ring_type;
1388 if (BNXT_HAS_NQ(bp)) {
1389 /* Association of cp ring with nq */
1390 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1392 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1394 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1396 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1397 req.ring_type = ring_type;
1398 req.page_size = BNXT_PAGE_SHFT;
1399 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1401 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1402 req.ring_type = ring_type;
1403 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1405 mb_pool = bp->rx_queues[0]->mb_pool;
1406 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1407 RTE_PKTMBUF_HEADROOM;
1408 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1409 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1411 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1412 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1413 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1414 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1417 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1422 req.enables = rte_cpu_to_le_32(enables);
1424 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1426 if (rc || resp->error_code) {
1427 if (rc == 0 && resp->error_code)
1428 rc = rte_le_to_cpu_16(resp->error_code);
1429 switch (ring_type) {
1430 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1432 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1435 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1437 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1440 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1442 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1446 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1448 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1451 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1453 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1457 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1463 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1468 int bnxt_hwrm_ring_free(struct bnxt *bp,
1469 struct bnxt_ring *ring, uint32_t ring_type)
1472 struct hwrm_ring_free_input req = {.req_type = 0 };
1473 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1475 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1477 req.ring_type = ring_type;
1478 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1480 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1482 if (rc || resp->error_code) {
1483 if (rc == 0 && resp->error_code)
1484 rc = rte_le_to_cpu_16(resp->error_code);
1487 switch (ring_type) {
1488 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1489 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1492 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1493 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1496 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1497 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1500 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1502 "hwrm_ring_free nq failed. rc:%d\n", rc);
1504 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1506 "hwrm_ring_free agg failed. rc:%d\n", rc);
1509 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1517 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1520 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1521 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1523 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1525 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1526 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1527 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1528 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1530 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1532 HWRM_CHECK_RESULT();
1534 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1541 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1544 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1545 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1547 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1549 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1551 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1553 HWRM_CHECK_RESULT();
1556 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1560 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1563 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1564 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1566 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1569 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1571 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1573 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1575 HWRM_CHECK_RESULT();
1581 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1582 unsigned int idx __rte_unused)
1585 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1586 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1588 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1590 req.update_period_ms = rte_cpu_to_le_32(0);
1592 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1594 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1596 HWRM_CHECK_RESULT();
1598 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1605 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1606 unsigned int idx __rte_unused)
1609 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1610 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1612 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1614 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1616 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1618 HWRM_CHECK_RESULT();
1624 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1627 struct hwrm_vnic_alloc_input req = { 0 };
1628 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1630 if (!BNXT_HAS_RING_GRPS(bp))
1631 goto skip_ring_grps;
1633 /* map ring groups to this vnic */
1634 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1635 vnic->start_grp_id, vnic->end_grp_id);
1636 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1637 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1639 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1640 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1641 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1642 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1645 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1646 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1648 if (vnic->func_default)
1650 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1651 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1653 HWRM_CHECK_RESULT();
1655 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1657 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1661 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1662 struct bnxt_vnic_info *vnic,
1663 struct bnxt_plcmodes_cfg *pmode)
1666 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1667 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1669 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1671 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1673 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1675 HWRM_CHECK_RESULT();
1677 pmode->flags = rte_le_to_cpu_32(resp->flags);
1678 /* dflt_vnic bit doesn't exist in the _cfg command */
1679 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1680 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1681 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1682 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1689 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1690 struct bnxt_vnic_info *vnic,
1691 struct bnxt_plcmodes_cfg *pmode)
1694 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1695 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1697 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1698 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1702 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1704 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1705 req.flags = rte_cpu_to_le_32(pmode->flags);
1706 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1707 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1708 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1709 req.enables = rte_cpu_to_le_32(
1710 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1711 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1712 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1715 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1717 HWRM_CHECK_RESULT();
1723 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1726 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1727 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1728 struct bnxt_plcmodes_cfg pmodes = { 0 };
1729 uint32_t ctx_enable_flag = 0;
1730 uint32_t enables = 0;
1732 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1733 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1737 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1741 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1743 if (BNXT_CHIP_THOR(bp)) {
1744 int dflt_rxq = vnic->start_grp_id;
1745 struct bnxt_rx_ring_info *rxr;
1746 struct bnxt_cp_ring_info *cpr;
1747 struct bnxt_rx_queue *rxq;
1751 * The first active receive ring is used as the VNIC
1752 * default receive ring. If there are no active receive
1753 * rings (all corresponding receive queues are stopped),
1754 * the first receive ring is used.
1756 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1757 rxq = bp->eth_dev->data->rx_queues[i];
1758 if (rxq->rx_started) {
1764 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1768 req.default_rx_ring_id =
1769 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1770 req.default_cmpl_ring_id =
1771 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1772 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1773 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1777 /* Only RSS support for now TBD: COS & LB */
1778 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1779 if (vnic->lb_rule != 0xffff)
1780 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1781 if (vnic->cos_rule != 0xffff)
1782 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1783 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1784 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1785 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1787 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1788 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1789 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1792 enables |= ctx_enable_flag;
1793 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1794 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1795 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1796 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1799 req.enables = rte_cpu_to_le_32(enables);
1800 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1801 req.mru = rte_cpu_to_le_16(vnic->mru);
1802 /* Configure default VNIC only once. */
1803 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1805 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1806 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1808 if (vnic->vlan_strip)
1810 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1813 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1814 if (vnic->roce_dual)
1815 req.flags |= rte_cpu_to_le_32(
1816 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1817 if (vnic->roce_only)
1818 req.flags |= rte_cpu_to_le_32(
1819 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1820 if (vnic->rss_dflt_cr)
1821 req.flags |= rte_cpu_to_le_32(
1822 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1824 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1826 HWRM_CHECK_RESULT();
1829 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1834 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1838 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1839 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1841 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1842 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1845 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1848 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1849 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1850 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1852 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1854 HWRM_CHECK_RESULT();
1856 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1857 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1858 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1859 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1860 vnic->mru = rte_le_to_cpu_16(resp->mru);
1861 vnic->func_default = rte_le_to_cpu_32(
1862 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1863 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1864 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1865 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1866 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1867 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1868 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1869 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1870 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1871 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1872 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1879 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1880 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1884 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1885 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1886 bp->hwrm_cmd_resp_addr;
1888 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1890 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1891 HWRM_CHECK_RESULT();
1893 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1894 if (!BNXT_HAS_RING_GRPS(bp))
1895 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1896 else if (ctx_idx == 0)
1897 vnic->rss_rule = ctx_id;
1905 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1906 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1909 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1910 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1911 bp->hwrm_cmd_resp_addr;
1913 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1914 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1917 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1919 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1921 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1923 HWRM_CHECK_RESULT();
1929 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1933 if (BNXT_CHIP_THOR(bp)) {
1936 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1937 rc = _bnxt_hwrm_vnic_ctx_free(bp,
1939 vnic->fw_grp_ids[j]);
1940 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1942 vnic->num_lb_ctxts = 0;
1944 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1945 vnic->rss_rule = INVALID_HW_RING_ID;
1951 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1954 struct hwrm_vnic_free_input req = {.req_type = 0 };
1955 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1957 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1958 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1962 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1964 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1966 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1968 HWRM_CHECK_RESULT();
1971 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1972 /* Configure default VNIC again if necessary. */
1973 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1974 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1980 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1984 int nr_ctxs = vnic->num_lb_ctxts;
1985 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1986 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1988 for (i = 0; i < nr_ctxs; i++) {
1989 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1991 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1992 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1993 req.hash_mode_flags = vnic->hash_mode;
1995 req.hash_key_tbl_addr =
1996 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1998 req.ring_grp_tbl_addr =
1999 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2000 i * HW_HASH_INDEX_SIZE);
2001 req.ring_table_pair_index = i;
2002 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2004 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2007 HWRM_CHECK_RESULT();
2014 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2015 struct bnxt_vnic_info *vnic)
2018 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2019 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2021 if (!vnic->rss_table)
2024 if (BNXT_CHIP_THOR(bp))
2025 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2027 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2029 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2030 req.hash_mode_flags = vnic->hash_mode;
2032 req.ring_grp_tbl_addr =
2033 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2034 req.hash_key_tbl_addr =
2035 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2036 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2037 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2039 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2041 HWRM_CHECK_RESULT();
2047 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2048 struct bnxt_vnic_info *vnic)
2051 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2052 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2055 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2056 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2060 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2062 req.flags = rte_cpu_to_le_32(
2063 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2065 req.enables = rte_cpu_to_le_32(
2066 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2068 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2069 size -= RTE_PKTMBUF_HEADROOM;
2070 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2072 req.jumbo_thresh = rte_cpu_to_le_16(size);
2073 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2075 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2077 HWRM_CHECK_RESULT();
2083 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2084 struct bnxt_vnic_info *vnic, bool enable)
2087 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2088 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2090 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2092 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2096 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2097 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2101 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2104 req.enables = rte_cpu_to_le_32(
2105 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2106 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2107 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2108 req.flags = rte_cpu_to_le_32(
2109 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2110 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2111 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2112 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2113 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2114 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2115 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2116 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2117 req.min_agg_len = rte_cpu_to_le_32(512);
2119 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2121 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2123 HWRM_CHECK_RESULT();
2129 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2131 struct hwrm_func_cfg_input req = {0};
2132 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2135 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2136 req.enables = rte_cpu_to_le_32(
2137 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2138 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2139 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2141 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2143 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2144 HWRM_CHECK_RESULT();
2147 bp->pf.vf_info[vf].random_mac = false;
2152 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2156 struct hwrm_func_qstats_input req = {.req_type = 0};
2157 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2159 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2161 req.fid = rte_cpu_to_le_16(fid);
2163 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2165 HWRM_CHECK_RESULT();
2168 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2175 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2176 struct rte_eth_stats *stats)
2179 struct hwrm_func_qstats_input req = {.req_type = 0};
2180 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2182 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2184 req.fid = rte_cpu_to_le_16(fid);
2186 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2188 HWRM_CHECK_RESULT();
2190 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2191 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2192 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2193 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2194 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2195 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2197 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2198 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2199 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2200 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2201 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2202 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2204 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2205 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2206 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2213 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2216 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2217 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2219 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2221 req.fid = rte_cpu_to_le_16(fid);
2223 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2225 HWRM_CHECK_RESULT();
2231 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2236 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2237 struct bnxt_tx_queue *txq;
2238 struct bnxt_rx_queue *rxq;
2239 struct bnxt_cp_ring_info *cpr;
2241 if (i >= bp->rx_cp_nr_rings) {
2242 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2245 rxq = bp->rx_queues[i];
2249 rc = bnxt_hwrm_stat_clear(bp, cpr);
2256 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2260 struct bnxt_cp_ring_info *cpr;
2262 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2264 if (i >= bp->rx_cp_nr_rings) {
2265 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2267 cpr = bp->rx_queues[i]->cp_ring;
2268 if (BNXT_HAS_RING_GRPS(bp))
2269 bp->grp_info[i].fw_stats_ctx = -1;
2271 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2272 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2273 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2281 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2286 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2287 struct bnxt_tx_queue *txq;
2288 struct bnxt_rx_queue *rxq;
2289 struct bnxt_cp_ring_info *cpr;
2291 if (i >= bp->rx_cp_nr_rings) {
2292 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2295 rxq = bp->rx_queues[i];
2299 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2307 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2312 if (!BNXT_HAS_RING_GRPS(bp))
2315 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2317 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2320 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2328 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2330 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2332 bnxt_hwrm_ring_free(bp, cp_ring,
2333 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2334 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2335 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2336 sizeof(*cpr->cp_desc_ring));
2337 cpr->cp_raw_cons = 0;
2341 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2343 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2345 bnxt_hwrm_ring_free(bp, cp_ring,
2346 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2347 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2348 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2349 sizeof(*cpr->cp_desc_ring));
2350 cpr->cp_raw_cons = 0;
2354 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2356 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2357 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2358 struct bnxt_ring *ring = rxr->rx_ring_struct;
2359 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2361 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2362 bnxt_hwrm_ring_free(bp, ring,
2363 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2364 ring->fw_ring_id = INVALID_HW_RING_ID;
2365 if (BNXT_HAS_RING_GRPS(bp))
2366 bp->grp_info[queue_index].rx_fw_ring_id =
2368 memset(rxr->rx_desc_ring, 0,
2369 rxr->rx_ring_struct->ring_size *
2370 sizeof(*rxr->rx_desc_ring));
2371 memset(rxr->rx_buf_ring, 0,
2372 rxr->rx_ring_struct->ring_size *
2373 sizeof(*rxr->rx_buf_ring));
2376 ring = rxr->ag_ring_struct;
2377 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2378 bnxt_hwrm_ring_free(bp, ring,
2379 BNXT_CHIP_THOR(bp) ?
2380 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2381 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2382 ring->fw_ring_id = INVALID_HW_RING_ID;
2383 memset(rxr->ag_buf_ring, 0,
2384 rxr->ag_ring_struct->ring_size *
2385 sizeof(*rxr->ag_buf_ring));
2387 if (BNXT_HAS_RING_GRPS(bp))
2388 bp->grp_info[queue_index].ag_fw_ring_id =
2391 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2392 bnxt_free_cp_ring(bp, cpr);
2394 if (BNXT_HAS_RING_GRPS(bp))
2395 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2398 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2402 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2403 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2404 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2405 struct bnxt_ring *ring = txr->tx_ring_struct;
2406 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2408 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2409 bnxt_hwrm_ring_free(bp, ring,
2410 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2411 ring->fw_ring_id = INVALID_HW_RING_ID;
2412 memset(txr->tx_desc_ring, 0,
2413 txr->tx_ring_struct->ring_size *
2414 sizeof(*txr->tx_desc_ring));
2415 memset(txr->tx_buf_ring, 0,
2416 txr->tx_ring_struct->ring_size *
2417 sizeof(*txr->tx_buf_ring));
2421 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2422 bnxt_free_cp_ring(bp, cpr);
2423 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2427 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2428 bnxt_free_hwrm_rx_ring(bp, i);
2433 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2438 if (!BNXT_HAS_RING_GRPS(bp))
2441 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2442 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2450 * HWRM utility functions
2453 void bnxt_free_hwrm_resources(struct bnxt *bp)
2455 /* Release memzone */
2456 rte_free(bp->hwrm_cmd_resp_addr);
2457 rte_free(bp->hwrm_short_cmd_req_addr);
2458 bp->hwrm_cmd_resp_addr = NULL;
2459 bp->hwrm_short_cmd_req_addr = NULL;
2460 bp->hwrm_cmd_resp_dma_addr = 0;
2461 bp->hwrm_short_cmd_req_dma_addr = 0;
2464 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2466 struct rte_pci_device *pdev = bp->pdev;
2467 char type[RTE_MEMZONE_NAMESIZE];
2469 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2470 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2471 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2472 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2473 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2474 if (bp->hwrm_cmd_resp_addr == NULL)
2476 bp->hwrm_cmd_resp_dma_addr =
2477 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2478 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2480 "unable to map response address to physical memory\n");
2483 rte_spinlock_init(&bp->hwrm_lock);
2488 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2490 struct bnxt_filter_info *filter;
2493 STAILQ_FOREACH(filter, &vnic->filter, next) {
2494 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2495 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2496 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2497 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2498 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2499 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2500 bnxt_free_filter(bp, filter);
2506 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2508 struct bnxt_filter_info *filter;
2509 struct rte_flow *flow;
2512 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2513 flow = STAILQ_FIRST(&vnic->flow_list);
2514 filter = flow->filter;
2515 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2516 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2517 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2518 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2519 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2520 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2522 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2528 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2530 struct bnxt_filter_info *filter;
2533 STAILQ_FOREACH(filter, &vnic->filter, next) {
2534 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2535 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2537 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2538 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2541 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2549 void bnxt_free_tunnel_ports(struct bnxt *bp)
2551 if (bp->vxlan_port_cnt)
2552 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2553 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2555 if (bp->geneve_port_cnt)
2556 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2557 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2558 bp->geneve_port = 0;
2561 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2565 if (bp->vnic_info == NULL)
2569 * Cleanup VNICs in reverse order, to make sure the L2 filter
2570 * from vnic0 is last to be cleaned up.
2572 for (i = bp->max_vnics - 1; i >= 0; i--) {
2573 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2575 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2578 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2580 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2582 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2584 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2586 bnxt_hwrm_vnic_free(bp, vnic);
2588 rte_free(vnic->fw_grp_ids);
2590 /* Ring resources */
2591 bnxt_free_all_hwrm_rings(bp);
2592 bnxt_free_all_hwrm_ring_grps(bp);
2593 bnxt_free_all_hwrm_stat_ctxs(bp);
2594 bnxt_free_tunnel_ports(bp);
2597 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2599 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2601 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2602 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2604 switch (conf_link_speed) {
2605 case ETH_LINK_SPEED_10M_HD:
2606 case ETH_LINK_SPEED_100M_HD:
2608 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2610 return hw_link_duplex;
2613 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2615 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2618 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2620 uint16_t eth_link_speed = 0;
2622 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2623 return ETH_LINK_SPEED_AUTONEG;
2625 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2626 case ETH_LINK_SPEED_100M:
2627 case ETH_LINK_SPEED_100M_HD:
2630 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2632 case ETH_LINK_SPEED_1G:
2634 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2636 case ETH_LINK_SPEED_2_5G:
2638 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2640 case ETH_LINK_SPEED_10G:
2642 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2644 case ETH_LINK_SPEED_20G:
2646 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2648 case ETH_LINK_SPEED_25G:
2650 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2652 case ETH_LINK_SPEED_40G:
2654 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2656 case ETH_LINK_SPEED_50G:
2658 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2660 case ETH_LINK_SPEED_100G:
2662 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2666 "Unsupported link speed %d; default to AUTO\n",
2670 return eth_link_speed;
2673 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2674 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2675 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2676 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2678 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2682 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2685 if (link_speed & ETH_LINK_SPEED_FIXED) {
2686 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2688 if (one_speed & (one_speed - 1)) {
2690 "Invalid advertised speeds (%u) for port %u\n",
2691 link_speed, port_id);
2694 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2696 "Unsupported advertised speed (%u) for port %u\n",
2697 link_speed, port_id);
2701 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2703 "Unsupported advertised speeds (%u) for port %u\n",
2704 link_speed, port_id);
2712 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2716 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2717 if (bp->link_info.support_speeds)
2718 return bp->link_info.support_speeds;
2719 link_speed = BNXT_SUPPORTED_SPEEDS;
2722 if (link_speed & ETH_LINK_SPEED_100M)
2723 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2724 if (link_speed & ETH_LINK_SPEED_100M_HD)
2725 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2726 if (link_speed & ETH_LINK_SPEED_1G)
2727 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2728 if (link_speed & ETH_LINK_SPEED_2_5G)
2729 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2730 if (link_speed & ETH_LINK_SPEED_10G)
2731 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2732 if (link_speed & ETH_LINK_SPEED_20G)
2733 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2734 if (link_speed & ETH_LINK_SPEED_25G)
2735 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2736 if (link_speed & ETH_LINK_SPEED_40G)
2737 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2738 if (link_speed & ETH_LINK_SPEED_50G)
2739 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2740 if (link_speed & ETH_LINK_SPEED_100G)
2741 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2745 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2747 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2749 switch (hw_link_speed) {
2750 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2751 eth_link_speed = ETH_SPEED_NUM_100M;
2753 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2754 eth_link_speed = ETH_SPEED_NUM_1G;
2756 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2757 eth_link_speed = ETH_SPEED_NUM_2_5G;
2759 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2760 eth_link_speed = ETH_SPEED_NUM_10G;
2762 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2763 eth_link_speed = ETH_SPEED_NUM_20G;
2765 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2766 eth_link_speed = ETH_SPEED_NUM_25G;
2768 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2769 eth_link_speed = ETH_SPEED_NUM_40G;
2771 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2772 eth_link_speed = ETH_SPEED_NUM_50G;
2774 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2775 eth_link_speed = ETH_SPEED_NUM_100G;
2777 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2779 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2783 return eth_link_speed;
2786 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2788 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2790 switch (hw_link_duplex) {
2791 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2792 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2794 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2796 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2797 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2800 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2804 return eth_link_duplex;
2807 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2810 struct bnxt_link_info *link_info = &bp->link_info;
2812 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2815 "Get link config failed with rc %d\n", rc);
2818 if (link_info->link_speed)
2820 bnxt_parse_hw_link_speed(link_info->link_speed);
2822 link->link_speed = ETH_SPEED_NUM_NONE;
2823 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2824 link->link_status = link_info->link_up;
2825 link->link_autoneg = link_info->auto_mode ==
2826 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2827 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2832 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2835 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2836 struct bnxt_link_info link_req;
2837 uint16_t speed, autoneg;
2839 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2842 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2843 bp->eth_dev->data->port_id);
2847 memset(&link_req, 0, sizeof(link_req));
2848 link_req.link_up = link_up;
2852 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2853 if (BNXT_CHIP_THOR(bp) &&
2854 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2855 /* 40G is not supported as part of media auto detect.
2856 * The speed should be forced and autoneg disabled
2857 * to configure 40G speed.
2859 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2863 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2864 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2865 /* Autoneg can be done only when the FW allows.
2866 * When user configures fixed speed of 40G and later changes to
2867 * any other speed, auto_link_speed/force_link_speed is still set
2868 * to 40G until link comes up at new speed.
2871 !(!BNXT_CHIP_THOR(bp) &&
2872 (bp->link_info.auto_link_speed ||
2873 bp->link_info.force_link_speed))) {
2874 link_req.phy_flags |=
2875 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2876 link_req.auto_link_speed_mask =
2877 bnxt_parse_eth_link_speed_mask(bp,
2878 dev_conf->link_speeds);
2880 if (bp->link_info.phy_type ==
2881 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2882 bp->link_info.phy_type ==
2883 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2884 bp->link_info.media_type ==
2885 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2886 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2890 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2891 /* If user wants a particular speed try that first. */
2893 link_req.link_speed = speed;
2894 else if (bp->link_info.force_link_speed)
2895 link_req.link_speed = bp->link_info.force_link_speed;
2897 link_req.link_speed = bp->link_info.auto_link_speed;
2899 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2900 link_req.auto_pause = bp->link_info.auto_pause;
2901 link_req.force_pause = bp->link_info.force_pause;
2904 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2907 "Set link config failed with rc %d\n", rc);
2915 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2917 struct hwrm_func_qcfg_input req = {0};
2918 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2922 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2923 req.fid = rte_cpu_to_le_16(0xffff);
2925 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2927 HWRM_CHECK_RESULT();
2929 /* Hard Coded.. 0xfff VLAN ID mask */
2930 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2931 flags = rte_le_to_cpu_16(resp->flags);
2932 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2933 bp->flags |= BNXT_FLAG_MULTI_HOST;
2936 !BNXT_VF_IS_TRUSTED(bp) &&
2937 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2938 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2939 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2940 } else if (BNXT_VF(bp) &&
2941 BNXT_VF_IS_TRUSTED(bp) &&
2942 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2943 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2944 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2948 *mtu = rte_le_to_cpu_16(resp->mtu);
2950 switch (resp->port_partition_type) {
2951 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2952 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2953 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2955 bp->port_partition_type = resp->port_partition_type;
2958 bp->port_partition_type = 0;
2967 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2968 struct hwrm_func_qcaps_output *qcaps)
2970 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2971 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2972 sizeof(qcaps->mac_address));
2973 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2974 qcaps->max_rx_rings = fcfg->num_rx_rings;
2975 qcaps->max_tx_rings = fcfg->num_tx_rings;
2976 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2977 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2979 qcaps->first_vf_id = 0;
2980 qcaps->max_vnics = fcfg->num_vnics;
2981 qcaps->max_decap_records = 0;
2982 qcaps->max_encap_records = 0;
2983 qcaps->max_tx_wm_flows = 0;
2984 qcaps->max_tx_em_flows = 0;
2985 qcaps->max_rx_wm_flows = 0;
2986 qcaps->max_rx_em_flows = 0;
2987 qcaps->max_flow_id = 0;
2988 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2989 qcaps->max_sp_tx_rings = 0;
2990 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2993 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2995 struct hwrm_func_cfg_input req = {0};
2996 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3000 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3001 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3002 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3003 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3004 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3005 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3006 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3007 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3008 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3010 if (BNXT_HAS_RING_GRPS(bp)) {
3011 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3012 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3013 } else if (BNXT_HAS_NQ(bp)) {
3014 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3015 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3018 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3019 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3020 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3021 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3022 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3023 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3024 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3025 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3026 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3027 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3028 req.fid = rte_cpu_to_le_16(0xffff);
3029 req.enables = rte_cpu_to_le_32(enables);
3031 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3033 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3035 HWRM_CHECK_RESULT();
3041 static void populate_vf_func_cfg_req(struct bnxt *bp,
3042 struct hwrm_func_cfg_input *req,
3045 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3046 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3047 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3048 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3049 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3050 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3051 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3052 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3053 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3054 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3056 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3057 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3059 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3060 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3062 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3063 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3065 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3066 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3067 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3068 /* TODO: For now, do not support VMDq/RFS on VFs. */
3069 req->num_vnics = rte_cpu_to_le_16(1);
3070 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3074 static void add_random_mac_if_needed(struct bnxt *bp,
3075 struct hwrm_func_cfg_input *cfg_req,
3078 struct rte_ether_addr mac;
3080 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3083 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3085 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3086 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3087 bp->pf.vf_info[vf].random_mac = true;
3089 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3090 RTE_ETHER_ADDR_LEN);
3094 static void reserve_resources_from_vf(struct bnxt *bp,
3095 struct hwrm_func_cfg_input *cfg_req,
3098 struct hwrm_func_qcaps_input req = {0};
3099 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3102 /* Get the actual allocated values now */
3103 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3104 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3105 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3108 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3109 copy_func_cfg_to_qcaps(cfg_req, resp);
3110 } else if (resp->error_code) {
3111 rc = rte_le_to_cpu_16(resp->error_code);
3112 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3113 copy_func_cfg_to_qcaps(cfg_req, resp);
3116 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3117 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3118 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3119 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3120 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3121 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3123 * TODO: While not supporting VMDq with VFs, max_vnics is always
3124 * forced to 1 in this case
3126 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3127 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3132 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3134 struct hwrm_func_qcfg_input req = {0};
3135 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3138 /* Check for zero MAC address */
3139 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3140 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3141 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3142 HWRM_CHECK_RESULT();
3143 rc = rte_le_to_cpu_16(resp->vlan);
3150 static int update_pf_resource_max(struct bnxt *bp)
3152 struct hwrm_func_qcfg_input req = {0};
3153 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3156 /* And copy the allocated numbers into the pf struct */
3157 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3158 req.fid = rte_cpu_to_le_16(0xffff);
3159 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3160 HWRM_CHECK_RESULT();
3162 /* Only TX ring value reflects actual allocation? TODO */
3163 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3164 bp->pf.evb_mode = resp->evb_mode;
3171 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3176 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3180 rc = bnxt_hwrm_func_qcaps(bp);
3184 bp->pf.func_cfg_flags &=
3185 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3186 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3187 bp->pf.func_cfg_flags |=
3188 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3189 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3190 rc = __bnxt_hwrm_func_qcaps(bp);
3194 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3196 struct hwrm_func_cfg_input req = {0};
3197 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3204 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3208 rc = bnxt_hwrm_func_qcaps(bp);
3213 bp->pf.active_vfs = num_vfs;
3216 * First, configure the PF to only use one TX ring. This ensures that
3217 * there are enough rings for all VFs.
3219 * If we don't do this, when we call func_alloc() later, we will lock
3220 * extra rings to the PF that won't be available during func_cfg() of
3223 * This has been fixed with firmware versions above 20.6.54
3225 bp->pf.func_cfg_flags &=
3226 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3227 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3228 bp->pf.func_cfg_flags |=
3229 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3230 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3235 * Now, create and register a buffer to hold forwarded VF requests
3237 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3238 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3239 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3240 if (bp->pf.vf_req_buf == NULL) {
3244 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3245 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3246 for (i = 0; i < num_vfs; i++)
3247 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3248 (i * HWRM_MAX_REQ_LEN);
3250 rc = bnxt_hwrm_func_buf_rgtr(bp);
3254 populate_vf_func_cfg_req(bp, &req, num_vfs);
3256 bp->pf.active_vfs = 0;
3257 for (i = 0; i < num_vfs; i++) {
3258 add_random_mac_if_needed(bp, &req, i);
3260 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3261 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3262 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3263 rc = bnxt_hwrm_send_message(bp,
3268 /* Clear enable flag for next pass */
3269 req.enables &= ~rte_cpu_to_le_32(
3270 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3272 if (rc || resp->error_code) {
3274 "Failed to initizlie VF %d\n", i);
3276 "Not all VFs available. (%d, %d)\n",
3277 rc, resp->error_code);
3284 reserve_resources_from_vf(bp, &req, i);
3285 bp->pf.active_vfs++;
3286 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3290 * Now configure the PF to use "the rest" of the resources
3291 * We're using STD_TX_RING_MODE here though which will limit the TX
3292 * rings. This will allow QoS to function properly. Not setting this
3293 * will cause PF rings to break bandwidth settings.
3295 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3299 rc = update_pf_resource_max(bp);
3306 bnxt_hwrm_func_buf_unrgtr(bp);
3310 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3312 struct hwrm_func_cfg_input req = {0};
3313 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3316 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3318 req.fid = rte_cpu_to_le_16(0xffff);
3319 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3320 req.evb_mode = bp->pf.evb_mode;
3322 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3323 HWRM_CHECK_RESULT();
3329 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3330 uint8_t tunnel_type)
3332 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3333 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3336 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3337 req.tunnel_type = tunnel_type;
3338 req.tunnel_dst_port_val = port;
3339 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3340 HWRM_CHECK_RESULT();
3342 switch (tunnel_type) {
3343 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3344 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3345 bp->vxlan_port = port;
3347 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3348 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3349 bp->geneve_port = port;
3360 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3361 uint8_t tunnel_type)
3363 struct hwrm_tunnel_dst_port_free_input req = {0};
3364 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3367 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3369 req.tunnel_type = tunnel_type;
3370 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3371 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3373 HWRM_CHECK_RESULT();
3379 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3382 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3383 struct hwrm_func_cfg_input req = {0};
3386 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3388 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3389 req.flags = rte_cpu_to_le_32(flags);
3390 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3392 HWRM_CHECK_RESULT();
3398 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3400 uint32_t *flag = flagp;
3402 vnic->flags = *flag;
3405 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3407 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3410 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3413 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3414 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3416 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3418 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3419 req.req_buf_page_size = rte_cpu_to_le_16(
3420 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3421 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3422 req.req_buf_page_addr0 =
3423 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3424 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3426 "unable to map buffer address to physical memory\n");
3430 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3432 HWRM_CHECK_RESULT();
3438 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3441 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3442 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3444 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3447 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3449 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3451 HWRM_CHECK_RESULT();
3457 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3459 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3460 struct hwrm_func_cfg_input req = {0};
3463 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3465 req.fid = rte_cpu_to_le_16(0xffff);
3466 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3467 req.enables = rte_cpu_to_le_32(
3468 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3469 req.async_event_cr = rte_cpu_to_le_16(
3470 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3471 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3473 HWRM_CHECK_RESULT();
3479 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3481 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3482 struct hwrm_func_vf_cfg_input req = {0};
3485 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3487 req.enables = rte_cpu_to_le_32(
3488 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3489 req.async_event_cr = rte_cpu_to_le_16(
3490 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3493 HWRM_CHECK_RESULT();
3499 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3501 struct hwrm_func_cfg_input req = {0};
3502 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3503 uint16_t dflt_vlan, fid;
3504 uint32_t func_cfg_flags;
3507 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3510 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3511 fid = bp->pf.vf_info[vf].fid;
3512 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3514 fid = rte_cpu_to_le_16(0xffff);
3515 func_cfg_flags = bp->pf.func_cfg_flags;
3516 dflt_vlan = bp->vlan;
3519 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3520 req.fid = rte_cpu_to_le_16(fid);
3521 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3522 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3524 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3526 HWRM_CHECK_RESULT();
3532 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3533 uint16_t max_bw, uint16_t enables)
3535 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3536 struct hwrm_func_cfg_input req = {0};
3539 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3541 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3542 req.enables |= rte_cpu_to_le_32(enables);
3543 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3544 req.max_bw = rte_cpu_to_le_32(max_bw);
3545 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3547 HWRM_CHECK_RESULT();
3553 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3555 struct hwrm_func_cfg_input req = {0};
3556 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3559 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3561 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3562 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3563 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3564 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3566 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3568 HWRM_CHECK_RESULT();
3574 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3579 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3581 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3586 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3587 void *encaped, size_t ec_size)
3590 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3591 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3593 if (ec_size > sizeof(req.encap_request))
3596 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3598 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3599 memcpy(req.encap_request, encaped, ec_size);
3601 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3603 HWRM_CHECK_RESULT();
3609 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3610 struct rte_ether_addr *mac)
3612 struct hwrm_func_qcfg_input req = {0};
3613 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3616 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3618 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3619 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3621 HWRM_CHECK_RESULT();
3623 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3630 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3631 void *encaped, size_t ec_size)
3634 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3635 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3637 if (ec_size > sizeof(req.encap_request))
3640 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3642 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3643 memcpy(req.encap_request, encaped, ec_size);
3645 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3647 HWRM_CHECK_RESULT();
3653 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3654 struct rte_eth_stats *stats, uint8_t rx)
3657 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3658 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3660 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3662 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3664 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3666 HWRM_CHECK_RESULT();
3669 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3670 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3671 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3672 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3673 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3674 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3675 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3676 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3678 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3679 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3680 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3681 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3682 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3683 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3691 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3693 struct hwrm_port_qstats_input req = {0};
3694 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3695 struct bnxt_pf_info *pf = &bp->pf;
3698 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3700 req.port_id = rte_cpu_to_le_16(pf->port_id);
3701 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3702 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3703 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3705 HWRM_CHECK_RESULT();
3711 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3713 struct hwrm_port_clr_stats_input req = {0};
3714 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3715 struct bnxt_pf_info *pf = &bp->pf;
3718 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3719 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3720 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3723 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3725 req.port_id = rte_cpu_to_le_16(pf->port_id);
3726 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3728 HWRM_CHECK_RESULT();
3734 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3736 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3737 struct hwrm_port_led_qcaps_input req = {0};
3743 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3744 req.port_id = bp->pf.port_id;
3745 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3747 HWRM_CHECK_RESULT();
3749 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3752 bp->num_leds = resp->num_leds;
3753 memcpy(bp->leds, &resp->led0_id,
3754 sizeof(bp->leds[0]) * bp->num_leds);
3755 for (i = 0; i < bp->num_leds; i++) {
3756 struct bnxt_led_info *led = &bp->leds[i];
3758 uint16_t caps = led->led_state_caps;
3760 if (!led->led_group_id ||
3761 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3773 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3775 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3776 struct hwrm_port_led_cfg_input req = {0};
3777 struct bnxt_led_cfg *led_cfg;
3778 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3779 uint16_t duration = 0;
3782 if (!bp->num_leds || BNXT_VF(bp))
3785 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3788 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3789 duration = rte_cpu_to_le_16(500);
3791 req.port_id = bp->pf.port_id;
3792 req.num_leds = bp->num_leds;
3793 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3794 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3795 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3796 led_cfg->led_id = bp->leds[i].led_id;
3797 led_cfg->led_state = led_state;
3798 led_cfg->led_blink_on = duration;
3799 led_cfg->led_blink_off = duration;
3800 led_cfg->led_group_id = bp->leds[i].led_group_id;
3803 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3805 HWRM_CHECK_RESULT();
3811 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3815 struct hwrm_nvm_get_dir_info_input req = {0};
3816 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3818 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3820 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3822 HWRM_CHECK_RESULT();
3824 *entries = rte_le_to_cpu_32(resp->entries);
3825 *length = rte_le_to_cpu_32(resp->entry_length);
3831 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3834 uint32_t dir_entries;
3835 uint32_t entry_length;
3838 rte_iova_t dma_handle;
3839 struct hwrm_nvm_get_dir_entries_input req = {0};
3840 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3842 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3846 *data++ = dir_entries;
3847 *data++ = entry_length;
3849 memset(data, 0xff, len);
3851 buflen = dir_entries * entry_length;
3852 buf = rte_malloc("nvm_dir", buflen, 0);
3853 rte_mem_lock_page(buf);
3856 dma_handle = rte_mem_virt2iova(buf);
3857 if (dma_handle == RTE_BAD_IOVA) {
3859 "unable to map response address to physical memory\n");
3862 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3863 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3864 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3867 memcpy(data, buf, len > buflen ? buflen : len);
3870 HWRM_CHECK_RESULT();
3876 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3877 uint32_t offset, uint32_t length,
3882 rte_iova_t dma_handle;
3883 struct hwrm_nvm_read_input req = {0};
3884 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3886 buf = rte_malloc("nvm_item", length, 0);
3887 rte_mem_lock_page(buf);
3891 dma_handle = rte_mem_virt2iova(buf);
3892 if (dma_handle == RTE_BAD_IOVA) {
3894 "unable to map response address to physical memory\n");
3897 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3898 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3899 req.dir_idx = rte_cpu_to_le_16(index);
3900 req.offset = rte_cpu_to_le_32(offset);
3901 req.len = rte_cpu_to_le_32(length);
3902 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3904 memcpy(data, buf, length);
3907 HWRM_CHECK_RESULT();
3913 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3916 struct hwrm_nvm_erase_dir_entry_input req = {0};
3917 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3919 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3920 req.dir_idx = rte_cpu_to_le_16(index);
3921 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3922 HWRM_CHECK_RESULT();
3929 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3930 uint16_t dir_ordinal, uint16_t dir_ext,
3931 uint16_t dir_attr, const uint8_t *data,
3935 struct hwrm_nvm_write_input req = {0};
3936 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3937 rte_iova_t dma_handle;
3940 buf = rte_malloc("nvm_write", data_len, 0);
3941 rte_mem_lock_page(buf);
3945 dma_handle = rte_mem_virt2iova(buf);
3946 if (dma_handle == RTE_BAD_IOVA) {
3948 "unable to map response address to physical memory\n");
3951 memcpy(buf, data, data_len);
3953 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3955 req.dir_type = rte_cpu_to_le_16(dir_type);
3956 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3957 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3958 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3959 req.dir_data_length = rte_cpu_to_le_32(data_len);
3960 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3962 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3965 HWRM_CHECK_RESULT();
3972 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3974 uint32_t *count = cbdata;
3976 *count = *count + 1;
3979 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3980 struct bnxt_vnic_info *vnic __rte_unused)
3985 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3989 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3990 &count, bnxt_vnic_count_hwrm_stub);
3995 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3998 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3999 struct hwrm_func_vf_vnic_ids_query_output *resp =
4000 bp->hwrm_cmd_resp_addr;
4003 /* First query all VNIC ids */
4004 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4006 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4007 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4008 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
4010 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4013 "unable to map VNIC ID table address to physical memory\n");
4016 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4017 HWRM_CHECK_RESULT();
4018 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4026 * This function queries the VNIC IDs for a specified VF. It then calls
4027 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4028 * Then it calls the hwrm_cb function to program this new vnic configuration.
4030 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4031 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4032 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4034 struct bnxt_vnic_info vnic;
4036 int i, num_vnic_ids;
4041 /* First query all VNIC ids */
4042 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4043 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4044 RTE_CACHE_LINE_SIZE);
4045 if (vnic_ids == NULL)
4048 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4049 rte_mem_lock_page(((char *)vnic_ids) + sz);
4051 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4053 if (num_vnic_ids < 0)
4054 return num_vnic_ids;
4056 /* Retrieve VNIC, update bd_stall then update */
4058 for (i = 0; i < num_vnic_ids; i++) {
4059 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4060 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4061 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4064 if (vnic.mru <= 4) /* Indicates unallocated */
4067 vnic_cb(&vnic, cbdata);
4069 rc = hwrm_cb(bp, &vnic);
4079 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4082 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4083 struct hwrm_func_cfg_input req = {0};
4086 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4088 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4089 req.enables |= rte_cpu_to_le_32(
4090 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4091 req.vlan_antispoof_mode = on ?
4092 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4093 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4094 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4096 HWRM_CHECK_RESULT();
4102 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4104 struct bnxt_vnic_info vnic;
4107 int num_vnic_ids, i;
4111 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4112 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4113 RTE_CACHE_LINE_SIZE);
4114 if (vnic_ids == NULL)
4117 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4118 rte_mem_lock_page(((char *)vnic_ids) + sz);
4120 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4126 * Loop through to find the default VNIC ID.
4127 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4128 * by sending the hwrm_func_qcfg command to the firmware.
4130 for (i = 0; i < num_vnic_ids; i++) {
4131 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4132 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4133 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4134 bp->pf.first_vf_id + vf);
4137 if (vnic.func_default) {
4139 return vnic.fw_vnic_id;
4142 /* Could not find a default VNIC. */
4143 PMD_DRV_LOG(ERR, "No default VNIC\n");
4149 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4151 struct bnxt_filter_info *filter)
4154 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4155 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4156 uint32_t enables = 0;
4158 if (filter->fw_em_filter_id != UINT64_MAX)
4159 bnxt_hwrm_clear_em_filter(bp, filter);
4161 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4163 req.flags = rte_cpu_to_le_32(filter->flags);
4165 enables = filter->enables |
4166 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4167 req.dst_id = rte_cpu_to_le_16(dst_id);
4169 if (filter->ip_addr_type) {
4170 req.ip_addr_type = filter->ip_addr_type;
4171 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4174 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4175 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4177 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4178 memcpy(req.src_macaddr, filter->src_macaddr,
4179 RTE_ETHER_ADDR_LEN);
4181 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4182 memcpy(req.dst_macaddr, filter->dst_macaddr,
4183 RTE_ETHER_ADDR_LEN);
4185 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4186 req.ovlan_vid = filter->l2_ovlan;
4188 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4189 req.ivlan_vid = filter->l2_ivlan;
4191 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4192 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4194 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4195 req.ip_protocol = filter->ip_protocol;
4197 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4198 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4200 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4201 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4203 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4204 req.src_port = rte_cpu_to_be_16(filter->src_port);
4206 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4207 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4209 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4210 req.mirror_vnic_id = filter->mirror_vnic_id;
4212 req.enables = rte_cpu_to_le_32(enables);
4214 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4216 HWRM_CHECK_RESULT();
4218 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4224 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4227 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4228 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4230 if (filter->fw_em_filter_id == UINT64_MAX)
4233 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4235 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4237 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4239 HWRM_CHECK_RESULT();
4242 filter->fw_em_filter_id = UINT64_MAX;
4243 filter->fw_l2_filter_id = UINT64_MAX;
4248 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4250 struct bnxt_filter_info *filter)
4253 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4254 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4255 bp->hwrm_cmd_resp_addr;
4256 uint32_t enables = 0;
4258 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4259 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4261 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4263 req.flags = rte_cpu_to_le_32(filter->flags);
4265 enables = filter->enables |
4266 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4267 req.dst_id = rte_cpu_to_le_16(dst_id);
4269 if (filter->ip_addr_type) {
4270 req.ip_addr_type = filter->ip_addr_type;
4272 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4275 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4276 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4278 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4279 memcpy(req.src_macaddr, filter->src_macaddr,
4280 RTE_ETHER_ADDR_LEN);
4282 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4283 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4285 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4286 req.ip_protocol = filter->ip_protocol;
4288 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4289 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4291 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4292 req.src_ipaddr_mask[0] =
4293 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4295 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4296 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4298 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4299 req.dst_ipaddr_mask[0] =
4300 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4302 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4303 req.src_port = rte_cpu_to_le_16(filter->src_port);
4305 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4306 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4308 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4309 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4311 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4312 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4314 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4315 req.mirror_vnic_id = filter->mirror_vnic_id;
4317 req.enables = rte_cpu_to_le_32(enables);
4319 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4321 HWRM_CHECK_RESULT();
4323 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4329 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4330 struct bnxt_filter_info *filter)
4333 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4334 struct hwrm_cfa_ntuple_filter_free_output *resp =
4335 bp->hwrm_cmd_resp_addr;
4337 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4340 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4342 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4344 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4346 HWRM_CHECK_RESULT();
4349 filter->fw_ntuple_filter_id = UINT64_MAX;
4355 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4357 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4358 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4359 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4360 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4361 uint16_t *ring_tbl = vnic->rss_table;
4362 int nr_ctxs = vnic->num_lb_ctxts;
4363 int max_rings = bp->rx_nr_rings;
4367 for (i = 0, k = 0; i < nr_ctxs; i++) {
4368 struct bnxt_rx_ring_info *rxr;
4369 struct bnxt_cp_ring_info *cpr;
4371 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4373 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4374 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4375 req.hash_mode_flags = vnic->hash_mode;
4377 req.ring_grp_tbl_addr =
4378 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4379 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4380 2 * sizeof(*ring_tbl));
4381 req.hash_key_tbl_addr =
4382 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4384 req.ring_table_pair_index = i;
4385 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4387 for (j = 0; j < 64; j++) {
4390 /* Find next active ring. */
4391 for (cnt = 0; cnt < max_rings; cnt++) {
4392 if (rx_queue_state[k] !=
4393 RTE_ETH_QUEUE_STATE_STOPPED)
4395 if (++k == max_rings)
4399 /* Return if no rings are active. */
4400 if (cnt == max_rings) {
4405 /* Add rx/cp ring pair to RSS table. */
4406 rxr = rxqs[k]->rx_ring;
4407 cpr = rxqs[k]->cp_ring;
4409 ring_id = rxr->rx_ring_struct->fw_ring_id;
4410 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4411 ring_id = cpr->cp_ring_struct->fw_ring_id;
4412 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4414 if (++k == max_rings)
4417 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4420 HWRM_CHECK_RESULT();
4427 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4429 unsigned int rss_idx, fw_idx, i;
4431 if (!(vnic->rss_table && vnic->hash_type))
4434 if (BNXT_CHIP_THOR(bp))
4435 return bnxt_vnic_rss_configure_thor(bp, vnic);
4437 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4440 if (vnic->rss_table && vnic->hash_type) {
4442 * Fill the RSS hash & redirection table with
4443 * ring group ids for all VNICs
4445 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4446 rss_idx++, fw_idx++) {
4447 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4448 fw_idx %= bp->rx_cp_nr_rings;
4449 if (vnic->fw_grp_ids[fw_idx] !=
4454 if (i == bp->rx_cp_nr_rings)
4456 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4458 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4464 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4465 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4469 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4471 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4472 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4474 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4475 req->num_cmpl_dma_aggr_during_int =
4476 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4478 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4480 /* min timer set to 1/2 of interrupt timer */
4481 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4483 /* buf timer set to 1/4 of interrupt timer */
4484 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4486 req->cmpl_aggr_dma_tmr_during_int =
4487 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4489 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4490 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4491 req->flags = rte_cpu_to_le_16(flags);
4494 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4495 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4497 struct hwrm_ring_aggint_qcaps_input req = {0};
4498 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4503 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4504 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4505 HWRM_CHECK_RESULT();
4507 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4508 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4510 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4511 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4512 agg_req->flags = rte_cpu_to_le_16(flags);
4514 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4515 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4516 agg_req->enables = rte_cpu_to_le_32(enables);
4522 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4523 struct bnxt_coal *coal, uint16_t ring_id)
4525 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4526 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4527 bp->hwrm_cmd_resp_addr;
4530 /* Set ring coalesce parameters only for 100G NICs */
4531 if (BNXT_CHIP_THOR(bp)) {
4532 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4534 } else if (bnxt_stratus_device(bp)) {
4535 bnxt_hwrm_set_coal_params(coal, &req);
4540 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4541 req.ring_id = rte_cpu_to_le_16(ring_id);
4542 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4543 HWRM_CHECK_RESULT();
4548 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4549 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4551 struct hwrm_func_backing_store_qcaps_input req = {0};
4552 struct hwrm_func_backing_store_qcaps_output *resp =
4553 bp->hwrm_cmd_resp_addr;
4554 struct bnxt_ctx_pg_info *ctx_pg;
4555 struct bnxt_ctx_mem_info *ctx;
4556 int total_alloc_len;
4559 if (!BNXT_CHIP_THOR(bp) ||
4560 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4565 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4566 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4567 HWRM_CHECK_RESULT_SILENT();
4569 total_alloc_len = sizeof(*ctx);
4570 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4571 RTE_CACHE_LINE_SIZE);
4577 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4578 sizeof(*ctx_pg) * BNXT_MAX_Q,
4579 RTE_CACHE_LINE_SIZE);
4584 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4585 ctx->tqm_mem[i] = ctx_pg;
4588 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4589 ctx->qp_min_qp1_entries =
4590 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4591 ctx->qp_max_l2_entries =
4592 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4593 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4594 ctx->srq_max_l2_entries =
4595 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4596 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4597 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4598 ctx->cq_max_l2_entries =
4599 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4600 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4601 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4602 ctx->vnic_max_vnic_entries =
4603 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4604 ctx->vnic_max_ring_table_entries =
4605 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4606 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4607 ctx->stat_max_entries =
4608 rte_le_to_cpu_32(resp->stat_max_entries);
4609 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4610 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4611 ctx->tqm_min_entries_per_ring =
4612 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4613 ctx->tqm_max_entries_per_ring =
4614 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4615 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4616 if (!ctx->tqm_entries_multiple)
4617 ctx->tqm_entries_multiple = 1;
4618 ctx->mrav_max_entries =
4619 rte_le_to_cpu_32(resp->mrav_max_entries);
4620 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4621 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4622 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4628 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4630 struct hwrm_func_backing_store_cfg_input req = {0};
4631 struct hwrm_func_backing_store_cfg_output *resp =
4632 bp->hwrm_cmd_resp_addr;
4633 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4634 struct bnxt_ctx_pg_info *ctx_pg;
4635 uint32_t *num_entries;
4644 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4645 req.enables = rte_cpu_to_le_32(enables);
4647 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4648 ctx_pg = &ctx->qp_mem;
4649 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4650 req.qp_num_qp1_entries =
4651 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4652 req.qp_num_l2_entries =
4653 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4654 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4655 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4656 &req.qpc_pg_size_qpc_lvl,
4660 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4661 ctx_pg = &ctx->srq_mem;
4662 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4663 req.srq_num_l2_entries =
4664 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4665 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4666 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4667 &req.srq_pg_size_srq_lvl,
4671 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4672 ctx_pg = &ctx->cq_mem;
4673 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4674 req.cq_num_l2_entries =
4675 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4676 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4677 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4678 &req.cq_pg_size_cq_lvl,
4682 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4683 ctx_pg = &ctx->vnic_mem;
4684 req.vnic_num_vnic_entries =
4685 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4686 req.vnic_num_ring_table_entries =
4687 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4688 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4689 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4690 &req.vnic_pg_size_vnic_lvl,
4691 &req.vnic_page_dir);
4694 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4695 ctx_pg = &ctx->stat_mem;
4696 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4697 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4698 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4699 &req.stat_pg_size_stat_lvl,
4700 &req.stat_page_dir);
4703 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4704 num_entries = &req.tqm_sp_num_entries;
4705 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4706 pg_dir = &req.tqm_sp_page_dir;
4707 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4708 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4709 if (!(enables & ena))
4712 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4714 ctx_pg = ctx->tqm_mem[i];
4715 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4716 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4719 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4720 HWRM_CHECK_RESULT();
4726 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4728 struct hwrm_port_qstats_ext_input req = {0};
4729 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4730 struct bnxt_pf_info *pf = &bp->pf;
4733 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4734 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4737 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4739 req.port_id = rte_cpu_to_le_16(pf->port_id);
4740 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4741 req.tx_stat_host_addr =
4742 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4744 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4746 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4747 req.rx_stat_host_addr =
4748 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4750 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4752 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4755 bp->fw_rx_port_stats_ext_size = 0;
4756 bp->fw_tx_port_stats_ext_size = 0;
4758 bp->fw_rx_port_stats_ext_size =
4759 rte_le_to_cpu_16(resp->rx_stat_size);
4760 bp->fw_tx_port_stats_ext_size =
4761 rte_le_to_cpu_16(resp->tx_stat_size);
4764 HWRM_CHECK_RESULT();
4771 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4773 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4774 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4775 bp->hwrm_cmd_resp_addr;
4778 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4779 req.tunnel_type = type;
4780 req.dest_fid = bp->fw_fid;
4781 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4782 HWRM_CHECK_RESULT();
4790 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4792 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4793 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4794 bp->hwrm_cmd_resp_addr;
4797 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4798 req.tunnel_type = type;
4799 req.dest_fid = bp->fw_fid;
4800 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4801 HWRM_CHECK_RESULT();
4808 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4810 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4811 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4812 bp->hwrm_cmd_resp_addr;
4815 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4816 req.src_fid = bp->fw_fid;
4817 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4818 HWRM_CHECK_RESULT();
4821 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4828 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4831 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4832 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4833 bp->hwrm_cmd_resp_addr;
4836 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4837 req.src_fid = bp->fw_fid;
4838 req.tunnel_type = tun_type;
4839 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4840 HWRM_CHECK_RESULT();
4843 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4845 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4852 int bnxt_hwrm_set_mac(struct bnxt *bp)
4854 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4855 struct hwrm_func_vf_cfg_input req = {0};
4861 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4864 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4865 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4867 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4869 HWRM_CHECK_RESULT();
4871 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4877 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4879 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4880 struct hwrm_func_drv_if_change_input req = {0};
4884 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
4887 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4888 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4889 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4891 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4894 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4898 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4900 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4902 HWRM_CHECK_RESULT();
4903 flags = rte_le_to_cpu_32(resp->flags);
4909 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4910 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4911 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4917 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4919 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4920 struct bnxt_error_recovery_info *info = bp->recovery_info;
4921 struct hwrm_error_recovery_qcfg_input req = {0};
4926 /* Older FW does not have error recovery support */
4927 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4931 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4933 bp->recovery_info = info;
4937 memset(info, 0, sizeof(*info));
4940 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4942 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4944 HWRM_CHECK_RESULT();
4946 flags = rte_le_to_cpu_32(resp->flags);
4947 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4948 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4949 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4950 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4952 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4953 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4958 /* FW returned values are in units of 100msec */
4959 info->driver_polling_freq =
4960 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4961 info->master_func_wait_period =
4962 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4963 info->normal_func_wait_period =
4964 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4965 info->master_func_wait_period_after_reset =
4966 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4967 info->max_bailout_time_after_reset =
4968 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4969 info->status_regs[BNXT_FW_STATUS_REG] =
4970 rte_le_to_cpu_32(resp->fw_health_status_reg);
4971 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4972 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4973 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4974 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4975 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4976 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4977 info->reg_array_cnt =
4978 rte_le_to_cpu_32(resp->reg_array_cnt);
4980 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4985 for (i = 0; i < info->reg_array_cnt; i++) {
4986 info->reset_reg[i] =
4987 rte_le_to_cpu_32(resp->reset_reg[i]);
4988 info->reset_reg_val[i] =
4989 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4990 info->delay_after_reset[i] =
4991 resp->delay_after_reset[i];
4996 /* Map the FW status registers */
4998 rc = bnxt_map_fw_health_status_regs(bp);
5001 rte_free(bp->recovery_info);
5002 bp->recovery_info = NULL;
5007 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5009 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5010 struct hwrm_fw_reset_input req = {0};
5016 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
5018 req.embedded_proc_type =
5019 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5020 req.selfrst_status =
5021 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5022 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5024 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5027 HWRM_CHECK_RESULT();
5033 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5035 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5036 struct hwrm_port_ts_query_input req = {0};
5037 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5044 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5047 case BNXT_PTP_FLAGS_PATH_TX:
5048 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5050 case BNXT_PTP_FLAGS_PATH_RX:
5051 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5053 case BNXT_PTP_FLAGS_CURRENT_TIME:
5054 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5058 req.flags = rte_cpu_to_le_32(flags);
5059 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5061 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5063 HWRM_CHECK_RESULT();
5066 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5068 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5075 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5077 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5078 bp->hwrm_cmd_resp_addr;
5079 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5083 if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5086 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5088 "Not a PF or trusted VF. Command not supported\n");
5092 HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5093 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5095 HWRM_CHECK_RESULT();
5096 flags = rte_le_to_cpu_32(resp->flags);
5099 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5100 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5101 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");