1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
30 #define HWRM_VERSION_1_10_2_13 0x10a020d
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(int) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages == 0)
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
78 static struct bnxt_cp_ring_info*
79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
81 struct bnxt_cp_ring_info *cp_ring = NULL;
85 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
86 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
88 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
89 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
91 if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
92 rte_cpu_to_le_16(rid)) {
97 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
98 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
99 struct bnxt_tx_queue *txq = bp->tx_queues[i];
101 if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
102 rte_cpu_to_le_16(rid)) {
113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
114 * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
115 * before timeout, we force the done bit for the cleanup to proceed.
116 * Also if cpr is null, do nothing.. The HWRM command is not for a
117 * Tx/Rx/AGG ring cleanup.
120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
121 bool tx, bool rx, bool timeout)
127 done = bnxt_flush_tx_cmp(cpr);
130 done = bnxt_flush_rx_cmp(cpr);
133 PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
136 /* We are about to timeout and still haven't seen the
137 * HWRM done for the Ring free. Force the cleanup.
139 if (!done && timeout) {
141 PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
145 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
146 * Otherwise the cpr would have been valid. So do nothing.
155 * HWRM Functions (sent to HWRM)
156 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
157 * HWRM command times out, or a negative error code if the HWRM
158 * command was failed by the FW.
161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
162 uint32_t msg_len, bool use_kong_mb)
165 struct input *req = msg;
166 struct output *resp = bp->hwrm_cmd_resp_addr;
167 uint32_t *data = msg;
170 uint16_t max_req_len = bp->max_req_len;
171 struct hwrm_short_input short_input = { 0 };
172 uint16_t bar_offset = use_kong_mb ?
173 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
174 uint16_t mb_trigger_offset = use_kong_mb ?
175 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
176 struct bnxt_cp_ring_info *cpr = NULL;
181 /* Do not send HWRM commands to firmware in error state */
182 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
185 timeout = bp->hwrm_cmd_timeout;
187 /* Update the message length for backing store config for new FW. */
188 if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
189 rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
190 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
192 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
193 msg_len > bp->max_req_len) {
194 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
196 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
197 memcpy(short_cmd_req, req, msg_len);
199 short_input.req_type = rte_cpu_to_le_16(req->req_type);
200 short_input.signature = rte_cpu_to_le_16(
201 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
202 short_input.size = rte_cpu_to_le_16(msg_len);
203 short_input.req_addr =
204 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
206 data = (uint32_t *)&short_input;
207 msg_len = sizeof(short_input);
209 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
212 /* Write request msg to hwrm channel */
213 for (i = 0; i < msg_len; i += 4) {
214 bar = (uint8_t *)bp->bar0 + bar_offset + i;
215 rte_write32(*data, bar);
219 /* Zero the rest of the request space */
220 for (; i < max_req_len; i += 4) {
221 bar = (uint8_t *)bp->bar0 + bar_offset + i;
225 /* Ring channel doorbell */
226 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
229 * Make sure the channel doorbell ring command complete before
230 * reading the response to avoid getting stale or invalid
235 /* Check ring flush is done.
236 * This is valid only for Tx and Rx rings (including AGG rings).
237 * The Tx and Rx rings should be freed once the HW confirms all
238 * the internal buffers and BDs associated with the rings are
239 * consumed and the corresponding DMA is handled.
241 if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
242 /* Check if the TxCQ matches. If that fails check if RxCQ
243 * matches. And if neither match, is_rx = false, is_tx = false.
245 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
246 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
248 /* Not a TxCQ. Check if the RxCQ matches. */
250 bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
251 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
259 /* Poll for the valid bit */
260 for (i = 0; i < timeout; i++) {
263 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
265 /* Sanity check on the resp->resp_len */
267 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
268 /* Last byte of resp contains the valid key */
269 valid = (uint8_t *)resp + resp->resp_len - 1;
270 if (*valid == HWRM_RESP_VALID_KEY && done)
277 /* Suppress VER_GET timeout messages during reset recovery */
278 if (bp->flags & BNXT_FLAG_FW_RESET &&
279 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
283 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
284 req->req_type, req->seq_id);
291 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
292 * spinlock, and does initial processing.
294 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
295 * releases the spinlock only if it returns. If the regular int return codes
296 * are not used by the function, HWRM_CHECK_RESULT() should not be used
297 * directly, rather it should be copied and modified to suit the function.
299 * HWRM_UNLOCK() must be called after all response processing is completed.
301 #define HWRM_PREP(req, type, kong) do { \
302 rte_spinlock_lock(&bp->hwrm_lock); \
303 if (bp->hwrm_cmd_resp_addr == NULL) { \
304 rte_spinlock_unlock(&bp->hwrm_lock); \
307 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
308 (req)->req_type = rte_cpu_to_le_16(type); \
309 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
310 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
311 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
312 (req)->target_id = rte_cpu_to_le_16(0xffff); \
313 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
316 #define HWRM_CHECK_RESULT_SILENT() do {\
318 rte_spinlock_unlock(&bp->hwrm_lock); \
321 if (resp->error_code) { \
322 rc = rte_le_to_cpu_16(resp->error_code); \
323 rte_spinlock_unlock(&bp->hwrm_lock); \
328 #define HWRM_CHECK_RESULT() do {\
330 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
331 rte_spinlock_unlock(&bp->hwrm_lock); \
332 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
334 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
336 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
338 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
340 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
346 if (resp->error_code) { \
347 rc = rte_le_to_cpu_16(resp->error_code); \
348 if (resp->resp_len >= 16) { \
349 struct hwrm_err_output *tmp_hwrm_err_op = \
352 "error %d:%d:%08x:%04x\n", \
353 rc, tmp_hwrm_err_op->cmd_err, \
355 tmp_hwrm_err_op->opaque_0), \
357 tmp_hwrm_err_op->opaque_1)); \
359 PMD_DRV_LOG(ERR, "error %d\n", rc); \
361 rte_spinlock_unlock(&bp->hwrm_lock); \
362 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
364 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
366 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
368 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
370 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
378 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
389 bool mailbox = BNXT_USE_CHIMP_MB;
390 struct input *req = msg;
391 struct output *resp = bp->hwrm_cmd_resp_addr;
394 mailbox = BNXT_USE_KONG(bp);
396 HWRM_PREP(req, msg_type, mailbox);
398 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
403 memcpy(resp_msg, resp, resp_len);
410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
414 uint32_t *tf_response_code,
418 uint32_t response_len)
421 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
422 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
423 bool mailbox = BNXT_USE_CHIMP_MB;
425 if (msg_len > sizeof(req.tf_req))
429 mailbox = BNXT_USE_KONG(bp);
431 HWRM_PREP(&req, HWRM_TF, mailbox);
432 /* Build request using the user supplied request payload.
433 * TLV request size is checked at build time against HWRM
434 * request max size, thus no checking required.
436 req.tf_type = tf_type;
437 req.tf_subtype = tf_subtype;
438 memcpy(req.tf_req, msg, msg_len);
440 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
443 /* Copy the resp to user provided response buffer */
444 if (response != NULL)
445 /* Post process response data. We need to copy only
446 * the 'payload' as the HWRM data structure really is
447 * HWRM header + msg header + payload and the TFLIB
448 * only provided a payload place holder.
450 if (response_len != 0) {
456 /* Extract the internal tflib response code */
457 *tf_response_code = resp->tf_resp_code;
463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
466 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
467 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
469 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
470 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
473 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
482 struct bnxt_vnic_info *vnic,
484 struct bnxt_vlan_table_entry *vlan_table)
487 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
488 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
491 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
494 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
495 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
497 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
498 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
499 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
500 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
502 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
503 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
505 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
506 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
507 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
508 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
509 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
510 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
513 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
514 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
515 req.vlan_tag_tbl_addr =
516 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
517 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
519 req.mask = rte_cpu_to_le_32(mask);
521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
531 struct bnxt_vlan_antispoof_table_entry *vlan_table)
534 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
535 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
536 bp->hwrm_cmd_resp_addr;
539 * Older HWRM versions did not support this command, and the set_rx_mask
540 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
541 * removed from set_rx_mask call, and this command was added.
543 * This command is also present from 1.7.8.11 and higher,
546 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
547 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
548 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
553 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
554 req.fid = rte_cpu_to_le_16(fid);
556 req.vlan_tag_mask_tbl_addr =
557 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
558 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
569 struct bnxt_filter_info *filter)
572 struct bnxt_filter_info *l2_filter = filter;
573 struct bnxt_vnic_info *vnic = NULL;
574 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
575 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
577 if (filter->fw_l2_filter_id == UINT64_MAX)
580 if (filter->matching_l2_fltr_ptr)
581 l2_filter = filter->matching_l2_fltr_ptr;
583 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
584 filter, l2_filter, l2_filter->l2_ref_cnt);
586 if (l2_filter->l2_ref_cnt == 0)
589 if (l2_filter->l2_ref_cnt > 0)
590 l2_filter->l2_ref_cnt--;
592 if (l2_filter->l2_ref_cnt > 0)
595 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
597 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
599 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
604 filter->fw_l2_filter_id = UINT64_MAX;
605 if (l2_filter->l2_ref_cnt == 0) {
606 vnic = l2_filter->vnic;
608 STAILQ_REMOVE(&vnic->filter, l2_filter,
609 bnxt_filter_info, next);
610 bnxt_free_filter(bp, l2_filter);
617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
619 struct bnxt_filter_info *filter)
622 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
623 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
624 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
625 const struct rte_eth_vmdq_rx_conf *conf =
626 &dev_conf->rx_adv_conf.vmdq_rx_conf;
627 uint32_t enables = 0;
628 uint16_t j = dst_id - 1;
630 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
631 if ((dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) &&
632 conf->pool_map[j].pools & (1UL << j)) {
634 "Add vlan %u to vmdq pool %u\n",
635 conf->pool_map[j].vlan_id, j);
637 filter->l2_ivlan = conf->pool_map[j].vlan_id;
639 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
640 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
643 if (filter->fw_l2_filter_id != UINT64_MAX)
644 bnxt_hwrm_clear_l2_filter(bp, filter);
646 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
648 /* PMD does not support XDP and RoCE */
649 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
650 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
651 req.flags = rte_cpu_to_le_32(filter->flags);
653 enables = filter->enables |
654 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
655 req.dst_id = rte_cpu_to_le_16(dst_id);
658 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
659 memcpy(req.l2_addr, filter->l2_addr,
662 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
663 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
666 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
667 req.l2_ovlan = filter->l2_ovlan;
669 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
670 req.l2_ivlan = filter->l2_ivlan;
672 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
673 req.l2_ovlan_mask = filter->l2_ovlan_mask;
675 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
676 req.l2_ivlan_mask = filter->l2_ivlan_mask;
677 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
678 req.src_id = rte_cpu_to_le_32(filter->src_id);
679 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
680 req.src_type = filter->src_type;
681 if (filter->pri_hint) {
682 req.pri_hint = filter->pri_hint;
683 req.l2_filter_id_hint =
684 rte_cpu_to_le_64(filter->l2_filter_id_hint);
687 req.enables = rte_cpu_to_le_32(enables);
689 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
693 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
694 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
697 filter->l2_ref_cnt++;
702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
704 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
705 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
712 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
715 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
718 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
719 if (ptp->tx_tstamp_en)
720 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
723 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
724 req.flags = rte_cpu_to_le_32(flags);
725 req.enables = rte_cpu_to_le_32
726 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
727 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
729 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
738 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
739 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
740 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
745 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
747 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
749 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
753 if (BNXT_CHIP_P5(bp)) {
754 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
757 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
761 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
762 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
764 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
768 if (!BNXT_CHIP_P5(bp)) {
769 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
770 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
771 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
772 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
773 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
774 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
775 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
776 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
777 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
778 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
779 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
780 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
781 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
782 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
783 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
784 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
785 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
786 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
795 void bnxt_free_vf_info(struct bnxt *bp)
802 if (bp->pf->vf_info == NULL)
805 for (i = 0; i < bp->pf->max_vfs; i++) {
806 rte_free(bp->pf->vf_info[i].vlan_table);
807 bp->pf->vf_info[i].vlan_table = NULL;
808 rte_free(bp->pf->vf_info[i].vlan_as_table);
809 bp->pf->vf_info[i].vlan_as_table = NULL;
811 rte_free(bp->pf->vf_info);
812 bp->pf->vf_info = NULL;
815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
817 struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
821 bnxt_free_vf_info(bp);
823 vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
824 if (vf_info == NULL) {
825 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
829 bp->pf->max_vfs = max_vfs;
830 for (i = 0; i < max_vfs; i++) {
831 vf_info[i].fid = bp->pf->first_vf_id + i;
832 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
833 getpagesize(), getpagesize());
834 if (vf_info[i].vlan_table == NULL) {
835 PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
838 rte_mem_lock_page(vf_info[i].vlan_table);
840 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
841 getpagesize(), getpagesize());
842 if (vf_info[i].vlan_as_table == NULL) {
843 PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
846 rte_mem_lock_page(vf_info[i].vlan_as_table);
848 STAILQ_INIT(&vf_info[i].filter);
851 bp->pf->vf_info = vf_info;
855 bnxt_free_vf_info(bp);
859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
862 struct hwrm_func_qcaps_input req = {.req_type = 0 };
863 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
864 uint16_t new_max_vfs;
867 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
869 req.fid = rte_cpu_to_le_16(0xffff);
871 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
875 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
876 flags = rte_le_to_cpu_32(resp->flags);
878 bp->pf->port_id = resp->port_id;
879 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
880 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
881 new_max_vfs = bp->pdev->max_vfs;
882 if (new_max_vfs != bp->pf->max_vfs) {
883 rc = bnxt_alloc_vf_info(bp, new_max_vfs);
889 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
890 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
891 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
892 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
894 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
896 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
897 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
898 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
899 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
900 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
901 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
902 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
903 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
904 bp->max_l2_ctx += bp->max_rx_em_flows;
905 /* TODO: For now, do not support VMDq/RFS on VFs. */
910 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
914 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
915 bp->max_l2_ctx, bp->max_vnics);
916 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
918 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
919 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
920 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
921 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
923 bnxt_hwrm_ptp_qcfg(bp);
927 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
928 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
930 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
931 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
932 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
935 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
936 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
938 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
939 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
941 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
942 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
944 if (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) {
945 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
946 PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n");
954 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
958 rc = __bnxt_hwrm_func_qcaps(bp);
962 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
963 rc = bnxt_alloc_ctx_mem(bp);
968 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
969 * But the error can be ignored. Return success.
971 rc = bnxt_hwrm_func_resc_qcaps(bp);
973 bp->flags |= BNXT_FLAG_NEW_RM;
979 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
980 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
984 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
985 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
987 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
989 req.target_id = rte_cpu_to_le_16(0xffff);
991 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
995 flags = rte_le_to_cpu_32(resp->flags);
997 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
998 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
999 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
1002 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
1003 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1005 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1006 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1008 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP) {
1009 bp->vnic_cap_flags |= BNXT_VNIC_CAP_VLAN_RX_STRIP;
1010 PMD_DRV_LOG(DEBUG, "Rx VLAN strip capability enabled\n");
1013 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1020 int bnxt_hwrm_func_reset(struct bnxt *bp)
1023 struct hwrm_func_reset_input req = {.req_type = 0 };
1024 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1026 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1028 req.enables = rte_cpu_to_le_32(0);
1030 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1032 HWRM_CHECK_RESULT();
1038 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1042 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1043 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1045 if (bp->flags & BNXT_FLAG_REGISTERED)
1048 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1049 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1050 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1051 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1053 /* PFs and trusted VFs should indicate the support of the
1054 * Master capability on non Stingray platform
1056 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1057 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1059 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1060 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1061 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1062 req.ver_maj_8b = RTE_VER_YEAR;
1063 req.ver_min_8b = RTE_VER_MONTH;
1064 req.ver_upd_8b = RTE_VER_MINOR;
1067 req.enables |= rte_cpu_to_le_32(
1068 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1069 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1070 RTE_MIN(sizeof(req.vf_req_fwd),
1071 sizeof(bp->pf->vf_req_fwd)));
1074 req.flags = rte_cpu_to_le_32(flags);
1076 req.async_event_fwd[0] |=
1077 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1078 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1079 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1080 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1081 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1082 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1083 req.async_event_fwd[0] |=
1084 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1085 req.async_event_fwd[1] |=
1086 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1087 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1089 req.async_event_fwd[1] |=
1090 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1092 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1093 req.async_event_fwd[1] |=
1094 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1096 req.async_event_fwd[2] |=
1097 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST |
1098 ASYNC_CMPL_EVENT_ID_ERROR_REPORT);
1100 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1102 HWRM_CHECK_RESULT();
1104 flags = rte_le_to_cpu_32(resp->flags);
1105 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1106 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1110 bp->flags |= BNXT_FLAG_REGISTERED;
1115 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1117 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1120 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1123 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1128 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1129 struct hwrm_func_vf_cfg_input req = {0};
1131 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1133 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1134 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1135 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1136 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1137 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1139 if (BNXT_HAS_RING_GRPS(bp)) {
1140 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1141 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1144 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1145 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1146 AGG_RING_MULTIPLIER);
1147 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1148 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1150 BNXT_NUM_ASYNC_CPR(bp));
1151 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1152 if (bp->vf_resv_strategy ==
1153 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1154 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1155 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1156 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1157 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1158 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1159 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1160 } else if (bp->vf_resv_strategy ==
1161 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1162 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1163 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1167 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1168 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1169 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1170 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1171 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1172 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1174 if (test && BNXT_HAS_RING_GRPS(bp))
1175 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1177 req.flags = rte_cpu_to_le_32(flags);
1178 req.enables |= rte_cpu_to_le_32(enables);
1180 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1183 HWRM_CHECK_RESULT_SILENT();
1185 HWRM_CHECK_RESULT();
1191 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1194 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1195 struct hwrm_func_resource_qcaps_input req = {0};
1197 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1198 req.fid = rte_cpu_to_le_16(0xffff);
1200 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1202 HWRM_CHECK_RESULT_SILENT();
1204 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1205 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1206 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1207 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1208 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1209 /* func_resource_qcaps does not return max_rx_em_flows.
1210 * So use the value provided by func_qcaps.
1212 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1213 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1214 bp->max_l2_ctx += bp->max_rx_em_flows;
1215 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1216 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1217 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1218 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1219 if (bp->vf_resv_strategy >
1220 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1221 bp->vf_resv_strategy =
1222 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1228 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1231 struct hwrm_ver_get_input req = {.req_type = 0 };
1232 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1233 uint32_t fw_version;
1234 uint16_t max_resp_len;
1235 char type[RTE_MEMZONE_NAMESIZE];
1236 uint32_t dev_caps_cfg;
1238 bp->max_req_len = HWRM_MAX_REQ_LEN;
1239 bp->hwrm_cmd_timeout = timeout;
1240 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1242 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1243 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1244 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1246 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1248 if (bp->flags & BNXT_FLAG_FW_RESET)
1249 HWRM_CHECK_RESULT_SILENT();
1251 HWRM_CHECK_RESULT();
1253 if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1258 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1259 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1260 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1261 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1262 resp->hwrm_fw_rsvd_8b);
1263 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1264 (resp->hwrm_fw_min_8b << 16) |
1265 (resp->hwrm_fw_bld_8b << 8) |
1266 resp->hwrm_fw_rsvd_8b;
1267 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1268 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1270 fw_version = resp->hwrm_intf_maj_8b << 16;
1271 fw_version |= resp->hwrm_intf_min_8b << 8;
1272 fw_version |= resp->hwrm_intf_upd_8b;
1273 bp->hwrm_spec_code = fw_version;
1275 /* def_req_timeout value is in milliseconds */
1276 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1277 /* convert timeout to usec */
1278 bp->hwrm_cmd_timeout *= 1000;
1279 if (!bp->hwrm_cmd_timeout)
1280 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1282 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1283 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1288 if (bp->max_req_len > resp->max_req_win_len) {
1289 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1294 bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1296 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1297 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1298 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1299 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1301 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1302 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1304 RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1305 bp->max_resp_len = max_resp_len;
1308 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1310 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1311 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1312 bp->flags |= BNXT_FLAG_SHORT_CMD;
1315 if (((dev_caps_cfg &
1316 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1318 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1319 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1320 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1321 bp->pdev->addr.domain, bp->pdev->addr.bus,
1322 bp->pdev->addr.devid, bp->pdev->addr.function);
1324 rte_free(bp->hwrm_short_cmd_req_addr);
1326 bp->hwrm_short_cmd_req_addr =
1327 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1328 if (bp->hwrm_short_cmd_req_addr == NULL) {
1332 bp->hwrm_short_cmd_req_dma_addr =
1333 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1334 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1335 rte_free(bp->hwrm_short_cmd_req_addr);
1337 "Unable to map buffer to physical memory.\n");
1343 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1344 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1345 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1348 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1349 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1351 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1352 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1353 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1357 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1358 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1359 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1363 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
1364 PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
1365 bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
1373 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp)
1376 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1377 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1379 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1382 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1384 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1386 HWRM_CHECK_RESULT();
1389 PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1390 bp->eth_dev->data->port_id);
1395 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1398 struct hwrm_port_phy_cfg_input req = {0};
1399 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1400 uint32_t enables = 0;
1402 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1404 if (conf->link_up) {
1405 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1406 if (bp->link_info->auto_mode && conf->link_speed) {
1407 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1408 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1411 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1413 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1414 * any auto mode, even "none".
1416 if (!conf->link_speed) {
1417 /* No speeds specified. Enable AutoNeg - all speeds */
1418 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1420 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1422 if (bp->link_info->link_signal_mode) {
1424 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1425 req.force_pam4_link_speed =
1426 rte_cpu_to_le_16(conf->link_speed);
1428 req.force_link_speed =
1429 rte_cpu_to_le_16(conf->link_speed);
1432 /* AutoNeg - Advertise speeds specified. */
1433 if (conf->auto_link_speed_mask &&
1434 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1436 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1437 req.auto_link_speed_mask =
1438 conf->auto_link_speed_mask;
1439 if (conf->auto_pam4_link_speeds) {
1441 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1442 req.auto_link_pam4_speed_mask =
1443 conf->auto_pam4_link_speeds;
1446 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1449 if (conf->auto_link_speed &&
1450 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1452 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1454 req.auto_duplex = conf->duplex;
1455 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1456 req.auto_pause = conf->auto_pause;
1457 req.force_pause = conf->force_pause;
1458 /* Set force_pause if there is no auto or if there is a force */
1459 if (req.auto_pause && !req.force_pause)
1460 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1462 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1464 req.enables = rte_cpu_to_le_32(enables);
1467 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1468 PMD_DRV_LOG(INFO, "Force Link Down\n");
1471 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1473 HWRM_CHECK_RESULT();
1479 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1480 struct bnxt_link_info *link_info)
1483 struct hwrm_port_phy_qcfg_input req = {0};
1484 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1486 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1488 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1490 HWRM_CHECK_RESULT();
1492 link_info->phy_link_status = resp->link;
1493 link_info->link_up =
1494 (link_info->phy_link_status ==
1495 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1496 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1497 link_info->duplex = resp->duplex_cfg;
1498 link_info->pause = resp->pause;
1499 link_info->auto_pause = resp->auto_pause;
1500 link_info->force_pause = resp->force_pause;
1501 link_info->auto_mode = resp->auto_mode;
1502 link_info->phy_type = resp->phy_type;
1503 link_info->media_type = resp->media_type;
1505 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1506 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1507 link_info->auto_link_speed_mask = rte_le_to_cpu_16(resp->auto_link_speed_mask);
1508 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1509 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1510 link_info->phy_ver[0] = resp->phy_maj;
1511 link_info->phy_ver[1] = resp->phy_min;
1512 link_info->phy_ver[2] = resp->phy_bld;
1513 link_info->link_signal_mode =
1514 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1515 link_info->force_pam4_link_speed =
1516 rte_le_to_cpu_16(resp->force_pam4_link_speed);
1517 link_info->support_pam4_speeds =
1518 rte_le_to_cpu_16(resp->support_pam4_speeds);
1519 link_info->auto_pam4_link_speeds =
1520 rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1521 link_info->module_status = resp->module_status;
1524 PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1525 link_info->link_speed, link_info->auto_mode,
1526 link_info->auto_link_speed, link_info->auto_link_speed_mask,
1527 link_info->support_speeds, link_info->force_link_speed);
1528 PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1529 link_info->link_signal_mode,
1530 link_info->auto_pam4_link_speeds,
1531 link_info->support_pam4_speeds,
1532 link_info->force_pam4_link_speed);
1536 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1539 struct hwrm_port_phy_qcaps_input req = {0};
1540 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1541 struct bnxt_link_info *link_info = bp->link_info;
1543 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1546 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1548 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1550 HWRM_CHECK_RESULT_SILENT();
1552 bp->port_cnt = resp->port_cnt;
1553 if (resp->supported_speeds_auto_mode)
1554 link_info->support_auto_speeds =
1555 rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1556 if (resp->supported_pam4_speeds_auto_mode)
1557 link_info->support_pam4_auto_speeds =
1558 rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1562 /* Older firmware does not have supported_auto_speeds, so assume
1563 * that all supported speeds can be autonegotiated.
1565 if (link_info->auto_link_speed_mask && !link_info->support_auto_speeds)
1566 link_info->support_auto_speeds = link_info->support_speeds;
1571 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1575 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1576 if (bp->tx_cos_queue[i].profile ==
1577 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1578 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1585 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1589 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1590 if (bp->tx_cos_queue[i].profile !=
1591 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1592 bp->tx_cos_queue[i].id !=
1593 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1594 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1600 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1603 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1604 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1605 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1609 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1611 req.flags = rte_cpu_to_le_32(dir);
1612 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1613 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1614 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1616 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1617 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1619 HWRM_CHECK_RESULT();
1621 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1622 GET_TX_QUEUE_INFO(0);
1623 GET_TX_QUEUE_INFO(1);
1624 GET_TX_QUEUE_INFO(2);
1625 GET_TX_QUEUE_INFO(3);
1626 GET_TX_QUEUE_INFO(4);
1627 GET_TX_QUEUE_INFO(5);
1628 GET_TX_QUEUE_INFO(6);
1629 GET_TX_QUEUE_INFO(7);
1631 GET_RX_QUEUE_INFO(0);
1632 GET_RX_QUEUE_INFO(1);
1633 GET_RX_QUEUE_INFO(2);
1634 GET_RX_QUEUE_INFO(3);
1635 GET_RX_QUEUE_INFO(4);
1636 GET_RX_QUEUE_INFO(5);
1637 GET_RX_QUEUE_INFO(6);
1638 GET_RX_QUEUE_INFO(7);
1643 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1646 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1647 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1651 /* iterate and find the COSq profile to use for Tx */
1652 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1653 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1654 if (bp->tx_cos_queue[i].id != 0xff)
1655 bp->tx_cosq_id[j++] =
1656 bp->tx_cos_queue[i].id;
1659 /* When CoS classification is disabled, for normal NIC
1660 * operations, ideally we should look to use LOSSY.
1661 * If not found, fallback to the first valid profile
1663 if (!bnxt_find_lossy_profile(bp))
1664 bnxt_find_first_valid_profile(bp);
1669 bp->max_tc = resp->max_configurable_queues;
1670 bp->max_lltc = resp->max_configurable_lossless_queues;
1671 if (bp->max_tc > BNXT_MAX_QUEUE)
1672 bp->max_tc = BNXT_MAX_QUEUE;
1673 bp->max_q = bp->max_tc;
1675 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1676 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1684 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1685 struct bnxt_ring *ring,
1686 uint32_t ring_type, uint32_t map_index,
1687 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1688 uint16_t tx_cosq_id)
1691 uint32_t enables = 0;
1692 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1693 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1694 struct rte_mempool *mb_pool;
1695 uint16_t rx_buf_size;
1697 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1699 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1700 req.fbo = rte_cpu_to_le_32(0);
1701 /* Association of ring index with doorbell index */
1702 req.logical_id = rte_cpu_to_le_16(map_index);
1703 req.length = rte_cpu_to_le_32(ring->ring_size);
1705 switch (ring_type) {
1706 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1707 req.ring_type = ring_type;
1708 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1709 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1710 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1711 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1713 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1715 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1716 req.ring_type = ring_type;
1717 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1718 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1719 if (BNXT_CHIP_P5(bp)) {
1720 mb_pool = bp->rx_queues[0]->mb_pool;
1721 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1722 RTE_PKTMBUF_HEADROOM;
1723 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1724 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1726 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1728 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1730 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1732 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1733 req.ring_type = ring_type;
1734 if (BNXT_HAS_NQ(bp)) {
1735 /* Association of cp ring with nq */
1736 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1738 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1740 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1742 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1743 req.ring_type = ring_type;
1744 req.page_size = BNXT_PAGE_SHFT;
1745 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1747 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1748 req.ring_type = ring_type;
1749 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1751 mb_pool = bp->rx_queues[0]->mb_pool;
1752 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1753 RTE_PKTMBUF_HEADROOM;
1754 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1755 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1757 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1758 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1759 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1760 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1763 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1768 req.enables = rte_cpu_to_le_32(enables);
1770 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1772 if (rc || resp->error_code) {
1773 if (rc == 0 && resp->error_code)
1774 rc = rte_le_to_cpu_16(resp->error_code);
1775 switch (ring_type) {
1776 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1778 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1781 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1783 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1786 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1788 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1792 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1794 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1797 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1799 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1803 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1809 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1814 int bnxt_hwrm_ring_free(struct bnxt *bp,
1815 struct bnxt_ring *ring, uint32_t ring_type,
1816 uint16_t cp_ring_id)
1819 struct hwrm_ring_free_input req = {.req_type = 0 };
1820 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1822 if (ring->fw_ring_id == INVALID_HW_RING_ID)
1825 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1827 req.ring_type = ring_type;
1828 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1829 req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1831 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1832 ring->fw_ring_id = INVALID_HW_RING_ID;
1834 if (rc || resp->error_code) {
1835 if (rc == 0 && resp->error_code)
1836 rc = rte_le_to_cpu_16(resp->error_code);
1839 switch (ring_type) {
1840 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1841 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1844 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1845 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1848 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1849 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1852 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1854 "hwrm_ring_free nq failed. rc:%d\n", rc);
1856 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1858 "hwrm_ring_free agg failed. rc:%d\n", rc);
1861 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1869 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1872 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1873 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1875 /* Don't attempt to re-create the ring group if it is already created */
1876 if (bp->grp_info[idx].fw_grp_id != INVALID_HW_RING_ID)
1879 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1881 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1882 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1883 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1884 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1886 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1888 HWRM_CHECK_RESULT();
1890 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1897 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1900 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1901 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1903 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1906 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1908 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1910 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1912 HWRM_CHECK_RESULT();
1915 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1919 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1922 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1923 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1925 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1928 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1930 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1932 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1934 HWRM_CHECK_RESULT();
1940 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1943 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1944 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1946 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE)
1949 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1951 req.update_period_ms = rte_cpu_to_le_32(0);
1953 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1955 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1957 HWRM_CHECK_RESULT();
1959 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1966 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1969 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1970 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1972 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1975 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1977 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1979 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1981 HWRM_CHECK_RESULT();
1984 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1989 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1992 struct hwrm_vnic_alloc_input req = { 0 };
1993 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1995 if (!BNXT_HAS_RING_GRPS(bp))
1996 goto skip_ring_grps;
1998 /* map ring groups to this vnic */
1999 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
2000 vnic->start_grp_id, vnic->end_grp_id);
2001 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
2002 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
2004 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
2005 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
2006 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
2007 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
2010 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
2011 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
2013 if (vnic->func_default)
2015 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
2016 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2018 HWRM_CHECK_RESULT();
2020 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
2022 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2026 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
2027 struct bnxt_vnic_info *vnic,
2028 struct bnxt_plcmodes_cfg *pmode)
2031 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2032 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2034 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2036 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2038 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2040 HWRM_CHECK_RESULT();
2042 pmode->flags = rte_le_to_cpu_32(resp->flags);
2043 /* dflt_vnic bit doesn't exist in the _cfg command */
2044 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2045 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2046 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2047 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2054 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2055 struct bnxt_vnic_info *vnic,
2056 struct bnxt_plcmodes_cfg *pmode)
2059 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2060 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2062 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2063 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2067 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2069 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2070 req.flags = rte_cpu_to_le_32(pmode->flags);
2071 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2072 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2073 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2074 req.enables = rte_cpu_to_le_32(
2075 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2076 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2077 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2080 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2082 HWRM_CHECK_RESULT();
2088 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2091 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2092 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2093 struct bnxt_plcmodes_cfg pmodes = { 0 };
2094 uint32_t ctx_enable_flag = 0;
2095 uint32_t enables = 0;
2097 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2098 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2102 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2106 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2108 if (BNXT_CHIP_P5(bp)) {
2109 int dflt_rxq = vnic->start_grp_id;
2110 struct bnxt_rx_ring_info *rxr;
2111 struct bnxt_cp_ring_info *cpr;
2112 struct bnxt_rx_queue *rxq;
2116 * The first active receive ring is used as the VNIC
2117 * default receive ring. If there are no active receive
2118 * rings (all corresponding receive queues are stopped),
2119 * the first receive ring is used.
2121 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2122 rxq = bp->eth_dev->data->rx_queues[i];
2123 if (rxq->rx_started) {
2129 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2133 req.default_rx_ring_id =
2134 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2135 req.default_cmpl_ring_id =
2136 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2137 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2138 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2139 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2140 enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2141 req.rx_csum_v2_mode =
2142 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2147 /* Only RSS support for now TBD: COS & LB */
2148 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2149 if (vnic->lb_rule != 0xffff)
2150 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2151 if (vnic->cos_rule != 0xffff)
2152 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2153 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2154 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2155 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2157 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2158 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2159 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2162 enables |= ctx_enable_flag;
2163 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2164 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2165 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2166 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2169 req.enables = rte_cpu_to_le_32(enables);
2170 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2171 req.mru = rte_cpu_to_le_16(vnic->mru);
2172 /* Configure default VNIC only once. */
2173 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2175 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2176 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2178 if (vnic->vlan_strip)
2180 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2183 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2184 if (vnic->rss_dflt_cr)
2185 req.flags |= rte_cpu_to_le_32(
2186 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2188 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2190 HWRM_CHECK_RESULT();
2193 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2198 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2202 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2203 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2205 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2206 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2209 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2212 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2213 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2214 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2216 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2218 HWRM_CHECK_RESULT();
2220 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2221 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2222 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2223 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2224 vnic->mru = rte_le_to_cpu_16(resp->mru);
2225 vnic->func_default = rte_le_to_cpu_32(
2226 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2227 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2228 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2229 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2230 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2231 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2232 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2239 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2240 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2244 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2245 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2246 bp->hwrm_cmd_resp_addr;
2248 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2250 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2251 HWRM_CHECK_RESULT();
2253 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2254 if (!BNXT_HAS_RING_GRPS(bp))
2255 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2256 else if (ctx_idx == 0)
2257 vnic->rss_rule = ctx_id;
2265 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2266 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2269 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2270 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2271 bp->hwrm_cmd_resp_addr;
2273 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2274 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2277 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2279 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2281 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2283 HWRM_CHECK_RESULT();
2289 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2293 if (BNXT_CHIP_P5(bp)) {
2296 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2297 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2299 vnic->fw_grp_ids[j]);
2300 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2302 vnic->num_lb_ctxts = 0;
2304 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2305 vnic->rss_rule = INVALID_HW_RING_ID;
2311 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2314 struct hwrm_vnic_free_input req = {.req_type = 0 };
2315 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2317 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2318 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2322 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2324 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2326 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2328 HWRM_CHECK_RESULT();
2331 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2332 /* Configure default VNIC again if necessary. */
2333 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2334 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2340 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2344 int nr_ctxs = vnic->num_lb_ctxts;
2345 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2346 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2348 for (i = 0; i < nr_ctxs; i++) {
2349 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2351 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2352 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2353 req.hash_mode_flags = vnic->hash_mode;
2355 req.hash_key_tbl_addr =
2356 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2358 req.ring_grp_tbl_addr =
2359 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2360 i * HW_HASH_INDEX_SIZE);
2361 req.ring_table_pair_index = i;
2362 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2364 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2367 HWRM_CHECK_RESULT();
2374 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2375 struct bnxt_vnic_info *vnic)
2378 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2379 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2381 if (!vnic->rss_table)
2384 if (BNXT_CHIP_P5(bp))
2385 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2387 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2389 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2390 req.hash_mode_flags = vnic->hash_mode;
2392 req.ring_grp_tbl_addr =
2393 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2394 req.hash_key_tbl_addr =
2395 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2396 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2397 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2399 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2401 HWRM_CHECK_RESULT();
2407 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2408 struct bnxt_vnic_info *vnic)
2411 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2412 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2415 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2416 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2420 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2422 req.flags = rte_cpu_to_le_32(
2423 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2425 req.enables = rte_cpu_to_le_32(
2426 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2428 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2429 size -= RTE_PKTMBUF_HEADROOM;
2430 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2432 req.jumbo_thresh = rte_cpu_to_le_16(size);
2433 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2435 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2437 HWRM_CHECK_RESULT();
2443 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2444 struct bnxt_vnic_info *vnic, bool enable)
2447 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2448 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2450 if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2452 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2456 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2457 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2461 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2464 req.enables = rte_cpu_to_le_32(
2465 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2466 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2467 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2468 req.flags = rte_cpu_to_le_32(
2469 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2470 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2471 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2472 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2473 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2474 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2475 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2476 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2477 req.min_agg_len = rte_cpu_to_le_32(512);
2479 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2481 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2483 HWRM_CHECK_RESULT();
2489 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2491 struct hwrm_func_cfg_input req = {0};
2492 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2495 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2496 req.enables = rte_cpu_to_le_32(
2497 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2498 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2499 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2501 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2503 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2504 HWRM_CHECK_RESULT();
2507 bp->pf->vf_info[vf].random_mac = false;
2512 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2516 struct hwrm_func_qstats_input req = {.req_type = 0};
2517 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2519 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2521 req.fid = rte_cpu_to_le_16(fid);
2523 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2525 HWRM_CHECK_RESULT();
2528 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2535 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2536 struct rte_eth_stats *stats,
2537 struct hwrm_func_qstats_output *func_qstats)
2540 struct hwrm_func_qstats_input req = {.req_type = 0};
2541 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2543 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2545 req.fid = rte_cpu_to_le_16(fid);
2547 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2549 HWRM_CHECK_RESULT();
2551 memcpy(func_qstats, resp,
2552 sizeof(struct hwrm_func_qstats_output));
2557 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2558 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2559 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2560 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2561 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2562 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2564 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2565 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2566 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2567 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2568 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2569 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2571 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2572 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2573 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2581 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2584 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2585 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2587 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2589 req.fid = rte_cpu_to_le_16(fid);
2591 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2593 HWRM_CHECK_RESULT();
2599 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2604 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2605 struct bnxt_tx_queue *txq;
2606 struct bnxt_rx_queue *rxq;
2607 struct bnxt_cp_ring_info *cpr;
2609 if (i >= bp->rx_cp_nr_rings) {
2610 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2613 rxq = bp->rx_queues[i];
2617 rc = bnxt_hwrm_stat_clear(bp, cpr);
2625 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2629 struct bnxt_cp_ring_info *cpr;
2631 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2633 cpr = bp->rx_queues[i]->cp_ring;
2634 if (BNXT_HAS_RING_GRPS(bp))
2635 bp->grp_info[i].fw_stats_ctx = -1;
2636 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2641 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2642 cpr = bp->tx_queues[i]->cp_ring;
2643 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2651 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2653 struct bnxt_cp_ring_info *cpr;
2657 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2658 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
2661 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
2662 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2668 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2669 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2672 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
2673 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2683 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2688 if (!BNXT_HAS_RING_GRPS(bp))
2691 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2693 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2696 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2704 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2706 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2708 bnxt_hwrm_ring_free(bp, cp_ring,
2709 HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2710 INVALID_HW_RING_ID);
2711 memset(cpr->cp_desc_ring, 0,
2712 cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2713 cpr->cp_raw_cons = 0;
2716 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2718 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2720 bnxt_hwrm_ring_free(bp, cp_ring,
2721 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2722 INVALID_HW_RING_ID);
2723 memset(cpr->cp_desc_ring, 0,
2724 cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2725 cpr->cp_raw_cons = 0;
2728 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2730 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2731 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2732 struct bnxt_ring *ring = rxr->rx_ring_struct;
2733 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2735 if (BNXT_HAS_RING_GRPS(bp))
2736 bnxt_hwrm_ring_grp_free(bp, queue_index);
2738 bnxt_hwrm_ring_free(bp, ring,
2739 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2740 cpr->cp_ring_struct->fw_ring_id);
2741 if (BNXT_HAS_RING_GRPS(bp))
2742 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2744 /* Check agg ring struct explicitly.
2745 * bnxt_need_agg_ring() returns the current state of offload flags,
2746 * but we may have to deal with agg ring struct before the offload
2747 * flags are updated.
2749 if (!bnxt_need_agg_ring(bp->eth_dev) || rxr->ag_ring_struct == NULL)
2752 ring = rxr->ag_ring_struct;
2753 bnxt_hwrm_ring_free(bp, ring,
2755 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2756 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2757 cpr->cp_ring_struct->fw_ring_id);
2758 if (BNXT_HAS_RING_GRPS(bp))
2759 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2762 bnxt_hwrm_stat_ctx_free(bp, cpr);
2764 bnxt_free_cp_ring(bp, cpr);
2766 if (BNXT_HAS_RING_GRPS(bp))
2767 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2770 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2773 struct hwrm_ring_reset_input req = {.req_type = 0 };
2774 struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2776 HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2778 req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2779 req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2780 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2782 HWRM_CHECK_RESULT();
2790 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2794 for (i = 0; i < bp->tx_cp_nr_rings; i++)
2795 bnxt_free_hwrm_tx_ring(bp, i);
2797 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2798 bnxt_free_hwrm_rx_ring(bp, i);
2803 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2808 if (!BNXT_HAS_RING_GRPS(bp))
2811 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2812 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2820 * HWRM utility functions
2823 void bnxt_free_hwrm_resources(struct bnxt *bp)
2825 /* Release memzone */
2826 rte_free(bp->hwrm_cmd_resp_addr);
2827 rte_free(bp->hwrm_short_cmd_req_addr);
2828 bp->hwrm_cmd_resp_addr = NULL;
2829 bp->hwrm_short_cmd_req_addr = NULL;
2830 bp->hwrm_cmd_resp_dma_addr = 0;
2831 bp->hwrm_short_cmd_req_dma_addr = 0;
2834 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2836 struct rte_pci_device *pdev = bp->pdev;
2837 char type[RTE_MEMZONE_NAMESIZE];
2839 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2840 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2841 bp->max_resp_len = BNXT_PAGE_SIZE;
2842 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2843 if (bp->hwrm_cmd_resp_addr == NULL)
2845 bp->hwrm_cmd_resp_dma_addr =
2846 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2847 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2849 "unable to map response address to physical memory\n");
2852 rte_spinlock_init(&bp->hwrm_lock);
2858 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2862 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2863 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2866 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2867 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2872 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2877 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2879 struct bnxt_filter_info *filter;
2882 STAILQ_FOREACH(filter, &vnic->filter, next) {
2883 rc = bnxt_clear_one_vnic_filter(bp, filter);
2884 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2885 bnxt_free_filter(bp, filter);
2891 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2893 struct bnxt_filter_info *filter;
2894 struct rte_flow *flow;
2897 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2898 flow = STAILQ_FIRST(&vnic->flow_list);
2899 filter = flow->filter;
2900 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2901 rc = bnxt_clear_one_vnic_filter(bp, filter);
2903 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2909 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2911 struct bnxt_filter_info *filter;
2914 STAILQ_FOREACH(filter, &vnic->filter, next) {
2915 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2916 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2918 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2919 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2922 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2931 bnxt_free_tunnel_ports(struct bnxt *bp)
2933 if (bp->vxlan_port_cnt)
2934 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2935 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2937 if (bp->geneve_port_cnt)
2938 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2939 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2942 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2946 if (bp->vnic_info == NULL)
2950 * Cleanup VNICs in reverse order, to make sure the L2 filter
2951 * from vnic0 is last to be cleaned up.
2953 for (i = bp->max_vnics - 1; i >= 0; i--) {
2954 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2956 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2959 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2961 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2963 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2965 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2967 bnxt_hwrm_vnic_free(bp, vnic);
2969 rte_free(vnic->fw_grp_ids);
2971 /* Ring resources */
2972 bnxt_free_all_hwrm_rings(bp);
2973 bnxt_free_all_hwrm_ring_grps(bp);
2974 bnxt_free_all_hwrm_stat_ctxs(bp);
2975 bnxt_free_tunnel_ports(bp);
2978 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2980 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2982 if ((conf_link_speed & RTE_ETH_LINK_SPEED_FIXED) == RTE_ETH_LINK_SPEED_AUTONEG)
2983 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2985 switch (conf_link_speed) {
2986 case RTE_ETH_LINK_SPEED_10M_HD:
2987 case RTE_ETH_LINK_SPEED_100M_HD:
2989 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2991 return hw_link_duplex;
2994 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2999 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
3002 uint16_t eth_link_speed = 0;
3004 if (conf_link_speed == RTE_ETH_LINK_SPEED_AUTONEG)
3005 return RTE_ETH_LINK_SPEED_AUTONEG;
3007 switch (conf_link_speed & ~RTE_ETH_LINK_SPEED_FIXED) {
3008 case RTE_ETH_LINK_SPEED_100M:
3009 case RTE_ETH_LINK_SPEED_100M_HD:
3012 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
3014 case RTE_ETH_LINK_SPEED_1G:
3016 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
3018 case RTE_ETH_LINK_SPEED_2_5G:
3020 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
3022 case RTE_ETH_LINK_SPEED_10G:
3024 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
3026 case RTE_ETH_LINK_SPEED_20G:
3028 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3030 case RTE_ETH_LINK_SPEED_25G:
3032 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3034 case RTE_ETH_LINK_SPEED_40G:
3036 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3038 case RTE_ETH_LINK_SPEED_50G:
3039 eth_link_speed = pam4_link ?
3040 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3041 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3043 case RTE_ETH_LINK_SPEED_100G:
3044 eth_link_speed = pam4_link ?
3045 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3046 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3048 case RTE_ETH_LINK_SPEED_200G:
3050 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3054 "Unsupported link speed %d; default to AUTO\n",
3058 return eth_link_speed;
3061 #define BNXT_SUPPORTED_SPEEDS (RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_100M_HD | \
3062 RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_2_5G | \
3063 RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_20G | RTE_ETH_LINK_SPEED_25G | \
3064 RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_50G | \
3065 RTE_ETH_LINK_SPEED_100G | RTE_ETH_LINK_SPEED_200G)
3067 static int bnxt_validate_link_speed(struct bnxt *bp)
3069 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3070 uint16_t port_id = bp->eth_dev->data->port_id;
3071 uint32_t link_speed_capa;
3074 if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG)
3077 link_speed_capa = bnxt_get_speed_capabilities(bp);
3079 if (link_speed & RTE_ETH_LINK_SPEED_FIXED) {
3080 one_speed = link_speed & ~RTE_ETH_LINK_SPEED_FIXED;
3082 if (one_speed & (one_speed - 1)) {
3084 "Invalid advertised speeds (%u) for port %u\n",
3085 link_speed, port_id);
3088 if ((one_speed & link_speed_capa) != one_speed) {
3090 "Unsupported advertised speed (%u) for port %u\n",
3091 link_speed, port_id);
3095 if (!(link_speed & link_speed_capa)) {
3097 "Unsupported advertised speeds (%u) for port %u\n",
3098 link_speed, port_id);
3106 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3110 if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG) {
3111 if (bp->link_info->support_speeds)
3112 return bp->link_info->support_speeds;
3113 link_speed = BNXT_SUPPORTED_SPEEDS;
3116 if (link_speed & RTE_ETH_LINK_SPEED_100M)
3117 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3118 if (link_speed & RTE_ETH_LINK_SPEED_100M_HD)
3119 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3120 if (link_speed & RTE_ETH_LINK_SPEED_1G)
3121 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3122 if (link_speed & RTE_ETH_LINK_SPEED_2_5G)
3123 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3124 if (link_speed & RTE_ETH_LINK_SPEED_10G)
3125 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3126 if (link_speed & RTE_ETH_LINK_SPEED_20G)
3127 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3128 if (link_speed & RTE_ETH_LINK_SPEED_25G)
3129 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3130 if (link_speed & RTE_ETH_LINK_SPEED_40G)
3131 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3132 if (link_speed & RTE_ETH_LINK_SPEED_50G)
3133 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3134 if (link_speed & RTE_ETH_LINK_SPEED_100G)
3135 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3136 if (link_speed & RTE_ETH_LINK_SPEED_200G)
3137 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3141 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3143 uint32_t eth_link_speed = RTE_ETH_SPEED_NUM_NONE;
3145 switch (hw_link_speed) {
3146 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3147 eth_link_speed = RTE_ETH_SPEED_NUM_100M;
3149 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3150 eth_link_speed = RTE_ETH_SPEED_NUM_1G;
3152 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3153 eth_link_speed = RTE_ETH_SPEED_NUM_2_5G;
3155 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3156 eth_link_speed = RTE_ETH_SPEED_NUM_10G;
3158 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3159 eth_link_speed = RTE_ETH_SPEED_NUM_20G;
3161 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3162 eth_link_speed = RTE_ETH_SPEED_NUM_25G;
3164 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3165 eth_link_speed = RTE_ETH_SPEED_NUM_40G;
3167 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3168 eth_link_speed = RTE_ETH_SPEED_NUM_50G;
3170 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3171 eth_link_speed = RTE_ETH_SPEED_NUM_100G;
3173 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3174 eth_link_speed = RTE_ETH_SPEED_NUM_200G;
3176 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3178 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3182 return eth_link_speed;
3185 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3187 uint16_t eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3189 switch (hw_link_duplex) {
3190 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3191 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3193 eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3195 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3196 eth_link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
3199 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3203 return eth_link_duplex;
3206 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3209 struct bnxt_link_info *link_info = bp->link_info;
3211 rc = bnxt_hwrm_port_phy_qcaps(bp);
3213 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3215 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3217 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3221 if (link_info->link_speed)
3223 bnxt_parse_hw_link_speed(link_info->link_speed);
3225 link->link_speed = RTE_ETH_SPEED_NUM_NONE;
3226 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3227 link->link_status = link_info->link_up;
3228 link->link_autoneg = link_info->auto_mode ==
3229 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3230 RTE_ETH_LINK_FIXED : RTE_ETH_LINK_AUTONEG;
3235 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3238 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3239 struct bnxt_link_info link_req;
3240 uint16_t speed, autoneg;
3242 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3245 rc = bnxt_validate_link_speed(bp);
3249 memset(&link_req, 0, sizeof(link_req));
3250 link_req.link_up = link_up;
3254 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3255 if (BNXT_CHIP_P5(bp) &&
3256 dev_conf->link_speeds == RTE_ETH_LINK_SPEED_40G) {
3257 /* 40G is not supported as part of media auto detect.
3258 * The speed should be forced and autoneg disabled
3259 * to configure 40G speed.
3261 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3265 /* No auto speeds and no auto_pam4_link. Disable autoneg */
3266 if (bp->link_info->auto_link_speed == 0 &&
3267 bp->link_info->link_signal_mode &&
3268 bp->link_info->auto_pam4_link_speeds == 0)
3271 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3272 bp->link_info->link_signal_mode);
3273 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3274 /* Autoneg can be done only when the FW allows. */
3275 if (autoneg == 1 && bp->link_info->support_auto_speeds) {
3276 link_req.phy_flags |=
3277 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3278 link_req.auto_link_speed_mask =
3279 bnxt_parse_eth_link_speed_mask(bp,
3280 dev_conf->link_speeds);
3282 if (bp->link_info->phy_type ==
3283 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3284 bp->link_info->phy_type ==
3285 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3286 bp->link_info->media_type ==
3287 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3288 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3292 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3293 /* If user wants a particular speed try that first. */
3295 link_req.link_speed = speed;
3296 else if (bp->link_info->force_pam4_link_speed)
3297 link_req.link_speed =
3298 bp->link_info->force_pam4_link_speed;
3299 else if (bp->link_info->auto_pam4_link_speeds)
3300 link_req.link_speed =
3301 bp->link_info->auto_pam4_link_speeds;
3302 else if (bp->link_info->support_pam4_speeds)
3303 link_req.link_speed =
3304 bp->link_info->support_pam4_speeds;
3305 else if (bp->link_info->force_link_speed)
3306 link_req.link_speed = bp->link_info->force_link_speed;
3308 link_req.link_speed = bp->link_info->auto_link_speed;
3309 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3310 * zero. Use the auto_link_speed.
3312 if (bp->link_info->auto_link_speed != 0 &&
3313 bp->link_info->auto_pam4_link_speeds == 0)
3314 link_req.link_speed = bp->link_info->auto_link_speed;
3316 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3317 link_req.auto_pause = bp->link_info->auto_pause;
3318 link_req.force_pause = bp->link_info->force_pause;
3321 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3324 "Set link config failed with rc %d\n", rc);
3331 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3333 struct hwrm_func_qcfg_input req = {0};
3334 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3337 bp->func_svif = BNXT_SVIF_INVALID;
3340 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3341 req.fid = rte_cpu_to_le_16(0xffff);
3343 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3345 HWRM_CHECK_RESULT();
3347 bp->vlan = rte_le_to_cpu_16(resp->vlan) & RTE_ETH_VLAN_ID_MAX;
3349 svif_info = rte_le_to_cpu_16(resp->svif_info);
3350 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3351 bp->func_svif = svif_info &
3352 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3354 flags = rte_le_to_cpu_16(resp->flags);
3355 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3356 bp->flags |= BNXT_FLAG_MULTI_HOST;
3359 !BNXT_VF_IS_TRUSTED(bp) &&
3360 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3361 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3362 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3363 } else if (BNXT_VF(bp) &&
3364 BNXT_VF_IS_TRUSTED(bp) &&
3365 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3366 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3367 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3371 *mtu = rte_le_to_cpu_16(resp->admin_mtu);
3373 switch (resp->port_partition_type) {
3374 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3375 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3376 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3378 bp->flags |= BNXT_FLAG_NPAR_PF;
3381 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3385 bp->legacy_db_size =
3386 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3393 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3395 struct hwrm_func_qcfg_input req = {0};
3396 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3399 if (!BNXT_VF_IS_TRUSTED(bp))
3405 bp->parent->fid = BNXT_PF_FID_INVALID;
3407 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3409 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3411 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3413 HWRM_CHECK_RESULT_SILENT();
3415 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3416 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3417 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3418 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3425 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3426 uint16_t *vnic_id, uint16_t *svif)
3428 struct hwrm_func_qcfg_input req = {0};
3429 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3433 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3434 req.fid = rte_cpu_to_le_16(fid);
3436 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3438 HWRM_CHECK_RESULT();
3441 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3443 svif_info = rte_le_to_cpu_16(resp->svif_info);
3444 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3445 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3452 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3454 struct hwrm_port_mac_qcfg_input req = {0};
3455 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3456 uint16_t port_svif_info;
3459 bp->port_svif = BNXT_SVIF_INVALID;
3461 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3464 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3466 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3468 HWRM_CHECK_RESULT_SILENT();
3470 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3471 if (port_svif_info &
3472 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3473 bp->port_svif = port_svif_info &
3474 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3481 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3482 struct bnxt_pf_resource_info *pf_resc)
3484 struct hwrm_func_cfg_input req = {0};
3485 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3489 enables = HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3490 HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU |
3491 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3492 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3493 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3494 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3495 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3496 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3497 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3498 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3500 if (BNXT_HAS_RING_GRPS(bp)) {
3501 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3502 req.num_hw_ring_grps =
3503 rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3504 } else if (BNXT_HAS_NQ(bp)) {
3505 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3506 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3509 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3510 req.admin_mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3511 req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
3512 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3513 req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3514 req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3515 req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3516 req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3517 req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3518 req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3519 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3520 req.fid = rte_cpu_to_le_16(0xffff);
3521 req.enables = rte_cpu_to_le_32(enables);
3523 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3525 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3527 HWRM_CHECK_RESULT();
3533 /* min values are the guaranteed resources and max values are subject
3534 * to availability. The strategy for now is to keep both min & max
3538 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3539 struct hwrm_func_vf_resource_cfg_input *req,
3542 req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3544 req->min_rsscos_ctx = req->max_rsscos_ctx;
3545 req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3546 req->min_stat_ctx = req->max_stat_ctx;
3547 req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3549 req->min_cmpl_rings = req->max_cmpl_rings;
3550 req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3551 req->min_tx_rings = req->max_tx_rings;
3552 req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3553 req->min_rx_rings = req->max_rx_rings;
3554 req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3555 req->min_l2_ctxs = req->max_l2_ctxs;
3556 /* TODO: For now, do not support VMDq/RFS on VFs. */
3557 req->max_vnics = rte_cpu_to_le_16(1);
3558 req->min_vnics = req->max_vnics;
3559 req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3561 req->min_hw_ring_grps = req->max_hw_ring_grps;
3563 rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3567 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3568 struct hwrm_func_cfg_input *req,
3571 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3572 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3573 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3574 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3575 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3576 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3577 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3578 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3579 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3580 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3582 req->admin_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3583 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3585 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3586 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3588 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3589 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3591 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3592 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3593 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3594 /* TODO: For now, do not support VMDq/RFS on VFs. */
3595 req->num_vnics = rte_cpu_to_le_16(1);
3596 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3600 /* Update the port wide resource values based on how many resources
3601 * got allocated to the VF.
3603 static int bnxt_update_max_resources(struct bnxt *bp,
3606 struct hwrm_func_qcfg_input req = {0};
3607 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3610 /* Get the actual allocated values now */
3611 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3612 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3613 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3614 HWRM_CHECK_RESULT();
3616 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3617 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3618 bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3619 bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3620 bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3621 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3622 bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3629 /* Update the PF resource values based on how many resources
3630 * got allocated to it.
3632 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3634 struct hwrm_func_qcfg_input req = {0};
3635 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3638 /* Get the actual allocated values now */
3639 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3640 req.fid = rte_cpu_to_le_16(0xffff);
3641 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3642 HWRM_CHECK_RESULT();
3644 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3645 bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3646 bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3647 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3648 bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3649 bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3650 bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3651 bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3658 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3660 struct hwrm_func_qcfg_input req = {0};
3661 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3664 /* Check for zero MAC address */
3665 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3666 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3667 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3668 HWRM_CHECK_RESULT();
3669 rc = rte_le_to_cpu_16(resp->vlan);
3676 static int bnxt_query_pf_resources(struct bnxt *bp,
3677 struct bnxt_pf_resource_info *pf_resc)
3679 struct hwrm_func_qcfg_input req = {0};
3680 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3683 /* And copy the allocated numbers into the pf struct */
3684 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3685 req.fid = rte_cpu_to_le_16(0xffff);
3686 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3687 HWRM_CHECK_RESULT();
3689 pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3690 pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3691 pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3692 pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3693 pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3694 pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3695 pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3696 bp->pf->evb_mode = resp->evb_mode;
3704 bnxt_calculate_pf_resources(struct bnxt *bp,
3705 struct bnxt_pf_resource_info *pf_resc,
3709 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3710 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3711 pf_resc->num_cp_rings = bp->max_cp_rings;
3712 pf_resc->num_tx_rings = bp->max_tx_rings;
3713 pf_resc->num_rx_rings = bp->max_rx_rings;
3714 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3715 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3720 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3721 bp->max_rsscos_ctx % (num_vfs + 1);
3722 pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3723 bp->max_stat_ctx % (num_vfs + 1);
3724 pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3725 bp->max_cp_rings % (num_vfs + 1);
3726 pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3727 bp->max_tx_rings % (num_vfs + 1);
3728 pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3729 bp->max_rx_rings % (num_vfs + 1);
3730 pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3731 bp->max_l2_ctx % (num_vfs + 1);
3732 pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3733 bp->max_ring_grps % (num_vfs + 1);
3736 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3738 struct bnxt_pf_resource_info pf_resc = { 0 };
3742 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3746 rc = bnxt_hwrm_func_qcaps(bp);
3750 bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3752 bp->pf->func_cfg_flags &=
3753 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3754 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3755 bp->pf->func_cfg_flags |=
3756 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3758 rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3762 rc = bnxt_update_max_resources_pf_only(bp);
3768 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3770 size_t req_buf_sz, sz;
3773 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3774 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3775 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3776 if (bp->pf->vf_req_buf == NULL) {
3780 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3781 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3783 for (i = 0; i < num_vfs; i++)
3784 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3785 (i * HWRM_MAX_REQ_LEN);
3787 rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3789 rte_free(bp->pf->vf_req_buf);
3795 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3797 struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3798 struct hwrm_func_vf_resource_cfg_input req = {0};
3801 bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3802 bp->pf->active_vfs = 0;
3803 for (i = 0; i < num_vfs; i++) {
3804 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3805 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3806 rc = bnxt_hwrm_send_message(bp,
3810 if (rc || resp->error_code) {
3812 "Failed to initialize VF %d\n", i);
3814 "Not all VFs available. (%d, %d)\n",
3815 rc, resp->error_code);
3818 /* If the first VF configuration itself fails,
3819 * unregister the vf_fwd_request buffer.
3822 bnxt_hwrm_func_buf_unrgtr(bp);
3827 /* Update the max resource values based on the resource values
3828 * allocated to the VF.
3830 bnxt_update_max_resources(bp, i);
3831 bp->pf->active_vfs++;
3832 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3839 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3841 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3842 struct hwrm_func_cfg_input req = {0};
3845 bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3847 bp->pf->active_vfs = 0;
3848 for (i = 0; i < num_vfs; i++) {
3849 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3850 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3851 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3852 rc = bnxt_hwrm_send_message(bp,
3857 /* Clear enable flag for next pass */
3858 req.enables &= ~rte_cpu_to_le_32(
3859 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3861 if (rc || resp->error_code) {
3863 "Failed to initialize VF %d\n", i);
3865 "Not all VFs available. (%d, %d)\n",
3866 rc, resp->error_code);
3869 /* If the first VF configuration itself fails,
3870 * unregister the vf_fwd_request buffer.
3873 bnxt_hwrm_func_buf_unrgtr(bp);
3879 /* Update the max resource values based on the resource values
3880 * allocated to the VF.
3882 bnxt_update_max_resources(bp, i);
3883 bp->pf->active_vfs++;
3884 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3891 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3893 if (bp->flags & BNXT_FLAG_NEW_RM)
3894 bnxt_process_vf_resc_config_new(bp, num_vfs);
3896 bnxt_process_vf_resc_config_old(bp, num_vfs);
3900 bnxt_update_pf_resources(struct bnxt *bp,
3901 struct bnxt_pf_resource_info *pf_resc)
3903 bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3904 bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3905 bp->max_cp_rings = pf_resc->num_cp_rings;
3906 bp->max_tx_rings = pf_resc->num_tx_rings;
3907 bp->max_rx_rings = pf_resc->num_rx_rings;
3908 bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3912 bnxt_configure_pf_resources(struct bnxt *bp,
3913 struct bnxt_pf_resource_info *pf_resc)
3916 * We're using STD_TX_RING_MODE here which will limit the TX
3917 * rings. This will allow QoS to function properly. Not setting this
3918 * will cause PF rings to break bandwidth settings.
3920 bp->pf->func_cfg_flags &=
3921 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3922 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3923 bp->pf->func_cfg_flags |=
3924 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3925 return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3928 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3930 struct bnxt_pf_resource_info pf_resc = { 0 };
3934 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3938 rc = bnxt_hwrm_func_qcaps(bp);
3942 bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3944 rc = bnxt_configure_pf_resources(bp, &pf_resc);
3948 rc = bnxt_query_pf_resources(bp, &pf_resc);
3953 * Now, create and register a buffer to hold forwarded VF requests
3955 rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3959 bnxt_configure_vf_resources(bp, num_vfs);
3961 bnxt_update_pf_resources(bp, &pf_resc);
3966 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3968 struct hwrm_func_cfg_input req = {0};
3969 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3972 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3974 req.fid = rte_cpu_to_le_16(0xffff);
3975 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3976 req.evb_mode = bp->pf->evb_mode;
3978 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3979 HWRM_CHECK_RESULT();
3985 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3986 uint8_t tunnel_type)
3988 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3989 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3992 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3993 req.tunnel_type = tunnel_type;
3994 req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3995 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3996 HWRM_CHECK_RESULT();
3998 switch (tunnel_type) {
3999 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
4000 bp->vxlan_fw_dst_port_id =
4001 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
4002 bp->vxlan_port = port;
4004 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
4005 bp->geneve_fw_dst_port_id =
4006 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
4007 bp->geneve_port = port;
4018 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4019 uint8_t tunnel_type)
4021 struct hwrm_tunnel_dst_port_free_input req = {0};
4022 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4025 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4027 req.tunnel_type = tunnel_type;
4028 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4029 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4031 HWRM_CHECK_RESULT();
4035 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4037 bp->vxlan_port_cnt = 0;
4041 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4042 bp->geneve_port = 0;
4043 bp->geneve_port_cnt = 0;
4049 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4052 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4053 struct hwrm_func_cfg_input req = {0};
4056 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4058 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4059 req.flags = rte_cpu_to_le_32(flags);
4060 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4062 HWRM_CHECK_RESULT();
4068 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4070 uint32_t *flag = flagp;
4072 vnic->flags = *flag;
4075 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4077 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4080 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4082 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4083 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4086 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4088 req.req_buf_num_pages = rte_cpu_to_le_16(1);
4089 req.req_buf_page_size =
4090 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4091 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4092 req.req_buf_page_addr0 =
4093 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4094 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4096 "unable to map buffer address to physical memory\n");
4101 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4103 HWRM_CHECK_RESULT();
4109 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4112 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4113 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4115 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4118 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4120 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4122 HWRM_CHECK_RESULT();
4128 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4130 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4131 struct hwrm_func_cfg_input req = {0};
4134 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4136 req.fid = rte_cpu_to_le_16(0xffff);
4137 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4138 req.enables = rte_cpu_to_le_32(
4139 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4140 req.async_event_cr = rte_cpu_to_le_16(
4141 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4142 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4144 HWRM_CHECK_RESULT();
4150 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4152 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4153 struct hwrm_func_vf_cfg_input req = {0};
4156 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4158 req.enables = rte_cpu_to_le_32(
4159 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4160 req.async_event_cr = rte_cpu_to_le_16(
4161 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4162 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4164 HWRM_CHECK_RESULT();
4170 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4172 struct hwrm_func_cfg_input req = {0};
4173 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4174 uint16_t dflt_vlan, fid;
4175 uint32_t func_cfg_flags;
4178 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4181 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4182 fid = bp->pf->vf_info[vf].fid;
4183 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4185 fid = rte_cpu_to_le_16(0xffff);
4186 func_cfg_flags = bp->pf->func_cfg_flags;
4187 dflt_vlan = bp->vlan;
4190 req.flags = rte_cpu_to_le_32(func_cfg_flags);
4191 req.fid = rte_cpu_to_le_16(fid);
4192 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4193 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4195 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4197 HWRM_CHECK_RESULT();
4203 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4204 uint16_t max_bw, uint16_t enables)
4206 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4207 struct hwrm_func_cfg_input req = {0};
4210 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4212 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4213 req.enables |= rte_cpu_to_le_32(enables);
4214 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4215 req.max_bw = rte_cpu_to_le_32(max_bw);
4216 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4218 HWRM_CHECK_RESULT();
4224 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4226 struct hwrm_func_cfg_input req = {0};
4227 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4230 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4232 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4233 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4234 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4235 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4237 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4239 HWRM_CHECK_RESULT();
4245 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4250 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4252 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4257 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4258 void *encaped, size_t ec_size)
4261 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4262 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4264 if (ec_size > sizeof(req.encap_request))
4267 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4269 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4270 memcpy(req.encap_request, encaped, ec_size);
4272 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4274 HWRM_CHECK_RESULT();
4280 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4281 struct rte_ether_addr *mac)
4283 struct hwrm_func_qcfg_input req = {0};
4284 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4287 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4289 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4290 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4292 HWRM_CHECK_RESULT();
4294 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4301 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4302 void *encaped, size_t ec_size)
4305 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4306 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4308 if (ec_size > sizeof(req.encap_request))
4311 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4313 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4314 memcpy(req.encap_request, encaped, ec_size);
4316 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4318 HWRM_CHECK_RESULT();
4324 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4326 /* One of the HW stat values that make up this counter was zero as
4327 * returned by HW in this iteration, so use the previous
4328 * iteration's counter value
4330 if (*prev_cntr && *cntr == 0)
4336 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4337 struct bnxt_ring_stats *ring_stats, bool rx)
4340 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4341 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4343 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4345 req.stat_ctx_id = rte_cpu_to_le_32(cid);
4347 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4349 HWRM_CHECK_RESULT();
4352 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4354 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4355 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4356 &prev_stats->rx_ucast_pkts);
4358 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4359 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4360 &prev_stats->rx_mcast_pkts);
4362 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4363 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4364 &prev_stats->rx_bcast_pkts);
4366 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4367 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4368 &prev_stats->rx_ucast_bytes);
4370 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4371 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4372 &prev_stats->rx_mcast_bytes);
4374 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4375 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4376 &prev_stats->rx_bcast_bytes);
4378 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4379 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4380 &prev_stats->rx_discard_pkts);
4382 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4383 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4384 &prev_stats->rx_error_pkts);
4386 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4387 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4388 &prev_stats->rx_agg_pkts);
4390 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4391 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4392 &prev_stats->rx_agg_bytes);
4394 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4395 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4396 &prev_stats->rx_agg_events);
4398 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4399 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4400 &prev_stats->rx_agg_aborts);
4402 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4404 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4405 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4406 &prev_stats->tx_ucast_pkts);
4408 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4409 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4410 &prev_stats->tx_mcast_pkts);
4412 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4413 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4414 &prev_stats->tx_bcast_pkts);
4416 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4417 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4418 &prev_stats->tx_ucast_bytes);
4420 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4421 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4422 &prev_stats->tx_mcast_bytes);
4424 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4425 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4426 &prev_stats->tx_bcast_bytes);
4428 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4429 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4430 &prev_stats->tx_discard_pkts);
4438 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4440 struct hwrm_port_qstats_input req = {0};
4441 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4442 struct bnxt_pf_info *pf = bp->pf;
4445 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4447 req.port_id = rte_cpu_to_le_16(pf->port_id);
4448 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4449 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4450 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4452 HWRM_CHECK_RESULT();
4458 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4460 struct hwrm_port_clr_stats_input req = {0};
4461 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4462 struct bnxt_pf_info *pf = bp->pf;
4465 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4466 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4467 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4470 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4472 req.port_id = rte_cpu_to_le_16(pf->port_id);
4473 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4475 HWRM_CHECK_RESULT();
4481 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4483 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4484 struct hwrm_port_led_qcaps_input req = {0};
4490 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4491 req.port_id = bp->pf->port_id;
4492 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4494 HWRM_CHECK_RESULT_SILENT();
4496 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4499 bp->leds->num_leds = resp->num_leds;
4500 memcpy(bp->leds, &resp->led0_id,
4501 sizeof(bp->leds[0]) * bp->leds->num_leds);
4502 for (i = 0; i < bp->leds->num_leds; i++) {
4503 struct bnxt_led_info *led = &bp->leds[i];
4505 uint16_t caps = led->led_state_caps;
4507 if (!led->led_group_id ||
4508 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4509 bp->leds->num_leds = 0;
4520 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4522 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4523 struct hwrm_port_led_cfg_input req = {0};
4524 struct bnxt_led_cfg *led_cfg;
4525 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4526 uint16_t duration = 0;
4529 if (!bp->leds->num_leds || BNXT_VF(bp))
4532 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4535 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4536 duration = rte_cpu_to_le_16(500);
4538 req.port_id = bp->pf->port_id;
4539 req.num_leds = bp->leds->num_leds;
4540 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4541 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4542 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4543 led_cfg->led_id = bp->leds[i].led_id;
4544 led_cfg->led_state = led_state;
4545 led_cfg->led_blink_on = duration;
4546 led_cfg->led_blink_off = duration;
4547 led_cfg->led_group_id = bp->leds[i].led_group_id;
4550 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4552 HWRM_CHECK_RESULT();
4558 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4562 struct hwrm_nvm_get_dir_info_input req = {0};
4563 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4565 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4567 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4569 HWRM_CHECK_RESULT();
4571 *entries = rte_le_to_cpu_32(resp->entries);
4572 *length = rte_le_to_cpu_32(resp->entry_length);
4578 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4581 uint32_t dir_entries;
4582 uint32_t entry_length;
4585 rte_iova_t dma_handle;
4586 struct hwrm_nvm_get_dir_entries_input req = {0};
4587 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4589 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4593 *data++ = dir_entries;
4594 *data++ = entry_length;
4596 memset(data, 0xff, len);
4598 buflen = dir_entries * entry_length;
4599 buf = rte_malloc("nvm_dir", buflen, 0);
4602 dma_handle = rte_malloc_virt2iova(buf);
4603 if (dma_handle == RTE_BAD_IOVA) {
4606 "unable to map response address to physical memory\n");
4609 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4610 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4611 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4614 memcpy(data, buf, len > buflen ? buflen : len);
4617 HWRM_CHECK_RESULT();
4623 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4624 uint32_t offset, uint32_t length,
4629 rte_iova_t dma_handle;
4630 struct hwrm_nvm_read_input req = {0};
4631 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4633 buf = rte_malloc("nvm_item", length, 0);
4637 dma_handle = rte_malloc_virt2iova(buf);
4638 if (dma_handle == RTE_BAD_IOVA) {
4641 "unable to map response address to physical memory\n");
4644 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4645 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4646 req.dir_idx = rte_cpu_to_le_16(index);
4647 req.offset = rte_cpu_to_le_32(offset);
4648 req.len = rte_cpu_to_le_32(length);
4649 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4651 memcpy(data, buf, length);
4654 HWRM_CHECK_RESULT();
4660 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4663 struct hwrm_nvm_erase_dir_entry_input req = {0};
4664 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4666 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4667 req.dir_idx = rte_cpu_to_le_16(index);
4668 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4669 HWRM_CHECK_RESULT();
4675 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4676 uint16_t dir_ordinal, uint16_t dir_ext,
4677 uint16_t dir_attr, const uint8_t *data,
4681 struct hwrm_nvm_write_input req = {0};
4682 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4683 rte_iova_t dma_handle;
4686 buf = rte_malloc("nvm_write", data_len, 0);
4690 dma_handle = rte_malloc_virt2iova(buf);
4691 if (dma_handle == RTE_BAD_IOVA) {
4694 "unable to map response address to physical memory\n");
4697 memcpy(buf, data, data_len);
4699 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4701 req.dir_type = rte_cpu_to_le_16(dir_type);
4702 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4703 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4704 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4705 req.dir_data_length = rte_cpu_to_le_32(data_len);
4706 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4708 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4711 HWRM_CHECK_RESULT();
4718 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4720 uint32_t *count = cbdata;
4722 *count = *count + 1;
4725 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4726 struct bnxt_vnic_info *vnic __rte_unused)
4731 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4735 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4736 &count, bnxt_vnic_count_hwrm_stub);
4741 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4744 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4745 struct hwrm_func_vf_vnic_ids_query_output *resp =
4746 bp->hwrm_cmd_resp_addr;
4749 /* First query all VNIC ids */
4750 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4752 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4753 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4754 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4756 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4759 "unable to map VNIC ID table address to physical memory\n");
4762 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4763 HWRM_CHECK_RESULT();
4764 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4772 * This function queries the VNIC IDs for a specified VF. It then calls
4773 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4774 * Then it calls the hwrm_cb function to program this new vnic configuration.
4776 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4777 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4778 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4780 struct bnxt_vnic_info vnic;
4782 int i, num_vnic_ids;
4787 /* First query all VNIC ids */
4788 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4789 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4790 RTE_CACHE_LINE_SIZE);
4791 if (vnic_ids == NULL)
4794 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4795 rte_mem_lock_page(((char *)vnic_ids) + sz);
4797 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4799 if (num_vnic_ids < 0)
4800 return num_vnic_ids;
4802 /* Retrieve VNIC, update bd_stall then update */
4804 for (i = 0; i < num_vnic_ids; i++) {
4805 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4806 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4807 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4810 if (vnic.mru <= 4) /* Indicates unallocated */
4813 vnic_cb(&vnic, cbdata);
4815 rc = hwrm_cb(bp, &vnic);
4825 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4828 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4829 struct hwrm_func_cfg_input req = {0};
4832 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4834 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4835 req.enables |= rte_cpu_to_le_32(
4836 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4837 req.vlan_antispoof_mode = on ?
4838 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4839 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4840 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4842 HWRM_CHECK_RESULT();
4848 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4850 struct bnxt_vnic_info vnic;
4853 int num_vnic_ids, i;
4857 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4858 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4859 RTE_CACHE_LINE_SIZE);
4860 if (vnic_ids == NULL)
4863 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4864 rte_mem_lock_page(((char *)vnic_ids) + sz);
4866 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4872 * Loop through to find the default VNIC ID.
4873 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4874 * by sending the hwrm_func_qcfg command to the firmware.
4876 for (i = 0; i < num_vnic_ids; i++) {
4877 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4878 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4879 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4880 bp->pf->first_vf_id + vf);
4883 if (vnic.func_default) {
4885 return vnic.fw_vnic_id;
4888 /* Could not find a default VNIC. */
4889 PMD_DRV_LOG(ERR, "No default VNIC\n");
4895 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4897 struct bnxt_filter_info *filter)
4900 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4901 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4902 uint32_t enables = 0;
4904 if (filter->fw_em_filter_id != UINT64_MAX)
4905 bnxt_hwrm_clear_em_filter(bp, filter);
4907 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4909 req.flags = rte_cpu_to_le_32(filter->flags);
4911 enables = filter->enables |
4912 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4913 req.dst_id = rte_cpu_to_le_16(dst_id);
4915 if (filter->ip_addr_type) {
4916 req.ip_addr_type = filter->ip_addr_type;
4917 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4920 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4921 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4923 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4924 memcpy(req.src_macaddr, filter->src_macaddr,
4925 RTE_ETHER_ADDR_LEN);
4927 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4928 memcpy(req.dst_macaddr, filter->dst_macaddr,
4929 RTE_ETHER_ADDR_LEN);
4931 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4932 req.ovlan_vid = filter->l2_ovlan;
4934 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4935 req.ivlan_vid = filter->l2_ivlan;
4937 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4938 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4940 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4941 req.ip_protocol = filter->ip_protocol;
4943 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4944 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4946 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4947 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4949 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4950 req.src_port = rte_cpu_to_be_16(filter->src_port);
4952 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4953 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4955 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4956 req.mirror_vnic_id = filter->mirror_vnic_id;
4958 req.enables = rte_cpu_to_le_32(enables);
4960 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4962 HWRM_CHECK_RESULT();
4964 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4970 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4973 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4974 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4976 if (filter->fw_em_filter_id == UINT64_MAX)
4979 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4981 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4983 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4985 HWRM_CHECK_RESULT();
4988 filter->fw_em_filter_id = UINT64_MAX;
4989 filter->fw_l2_filter_id = UINT64_MAX;
4994 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4996 struct bnxt_filter_info *filter)
4999 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
5000 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
5001 bp->hwrm_cmd_resp_addr;
5002 uint32_t enables = 0;
5004 if (filter->fw_ntuple_filter_id != UINT64_MAX)
5005 bnxt_hwrm_clear_ntuple_filter(bp, filter);
5007 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
5009 req.flags = rte_cpu_to_le_32(filter->flags);
5011 enables = filter->enables |
5012 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
5013 req.dst_id = rte_cpu_to_le_16(dst_id);
5015 if (filter->ip_addr_type) {
5016 req.ip_addr_type = filter->ip_addr_type;
5018 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
5021 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5022 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5024 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5025 memcpy(req.src_macaddr, filter->src_macaddr,
5026 RTE_ETHER_ADDR_LEN);
5028 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5029 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5031 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5032 req.ip_protocol = filter->ip_protocol;
5034 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5035 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5037 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5038 req.src_ipaddr_mask[0] =
5039 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5041 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5042 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5044 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5045 req.dst_ipaddr_mask[0] =
5046 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5048 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5049 req.src_port = rte_cpu_to_le_16(filter->src_port);
5051 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5052 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5054 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5055 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5057 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5058 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5060 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5061 req.mirror_vnic_id = filter->mirror_vnic_id;
5063 req.enables = rte_cpu_to_le_32(enables);
5065 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5067 HWRM_CHECK_RESULT();
5069 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5070 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5076 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5077 struct bnxt_filter_info *filter)
5080 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5081 struct hwrm_cfa_ntuple_filter_free_output *resp =
5082 bp->hwrm_cmd_resp_addr;
5084 if (filter->fw_ntuple_filter_id == UINT64_MAX)
5087 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5089 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5091 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5093 HWRM_CHECK_RESULT();
5096 filter->fw_ntuple_filter_id = UINT64_MAX;
5102 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5104 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5105 uint8_t *rxq_state = bp->eth_dev->data->rx_queue_state;
5106 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5107 struct bnxt_rx_queue **rxqs = bp->rx_queues;
5108 uint16_t *ring_tbl = vnic->rss_table;
5109 int nr_ctxs = vnic->num_lb_ctxts;
5110 int max_rings = bp->rx_nr_rings;
5114 for (i = 0, k = 0; i < nr_ctxs; i++) {
5115 struct bnxt_rx_ring_info *rxr;
5116 struct bnxt_cp_ring_info *cpr;
5118 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5120 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5121 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5122 req.hash_mode_flags = vnic->hash_mode;
5124 req.ring_grp_tbl_addr =
5125 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5126 i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5127 2 * sizeof(*ring_tbl));
5128 req.hash_key_tbl_addr =
5129 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5131 req.ring_table_pair_index = i;
5132 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5134 for (j = 0; j < 64; j++) {
5137 /* Find next active ring. */
5138 for (cnt = 0; cnt < max_rings; cnt++) {
5139 if (rxq_state[k] != RTE_ETH_QUEUE_STATE_STOPPED)
5141 if (++k == max_rings)
5145 /* Return if no rings are active. */
5146 if (cnt == max_rings) {
5151 /* Add rx/cp ring pair to RSS table. */
5152 rxr = rxqs[k]->rx_ring;
5153 cpr = rxqs[k]->cp_ring;
5155 ring_id = rxr->rx_ring_struct->fw_ring_id;
5156 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5157 ring_id = cpr->cp_ring_struct->fw_ring_id;
5158 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5160 if (++k == max_rings)
5163 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5166 HWRM_CHECK_RESULT();
5173 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5175 unsigned int rss_idx, fw_idx, i;
5177 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5180 if (!(vnic->rss_table && vnic->hash_type))
5183 if (BNXT_CHIP_P5(bp))
5184 return bnxt_vnic_rss_configure_p5(bp, vnic);
5187 * Fill the RSS hash & redirection table with
5188 * ring group ids for all VNICs
5190 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5191 rss_idx++, fw_idx++) {
5192 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5193 fw_idx %= bp->rx_cp_nr_rings;
5194 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5199 if (i == bp->rx_cp_nr_rings)
5202 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5205 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5208 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5209 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5213 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5215 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5216 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5218 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5219 req->num_cmpl_dma_aggr_during_int =
5220 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5222 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5224 /* min timer set to 1/2 of interrupt timer */
5225 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5227 /* buf timer set to 1/4 of interrupt timer */
5228 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5230 req->cmpl_aggr_dma_tmr_during_int =
5231 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5233 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5234 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5235 req->flags = rte_cpu_to_le_16(flags);
5238 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5239 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5241 struct hwrm_ring_aggint_qcaps_input req = {0};
5242 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5247 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5248 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5249 HWRM_CHECK_RESULT();
5251 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5252 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5254 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5255 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5256 agg_req->flags = rte_cpu_to_le_16(flags);
5258 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5259 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5260 agg_req->enables = rte_cpu_to_le_32(enables);
5266 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5267 struct bnxt_coal *coal, uint16_t ring_id)
5269 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5270 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5271 bp->hwrm_cmd_resp_addr;
5274 /* Set ring coalesce parameters only for 100G NICs */
5275 if (BNXT_CHIP_P5(bp)) {
5276 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5278 } else if (bnxt_stratus_device(bp)) {
5279 bnxt_hwrm_set_coal_params(coal, &req);
5285 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5287 req.ring_id = rte_cpu_to_le_16(ring_id);
5288 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5289 HWRM_CHECK_RESULT();
5294 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5295 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5297 struct hwrm_func_backing_store_qcaps_input req = {0};
5298 struct hwrm_func_backing_store_qcaps_output *resp =
5299 bp->hwrm_cmd_resp_addr;
5300 struct bnxt_ctx_pg_info *ctx_pg;
5301 struct bnxt_ctx_mem_info *ctx;
5302 int total_alloc_len;
5303 int rc, i, tqm_rings;
5305 if (!BNXT_CHIP_P5(bp) ||
5306 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5311 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5312 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5313 HWRM_CHECK_RESULT_SILENT();
5315 total_alloc_len = sizeof(*ctx);
5316 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5317 RTE_CACHE_LINE_SIZE);
5323 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5324 ctx->qp_min_qp1_entries =
5325 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5326 ctx->qp_max_l2_entries =
5327 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5328 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5329 ctx->srq_max_l2_entries =
5330 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5331 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5332 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5333 ctx->cq_max_l2_entries =
5334 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5335 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5336 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5337 ctx->vnic_max_vnic_entries =
5338 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5339 ctx->vnic_max_ring_table_entries =
5340 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5341 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5342 ctx->stat_max_entries =
5343 rte_le_to_cpu_32(resp->stat_max_entries);
5344 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5345 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5346 ctx->tqm_min_entries_per_ring =
5347 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5348 ctx->tqm_max_entries_per_ring =
5349 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5350 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5351 if (!ctx->tqm_entries_multiple)
5352 ctx->tqm_entries_multiple = 1;
5353 ctx->mrav_max_entries =
5354 rte_le_to_cpu_32(resp->mrav_max_entries);
5355 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5356 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5357 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5358 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5360 ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5361 RTE_MIN(ctx->tqm_fp_rings_count,
5362 BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5365 /* Check if the ext ring count needs to be counted.
5366 * Ext ring count is available only with new FW so we should not
5367 * look at the field on older FW.
5369 if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5370 bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5371 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5372 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5373 ctx->tqm_fp_rings_count);
5376 tqm_rings = ctx->tqm_fp_rings_count + 1;
5378 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5379 sizeof(*ctx_pg) * tqm_rings,
5380 RTE_CACHE_LINE_SIZE);
5385 for (i = 0; i < tqm_rings; i++, ctx_pg++)
5386 ctx->tqm_mem[i] = ctx_pg;
5394 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5396 struct hwrm_func_backing_store_cfg_input req = {0};
5397 struct hwrm_func_backing_store_cfg_output *resp =
5398 bp->hwrm_cmd_resp_addr;
5399 struct bnxt_ctx_mem_info *ctx = bp->ctx;
5400 struct bnxt_ctx_pg_info *ctx_pg;
5401 uint32_t *num_entries;
5410 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5411 req.enables = rte_cpu_to_le_32(enables);
5413 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5414 ctx_pg = &ctx->qp_mem;
5415 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5416 req.qp_num_qp1_entries =
5417 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5418 req.qp_num_l2_entries =
5419 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5420 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5421 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5422 &req.qpc_pg_size_qpc_lvl,
5426 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5427 ctx_pg = &ctx->srq_mem;
5428 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5429 req.srq_num_l2_entries =
5430 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5431 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5432 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5433 &req.srq_pg_size_srq_lvl,
5437 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5438 ctx_pg = &ctx->cq_mem;
5439 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5440 req.cq_num_l2_entries =
5441 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5442 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5443 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5444 &req.cq_pg_size_cq_lvl,
5448 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5449 ctx_pg = &ctx->vnic_mem;
5450 req.vnic_num_vnic_entries =
5451 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5452 req.vnic_num_ring_table_entries =
5453 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5454 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5455 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5456 &req.vnic_pg_size_vnic_lvl,
5457 &req.vnic_page_dir);
5460 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5461 ctx_pg = &ctx->stat_mem;
5462 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5463 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5464 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5465 &req.stat_pg_size_stat_lvl,
5466 &req.stat_page_dir);
5469 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5470 num_entries = &req.tqm_sp_num_entries;
5471 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5472 pg_dir = &req.tqm_sp_page_dir;
5473 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5474 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5475 if (!(enables & ena))
5478 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5480 ctx_pg = ctx->tqm_mem[i];
5481 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5482 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5485 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5486 /* DPDK does not need to configure MRAV and TIM type.
5487 * So we are skipping over MRAV and TIM. Skip to configure
5488 * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5490 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5491 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5492 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5493 &req.tqm_ring8_pg_size_tqm_ring_lvl,
5494 &req.tqm_ring8_page_dir);
5497 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5498 HWRM_CHECK_RESULT();
5504 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5506 struct hwrm_port_qstats_ext_input req = {0};
5507 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5508 struct bnxt_pf_info *pf = bp->pf;
5511 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5512 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5515 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5517 req.port_id = rte_cpu_to_le_16(pf->port_id);
5518 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5519 req.tx_stat_host_addr =
5520 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5522 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5524 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5525 req.rx_stat_host_addr =
5526 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5528 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5530 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5533 bp->fw_rx_port_stats_ext_size = 0;
5534 bp->fw_tx_port_stats_ext_size = 0;
5536 bp->fw_rx_port_stats_ext_size =
5537 rte_le_to_cpu_16(resp->rx_stat_size);
5538 bp->fw_tx_port_stats_ext_size =
5539 rte_le_to_cpu_16(resp->tx_stat_size);
5542 HWRM_CHECK_RESULT();
5549 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5551 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5552 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5553 bp->hwrm_cmd_resp_addr;
5556 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5557 req.tunnel_type = type;
5558 req.dest_fid = bp->fw_fid;
5559 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5560 HWRM_CHECK_RESULT();
5568 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5570 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5571 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5572 bp->hwrm_cmd_resp_addr;
5575 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5576 req.tunnel_type = type;
5577 req.dest_fid = bp->fw_fid;
5578 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5579 HWRM_CHECK_RESULT();
5586 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5588 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5589 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5590 bp->hwrm_cmd_resp_addr;
5593 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5594 req.src_fid = bp->fw_fid;
5595 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5596 HWRM_CHECK_RESULT();
5599 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5606 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5609 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5610 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5611 bp->hwrm_cmd_resp_addr;
5614 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5615 req.src_fid = bp->fw_fid;
5616 req.tunnel_type = tun_type;
5617 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5618 HWRM_CHECK_RESULT();
5621 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5623 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5630 int bnxt_hwrm_set_mac(struct bnxt *bp)
5632 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5633 struct hwrm_func_vf_cfg_input req = {0};
5639 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5642 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5643 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5645 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5647 HWRM_CHECK_RESULT();
5654 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5656 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5657 struct hwrm_func_drv_if_change_input req = {0};
5661 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5664 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5665 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5666 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5668 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5671 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5675 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5677 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5679 HWRM_CHECK_RESULT();
5680 flags = rte_le_to_cpu_32(resp->flags);
5686 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5687 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5688 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5694 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5696 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5697 struct bnxt_error_recovery_info *info = bp->recovery_info;
5698 struct hwrm_error_recovery_qcfg_input req = {0};
5703 /* Older FW does not have error recovery support */
5704 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5707 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5709 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5711 HWRM_CHECK_RESULT();
5713 flags = rte_le_to_cpu_32(resp->flags);
5714 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5715 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5716 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5717 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5719 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5720 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5725 /* FW returned values are in units of 100msec */
5726 info->driver_polling_freq =
5727 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5728 info->primary_func_wait_period =
5729 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5730 info->normal_func_wait_period =
5731 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5732 info->primary_func_wait_period_after_reset =
5733 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5734 info->max_bailout_time_after_reset =
5735 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5736 info->status_regs[BNXT_FW_STATUS_REG] =
5737 rte_le_to_cpu_32(resp->fw_health_status_reg);
5738 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5739 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5740 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5741 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5742 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5743 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5744 info->reg_array_cnt =
5745 rte_le_to_cpu_32(resp->reg_array_cnt);
5747 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5752 for (i = 0; i < info->reg_array_cnt; i++) {
5753 info->reset_reg[i] =
5754 rte_le_to_cpu_32(resp->reset_reg[i]);
5755 info->reset_reg_val[i] =
5756 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5757 info->delay_after_reset[i] =
5758 resp->delay_after_reset[i];
5763 /* Map the FW status registers */
5765 rc = bnxt_map_fw_health_status_regs(bp);
5768 rte_free(bp->recovery_info);
5769 bp->recovery_info = NULL;
5774 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5776 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5777 struct hwrm_fw_reset_input req = {0};
5783 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5785 req.embedded_proc_type =
5786 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5787 req.selfrst_status =
5788 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5789 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5791 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5794 HWRM_CHECK_RESULT();
5800 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5802 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5803 struct hwrm_port_ts_query_input req = {0};
5804 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5811 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5814 case BNXT_PTP_FLAGS_PATH_TX:
5815 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5817 case BNXT_PTP_FLAGS_PATH_RX:
5818 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5820 case BNXT_PTP_FLAGS_CURRENT_TIME:
5821 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5825 req.flags = rte_cpu_to_le_32(flags);
5826 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5828 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5830 HWRM_CHECK_RESULT();
5833 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5835 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5842 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5846 struct hwrm_cfa_counter_qcaps_input req = {0};
5847 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5849 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5851 "Not a PF or trusted VF. Command not supported\n");
5855 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5856 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5857 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5859 HWRM_CHECK_RESULT();
5861 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5867 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5870 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5871 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5873 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5875 "Not a PF or trusted VF. Command not supported\n");
5879 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5881 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5882 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5883 req.page_dir = rte_cpu_to_le_64(dma_addr);
5885 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5887 HWRM_CHECK_RESULT();
5889 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5890 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5897 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5900 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5901 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5903 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5905 "Not a PF or trusted VF. Command not supported\n");
5909 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5911 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5913 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5915 HWRM_CHECK_RESULT();
5921 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5922 uint16_t cntr, uint16_t ctx_id,
5923 uint32_t num_entries, bool enable)
5925 struct hwrm_cfa_counter_cfg_input req = {0};
5926 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5930 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5932 "Not a PF or trusted VF. Command not supported\n");
5936 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5938 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5939 req.counter_type = rte_cpu_to_le_16(cntr);
5940 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5941 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5942 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5943 if (dir == BNXT_DIR_RX)
5944 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5945 else if (dir == BNXT_DIR_TX)
5946 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5947 req.flags = rte_cpu_to_le_16(flags);
5948 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5949 req.num_entries = rte_cpu_to_le_32(num_entries);
5951 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5952 HWRM_CHECK_RESULT();
5958 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5959 enum bnxt_flow_dir dir,
5961 uint16_t num_entries)
5963 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5964 struct hwrm_cfa_counter_qstats_input req = {0};
5965 uint16_t flow_ctx_id = 0;
5969 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5971 "Not a PF or trusted VF. Command not supported\n");
5975 if (dir == BNXT_DIR_RX) {
5976 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5977 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5978 } else if (dir == BNXT_DIR_TX) {
5979 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5980 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5983 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5984 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5985 req.counter_type = rte_cpu_to_le_16(cntr);
5986 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5987 req.num_entries = rte_cpu_to_le_16(num_entries);
5988 req.flags = rte_cpu_to_le_16(flags);
5989 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5991 HWRM_CHECK_RESULT();
5997 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5998 uint16_t *first_vf_id)
6001 struct hwrm_func_qcaps_input req = {.req_type = 0 };
6002 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6004 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
6006 req.fid = rte_cpu_to_le_16(fid);
6008 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6010 HWRM_CHECK_RESULT();
6013 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
6020 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6022 struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6023 struct hwrm_cfa_pair_alloc_input req = {0};
6026 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6028 "Not a PF or trusted VF. Command not supported\n");
6032 HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6033 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6034 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6035 bp->eth_dev->data->name, rep_bp->vf_id);
6037 req.pf_b_id = rep_bp->parent_pf_idx;
6038 req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6039 rte_cpu_to_le_16(rep_bp->vf_id);
6040 req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6041 req.host_b_id = 1; /* TBD - Confirm if this is OK */
6043 req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6044 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6045 req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6046 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6047 req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6048 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6049 req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6050 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6052 req.q_ab = rep_bp->rep_q_r2f;
6053 req.q_ba = rep_bp->rep_q_f2r;
6054 req.fc_ab = rep_bp->rep_fc_r2f;
6055 req.fc_ba = rep_bp->rep_fc_f2r;
6057 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6058 HWRM_CHECK_RESULT();
6061 PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6062 BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6066 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6068 struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6069 struct hwrm_cfa_pair_free_input req = {0};
6072 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6074 "Not a PF or trusted VF. Command not supported\n");
6078 HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6079 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6080 bp->eth_dev->data->name, rep_bp->vf_id);
6081 req.pf_b_id = rep_bp->parent_pf_idx;
6082 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6083 req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6084 rte_cpu_to_le_16(rep_bp->vf_id);
6085 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6086 HWRM_CHECK_RESULT();
6088 PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6093 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6095 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6096 bp->hwrm_cmd_resp_addr;
6097 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6101 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6104 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6106 "Not a PF or trusted VF. Command not supported\n");
6110 HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6111 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6113 HWRM_CHECK_RESULT();
6114 flags = rte_le_to_cpu_32(resp->flags);
6117 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6118 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6120 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6125 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6126 uint32_t echo_req_data2)
6128 struct hwrm_func_echo_response_input req = {0};
6129 struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6132 HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6133 req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6134 req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6136 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6138 HWRM_CHECK_RESULT();
6144 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6146 struct hwrm_ver_get_input req = {.req_type = 0 };
6147 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6150 bp->max_req_len = HWRM_MAX_REQ_LEN;
6151 bp->max_resp_len = BNXT_PAGE_SIZE;
6152 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6154 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6155 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6156 req.hwrm_intf_min = HWRM_VERSION_MINOR;
6157 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6159 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6161 HWRM_CHECK_RESULT_SILENT();
6163 if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6171 int bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt *bp, uint16_t i2c_addr,
6172 uint16_t page_number, uint16_t start_addr,
6173 uint16_t data_length, uint8_t *buf)
6175 struct hwrm_port_phy_i2c_read_output *resp = bp->hwrm_cmd_resp_addr;
6176 struct hwrm_port_phy_i2c_read_input req = {0};
6177 uint32_t enables = HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET;
6178 int rc, byte_offset = 0;
6183 HWRM_PREP(&req, HWRM_PORT_PHY_I2C_READ, BNXT_USE_CHIMP_MB);
6184 req.i2c_slave_addr = i2c_addr;
6185 req.page_number = rte_cpu_to_le_16(page_number);
6186 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
6188 xfer_size = RTE_MIN(data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
6189 req.page_offset = rte_cpu_to_le_16(start_addr + byte_offset);
6190 req.data_length = xfer_size;
6191 req.enables = rte_cpu_to_le_32(start_addr + byte_offset ? enables : 0);
6192 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6193 HWRM_CHECK_RESULT();
6195 memcpy(buf + byte_offset, resp->data, xfer_size);
6197 data_length -= xfer_size;
6198 byte_offset += xfer_size;
6201 } while (data_length > 0);
6206 void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index)
6208 struct bnxt_tx_queue *txq = bp->tx_queues[queue_index];
6209 struct bnxt_tx_ring_info *txr = txq->tx_ring;
6210 struct bnxt_ring *ring = txr->tx_ring_struct;
6211 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
6213 bnxt_hwrm_ring_free(bp, ring,
6214 HWRM_RING_FREE_INPUT_RING_TYPE_TX,
6215 cpr->cp_ring_struct->fw_ring_id);
6216 txr->tx_raw_prod = 0;
6217 txr->tx_raw_cons = 0;
6218 memset(txr->tx_desc_ring, 0,
6219 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_desc_ring));
6220 memset(txr->tx_buf_ring, 0,
6221 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_buf_ring));
6223 bnxt_hwrm_stat_ctx_free(bp, cpr);
6225 bnxt_free_cp_ring(bp, cpr);
6228 int bnxt_hwrm_config_host_mtu(struct bnxt *bp)
6230 struct hwrm_func_cfg_input req = {0};
6231 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
6237 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
6239 req.fid = rte_cpu_to_le_16(0xffff);
6240 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU);
6241 req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
6243 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6244 HWRM_CHECK_RESULT();