1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SPEC_CODE_1_8_3 0x10803
31 #define HWRM_VERSION_1_9_1 0x10901
32 #define HWRM_VERSION_1_9_2 0x10903
34 struct bnxt_plcmodes_cfg {
36 uint16_t jumbo_thresh;
38 uint16_t hds_threshold;
41 static int page_getenum(size_t size)
57 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
58 return sizeof(void *) * 8 - 1;
61 static int page_roundup(size_t size)
63 return 1 << page_getenum(size);
66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
79 * HWRM Functions (sent to HWRM)
80 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
81 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
82 * command was failed by the ChiMP.
85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
86 uint32_t msg_len, bool use_kong_mb)
89 struct input *req = msg;
90 struct output *resp = bp->hwrm_cmd_resp_addr;
94 uint16_t max_req_len = bp->max_req_len;
95 struct hwrm_short_input short_input = { 0 };
96 uint16_t bar_offset = use_kong_mb ?
97 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
98 uint16_t mb_trigger_offset = use_kong_mb ?
99 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
101 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
102 msg_len > bp->max_req_len) {
103 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
105 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
106 memcpy(short_cmd_req, req, msg_len);
108 short_input.req_type = rte_cpu_to_le_16(req->req_type);
109 short_input.signature = rte_cpu_to_le_16(
110 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
111 short_input.size = rte_cpu_to_le_16(msg_len);
112 short_input.req_addr =
113 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
115 data = (uint32_t *)&short_input;
116 msg_len = sizeof(short_input);
118 /* Sync memory write before updating doorbell */
121 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
124 /* Write request msg to hwrm channel */
125 for (i = 0; i < msg_len; i += 4) {
126 bar = (uint8_t *)bp->bar0 + bar_offset + i;
127 rte_write32(*data, bar);
131 /* Zero the rest of the request space */
132 for (; i < max_req_len; i += 4) {
133 bar = (uint8_t *)bp->bar0 + bar_offset + i;
137 /* Ring channel doorbell */
138 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
141 /* Poll for the valid bit */
142 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
143 /* Sanity check on the resp->resp_len */
145 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
146 /* Last byte of resp contains the valid key */
147 valid = (uint8_t *)resp + resp->resp_len - 1;
148 if (*valid == HWRM_RESP_VALID_KEY)
154 if (i >= HWRM_CMD_TIMEOUT) {
155 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
166 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
167 * spinlock, and does initial processing.
169 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
170 * releases the spinlock only if it returns. If the regular int return codes
171 * are not used by the function, HWRM_CHECK_RESULT() should not be used
172 * directly, rather it should be copied and modified to suit the function.
174 * HWRM_UNLOCK() must be called after all response processing is completed.
176 #define HWRM_PREP(req, type, kong) do { \
177 rte_spinlock_lock(&bp->hwrm_lock); \
178 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
179 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
180 req.cmpl_ring = rte_cpu_to_le_16(-1); \
181 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
182 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
183 req.target_id = rte_cpu_to_le_16(0xffff); \
184 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
187 #define HWRM_CHECK_RESULT_SILENT() do {\
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 if (resp->error_code) { \
193 rc = rte_le_to_cpu_16(resp->error_code); \
194 rte_spinlock_unlock(&bp->hwrm_lock); \
199 #define HWRM_CHECK_RESULT() do {\
201 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
202 rte_spinlock_unlock(&bp->hwrm_lock); \
203 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 if (resp->resp_len >= 16) { \
212 struct hwrm_err_output *tmp_hwrm_err_op = \
215 "error %d:%d:%08x:%04x\n", \
216 rc, tmp_hwrm_err_op->cmd_err, \
218 tmp_hwrm_err_op->opaque_0), \
220 tmp_hwrm_err_op->opaque_1)); \
222 PMD_DRV_LOG(ERR, "error %d\n", rc); \
224 rte_spinlock_unlock(&bp->hwrm_lock); \
225 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
233 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
238 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
239 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
241 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
242 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
254 struct bnxt_vnic_info *vnic,
256 struct bnxt_vlan_table_entry *vlan_table)
259 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
260 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
263 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
269 /* FIXME add multicast flag, when multicast adding options is supported
272 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
273 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
274 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
275 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
276 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
277 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
278 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
279 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
280 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
281 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
282 if (vnic->mc_addr_cnt) {
283 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
284 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
285 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
288 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
290 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
291 rte_mem_virt2iova(vlan_table));
292 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
294 req.mask = rte_cpu_to_le_32(mask);
296 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
306 struct bnxt_vlan_antispoof_table_entry *vlan_table)
309 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
310 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
311 bp->hwrm_cmd_resp_addr;
314 * Older HWRM versions did not support this command, and the set_rx_mask
315 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
316 * removed from set_rx_mask call, and this command was added.
318 * This command is also present from 1.7.8.11 and higher,
321 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
322 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
323 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
328 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
329 req.fid = rte_cpu_to_le_16(fid);
331 req.vlan_tag_mask_tbl_addr =
332 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
333 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
344 struct bnxt_filter_info *filter)
347 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
348 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
350 if (filter->fw_l2_filter_id == UINT64_MAX)
353 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
355 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
362 filter->fw_l2_filter_id = UINT64_MAX;
367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
369 struct bnxt_filter_info *filter)
372 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
374 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
375 const struct rte_eth_vmdq_rx_conf *conf =
376 &dev_conf->rx_adv_conf.vmdq_rx_conf;
377 uint32_t enables = 0;
378 uint16_t j = dst_id - 1;
380 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
381 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
382 conf->pool_map[j].pools & (1UL << j)) {
384 "Add vlan %u to vmdq pool %u\n",
385 conf->pool_map[j].vlan_id, j);
387 filter->l2_ivlan = conf->pool_map[j].vlan_id;
389 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
393 if (filter->fw_l2_filter_id != UINT64_MAX)
394 bnxt_hwrm_clear_l2_filter(bp, filter);
396 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
398 req.flags = rte_cpu_to_le_32(filter->flags);
400 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
402 enables = filter->enables |
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
404 req.dst_id = rte_cpu_to_le_16(dst_id);
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
408 memcpy(req.l2_addr, filter->l2_addr,
411 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
412 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
415 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
416 req.l2_ovlan = filter->l2_ovlan;
418 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
419 req.l2_ivlan = filter->l2_ivlan;
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
422 req.l2_ovlan_mask = filter->l2_ovlan_mask;
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
425 req.l2_ivlan_mask = filter->l2_ivlan_mask;
426 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
427 req.src_id = rte_cpu_to_le_32(filter->src_id);
428 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
429 req.src_type = filter->src_type;
431 req.enables = rte_cpu_to_le_32(enables);
433 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
437 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
445 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
446 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
453 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
456 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
459 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
460 if (ptp->tx_tstamp_en)
461 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
464 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
465 req.flags = rte_cpu_to_le_32(flags);
466 req.enables = rte_cpu_to_le_32
467 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
468 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
470 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
479 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
480 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
481 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
483 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
487 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
489 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
495 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
498 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
502 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
503 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
504 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
505 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
506 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
507 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
508 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
509 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
510 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
511 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
512 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
513 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
514 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
515 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
516 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
517 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
518 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
519 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
530 struct hwrm_func_qcaps_input req = {.req_type = 0 };
531 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
532 uint16_t new_max_vfs;
536 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
538 req.fid = rte_cpu_to_le_16(0xffff);
540 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
544 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
545 flags = rte_le_to_cpu_32(resp->flags);
547 bp->pf.port_id = resp->port_id;
548 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
549 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
550 new_max_vfs = bp->pdev->max_vfs;
551 if (new_max_vfs != bp->pf.max_vfs) {
553 rte_free(bp->pf.vf_info);
554 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
555 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
556 bp->pf.max_vfs = new_max_vfs;
557 for (i = 0; i < new_max_vfs; i++) {
558 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
559 bp->pf.vf_info[i].vlan_table =
560 rte_zmalloc("VF VLAN table",
563 if (bp->pf.vf_info[i].vlan_table == NULL)
565 "Fail to alloc VLAN table for VF %d\n",
569 bp->pf.vf_info[i].vlan_table);
570 bp->pf.vf_info[i].vlan_as_table =
571 rte_zmalloc("VF VLAN AS table",
574 if (bp->pf.vf_info[i].vlan_as_table == NULL)
576 "Alloc VLAN AS table for VF %d fail\n",
580 bp->pf.vf_info[i].vlan_as_table);
581 STAILQ_INIT(&bp->pf.vf_info[i].filter);
586 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
587 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
588 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
589 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
590 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
591 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
592 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
593 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
595 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
596 /* TODO: For now, do not support VMDq/RFS on VFs. */
601 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
605 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
607 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
608 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
609 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
610 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
612 bnxt_hwrm_ptp_qcfg(bp);
616 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
617 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
624 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
628 rc = __bnxt_hwrm_func_qcaps(bp);
629 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
630 rc = bnxt_alloc_ctx_mem(bp);
634 rc = bnxt_hwrm_func_resc_qcaps(bp);
636 bp->flags |= BNXT_FLAG_NEW_RM;
642 int bnxt_hwrm_func_reset(struct bnxt *bp)
645 struct hwrm_func_reset_input req = {.req_type = 0 };
646 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
648 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
650 req.enables = rte_cpu_to_le_32(0);
652 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
660 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
663 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
664 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
666 if (bp->flags & BNXT_FLAG_REGISTERED)
669 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
670 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
671 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
672 req.ver_maj = RTE_VER_YEAR;
673 req.ver_min = RTE_VER_MONTH;
674 req.ver_upd = RTE_VER_MINOR;
677 req.enables |= rte_cpu_to_le_32(
678 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
679 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
680 RTE_MIN(sizeof(req.vf_req_fwd),
681 sizeof(bp->pf.vf_req_fwd)));
684 * PF can sniff HWRM API issued by VF. This can be set up by
685 * linux driver and inherited by the DPDK PF driver. Clear
686 * this HWRM sniffer list in FW because DPDK PF driver does
690 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
693 req.async_event_fwd[0] |=
694 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
695 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
696 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
697 req.async_event_fwd[1] |=
698 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
699 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
701 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
706 bp->flags |= BNXT_FLAG_REGISTERED;
711 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
713 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
716 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
719 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
724 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
725 struct hwrm_func_vf_cfg_input req = {0};
727 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
729 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
730 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
731 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
732 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
733 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
735 if (BNXT_HAS_RING_GRPS(bp)) {
736 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
737 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
740 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
741 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
742 AGG_RING_MULTIPLIER);
743 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
744 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
746 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
747 if (bp->vf_resv_strategy ==
748 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
749 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
750 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
751 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
752 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
753 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
754 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
758 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
759 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
760 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
761 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
762 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
763 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
765 if (test && BNXT_HAS_RING_GRPS(bp))
766 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
768 req.flags = rte_cpu_to_le_32(flags);
769 req.enables |= rte_cpu_to_le_32(enables);
771 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
774 HWRM_CHECK_RESULT_SILENT();
782 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
785 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
786 struct hwrm_func_resource_qcaps_input req = {0};
788 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
789 req.fid = rte_cpu_to_le_16(0xffff);
791 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
796 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
797 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
798 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
799 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
800 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
801 /* func_resource_qcaps does not return max_rx_em_flows.
802 * So use the value provided by func_qcaps.
805 rte_le_to_cpu_16(resp->max_l2_ctxs) +
807 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
808 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
810 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
811 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
812 if (bp->vf_resv_strategy >
813 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
814 bp->vf_resv_strategy =
815 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
821 int bnxt_hwrm_ver_get(struct bnxt *bp)
824 struct hwrm_ver_get_input req = {.req_type = 0 };
825 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
827 uint16_t max_resp_len;
828 char type[RTE_MEMZONE_NAMESIZE];
829 uint32_t dev_caps_cfg;
831 bp->max_req_len = HWRM_MAX_REQ_LEN;
832 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
834 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
835 req.hwrm_intf_min = HWRM_VERSION_MINOR;
836 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
838 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
842 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
843 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
844 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
845 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
846 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
847 (resp->hwrm_fw_min_8b << 16) |
848 (resp->hwrm_fw_bld_8b << 8) |
849 resp->hwrm_fw_rsvd_8b;
850 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
851 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
853 fw_version = resp->hwrm_intf_maj_8b << 16;
854 fw_version |= resp->hwrm_intf_min_8b << 8;
855 fw_version |= resp->hwrm_intf_upd_8b;
856 bp->hwrm_spec_code = fw_version;
858 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
859 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
864 if (bp->max_req_len > resp->max_req_win_len) {
865 PMD_DRV_LOG(ERR, "Unsupported request length\n");
868 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
869 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
870 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
871 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
873 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
874 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
876 if (bp->max_resp_len != max_resp_len) {
877 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
878 bp->pdev->addr.domain, bp->pdev->addr.bus,
879 bp->pdev->addr.devid, bp->pdev->addr.function);
881 rte_free(bp->hwrm_cmd_resp_addr);
883 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
884 if (bp->hwrm_cmd_resp_addr == NULL) {
888 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
889 bp->hwrm_cmd_resp_dma_addr =
890 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
891 if (bp->hwrm_cmd_resp_dma_addr == 0) {
893 "Unable to map response buffer to physical memory.\n");
897 bp->max_resp_len = max_resp_len;
901 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
903 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
904 PMD_DRV_LOG(DEBUG, "Short command supported\n");
905 bp->flags |= BNXT_FLAG_SHORT_CMD;
909 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
911 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
912 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
913 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
914 bp->pdev->addr.domain, bp->pdev->addr.bus,
915 bp->pdev->addr.devid, bp->pdev->addr.function);
917 rte_free(bp->hwrm_short_cmd_req_addr);
919 bp->hwrm_short_cmd_req_addr =
920 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
921 if (bp->hwrm_short_cmd_req_addr == NULL) {
925 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
926 bp->hwrm_short_cmd_req_dma_addr =
927 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
928 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
929 rte_free(bp->hwrm_short_cmd_req_addr);
931 "Unable to map buffer to physical memory.\n");
937 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
938 bp->flags |= BNXT_FLAG_KONG_MB_EN;
939 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
942 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
943 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
950 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
953 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
954 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
956 if (!(bp->flags & BNXT_FLAG_REGISTERED))
959 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
962 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
967 bp->flags &= ~BNXT_FLAG_REGISTERED;
972 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
975 struct hwrm_port_phy_cfg_input req = {0};
976 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
977 uint32_t enables = 0;
979 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
982 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
983 if (bp->link_info.auto_mode && conf->link_speed) {
984 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
985 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
988 req.flags = rte_cpu_to_le_32(conf->phy_flags);
989 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
990 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
992 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
993 * any auto mode, even "none".
995 if (!conf->link_speed) {
996 /* No speeds specified. Enable AutoNeg - all speeds */
998 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1000 /* AutoNeg - Advertise speeds specified. */
1001 if (conf->auto_link_speed_mask &&
1002 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1004 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1005 req.auto_link_speed_mask =
1006 conf->auto_link_speed_mask;
1008 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1011 req.auto_duplex = conf->duplex;
1012 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1013 req.auto_pause = conf->auto_pause;
1014 req.force_pause = conf->force_pause;
1015 /* Set force_pause if there is no auto or if there is a force */
1016 if (req.auto_pause && !req.force_pause)
1017 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1019 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1021 req.enables = rte_cpu_to_le_32(enables);
1024 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1025 PMD_DRV_LOG(INFO, "Force Link Down\n");
1028 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1030 HWRM_CHECK_RESULT();
1036 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1037 struct bnxt_link_info *link_info)
1040 struct hwrm_port_phy_qcfg_input req = {0};
1041 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1043 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1045 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1047 HWRM_CHECK_RESULT();
1049 link_info->phy_link_status = resp->link;
1050 link_info->link_up =
1051 (link_info->phy_link_status ==
1052 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1053 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1054 link_info->duplex = resp->duplex_cfg;
1055 link_info->pause = resp->pause;
1056 link_info->auto_pause = resp->auto_pause;
1057 link_info->force_pause = resp->force_pause;
1058 link_info->auto_mode = resp->auto_mode;
1059 link_info->phy_type = resp->phy_type;
1060 link_info->media_type = resp->media_type;
1062 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1063 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1064 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1065 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1066 link_info->phy_ver[0] = resp->phy_maj;
1067 link_info->phy_ver[1] = resp->phy_min;
1068 link_info->phy_ver[2] = resp->phy_bld;
1072 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1073 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1074 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1075 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1076 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1077 link_info->auto_link_speed_mask);
1078 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1079 link_info->force_link_speed);
1084 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1087 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1088 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1091 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1093 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1094 /* HWRM Version >= 1.9.1 */
1095 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1097 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1098 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1100 HWRM_CHECK_RESULT();
1102 #define GET_QUEUE_INFO(x) \
1103 bp->cos_queue[x].id = resp->queue_id##x; \
1104 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1117 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1118 bp->tx_cosq_id = bp->cos_queue[0].id;
1120 /* iterate and find the COSq profile to use for Tx */
1121 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1122 if (bp->cos_queue[i].profile ==
1123 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1124 bp->tx_cosq_id = bp->cos_queue[i].id;
1130 bp->max_tc = resp->max_configurable_queues;
1131 bp->max_lltc = resp->max_configurable_lossless_queues;
1132 if (bp->max_tc > BNXT_MAX_QUEUE)
1133 bp->max_tc = BNXT_MAX_QUEUE;
1134 bp->max_q = bp->max_tc;
1136 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1141 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1142 struct bnxt_ring *ring,
1143 uint32_t ring_type, uint32_t map_index,
1144 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1147 uint32_t enables = 0;
1148 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1149 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1150 struct rte_mempool *mb_pool;
1151 uint16_t rx_buf_size;
1153 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1155 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1156 req.fbo = rte_cpu_to_le_32(0);
1157 /* Association of ring index with doorbell index */
1158 req.logical_id = rte_cpu_to_le_16(map_index);
1159 req.length = rte_cpu_to_le_32(ring->ring_size);
1161 switch (ring_type) {
1162 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1163 req.ring_type = ring_type;
1164 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1165 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1166 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1167 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1169 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1171 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1172 req.ring_type = ring_type;
1173 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1174 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1175 if (BNXT_CHIP_THOR(bp)) {
1176 mb_pool = bp->rx_queues[0]->mb_pool;
1177 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1178 RTE_PKTMBUF_HEADROOM;
1179 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1181 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1183 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1185 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1187 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1188 req.ring_type = ring_type;
1189 if (BNXT_HAS_NQ(bp)) {
1190 /* Association of cp ring with nq */
1191 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1193 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1195 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1197 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1198 req.ring_type = ring_type;
1199 req.page_size = BNXT_PAGE_SHFT;
1200 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1202 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1203 req.ring_type = ring_type;
1204 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1206 mb_pool = bp->rx_queues[0]->mb_pool;
1207 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1208 RTE_PKTMBUF_HEADROOM;
1209 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1211 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1212 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1213 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1214 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1217 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1222 req.enables = rte_cpu_to_le_32(enables);
1224 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1226 if (rc || resp->error_code) {
1227 if (rc == 0 && resp->error_code)
1228 rc = rte_le_to_cpu_16(resp->error_code);
1229 switch (ring_type) {
1230 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1232 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1235 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1237 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1240 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1242 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1246 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1248 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1251 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1253 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1257 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1263 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1268 int bnxt_hwrm_ring_free(struct bnxt *bp,
1269 struct bnxt_ring *ring, uint32_t ring_type)
1272 struct hwrm_ring_free_input req = {.req_type = 0 };
1273 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1275 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1277 req.ring_type = ring_type;
1278 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1280 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1282 if (rc || resp->error_code) {
1283 if (rc == 0 && resp->error_code)
1284 rc = rte_le_to_cpu_16(resp->error_code);
1287 switch (ring_type) {
1288 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1289 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1292 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1293 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1296 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1297 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1300 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1302 "hwrm_ring_free nq failed. rc:%d\n", rc);
1304 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1306 "hwrm_ring_free agg failed. rc:%d\n", rc);
1309 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1317 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1320 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1321 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1323 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1325 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1326 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1327 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1328 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1330 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1332 HWRM_CHECK_RESULT();
1334 bp->grp_info[idx].fw_grp_id =
1335 rte_le_to_cpu_16(resp->ring_group_id);
1342 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1345 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1346 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1348 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1350 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1352 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1354 HWRM_CHECK_RESULT();
1357 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1361 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1364 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1365 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1367 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1370 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1372 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1374 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1376 HWRM_CHECK_RESULT();
1382 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1383 unsigned int idx __rte_unused)
1386 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1387 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1389 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1391 req.update_period_ms = rte_cpu_to_le_32(0);
1393 req.stats_dma_addr =
1394 rte_cpu_to_le_64(cpr->hw_stats_map);
1396 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1398 HWRM_CHECK_RESULT();
1400 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1407 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1408 unsigned int idx __rte_unused)
1411 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1412 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1414 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1416 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1418 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1420 HWRM_CHECK_RESULT();
1426 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1429 struct hwrm_vnic_alloc_input req = { 0 };
1430 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1432 if (!BNXT_HAS_RING_GRPS(bp))
1433 goto skip_ring_grps;
1435 /* map ring groups to this vnic */
1436 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1437 vnic->start_grp_id, vnic->end_grp_id);
1438 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1439 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1441 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1442 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1443 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1444 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1447 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1448 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1449 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1451 if (vnic->func_default)
1453 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1454 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1456 HWRM_CHECK_RESULT();
1458 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1460 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1464 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1465 struct bnxt_vnic_info *vnic,
1466 struct bnxt_plcmodes_cfg *pmode)
1469 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1470 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1472 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1474 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1476 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1478 HWRM_CHECK_RESULT();
1480 pmode->flags = rte_le_to_cpu_32(resp->flags);
1481 /* dflt_vnic bit doesn't exist in the _cfg command */
1482 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1483 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1484 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1485 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1492 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1493 struct bnxt_vnic_info *vnic,
1494 struct bnxt_plcmodes_cfg *pmode)
1497 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1498 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1500 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1502 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1503 req.flags = rte_cpu_to_le_32(pmode->flags);
1504 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1505 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1506 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1507 req.enables = rte_cpu_to_le_32(
1508 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1509 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1510 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1513 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1515 HWRM_CHECK_RESULT();
1521 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1524 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1525 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1526 uint32_t ctx_enable_flag = 0;
1527 struct bnxt_plcmodes_cfg pmodes;
1528 uint32_t enables = 0;
1530 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1531 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1535 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1539 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1541 if (BNXT_CHIP_THOR(bp)) {
1542 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1543 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1544 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1546 req.default_rx_ring_id =
1547 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1548 req.default_cmpl_ring_id =
1549 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1550 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1551 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1555 /* Only RSS support for now TBD: COS & LB */
1556 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1557 if (vnic->lb_rule != 0xffff)
1558 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1559 if (vnic->cos_rule != 0xffff)
1560 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1561 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1562 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1563 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1565 enables |= ctx_enable_flag;
1566 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1567 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1568 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1569 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1572 req.enables = rte_cpu_to_le_32(enables);
1573 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1574 req.mru = rte_cpu_to_le_16(vnic->mru);
1575 /* Configure default VNIC only once. */
1576 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1578 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1579 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1581 if (vnic->vlan_strip)
1583 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1586 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1587 if (vnic->roce_dual)
1588 req.flags |= rte_cpu_to_le_32(
1589 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1590 if (vnic->roce_only)
1591 req.flags |= rte_cpu_to_le_32(
1592 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1593 if (vnic->rss_dflt_cr)
1594 req.flags |= rte_cpu_to_le_32(
1595 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1597 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1599 HWRM_CHECK_RESULT();
1602 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1607 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1611 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1612 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1614 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1615 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1618 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1621 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1622 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1623 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1625 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1627 HWRM_CHECK_RESULT();
1629 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1630 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1631 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1632 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1633 vnic->mru = rte_le_to_cpu_16(resp->mru);
1634 vnic->func_default = rte_le_to_cpu_32(
1635 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1636 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1637 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1638 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1639 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1640 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1641 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1642 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1643 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1644 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1645 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1652 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1653 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1657 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1658 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1659 bp->hwrm_cmd_resp_addr;
1661 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1663 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1664 HWRM_CHECK_RESULT();
1666 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1667 if (!BNXT_HAS_RING_GRPS(bp))
1668 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1669 else if (ctx_idx == 0)
1670 vnic->rss_rule = ctx_id;
1677 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1678 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1681 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1682 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1683 bp->hwrm_cmd_resp_addr;
1685 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1686 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1689 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1691 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1693 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1695 HWRM_CHECK_RESULT();
1701 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1704 struct hwrm_vnic_free_input req = {.req_type = 0 };
1705 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1707 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1708 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1712 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1714 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1716 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1718 HWRM_CHECK_RESULT();
1721 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1722 /* Configure default VNIC again if necessary. */
1723 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1724 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1730 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1734 int nr_ctxs = bp->max_ring_grps;
1735 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1736 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1738 if (!(vnic->rss_table && vnic->hash_type))
1741 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1743 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1744 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1745 req.hash_mode_flags = vnic->hash_mode;
1747 req.hash_key_tbl_addr =
1748 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1750 for (i = 0; i < nr_ctxs; i++) {
1751 req.ring_grp_tbl_addr =
1752 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1753 i * HW_HASH_INDEX_SIZE);
1754 req.ring_table_pair_index = i;
1755 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1757 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1760 HWRM_CHECK_RESULT();
1770 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1771 struct bnxt_vnic_info *vnic)
1774 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1775 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1777 if (BNXT_CHIP_THOR(bp))
1778 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1780 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1782 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1783 req.hash_mode_flags = vnic->hash_mode;
1785 req.ring_grp_tbl_addr =
1786 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1787 req.hash_key_tbl_addr =
1788 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1789 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1790 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1792 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1794 HWRM_CHECK_RESULT();
1800 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1801 struct bnxt_vnic_info *vnic)
1804 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1805 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1808 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1809 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1813 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1815 req.flags = rte_cpu_to_le_32(
1816 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1818 req.enables = rte_cpu_to_le_32(
1819 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1821 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1822 size -= RTE_PKTMBUF_HEADROOM;
1824 req.jumbo_thresh = rte_cpu_to_le_16(size);
1825 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1827 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1829 HWRM_CHECK_RESULT();
1835 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1836 struct bnxt_vnic_info *vnic, bool enable)
1839 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1840 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1842 if (BNXT_CHIP_THOR(bp))
1845 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1848 req.enables = rte_cpu_to_le_32(
1849 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1850 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1851 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1852 req.flags = rte_cpu_to_le_32(
1853 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1854 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1855 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1856 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1857 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1858 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1859 req.max_agg_segs = rte_cpu_to_le_16(5);
1861 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1862 req.min_agg_len = rte_cpu_to_le_32(512);
1864 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1866 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1868 HWRM_CHECK_RESULT();
1874 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1876 struct hwrm_func_cfg_input req = {0};
1877 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1880 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1881 req.enables = rte_cpu_to_le_32(
1882 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1883 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1884 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1886 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1888 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1889 HWRM_CHECK_RESULT();
1892 bp->pf.vf_info[vf].random_mac = false;
1897 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1901 struct hwrm_func_qstats_input req = {.req_type = 0};
1902 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1904 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1906 req.fid = rte_cpu_to_le_16(fid);
1908 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1910 HWRM_CHECK_RESULT();
1913 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1920 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1921 struct rte_eth_stats *stats)
1924 struct hwrm_func_qstats_input req = {.req_type = 0};
1925 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1927 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1929 req.fid = rte_cpu_to_le_16(fid);
1931 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933 HWRM_CHECK_RESULT();
1935 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1936 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1937 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1938 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1939 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1940 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1942 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1943 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1944 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1945 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1946 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1947 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1949 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1950 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1951 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1958 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1961 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1962 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1964 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1966 req.fid = rte_cpu_to_le_16(fid);
1968 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1970 HWRM_CHECK_RESULT();
1977 * HWRM utility functions
1980 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1985 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1986 struct bnxt_tx_queue *txq;
1987 struct bnxt_rx_queue *rxq;
1988 struct bnxt_cp_ring_info *cpr;
1990 if (i >= bp->rx_cp_nr_rings) {
1991 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1994 rxq = bp->rx_queues[i];
1998 rc = bnxt_hwrm_stat_clear(bp, cpr);
2005 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2009 struct bnxt_cp_ring_info *cpr;
2011 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2013 if (i >= bp->rx_cp_nr_rings) {
2014 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2016 cpr = bp->rx_queues[i]->cp_ring;
2017 if (BNXT_HAS_RING_GRPS(bp))
2018 bp->grp_info[i].fw_stats_ctx = -1;
2020 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2021 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2022 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2030 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2035 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2036 struct bnxt_tx_queue *txq;
2037 struct bnxt_rx_queue *rxq;
2038 struct bnxt_cp_ring_info *cpr;
2040 if (i >= bp->rx_cp_nr_rings) {
2041 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2044 rxq = bp->rx_queues[i];
2048 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2056 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2061 if (!BNXT_HAS_RING_GRPS(bp))
2064 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2066 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2069 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2077 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2079 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2081 bnxt_hwrm_ring_free(bp, cp_ring,
2082 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2083 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2084 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2085 sizeof(*cpr->cp_desc_ring));
2086 cpr->cp_raw_cons = 0;
2089 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2091 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2093 bnxt_hwrm_ring_free(bp, cp_ring,
2094 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2095 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2096 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2097 sizeof(*cpr->cp_desc_ring));
2098 cpr->cp_raw_cons = 0;
2102 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2104 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2105 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2106 struct bnxt_ring *ring = rxr->rx_ring_struct;
2107 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2109 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2110 bnxt_hwrm_ring_free(bp, ring,
2111 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2112 ring->fw_ring_id = INVALID_HW_RING_ID;
2113 if (BNXT_HAS_RING_GRPS(bp))
2114 bp->grp_info[queue_index].rx_fw_ring_id =
2116 memset(rxr->rx_desc_ring, 0,
2117 rxr->rx_ring_struct->ring_size *
2118 sizeof(*rxr->rx_desc_ring));
2119 memset(rxr->rx_buf_ring, 0,
2120 rxr->rx_ring_struct->ring_size *
2121 sizeof(*rxr->rx_buf_ring));
2124 ring = rxr->ag_ring_struct;
2125 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2126 bnxt_hwrm_ring_free(bp, ring,
2127 BNXT_CHIP_THOR(bp) ?
2128 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2129 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2130 ring->fw_ring_id = INVALID_HW_RING_ID;
2131 memset(rxr->ag_buf_ring, 0,
2132 rxr->ag_ring_struct->ring_size *
2133 sizeof(*rxr->ag_buf_ring));
2135 if (BNXT_HAS_RING_GRPS(bp))
2136 bp->grp_info[queue_index].ag_fw_ring_id =
2139 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2140 bnxt_free_cp_ring(bp, cpr);
2142 bnxt_free_nq_ring(bp, rxq->nq_ring);
2145 if (BNXT_HAS_RING_GRPS(bp))
2146 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2149 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2153 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2154 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2155 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2156 struct bnxt_ring *ring = txr->tx_ring_struct;
2157 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2159 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2160 bnxt_hwrm_ring_free(bp, ring,
2161 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2162 ring->fw_ring_id = INVALID_HW_RING_ID;
2163 memset(txr->tx_desc_ring, 0,
2164 txr->tx_ring_struct->ring_size *
2165 sizeof(*txr->tx_desc_ring));
2166 memset(txr->tx_buf_ring, 0,
2167 txr->tx_ring_struct->ring_size *
2168 sizeof(*txr->tx_buf_ring));
2172 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2173 bnxt_free_cp_ring(bp, cpr);
2174 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2176 bnxt_free_nq_ring(bp, txq->nq_ring);
2180 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2181 bnxt_free_hwrm_rx_ring(bp, i);
2186 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2191 if (!BNXT_HAS_RING_GRPS(bp))
2194 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2195 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2202 void bnxt_free_hwrm_resources(struct bnxt *bp)
2204 /* Release memzone */
2205 rte_free(bp->hwrm_cmd_resp_addr);
2206 rte_free(bp->hwrm_short_cmd_req_addr);
2207 bp->hwrm_cmd_resp_addr = NULL;
2208 bp->hwrm_short_cmd_req_addr = NULL;
2209 bp->hwrm_cmd_resp_dma_addr = 0;
2210 bp->hwrm_short_cmd_req_dma_addr = 0;
2213 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2215 struct rte_pci_device *pdev = bp->pdev;
2216 char type[RTE_MEMZONE_NAMESIZE];
2218 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2219 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2220 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2221 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2222 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2223 if (bp->hwrm_cmd_resp_addr == NULL)
2225 bp->hwrm_cmd_resp_dma_addr =
2226 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2227 if (bp->hwrm_cmd_resp_dma_addr == 0) {
2229 "unable to map response address to physical memory\n");
2232 rte_spinlock_init(&bp->hwrm_lock);
2237 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2239 struct bnxt_filter_info *filter;
2242 STAILQ_FOREACH(filter, &vnic->filter, next) {
2243 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2244 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2245 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2246 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2248 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2249 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2257 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2259 struct bnxt_filter_info *filter;
2260 struct rte_flow *flow;
2263 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2264 filter = flow->filter;
2265 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2266 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2267 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2268 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2269 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2271 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2273 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2281 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2283 struct bnxt_filter_info *filter;
2286 STAILQ_FOREACH(filter, &vnic->filter, next) {
2287 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2288 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2290 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2291 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2294 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2302 void bnxt_free_tunnel_ports(struct bnxt *bp)
2304 if (bp->vxlan_port_cnt)
2305 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2306 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2308 if (bp->geneve_port_cnt)
2309 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2310 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2311 bp->geneve_port = 0;
2314 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2318 if (bp->vnic_info == NULL)
2322 * Cleanup VNICs in reverse order, to make sure the L2 filter
2323 * from vnic0 is last to be cleaned up.
2325 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2326 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2328 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2330 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2332 if (BNXT_CHIP_THOR(bp)) {
2333 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2334 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2335 vnic->fw_grp_ids[j]);
2336 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2338 vnic->num_lb_ctxts = 0;
2340 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2341 vnic->rss_rule = INVALID_HW_RING_ID;
2344 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2346 bnxt_hwrm_vnic_free(bp, vnic);
2348 rte_free(vnic->fw_grp_ids);
2350 /* Ring resources */
2351 bnxt_free_all_hwrm_rings(bp);
2352 bnxt_free_all_hwrm_ring_grps(bp);
2353 bnxt_free_all_hwrm_stat_ctxs(bp);
2354 bnxt_free_tunnel_ports(bp);
2357 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2359 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2361 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2362 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2364 switch (conf_link_speed) {
2365 case ETH_LINK_SPEED_10M_HD:
2366 case ETH_LINK_SPEED_100M_HD:
2368 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2370 return hw_link_duplex;
2373 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2375 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2378 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2380 uint16_t eth_link_speed = 0;
2382 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2383 return ETH_LINK_SPEED_AUTONEG;
2385 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2386 case ETH_LINK_SPEED_100M:
2387 case ETH_LINK_SPEED_100M_HD:
2390 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2392 case ETH_LINK_SPEED_1G:
2394 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2396 case ETH_LINK_SPEED_2_5G:
2398 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2400 case ETH_LINK_SPEED_10G:
2402 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2404 case ETH_LINK_SPEED_20G:
2406 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2408 case ETH_LINK_SPEED_25G:
2410 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2412 case ETH_LINK_SPEED_40G:
2414 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2416 case ETH_LINK_SPEED_50G:
2418 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2420 case ETH_LINK_SPEED_100G:
2422 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2426 "Unsupported link speed %d; default to AUTO\n",
2430 return eth_link_speed;
2433 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2434 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2435 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2436 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2438 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2442 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2445 if (link_speed & ETH_LINK_SPEED_FIXED) {
2446 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2448 if (one_speed & (one_speed - 1)) {
2450 "Invalid advertised speeds (%u) for port %u\n",
2451 link_speed, port_id);
2454 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2456 "Unsupported advertised speed (%u) for port %u\n",
2457 link_speed, port_id);
2461 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2463 "Unsupported advertised speeds (%u) for port %u\n",
2464 link_speed, port_id);
2472 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2476 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2477 if (bp->link_info.support_speeds)
2478 return bp->link_info.support_speeds;
2479 link_speed = BNXT_SUPPORTED_SPEEDS;
2482 if (link_speed & ETH_LINK_SPEED_100M)
2483 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2484 if (link_speed & ETH_LINK_SPEED_100M_HD)
2485 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2486 if (link_speed & ETH_LINK_SPEED_1G)
2487 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2488 if (link_speed & ETH_LINK_SPEED_2_5G)
2489 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2490 if (link_speed & ETH_LINK_SPEED_10G)
2491 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2492 if (link_speed & ETH_LINK_SPEED_20G)
2493 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2494 if (link_speed & ETH_LINK_SPEED_25G)
2495 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2496 if (link_speed & ETH_LINK_SPEED_40G)
2497 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2498 if (link_speed & ETH_LINK_SPEED_50G)
2499 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2500 if (link_speed & ETH_LINK_SPEED_100G)
2501 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2505 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2507 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2509 switch (hw_link_speed) {
2510 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2511 eth_link_speed = ETH_SPEED_NUM_100M;
2513 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2514 eth_link_speed = ETH_SPEED_NUM_1G;
2516 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2517 eth_link_speed = ETH_SPEED_NUM_2_5G;
2519 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2520 eth_link_speed = ETH_SPEED_NUM_10G;
2522 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2523 eth_link_speed = ETH_SPEED_NUM_20G;
2525 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2526 eth_link_speed = ETH_SPEED_NUM_25G;
2528 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2529 eth_link_speed = ETH_SPEED_NUM_40G;
2531 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2532 eth_link_speed = ETH_SPEED_NUM_50G;
2534 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2535 eth_link_speed = ETH_SPEED_NUM_100G;
2537 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2539 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2543 return eth_link_speed;
2546 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2548 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2550 switch (hw_link_duplex) {
2551 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2552 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2554 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2556 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2557 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2560 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2564 return eth_link_duplex;
2567 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2570 struct bnxt_link_info *link_info = &bp->link_info;
2572 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2575 "Get link config failed with rc %d\n", rc);
2578 if (link_info->link_speed)
2580 bnxt_parse_hw_link_speed(link_info->link_speed);
2582 link->link_speed = ETH_SPEED_NUM_NONE;
2583 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2584 link->link_status = link_info->link_up;
2585 link->link_autoneg = link_info->auto_mode ==
2586 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2587 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2592 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2595 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2596 struct bnxt_link_info link_req;
2597 uint16_t speed, autoneg;
2599 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2602 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2603 bp->eth_dev->data->port_id);
2607 memset(&link_req, 0, sizeof(link_req));
2608 link_req.link_up = link_up;
2612 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2613 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2614 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2615 /* Autoneg can be done only when the FW allows */
2616 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2617 bp->link_info.force_link_speed)) {
2618 link_req.phy_flags |=
2619 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2620 link_req.auto_link_speed_mask =
2621 bnxt_parse_eth_link_speed_mask(bp,
2622 dev_conf->link_speeds);
2624 if (bp->link_info.phy_type ==
2625 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2626 bp->link_info.phy_type ==
2627 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2628 bp->link_info.media_type ==
2629 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2630 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2634 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2635 /* If user wants a particular speed try that first. */
2637 link_req.link_speed = speed;
2638 else if (bp->link_info.force_link_speed)
2639 link_req.link_speed = bp->link_info.force_link_speed;
2641 link_req.link_speed = bp->link_info.auto_link_speed;
2643 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2644 link_req.auto_pause = bp->link_info.auto_pause;
2645 link_req.force_pause = bp->link_info.force_pause;
2648 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2651 "Set link config failed with rc %d\n", rc);
2659 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2661 struct hwrm_func_qcfg_input req = {0};
2662 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2666 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2667 req.fid = rte_cpu_to_le_16(0xffff);
2669 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2671 HWRM_CHECK_RESULT();
2673 /* Hard Coded.. 0xfff VLAN ID mask */
2674 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2675 flags = rte_le_to_cpu_16(resp->flags);
2676 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2677 bp->flags |= BNXT_FLAG_MULTI_HOST;
2679 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2680 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2681 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2687 switch (resp->port_partition_type) {
2688 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2689 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2690 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2692 bp->port_partition_type = resp->port_partition_type;
2695 bp->port_partition_type = 0;
2704 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2705 struct hwrm_func_qcaps_output *qcaps)
2707 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2708 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2709 sizeof(qcaps->mac_address));
2710 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2711 qcaps->max_rx_rings = fcfg->num_rx_rings;
2712 qcaps->max_tx_rings = fcfg->num_tx_rings;
2713 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2714 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2716 qcaps->first_vf_id = 0;
2717 qcaps->max_vnics = fcfg->num_vnics;
2718 qcaps->max_decap_records = 0;
2719 qcaps->max_encap_records = 0;
2720 qcaps->max_tx_wm_flows = 0;
2721 qcaps->max_tx_em_flows = 0;
2722 qcaps->max_rx_wm_flows = 0;
2723 qcaps->max_rx_em_flows = 0;
2724 qcaps->max_flow_id = 0;
2725 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2726 qcaps->max_sp_tx_rings = 0;
2727 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2730 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2732 struct hwrm_func_cfg_input req = {0};
2733 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2737 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2738 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2739 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2740 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2741 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2742 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2743 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2744 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2745 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2747 if (BNXT_HAS_RING_GRPS(bp)) {
2748 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2749 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2750 } else if (BNXT_HAS_NQ(bp)) {
2751 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2752 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2755 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2756 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2757 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2758 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2760 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2761 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2762 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2763 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2764 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2765 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2766 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2767 req.fid = rte_cpu_to_le_16(0xffff);
2768 req.enables = rte_cpu_to_le_32(enables);
2770 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2772 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2774 HWRM_CHECK_RESULT();
2780 static void populate_vf_func_cfg_req(struct bnxt *bp,
2781 struct hwrm_func_cfg_input *req,
2784 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2785 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2786 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2787 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2788 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2789 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2790 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2791 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2792 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2793 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2795 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2796 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2798 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2799 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2801 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2803 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2804 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2806 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2807 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2808 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2809 /* TODO: For now, do not support VMDq/RFS on VFs. */
2810 req->num_vnics = rte_cpu_to_le_16(1);
2811 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2815 static void add_random_mac_if_needed(struct bnxt *bp,
2816 struct hwrm_func_cfg_input *cfg_req,
2819 struct rte_ether_addr mac;
2821 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2824 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2826 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2827 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2828 bp->pf.vf_info[vf].random_mac = true;
2830 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2831 RTE_ETHER_ADDR_LEN);
2835 static void reserve_resources_from_vf(struct bnxt *bp,
2836 struct hwrm_func_cfg_input *cfg_req,
2839 struct hwrm_func_qcaps_input req = {0};
2840 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2843 /* Get the actual allocated values now */
2844 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2845 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2846 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2849 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2850 copy_func_cfg_to_qcaps(cfg_req, resp);
2851 } else if (resp->error_code) {
2852 rc = rte_le_to_cpu_16(resp->error_code);
2853 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2854 copy_func_cfg_to_qcaps(cfg_req, resp);
2857 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2858 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2859 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2860 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2861 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2862 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2864 * TODO: While not supporting VMDq with VFs, max_vnics is always
2865 * forced to 1 in this case
2867 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2868 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2873 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2875 struct hwrm_func_qcfg_input req = {0};
2876 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2879 /* Check for zero MAC address */
2880 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2881 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2882 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2884 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2886 } else if (resp->error_code) {
2887 rc = rte_le_to_cpu_16(resp->error_code);
2888 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2891 rc = rte_le_to_cpu_16(resp->vlan);
2898 static int update_pf_resource_max(struct bnxt *bp)
2900 struct hwrm_func_qcfg_input req = {0};
2901 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2904 /* And copy the allocated numbers into the pf struct */
2905 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2906 req.fid = rte_cpu_to_le_16(0xffff);
2907 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2908 HWRM_CHECK_RESULT();
2910 /* Only TX ring value reflects actual allocation? TODO */
2911 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2912 bp->pf.evb_mode = resp->evb_mode;
2919 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2924 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2928 rc = bnxt_hwrm_func_qcaps(bp);
2932 bp->pf.func_cfg_flags &=
2933 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2934 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2935 bp->pf.func_cfg_flags |=
2936 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2937 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2938 rc = __bnxt_hwrm_func_qcaps(bp);
2942 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2944 struct hwrm_func_cfg_input req = {0};
2945 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2952 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2956 rc = bnxt_hwrm_func_qcaps(bp);
2961 bp->pf.active_vfs = num_vfs;
2964 * First, configure the PF to only use one TX ring. This ensures that
2965 * there are enough rings for all VFs.
2967 * If we don't do this, when we call func_alloc() later, we will lock
2968 * extra rings to the PF that won't be available during func_cfg() of
2971 * This has been fixed with firmware versions above 20.6.54
2973 bp->pf.func_cfg_flags &=
2974 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2975 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2976 bp->pf.func_cfg_flags |=
2977 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2978 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2983 * Now, create and register a buffer to hold forwarded VF requests
2985 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2986 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2987 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2988 if (bp->pf.vf_req_buf == NULL) {
2992 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2993 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2994 for (i = 0; i < num_vfs; i++)
2995 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2996 (i * HWRM_MAX_REQ_LEN);
2998 rc = bnxt_hwrm_func_buf_rgtr(bp);
3002 populate_vf_func_cfg_req(bp, &req, num_vfs);
3004 bp->pf.active_vfs = 0;
3005 for (i = 0; i < num_vfs; i++) {
3006 add_random_mac_if_needed(bp, &req, i);
3008 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3009 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3010 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3011 rc = bnxt_hwrm_send_message(bp,
3016 /* Clear enable flag for next pass */
3017 req.enables &= ~rte_cpu_to_le_32(
3018 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3020 if (rc || resp->error_code) {
3022 "Failed to initizlie VF %d\n", i);
3024 "Not all VFs available. (%d, %d)\n",
3025 rc, resp->error_code);
3032 reserve_resources_from_vf(bp, &req, i);
3033 bp->pf.active_vfs++;
3034 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3038 * Now configure the PF to use "the rest" of the resources
3039 * We're using STD_TX_RING_MODE here though which will limit the TX
3040 * rings. This will allow QoS to function properly. Not setting this
3041 * will cause PF rings to break bandwidth settings.
3043 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3047 rc = update_pf_resource_max(bp);
3054 bnxt_hwrm_func_buf_unrgtr(bp);
3058 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3060 struct hwrm_func_cfg_input req = {0};
3061 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3064 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3066 req.fid = rte_cpu_to_le_16(0xffff);
3067 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3068 req.evb_mode = bp->pf.evb_mode;
3070 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3071 HWRM_CHECK_RESULT();
3077 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3078 uint8_t tunnel_type)
3080 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3081 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3084 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3085 req.tunnel_type = tunnel_type;
3086 req.tunnel_dst_port_val = port;
3087 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3088 HWRM_CHECK_RESULT();
3090 switch (tunnel_type) {
3091 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3092 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3093 bp->vxlan_port = port;
3095 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3096 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3097 bp->geneve_port = port;
3108 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3109 uint8_t tunnel_type)
3111 struct hwrm_tunnel_dst_port_free_input req = {0};
3112 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3115 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3117 req.tunnel_type = tunnel_type;
3118 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3119 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3121 HWRM_CHECK_RESULT();
3127 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3130 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3131 struct hwrm_func_cfg_input req = {0};
3134 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3136 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3137 req.flags = rte_cpu_to_le_32(flags);
3138 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3140 HWRM_CHECK_RESULT();
3146 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3148 uint32_t *flag = flagp;
3150 vnic->flags = *flag;
3153 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3155 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3158 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3161 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3162 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3164 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3166 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3167 req.req_buf_page_size = rte_cpu_to_le_16(
3168 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3169 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3170 req.req_buf_page_addr0 =
3171 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3172 if (req.req_buf_page_addr0 == 0) {
3174 "unable to map buffer address to physical memory\n");
3178 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3180 HWRM_CHECK_RESULT();
3186 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3189 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3190 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3192 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3194 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3196 HWRM_CHECK_RESULT();
3202 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3204 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3205 struct hwrm_func_cfg_input req = {0};
3208 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3210 req.fid = rte_cpu_to_le_16(0xffff);
3211 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3212 req.enables = rte_cpu_to_le_32(
3213 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3214 req.async_event_cr = rte_cpu_to_le_16(
3215 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3216 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3218 HWRM_CHECK_RESULT();
3224 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3226 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3227 struct hwrm_func_vf_cfg_input req = {0};
3230 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3232 req.enables = rte_cpu_to_le_32(
3233 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3234 req.async_event_cr = rte_cpu_to_le_16(
3235 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3236 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3238 HWRM_CHECK_RESULT();
3244 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3246 struct hwrm_func_cfg_input req = {0};
3247 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3248 uint16_t dflt_vlan, fid;
3249 uint32_t func_cfg_flags;
3252 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3255 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3256 fid = bp->pf.vf_info[vf].fid;
3257 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3259 fid = rte_cpu_to_le_16(0xffff);
3260 func_cfg_flags = bp->pf.func_cfg_flags;
3261 dflt_vlan = bp->vlan;
3264 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3265 req.fid = rte_cpu_to_le_16(fid);
3266 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3267 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3269 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3271 HWRM_CHECK_RESULT();
3277 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3278 uint16_t max_bw, uint16_t enables)
3280 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3281 struct hwrm_func_cfg_input req = {0};
3284 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3286 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3287 req.enables |= rte_cpu_to_le_32(enables);
3288 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3289 req.max_bw = rte_cpu_to_le_32(max_bw);
3290 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3292 HWRM_CHECK_RESULT();
3298 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3300 struct hwrm_func_cfg_input req = {0};
3301 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3304 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3306 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3307 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3308 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3309 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3311 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3313 HWRM_CHECK_RESULT();
3319 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3324 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3326 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3331 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3332 void *encaped, size_t ec_size)
3335 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3336 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3338 if (ec_size > sizeof(req.encap_request))
3341 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3343 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3344 memcpy(req.encap_request, encaped, ec_size);
3346 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3348 HWRM_CHECK_RESULT();
3354 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3355 struct rte_ether_addr *mac)
3357 struct hwrm_func_qcfg_input req = {0};
3358 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3361 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3363 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3364 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3366 HWRM_CHECK_RESULT();
3368 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3375 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3376 void *encaped, size_t ec_size)
3379 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3380 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3382 if (ec_size > sizeof(req.encap_request))
3385 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3387 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3388 memcpy(req.encap_request, encaped, ec_size);
3390 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3392 HWRM_CHECK_RESULT();
3398 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3399 struct rte_eth_stats *stats, uint8_t rx)
3402 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3403 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3405 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3407 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3409 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3411 HWRM_CHECK_RESULT();
3414 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3415 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3416 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3417 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3418 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3419 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3420 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3421 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3423 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3424 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3425 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3426 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3427 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3428 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3437 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3439 struct hwrm_port_qstats_input req = {0};
3440 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3441 struct bnxt_pf_info *pf = &bp->pf;
3444 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3446 req.port_id = rte_cpu_to_le_16(pf->port_id);
3447 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3448 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3449 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3451 HWRM_CHECK_RESULT();
3457 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3459 struct hwrm_port_clr_stats_input req = {0};
3460 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3461 struct bnxt_pf_info *pf = &bp->pf;
3464 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3465 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3466 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3469 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3471 req.port_id = rte_cpu_to_le_16(pf->port_id);
3472 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3474 HWRM_CHECK_RESULT();
3480 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3482 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3483 struct hwrm_port_led_qcaps_input req = {0};
3489 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3490 req.port_id = bp->pf.port_id;
3491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3493 HWRM_CHECK_RESULT();
3495 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3498 bp->num_leds = resp->num_leds;
3499 memcpy(bp->leds, &resp->led0_id,
3500 sizeof(bp->leds[0]) * bp->num_leds);
3501 for (i = 0; i < bp->num_leds; i++) {
3502 struct bnxt_led_info *led = &bp->leds[i];
3504 uint16_t caps = led->led_state_caps;
3506 if (!led->led_group_id ||
3507 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3519 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3521 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3522 struct hwrm_port_led_cfg_input req = {0};
3523 struct bnxt_led_cfg *led_cfg;
3524 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3525 uint16_t duration = 0;
3528 if (!bp->num_leds || BNXT_VF(bp))
3531 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3534 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3535 duration = rte_cpu_to_le_16(500);
3537 req.port_id = bp->pf.port_id;
3538 req.num_leds = bp->num_leds;
3539 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3540 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3541 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3542 led_cfg->led_id = bp->leds[i].led_id;
3543 led_cfg->led_state = led_state;
3544 led_cfg->led_blink_on = duration;
3545 led_cfg->led_blink_off = duration;
3546 led_cfg->led_group_id = bp->leds[i].led_group_id;
3549 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3551 HWRM_CHECK_RESULT();
3557 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3561 struct hwrm_nvm_get_dir_info_input req = {0};
3562 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3564 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3566 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3568 HWRM_CHECK_RESULT();
3572 *entries = rte_le_to_cpu_32(resp->entries);
3573 *length = rte_le_to_cpu_32(resp->entry_length);
3578 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3581 uint32_t dir_entries;
3582 uint32_t entry_length;
3585 rte_iova_t dma_handle;
3586 struct hwrm_nvm_get_dir_entries_input req = {0};
3587 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3589 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3593 *data++ = dir_entries;
3594 *data++ = entry_length;
3596 memset(data, 0xff, len);
3598 buflen = dir_entries * entry_length;
3599 buf = rte_malloc("nvm_dir", buflen, 0);
3600 rte_mem_lock_page(buf);
3603 dma_handle = rte_mem_virt2iova(buf);
3604 if (dma_handle == 0) {
3606 "unable to map response address to physical memory\n");
3609 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3610 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3611 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3614 memcpy(data, buf, len > buflen ? buflen : len);
3617 HWRM_CHECK_RESULT();
3623 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3624 uint32_t offset, uint32_t length,
3629 rte_iova_t dma_handle;
3630 struct hwrm_nvm_read_input req = {0};
3631 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3633 buf = rte_malloc("nvm_item", length, 0);
3634 rte_mem_lock_page(buf);
3638 dma_handle = rte_mem_virt2iova(buf);
3639 if (dma_handle == 0) {
3641 "unable to map response address to physical memory\n");
3644 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3645 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3646 req.dir_idx = rte_cpu_to_le_16(index);
3647 req.offset = rte_cpu_to_le_32(offset);
3648 req.len = rte_cpu_to_le_32(length);
3649 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3651 memcpy(data, buf, length);
3654 HWRM_CHECK_RESULT();
3660 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3663 struct hwrm_nvm_erase_dir_entry_input req = {0};
3664 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3666 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3667 req.dir_idx = rte_cpu_to_le_16(index);
3668 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3669 HWRM_CHECK_RESULT();
3676 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3677 uint16_t dir_ordinal, uint16_t dir_ext,
3678 uint16_t dir_attr, const uint8_t *data,
3682 struct hwrm_nvm_write_input req = {0};
3683 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3684 rte_iova_t dma_handle;
3687 buf = rte_malloc("nvm_write", data_len, 0);
3688 rte_mem_lock_page(buf);
3692 dma_handle = rte_mem_virt2iova(buf);
3693 if (dma_handle == 0) {
3695 "unable to map response address to physical memory\n");
3698 memcpy(buf, data, data_len);
3700 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3702 req.dir_type = rte_cpu_to_le_16(dir_type);
3703 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3704 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3705 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3706 req.dir_data_length = rte_cpu_to_le_32(data_len);
3707 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3709 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3712 HWRM_CHECK_RESULT();
3719 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3721 uint32_t *count = cbdata;
3723 *count = *count + 1;
3726 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3727 struct bnxt_vnic_info *vnic __rte_unused)
3732 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3736 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3737 &count, bnxt_vnic_count_hwrm_stub);
3742 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3745 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3746 struct hwrm_func_vf_vnic_ids_query_output *resp =
3747 bp->hwrm_cmd_resp_addr;
3750 /* First query all VNIC ids */
3751 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3753 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3754 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3755 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3757 if (req.vnic_id_tbl_addr == 0) {
3760 "unable to map VNIC ID table address to physical memory\n");
3763 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3766 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3768 } else if (resp->error_code) {
3769 rc = rte_le_to_cpu_16(resp->error_code);
3771 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3774 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3782 * This function queries the VNIC IDs for a specified VF. It then calls
3783 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3784 * Then it calls the hwrm_cb function to program this new vnic configuration.
3786 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3787 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3788 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3790 struct bnxt_vnic_info vnic;
3792 int i, num_vnic_ids;
3797 /* First query all VNIC ids */
3798 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3799 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3800 RTE_CACHE_LINE_SIZE);
3801 if (vnic_ids == NULL) {
3805 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3806 rte_mem_lock_page(((char *)vnic_ids) + sz);
3808 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3810 if (num_vnic_ids < 0)
3811 return num_vnic_ids;
3813 /* Retrieve VNIC, update bd_stall then update */
3815 for (i = 0; i < num_vnic_ids; i++) {
3816 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3817 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3818 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3821 if (vnic.mru <= 4) /* Indicates unallocated */
3824 vnic_cb(&vnic, cbdata);
3826 rc = hwrm_cb(bp, &vnic);
3836 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3839 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3840 struct hwrm_func_cfg_input req = {0};
3843 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3845 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3846 req.enables |= rte_cpu_to_le_32(
3847 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3848 req.vlan_antispoof_mode = on ?
3849 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3850 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3853 HWRM_CHECK_RESULT();
3859 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3861 struct bnxt_vnic_info vnic;
3864 int num_vnic_ids, i;
3868 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3869 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3870 RTE_CACHE_LINE_SIZE);
3871 if (vnic_ids == NULL) {
3876 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3877 rte_mem_lock_page(((char *)vnic_ids) + sz);
3879 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3885 * Loop through to find the default VNIC ID.
3886 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3887 * by sending the hwrm_func_qcfg command to the firmware.
3889 for (i = 0; i < num_vnic_ids; i++) {
3890 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3891 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3892 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3893 bp->pf.first_vf_id + vf);
3896 if (vnic.func_default) {
3898 return vnic.fw_vnic_id;
3901 /* Could not find a default VNIC. */
3902 PMD_DRV_LOG(ERR, "No default VNIC\n");
3908 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3910 struct bnxt_filter_info *filter)
3913 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3914 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3915 uint32_t enables = 0;
3917 if (filter->fw_em_filter_id != UINT64_MAX)
3918 bnxt_hwrm_clear_em_filter(bp, filter);
3920 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3922 req.flags = rte_cpu_to_le_32(filter->flags);
3924 enables = filter->enables |
3925 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3926 req.dst_id = rte_cpu_to_le_16(dst_id);
3928 if (filter->ip_addr_type) {
3929 req.ip_addr_type = filter->ip_addr_type;
3930 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3933 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3934 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3936 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3937 memcpy(req.src_macaddr, filter->src_macaddr,
3938 RTE_ETHER_ADDR_LEN);
3940 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3941 memcpy(req.dst_macaddr, filter->dst_macaddr,
3942 RTE_ETHER_ADDR_LEN);
3944 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3945 req.ovlan_vid = filter->l2_ovlan;
3947 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3948 req.ivlan_vid = filter->l2_ivlan;
3950 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3951 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3953 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3954 req.ip_protocol = filter->ip_protocol;
3956 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3957 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3959 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3960 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3962 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3963 req.src_port = rte_cpu_to_be_16(filter->src_port);
3965 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3966 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3968 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3969 req.mirror_vnic_id = filter->mirror_vnic_id;
3971 req.enables = rte_cpu_to_le_32(enables);
3973 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3975 HWRM_CHECK_RESULT();
3977 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3983 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3986 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3987 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3989 if (filter->fw_em_filter_id == UINT64_MAX)
3992 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3993 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3995 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3997 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3999 HWRM_CHECK_RESULT();
4002 filter->fw_em_filter_id = UINT64_MAX;
4003 filter->fw_l2_filter_id = UINT64_MAX;
4008 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4010 struct bnxt_filter_info *filter)
4013 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4014 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4015 bp->hwrm_cmd_resp_addr;
4016 uint32_t enables = 0;
4018 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4019 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4021 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4023 req.flags = rte_cpu_to_le_32(filter->flags);
4025 enables = filter->enables |
4026 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4027 req.dst_id = rte_cpu_to_le_16(dst_id);
4030 if (filter->ip_addr_type) {
4031 req.ip_addr_type = filter->ip_addr_type;
4033 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4036 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4037 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4039 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4040 memcpy(req.src_macaddr, filter->src_macaddr,
4041 RTE_ETHER_ADDR_LEN);
4043 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4044 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4045 //RTE_ETHER_ADDR_LEN);
4047 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4048 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4050 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4051 req.ip_protocol = filter->ip_protocol;
4053 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4054 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4056 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4057 req.src_ipaddr_mask[0] =
4058 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4060 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4061 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4063 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4064 req.dst_ipaddr_mask[0] =
4065 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4067 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4068 req.src_port = rte_cpu_to_le_16(filter->src_port);
4070 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4071 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4073 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4074 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4076 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4077 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4079 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4080 req.mirror_vnic_id = filter->mirror_vnic_id;
4082 req.enables = rte_cpu_to_le_32(enables);
4084 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4086 HWRM_CHECK_RESULT();
4088 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4094 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4095 struct bnxt_filter_info *filter)
4098 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4099 struct hwrm_cfa_ntuple_filter_free_output *resp =
4100 bp->hwrm_cmd_resp_addr;
4102 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4105 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4107 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4109 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4111 HWRM_CHECK_RESULT();
4114 filter->fw_ntuple_filter_id = UINT64_MAX;
4120 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4122 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4123 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4124 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4125 int nr_ctxs = bp->max_ring_grps;
4126 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4127 uint16_t *ring_tbl = vnic->rss_table;
4128 int max_rings = bp->rx_nr_rings;
4132 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4134 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4135 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4136 req.hash_mode_flags = vnic->hash_mode;
4138 req.ring_grp_tbl_addr =
4139 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4140 req.hash_key_tbl_addr =
4141 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4143 for (i = 0, k = 0; i < nr_ctxs; i++) {
4144 struct bnxt_rx_ring_info *rxr;
4145 struct bnxt_cp_ring_info *cpr;
4147 req.ring_table_pair_index = i;
4148 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4150 for (j = 0; j < 64; j++) {
4153 /* Find next active ring. */
4154 for (cnt = 0; cnt < max_rings; cnt++) {
4155 if (rx_queue_state[k] !=
4156 RTE_ETH_QUEUE_STATE_STOPPED)
4158 if (++k == max_rings)
4162 /* Return if no rings are active. */
4163 if (cnt == max_rings)
4166 /* Add rx/cp ring pair to RSS table. */
4167 rxr = rxqs[k]->rx_ring;
4168 cpr = rxqs[k]->cp_ring;
4170 ring_id = rxr->rx_ring_struct->fw_ring_id;
4171 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4172 ring_id = cpr->cp_ring_struct->fw_ring_id;
4173 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4175 if (++k == max_rings)
4178 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4181 HWRM_CHECK_RESULT();
4191 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4193 unsigned int rss_idx, fw_idx, i;
4195 if (!(vnic->rss_table && vnic->hash_type))
4198 if (BNXT_CHIP_THOR(bp))
4199 return bnxt_vnic_rss_configure_thor(bp, vnic);
4202 * Fill the RSS hash & redirection table with
4203 * ring group ids for all VNICs
4205 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4206 rss_idx++, fw_idx++) {
4207 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4208 fw_idx %= bp->rx_cp_nr_rings;
4209 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4213 if (i == bp->rx_cp_nr_rings)
4215 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4217 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4220 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4221 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4225 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4227 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4228 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4230 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4231 req->num_cmpl_dma_aggr_during_int =
4232 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4234 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4236 /* min timer set to 1/2 of interrupt timer */
4237 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4239 /* buf timer set to 1/4 of interrupt timer */
4240 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4242 req->cmpl_aggr_dma_tmr_during_int =
4243 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4245 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4246 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4247 req->flags = rte_cpu_to_le_16(flags);
4250 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4251 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4253 struct hwrm_ring_aggint_qcaps_input req = {0};
4254 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4259 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4260 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4264 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4265 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4267 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4268 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4269 agg_req->flags = rte_cpu_to_le_16(flags);
4271 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4272 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4273 agg_req->enables = rte_cpu_to_le_32(enables);
4276 HWRM_CHECK_RESULT();
4281 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4282 struct bnxt_coal *coal, uint16_t ring_id)
4284 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4285 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4286 bp->hwrm_cmd_resp_addr;
4289 /* Set ring coalesce parameters only for 100G NICs */
4290 if (BNXT_CHIP_THOR(bp)) {
4291 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4293 } else if (bnxt_stratus_device(bp)) {
4294 bnxt_hwrm_set_coal_params(coal, &req);
4299 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4300 req.ring_id = rte_cpu_to_le_16(ring_id);
4301 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4302 HWRM_CHECK_RESULT();
4307 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4308 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4310 struct hwrm_func_backing_store_qcaps_input req = {0};
4311 struct hwrm_func_backing_store_qcaps_output *resp =
4312 bp->hwrm_cmd_resp_addr;
4315 if (!BNXT_CHIP_THOR(bp) ||
4316 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4321 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4322 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4323 HWRM_CHECK_RESULT_SILENT();
4326 struct bnxt_ctx_pg_info *ctx_pg;
4327 struct bnxt_ctx_mem_info *ctx;
4328 int total_alloc_len;
4331 total_alloc_len = sizeof(*ctx);
4332 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4333 RTE_CACHE_LINE_SIZE);
4338 memset(ctx, 0, total_alloc_len);
4340 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4341 sizeof(*ctx_pg) * BNXT_MAX_Q,
4342 RTE_CACHE_LINE_SIZE);
4347 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4348 ctx->tqm_mem[i] = ctx_pg;
4351 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4352 ctx->qp_min_qp1_entries =
4353 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4354 ctx->qp_max_l2_entries =
4355 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4356 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4357 ctx->srq_max_l2_entries =
4358 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4359 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4360 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4361 ctx->cq_max_l2_entries =
4362 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4363 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4364 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4365 ctx->vnic_max_vnic_entries =
4366 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4367 ctx->vnic_max_ring_table_entries =
4368 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4369 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4370 ctx->stat_max_entries =
4371 rte_le_to_cpu_32(resp->stat_max_entries);
4372 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4373 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4374 ctx->tqm_min_entries_per_ring =
4375 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4376 ctx->tqm_max_entries_per_ring =
4377 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4378 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4379 if (!ctx->tqm_entries_multiple)
4380 ctx->tqm_entries_multiple = 1;
4381 ctx->mrav_max_entries =
4382 rte_le_to_cpu_32(resp->mrav_max_entries);
4383 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4384 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4385 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4394 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4396 struct hwrm_func_backing_store_cfg_input req = {0};
4397 struct hwrm_func_backing_store_cfg_output *resp =
4398 bp->hwrm_cmd_resp_addr;
4399 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4400 struct bnxt_ctx_pg_info *ctx_pg;
4401 uint32_t *num_entries;
4410 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4411 req.enables = rte_cpu_to_le_32(enables);
4413 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4414 ctx_pg = &ctx->qp_mem;
4415 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4416 req.qp_num_qp1_entries =
4417 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4418 req.qp_num_l2_entries =
4419 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4420 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4421 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4422 &req.qpc_pg_size_qpc_lvl,
4426 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4427 ctx_pg = &ctx->srq_mem;
4428 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4429 req.srq_num_l2_entries =
4430 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4431 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4432 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4433 &req.srq_pg_size_srq_lvl,
4437 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4438 ctx_pg = &ctx->cq_mem;
4439 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4440 req.cq_num_l2_entries =
4441 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4442 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4443 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4444 &req.cq_pg_size_cq_lvl,
4448 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4449 ctx_pg = &ctx->vnic_mem;
4450 req.vnic_num_vnic_entries =
4451 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4452 req.vnic_num_ring_table_entries =
4453 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4454 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4455 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4456 &req.vnic_pg_size_vnic_lvl,
4457 &req.vnic_page_dir);
4460 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4461 ctx_pg = &ctx->stat_mem;
4462 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4463 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4464 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4465 &req.stat_pg_size_stat_lvl,
4466 &req.stat_page_dir);
4469 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4470 num_entries = &req.tqm_sp_num_entries;
4471 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4472 pg_dir = &req.tqm_sp_page_dir;
4473 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4474 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4475 if (!(enables & ena))
4478 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4480 ctx_pg = ctx->tqm_mem[i];
4481 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4482 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4485 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4486 HWRM_CHECK_RESULT();
4493 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4495 struct hwrm_port_qstats_ext_input req = {0};
4496 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4497 struct bnxt_pf_info *pf = &bp->pf;
4500 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4501 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4504 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4506 req.port_id = rte_cpu_to_le_16(pf->port_id);
4507 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4508 req.tx_stat_host_addr =
4509 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4511 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4513 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4514 req.rx_stat_host_addr =
4515 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4517 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4519 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4522 bp->fw_rx_port_stats_ext_size = 0;
4523 bp->fw_tx_port_stats_ext_size = 0;
4525 bp->fw_rx_port_stats_ext_size =
4526 rte_le_to_cpu_16(resp->rx_stat_size);
4527 bp->fw_tx_port_stats_ext_size =
4528 rte_le_to_cpu_16(resp->tx_stat_size);
4531 HWRM_CHECK_RESULT();
4538 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4540 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4541 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4542 bp->hwrm_cmd_resp_addr;
4545 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_KONG(bp));
4546 req.tunnel_type = type;
4547 req.dest_fid = bp->fw_fid;
4548 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4549 HWRM_CHECK_RESULT();
4557 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4559 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4560 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4561 bp->hwrm_cmd_resp_addr;
4564 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_KONG(bp));
4565 req.tunnel_type = type;
4566 req.dest_fid = bp->fw_fid;
4567 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4568 HWRM_CHECK_RESULT();
4575 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4577 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4578 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4579 bp->hwrm_cmd_resp_addr;
4582 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_KONG(bp));
4583 req.src_fid = bp->fw_fid;
4584 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4585 HWRM_CHECK_RESULT();
4588 *type = resp->tunnel_mask;
4595 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4598 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4599 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4600 bp->hwrm_cmd_resp_addr;
4603 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_KONG(bp));
4604 req.src_fid = bp->fw_fid;
4605 req.tunnel_type = tun_type;
4606 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4607 HWRM_CHECK_RESULT();
4610 *dst_fid = resp->dest_fid;
4612 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4619 int bnxt_hwrm_set_mac(struct bnxt *bp)
4621 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4622 struct hwrm_func_vf_cfg_input req = {0};
4628 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4631 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4632 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4634 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4636 HWRM_CHECK_RESULT();
4638 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);