1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SPEC_CODE_1_8_3 0x10803
31 #define HWRM_VERSION_1_9_1 0x10901
32 #define HWRM_VERSION_1_9_2 0x10903
34 struct bnxt_plcmodes_cfg {
36 uint16_t jumbo_thresh;
38 uint16_t hds_threshold;
41 static int page_getenum(size_t size)
57 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
58 return sizeof(void *) * 8 - 1;
61 static int page_roundup(size_t size)
63 return 1 << page_getenum(size);
66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
79 * HWRM Functions (sent to HWRM)
80 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
81 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
82 * command was failed by the ChiMP.
85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
86 uint32_t msg_len, bool use_kong_mb)
89 struct input *req = msg;
90 struct output *resp = bp->hwrm_cmd_resp_addr;
94 uint16_t max_req_len = bp->max_req_len;
95 struct hwrm_short_input short_input = { 0 };
96 uint16_t bar_offset = use_kong_mb ?
97 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
98 uint16_t mb_trigger_offset = use_kong_mb ?
99 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
101 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
102 msg_len > bp->max_req_len) {
103 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
105 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
106 memcpy(short_cmd_req, req, msg_len);
108 short_input.req_type = rte_cpu_to_le_16(req->req_type);
109 short_input.signature = rte_cpu_to_le_16(
110 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
111 short_input.size = rte_cpu_to_le_16(msg_len);
112 short_input.req_addr =
113 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
115 data = (uint32_t *)&short_input;
116 msg_len = sizeof(short_input);
118 /* Sync memory write before updating doorbell */
121 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
124 /* Write request msg to hwrm channel */
125 for (i = 0; i < msg_len; i += 4) {
126 bar = (uint8_t *)bp->bar0 + bar_offset + i;
127 rte_write32(*data, bar);
131 /* Zero the rest of the request space */
132 for (; i < max_req_len; i += 4) {
133 bar = (uint8_t *)bp->bar0 + bar_offset + i;
137 /* Ring channel doorbell */
138 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
141 /* Poll for the valid bit */
142 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
143 /* Sanity check on the resp->resp_len */
145 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
146 /* Last byte of resp contains the valid key */
147 valid = (uint8_t *)resp + resp->resp_len - 1;
148 if (*valid == HWRM_RESP_VALID_KEY)
154 if (i >= HWRM_CMD_TIMEOUT) {
155 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
166 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
167 * spinlock, and does initial processing.
169 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
170 * releases the spinlock only if it returns. If the regular int return codes
171 * are not used by the function, HWRM_CHECK_RESULT() should not be used
172 * directly, rather it should be copied and modified to suit the function.
174 * HWRM_UNLOCK() must be called after all response processing is completed.
176 #define HWRM_PREP(req, type, kong) do { \
177 rte_spinlock_lock(&bp->hwrm_lock); \
178 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
179 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
180 req.cmpl_ring = rte_cpu_to_le_16(-1); \
181 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
182 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
183 req.target_id = rte_cpu_to_le_16(0xffff); \
184 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
187 #define HWRM_CHECK_RESULT_SILENT() do {\
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 if (resp->error_code) { \
193 rc = rte_le_to_cpu_16(resp->error_code); \
194 rte_spinlock_unlock(&bp->hwrm_lock); \
199 #define HWRM_CHECK_RESULT() do {\
201 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
202 rte_spinlock_unlock(&bp->hwrm_lock); \
203 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 if (resp->resp_len >= 16) { \
212 struct hwrm_err_output *tmp_hwrm_err_op = \
215 "error %d:%d:%08x:%04x\n", \
216 rc, tmp_hwrm_err_op->cmd_err, \
218 tmp_hwrm_err_op->opaque_0), \
220 tmp_hwrm_err_op->opaque_1)); \
222 PMD_DRV_LOG(ERR, "error %d\n", rc); \
224 rte_spinlock_unlock(&bp->hwrm_lock); \
225 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
233 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
238 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
239 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
241 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
242 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
254 struct bnxt_vnic_info *vnic,
256 struct bnxt_vlan_table_entry *vlan_table)
259 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
260 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
263 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
269 /* FIXME add multicast flag, when multicast adding options is supported
272 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
273 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
274 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
275 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
276 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
277 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
278 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
279 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
280 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
281 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
282 if (vnic->mc_addr_cnt) {
283 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
284 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
285 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
288 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
290 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
291 rte_mem_virt2iova(vlan_table));
292 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
294 req.mask = rte_cpu_to_le_32(mask);
296 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
306 struct bnxt_vlan_antispoof_table_entry *vlan_table)
309 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
310 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
311 bp->hwrm_cmd_resp_addr;
314 * Older HWRM versions did not support this command, and the set_rx_mask
315 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
316 * removed from set_rx_mask call, and this command was added.
318 * This command is also present from 1.7.8.11 and higher,
321 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
322 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
323 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
328 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
329 req.fid = rte_cpu_to_le_16(fid);
331 req.vlan_tag_mask_tbl_addr =
332 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
333 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
344 struct bnxt_filter_info *filter)
347 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
348 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
350 if (filter->fw_l2_filter_id == UINT64_MAX)
353 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
355 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
362 filter->fw_l2_filter_id = UINT64_MAX;
367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
369 struct bnxt_filter_info *filter)
372 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
374 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
375 const struct rte_eth_vmdq_rx_conf *conf =
376 &dev_conf->rx_adv_conf.vmdq_rx_conf;
377 uint32_t enables = 0;
378 uint16_t j = dst_id - 1;
380 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
381 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
382 conf->pool_map[j].pools & (1UL << j)) {
384 "Add vlan %u to vmdq pool %u\n",
385 conf->pool_map[j].vlan_id, j);
387 filter->l2_ivlan = conf->pool_map[j].vlan_id;
389 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
393 if (filter->fw_l2_filter_id != UINT64_MAX)
394 bnxt_hwrm_clear_l2_filter(bp, filter);
396 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
398 req.flags = rte_cpu_to_le_32(filter->flags);
400 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
402 enables = filter->enables |
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
404 req.dst_id = rte_cpu_to_le_16(dst_id);
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
408 memcpy(req.l2_addr, filter->l2_addr,
411 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
412 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
415 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
416 req.l2_ovlan = filter->l2_ovlan;
418 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
419 req.l2_ivlan = filter->l2_ivlan;
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
422 req.l2_ovlan_mask = filter->l2_ovlan_mask;
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
425 req.l2_ivlan_mask = filter->l2_ivlan_mask;
426 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
427 req.src_id = rte_cpu_to_le_32(filter->src_id);
428 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
429 req.src_type = filter->src_type;
431 req.enables = rte_cpu_to_le_32(enables);
433 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
437 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
445 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
446 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
453 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
456 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
459 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
460 if (ptp->tx_tstamp_en)
461 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
464 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
465 req.flags = rte_cpu_to_le_32(flags);
466 req.enables = rte_cpu_to_le_32
467 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
468 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
470 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
479 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
480 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
481 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
483 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
487 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
489 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
495 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
498 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
502 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
503 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
504 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
505 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
506 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
507 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
508 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
509 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
510 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
511 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
512 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
513 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
514 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
515 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
516 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
517 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
518 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
519 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
530 struct hwrm_func_qcaps_input req = {.req_type = 0 };
531 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
532 uint16_t new_max_vfs;
536 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
538 req.fid = rte_cpu_to_le_16(0xffff);
540 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
544 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
545 flags = rte_le_to_cpu_32(resp->flags);
547 bp->pf.port_id = resp->port_id;
548 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
549 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
550 new_max_vfs = bp->pdev->max_vfs;
551 if (new_max_vfs != bp->pf.max_vfs) {
553 rte_free(bp->pf.vf_info);
554 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
555 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
556 bp->pf.max_vfs = new_max_vfs;
557 for (i = 0; i < new_max_vfs; i++) {
558 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
559 bp->pf.vf_info[i].vlan_table =
560 rte_zmalloc("VF VLAN table",
563 if (bp->pf.vf_info[i].vlan_table == NULL)
565 "Fail to alloc VLAN table for VF %d\n",
569 bp->pf.vf_info[i].vlan_table);
570 bp->pf.vf_info[i].vlan_as_table =
571 rte_zmalloc("VF VLAN AS table",
574 if (bp->pf.vf_info[i].vlan_as_table == NULL)
576 "Alloc VLAN AS table for VF %d fail\n",
580 bp->pf.vf_info[i].vlan_as_table);
581 STAILQ_INIT(&bp->pf.vf_info[i].filter);
586 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
587 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
588 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
589 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
590 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
591 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
592 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
593 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
594 /* TODO: For now, do not support VMDq/RFS on VFs. */
599 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
603 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
605 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
606 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
607 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
608 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
610 bnxt_hwrm_ptp_qcfg(bp);
619 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
623 rc = __bnxt_hwrm_func_qcaps(bp);
624 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
625 rc = bnxt_alloc_ctx_mem(bp);
629 rc = bnxt_hwrm_func_resc_qcaps(bp);
631 bp->flags |= BNXT_FLAG_NEW_RM;
637 int bnxt_hwrm_func_reset(struct bnxt *bp)
640 struct hwrm_func_reset_input req = {.req_type = 0 };
641 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
643 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
645 req.enables = rte_cpu_to_le_32(0);
647 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
655 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
658 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
659 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
661 if (bp->flags & BNXT_FLAG_REGISTERED)
664 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
665 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
666 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
667 req.ver_maj = RTE_VER_YEAR;
668 req.ver_min = RTE_VER_MONTH;
669 req.ver_upd = RTE_VER_MINOR;
672 req.enables |= rte_cpu_to_le_32(
673 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
674 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
675 RTE_MIN(sizeof(req.vf_req_fwd),
676 sizeof(bp->pf.vf_req_fwd)));
679 * PF can sniff HWRM API issued by VF. This can be set up by
680 * linux driver and inherited by the DPDK PF driver. Clear
681 * this HWRM sniffer list in FW because DPDK PF driver does
685 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
688 req.async_event_fwd[0] |=
689 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
690 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
691 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
692 req.async_event_fwd[1] |=
693 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
694 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
696 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
701 bp->flags |= BNXT_FLAG_REGISTERED;
706 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
708 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
711 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
714 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
719 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
720 struct hwrm_func_vf_cfg_input req = {0};
722 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
724 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
725 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
726 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
727 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
728 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
730 if (BNXT_HAS_RING_GRPS(bp)) {
731 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
732 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
735 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
736 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
737 AGG_RING_MULTIPLIER);
738 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
739 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
741 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
742 if (bp->vf_resv_strategy ==
743 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
744 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
745 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
746 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
747 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
748 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
749 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
753 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
754 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
755 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
756 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
757 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
758 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
760 if (test && BNXT_HAS_RING_GRPS(bp))
761 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
763 req.flags = rte_cpu_to_le_32(flags);
764 req.enables |= rte_cpu_to_le_32(enables);
766 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
769 HWRM_CHECK_RESULT_SILENT();
777 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
780 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
781 struct hwrm_func_resource_qcaps_input req = {0};
783 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
784 req.fid = rte_cpu_to_le_16(0xffff);
786 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
791 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
792 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
793 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
794 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
795 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
796 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
797 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
798 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
800 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
801 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
802 if (bp->vf_resv_strategy >
803 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
804 bp->vf_resv_strategy =
805 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
811 int bnxt_hwrm_ver_get(struct bnxt *bp)
814 struct hwrm_ver_get_input req = {.req_type = 0 };
815 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
817 uint16_t max_resp_len;
818 char type[RTE_MEMZONE_NAMESIZE];
819 uint32_t dev_caps_cfg;
821 bp->max_req_len = HWRM_MAX_REQ_LEN;
822 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
824 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
825 req.hwrm_intf_min = HWRM_VERSION_MINOR;
826 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
828 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
832 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
833 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
834 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
835 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
836 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
837 (resp->hwrm_fw_min_8b << 16) |
838 (resp->hwrm_fw_bld_8b << 8) |
839 resp->hwrm_fw_rsvd_8b;
840 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
841 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
843 fw_version = resp->hwrm_intf_maj_8b << 16;
844 fw_version |= resp->hwrm_intf_min_8b << 8;
845 fw_version |= resp->hwrm_intf_upd_8b;
846 bp->hwrm_spec_code = fw_version;
848 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
849 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
854 if (bp->max_req_len > resp->max_req_win_len) {
855 PMD_DRV_LOG(ERR, "Unsupported request length\n");
858 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
859 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
860 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
861 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
863 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
864 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
866 if (bp->max_resp_len != max_resp_len) {
867 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
868 bp->pdev->addr.domain, bp->pdev->addr.bus,
869 bp->pdev->addr.devid, bp->pdev->addr.function);
871 rte_free(bp->hwrm_cmd_resp_addr);
873 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
874 if (bp->hwrm_cmd_resp_addr == NULL) {
878 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
879 bp->hwrm_cmd_resp_dma_addr =
880 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
881 if (bp->hwrm_cmd_resp_dma_addr == 0) {
883 "Unable to map response buffer to physical memory.\n");
887 bp->max_resp_len = max_resp_len;
891 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
893 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
894 PMD_DRV_LOG(DEBUG, "Short command supported\n");
895 bp->flags |= BNXT_FLAG_SHORT_CMD;
899 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
901 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
902 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
903 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
904 bp->pdev->addr.domain, bp->pdev->addr.bus,
905 bp->pdev->addr.devid, bp->pdev->addr.function);
907 rte_free(bp->hwrm_short_cmd_req_addr);
909 bp->hwrm_short_cmd_req_addr =
910 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
911 if (bp->hwrm_short_cmd_req_addr == NULL) {
915 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
916 bp->hwrm_short_cmd_req_dma_addr =
917 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
918 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
919 rte_free(bp->hwrm_short_cmd_req_addr);
921 "Unable to map buffer to physical memory.\n");
927 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
928 bp->flags |= BNXT_FLAG_KONG_MB_EN;
929 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
932 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
933 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
940 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
943 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
944 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
946 if (!(bp->flags & BNXT_FLAG_REGISTERED))
949 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
952 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
957 bp->flags &= ~BNXT_FLAG_REGISTERED;
962 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
965 struct hwrm_port_phy_cfg_input req = {0};
966 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
967 uint32_t enables = 0;
969 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
972 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
973 if (bp->link_info.auto_mode && conf->link_speed) {
974 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
975 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
978 req.flags = rte_cpu_to_le_32(conf->phy_flags);
979 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
980 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
982 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
983 * any auto mode, even "none".
985 if (!conf->link_speed) {
986 /* No speeds specified. Enable AutoNeg - all speeds */
988 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
990 /* AutoNeg - Advertise speeds specified. */
991 if (conf->auto_link_speed_mask &&
992 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
994 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
995 req.auto_link_speed_mask =
996 conf->auto_link_speed_mask;
998 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1001 req.auto_duplex = conf->duplex;
1002 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1003 req.auto_pause = conf->auto_pause;
1004 req.force_pause = conf->force_pause;
1005 /* Set force_pause if there is no auto or if there is a force */
1006 if (req.auto_pause && !req.force_pause)
1007 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1009 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1011 req.enables = rte_cpu_to_le_32(enables);
1014 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1015 PMD_DRV_LOG(INFO, "Force Link Down\n");
1018 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1020 HWRM_CHECK_RESULT();
1026 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1027 struct bnxt_link_info *link_info)
1030 struct hwrm_port_phy_qcfg_input req = {0};
1031 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1033 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1035 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1037 HWRM_CHECK_RESULT();
1039 link_info->phy_link_status = resp->link;
1040 link_info->link_up =
1041 (link_info->phy_link_status ==
1042 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1043 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1044 link_info->duplex = resp->duplex_cfg;
1045 link_info->pause = resp->pause;
1046 link_info->auto_pause = resp->auto_pause;
1047 link_info->force_pause = resp->force_pause;
1048 link_info->auto_mode = resp->auto_mode;
1049 link_info->phy_type = resp->phy_type;
1050 link_info->media_type = resp->media_type;
1052 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1053 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1054 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1055 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1056 link_info->phy_ver[0] = resp->phy_maj;
1057 link_info->phy_ver[1] = resp->phy_min;
1058 link_info->phy_ver[2] = resp->phy_bld;
1062 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1063 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1064 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1065 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1066 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1067 link_info->auto_link_speed_mask);
1068 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1069 link_info->force_link_speed);
1074 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1077 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1078 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1081 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1083 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1084 /* HWRM Version >= 1.9.1 */
1085 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1087 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1088 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1090 HWRM_CHECK_RESULT();
1092 #define GET_QUEUE_INFO(x) \
1093 bp->cos_queue[x].id = resp->queue_id##x; \
1094 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1107 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1108 bp->tx_cosq_id = bp->cos_queue[0].id;
1110 /* iterate and find the COSq profile to use for Tx */
1111 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1112 if (bp->cos_queue[i].profile ==
1113 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1114 bp->tx_cosq_id = bp->cos_queue[i].id;
1120 bp->max_tc = resp->max_configurable_queues;
1121 bp->max_lltc = resp->max_configurable_lossless_queues;
1122 if (bp->max_tc > BNXT_MAX_QUEUE)
1123 bp->max_tc = BNXT_MAX_QUEUE;
1124 bp->max_q = bp->max_tc;
1126 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1131 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1132 struct bnxt_ring *ring,
1133 uint32_t ring_type, uint32_t map_index,
1134 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1137 uint32_t enables = 0;
1138 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1139 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1140 struct rte_mempool *mb_pool;
1141 uint16_t rx_buf_size;
1143 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1145 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1146 req.fbo = rte_cpu_to_le_32(0);
1147 /* Association of ring index with doorbell index */
1148 req.logical_id = rte_cpu_to_le_16(map_index);
1149 req.length = rte_cpu_to_le_32(ring->ring_size);
1151 switch (ring_type) {
1152 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1153 req.ring_type = ring_type;
1154 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1155 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1156 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1157 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1159 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1161 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1162 req.ring_type = ring_type;
1163 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1164 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1165 if (BNXT_CHIP_THOR(bp)) {
1166 mb_pool = bp->rx_queues[0]->mb_pool;
1167 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1168 RTE_PKTMBUF_HEADROOM;
1169 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1171 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1173 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1175 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1177 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1178 req.ring_type = ring_type;
1179 if (BNXT_HAS_NQ(bp)) {
1180 /* Association of cp ring with nq */
1181 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1183 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1185 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1187 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1188 req.ring_type = ring_type;
1189 req.page_size = BNXT_PAGE_SHFT;
1190 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1192 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1193 req.ring_type = ring_type;
1194 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1196 mb_pool = bp->rx_queues[0]->mb_pool;
1197 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1198 RTE_PKTMBUF_HEADROOM;
1199 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1201 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1202 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1203 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1204 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1207 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1212 req.enables = rte_cpu_to_le_32(enables);
1214 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1216 if (rc || resp->error_code) {
1217 if (rc == 0 && resp->error_code)
1218 rc = rte_le_to_cpu_16(resp->error_code);
1219 switch (ring_type) {
1220 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1222 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1225 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1227 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1230 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1232 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1236 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1238 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1241 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1243 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1247 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1253 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1258 int bnxt_hwrm_ring_free(struct bnxt *bp,
1259 struct bnxt_ring *ring, uint32_t ring_type)
1262 struct hwrm_ring_free_input req = {.req_type = 0 };
1263 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1265 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1267 req.ring_type = ring_type;
1268 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1270 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1272 if (rc || resp->error_code) {
1273 if (rc == 0 && resp->error_code)
1274 rc = rte_le_to_cpu_16(resp->error_code);
1277 switch (ring_type) {
1278 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1279 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1282 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1283 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1286 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1287 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1290 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1292 "hwrm_ring_free nq failed. rc:%d\n", rc);
1294 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1296 "hwrm_ring_free agg failed. rc:%d\n", rc);
1299 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1307 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1310 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1311 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1313 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1315 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1316 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1317 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1318 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1320 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1322 HWRM_CHECK_RESULT();
1324 bp->grp_info[idx].fw_grp_id =
1325 rte_le_to_cpu_16(resp->ring_group_id);
1332 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1335 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1336 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1338 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1340 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1342 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1344 HWRM_CHECK_RESULT();
1347 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1351 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1354 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1355 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1357 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1360 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1362 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1364 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1366 HWRM_CHECK_RESULT();
1372 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1373 unsigned int idx __rte_unused)
1376 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1377 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1379 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1381 req.update_period_ms = rte_cpu_to_le_32(0);
1383 req.stats_dma_addr =
1384 rte_cpu_to_le_64(cpr->hw_stats_map);
1386 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1388 HWRM_CHECK_RESULT();
1390 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1397 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1398 unsigned int idx __rte_unused)
1401 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1402 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1404 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1406 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1408 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1410 HWRM_CHECK_RESULT();
1416 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1419 struct hwrm_vnic_alloc_input req = { 0 };
1420 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1422 if (!BNXT_HAS_RING_GRPS(bp))
1423 goto skip_ring_grps;
1425 /* map ring groups to this vnic */
1426 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1427 vnic->start_grp_id, vnic->end_grp_id);
1428 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1429 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1431 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1432 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1433 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1434 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1437 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1438 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1439 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1441 if (vnic->func_default)
1443 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1444 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1446 HWRM_CHECK_RESULT();
1448 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1450 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1454 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1455 struct bnxt_vnic_info *vnic,
1456 struct bnxt_plcmodes_cfg *pmode)
1459 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1460 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1462 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1464 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1466 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1468 HWRM_CHECK_RESULT();
1470 pmode->flags = rte_le_to_cpu_32(resp->flags);
1471 /* dflt_vnic bit doesn't exist in the _cfg command */
1472 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1473 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1474 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1475 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1482 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1483 struct bnxt_vnic_info *vnic,
1484 struct bnxt_plcmodes_cfg *pmode)
1487 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1488 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1490 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1492 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1493 req.flags = rte_cpu_to_le_32(pmode->flags);
1494 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1495 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1496 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1497 req.enables = rte_cpu_to_le_32(
1498 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1499 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1500 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1503 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1505 HWRM_CHECK_RESULT();
1511 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1514 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1515 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1516 uint32_t ctx_enable_flag = 0;
1517 struct bnxt_plcmodes_cfg pmodes;
1518 uint32_t enables = 0;
1520 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1521 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1525 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1529 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1531 if (BNXT_CHIP_THOR(bp)) {
1532 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1533 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1534 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1536 req.default_rx_ring_id =
1537 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1538 req.default_cmpl_ring_id =
1539 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1540 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1541 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1545 /* Only RSS support for now TBD: COS & LB */
1546 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1547 if (vnic->lb_rule != 0xffff)
1548 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1549 if (vnic->cos_rule != 0xffff)
1550 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1551 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1552 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1553 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1555 enables |= ctx_enable_flag;
1556 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1557 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1558 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1559 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1562 req.enables = rte_cpu_to_le_32(enables);
1563 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1564 req.mru = rte_cpu_to_le_16(vnic->mru);
1565 /* Configure default VNIC only once. */
1566 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1568 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1569 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1571 if (vnic->vlan_strip)
1573 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1576 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1577 if (vnic->roce_dual)
1578 req.flags |= rte_cpu_to_le_32(
1579 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1580 if (vnic->roce_only)
1581 req.flags |= rte_cpu_to_le_32(
1582 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1583 if (vnic->rss_dflt_cr)
1584 req.flags |= rte_cpu_to_le_32(
1585 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1587 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1589 HWRM_CHECK_RESULT();
1592 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1597 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1601 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1602 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1604 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1605 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1608 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1611 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1612 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1613 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1615 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1617 HWRM_CHECK_RESULT();
1619 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1620 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1621 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1622 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1623 vnic->mru = rte_le_to_cpu_16(resp->mru);
1624 vnic->func_default = rte_le_to_cpu_32(
1625 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1626 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1627 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1628 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1629 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1630 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1631 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1632 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1633 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1634 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1635 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1642 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1643 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1647 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1648 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1649 bp->hwrm_cmd_resp_addr;
1651 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1653 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1654 HWRM_CHECK_RESULT();
1656 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1657 if (!BNXT_HAS_RING_GRPS(bp))
1658 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1659 else if (ctx_idx == 0)
1660 vnic->rss_rule = ctx_id;
1667 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1668 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1671 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1672 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1673 bp->hwrm_cmd_resp_addr;
1675 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1676 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1679 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1681 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1683 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1685 HWRM_CHECK_RESULT();
1691 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1694 struct hwrm_vnic_free_input req = {.req_type = 0 };
1695 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1697 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1698 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1702 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1704 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1706 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1708 HWRM_CHECK_RESULT();
1711 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1712 /* Configure default VNIC again if necessary. */
1713 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1714 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1720 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1724 int nr_ctxs = bp->max_ring_grps;
1725 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1726 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1728 if (!(vnic->rss_table && vnic->hash_type))
1731 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1733 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1734 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1735 req.hash_mode_flags = vnic->hash_mode;
1737 req.hash_key_tbl_addr =
1738 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1740 for (i = 0; i < nr_ctxs; i++) {
1741 req.ring_grp_tbl_addr =
1742 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1743 i * HW_HASH_INDEX_SIZE);
1744 req.ring_table_pair_index = i;
1745 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1747 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1750 HWRM_CHECK_RESULT();
1760 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1761 struct bnxt_vnic_info *vnic)
1764 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1765 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1767 if (BNXT_CHIP_THOR(bp))
1768 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1770 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1772 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1773 req.hash_mode_flags = vnic->hash_mode;
1775 req.ring_grp_tbl_addr =
1776 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1777 req.hash_key_tbl_addr =
1778 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1779 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1780 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1782 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1784 HWRM_CHECK_RESULT();
1790 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1791 struct bnxt_vnic_info *vnic)
1794 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1795 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1798 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1799 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1803 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1805 req.flags = rte_cpu_to_le_32(
1806 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1808 req.enables = rte_cpu_to_le_32(
1809 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1811 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1812 size -= RTE_PKTMBUF_HEADROOM;
1814 req.jumbo_thresh = rte_cpu_to_le_16(size);
1815 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1817 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1819 HWRM_CHECK_RESULT();
1825 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1826 struct bnxt_vnic_info *vnic, bool enable)
1829 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1830 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1832 if (BNXT_CHIP_THOR(bp))
1835 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1838 req.enables = rte_cpu_to_le_32(
1839 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1840 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1841 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1842 req.flags = rte_cpu_to_le_32(
1843 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1844 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1845 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1846 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1847 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1848 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1849 req.max_agg_segs = rte_cpu_to_le_16(5);
1851 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1852 req.min_agg_len = rte_cpu_to_le_32(512);
1854 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1856 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1858 HWRM_CHECK_RESULT();
1864 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1866 struct hwrm_func_cfg_input req = {0};
1867 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1870 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1871 req.enables = rte_cpu_to_le_32(
1872 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1873 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1874 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1876 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1878 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1879 HWRM_CHECK_RESULT();
1882 bp->pf.vf_info[vf].random_mac = false;
1887 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1891 struct hwrm_func_qstats_input req = {.req_type = 0};
1892 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1894 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1896 req.fid = rte_cpu_to_le_16(fid);
1898 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1900 HWRM_CHECK_RESULT();
1903 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1910 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1911 struct rte_eth_stats *stats)
1914 struct hwrm_func_qstats_input req = {.req_type = 0};
1915 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1917 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1919 req.fid = rte_cpu_to_le_16(fid);
1921 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1923 HWRM_CHECK_RESULT();
1925 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1926 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1927 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1928 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1929 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1930 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1932 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1933 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1934 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1935 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1936 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1937 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1939 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1940 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1941 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1948 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1951 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1952 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1954 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1956 req.fid = rte_cpu_to_le_16(fid);
1958 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1960 HWRM_CHECK_RESULT();
1967 * HWRM utility functions
1970 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1975 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1976 struct bnxt_tx_queue *txq;
1977 struct bnxt_rx_queue *rxq;
1978 struct bnxt_cp_ring_info *cpr;
1980 if (i >= bp->rx_cp_nr_rings) {
1981 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1984 rxq = bp->rx_queues[i];
1988 rc = bnxt_hwrm_stat_clear(bp, cpr);
1995 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1999 struct bnxt_cp_ring_info *cpr;
2001 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2003 if (i >= bp->rx_cp_nr_rings) {
2004 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2006 cpr = bp->rx_queues[i]->cp_ring;
2007 if (BNXT_HAS_RING_GRPS(bp))
2008 bp->grp_info[i].fw_stats_ctx = -1;
2010 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2011 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2012 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2020 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2025 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2026 struct bnxt_tx_queue *txq;
2027 struct bnxt_rx_queue *rxq;
2028 struct bnxt_cp_ring_info *cpr;
2030 if (i >= bp->rx_cp_nr_rings) {
2031 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2034 rxq = bp->rx_queues[i];
2038 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2046 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2051 if (!BNXT_HAS_RING_GRPS(bp))
2054 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2056 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2059 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2067 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2069 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2071 bnxt_hwrm_ring_free(bp, cp_ring,
2072 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2073 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2074 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2075 sizeof(*cpr->cp_desc_ring));
2076 cpr->cp_raw_cons = 0;
2079 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2081 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2083 bnxt_hwrm_ring_free(bp, cp_ring,
2084 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2085 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2086 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2087 sizeof(*cpr->cp_desc_ring));
2088 cpr->cp_raw_cons = 0;
2091 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2093 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2094 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2095 struct bnxt_ring *ring = rxr->rx_ring_struct;
2096 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2098 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2099 bnxt_hwrm_ring_free(bp, ring,
2100 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2101 ring->fw_ring_id = INVALID_HW_RING_ID;
2102 if (BNXT_HAS_RING_GRPS(bp))
2103 bp->grp_info[queue_index].rx_fw_ring_id =
2105 memset(rxr->rx_desc_ring, 0,
2106 rxr->rx_ring_struct->ring_size *
2107 sizeof(*rxr->rx_desc_ring));
2108 memset(rxr->rx_buf_ring, 0,
2109 rxr->rx_ring_struct->ring_size *
2110 sizeof(*rxr->rx_buf_ring));
2113 ring = rxr->ag_ring_struct;
2114 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2115 bnxt_hwrm_ring_free(bp, ring,
2116 BNXT_CHIP_THOR(bp) ?
2117 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2118 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2119 ring->fw_ring_id = INVALID_HW_RING_ID;
2120 memset(rxr->ag_buf_ring, 0,
2121 rxr->ag_ring_struct->ring_size *
2122 sizeof(*rxr->ag_buf_ring));
2124 if (BNXT_HAS_RING_GRPS(bp))
2125 bp->grp_info[queue_index].ag_fw_ring_id =
2128 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2129 bnxt_free_cp_ring(bp, cpr);
2131 bnxt_free_nq_ring(bp, rxq->nq_ring);
2134 if (BNXT_HAS_RING_GRPS(bp))
2135 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2138 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2142 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2143 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2144 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2145 struct bnxt_ring *ring = txr->tx_ring_struct;
2146 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2148 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2149 bnxt_hwrm_ring_free(bp, ring,
2150 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2151 ring->fw_ring_id = INVALID_HW_RING_ID;
2152 memset(txr->tx_desc_ring, 0,
2153 txr->tx_ring_struct->ring_size *
2154 sizeof(*txr->tx_desc_ring));
2155 memset(txr->tx_buf_ring, 0,
2156 txr->tx_ring_struct->ring_size *
2157 sizeof(*txr->tx_buf_ring));
2161 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2162 bnxt_free_cp_ring(bp, cpr);
2163 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2165 bnxt_free_nq_ring(bp, txq->nq_ring);
2169 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2170 bnxt_free_hwrm_rx_ring(bp, i);
2175 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2180 if (!BNXT_HAS_RING_GRPS(bp))
2183 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2184 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2191 void bnxt_free_hwrm_resources(struct bnxt *bp)
2193 /* Release memzone */
2194 rte_free(bp->hwrm_cmd_resp_addr);
2195 rte_free(bp->hwrm_short_cmd_req_addr);
2196 bp->hwrm_cmd_resp_addr = NULL;
2197 bp->hwrm_short_cmd_req_addr = NULL;
2198 bp->hwrm_cmd_resp_dma_addr = 0;
2199 bp->hwrm_short_cmd_req_dma_addr = 0;
2202 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2204 struct rte_pci_device *pdev = bp->pdev;
2205 char type[RTE_MEMZONE_NAMESIZE];
2207 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2208 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2209 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2210 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2211 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2212 if (bp->hwrm_cmd_resp_addr == NULL)
2214 bp->hwrm_cmd_resp_dma_addr =
2215 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2216 if (bp->hwrm_cmd_resp_dma_addr == 0) {
2218 "unable to map response address to physical memory\n");
2221 rte_spinlock_init(&bp->hwrm_lock);
2226 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2228 struct bnxt_filter_info *filter;
2231 STAILQ_FOREACH(filter, &vnic->filter, next) {
2232 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2233 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2234 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2235 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2237 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2238 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2246 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2248 struct bnxt_filter_info *filter;
2249 struct rte_flow *flow;
2252 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2253 filter = flow->filter;
2254 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2255 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2256 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2257 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2258 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2260 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2262 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2270 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2272 struct bnxt_filter_info *filter;
2275 STAILQ_FOREACH(filter, &vnic->filter, next) {
2276 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2277 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2279 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2280 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2283 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2291 void bnxt_free_tunnel_ports(struct bnxt *bp)
2293 if (bp->vxlan_port_cnt)
2294 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2295 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2297 if (bp->geneve_port_cnt)
2298 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2299 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2300 bp->geneve_port = 0;
2303 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2307 if (bp->vnic_info == NULL)
2311 * Cleanup VNICs in reverse order, to make sure the L2 filter
2312 * from vnic0 is last to be cleaned up.
2314 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2315 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2317 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2319 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2321 if (BNXT_CHIP_THOR(bp)) {
2322 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2323 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2324 vnic->fw_grp_ids[j]);
2325 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2327 vnic->num_lb_ctxts = 0;
2329 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2330 vnic->rss_rule = INVALID_HW_RING_ID;
2333 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2335 bnxt_hwrm_vnic_free(bp, vnic);
2337 rte_free(vnic->fw_grp_ids);
2339 /* Ring resources */
2340 bnxt_free_all_hwrm_rings(bp);
2341 bnxt_free_all_hwrm_ring_grps(bp);
2342 bnxt_free_all_hwrm_stat_ctxs(bp);
2343 bnxt_free_tunnel_ports(bp);
2346 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2348 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2350 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2351 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2353 switch (conf_link_speed) {
2354 case ETH_LINK_SPEED_10M_HD:
2355 case ETH_LINK_SPEED_100M_HD:
2357 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2359 return hw_link_duplex;
2362 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2364 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2367 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2369 uint16_t eth_link_speed = 0;
2371 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2372 return ETH_LINK_SPEED_AUTONEG;
2374 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2375 case ETH_LINK_SPEED_100M:
2376 case ETH_LINK_SPEED_100M_HD:
2379 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2381 case ETH_LINK_SPEED_1G:
2383 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2385 case ETH_LINK_SPEED_2_5G:
2387 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2389 case ETH_LINK_SPEED_10G:
2391 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2393 case ETH_LINK_SPEED_20G:
2395 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2397 case ETH_LINK_SPEED_25G:
2399 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2401 case ETH_LINK_SPEED_40G:
2403 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2405 case ETH_LINK_SPEED_50G:
2407 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2409 case ETH_LINK_SPEED_100G:
2411 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2415 "Unsupported link speed %d; default to AUTO\n",
2419 return eth_link_speed;
2422 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2423 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2424 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2425 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2427 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2431 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2434 if (link_speed & ETH_LINK_SPEED_FIXED) {
2435 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2437 if (one_speed & (one_speed - 1)) {
2439 "Invalid advertised speeds (%u) for port %u\n",
2440 link_speed, port_id);
2443 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2445 "Unsupported advertised speed (%u) for port %u\n",
2446 link_speed, port_id);
2450 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2452 "Unsupported advertised speeds (%u) for port %u\n",
2453 link_speed, port_id);
2461 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2465 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2466 if (bp->link_info.support_speeds)
2467 return bp->link_info.support_speeds;
2468 link_speed = BNXT_SUPPORTED_SPEEDS;
2471 if (link_speed & ETH_LINK_SPEED_100M)
2472 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2473 if (link_speed & ETH_LINK_SPEED_100M_HD)
2474 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2475 if (link_speed & ETH_LINK_SPEED_1G)
2476 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2477 if (link_speed & ETH_LINK_SPEED_2_5G)
2478 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2479 if (link_speed & ETH_LINK_SPEED_10G)
2480 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2481 if (link_speed & ETH_LINK_SPEED_20G)
2482 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2483 if (link_speed & ETH_LINK_SPEED_25G)
2484 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2485 if (link_speed & ETH_LINK_SPEED_40G)
2486 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2487 if (link_speed & ETH_LINK_SPEED_50G)
2488 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2489 if (link_speed & ETH_LINK_SPEED_100G)
2490 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2494 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2496 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2498 switch (hw_link_speed) {
2499 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2500 eth_link_speed = ETH_SPEED_NUM_100M;
2502 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2503 eth_link_speed = ETH_SPEED_NUM_1G;
2505 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2506 eth_link_speed = ETH_SPEED_NUM_2_5G;
2508 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2509 eth_link_speed = ETH_SPEED_NUM_10G;
2511 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2512 eth_link_speed = ETH_SPEED_NUM_20G;
2514 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2515 eth_link_speed = ETH_SPEED_NUM_25G;
2517 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2518 eth_link_speed = ETH_SPEED_NUM_40G;
2520 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2521 eth_link_speed = ETH_SPEED_NUM_50G;
2523 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2524 eth_link_speed = ETH_SPEED_NUM_100G;
2526 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2528 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2532 return eth_link_speed;
2535 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2537 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2539 switch (hw_link_duplex) {
2540 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2541 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2543 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2545 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2546 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2549 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2553 return eth_link_duplex;
2556 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2559 struct bnxt_link_info *link_info = &bp->link_info;
2561 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2564 "Get link config failed with rc %d\n", rc);
2567 if (link_info->link_speed)
2569 bnxt_parse_hw_link_speed(link_info->link_speed);
2571 link->link_speed = ETH_SPEED_NUM_NONE;
2572 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2573 link->link_status = link_info->link_up;
2574 link->link_autoneg = link_info->auto_mode ==
2575 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2576 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2581 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2584 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2585 struct bnxt_link_info link_req;
2586 uint16_t speed, autoneg;
2588 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2591 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2592 bp->eth_dev->data->port_id);
2596 memset(&link_req, 0, sizeof(link_req));
2597 link_req.link_up = link_up;
2601 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2602 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2603 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2604 /* Autoneg can be done only when the FW allows */
2605 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2606 bp->link_info.force_link_speed)) {
2607 link_req.phy_flags |=
2608 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2609 link_req.auto_link_speed_mask =
2610 bnxt_parse_eth_link_speed_mask(bp,
2611 dev_conf->link_speeds);
2613 if (bp->link_info.phy_type ==
2614 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2615 bp->link_info.phy_type ==
2616 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2617 bp->link_info.media_type ==
2618 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2619 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2623 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2624 /* If user wants a particular speed try that first. */
2626 link_req.link_speed = speed;
2627 else if (bp->link_info.force_link_speed)
2628 link_req.link_speed = bp->link_info.force_link_speed;
2630 link_req.link_speed = bp->link_info.auto_link_speed;
2632 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2633 link_req.auto_pause = bp->link_info.auto_pause;
2634 link_req.force_pause = bp->link_info.force_pause;
2637 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2640 "Set link config failed with rc %d\n", rc);
2648 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2650 struct hwrm_func_qcfg_input req = {0};
2651 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2655 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2656 req.fid = rte_cpu_to_le_16(0xffff);
2658 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2660 HWRM_CHECK_RESULT();
2662 /* Hard Coded.. 0xfff VLAN ID mask */
2663 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2664 flags = rte_le_to_cpu_16(resp->flags);
2665 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2666 bp->flags |= BNXT_FLAG_MULTI_HOST;
2668 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2669 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2670 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2676 switch (resp->port_partition_type) {
2677 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2678 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2679 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2681 bp->port_partition_type = resp->port_partition_type;
2684 bp->port_partition_type = 0;
2693 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2694 struct hwrm_func_qcaps_output *qcaps)
2696 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2697 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2698 sizeof(qcaps->mac_address));
2699 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2700 qcaps->max_rx_rings = fcfg->num_rx_rings;
2701 qcaps->max_tx_rings = fcfg->num_tx_rings;
2702 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2703 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2705 qcaps->first_vf_id = 0;
2706 qcaps->max_vnics = fcfg->num_vnics;
2707 qcaps->max_decap_records = 0;
2708 qcaps->max_encap_records = 0;
2709 qcaps->max_tx_wm_flows = 0;
2710 qcaps->max_tx_em_flows = 0;
2711 qcaps->max_rx_wm_flows = 0;
2712 qcaps->max_rx_em_flows = 0;
2713 qcaps->max_flow_id = 0;
2714 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2715 qcaps->max_sp_tx_rings = 0;
2716 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2719 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2721 struct hwrm_func_cfg_input req = {0};
2722 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2726 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2727 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2728 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2729 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2730 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2731 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2732 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2733 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2734 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2736 if (BNXT_HAS_RING_GRPS(bp)) {
2737 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2738 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2739 } else if (BNXT_HAS_NQ(bp)) {
2740 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2741 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2744 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2745 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2746 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2747 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2749 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2750 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2751 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2752 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2753 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2754 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2755 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2756 req.fid = rte_cpu_to_le_16(0xffff);
2757 req.enables = rte_cpu_to_le_32(enables);
2759 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2761 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2763 HWRM_CHECK_RESULT();
2769 static void populate_vf_func_cfg_req(struct bnxt *bp,
2770 struct hwrm_func_cfg_input *req,
2773 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2774 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2775 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2776 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2777 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2778 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2779 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2780 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2781 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2782 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2784 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2785 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2787 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2788 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2790 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2792 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2793 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2795 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2796 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2797 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2798 /* TODO: For now, do not support VMDq/RFS on VFs. */
2799 req->num_vnics = rte_cpu_to_le_16(1);
2800 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2804 static void add_random_mac_if_needed(struct bnxt *bp,
2805 struct hwrm_func_cfg_input *cfg_req,
2808 struct rte_ether_addr mac;
2810 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2813 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2815 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2816 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2817 bp->pf.vf_info[vf].random_mac = true;
2819 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2820 RTE_ETHER_ADDR_LEN);
2824 static void reserve_resources_from_vf(struct bnxt *bp,
2825 struct hwrm_func_cfg_input *cfg_req,
2828 struct hwrm_func_qcaps_input req = {0};
2829 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2832 /* Get the actual allocated values now */
2833 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2834 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2835 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2838 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2839 copy_func_cfg_to_qcaps(cfg_req, resp);
2840 } else if (resp->error_code) {
2841 rc = rte_le_to_cpu_16(resp->error_code);
2842 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2843 copy_func_cfg_to_qcaps(cfg_req, resp);
2846 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2847 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2848 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2849 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2850 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2851 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2853 * TODO: While not supporting VMDq with VFs, max_vnics is always
2854 * forced to 1 in this case
2856 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2857 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2862 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2864 struct hwrm_func_qcfg_input req = {0};
2865 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2868 /* Check for zero MAC address */
2869 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2870 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2871 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2873 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2875 } else if (resp->error_code) {
2876 rc = rte_le_to_cpu_16(resp->error_code);
2877 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2880 rc = rte_le_to_cpu_16(resp->vlan);
2887 static int update_pf_resource_max(struct bnxt *bp)
2889 struct hwrm_func_qcfg_input req = {0};
2890 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2893 /* And copy the allocated numbers into the pf struct */
2894 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2895 req.fid = rte_cpu_to_le_16(0xffff);
2896 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2897 HWRM_CHECK_RESULT();
2899 /* Only TX ring value reflects actual allocation? TODO */
2900 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2901 bp->pf.evb_mode = resp->evb_mode;
2908 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2913 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2917 rc = bnxt_hwrm_func_qcaps(bp);
2921 bp->pf.func_cfg_flags &=
2922 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2923 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2924 bp->pf.func_cfg_flags |=
2925 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2926 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2927 rc = __bnxt_hwrm_func_qcaps(bp);
2931 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2933 struct hwrm_func_cfg_input req = {0};
2934 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2941 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2945 rc = bnxt_hwrm_func_qcaps(bp);
2950 bp->pf.active_vfs = num_vfs;
2953 * First, configure the PF to only use one TX ring. This ensures that
2954 * there are enough rings for all VFs.
2956 * If we don't do this, when we call func_alloc() later, we will lock
2957 * extra rings to the PF that won't be available during func_cfg() of
2960 * This has been fixed with firmware versions above 20.6.54
2962 bp->pf.func_cfg_flags &=
2963 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2964 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2965 bp->pf.func_cfg_flags |=
2966 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2967 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2972 * Now, create and register a buffer to hold forwarded VF requests
2974 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2975 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2976 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2977 if (bp->pf.vf_req_buf == NULL) {
2981 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2982 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2983 for (i = 0; i < num_vfs; i++)
2984 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2985 (i * HWRM_MAX_REQ_LEN);
2987 rc = bnxt_hwrm_func_buf_rgtr(bp);
2991 populate_vf_func_cfg_req(bp, &req, num_vfs);
2993 bp->pf.active_vfs = 0;
2994 for (i = 0; i < num_vfs; i++) {
2995 add_random_mac_if_needed(bp, &req, i);
2997 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2998 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2999 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3000 rc = bnxt_hwrm_send_message(bp,
3005 /* Clear enable flag for next pass */
3006 req.enables &= ~rte_cpu_to_le_32(
3007 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3009 if (rc || resp->error_code) {
3011 "Failed to initizlie VF %d\n", i);
3013 "Not all VFs available. (%d, %d)\n",
3014 rc, resp->error_code);
3021 reserve_resources_from_vf(bp, &req, i);
3022 bp->pf.active_vfs++;
3023 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3027 * Now configure the PF to use "the rest" of the resources
3028 * We're using STD_TX_RING_MODE here though which will limit the TX
3029 * rings. This will allow QoS to function properly. Not setting this
3030 * will cause PF rings to break bandwidth settings.
3032 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3036 rc = update_pf_resource_max(bp);
3043 bnxt_hwrm_func_buf_unrgtr(bp);
3047 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3049 struct hwrm_func_cfg_input req = {0};
3050 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3053 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3055 req.fid = rte_cpu_to_le_16(0xffff);
3056 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3057 req.evb_mode = bp->pf.evb_mode;
3059 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3060 HWRM_CHECK_RESULT();
3066 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3067 uint8_t tunnel_type)
3069 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3070 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3073 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3074 req.tunnel_type = tunnel_type;
3075 req.tunnel_dst_port_val = port;
3076 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3077 HWRM_CHECK_RESULT();
3079 switch (tunnel_type) {
3080 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3081 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3082 bp->vxlan_port = port;
3084 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3085 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3086 bp->geneve_port = port;
3097 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3098 uint8_t tunnel_type)
3100 struct hwrm_tunnel_dst_port_free_input req = {0};
3101 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3104 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3106 req.tunnel_type = tunnel_type;
3107 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3108 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3110 HWRM_CHECK_RESULT();
3116 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3119 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3120 struct hwrm_func_cfg_input req = {0};
3123 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3125 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3126 req.flags = rte_cpu_to_le_32(flags);
3127 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3129 HWRM_CHECK_RESULT();
3135 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3137 uint32_t *flag = flagp;
3139 vnic->flags = *flag;
3142 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3144 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3147 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3150 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3151 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3153 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3155 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3156 req.req_buf_page_size = rte_cpu_to_le_16(
3157 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3158 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3159 req.req_buf_page_addr0 =
3160 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3161 if (req.req_buf_page_addr0 == 0) {
3163 "unable to map buffer address to physical memory\n");
3167 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3169 HWRM_CHECK_RESULT();
3175 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3178 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3179 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3181 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3183 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3185 HWRM_CHECK_RESULT();
3191 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3193 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3194 struct hwrm_func_cfg_input req = {0};
3197 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3199 req.fid = rte_cpu_to_le_16(0xffff);
3200 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3201 req.enables = rte_cpu_to_le_32(
3202 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3203 req.async_event_cr = rte_cpu_to_le_16(
3204 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3205 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3207 HWRM_CHECK_RESULT();
3213 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3215 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3216 struct hwrm_func_vf_cfg_input req = {0};
3219 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3221 req.enables = rte_cpu_to_le_32(
3222 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3223 req.async_event_cr = rte_cpu_to_le_16(
3224 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3225 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3227 HWRM_CHECK_RESULT();
3233 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3235 struct hwrm_func_cfg_input req = {0};
3236 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3237 uint16_t dflt_vlan, fid;
3238 uint32_t func_cfg_flags;
3241 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3244 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3245 fid = bp->pf.vf_info[vf].fid;
3246 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3248 fid = rte_cpu_to_le_16(0xffff);
3249 func_cfg_flags = bp->pf.func_cfg_flags;
3250 dflt_vlan = bp->vlan;
3253 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3254 req.fid = rte_cpu_to_le_16(fid);
3255 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3256 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3258 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3260 HWRM_CHECK_RESULT();
3266 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3267 uint16_t max_bw, uint16_t enables)
3269 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3270 struct hwrm_func_cfg_input req = {0};
3273 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3275 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3276 req.enables |= rte_cpu_to_le_32(enables);
3277 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3278 req.max_bw = rte_cpu_to_le_32(max_bw);
3279 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3281 HWRM_CHECK_RESULT();
3287 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3289 struct hwrm_func_cfg_input req = {0};
3290 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3293 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3295 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3296 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3297 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3298 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3300 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3302 HWRM_CHECK_RESULT();
3308 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3313 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3315 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3320 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3321 void *encaped, size_t ec_size)
3324 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3325 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3327 if (ec_size > sizeof(req.encap_request))
3330 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3332 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3333 memcpy(req.encap_request, encaped, ec_size);
3335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3337 HWRM_CHECK_RESULT();
3343 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3344 struct rte_ether_addr *mac)
3346 struct hwrm_func_qcfg_input req = {0};
3347 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3350 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3352 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3353 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3355 HWRM_CHECK_RESULT();
3357 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3364 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3365 void *encaped, size_t ec_size)
3368 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3369 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3371 if (ec_size > sizeof(req.encap_request))
3374 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3376 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3377 memcpy(req.encap_request, encaped, ec_size);
3379 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3381 HWRM_CHECK_RESULT();
3387 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3388 struct rte_eth_stats *stats, uint8_t rx)
3391 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3392 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3394 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3396 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3398 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3400 HWRM_CHECK_RESULT();
3403 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3404 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3405 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3406 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3407 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3408 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3409 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3410 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3412 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3413 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3414 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3415 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3416 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3417 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3426 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3428 struct hwrm_port_qstats_input req = {0};
3429 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3430 struct bnxt_pf_info *pf = &bp->pf;
3433 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3435 req.port_id = rte_cpu_to_le_16(pf->port_id);
3436 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3437 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3438 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3440 HWRM_CHECK_RESULT();
3446 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3448 struct hwrm_port_clr_stats_input req = {0};
3449 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3450 struct bnxt_pf_info *pf = &bp->pf;
3453 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3454 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3455 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3458 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3460 req.port_id = rte_cpu_to_le_16(pf->port_id);
3461 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3463 HWRM_CHECK_RESULT();
3469 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3471 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3472 struct hwrm_port_led_qcaps_input req = {0};
3478 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3479 req.port_id = bp->pf.port_id;
3480 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3482 HWRM_CHECK_RESULT();
3484 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3487 bp->num_leds = resp->num_leds;
3488 memcpy(bp->leds, &resp->led0_id,
3489 sizeof(bp->leds[0]) * bp->num_leds);
3490 for (i = 0; i < bp->num_leds; i++) {
3491 struct bnxt_led_info *led = &bp->leds[i];
3493 uint16_t caps = led->led_state_caps;
3495 if (!led->led_group_id ||
3496 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3508 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3510 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3511 struct hwrm_port_led_cfg_input req = {0};
3512 struct bnxt_led_cfg *led_cfg;
3513 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3514 uint16_t duration = 0;
3517 if (!bp->num_leds || BNXT_VF(bp))
3520 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3523 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3524 duration = rte_cpu_to_le_16(500);
3526 req.port_id = bp->pf.port_id;
3527 req.num_leds = bp->num_leds;
3528 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3529 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3530 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3531 led_cfg->led_id = bp->leds[i].led_id;
3532 led_cfg->led_state = led_state;
3533 led_cfg->led_blink_on = duration;
3534 led_cfg->led_blink_off = duration;
3535 led_cfg->led_group_id = bp->leds[i].led_group_id;
3538 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3540 HWRM_CHECK_RESULT();
3546 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3550 struct hwrm_nvm_get_dir_info_input req = {0};
3551 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3553 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3555 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3557 HWRM_CHECK_RESULT();
3561 *entries = rte_le_to_cpu_32(resp->entries);
3562 *length = rte_le_to_cpu_32(resp->entry_length);
3567 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3570 uint32_t dir_entries;
3571 uint32_t entry_length;
3574 rte_iova_t dma_handle;
3575 struct hwrm_nvm_get_dir_entries_input req = {0};
3576 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3578 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3582 *data++ = dir_entries;
3583 *data++ = entry_length;
3585 memset(data, 0xff, len);
3587 buflen = dir_entries * entry_length;
3588 buf = rte_malloc("nvm_dir", buflen, 0);
3589 rte_mem_lock_page(buf);
3592 dma_handle = rte_mem_virt2iova(buf);
3593 if (dma_handle == 0) {
3595 "unable to map response address to physical memory\n");
3598 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3599 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3600 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3603 memcpy(data, buf, len > buflen ? buflen : len);
3606 HWRM_CHECK_RESULT();
3612 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3613 uint32_t offset, uint32_t length,
3618 rte_iova_t dma_handle;
3619 struct hwrm_nvm_read_input req = {0};
3620 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3622 buf = rte_malloc("nvm_item", length, 0);
3623 rte_mem_lock_page(buf);
3627 dma_handle = rte_mem_virt2iova(buf);
3628 if (dma_handle == 0) {
3630 "unable to map response address to physical memory\n");
3633 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3634 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3635 req.dir_idx = rte_cpu_to_le_16(index);
3636 req.offset = rte_cpu_to_le_32(offset);
3637 req.len = rte_cpu_to_le_32(length);
3638 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3640 memcpy(data, buf, length);
3643 HWRM_CHECK_RESULT();
3649 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3652 struct hwrm_nvm_erase_dir_entry_input req = {0};
3653 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3655 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3656 req.dir_idx = rte_cpu_to_le_16(index);
3657 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3658 HWRM_CHECK_RESULT();
3665 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3666 uint16_t dir_ordinal, uint16_t dir_ext,
3667 uint16_t dir_attr, const uint8_t *data,
3671 struct hwrm_nvm_write_input req = {0};
3672 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3673 rte_iova_t dma_handle;
3676 buf = rte_malloc("nvm_write", data_len, 0);
3677 rte_mem_lock_page(buf);
3681 dma_handle = rte_mem_virt2iova(buf);
3682 if (dma_handle == 0) {
3684 "unable to map response address to physical memory\n");
3687 memcpy(buf, data, data_len);
3689 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3691 req.dir_type = rte_cpu_to_le_16(dir_type);
3692 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3693 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3694 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3695 req.dir_data_length = rte_cpu_to_le_32(data_len);
3696 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3698 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3701 HWRM_CHECK_RESULT();
3708 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3710 uint32_t *count = cbdata;
3712 *count = *count + 1;
3715 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3716 struct bnxt_vnic_info *vnic __rte_unused)
3721 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3725 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3726 &count, bnxt_vnic_count_hwrm_stub);
3731 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3734 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3735 struct hwrm_func_vf_vnic_ids_query_output *resp =
3736 bp->hwrm_cmd_resp_addr;
3739 /* First query all VNIC ids */
3740 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3742 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3743 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3744 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3746 if (req.vnic_id_tbl_addr == 0) {
3749 "unable to map VNIC ID table address to physical memory\n");
3752 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3755 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3757 } else if (resp->error_code) {
3758 rc = rte_le_to_cpu_16(resp->error_code);
3760 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3763 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3771 * This function queries the VNIC IDs for a specified VF. It then calls
3772 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3773 * Then it calls the hwrm_cb function to program this new vnic configuration.
3775 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3776 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3777 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3779 struct bnxt_vnic_info vnic;
3781 int i, num_vnic_ids;
3786 /* First query all VNIC ids */
3787 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3788 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3789 RTE_CACHE_LINE_SIZE);
3790 if (vnic_ids == NULL) {
3794 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3795 rte_mem_lock_page(((char *)vnic_ids) + sz);
3797 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3799 if (num_vnic_ids < 0)
3800 return num_vnic_ids;
3802 /* Retrieve VNIC, update bd_stall then update */
3804 for (i = 0; i < num_vnic_ids; i++) {
3805 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3806 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3807 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3810 if (vnic.mru <= 4) /* Indicates unallocated */
3813 vnic_cb(&vnic, cbdata);
3815 rc = hwrm_cb(bp, &vnic);
3825 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3828 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3829 struct hwrm_func_cfg_input req = {0};
3832 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3834 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3835 req.enables |= rte_cpu_to_le_32(
3836 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3837 req.vlan_antispoof_mode = on ?
3838 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3839 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3840 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3842 HWRM_CHECK_RESULT();
3848 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3850 struct bnxt_vnic_info vnic;
3853 int num_vnic_ids, i;
3857 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3858 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3859 RTE_CACHE_LINE_SIZE);
3860 if (vnic_ids == NULL) {
3865 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3866 rte_mem_lock_page(((char *)vnic_ids) + sz);
3868 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3874 * Loop through to find the default VNIC ID.
3875 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3876 * by sending the hwrm_func_qcfg command to the firmware.
3878 for (i = 0; i < num_vnic_ids; i++) {
3879 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3880 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3881 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3882 bp->pf.first_vf_id + vf);
3885 if (vnic.func_default) {
3887 return vnic.fw_vnic_id;
3890 /* Could not find a default VNIC. */
3891 PMD_DRV_LOG(ERR, "No default VNIC\n");
3897 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3899 struct bnxt_filter_info *filter)
3902 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3903 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3904 uint32_t enables = 0;
3906 if (filter->fw_em_filter_id != UINT64_MAX)
3907 bnxt_hwrm_clear_em_filter(bp, filter);
3909 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3911 req.flags = rte_cpu_to_le_32(filter->flags);
3913 enables = filter->enables |
3914 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3915 req.dst_id = rte_cpu_to_le_16(dst_id);
3917 if (filter->ip_addr_type) {
3918 req.ip_addr_type = filter->ip_addr_type;
3919 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3922 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3923 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3925 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3926 memcpy(req.src_macaddr, filter->src_macaddr,
3927 RTE_ETHER_ADDR_LEN);
3929 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3930 memcpy(req.dst_macaddr, filter->dst_macaddr,
3931 RTE_ETHER_ADDR_LEN);
3933 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3934 req.ovlan_vid = filter->l2_ovlan;
3936 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3937 req.ivlan_vid = filter->l2_ivlan;
3939 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3940 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3942 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3943 req.ip_protocol = filter->ip_protocol;
3945 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3946 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3948 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3949 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3951 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3952 req.src_port = rte_cpu_to_be_16(filter->src_port);
3954 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3955 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3957 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3958 req.mirror_vnic_id = filter->mirror_vnic_id;
3960 req.enables = rte_cpu_to_le_32(enables);
3962 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3964 HWRM_CHECK_RESULT();
3966 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3972 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3975 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3976 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3978 if (filter->fw_em_filter_id == UINT64_MAX)
3981 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3982 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3984 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3986 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3988 HWRM_CHECK_RESULT();
3991 filter->fw_em_filter_id = UINT64_MAX;
3992 filter->fw_l2_filter_id = UINT64_MAX;
3997 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3999 struct bnxt_filter_info *filter)
4002 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4003 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4004 bp->hwrm_cmd_resp_addr;
4005 uint32_t enables = 0;
4007 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4008 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4010 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4012 req.flags = rte_cpu_to_le_32(filter->flags);
4014 enables = filter->enables |
4015 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4016 req.dst_id = rte_cpu_to_le_16(dst_id);
4019 if (filter->ip_addr_type) {
4020 req.ip_addr_type = filter->ip_addr_type;
4022 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4025 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4026 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4028 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4029 memcpy(req.src_macaddr, filter->src_macaddr,
4030 RTE_ETHER_ADDR_LEN);
4032 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4033 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4034 //RTE_ETHER_ADDR_LEN);
4036 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4037 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4039 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4040 req.ip_protocol = filter->ip_protocol;
4042 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4043 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4045 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4046 req.src_ipaddr_mask[0] =
4047 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4049 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4050 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4052 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4053 req.dst_ipaddr_mask[0] =
4054 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4056 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4057 req.src_port = rte_cpu_to_le_16(filter->src_port);
4059 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4060 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4062 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4063 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4065 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4066 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4068 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4069 req.mirror_vnic_id = filter->mirror_vnic_id;
4071 req.enables = rte_cpu_to_le_32(enables);
4073 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4075 HWRM_CHECK_RESULT();
4077 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4083 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4084 struct bnxt_filter_info *filter)
4087 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4088 struct hwrm_cfa_ntuple_filter_free_output *resp =
4089 bp->hwrm_cmd_resp_addr;
4091 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4094 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4096 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4098 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4100 HWRM_CHECK_RESULT();
4103 filter->fw_ntuple_filter_id = UINT64_MAX;
4109 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4111 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4112 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4113 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4114 int nr_ctxs = bp->max_ring_grps;
4115 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4116 uint16_t *ring_tbl = vnic->rss_table;
4117 int max_rings = bp->rx_nr_rings;
4121 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4123 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4124 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4125 req.hash_mode_flags = vnic->hash_mode;
4127 req.ring_grp_tbl_addr =
4128 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4129 req.hash_key_tbl_addr =
4130 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4132 for (i = 0, k = 0; i < nr_ctxs; i++) {
4133 struct bnxt_rx_ring_info *rxr;
4134 struct bnxt_cp_ring_info *cpr;
4136 req.ring_table_pair_index = i;
4137 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4139 for (j = 0; j < 64; j++) {
4142 /* Find next active ring. */
4143 for (cnt = 0; cnt < max_rings; cnt++) {
4144 if (rx_queue_state[k] !=
4145 RTE_ETH_QUEUE_STATE_STOPPED)
4147 if (++k == max_rings)
4151 /* Return if no rings are active. */
4152 if (cnt == max_rings)
4155 /* Add rx/cp ring pair to RSS table. */
4156 rxr = rxqs[k]->rx_ring;
4157 cpr = rxqs[k]->cp_ring;
4159 ring_id = rxr->rx_ring_struct->fw_ring_id;
4160 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4161 ring_id = cpr->cp_ring_struct->fw_ring_id;
4162 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4164 if (++k == max_rings)
4167 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4170 HWRM_CHECK_RESULT();
4180 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4182 unsigned int rss_idx, fw_idx, i;
4184 if (!(vnic->rss_table && vnic->hash_type))
4187 if (BNXT_CHIP_THOR(bp))
4188 return bnxt_vnic_rss_configure_thor(bp, vnic);
4191 * Fill the RSS hash & redirection table with
4192 * ring group ids for all VNICs
4194 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4195 rss_idx++, fw_idx++) {
4196 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4197 fw_idx %= bp->rx_cp_nr_rings;
4198 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4202 if (i == bp->rx_cp_nr_rings)
4204 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4206 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4209 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4210 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4214 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4216 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4217 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4219 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4220 req->num_cmpl_dma_aggr_during_int =
4221 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4223 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4225 /* min timer set to 1/2 of interrupt timer */
4226 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4228 /* buf timer set to 1/4 of interrupt timer */
4229 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4231 req->cmpl_aggr_dma_tmr_during_int =
4232 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4234 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4235 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4236 req->flags = rte_cpu_to_le_16(flags);
4239 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4240 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4242 struct hwrm_ring_aggint_qcaps_input req = {0};
4243 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4248 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4249 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4253 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4254 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4256 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4257 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4258 agg_req->flags = rte_cpu_to_le_16(flags);
4260 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4261 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4262 agg_req->enables = rte_cpu_to_le_32(enables);
4265 HWRM_CHECK_RESULT();
4270 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4271 struct bnxt_coal *coal, uint16_t ring_id)
4273 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4274 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4275 bp->hwrm_cmd_resp_addr;
4278 /* Set ring coalesce parameters only for 100G NICs */
4279 if (BNXT_CHIP_THOR(bp)) {
4280 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4282 } else if (bnxt_stratus_device(bp)) {
4283 bnxt_hwrm_set_coal_params(coal, &req);
4288 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4289 req.ring_id = rte_cpu_to_le_16(ring_id);
4290 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4291 HWRM_CHECK_RESULT();
4296 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4297 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4299 struct hwrm_func_backing_store_qcaps_input req = {0};
4300 struct hwrm_func_backing_store_qcaps_output *resp =
4301 bp->hwrm_cmd_resp_addr;
4304 if (!BNXT_CHIP_THOR(bp) ||
4305 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4310 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4311 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4312 HWRM_CHECK_RESULT_SILENT();
4315 struct bnxt_ctx_pg_info *ctx_pg;
4316 struct bnxt_ctx_mem_info *ctx;
4317 int total_alloc_len;
4320 total_alloc_len = sizeof(*ctx);
4321 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4322 RTE_CACHE_LINE_SIZE);
4327 memset(ctx, 0, total_alloc_len);
4329 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4330 sizeof(*ctx_pg) * BNXT_MAX_Q,
4331 RTE_CACHE_LINE_SIZE);
4336 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4337 ctx->tqm_mem[i] = ctx_pg;
4340 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4341 ctx->qp_min_qp1_entries =
4342 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4343 ctx->qp_max_l2_entries =
4344 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4345 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4346 ctx->srq_max_l2_entries =
4347 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4348 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4349 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4350 ctx->cq_max_l2_entries =
4351 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4352 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4353 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4354 ctx->vnic_max_vnic_entries =
4355 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4356 ctx->vnic_max_ring_table_entries =
4357 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4358 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4359 ctx->stat_max_entries =
4360 rte_le_to_cpu_32(resp->stat_max_entries);
4361 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4362 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4363 ctx->tqm_min_entries_per_ring =
4364 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4365 ctx->tqm_max_entries_per_ring =
4366 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4367 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4368 if (!ctx->tqm_entries_multiple)
4369 ctx->tqm_entries_multiple = 1;
4370 ctx->mrav_max_entries =
4371 rte_le_to_cpu_32(resp->mrav_max_entries);
4372 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4373 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4374 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4383 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4385 struct hwrm_func_backing_store_cfg_input req = {0};
4386 struct hwrm_func_backing_store_cfg_output *resp =
4387 bp->hwrm_cmd_resp_addr;
4388 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4389 struct bnxt_ctx_pg_info *ctx_pg;
4390 uint32_t *num_entries;
4399 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4400 req.enables = rte_cpu_to_le_32(enables);
4402 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4403 ctx_pg = &ctx->qp_mem;
4404 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4405 req.qp_num_qp1_entries =
4406 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4407 req.qp_num_l2_entries =
4408 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4409 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4410 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4411 &req.qpc_pg_size_qpc_lvl,
4415 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4416 ctx_pg = &ctx->srq_mem;
4417 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4418 req.srq_num_l2_entries =
4419 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4420 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4421 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4422 &req.srq_pg_size_srq_lvl,
4426 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4427 ctx_pg = &ctx->cq_mem;
4428 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4429 req.cq_num_l2_entries =
4430 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4431 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4432 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4433 &req.cq_pg_size_cq_lvl,
4437 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4438 ctx_pg = &ctx->vnic_mem;
4439 req.vnic_num_vnic_entries =
4440 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4441 req.vnic_num_ring_table_entries =
4442 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4443 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4444 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4445 &req.vnic_pg_size_vnic_lvl,
4446 &req.vnic_page_dir);
4449 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4450 ctx_pg = &ctx->stat_mem;
4451 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4452 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4453 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4454 &req.stat_pg_size_stat_lvl,
4455 &req.stat_page_dir);
4458 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4459 num_entries = &req.tqm_sp_num_entries;
4460 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4461 pg_dir = &req.tqm_sp_page_dir;
4462 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4463 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4464 if (!(enables & ena))
4467 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4469 ctx_pg = ctx->tqm_mem[i];
4470 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4471 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4474 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4475 HWRM_CHECK_RESULT();
4482 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4484 struct hwrm_port_qstats_ext_input req = {0};
4485 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4486 struct bnxt_pf_info *pf = &bp->pf;
4489 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4490 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4493 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4495 req.port_id = rte_cpu_to_le_16(pf->port_id);
4496 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4497 req.tx_stat_host_addr =
4498 rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4500 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4502 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4503 req.rx_stat_host_addr =
4504 rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4506 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4508 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4511 bp->fw_rx_port_stats_ext_size = 0;
4512 bp->fw_tx_port_stats_ext_size = 0;
4514 bp->fw_rx_port_stats_ext_size =
4515 rte_le_to_cpu_16(resp->rx_stat_size);
4516 bp->fw_tx_port_stats_ext_size =
4517 rte_le_to_cpu_16(resp->tx_stat_size);
4520 HWRM_CHECK_RESULT();
4527 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4529 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4530 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4531 bp->hwrm_cmd_resp_addr;
4534 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_KONG(bp));
4535 req.tunnel_type = type;
4536 req.dest_fid = bp->fw_fid;
4537 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4538 HWRM_CHECK_RESULT();
4546 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4548 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4549 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4550 bp->hwrm_cmd_resp_addr;
4553 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_KONG(bp));
4554 req.tunnel_type = type;
4555 req.dest_fid = bp->fw_fid;
4556 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4557 HWRM_CHECK_RESULT();
4564 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4566 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4567 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4568 bp->hwrm_cmd_resp_addr;
4571 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_KONG(bp));
4572 req.src_fid = bp->fw_fid;
4573 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4574 HWRM_CHECK_RESULT();
4577 *type = resp->tunnel_mask;
4584 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4587 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4588 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4589 bp->hwrm_cmd_resp_addr;
4592 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_KONG(bp));
4593 req.src_fid = bp->fw_fid;
4594 req.tunnel_type = tun_type;
4595 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4596 HWRM_CHECK_RESULT();
4599 *dst_fid = resp->dest_fid;
4601 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);