drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 /*
  79  * HWRM Functions (sent to HWRM)
  80  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  81  * HWRM command times out, or a negative error code if the HWRM
  82  * command was failed by the FW.
  83  */
  84
  85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  86                                   uint32_t msg_len, bool use_kong_mb)
  87 {
  88         unsigned int i;
  89         struct input *req = msg;
  90         struct output *resp = bp->hwrm_cmd_resp_addr;
  91         uint32_t *data = msg;
  92         uint8_t *bar;
  93         uint8_t *valid;
  94         uint16_t max_req_len = bp->max_req_len;
  95         struct hwrm_short_input short_input = { 0 };
  96         uint16_t bar_offset = use_kong_mb ?
  97                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  98         uint16_t mb_trigger_offset = use_kong_mb ?
  99                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 100         uint32_t timeout;
 101
 102         /* Do not send HWRM commands to firmware in error state */
 103         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 104                 return 0;
 105
 106         timeout = bp->hwrm_cmd_timeout;
 107
 108         /* Update the message length for backing store config for new FW. */
 109         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 110             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 111                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 131         }
 132
 133         /* Write request msg to hwrm channel */
 134         for (i = 0; i < msg_len; i += 4) {
 135                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 136                 rte_write32(*data, bar);
 137                 data++;
 138         }
 139
 140         /* Zero the rest of the request space */
 141         for (; i < max_req_len; i += 4) {
 142                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 143                 rte_write32(0, bar);
 144         }
 145
 146         /* Ring channel doorbell */
 147         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 148         rte_write32(1, bar);
 149         /*
 150          * Make sure the channel doorbell ring command complete before
 151          * reading the response to avoid getting stale or invalid
 152          * responses.
 153          */
 154         rte_io_mb();
 155
 156         /* Poll for the valid bit */
 157         for (i = 0; i < timeout; i++) {
 158                 /* Sanity check on the resp->resp_len */
 159                 rte_io_rmb();
 160                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 161                         /* Last byte of resp contains the valid key */
 162                         valid = (uint8_t *)resp + resp->resp_len - 1;
 163                         if (*valid == HWRM_RESP_VALID_KEY)
 164                                 break;
 165                 }
 166                 rte_delay_us(1);
 167         }
 168
 169         if (i >= timeout) {
 170                 /* Suppress VER_GET timeout messages during reset recovery */
 171                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 172                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 173                         return -ETIMEDOUT;
 174
 175                 PMD_DRV_LOG(ERR,
 176                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 177                             req->req_type, req->seq_id);
 178                 return -ETIMEDOUT;
 179         }
 180         return 0;
 181 }
 182
 183 /*
 184  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 185  * spinlock, and does initial processing.
 186  *
 187  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 188  * releases the spinlock only if it returns. If the regular int return codes
 189  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 190  * directly, rather it should be copied and modified to suit the function.
 191  *
 192  * HWRM_UNLOCK() must be called after all response processing is completed.
 193  */
 194 #define HWRM_PREP(req, type, kong) do { \
 195         rte_spinlock_lock(&bp->hwrm_lock); \
 196         if (bp->hwrm_cmd_resp_addr == NULL) { \
 197                 rte_spinlock_unlock(&bp->hwrm_lock); \
 198                 return -EACCES; \
 199         } \
 200         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 201         (req)->req_type = rte_cpu_to_le_16(type); \
 202         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 203         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 204                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 205         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 206         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 207 } while (0)
 208
 209 #define HWRM_CHECK_RESULT_SILENT() do {\
 210         if (rc) { \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 return rc; \
 213         } \
 214         if (resp->error_code) { \
 215                 rc = rte_le_to_cpu_16(resp->error_code); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 return rc; \
 218         } \
 219 } while (0)
 220
 221 #define HWRM_CHECK_RESULT() do {\
 222         if (rc) { \
 223                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 224                 rte_spinlock_unlock(&bp->hwrm_lock); \
 225                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 226                         rc = -EACCES; \
 227                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 228                         rc = -ENOSPC; \
 229                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 230                         rc = -EINVAL; \
 231                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 232                         rc = -ENOTSUP; \
 233                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 234                         rc = -EAGAIN; \
 235                 else if (rc > 0) \
 236                         rc = -EIO; \
 237                 return rc; \
 238         } \
 239         if (resp->error_code) { \
 240                 rc = rte_le_to_cpu_16(resp->error_code); \
 241                 if (resp->resp_len >= 16) { \
 242                         struct hwrm_err_output *tmp_hwrm_err_op = \
 243                                                 (void *)resp; \
 244                         PMD_DRV_LOG(ERR, \
 245                                 "error %d:%d:%08x:%04x\n", \
 246                                 rc, tmp_hwrm_err_op->cmd_err, \
 247                                 rte_le_to_cpu_32(\
 248                                         tmp_hwrm_err_op->opaque_0), \
 249                                 rte_le_to_cpu_16(\
 250                                         tmp_hwrm_err_op->opaque_1)); \
 251                 } else { \
 252                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 253                 } \
 254                 rte_spinlock_unlock(&bp->hwrm_lock); \
 255                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 256                         rc = -EACCES; \
 257                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 258                         rc = -ENOSPC; \
 259                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 260                         rc = -EINVAL; \
 261                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 262                         rc = -ENOTSUP; \
 263                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 264                         rc = -EAGAIN; \
 265                 else if (rc > 0) \
 266                         rc = -EIO; \
 267                 return rc; \
 268         } \
 269 } while (0)
 270
 271 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 272
 273 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 274                                 bool use_kong_mb,
 275                                 uint16_t msg_type,
 276                                 void *msg,
 277                                 uint32_t msg_len,
 278                                 void *resp_msg,
 279                                 uint32_t resp_len)
 280 {
 281         int rc = 0;
 282         bool mailbox = BNXT_USE_CHIMP_MB;
 283         struct input *req = msg;
 284         struct output *resp = bp->hwrm_cmd_resp_addr;
 285
 286         if (use_kong_mb)
 287                 mailbox = BNXT_USE_KONG(bp);
 288
 289         HWRM_PREP(req, msg_type, mailbox);
 290
 291         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 292
 293         HWRM_CHECK_RESULT();
 294
 295         if (resp_msg)
 296                 memcpy(resp_msg, resp, resp_len);
 297
 298         HWRM_UNLOCK();
 299
 300         return rc;
 301 }
 302
 303 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 304                                   bool use_kong_mb,
 305                                   uint16_t tf_type,
 306                                   uint16_t tf_subtype,
 307                                   uint32_t *tf_response_code,
 308                                   void *msg,
 309                                   uint32_t msg_len,
 310                                   void *response,
 311                                   uint32_t response_len)
 312 {
 313         int rc = 0;
 314         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 315         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 316         bool mailbox = BNXT_USE_CHIMP_MB;
 317
 318         if (msg_len > sizeof(req.tf_req))
 319                 return -ENOMEM;
 320
 321         if (use_kong_mb)
 322                 mailbox = BNXT_USE_KONG(bp);
 323
 324         HWRM_PREP(&req, HWRM_TF, mailbox);
 325         /* Build request using the user supplied request payload.
 326          * TLV request size is checked at build time against HWRM
 327          * request max size, thus no checking required.
 328          */
 329         req.tf_type = tf_type;
 330         req.tf_subtype = tf_subtype;
 331         memcpy(req.tf_req, msg, msg_len);
 332
 333         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 334         HWRM_CHECK_RESULT();
 335
 336         /* Copy the resp to user provided response buffer */
 337         if (response != NULL)
 338                 /* Post process response data. We need to copy only
 339                  * the 'payload' as the HWRM data structure really is
 340                  * HWRM header + msg header + payload and the TFLIB
 341                  * only provided a payload place holder.
 342                  */
 343                 if (response_len != 0) {
 344                         memcpy(response,
 345                                resp->tf_resp,
 346                                response_len);
 347                 }
 348
 349         /* Extract the internal tflib response code */
 350         *tf_response_code = resp->tf_resp_code;
 351         HWRM_UNLOCK();
 352
 353         return rc;
 354 }
 355
 356 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 357 {
 358         int rc = 0;
 359         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 360         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 361
 362         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 363         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 364         req.mask = 0;
 365
 366         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 367
 368         HWRM_CHECK_RESULT();
 369         HWRM_UNLOCK();
 370
 371         return rc;
 372 }
 373
 374 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 375                                  struct bnxt_vnic_info *vnic,
 376                                  uint16_t vlan_count,
 377                                  struct bnxt_vlan_table_entry *vlan_table)
 378 {
 379         int rc = 0;
 380         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 381         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 382         uint32_t mask = 0;
 383
 384         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 385                 return rc;
 386
 387         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 388         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 389
 390         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 391                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 392         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 393                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 394
 395         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 396                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 397
 398         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 399                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 400         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 401                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 402                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 403                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 404         }
 405         if (vlan_table) {
 406                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 407                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 408                 req.vlan_tag_tbl_addr =
 409                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 410                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 411         }
 412         req.mask = rte_cpu_to_le_32(mask);
 413
 414         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 415
 416         HWRM_CHECK_RESULT();
 417         HWRM_UNLOCK();
 418
 419         return rc;
 420 }
 421
 422 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 423                         uint16_t vlan_count,
 424                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 425 {
 426         int rc = 0;
 427         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 428         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 429                                                 bp->hwrm_cmd_resp_addr;
 430
 431         /*
 432          * Older HWRM versions did not support this command, and the set_rx_mask
 433          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 434          * removed from set_rx_mask call, and this command was added.
 435          *
 436          * This command is also present from 1.7.8.11 and higher,
 437          * as well as 1.7.8.0
 438          */
 439         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 440                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 441                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 442                                         (11)))
 443                                 return 0;
 444                 }
 445         }
 446         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 447         req.fid = rte_cpu_to_le_16(fid);
 448
 449         req.vlan_tag_mask_tbl_addr =
 450                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 451         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 452
 453         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 454
 455         HWRM_CHECK_RESULT();
 456         HWRM_UNLOCK();
 457
 458         return rc;
 459 }
 460
 461 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 462                              struct bnxt_filter_info *filter)
 463 {
 464         int rc = 0;
 465         struct bnxt_filter_info *l2_filter = filter;
 466         struct bnxt_vnic_info *vnic = NULL;
 467         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 468         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 469
 470         if (filter->fw_l2_filter_id == UINT64_MAX)
 471                 return 0;
 472
 473         if (filter->matching_l2_fltr_ptr)
 474                 l2_filter = filter->matching_l2_fltr_ptr;
 475
 476         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 477                     filter, l2_filter, l2_filter->l2_ref_cnt);
 478
 479         if (l2_filter->l2_ref_cnt == 0)
 480                 return 0;
 481
 482         if (l2_filter->l2_ref_cnt > 0)
 483                 l2_filter->l2_ref_cnt--;
 484
 485         if (l2_filter->l2_ref_cnt > 0)
 486                 return 0;
 487
 488         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 489
 490         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 491
 492         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 493
 494         HWRM_CHECK_RESULT();
 495         HWRM_UNLOCK();
 496
 497         filter->fw_l2_filter_id = UINT64_MAX;
 498         if (l2_filter->l2_ref_cnt == 0) {
 499                 vnic = l2_filter->vnic;
 500                 if (vnic) {
 501                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 502                                       bnxt_filter_info, next);
 503                         bnxt_free_filter(bp, l2_filter);
 504                 }
 505         }
 506
 507         return 0;
 508 }
 509
 510 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 511                          uint16_t dst_id,
 512                          struct bnxt_filter_info *filter)
 513 {
 514         int rc = 0;
 515         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 516         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 517         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 518         const struct rte_eth_vmdq_rx_conf *conf =
 519                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 520         uint32_t enables = 0;
 521         uint16_t j = dst_id - 1;
 522
 523         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 524         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 525             conf->pool_map[j].pools & (1UL << j)) {
 526                 PMD_DRV_LOG(DEBUG,
 527                         "Add vlan %u to vmdq pool %u\n",
 528                         conf->pool_map[j].vlan_id, j);
 529
 530                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 531                 filter->enables |=
 532                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 533                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 534         }
 535
 536         if (filter->fw_l2_filter_id != UINT64_MAX)
 537                 bnxt_hwrm_clear_l2_filter(bp, filter);
 538
 539         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 540
 541         /* PMD does not support XDP and RoCE */
 542         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 543                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 544         req.flags = rte_cpu_to_le_32(filter->flags);
 545
 546         enables = filter->enables |
 547               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 548         req.dst_id = rte_cpu_to_le_16(dst_id);
 549
 550         if (enables &
 551             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 552                 memcpy(req.l2_addr, filter->l2_addr,
 553                        RTE_ETHER_ADDR_LEN);
 554         if (enables &
 555             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 556                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 557                        RTE_ETHER_ADDR_LEN);
 558         if (enables &
 559             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 560                 req.l2_ovlan = filter->l2_ovlan;
 561         if (enables &
 562             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 563                 req.l2_ivlan = filter->l2_ivlan;
 564         if (enables &
 565             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 566                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 567         if (enables &
 568             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 569                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 570         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 571                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 572         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 573                 req.src_type = filter->src_type;
 574         if (filter->pri_hint) {
 575                 req.pri_hint = filter->pri_hint;
 576                 req.l2_filter_id_hint =
 577                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 578         }
 579
 580         req.enables = rte_cpu_to_le_32(enables);
 581
 582         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 583
 584         HWRM_CHECK_RESULT();
 585
 586         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 587         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 588         HWRM_UNLOCK();
 589
 590         filter->l2_ref_cnt++;
 591
 592         return rc;
 593 }
 594
 595 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 596 {
 597         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 598         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 599         uint32_t flags = 0;
 600         int rc;
 601
 602         if (!ptp)
 603                 return 0;
 604
 605         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 606
 607         if (ptp->rx_filter)
 608                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 609         else
 610                 flags |=
 611                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 612         if (ptp->tx_tstamp_en)
 613                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 614         else
 615                 flags |=
 616                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 617         req.flags = rte_cpu_to_le_32(flags);
 618         req.enables = rte_cpu_to_le_32
 619                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 620         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 621
 622         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 623         HWRM_UNLOCK();
 624
 625         return rc;
 626 }
 627
 628 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 629 {
 630         int rc = 0;
 631         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 632         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 633         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 634
 635         if (ptp)
 636                 return 0;
 637
 638         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 639
 640         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 641
 642         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 643
 644         HWRM_CHECK_RESULT();
 645
 646         if (!BNXT_CHIP_P5(bp) &&
 647             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 648                 return 0;
 649
 650         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 651                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 652
 653         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 654         if (!ptp)
 655                 return -ENOMEM;
 656
 657         if (!BNXT_CHIP_P5(bp)) {
 658                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 659                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 660                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 661                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 662                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 663                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 664                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 665                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 666                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 667                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 668                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 669                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 670                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 671                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 672                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 673                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 674                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 675                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 676         }
 677
 678         ptp->bp = bp;
 679         bp->ptp_cfg = ptp;
 680
 681         return 0;
 682 }
 683
 684 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
 685 {
 686         int i;
 687
 688         for (i = 0; i < bp->pf->max_vfs; i++) {
 689                 rte_free(bp->pf->vf_info[i].vlan_table);
 690                 bp->pf->vf_info[i].vlan_table = NULL;
 691                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 692                 bp->pf->vf_info[i].vlan_as_table = NULL;
 693         }
 694         rte_free(bp->pf->vf_info);
 695         bp->pf->vf_info = NULL;
 696 }
 697
 698 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 699 {
 700         int rc = 0;
 701         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 702         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 703         uint16_t new_max_vfs;
 704         uint32_t flags;
 705         int i;
 706
 707         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 708
 709         req.fid = rte_cpu_to_le_16(0xffff);
 710
 711         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 712
 713         HWRM_CHECK_RESULT();
 714
 715         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 716         flags = rte_le_to_cpu_32(resp->flags);
 717         if (BNXT_PF(bp)) {
 718                 bp->pf->port_id = resp->port_id;
 719                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 720                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 721                 new_max_vfs = bp->pdev->max_vfs;
 722                 if (new_max_vfs != bp->pf->max_vfs) {
 723                         if (bp->pf->vf_info)
 724                                 bnxt_hwrm_free_vf_info(bp);
 725                         bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
 726                             sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
 727                         if (bp->pf->vf_info == NULL) {
 728                                 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
 729                                 HWRM_UNLOCK();
 730                                 return -ENOMEM;
 731                         }
 732                         bp->pf->max_vfs = new_max_vfs;
 733                         for (i = 0; i < new_max_vfs; i++) {
 734                                 bp->pf->vf_info[i].fid =
 735                                         bp->pf->first_vf_id + i;
 736                                 bp->pf->vf_info[i].vlan_table =
 737                                         rte_zmalloc("VF VLAN table",
 738                                                     getpagesize(),
 739                                                     getpagesize());
 740                                 if (bp->pf->vf_info[i].vlan_table == NULL)
 741                                         PMD_DRV_LOG(ERR,
 742                                         "Fail to alloc VLAN table for VF %d\n",
 743                                         i);
 744                                 else
 745                                         rte_mem_lock_page(
 746                                                 bp->pf->vf_info[i].vlan_table);
 747                                 bp->pf->vf_info[i].vlan_as_table =
 748                                         rte_zmalloc("VF VLAN AS table",
 749                                                     getpagesize(),
 750                                                     getpagesize());
 751                                 if (bp->pf->vf_info[i].vlan_as_table == NULL)
 752                                         PMD_DRV_LOG(ERR,
 753                                         "Alloc VLAN AS table for VF %d fail\n",
 754                                         i);
 755                                 else
 756                                         rte_mem_lock_page(
 757                                               bp->pf->vf_info[i].vlan_as_table);
 758                                 STAILQ_INIT(&bp->pf->vf_info[i].filter);
 759                         }
 760                 }
 761         }
 762
 763         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 764         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 765                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 766                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 767         } else {
 768                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 769         }
 770         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 771         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 772         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 773         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 774         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 775         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 776         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 777         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 778                 bp->max_l2_ctx += bp->max_rx_em_flows;
 779         /* TODO: For now, do not support VMDq/RFS on VFs. */
 780         if (BNXT_PF(bp)) {
 781                 if (bp->pf->max_vfs)
 782                         bp->max_vnics = 1;
 783                 else
 784                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 785         } else {
 786                 bp->max_vnics = 1;
 787         }
 788         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 789                     bp->max_l2_ctx, bp->max_vnics);
 790         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 791         if (BNXT_PF(bp)) {
 792                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 793                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 794                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 795                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 796                         HWRM_UNLOCK();
 797                         bnxt_hwrm_ptp_qcfg(bp);
 798                 }
 799         }
 800
 801         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 802                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 803
 804         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 805                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 806                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 807         }
 808
 809         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 810                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 811
 812         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 813                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 814
 815         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 816                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 817
 818         HWRM_UNLOCK();
 819
 820         return rc;
 821 }
 822
 823 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 824 {
 825         int rc;
 826
 827         rc = __bnxt_hwrm_func_qcaps(bp);
 828         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 829                 rc = bnxt_alloc_ctx_mem(bp);
 830                 if (rc)
 831                         return rc;
 832
 833                 /* On older FW,
 834                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 835                  * But the error can be ignored. Return success.
 836                  */
 837                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 838                 if (!rc)
 839                         bp->flags |= BNXT_FLAG_NEW_RM;
 840         }
 841
 842         return 0;
 843 }
 844
 845 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 846 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 847 {
 848         int rc = 0;
 849         uint32_t flags;
 850         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 851         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 852
 853         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 854
 855         req.target_id = rte_cpu_to_le_16(0xffff);
 856
 857         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 858
 859         HWRM_CHECK_RESULT();
 860
 861         flags = rte_le_to_cpu_32(resp->flags);
 862
 863         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 864                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 865                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 866         }
 867
 868         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 869                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
 870
 871         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
 872                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
 873
 874         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 875
 876         HWRM_UNLOCK();
 877
 878         return rc;
 879 }
 880
 881 int bnxt_hwrm_func_reset(struct bnxt *bp)
 882 {
 883         int rc = 0;
 884         struct hwrm_func_reset_input req = {.req_type = 0 };
 885         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 886
 887         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 888
 889         req.enables = rte_cpu_to_le_32(0);
 890
 891         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 892
 893         HWRM_CHECK_RESULT();
 894         HWRM_UNLOCK();
 895
 896         return rc;
 897 }
 898
 899 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 900 {
 901         int rc;
 902         uint32_t flags = 0;
 903         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 904         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 905
 906         if (bp->flags & BNXT_FLAG_REGISTERED)
 907                 return 0;
 908
 909         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 910                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 911         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 912                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 913
 914         /* PFs and trusted VFs should indicate the support of the
 915          * Master capability on non Stingray platform
 916          */
 917         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 918                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 919
 920         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 921         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 922                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 923         req.ver_maj = RTE_VER_YEAR;
 924         req.ver_min = RTE_VER_MONTH;
 925         req.ver_upd = RTE_VER_MINOR;
 926
 927         if (BNXT_PF(bp)) {
 928                 req.enables |= rte_cpu_to_le_32(
 929                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 930                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
 931                        RTE_MIN(sizeof(req.vf_req_fwd),
 932                                sizeof(bp->pf->vf_req_fwd)));
 933         }
 934
 935         req.flags = rte_cpu_to_le_32(flags);
 936
 937         req.async_event_fwd[0] |=
 938                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 939                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 940                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 941                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 942                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 943         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 944                 req.async_event_fwd[0] |=
 945                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 946         req.async_event_fwd[1] |=
 947                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 948                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 949         if (BNXT_PF(bp))
 950                 req.async_event_fwd[1] |=
 951                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 952
 953         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
 954                 req.async_event_fwd[1] |=
 955                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
 956
 957         req.async_event_fwd[2] |=
 958                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
 959
 960         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 961
 962         HWRM_CHECK_RESULT();
 963
 964         flags = rte_le_to_cpu_32(resp->flags);
 965         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 966                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 967
 968         HWRM_UNLOCK();
 969
 970         bp->flags |= BNXT_FLAG_REGISTERED;
 971
 972         return rc;
 973 }
 974
 975 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 976 {
 977         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 978                 return 0;
 979
 980         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 981 }
 982
 983 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 984 {
 985         int rc;
 986         uint32_t flags = 0;
 987         uint32_t enables;
 988         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 989         struct hwrm_func_vf_cfg_input req = {0};
 990
 991         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 992
 993         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 994                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 995                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 996                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 997                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 998
 999         if (BNXT_HAS_RING_GRPS(bp)) {
1000                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1001                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1002         }
1003
1004         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1005         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1006                                             AGG_RING_MULTIPLIER);
1007         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1008         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1009                                               bp->tx_nr_rings +
1010                                               BNXT_NUM_ASYNC_CPR(bp));
1011         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1012         if (bp->vf_resv_strategy ==
1013             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1014                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1015                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1016                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1017                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1018                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1019                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1020         } else if (bp->vf_resv_strategy ==
1021                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1022                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1023                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1024         }
1025
1026         if (test)
1027                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1028                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1029                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1030                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1031                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1032                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1033
1034         if (test && BNXT_HAS_RING_GRPS(bp))
1035                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1036
1037         req.flags = rte_cpu_to_le_32(flags);
1038         req.enables |= rte_cpu_to_le_32(enables);
1039
1040         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1041
1042         if (test)
1043                 HWRM_CHECK_RESULT_SILENT();
1044         else
1045                 HWRM_CHECK_RESULT();
1046
1047         HWRM_UNLOCK();
1048         return rc;
1049 }
1050
1051 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1052 {
1053         int rc;
1054         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1055         struct hwrm_func_resource_qcaps_input req = {0};
1056
1057         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1058         req.fid = rte_cpu_to_le_16(0xffff);
1059
1060         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1061
1062         HWRM_CHECK_RESULT_SILENT();
1063
1064         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1065         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1066         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1067         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1068         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1069         /* func_resource_qcaps does not return max_rx_em_flows.
1070          * So use the value provided by func_qcaps.
1071          */
1072         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1073         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1074                 bp->max_l2_ctx += bp->max_rx_em_flows;
1075         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1076         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1077         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1078         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1079         if (bp->vf_resv_strategy >
1080             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1081                 bp->vf_resv_strategy =
1082                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1083
1084         HWRM_UNLOCK();
1085         return rc;
1086 }
1087
1088 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1089 {
1090         int rc = 0;
1091         struct hwrm_ver_get_input req = {.req_type = 0 };
1092         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1093         uint32_t fw_version;
1094         uint16_t max_resp_len;
1095         char type[RTE_MEMZONE_NAMESIZE];
1096         uint32_t dev_caps_cfg;
1097
1098         bp->max_req_len = HWRM_MAX_REQ_LEN;
1099         bp->hwrm_cmd_timeout = timeout;
1100         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1101
1102         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1103         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1104         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1105
1106         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1107
1108         if (bp->flags & BNXT_FLAG_FW_RESET)
1109                 HWRM_CHECK_RESULT_SILENT();
1110         else
1111                 HWRM_CHECK_RESULT();
1112
1113         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1114                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1115                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1116                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1117                 resp->hwrm_fw_rsvd_8b);
1118         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1119                      (resp->hwrm_fw_min_8b << 16) |
1120                      (resp->hwrm_fw_bld_8b << 8) |
1121                      resp->hwrm_fw_rsvd_8b;
1122         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1123                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1124
1125         fw_version = resp->hwrm_intf_maj_8b << 16;
1126         fw_version |= resp->hwrm_intf_min_8b << 8;
1127         fw_version |= resp->hwrm_intf_upd_8b;
1128         bp->hwrm_spec_code = fw_version;
1129
1130         /* def_req_timeout value is in milliseconds */
1131         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1132         /* convert timeout to usec */
1133         bp->hwrm_cmd_timeout *= 1000;
1134         if (!bp->hwrm_cmd_timeout)
1135                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1136
1137         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1138                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1139                 rc = -EINVAL;
1140                 goto error;
1141         }
1142
1143         if (bp->max_req_len > resp->max_req_win_len) {
1144                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1145                 rc = -EINVAL;
1146         }
1147
1148         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1149
1150         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1151         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1152         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1153                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1154
1155         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1156         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1157
1158         if (bp->max_resp_len != max_resp_len) {
1159                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1160                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1161                         bp->pdev->addr.devid, bp->pdev->addr.function);
1162
1163                 rte_free(bp->hwrm_cmd_resp_addr);
1164
1165                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1166                 if (bp->hwrm_cmd_resp_addr == NULL) {
1167                         rc = -ENOMEM;
1168                         goto error;
1169                 }
1170                 bp->hwrm_cmd_resp_dma_addr =
1171                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1172                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1173                         PMD_DRV_LOG(ERR,
1174                         "Unable to map response buffer to physical memory.\n");
1175                         rc = -ENOMEM;
1176                         goto error;
1177                 }
1178                 bp->max_resp_len = max_resp_len;
1179         }
1180
1181         if ((dev_caps_cfg &
1182                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1183             (dev_caps_cfg &
1184              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1185                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1186                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1187         }
1188
1189         if (((dev_caps_cfg &
1190               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1191              (dev_caps_cfg &
1192               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1193             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1194                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1195                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1196                         bp->pdev->addr.devid, bp->pdev->addr.function);
1197
1198                 rte_free(bp->hwrm_short_cmd_req_addr);
1199
1200                 bp->hwrm_short_cmd_req_addr =
1201                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1202                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1203                         rc = -ENOMEM;
1204                         goto error;
1205                 }
1206                 bp->hwrm_short_cmd_req_dma_addr =
1207                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1208                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1209                         rte_free(bp->hwrm_short_cmd_req_addr);
1210                         PMD_DRV_LOG(ERR,
1211                                 "Unable to map buffer to physical memory.\n");
1212                         rc = -ENOMEM;
1213                         goto error;
1214                 }
1215         }
1216         if (dev_caps_cfg &
1217             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1218                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1219                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1220         }
1221         if (dev_caps_cfg &
1222             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1223                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1224         if (dev_caps_cfg &
1225             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1226                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1227                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1228         }
1229
1230         if (dev_caps_cfg &
1231             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1232                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1233                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1234         }
1235
1236 error:
1237         HWRM_UNLOCK();
1238         return rc;
1239 }
1240
1241 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1242 {
1243         int rc;
1244         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1245         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1246
1247         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1248                 return 0;
1249
1250         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1251         req.flags = flags;
1252
1253         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1254
1255         HWRM_CHECK_RESULT();
1256         HWRM_UNLOCK();
1257
1258         return rc;
1259 }
1260
1261 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1262 {
1263         int rc = 0;
1264         struct hwrm_port_phy_cfg_input req = {0};
1265         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1266         uint32_t enables = 0;
1267
1268         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1269
1270         if (conf->link_up) {
1271                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1272                 if (bp->link_info->auto_mode && conf->link_speed) {
1273                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1274                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1275                 }
1276
1277                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1278                 /*
1279                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1280                  * any auto mode, even "none".
1281                  */
1282                 if (!conf->link_speed) {
1283                         /* No speeds specified. Enable AutoNeg - all speeds */
1284                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1285                         req.auto_mode =
1286                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1287                 } else {
1288                         if (bp->link_info->link_signal_mode) {
1289                                 enables |=
1290                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1291                                 req.force_pam4_link_speed =
1292                                         rte_cpu_to_le_16(conf->link_speed);
1293                         } else {
1294                                 req.force_link_speed =
1295                                         rte_cpu_to_le_16(conf->link_speed);
1296                         }
1297                 }
1298                 /* AutoNeg - Advertise speeds specified. */
1299                 if (conf->auto_link_speed_mask &&
1300                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1301                         req.auto_mode =
1302                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1303                         req.auto_link_speed_mask =
1304                                 conf->auto_link_speed_mask;
1305                         if (conf->auto_pam4_link_speeds) {
1306                                 enables |=
1307                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1308                                 req.auto_link_pam4_speed_mask =
1309                                         conf->auto_pam4_link_speeds;
1310                         } else {
1311                                 enables |=
1312                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1313                         }
1314                 }
1315                 if (conf->auto_link_speed &&
1316                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1317                         enables |=
1318                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1319
1320                 req.auto_duplex = conf->duplex;
1321                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1322                 req.auto_pause = conf->auto_pause;
1323                 req.force_pause = conf->force_pause;
1324                 /* Set force_pause if there is no auto or if there is a force */
1325                 if (req.auto_pause && !req.force_pause)
1326                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1327                 else
1328                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1329
1330                 req.enables = rte_cpu_to_le_32(enables);
1331         } else {
1332                 req.flags =
1333                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1334                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1335         }
1336
1337         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1338
1339         HWRM_CHECK_RESULT();
1340         HWRM_UNLOCK();
1341
1342         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1343                     bp->eth_dev->data->port_id);
1344         return rc;
1345 }
1346
1347 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1348                                    struct bnxt_link_info *link_info)
1349 {
1350         int rc = 0;
1351         struct hwrm_port_phy_qcfg_input req = {0};
1352         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1353
1354         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1355
1356         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1357
1358         HWRM_CHECK_RESULT();
1359
1360         link_info->phy_link_status = resp->link;
1361         link_info->link_up =
1362                 (link_info->phy_link_status ==
1363                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1364         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1365         link_info->duplex = resp->duplex_cfg;
1366         link_info->pause = resp->pause;
1367         link_info->auto_pause = resp->auto_pause;
1368         link_info->force_pause = resp->force_pause;
1369         link_info->auto_mode = resp->auto_mode;
1370         link_info->phy_type = resp->phy_type;
1371         link_info->media_type = resp->media_type;
1372
1373         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1374         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1375         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1376         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1377         link_info->phy_ver[0] = resp->phy_maj;
1378         link_info->phy_ver[1] = resp->phy_min;
1379         link_info->phy_ver[2] = resp->phy_bld;
1380         link_info->link_signal_mode =
1381                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1382         link_info->force_pam4_link_speed =
1383                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1384         link_info->support_pam4_speeds =
1385                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1386         link_info->auto_pam4_link_speeds =
1387                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1388         HWRM_UNLOCK();
1389
1390         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1391                     link_info->link_speed, link_info->auto_mode,
1392                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1393                     link_info->support_speeds, link_info->force_link_speed);
1394         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1395                     link_info->link_signal_mode,
1396                     link_info->auto_pam4_link_speeds,
1397                     link_info->support_pam4_speeds,
1398                     link_info->force_pam4_link_speed);
1399         return rc;
1400 }
1401
1402 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1403 {
1404         int rc = 0;
1405         struct hwrm_port_phy_qcaps_input req = {0};
1406         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1407         struct bnxt_link_info *link_info = bp->link_info;
1408
1409         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1410                 return 0;
1411
1412         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1413
1414         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1415
1416         HWRM_CHECK_RESULT();
1417
1418         bp->port_cnt = resp->port_cnt;
1419         if (resp->supported_speeds_auto_mode)
1420                 link_info->support_auto_speeds =
1421                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1422         if (resp->supported_pam4_speeds_auto_mode)
1423                 link_info->support_pam4_auto_speeds =
1424                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1425
1426         HWRM_UNLOCK();
1427
1428         return 0;
1429 }
1430
1431 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1432 {
1433         int i = 0;
1434
1435         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1436                 if (bp->tx_cos_queue[i].profile ==
1437                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1438                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1439                         return true;
1440                 }
1441         }
1442         return false;
1443 }
1444
1445 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1446 {
1447         int i = 0;
1448
1449         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1450                 if (bp->tx_cos_queue[i].profile !=
1451                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1452                     bp->tx_cos_queue[i].id !=
1453                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1454                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1455                         break;
1456                 }
1457         }
1458 }
1459
1460 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1461 {
1462         int rc = 0;
1463         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1464         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1465         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1466         int i;
1467
1468 get_rx_info:
1469         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1470
1471         req.flags = rte_cpu_to_le_32(dir);
1472         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1473         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1474             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1475                 req.drv_qmap_cap =
1476                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1477         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1478
1479         HWRM_CHECK_RESULT();
1480
1481         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1482                 GET_TX_QUEUE_INFO(0);
1483                 GET_TX_QUEUE_INFO(1);
1484                 GET_TX_QUEUE_INFO(2);
1485                 GET_TX_QUEUE_INFO(3);
1486                 GET_TX_QUEUE_INFO(4);
1487                 GET_TX_QUEUE_INFO(5);
1488                 GET_TX_QUEUE_INFO(6);
1489                 GET_TX_QUEUE_INFO(7);
1490         } else  {
1491                 GET_RX_QUEUE_INFO(0);
1492                 GET_RX_QUEUE_INFO(1);
1493                 GET_RX_QUEUE_INFO(2);
1494                 GET_RX_QUEUE_INFO(3);
1495                 GET_RX_QUEUE_INFO(4);
1496                 GET_RX_QUEUE_INFO(5);
1497                 GET_RX_QUEUE_INFO(6);
1498                 GET_RX_QUEUE_INFO(7);
1499         }
1500
1501         HWRM_UNLOCK();
1502
1503         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1504                 goto done;
1505
1506         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1507                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1508         } else {
1509                 int j;
1510
1511                 /* iterate and find the COSq profile to use for Tx */
1512                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1513                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1514                                 if (bp->tx_cos_queue[i].id != 0xff)
1515                                         bp->tx_cosq_id[j++] =
1516                                                 bp->tx_cos_queue[i].id;
1517                         }
1518                 } else {
1519                         /* When CoS classification is disabled, for normal NIC
1520                          * operations, ideally we should look to use LOSSY.
1521                          * If not found, fallback to the first valid profile
1522                          */
1523                         if (!bnxt_find_lossy_profile(bp))
1524                                 bnxt_find_first_valid_profile(bp);
1525
1526                 }
1527         }
1528
1529         bp->max_tc = resp->max_configurable_queues;
1530         bp->max_lltc = resp->max_configurable_lossless_queues;
1531         if (bp->max_tc > BNXT_MAX_QUEUE)
1532                 bp->max_tc = BNXT_MAX_QUEUE;
1533         bp->max_q = bp->max_tc;
1534
1535         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1536                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1537                 goto get_rx_info;
1538         }
1539
1540 done:
1541         return rc;
1542 }
1543
1544 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1545                          struct bnxt_ring *ring,
1546                          uint32_t ring_type, uint32_t map_index,
1547                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1548                          uint16_t tx_cosq_id)
1549 {
1550         int rc = 0;
1551         uint32_t enables = 0;
1552         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1553         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1554         struct rte_mempool *mb_pool;
1555         uint16_t rx_buf_size;
1556
1557         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1558
1559         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1560         req.fbo = rte_cpu_to_le_32(0);
1561         /* Association of ring index with doorbell index */
1562         req.logical_id = rte_cpu_to_le_16(map_index);
1563         req.length = rte_cpu_to_le_32(ring->ring_size);
1564
1565         switch (ring_type) {
1566         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1567                 req.ring_type = ring_type;
1568                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1569                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1570                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1571                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1572                         enables |=
1573                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1574                 break;
1575         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1576                 req.ring_type = ring_type;
1577                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1578                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1579                 if (BNXT_CHIP_P5(bp)) {
1580                         mb_pool = bp->rx_queues[0]->mb_pool;
1581                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1582                                       RTE_PKTMBUF_HEADROOM;
1583                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1584                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1585                         enables |=
1586                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1587                 }
1588                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1589                         enables |=
1590                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1591                 break;
1592         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1593                 req.ring_type = ring_type;
1594                 if (BNXT_HAS_NQ(bp)) {
1595                         /* Association of cp ring with nq */
1596                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1597                         enables |=
1598                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1599                 }
1600                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1601                 break;
1602         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1603                 req.ring_type = ring_type;
1604                 req.page_size = BNXT_PAGE_SHFT;
1605                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1606                 break;
1607         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1608                 req.ring_type = ring_type;
1609                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1610
1611                 mb_pool = bp->rx_queues[0]->mb_pool;
1612                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1613                               RTE_PKTMBUF_HEADROOM;
1614                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1615                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1616
1617                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1618                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1619                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1620                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1621                 break;
1622         default:
1623                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1624                         ring_type);
1625                 HWRM_UNLOCK();
1626                 return -EINVAL;
1627         }
1628         req.enables = rte_cpu_to_le_32(enables);
1629
1630         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1631
1632         if (rc || resp->error_code) {
1633                 if (rc == 0 && resp->error_code)
1634                         rc = rte_le_to_cpu_16(resp->error_code);
1635                 switch (ring_type) {
1636                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1637                         PMD_DRV_LOG(ERR,
1638                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1639                         HWRM_UNLOCK();
1640                         return rc;
1641                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1642                         PMD_DRV_LOG(ERR,
1643                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1644                         HWRM_UNLOCK();
1645                         return rc;
1646                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1647                         PMD_DRV_LOG(ERR,
1648                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1649                                     rc);
1650                         HWRM_UNLOCK();
1651                         return rc;
1652                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1653                         PMD_DRV_LOG(ERR,
1654                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1655                         HWRM_UNLOCK();
1656                         return rc;
1657                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1658                         PMD_DRV_LOG(ERR,
1659                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1660                         HWRM_UNLOCK();
1661                         return rc;
1662                 default:
1663                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1664                         HWRM_UNLOCK();
1665                         return rc;
1666                 }
1667         }
1668
1669         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1670         HWRM_UNLOCK();
1671         return rc;
1672 }
1673
1674 int bnxt_hwrm_ring_free(struct bnxt *bp,
1675                         struct bnxt_ring *ring, uint32_t ring_type)
1676 {
1677         int rc;
1678         struct hwrm_ring_free_input req = {.req_type = 0 };
1679         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1680
1681         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1682
1683         req.ring_type = ring_type;
1684         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1685
1686         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1687
1688         if (rc || resp->error_code) {
1689                 if (rc == 0 && resp->error_code)
1690                         rc = rte_le_to_cpu_16(resp->error_code);
1691                 HWRM_UNLOCK();
1692
1693                 switch (ring_type) {
1694                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1695                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1696                                 rc);
1697                         return rc;
1698                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1699                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1700                                 rc);
1701                         return rc;
1702                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1703                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1704                                 rc);
1705                         return rc;
1706                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1707                         PMD_DRV_LOG(ERR,
1708                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1709                         return rc;
1710                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1711                         PMD_DRV_LOG(ERR,
1712                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1713                         return rc;
1714                 default:
1715                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1716                         return rc;
1717                 }
1718         }
1719         HWRM_UNLOCK();
1720         return 0;
1721 }
1722
1723 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1724 {
1725         int rc = 0;
1726         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1727         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1728
1729         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1730
1731         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1732         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1733         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1734         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1735
1736         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1737
1738         HWRM_CHECK_RESULT();
1739
1740         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1741
1742         HWRM_UNLOCK();
1743
1744         return rc;
1745 }
1746
1747 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1748 {
1749         int rc;
1750         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1751         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1752
1753         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1754
1755         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1756
1757         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1758
1759         HWRM_CHECK_RESULT();
1760         HWRM_UNLOCK();
1761
1762         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1763         return rc;
1764 }
1765
1766 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1767 {
1768         int rc = 0;
1769         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1770         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1771
1772         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1773                 return rc;
1774
1775         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1776
1777         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1778
1779         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1780
1781         HWRM_CHECK_RESULT();
1782         HWRM_UNLOCK();
1783
1784         return rc;
1785 }
1786
1787 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1788                                 unsigned int idx __rte_unused)
1789 {
1790         int rc;
1791         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1792         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1793
1794         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1795
1796         req.update_period_ms = rte_cpu_to_le_32(0);
1797
1798         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1799
1800         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1801
1802         HWRM_CHECK_RESULT();
1803
1804         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1805
1806         HWRM_UNLOCK();
1807
1808         return rc;
1809 }
1810
1811 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1812                                 unsigned int idx __rte_unused)
1813 {
1814         int rc;
1815         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1816         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1817
1818         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1819
1820         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1821
1822         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1823
1824         HWRM_CHECK_RESULT();
1825         HWRM_UNLOCK();
1826
1827         return rc;
1828 }
1829
1830 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1831 {
1832         int rc = 0, i, j;
1833         struct hwrm_vnic_alloc_input req = { 0 };
1834         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1835
1836         if (!BNXT_HAS_RING_GRPS(bp))
1837                 goto skip_ring_grps;
1838
1839         /* map ring groups to this vnic */
1840         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1841                 vnic->start_grp_id, vnic->end_grp_id);
1842         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1843                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1844
1845         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1846         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1847         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1848         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1849
1850 skip_ring_grps:
1851         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1852         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1853
1854         if (vnic->func_default)
1855                 req.flags =
1856                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1857         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1858
1859         HWRM_CHECK_RESULT();
1860
1861         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1862         HWRM_UNLOCK();
1863         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1864         return rc;
1865 }
1866
1867 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1868                                         struct bnxt_vnic_info *vnic,
1869                                         struct bnxt_plcmodes_cfg *pmode)
1870 {
1871         int rc = 0;
1872         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1873         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1874
1875         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1876
1877         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1878
1879         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1880
1881         HWRM_CHECK_RESULT();
1882
1883         pmode->flags = rte_le_to_cpu_32(resp->flags);
1884         /* dflt_vnic bit doesn't exist in the _cfg command */
1885         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1886         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1887         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1888         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1889
1890         HWRM_UNLOCK();
1891
1892         return rc;
1893 }
1894
1895 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1896                                        struct bnxt_vnic_info *vnic,
1897                                        struct bnxt_plcmodes_cfg *pmode)
1898 {
1899         int rc = 0;
1900         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1901         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1902
1903         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1904                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1905                 return rc;
1906         }
1907
1908         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1909
1910         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1911         req.flags = rte_cpu_to_le_32(pmode->flags);
1912         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1913         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1914         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1915         req.enables = rte_cpu_to_le_32(
1916             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1917             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1918             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1919         );
1920
1921         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1922
1923         HWRM_CHECK_RESULT();
1924         HWRM_UNLOCK();
1925
1926         return rc;
1927 }
1928
1929 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1930 {
1931         int rc = 0;
1932         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1933         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1934         struct bnxt_plcmodes_cfg pmodes = { 0 };
1935         uint32_t ctx_enable_flag = 0;
1936         uint32_t enables = 0;
1937
1938         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1939                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1940                 return rc;
1941         }
1942
1943         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1944         if (rc)
1945                 return rc;
1946
1947         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1948
1949         if (BNXT_CHIP_P5(bp)) {
1950                 int dflt_rxq = vnic->start_grp_id;
1951                 struct bnxt_rx_ring_info *rxr;
1952                 struct bnxt_cp_ring_info *cpr;
1953                 struct bnxt_rx_queue *rxq;
1954                 int i;
1955
1956                 /*
1957                  * The first active receive ring is used as the VNIC
1958                  * default receive ring. If there are no active receive
1959                  * rings (all corresponding receive queues are stopped),
1960                  * the first receive ring is used.
1961                  */
1962                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1963                         rxq = bp->eth_dev->data->rx_queues[i];
1964                         if (rxq->rx_started) {
1965                                 dflt_rxq = i;
1966                                 break;
1967                         }
1968                 }
1969
1970                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1971                 rxr = rxq->rx_ring;
1972                 cpr = rxq->cp_ring;
1973
1974                 req.default_rx_ring_id =
1975                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1976                 req.default_cmpl_ring_id =
1977                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1978                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1979                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1980                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
1981                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
1982                         req.rx_csum_v2_mode =
1983                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
1984                 }
1985                 goto config_mru;
1986         }
1987
1988         /* Only RSS support for now TBD: COS & LB */
1989         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1990         if (vnic->lb_rule != 0xffff)
1991                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1992         if (vnic->cos_rule != 0xffff)
1993                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1994         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1995                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1996                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1997         }
1998         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1999                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2000                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2001         }
2002
2003         enables |= ctx_enable_flag;
2004         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2005         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2006         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2007         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2008
2009 config_mru:
2010         req.enables = rte_cpu_to_le_32(enables);
2011         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2012         req.mru = rte_cpu_to_le_16(vnic->mru);
2013         /* Configure default VNIC only once. */
2014         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2015                 req.flags |=
2016                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2017                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2018         }
2019         if (vnic->vlan_strip)
2020                 req.flags |=
2021                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2022         if (vnic->bd_stall)
2023                 req.flags |=
2024                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2025         if (vnic->rss_dflt_cr)
2026                 req.flags |= rte_cpu_to_le_32(
2027                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2028
2029         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2030
2031         HWRM_CHECK_RESULT();
2032         HWRM_UNLOCK();
2033
2034         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2035
2036         return rc;
2037 }
2038
2039 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2040                 int16_t fw_vf_id)
2041 {
2042         int rc = 0;
2043         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2044         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2045
2046         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2047                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2048                 return rc;
2049         }
2050         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2051
2052         req.enables =
2053                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2054         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2055         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2056
2057         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2058
2059         HWRM_CHECK_RESULT();
2060
2061         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2062         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2063         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2064         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2065         vnic->mru = rte_le_to_cpu_16(resp->mru);
2066         vnic->func_default = rte_le_to_cpu_32(
2067                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2068         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2069                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2070         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2071                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2072         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2073                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2074
2075         HWRM_UNLOCK();
2076
2077         return rc;
2078 }
2079
2080 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2081                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2082 {
2083         int rc = 0;
2084         uint16_t ctx_id;
2085         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2086         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2087                                                 bp->hwrm_cmd_resp_addr;
2088
2089         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2090
2091         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2092         HWRM_CHECK_RESULT();
2093
2094         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2095         if (!BNXT_HAS_RING_GRPS(bp))
2096                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2097         else if (ctx_idx == 0)
2098                 vnic->rss_rule = ctx_id;
2099
2100         HWRM_UNLOCK();
2101
2102         return rc;
2103 }
2104
2105 static
2106 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2107                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2108 {
2109         int rc = 0;
2110         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2111         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2112                                                 bp->hwrm_cmd_resp_addr;
2113
2114         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2115                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2116                 return rc;
2117         }
2118         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2119
2120         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2121
2122         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2123
2124         HWRM_CHECK_RESULT();
2125         HWRM_UNLOCK();
2126
2127         return rc;
2128 }
2129
2130 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2131 {
2132         int rc = 0;
2133
2134         if (BNXT_CHIP_P5(bp)) {
2135                 int j;
2136
2137                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2138                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2139                                                       vnic,
2140                                                       vnic->fw_grp_ids[j]);
2141                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2142                 }
2143                 vnic->num_lb_ctxts = 0;
2144         } else {
2145                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2146                 vnic->rss_rule = INVALID_HW_RING_ID;
2147         }
2148
2149         return rc;
2150 }
2151
2152 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2153 {
2154         int rc = 0;
2155         struct hwrm_vnic_free_input req = {.req_type = 0 };
2156         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2157
2158         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2159                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2160                 return rc;
2161         }
2162
2163         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2164
2165         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2166
2167         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2168
2169         HWRM_CHECK_RESULT();
2170         HWRM_UNLOCK();
2171
2172         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2173         /* Configure default VNIC again if necessary. */
2174         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2175                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2176
2177         return rc;
2178 }
2179
2180 static int
2181 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2182 {
2183         int i;
2184         int rc = 0;
2185         int nr_ctxs = vnic->num_lb_ctxts;
2186         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2187         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2188
2189         for (i = 0; i < nr_ctxs; i++) {
2190                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2191
2192                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2193                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2194                 req.hash_mode_flags = vnic->hash_mode;
2195
2196                 req.hash_key_tbl_addr =
2197                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2198
2199                 req.ring_grp_tbl_addr =
2200                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2201                                          i * HW_HASH_INDEX_SIZE);
2202                 req.ring_table_pair_index = i;
2203                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2204
2205                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2206                                             BNXT_USE_CHIMP_MB);
2207
2208                 HWRM_CHECK_RESULT();
2209                 HWRM_UNLOCK();
2210         }
2211
2212         return rc;
2213 }
2214
2215 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2216                            struct bnxt_vnic_info *vnic)
2217 {
2218         int rc = 0;
2219         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2220         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2221
2222         if (!vnic->rss_table)
2223                 return 0;
2224
2225         if (BNXT_CHIP_P5(bp))
2226                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2227
2228         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2229
2230         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2231         req.hash_mode_flags = vnic->hash_mode;
2232
2233         req.ring_grp_tbl_addr =
2234             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2235         req.hash_key_tbl_addr =
2236             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2237         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2238         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2239
2240         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2241
2242         HWRM_CHECK_RESULT();
2243         HWRM_UNLOCK();
2244
2245         return rc;
2246 }
2247
2248 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2249                         struct bnxt_vnic_info *vnic)
2250 {
2251         int rc = 0;
2252         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2253         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2254         uint16_t size;
2255
2256         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2257                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2258                 return rc;
2259         }
2260
2261         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2262
2263         req.flags = rte_cpu_to_le_32(
2264                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2265
2266         req.enables = rte_cpu_to_le_32(
2267                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2268
2269         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2270         size -= RTE_PKTMBUF_HEADROOM;
2271         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2272
2273         req.jumbo_thresh = rte_cpu_to_le_16(size);
2274         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2275
2276         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2277
2278         HWRM_CHECK_RESULT();
2279         HWRM_UNLOCK();
2280
2281         return rc;
2282 }
2283
2284 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2285                         struct bnxt_vnic_info *vnic, bool enable)
2286 {
2287         int rc = 0;
2288         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2289         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2290
2291         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2292                 if (enable)
2293                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2294                 return -ENOTSUP;
2295         }
2296
2297         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2298                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2299                 return 0;
2300         }
2301
2302         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2303
2304         if (enable) {
2305                 req.enables = rte_cpu_to_le_32(
2306                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2307                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2308                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2309                 req.flags = rte_cpu_to_le_32(
2310                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2311                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2312                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2313                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2314                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2315                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2316                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2317                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2318                 req.min_agg_len = rte_cpu_to_le_32(512);
2319         }
2320         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2321
2322         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2323
2324         HWRM_CHECK_RESULT();
2325         HWRM_UNLOCK();
2326
2327         return rc;
2328 }
2329
2330 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2331 {
2332         struct hwrm_func_cfg_input req = {0};
2333         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2334         int rc;
2335
2336         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2337         req.enables = rte_cpu_to_le_32(
2338                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2339         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2340         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2341
2342         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2343
2344         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2345         HWRM_CHECK_RESULT();
2346         HWRM_UNLOCK();
2347
2348         bp->pf->vf_info[vf].random_mac = false;
2349
2350         return rc;
2351 }
2352
2353 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2354                                   uint64_t *dropped)
2355 {
2356         int rc = 0;
2357         struct hwrm_func_qstats_input req = {.req_type = 0};
2358         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2359
2360         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2361
2362         req.fid = rte_cpu_to_le_16(fid);
2363
2364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2365
2366         HWRM_CHECK_RESULT();
2367
2368         if (dropped)
2369                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2370
2371         HWRM_UNLOCK();
2372
2373         return rc;
2374 }
2375
2376 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2377                           struct rte_eth_stats *stats,
2378                           struct hwrm_func_qstats_output *func_qstats)
2379 {
2380         int rc = 0;
2381         struct hwrm_func_qstats_input req = {.req_type = 0};
2382         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2383
2384         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2385
2386         req.fid = rte_cpu_to_le_16(fid);
2387
2388         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2389
2390         HWRM_CHECK_RESULT();
2391         if (func_qstats)
2392                 memcpy(func_qstats, resp,
2393                        sizeof(struct hwrm_func_qstats_output));
2394
2395         if (!stats)
2396                 goto exit;
2397
2398         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2399         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2400         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2401         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2402         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2403         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2404
2405         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2406         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2407         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2408         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2409         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2410         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2411
2412         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2413         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2414         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2415
2416 exit:
2417         HWRM_UNLOCK();
2418
2419         return rc;
2420 }
2421
2422 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2423 {
2424         int rc = 0;
2425         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2426         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2427
2428         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2429
2430         req.fid = rte_cpu_to_le_16(fid);
2431
2432         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2433
2434         HWRM_CHECK_RESULT();
2435         HWRM_UNLOCK();
2436
2437         return rc;
2438 }
2439
2440 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2441 {
2442         unsigned int i;
2443         int rc = 0;
2444
2445         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2446                 struct bnxt_tx_queue *txq;
2447                 struct bnxt_rx_queue *rxq;
2448                 struct bnxt_cp_ring_info *cpr;
2449
2450                 if (i >= bp->rx_cp_nr_rings) {
2451                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2452                         cpr = txq->cp_ring;
2453                 } else {
2454                         rxq = bp->rx_queues[i];
2455                         cpr = rxq->cp_ring;
2456                 }
2457
2458                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2459                 if (rc)
2460                         return rc;
2461         }
2462         return 0;
2463 }
2464
2465 static int
2466 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2467 {
2468         int rc;
2469         unsigned int i;
2470         struct bnxt_cp_ring_info *cpr;
2471
2472         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2473
2474                 if (i >= bp->rx_cp_nr_rings) {
2475                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2476                 } else {
2477                         cpr = bp->rx_queues[i]->cp_ring;
2478                         if (BNXT_HAS_RING_GRPS(bp))
2479                                 bp->grp_info[i].fw_stats_ctx = -1;
2480                 }
2481                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2482                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2483                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2484                         if (rc)
2485                                 return rc;
2486                 }
2487         }
2488         return 0;
2489 }
2490
2491 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2492 {
2493         unsigned int i;
2494         int rc = 0;
2495
2496         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2497                 struct bnxt_tx_queue *txq;
2498                 struct bnxt_rx_queue *rxq;
2499                 struct bnxt_cp_ring_info *cpr;
2500
2501                 if (i >= bp->rx_cp_nr_rings) {
2502                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2503                         cpr = txq->cp_ring;
2504                 } else {
2505                         rxq = bp->rx_queues[i];
2506                         cpr = rxq->cp_ring;
2507                 }
2508
2509                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2510
2511                 if (rc)
2512                         return rc;
2513         }
2514         return rc;
2515 }
2516
2517 static int
2518 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2519 {
2520         uint16_t idx;
2521         uint32_t rc = 0;
2522
2523         if (!BNXT_HAS_RING_GRPS(bp))
2524                 return 0;
2525
2526         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2527
2528                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2529                         continue;
2530
2531                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2532
2533                 if (rc)
2534                         return rc;
2535         }
2536         return rc;
2537 }
2538
2539 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2540 {
2541         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2542
2543         bnxt_hwrm_ring_free(bp, cp_ring,
2544                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2545         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2546         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2547                                      sizeof(*cpr->cp_desc_ring));
2548         cpr->cp_raw_cons = 0;
2549         cpr->valid = 0;
2550 }
2551
2552 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2553 {
2554         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2555
2556         bnxt_hwrm_ring_free(bp, cp_ring,
2557                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2558         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2559         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2560                         sizeof(*cpr->cp_desc_ring));
2561         cpr->cp_raw_cons = 0;
2562         cpr->valid = 0;
2563 }
2564
2565 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2566 {
2567         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2568         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2569         struct bnxt_ring *ring = rxr->rx_ring_struct;
2570         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2571
2572         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2573                 bnxt_hwrm_ring_free(bp, ring,
2574                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2575                 ring->fw_ring_id = INVALID_HW_RING_ID;
2576                 if (BNXT_HAS_RING_GRPS(bp))
2577                         bp->grp_info[queue_index].rx_fw_ring_id =
2578                                                         INVALID_HW_RING_ID;
2579         }
2580         ring = rxr->ag_ring_struct;
2581         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2582                 bnxt_hwrm_ring_free(bp, ring,
2583                                     BNXT_CHIP_P5(bp) ?
2584                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2585                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2586                 if (BNXT_HAS_RING_GRPS(bp))
2587                         bp->grp_info[queue_index].ag_fw_ring_id =
2588                                                         INVALID_HW_RING_ID;
2589         }
2590         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2591                 bnxt_free_cp_ring(bp, cpr);
2592
2593         if (BNXT_HAS_RING_GRPS(bp))
2594                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2595 }
2596
2597 static int
2598 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2599 {
2600         unsigned int i;
2601
2602         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2603                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2604                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2605                 struct bnxt_ring *ring = txr->tx_ring_struct;
2606                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2607
2608                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2609                         bnxt_hwrm_ring_free(bp, ring,
2610                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2611                         ring->fw_ring_id = INVALID_HW_RING_ID;
2612                         memset(txr->tx_desc_ring, 0,
2613                                         txr->tx_ring_struct->ring_size *
2614                                         sizeof(*txr->tx_desc_ring));
2615                         memset(txr->tx_buf_ring, 0,
2616                                         txr->tx_ring_struct->ring_size *
2617                                         sizeof(*txr->tx_buf_ring));
2618                         txr->tx_raw_prod = 0;
2619                         txr->tx_raw_cons = 0;
2620                 }
2621                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2622                         bnxt_free_cp_ring(bp, cpr);
2623                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2624                 }
2625         }
2626
2627         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2628                 bnxt_free_hwrm_rx_ring(bp, i);
2629
2630         return 0;
2631 }
2632
2633 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2634 {
2635         uint16_t i;
2636         uint32_t rc = 0;
2637
2638         if (!BNXT_HAS_RING_GRPS(bp))
2639                 return 0;
2640
2641         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2642                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2643                 if (rc)
2644                         return rc;
2645         }
2646         return rc;
2647 }
2648
2649 /*
2650  * HWRM utility functions
2651  */
2652
2653 void bnxt_free_hwrm_resources(struct bnxt *bp)
2654 {
2655         /* Release memzone */
2656         rte_free(bp->hwrm_cmd_resp_addr);
2657         rte_free(bp->hwrm_short_cmd_req_addr);
2658         bp->hwrm_cmd_resp_addr = NULL;
2659         bp->hwrm_short_cmd_req_addr = NULL;
2660         bp->hwrm_cmd_resp_dma_addr = 0;
2661         bp->hwrm_short_cmd_req_dma_addr = 0;
2662 }
2663
2664 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2665 {
2666         struct rte_pci_device *pdev = bp->pdev;
2667         char type[RTE_MEMZONE_NAMESIZE];
2668
2669         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2670                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2671         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2672         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2673         if (bp->hwrm_cmd_resp_addr == NULL)
2674                 return -ENOMEM;
2675         bp->hwrm_cmd_resp_dma_addr =
2676                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2677         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2678                 PMD_DRV_LOG(ERR,
2679                         "unable to map response address to physical memory\n");
2680                 return -ENOMEM;
2681         }
2682         rte_spinlock_init(&bp->hwrm_lock);
2683
2684         return 0;
2685 }
2686
2687 int
2688 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2689 {
2690         int rc = 0;
2691
2692         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2693                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2694                 if (rc)
2695                         return rc;
2696         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2697                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2698                 if (rc)
2699                         return rc;
2700         }
2701
2702         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2703         return rc;
2704 }
2705
2706 static int
2707 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2708 {
2709         struct bnxt_filter_info *filter;
2710         int rc = 0;
2711
2712         STAILQ_FOREACH(filter, &vnic->filter, next) {
2713                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2714                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2715                 bnxt_free_filter(bp, filter);
2716         }
2717         return rc;
2718 }
2719
2720 static int
2721 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2722 {
2723         struct bnxt_filter_info *filter;
2724         struct rte_flow *flow;
2725         int rc = 0;
2726
2727         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2728                 flow = STAILQ_FIRST(&vnic->flow_list);
2729                 filter = flow->filter;
2730                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2731                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2732
2733                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2734                 rte_free(flow);
2735         }
2736         return rc;
2737 }
2738
2739 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2740 {
2741         struct bnxt_filter_info *filter;
2742         int rc = 0;
2743
2744         STAILQ_FOREACH(filter, &vnic->filter, next) {
2745                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2746                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2747                                                      filter);
2748                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2749                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2750                                                          filter);
2751                 else
2752                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2753                                                      filter);
2754                 if (rc)
2755                         break;
2756         }
2757         return rc;
2758 }
2759
2760 static void
2761 bnxt_free_tunnel_ports(struct bnxt *bp)
2762 {
2763         if (bp->vxlan_port_cnt)
2764                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2765                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2766
2767         if (bp->geneve_port_cnt)
2768                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2769                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2770 }
2771
2772 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2773 {
2774         int i;
2775
2776         if (bp->vnic_info == NULL)
2777                 return;
2778
2779         /*
2780          * Cleanup VNICs in reverse order, to make sure the L2 filter
2781          * from vnic0 is last to be cleaned up.
2782          */
2783         for (i = bp->max_vnics - 1; i >= 0; i--) {
2784                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2785
2786                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2787                         continue;
2788
2789                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2790
2791                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2792
2793                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2794
2795                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2796
2797                 bnxt_hwrm_vnic_free(bp, vnic);
2798
2799                 rte_free(vnic->fw_grp_ids);
2800         }
2801         /* Ring resources */
2802         bnxt_free_all_hwrm_rings(bp);
2803         bnxt_free_all_hwrm_ring_grps(bp);
2804         bnxt_free_all_hwrm_stat_ctxs(bp);
2805         bnxt_free_tunnel_ports(bp);
2806 }
2807
2808 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2809 {
2810         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2811
2812         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2813                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2814
2815         switch (conf_link_speed) {
2816         case ETH_LINK_SPEED_10M_HD:
2817         case ETH_LINK_SPEED_100M_HD:
2818                 /* FALLTHROUGH */
2819                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2820         }
2821         return hw_link_duplex;
2822 }
2823
2824 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2825 {
2826         return !conf_link;
2827 }
2828
2829 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2830                                           uint16_t pam4_link)
2831 {
2832         uint16_t eth_link_speed = 0;
2833
2834         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2835                 return ETH_LINK_SPEED_AUTONEG;
2836
2837         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2838         case ETH_LINK_SPEED_100M:
2839         case ETH_LINK_SPEED_100M_HD:
2840                 /* FALLTHROUGH */
2841                 eth_link_speed =
2842                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2843                 break;
2844         case ETH_LINK_SPEED_1G:
2845                 eth_link_speed =
2846                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2847                 break;
2848         case ETH_LINK_SPEED_2_5G:
2849                 eth_link_speed =
2850                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2851                 break;
2852         case ETH_LINK_SPEED_10G:
2853                 eth_link_speed =
2854                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2855                 break;
2856         case ETH_LINK_SPEED_20G:
2857                 eth_link_speed =
2858                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2859                 break;
2860         case ETH_LINK_SPEED_25G:
2861                 eth_link_speed =
2862                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2863                 break;
2864         case ETH_LINK_SPEED_40G:
2865                 eth_link_speed =
2866                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2867                 break;
2868         case ETH_LINK_SPEED_50G:
2869                 eth_link_speed = pam4_link ?
2870                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
2871                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2872                 break;
2873         case ETH_LINK_SPEED_100G:
2874                 eth_link_speed = pam4_link ?
2875                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
2876                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2877                 break;
2878         case ETH_LINK_SPEED_200G:
2879                 eth_link_speed =
2880                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2881                 break;
2882         default:
2883                 PMD_DRV_LOG(ERR,
2884                         "Unsupported link speed %d; default to AUTO\n",
2885                         conf_link_speed);
2886                 break;
2887         }
2888         return eth_link_speed;
2889 }
2890
2891 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2892                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2893                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2894                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2895                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2896
2897 static int bnxt_validate_link_speed(struct bnxt *bp)
2898 {
2899         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2900         uint16_t port_id = bp->eth_dev->data->port_id;
2901         uint32_t link_speed_capa;
2902         uint32_t one_speed;
2903
2904         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2905                 return 0;
2906
2907         link_speed_capa = bnxt_get_speed_capabilities(bp);
2908
2909         if (link_speed & ETH_LINK_SPEED_FIXED) {
2910                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2911
2912                 if (one_speed & (one_speed - 1)) {
2913                         PMD_DRV_LOG(ERR,
2914                                 "Invalid advertised speeds (%u) for port %u\n",
2915                                 link_speed, port_id);
2916                         return -EINVAL;
2917                 }
2918                 if ((one_speed & link_speed_capa) != one_speed) {
2919                         PMD_DRV_LOG(ERR,
2920                                 "Unsupported advertised speed (%u) for port %u\n",
2921                                 link_speed, port_id);
2922                         return -EINVAL;
2923                 }
2924         } else {
2925                 if (!(link_speed & link_speed_capa)) {
2926                         PMD_DRV_LOG(ERR,
2927                                 "Unsupported advertised speeds (%u) for port %u\n",
2928                                 link_speed, port_id);
2929                         return -EINVAL;
2930                 }
2931         }
2932         return 0;
2933 }
2934
2935 static uint16_t
2936 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2937 {
2938         uint16_t ret = 0;
2939
2940         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2941                 if (bp->link_info->support_speeds)
2942                         return bp->link_info->support_speeds;
2943                 link_speed = BNXT_SUPPORTED_SPEEDS;
2944         }
2945
2946         if (link_speed & ETH_LINK_SPEED_100M)
2947                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2948         if (link_speed & ETH_LINK_SPEED_100M_HD)
2949                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2950         if (link_speed & ETH_LINK_SPEED_1G)
2951                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2952         if (link_speed & ETH_LINK_SPEED_2_5G)
2953                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2954         if (link_speed & ETH_LINK_SPEED_10G)
2955                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2956         if (link_speed & ETH_LINK_SPEED_20G)
2957                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2958         if (link_speed & ETH_LINK_SPEED_25G)
2959                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2960         if (link_speed & ETH_LINK_SPEED_40G)
2961                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2962         if (link_speed & ETH_LINK_SPEED_50G)
2963                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2964         if (link_speed & ETH_LINK_SPEED_100G)
2965                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2966         if (link_speed & ETH_LINK_SPEED_200G)
2967                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2968         return ret;
2969 }
2970
2971 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2972 {
2973         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2974
2975         switch (hw_link_speed) {
2976         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2977                 eth_link_speed = ETH_SPEED_NUM_100M;
2978                 break;
2979         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2980                 eth_link_speed = ETH_SPEED_NUM_1G;
2981                 break;
2982         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2983                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2984                 break;
2985         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2986                 eth_link_speed = ETH_SPEED_NUM_10G;
2987                 break;
2988         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2989                 eth_link_speed = ETH_SPEED_NUM_20G;
2990                 break;
2991         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2992                 eth_link_speed = ETH_SPEED_NUM_25G;
2993                 break;
2994         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2995                 eth_link_speed = ETH_SPEED_NUM_40G;
2996                 break;
2997         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2998                 eth_link_speed = ETH_SPEED_NUM_50G;
2999                 break;
3000         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3001                 eth_link_speed = ETH_SPEED_NUM_100G;
3002                 break;
3003         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3004                 eth_link_speed = ETH_SPEED_NUM_200G;
3005                 break;
3006         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3007         default:
3008                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3009                         hw_link_speed);
3010                 break;
3011         }
3012         return eth_link_speed;
3013 }
3014
3015 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3016 {
3017         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3018
3019         switch (hw_link_duplex) {
3020         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3021         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3022                 /* FALLTHROUGH */
3023                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3024                 break;
3025         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3026                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3027                 break;
3028         default:
3029                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3030                         hw_link_duplex);
3031                 break;
3032         }
3033         return eth_link_duplex;
3034 }
3035
3036 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3037 {
3038         int rc = 0;
3039         struct bnxt_link_info *link_info = bp->link_info;
3040
3041         rc = bnxt_hwrm_port_phy_qcaps(bp);
3042         if (rc)
3043                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3044
3045         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3046         if (rc) {
3047                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3048                 goto exit;
3049         }
3050
3051         if (link_info->link_speed)
3052                 link->link_speed =
3053                         bnxt_parse_hw_link_speed(link_info->link_speed);
3054         else
3055                 link->link_speed = ETH_SPEED_NUM_NONE;
3056         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3057         link->link_status = link_info->link_up;
3058         link->link_autoneg = link_info->auto_mode ==
3059                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3060                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3061 exit:
3062         return rc;
3063 }
3064
3065 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3066 {
3067         int rc = 0;
3068         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3069         struct bnxt_link_info link_req;
3070         uint16_t speed, autoneg;
3071
3072         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3073                 return 0;
3074
3075         rc = bnxt_validate_link_speed(bp);
3076         if (rc)
3077                 goto error;
3078
3079         memset(&link_req, 0, sizeof(link_req));
3080         link_req.link_up = link_up;
3081         if (!link_up)
3082                 goto port_phy_cfg;
3083
3084         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3085         if (BNXT_CHIP_P5(bp) &&
3086             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3087                 /* 40G is not supported as part of media auto detect.
3088                  * The speed should be forced and autoneg disabled
3089                  * to configure 40G speed.
3090                  */
3091                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3092                 autoneg = 0;
3093         }
3094
3095         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3096         if (bp->link_info->auto_link_speed == 0 &&
3097             bp->link_info->link_signal_mode &&
3098             bp->link_info->auto_pam4_link_speeds == 0)
3099                 autoneg = 0;
3100
3101         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3102                                           bp->link_info->link_signal_mode);
3103         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3104         /* Autoneg can be done only when the FW allows.
3105          * When user configures fixed speed of 40G and later changes to
3106          * any other speed, auto_link_speed/force_link_speed is still set
3107          * to 40G until link comes up at new speed.
3108          */
3109         if (autoneg == 1 &&
3110             !(!BNXT_CHIP_P5(bp) &&
3111               (bp->link_info->auto_link_speed ||
3112                bp->link_info->force_link_speed))) {
3113                 link_req.phy_flags |=
3114                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3115                 link_req.auto_link_speed_mask =
3116                         bnxt_parse_eth_link_speed_mask(bp,
3117                                                        dev_conf->link_speeds);
3118         } else {
3119                 if (bp->link_info->phy_type ==
3120                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3121                     bp->link_info->phy_type ==
3122                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3123                     bp->link_info->media_type ==
3124                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3125                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3126                         return -EINVAL;
3127                 }
3128
3129                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3130                 /* If user wants a particular speed try that first. */
3131                 if (speed)
3132                         link_req.link_speed = speed;
3133                 else if (bp->link_info->force_pam4_link_speed)
3134                         link_req.link_speed =
3135                                 bp->link_info->force_pam4_link_speed;
3136                 else if (bp->link_info->auto_pam4_link_speeds)
3137                         link_req.link_speed =
3138                                 bp->link_info->auto_pam4_link_speeds;
3139                 else if (bp->link_info->support_pam4_speeds)
3140                         link_req.link_speed =
3141                                 bp->link_info->support_pam4_speeds;
3142                 else if (bp->link_info->force_link_speed)
3143                         link_req.link_speed = bp->link_info->force_link_speed;
3144                 else
3145                         link_req.link_speed = bp->link_info->auto_link_speed;
3146                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3147                  * zero. Use the auto_link_speed.
3148                  */
3149                 if (bp->link_info->auto_link_speed != 0 &&
3150                     bp->link_info->auto_pam4_link_speeds == 0)
3151                         link_req.link_speed = bp->link_info->auto_link_speed;
3152         }
3153         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3154         link_req.auto_pause = bp->link_info->auto_pause;
3155         link_req.force_pause = bp->link_info->force_pause;
3156
3157 port_phy_cfg:
3158         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3159         if (rc) {
3160                 PMD_DRV_LOG(ERR,
3161                         "Set link config failed with rc %d\n", rc);
3162         }
3163
3164 error:
3165         return rc;
3166 }
3167
3168 /* JIRA 22088 */
3169 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3170 {
3171         struct hwrm_func_qcfg_input req = {0};
3172         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3173         uint16_t flags;
3174         int rc = 0;
3175         bp->func_svif = BNXT_SVIF_INVALID;
3176         uint16_t svif_info;
3177
3178         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3179         req.fid = rte_cpu_to_le_16(0xffff);
3180
3181         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3182
3183         HWRM_CHECK_RESULT();
3184
3185         /* Hard Coded.. 0xfff VLAN ID mask */
3186         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3187
3188         svif_info = rte_le_to_cpu_16(resp->svif_info);
3189         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3190                 bp->func_svif = svif_info &
3191                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3192
3193         flags = rte_le_to_cpu_16(resp->flags);
3194         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3195                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3196
3197         if (BNXT_VF(bp) &&
3198             !BNXT_VF_IS_TRUSTED(bp) &&
3199             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3200                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3201                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3202         } else if (BNXT_VF(bp) &&
3203                    BNXT_VF_IS_TRUSTED(bp) &&
3204                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3205                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3206                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3207         }
3208
3209         if (mtu)
3210                 *mtu = rte_le_to_cpu_16(resp->mtu);
3211
3212         switch (resp->port_partition_type) {
3213         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3214         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3215         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3216                 /* FALLTHROUGH */
3217                 bp->flags |= BNXT_FLAG_NPAR_PF;
3218                 break;
3219         default:
3220                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3221                 break;
3222         }
3223
3224         bp->legacy_db_size =
3225                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3226
3227         HWRM_UNLOCK();
3228
3229         return rc;
3230 }
3231
3232 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3233 {
3234         struct hwrm_func_qcfg_input req = {0};
3235         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3236         int rc;
3237
3238         if (!BNXT_VF_IS_TRUSTED(bp))
3239                 return 0;
3240
3241         if (!bp->parent)
3242                 return -EINVAL;
3243
3244         bp->parent->fid = BNXT_PF_FID_INVALID;
3245
3246         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3247
3248         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3249
3250         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3251
3252         HWRM_CHECK_RESULT();
3253
3254         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3255         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3256         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3257         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3258
3259         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3260         if (bp->parent->vnic == 0) {
3261                 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3262                 /* Use hard-coded values appropriate for current Wh+ fw. */
3263                 if (bp->parent->fid == 2)
3264                         bp->parent->vnic = 0x100;
3265                 else
3266                         bp->parent->vnic = 1;
3267         }
3268
3269         HWRM_UNLOCK();
3270
3271         return 0;
3272 }
3273
3274 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3275                                  uint16_t *vnic_id, uint16_t *svif)
3276 {
3277         struct hwrm_func_qcfg_input req = {0};
3278         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3279         uint16_t svif_info;
3280         int rc = 0;
3281
3282         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3283         req.fid = rte_cpu_to_le_16(fid);
3284
3285         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3286
3287         HWRM_CHECK_RESULT();
3288
3289         if (vnic_id)
3290                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3291
3292         svif_info = rte_le_to_cpu_16(resp->svif_info);
3293         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3294                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3295
3296         HWRM_UNLOCK();
3297
3298         return rc;
3299 }
3300
3301 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3302 {
3303         struct hwrm_port_mac_qcfg_input req = {0};
3304         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3305         uint16_t port_svif_info;
3306         int rc;
3307
3308         bp->port_svif = BNXT_SVIF_INVALID;
3309
3310         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3311                 return 0;
3312
3313         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3314
3315         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3316
3317         HWRM_CHECK_RESULT_SILENT();
3318
3319         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3320         if (port_svif_info &
3321             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3322                 bp->port_svif = port_svif_info &
3323                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3324
3325         HWRM_UNLOCK();
3326
3327         return 0;
3328 }
3329
3330 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3331                                  struct bnxt_pf_resource_info *pf_resc)
3332 {
3333         struct hwrm_func_cfg_input req = {0};
3334         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3335         uint32_t enables;
3336         int rc;
3337
3338         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3339                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3340                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3341                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3342                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3343                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3344                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3345                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3346                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3347
3348         if (BNXT_HAS_RING_GRPS(bp)) {
3349                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3350                 req.num_hw_ring_grps =
3351                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3352         } else if (BNXT_HAS_NQ(bp)) {
3353                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3354                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3355         }
3356
3357         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3358         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3359         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3360         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3361         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3362         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3363         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3364         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3365         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3366         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3367         req.fid = rte_cpu_to_le_16(0xffff);
3368         req.enables = rte_cpu_to_le_32(enables);
3369
3370         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3371
3372         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3373
3374         HWRM_CHECK_RESULT();
3375         HWRM_UNLOCK();
3376
3377         return rc;
3378 }
3379
3380 /* min values are the guaranteed resources and max values are subject
3381  * to availability. The strategy for now is to keep both min & max
3382  * values the same.
3383  */
3384 static void
3385 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3386                               struct hwrm_func_vf_resource_cfg_input *req,
3387                               int num_vfs)
3388 {
3389         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3390                                                (num_vfs + 1));
3391         req->min_rsscos_ctx = req->max_rsscos_ctx;
3392         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3393         req->min_stat_ctx = req->max_stat_ctx;
3394         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3395                                                (num_vfs + 1));
3396         req->min_cmpl_rings = req->max_cmpl_rings;
3397         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3398         req->min_tx_rings = req->max_tx_rings;
3399         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3400         req->min_rx_rings = req->max_rx_rings;
3401         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3402         req->min_l2_ctxs = req->max_l2_ctxs;
3403         /* TODO: For now, do not support VMDq/RFS on VFs. */
3404         req->max_vnics = rte_cpu_to_le_16(1);
3405         req->min_vnics = req->max_vnics;
3406         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3407                                                  (num_vfs + 1));
3408         req->min_hw_ring_grps = req->max_hw_ring_grps;
3409         req->flags =
3410          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3411 }
3412
3413 static void
3414 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3415                               struct hwrm_func_cfg_input *req,
3416                               int num_vfs)
3417 {
3418         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3419                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3420                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3421                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3422                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3423                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3424                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3425                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3426                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3427                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3428
3429         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3430                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3431                                     BNXT_NUM_VLANS);
3432         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3433         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3434                                                 (num_vfs + 1));
3435         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3436         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3437                                                (num_vfs + 1));
3438         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3439         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3440         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3441         /* TODO: For now, do not support VMDq/RFS on VFs. */
3442         req->num_vnics = rte_cpu_to_le_16(1);
3443         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3444                                                  (num_vfs + 1));
3445 }
3446
3447 /* Update the port wide resource values based on how many resources
3448  * got allocated to the VF.
3449  */
3450 static int bnxt_update_max_resources(struct bnxt *bp,
3451                                      int vf)
3452 {
3453         struct hwrm_func_qcfg_input req = {0};
3454         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3455         int rc;
3456
3457         /* Get the actual allocated values now */
3458         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3459         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3460         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3461         HWRM_CHECK_RESULT();
3462
3463         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3464         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3465         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3466         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3467         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3468         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3469         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3470
3471         HWRM_UNLOCK();
3472
3473         return 0;
3474 }
3475
3476 /* Update the PF resource values based on how many resources
3477  * got allocated to it.
3478  */
3479 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3480 {
3481         struct hwrm_func_qcfg_input req = {0};
3482         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3483         int rc;
3484
3485         /* Get the actual allocated values now */
3486         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3487         req.fid = rte_cpu_to_le_16(0xffff);
3488         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3489         HWRM_CHECK_RESULT();
3490
3491         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3492         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3493         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3494         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3495         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3496         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3497         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3498         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3499
3500         HWRM_UNLOCK();
3501
3502         return 0;
3503 }
3504
3505 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3506 {
3507         struct hwrm_func_qcfg_input req = {0};
3508         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3509         int rc;
3510
3511         /* Check for zero MAC address */
3512         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3513         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3514         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3515         HWRM_CHECK_RESULT();
3516         rc = rte_le_to_cpu_16(resp->vlan);
3517
3518         HWRM_UNLOCK();
3519
3520         return rc;
3521 }
3522
3523 static int bnxt_query_pf_resources(struct bnxt *bp,
3524                                    struct bnxt_pf_resource_info *pf_resc)
3525 {
3526         struct hwrm_func_qcfg_input req = {0};
3527         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3528         int rc;
3529
3530         /* And copy the allocated numbers into the pf struct */
3531         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3532         req.fid = rte_cpu_to_le_16(0xffff);
3533         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3534         HWRM_CHECK_RESULT();
3535
3536         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3537         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3538         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3539         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3540         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3541         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3542         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3543         bp->pf->evb_mode = resp->evb_mode;
3544
3545         HWRM_UNLOCK();
3546
3547         return rc;
3548 }
3549
3550 static void
3551 bnxt_calculate_pf_resources(struct bnxt *bp,
3552                             struct bnxt_pf_resource_info *pf_resc,
3553                             int num_vfs)
3554 {
3555         if (!num_vfs) {
3556                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3557                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3558                 pf_resc->num_cp_rings = bp->max_cp_rings;
3559                 pf_resc->num_tx_rings = bp->max_tx_rings;
3560                 pf_resc->num_rx_rings = bp->max_rx_rings;
3561                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3562                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3563
3564                 return;
3565         }
3566
3567         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3568                                    bp->max_rsscos_ctx % (num_vfs + 1);
3569         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3570                                  bp->max_stat_ctx % (num_vfs + 1);
3571         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3572                                 bp->max_cp_rings % (num_vfs + 1);
3573         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3574                                 bp->max_tx_rings % (num_vfs + 1);
3575         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3576                                 bp->max_rx_rings % (num_vfs + 1);
3577         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3578                                bp->max_l2_ctx % (num_vfs + 1);
3579         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3580                                     bp->max_ring_grps % (num_vfs + 1);
3581 }
3582
3583 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3584 {
3585         struct bnxt_pf_resource_info pf_resc = { 0 };
3586         int rc;
3587
3588         if (!BNXT_PF(bp)) {
3589                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3590                 return -EINVAL;
3591         }
3592
3593         rc = bnxt_hwrm_func_qcaps(bp);
3594         if (rc)
3595                 return rc;
3596
3597         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3598
3599         bp->pf->func_cfg_flags &=
3600                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3601                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3602         bp->pf->func_cfg_flags |=
3603                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3604
3605         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3606         if (rc)
3607                 return rc;
3608
3609         rc = bnxt_update_max_resources_pf_only(bp);
3610
3611         return rc;
3612 }
3613
3614 static int
3615 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3616 {
3617         size_t req_buf_sz, sz;
3618         int i, rc;
3619
3620         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3621         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3622                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3623         if (bp->pf->vf_req_buf == NULL) {
3624                 return -ENOMEM;
3625         }
3626
3627         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3628                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3629
3630         for (i = 0; i < num_vfs; i++)
3631                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3632                                              (i * HWRM_MAX_REQ_LEN);
3633
3634         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3635         if (rc)
3636                 rte_free(bp->pf->vf_req_buf);
3637
3638         return rc;
3639 }
3640
3641 static int
3642 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3643 {
3644         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3645         struct hwrm_func_vf_resource_cfg_input req = {0};
3646         int i, rc = 0;
3647
3648         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3649         bp->pf->active_vfs = 0;
3650         for (i = 0; i < num_vfs; i++) {
3651                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3652                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3653                 rc = bnxt_hwrm_send_message(bp,
3654                                             &req,
3655                                             sizeof(req),
3656                                             BNXT_USE_CHIMP_MB);
3657                 if (rc || resp->error_code) {
3658                         PMD_DRV_LOG(ERR,
3659                                 "Failed to initialize VF %d\n", i);
3660                         PMD_DRV_LOG(ERR,
3661                                 "Not all VFs available. (%d, %d)\n",
3662                                 rc, resp->error_code);
3663                         HWRM_UNLOCK();
3664
3665                         /* If the first VF configuration itself fails,
3666                          * unregister the vf_fwd_request buffer.
3667                          */
3668                         if (i == 0)
3669                                 bnxt_hwrm_func_buf_unrgtr(bp);
3670                         break;
3671                 }
3672                 HWRM_UNLOCK();
3673
3674                 /* Update the max resource values based on the resource values
3675                  * allocated to the VF.
3676                  */
3677                 bnxt_update_max_resources(bp, i);
3678                 bp->pf->active_vfs++;
3679                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3680         }
3681
3682         return 0;
3683 }
3684
3685 static int
3686 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3687 {
3688         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3689         struct hwrm_func_cfg_input req = {0};
3690         int i, rc;
3691
3692         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3693
3694         bp->pf->active_vfs = 0;
3695         for (i = 0; i < num_vfs; i++) {
3696                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3697                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3698                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3699                 rc = bnxt_hwrm_send_message(bp,
3700                                             &req,
3701                                             sizeof(req),
3702                                             BNXT_USE_CHIMP_MB);
3703
3704                 /* Clear enable flag for next pass */
3705                 req.enables &= ~rte_cpu_to_le_32(
3706                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3707
3708                 if (rc || resp->error_code) {
3709                         PMD_DRV_LOG(ERR,
3710                                 "Failed to initialize VF %d\n", i);
3711                         PMD_DRV_LOG(ERR,
3712                                 "Not all VFs available. (%d, %d)\n",
3713                                 rc, resp->error_code);
3714                         HWRM_UNLOCK();
3715
3716                         /* If the first VF configuration itself fails,
3717                          * unregister the vf_fwd_request buffer.
3718                          */
3719                         if (i == 0)
3720                                 bnxt_hwrm_func_buf_unrgtr(bp);
3721                         break;
3722                 }
3723
3724                 HWRM_UNLOCK();
3725
3726                 /* Update the max resource values based on the resource values
3727                  * allocated to the VF.
3728                  */
3729                 bnxt_update_max_resources(bp, i);
3730                 bp->pf->active_vfs++;
3731                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3732         }
3733
3734         return 0;
3735 }
3736
3737 static void
3738 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3739 {
3740         if (bp->flags & BNXT_FLAG_NEW_RM)
3741                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3742         else
3743                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3744 }
3745
3746 static void
3747 bnxt_update_pf_resources(struct bnxt *bp,
3748                          struct bnxt_pf_resource_info *pf_resc)
3749 {
3750         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3751         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3752         bp->max_cp_rings = pf_resc->num_cp_rings;
3753         bp->max_tx_rings = pf_resc->num_tx_rings;
3754         bp->max_rx_rings = pf_resc->num_rx_rings;
3755         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3756 }
3757
3758 static int32_t
3759 bnxt_configure_pf_resources(struct bnxt *bp,
3760                             struct bnxt_pf_resource_info *pf_resc)
3761 {
3762         /*
3763          * We're using STD_TX_RING_MODE here which will limit the TX
3764          * rings. This will allow QoS to function properly. Not setting this
3765          * will cause PF rings to break bandwidth settings.
3766          */
3767         bp->pf->func_cfg_flags &=
3768                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3769                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3770         bp->pf->func_cfg_flags |=
3771                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3772         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3773 }
3774
3775 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3776 {
3777         struct bnxt_pf_resource_info pf_resc = { 0 };
3778         int rc;
3779
3780         if (!BNXT_PF(bp)) {
3781                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3782                 return -EINVAL;
3783         }
3784
3785         rc = bnxt_hwrm_func_qcaps(bp);
3786         if (rc)
3787                 return rc;
3788
3789         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3790
3791         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3792         if (rc)
3793                 return rc;
3794
3795         rc = bnxt_query_pf_resources(bp, &pf_resc);
3796         if (rc)
3797                 return rc;
3798
3799         /*
3800          * Now, create and register a buffer to hold forwarded VF requests
3801          */
3802         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3803         if (rc)
3804                 return rc;
3805
3806         bnxt_configure_vf_resources(bp, num_vfs);
3807
3808         bnxt_update_pf_resources(bp, &pf_resc);
3809
3810         return 0;
3811 }
3812
3813 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3814 {
3815         struct hwrm_func_cfg_input req = {0};
3816         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3817         int rc;
3818
3819         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3820
3821         req.fid = rte_cpu_to_le_16(0xffff);
3822         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3823         req.evb_mode = bp->pf->evb_mode;
3824
3825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3826         HWRM_CHECK_RESULT();
3827         HWRM_UNLOCK();
3828
3829         return rc;
3830 }
3831
3832 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3833                                 uint8_t tunnel_type)
3834 {
3835         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3836         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3837         int rc = 0;
3838
3839         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3840         req.tunnel_type = tunnel_type;
3841         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3842         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3843         HWRM_CHECK_RESULT();
3844
3845         switch (tunnel_type) {
3846         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3847                 bp->vxlan_fw_dst_port_id =
3848                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3849                 bp->vxlan_port = port;
3850                 break;
3851         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3852                 bp->geneve_fw_dst_port_id =
3853                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3854                 bp->geneve_port = port;
3855                 break;
3856         default:
3857                 break;
3858         }
3859
3860         HWRM_UNLOCK();
3861
3862         return rc;
3863 }
3864
3865 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3866                                 uint8_t tunnel_type)
3867 {
3868         struct hwrm_tunnel_dst_port_free_input req = {0};
3869         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3870         int rc = 0;
3871
3872         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3873
3874         req.tunnel_type = tunnel_type;
3875         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3876         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3877
3878         HWRM_CHECK_RESULT();
3879         HWRM_UNLOCK();
3880
3881         if (tunnel_type ==
3882             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
3883                 bp->vxlan_port = 0;
3884                 bp->vxlan_port_cnt = 0;
3885         }
3886
3887         if (tunnel_type ==
3888             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
3889                 bp->geneve_port = 0;
3890                 bp->geneve_port_cnt = 0;
3891         }
3892
3893         return rc;
3894 }
3895
3896 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3897                                         uint32_t flags)
3898 {
3899         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3900         struct hwrm_func_cfg_input req = {0};
3901         int rc;
3902
3903         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3904
3905         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3906         req.flags = rte_cpu_to_le_32(flags);
3907         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3908
3909         HWRM_CHECK_RESULT();
3910         HWRM_UNLOCK();
3911
3912         return rc;
3913 }
3914
3915 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3916 {
3917         uint32_t *flag = flagp;
3918
3919         vnic->flags = *flag;
3920 }
3921
3922 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3923 {
3924         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3925 }
3926
3927 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
3928 {
3929         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3930         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3931         int rc;
3932
3933         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3934
3935         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3936         req.req_buf_page_size =
3937                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
3938         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3939         req.req_buf_page_addr0 =
3940                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3941         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3942                 PMD_DRV_LOG(ERR,
3943                         "unable to map buffer address to physical memory\n");
3944                 HWRM_UNLOCK();
3945                 return -ENOMEM;
3946         }
3947
3948         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3949
3950         HWRM_CHECK_RESULT();
3951         HWRM_UNLOCK();
3952
3953         return rc;
3954 }
3955
3956 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3957 {
3958         int rc = 0;
3959         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3960         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3961
3962         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3963                 return 0;
3964
3965         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3966
3967         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3968
3969         HWRM_CHECK_RESULT();
3970         HWRM_UNLOCK();
3971
3972         return rc;
3973 }
3974
3975 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3976 {
3977         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3978         struct hwrm_func_cfg_input req = {0};
3979         int rc;
3980
3981         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3982
3983         req.fid = rte_cpu_to_le_16(0xffff);
3984         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3985         req.enables = rte_cpu_to_le_32(
3986                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3987         req.async_event_cr = rte_cpu_to_le_16(
3988                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3989         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3990
3991         HWRM_CHECK_RESULT();
3992         HWRM_UNLOCK();
3993
3994         return rc;
3995 }
3996
3997 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3998 {
3999         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4000         struct hwrm_func_vf_cfg_input req = {0};
4001         int rc;
4002
4003         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4004
4005         req.enables = rte_cpu_to_le_32(
4006                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4007         req.async_event_cr = rte_cpu_to_le_16(
4008                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4009         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4010
4011         HWRM_CHECK_RESULT();
4012         HWRM_UNLOCK();
4013
4014         return rc;
4015 }
4016
4017 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4018 {
4019         struct hwrm_func_cfg_input req = {0};
4020         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4021         uint16_t dflt_vlan, fid;
4022         uint32_t func_cfg_flags;
4023         int rc = 0;
4024
4025         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4026
4027         if (is_vf) {
4028                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4029                 fid = bp->pf->vf_info[vf].fid;
4030                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4031         } else {
4032                 fid = rte_cpu_to_le_16(0xffff);
4033                 func_cfg_flags = bp->pf->func_cfg_flags;
4034                 dflt_vlan = bp->vlan;
4035         }
4036
4037         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4038         req.fid = rte_cpu_to_le_16(fid);
4039         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4040         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4041
4042         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4043
4044         HWRM_CHECK_RESULT();
4045         HWRM_UNLOCK();
4046
4047         return rc;
4048 }
4049
4050 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4051                         uint16_t max_bw, uint16_t enables)
4052 {
4053         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4054         struct hwrm_func_cfg_input req = {0};
4055         int rc;
4056
4057         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4058
4059         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4060         req.enables |= rte_cpu_to_le_32(enables);
4061         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4062         req.max_bw = rte_cpu_to_le_32(max_bw);
4063         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4064
4065         HWRM_CHECK_RESULT();
4066         HWRM_UNLOCK();
4067
4068         return rc;
4069 }
4070
4071 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4072 {
4073         struct hwrm_func_cfg_input req = {0};
4074         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4075         int rc = 0;
4076
4077         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4078
4079         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4080         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4081         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4082         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4083
4084         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4085
4086         HWRM_CHECK_RESULT();
4087         HWRM_UNLOCK();
4088
4089         return rc;
4090 }
4091
4092 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4093 {
4094         int rc;
4095
4096         if (BNXT_PF(bp))
4097                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4098         else
4099                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4100
4101         return rc;
4102 }
4103
4104 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4105                               void *encaped, size_t ec_size)
4106 {
4107         int rc = 0;
4108         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4109         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4110
4111         if (ec_size > sizeof(req.encap_request))
4112                 return -1;
4113
4114         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4115
4116         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4117         memcpy(req.encap_request, encaped, ec_size);
4118
4119         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4120
4121         HWRM_CHECK_RESULT();
4122         HWRM_UNLOCK();
4123
4124         return rc;
4125 }
4126
4127 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4128                                        struct rte_ether_addr *mac)
4129 {
4130         struct hwrm_func_qcfg_input req = {0};
4131         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4132         int rc;
4133
4134         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4135
4136         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4137         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4138
4139         HWRM_CHECK_RESULT();
4140
4141         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4142
4143         HWRM_UNLOCK();
4144
4145         return rc;
4146 }
4147
4148 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4149                             void *encaped, size_t ec_size)
4150 {
4151         int rc = 0;
4152         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4153         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4154
4155         if (ec_size > sizeof(req.encap_request))
4156                 return -1;
4157
4158         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4159
4160         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4161         memcpy(req.encap_request, encaped, ec_size);
4162
4163         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4164
4165         HWRM_CHECK_RESULT();
4166         HWRM_UNLOCK();
4167
4168         return rc;
4169 }
4170
4171 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
4172                          struct rte_eth_stats *stats, uint8_t rx)
4173 {
4174         int rc = 0;
4175         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4176         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4177
4178         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4179
4180         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4181
4182         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4183
4184         HWRM_CHECK_RESULT();
4185
4186         if (rx) {
4187                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4188                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4189                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4190                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4191                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4192                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4193                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4194                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4195         } else {
4196                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4197                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4198                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4199                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4200                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4201                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4202         }
4203
4204         HWRM_UNLOCK();
4205
4206         return rc;
4207 }
4208
4209 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4210 {
4211         struct hwrm_port_qstats_input req = {0};
4212         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4213         struct bnxt_pf_info *pf = bp->pf;
4214         int rc;
4215
4216         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4217
4218         req.port_id = rte_cpu_to_le_16(pf->port_id);
4219         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4220         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4221         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4222
4223         HWRM_CHECK_RESULT();
4224         HWRM_UNLOCK();
4225
4226         return rc;
4227 }
4228
4229 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4230 {
4231         struct hwrm_port_clr_stats_input req = {0};
4232         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4233         struct bnxt_pf_info *pf = bp->pf;
4234         int rc;
4235
4236         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4237         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4238             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4239                 return 0;
4240
4241         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4242
4243         req.port_id = rte_cpu_to_le_16(pf->port_id);
4244         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4245
4246         HWRM_CHECK_RESULT();
4247         HWRM_UNLOCK();
4248
4249         return rc;
4250 }
4251
4252 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4253 {
4254         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4255         struct hwrm_port_led_qcaps_input req = {0};
4256         int rc;
4257
4258         if (BNXT_VF(bp))
4259                 return 0;
4260
4261         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4262         req.port_id = bp->pf->port_id;
4263         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4264
4265         HWRM_CHECK_RESULT();
4266
4267         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4268                 unsigned int i;
4269
4270                 bp->leds->num_leds = resp->num_leds;
4271                 memcpy(bp->leds, &resp->led0_id,
4272                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4273                 for (i = 0; i < bp->leds->num_leds; i++) {
4274                         struct bnxt_led_info *led = &bp->leds[i];
4275
4276                         uint16_t caps = led->led_state_caps;
4277
4278                         if (!led->led_group_id ||
4279                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4280                                 bp->leds->num_leds = 0;
4281                                 break;
4282                         }
4283                 }
4284         }
4285
4286         HWRM_UNLOCK();
4287
4288         return rc;
4289 }
4290
4291 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4292 {
4293         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4294         struct hwrm_port_led_cfg_input req = {0};
4295         struct bnxt_led_cfg *led_cfg;
4296         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4297         uint16_t duration = 0;
4298         int rc, i;
4299
4300         if (!bp->leds->num_leds || BNXT_VF(bp))
4301                 return -EOPNOTSUPP;
4302
4303         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4304
4305         if (led_on) {
4306                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4307                 duration = rte_cpu_to_le_16(500);
4308         }
4309         req.port_id = bp->pf->port_id;
4310         req.num_leds = bp->leds->num_leds;
4311         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4312         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4313                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4314                 led_cfg->led_id = bp->leds[i].led_id;
4315                 led_cfg->led_state = led_state;
4316                 led_cfg->led_blink_on = duration;
4317                 led_cfg->led_blink_off = duration;
4318                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4319         }
4320
4321         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4322
4323         HWRM_CHECK_RESULT();
4324         HWRM_UNLOCK();
4325
4326         return rc;
4327 }
4328
4329 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4330                                uint32_t *length)
4331 {
4332         int rc;
4333         struct hwrm_nvm_get_dir_info_input req = {0};
4334         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4335
4336         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4337
4338         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4339
4340         HWRM_CHECK_RESULT();
4341
4342         *entries = rte_le_to_cpu_32(resp->entries);
4343         *length = rte_le_to_cpu_32(resp->entry_length);
4344
4345         HWRM_UNLOCK();
4346         return rc;
4347 }
4348
4349 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4350 {
4351         int rc;
4352         uint32_t dir_entries;
4353         uint32_t entry_length;
4354         uint8_t *buf;
4355         size_t buflen;
4356         rte_iova_t dma_handle;
4357         struct hwrm_nvm_get_dir_entries_input req = {0};
4358         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4359
4360         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4361         if (rc != 0)
4362                 return rc;
4363
4364         *data++ = dir_entries;
4365         *data++ = entry_length;
4366         len -= 2;
4367         memset(data, 0xff, len);
4368
4369         buflen = dir_entries * entry_length;
4370         buf = rte_malloc("nvm_dir", buflen, 0);
4371         if (buf == NULL)
4372                 return -ENOMEM;
4373         dma_handle = rte_malloc_virt2iova(buf);
4374         if (dma_handle == RTE_BAD_IOVA) {
4375                 rte_free(buf);
4376                 PMD_DRV_LOG(ERR,
4377                         "unable to map response address to physical memory\n");
4378                 return -ENOMEM;
4379         }
4380         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4381         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4382         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4383
4384         if (rc == 0)
4385                 memcpy(data, buf, len > buflen ? buflen : len);
4386
4387         rte_free(buf);
4388         HWRM_CHECK_RESULT();
4389         HWRM_UNLOCK();
4390
4391         return rc;
4392 }
4393
4394 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4395                              uint32_t offset, uint32_t length,
4396                              uint8_t *data)
4397 {
4398         int rc;
4399         uint8_t *buf;
4400         rte_iova_t dma_handle;
4401         struct hwrm_nvm_read_input req = {0};
4402         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4403
4404         buf = rte_malloc("nvm_item", length, 0);
4405         if (!buf)
4406                 return -ENOMEM;
4407
4408         dma_handle = rte_malloc_virt2iova(buf);
4409         if (dma_handle == RTE_BAD_IOVA) {
4410                 rte_free(buf);
4411                 PMD_DRV_LOG(ERR,
4412                         "unable to map response address to physical memory\n");
4413                 return -ENOMEM;
4414         }
4415         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4416         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4417         req.dir_idx = rte_cpu_to_le_16(index);
4418         req.offset = rte_cpu_to_le_32(offset);
4419         req.len = rte_cpu_to_le_32(length);
4420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4421         if (rc == 0)
4422                 memcpy(data, buf, length);
4423
4424         rte_free(buf);
4425         HWRM_CHECK_RESULT();
4426         HWRM_UNLOCK();
4427
4428         return rc;
4429 }
4430
4431 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4432 {
4433         int rc;
4434         struct hwrm_nvm_erase_dir_entry_input req = {0};
4435         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4436
4437         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4438         req.dir_idx = rte_cpu_to_le_16(index);
4439         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4440         HWRM_CHECK_RESULT();
4441         HWRM_UNLOCK();
4442
4443         return rc;
4444 }
4445
4446
4447 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4448                           uint16_t dir_ordinal, uint16_t dir_ext,
4449                           uint16_t dir_attr, const uint8_t *data,
4450                           size_t data_len)
4451 {
4452         int rc;
4453         struct hwrm_nvm_write_input req = {0};
4454         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4455         rte_iova_t dma_handle;
4456         uint8_t *buf;
4457
4458         buf = rte_malloc("nvm_write", data_len, 0);
4459         if (!buf)
4460                 return -ENOMEM;
4461
4462         dma_handle = rte_malloc_virt2iova(buf);
4463         if (dma_handle == RTE_BAD_IOVA) {
4464                 rte_free(buf);
4465                 PMD_DRV_LOG(ERR,
4466                         "unable to map response address to physical memory\n");
4467                 return -ENOMEM;
4468         }
4469         memcpy(buf, data, data_len);
4470
4471         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4472
4473         req.dir_type = rte_cpu_to_le_16(dir_type);
4474         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4475         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4476         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4477         req.dir_data_length = rte_cpu_to_le_32(data_len);
4478         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4479
4480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4481
4482         rte_free(buf);
4483         HWRM_CHECK_RESULT();
4484         HWRM_UNLOCK();
4485
4486         return rc;
4487 }
4488
4489 static void
4490 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4491 {
4492         uint32_t *count = cbdata;
4493
4494         *count = *count + 1;
4495 }
4496
4497 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4498                                      struct bnxt_vnic_info *vnic __rte_unused)
4499 {
4500         return 0;
4501 }
4502
4503 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4504 {
4505         uint32_t count = 0;
4506
4507         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4508             &count, bnxt_vnic_count_hwrm_stub);
4509
4510         return count;
4511 }
4512
4513 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4514                                         uint16_t *vnic_ids)
4515 {
4516         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4517         struct hwrm_func_vf_vnic_ids_query_output *resp =
4518                                                 bp->hwrm_cmd_resp_addr;
4519         int rc;
4520
4521         /* First query all VNIC ids */
4522         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4523
4524         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4525         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4526         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4527
4528         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4529                 HWRM_UNLOCK();
4530                 PMD_DRV_LOG(ERR,
4531                 "unable to map VNIC ID table address to physical memory\n");
4532                 return -ENOMEM;
4533         }
4534         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4535         HWRM_CHECK_RESULT();
4536         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4537
4538         HWRM_UNLOCK();
4539
4540         return rc;
4541 }
4542
4543 /*
4544  * This function queries the VNIC IDs  for a specified VF. It then calls
4545  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4546  * Then it calls the hwrm_cb function to program this new vnic configuration.
4547  */
4548 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4549         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4550         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4551 {
4552         struct bnxt_vnic_info vnic;
4553         int rc = 0;
4554         int i, num_vnic_ids;
4555         uint16_t *vnic_ids;
4556         size_t vnic_id_sz;
4557         size_t sz;
4558
4559         /* First query all VNIC ids */
4560         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4561         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4562                         RTE_CACHE_LINE_SIZE);
4563         if (vnic_ids == NULL)
4564                 return -ENOMEM;
4565
4566         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4567                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4568
4569         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4570
4571         if (num_vnic_ids < 0)
4572                 return num_vnic_ids;
4573
4574         /* Retrieve VNIC, update bd_stall then update */
4575
4576         for (i = 0; i < num_vnic_ids; i++) {
4577                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4578                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4579                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4580                 if (rc)
4581                         break;
4582                 if (vnic.mru <= 4)      /* Indicates unallocated */
4583                         continue;
4584
4585                 vnic_cb(&vnic, cbdata);
4586
4587                 rc = hwrm_cb(bp, &vnic);
4588                 if (rc)
4589                         break;
4590         }
4591
4592         rte_free(vnic_ids);
4593
4594         return rc;
4595 }
4596
4597 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4598                                               bool on)
4599 {
4600         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4601         struct hwrm_func_cfg_input req = {0};
4602         int rc;
4603
4604         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4605
4606         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4607         req.enables |= rte_cpu_to_le_32(
4608                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4609         req.vlan_antispoof_mode = on ?
4610                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4611                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4612         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4613
4614         HWRM_CHECK_RESULT();
4615         HWRM_UNLOCK();
4616
4617         return rc;
4618 }
4619
4620 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4621 {
4622         struct bnxt_vnic_info vnic;
4623         uint16_t *vnic_ids;
4624         size_t vnic_id_sz;
4625         int num_vnic_ids, i;
4626         size_t sz;
4627         int rc;
4628
4629         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4630         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4631                         RTE_CACHE_LINE_SIZE);
4632         if (vnic_ids == NULL)
4633                 return -ENOMEM;
4634
4635         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4636                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4637
4638         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4639         if (rc <= 0)
4640                 goto exit;
4641         num_vnic_ids = rc;
4642
4643         /*
4644          * Loop through to find the default VNIC ID.
4645          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4646          * by sending the hwrm_func_qcfg command to the firmware.
4647          */
4648         for (i = 0; i < num_vnic_ids; i++) {
4649                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4650                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4651                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4652                                         bp->pf->first_vf_id + vf);
4653                 if (rc)
4654                         goto exit;
4655                 if (vnic.func_default) {
4656                         rte_free(vnic_ids);
4657                         return vnic.fw_vnic_id;
4658                 }
4659         }
4660         /* Could not find a default VNIC. */
4661         PMD_DRV_LOG(ERR, "No default VNIC\n");
4662 exit:
4663         rte_free(vnic_ids);
4664         return rc;
4665 }
4666
4667 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4668                          uint16_t dst_id,
4669                          struct bnxt_filter_info *filter)
4670 {
4671         int rc = 0;
4672         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4673         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4674         uint32_t enables = 0;
4675
4676         if (filter->fw_em_filter_id != UINT64_MAX)
4677                 bnxt_hwrm_clear_em_filter(bp, filter);
4678
4679         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4680
4681         req.flags = rte_cpu_to_le_32(filter->flags);
4682
4683         enables = filter->enables |
4684               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4685         req.dst_id = rte_cpu_to_le_16(dst_id);
4686
4687         if (filter->ip_addr_type) {
4688                 req.ip_addr_type = filter->ip_addr_type;
4689                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4690         }
4691         if (enables &
4692             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4693                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4694         if (enables &
4695             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4696                 memcpy(req.src_macaddr, filter->src_macaddr,
4697                        RTE_ETHER_ADDR_LEN);
4698         if (enables &
4699             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4700                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4701                        RTE_ETHER_ADDR_LEN);
4702         if (enables &
4703             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4704                 req.ovlan_vid = filter->l2_ovlan;
4705         if (enables &
4706             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4707                 req.ivlan_vid = filter->l2_ivlan;
4708         if (enables &
4709             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4710                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4711         if (enables &
4712             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4713                 req.ip_protocol = filter->ip_protocol;
4714         if (enables &
4715             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4716                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4717         if (enables &
4718             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4719                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4720         if (enables &
4721             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4722                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4723         if (enables &
4724             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4725                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4726         if (enables &
4727             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4728                 req.mirror_vnic_id = filter->mirror_vnic_id;
4729
4730         req.enables = rte_cpu_to_le_32(enables);
4731
4732         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4733
4734         HWRM_CHECK_RESULT();
4735
4736         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4737         HWRM_UNLOCK();
4738
4739         return rc;
4740 }
4741
4742 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4743 {
4744         int rc = 0;
4745         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4746         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4747
4748         if (filter->fw_em_filter_id == UINT64_MAX)
4749                 return 0;
4750
4751         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4752
4753         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4754
4755         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4756
4757         HWRM_CHECK_RESULT();
4758         HWRM_UNLOCK();
4759
4760         filter->fw_em_filter_id = UINT64_MAX;
4761         filter->fw_l2_filter_id = UINT64_MAX;
4762
4763         return 0;
4764 }
4765
4766 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4767                          uint16_t dst_id,
4768                          struct bnxt_filter_info *filter)
4769 {
4770         int rc = 0;
4771         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4772         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4773                                                 bp->hwrm_cmd_resp_addr;
4774         uint32_t enables = 0;
4775
4776         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4777                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4778
4779         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4780
4781         req.flags = rte_cpu_to_le_32(filter->flags);
4782
4783         enables = filter->enables |
4784               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4785         req.dst_id = rte_cpu_to_le_16(dst_id);
4786
4787         if (filter->ip_addr_type) {
4788                 req.ip_addr_type = filter->ip_addr_type;
4789                 enables |=
4790                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4791         }
4792         if (enables &
4793             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4794                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4795         if (enables &
4796             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4797                 memcpy(req.src_macaddr, filter->src_macaddr,
4798                        RTE_ETHER_ADDR_LEN);
4799         if (enables &
4800             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4801                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4802         if (enables &
4803             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4804                 req.ip_protocol = filter->ip_protocol;
4805         if (enables &
4806             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4807                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4808         if (enables &
4809             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4810                 req.src_ipaddr_mask[0] =
4811                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4812         if (enables &
4813             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4814                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4815         if (enables &
4816             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4817                 req.dst_ipaddr_mask[0] =
4818                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4819         if (enables &
4820             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4821                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4822         if (enables &
4823             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4824                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4825         if (enables &
4826             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4827                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4828         if (enables &
4829             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4830                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4831         if (enables &
4832             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4833                 req.mirror_vnic_id = filter->mirror_vnic_id;
4834
4835         req.enables = rte_cpu_to_le_32(enables);
4836
4837         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4838
4839         HWRM_CHECK_RESULT();
4840
4841         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4842         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4843         HWRM_UNLOCK();
4844
4845         return rc;
4846 }
4847
4848 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4849                                 struct bnxt_filter_info *filter)
4850 {
4851         int rc = 0;
4852         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4853         struct hwrm_cfa_ntuple_filter_free_output *resp =
4854                                                 bp->hwrm_cmd_resp_addr;
4855
4856         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4857                 return 0;
4858
4859         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4860
4861         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4862
4863         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4864
4865         HWRM_CHECK_RESULT();
4866         HWRM_UNLOCK();
4867
4868         filter->fw_ntuple_filter_id = UINT64_MAX;
4869
4870         return 0;
4871 }
4872
4873 static int
4874 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4875 {
4876         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4877         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4878         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4879         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4880         uint16_t *ring_tbl = vnic->rss_table;
4881         int nr_ctxs = vnic->num_lb_ctxts;
4882         int max_rings = bp->rx_nr_rings;
4883         int i, j, k, cnt;
4884         int rc = 0;
4885
4886         for (i = 0, k = 0; i < nr_ctxs; i++) {
4887                 struct bnxt_rx_ring_info *rxr;
4888                 struct bnxt_cp_ring_info *cpr;
4889
4890                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4891
4892                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4893                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4894                 req.hash_mode_flags = vnic->hash_mode;
4895
4896                 req.ring_grp_tbl_addr =
4897                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4898                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
4899                                      2 * sizeof(*ring_tbl));
4900                 req.hash_key_tbl_addr =
4901                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4902
4903                 req.ring_table_pair_index = i;
4904                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4905
4906                 for (j = 0; j < 64; j++) {
4907                         uint16_t ring_id;
4908
4909                         /* Find next active ring. */
4910                         for (cnt = 0; cnt < max_rings; cnt++) {
4911                                 if (rx_queue_state[k] !=
4912                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4913                                         break;
4914                                 if (++k == max_rings)
4915                                         k = 0;
4916                         }
4917
4918                         /* Return if no rings are active. */
4919                         if (cnt == max_rings) {
4920                                 HWRM_UNLOCK();
4921                                 return 0;
4922                         }
4923
4924                         /* Add rx/cp ring pair to RSS table. */
4925                         rxr = rxqs[k]->rx_ring;
4926                         cpr = rxqs[k]->cp_ring;
4927
4928                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4929                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4930                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4931                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4932
4933                         if (++k == max_rings)
4934                                 k = 0;
4935                 }
4936                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4937                                             BNXT_USE_CHIMP_MB);
4938
4939                 HWRM_CHECK_RESULT();
4940                 HWRM_UNLOCK();
4941         }
4942
4943         return rc;
4944 }
4945
4946 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4947 {
4948         unsigned int rss_idx, fw_idx, i;
4949
4950         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4951                 return 0;
4952
4953         if (!(vnic->rss_table && vnic->hash_type))
4954                 return 0;
4955
4956         if (BNXT_CHIP_P5(bp))
4957                 return bnxt_vnic_rss_configure_p5(bp, vnic);
4958
4959         /*
4960          * Fill the RSS hash & redirection table with
4961          * ring group ids for all VNICs
4962          */
4963         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4964              rss_idx++, fw_idx++) {
4965                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4966                         fw_idx %= bp->rx_cp_nr_rings;
4967                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4968                                 break;
4969                         fw_idx++;
4970                 }
4971
4972                 if (i == bp->rx_cp_nr_rings)
4973                         return 0;
4974
4975                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4976         }
4977
4978         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4979 }
4980
4981 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4982         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4983 {
4984         uint16_t flags;
4985
4986         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4987
4988         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4989         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4990
4991         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4992         req->num_cmpl_dma_aggr_during_int =
4993                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4994
4995         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4996
4997         /* min timer set to 1/2 of interrupt timer */
4998         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4999
5000         /* buf timer set to 1/4 of interrupt timer */
5001         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5002
5003         req->cmpl_aggr_dma_tmr_during_int =
5004                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5005
5006         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5007                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5008         req->flags = rte_cpu_to_le_16(flags);
5009 }
5010
5011 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5012                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5013 {
5014         struct hwrm_ring_aggint_qcaps_input req = {0};
5015         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5016         uint32_t enables;
5017         uint16_t flags;
5018         int rc;
5019
5020         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5021         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5022         HWRM_CHECK_RESULT();
5023
5024         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5025         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5026
5027         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5028                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5029         agg_req->flags = rte_cpu_to_le_16(flags);
5030         enables =
5031          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5032          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5033         agg_req->enables = rte_cpu_to_le_32(enables);
5034
5035         HWRM_UNLOCK();
5036         return rc;
5037 }
5038
5039 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5040                         struct bnxt_coal *coal, uint16_t ring_id)
5041 {
5042         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5043         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5044                                                 bp->hwrm_cmd_resp_addr;
5045         int rc;
5046
5047         /* Set ring coalesce parameters only for 100G NICs */
5048         if (BNXT_CHIP_P5(bp)) {
5049                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5050                         return -1;
5051         } else if (bnxt_stratus_device(bp)) {
5052                 bnxt_hwrm_set_coal_params(coal, &req);
5053         } else {
5054                 return 0;
5055         }
5056
5057         HWRM_PREP(&req,
5058                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5059                   BNXT_USE_CHIMP_MB);
5060         req.ring_id = rte_cpu_to_le_16(ring_id);
5061         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5062         HWRM_CHECK_RESULT();
5063         HWRM_UNLOCK();
5064         return 0;
5065 }
5066
5067 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5068 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5069 {
5070         struct hwrm_func_backing_store_qcaps_input req = {0};
5071         struct hwrm_func_backing_store_qcaps_output *resp =
5072                 bp->hwrm_cmd_resp_addr;
5073         struct bnxt_ctx_pg_info *ctx_pg;
5074         struct bnxt_ctx_mem_info *ctx;
5075         int total_alloc_len;
5076         int rc, i, tqm_rings;
5077
5078         if (!BNXT_CHIP_P5(bp) ||
5079             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5080             BNXT_VF(bp) ||
5081             bp->ctx)
5082                 return 0;
5083
5084         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5085         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5086         HWRM_CHECK_RESULT_SILENT();
5087
5088         total_alloc_len = sizeof(*ctx);
5089         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5090                           RTE_CACHE_LINE_SIZE);
5091         if (!ctx) {
5092                 rc = -ENOMEM;
5093                 goto ctx_err;
5094         }
5095
5096         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5097         ctx->qp_min_qp1_entries =
5098                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5099         ctx->qp_max_l2_entries =
5100                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5101         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5102         ctx->srq_max_l2_entries =
5103                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5104         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5105         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5106         ctx->cq_max_l2_entries =
5107                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5108         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5109         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5110         ctx->vnic_max_vnic_entries =
5111                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5112         ctx->vnic_max_ring_table_entries =
5113                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5114         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5115         ctx->stat_max_entries =
5116                 rte_le_to_cpu_32(resp->stat_max_entries);
5117         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5118         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5119         ctx->tqm_min_entries_per_ring =
5120                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5121         ctx->tqm_max_entries_per_ring =
5122                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5123         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5124         if (!ctx->tqm_entries_multiple)
5125                 ctx->tqm_entries_multiple = 1;
5126         ctx->mrav_max_entries =
5127                 rte_le_to_cpu_32(resp->mrav_max_entries);
5128         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5129         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5130         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5131         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5132
5133         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5134                                   RTE_MIN(ctx->tqm_fp_rings_count,
5135                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5136                                   bp->max_q;
5137
5138         /* Check if the ext ring count needs to be counted.
5139          * Ext ring count is available only with new FW so we should not
5140          * look at the field on older FW.
5141          */
5142         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5143             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5144                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5145                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5146                                                   ctx->tqm_fp_rings_count);
5147         }
5148
5149         tqm_rings = ctx->tqm_fp_rings_count + 1;
5150
5151         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5152                             sizeof(*ctx_pg) * tqm_rings,
5153                             RTE_CACHE_LINE_SIZE);
5154         if (!ctx_pg) {
5155                 rc = -ENOMEM;
5156                 goto ctx_err;
5157         }
5158         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5159                 ctx->tqm_mem[i] = ctx_pg;
5160
5161         bp->ctx = ctx;
5162 ctx_err:
5163         HWRM_UNLOCK();
5164         return rc;
5165 }
5166
5167 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5168 {
5169         struct hwrm_func_backing_store_cfg_input req = {0};
5170         struct hwrm_func_backing_store_cfg_output *resp =
5171                 bp->hwrm_cmd_resp_addr;
5172         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5173         struct bnxt_ctx_pg_info *ctx_pg;
5174         uint32_t *num_entries;
5175         uint64_t *pg_dir;
5176         uint8_t *pg_attr;
5177         uint32_t ena;
5178         int i, rc;
5179
5180         if (!ctx)
5181                 return 0;
5182
5183         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5184         req.enables = rte_cpu_to_le_32(enables);
5185
5186         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5187                 ctx_pg = &ctx->qp_mem;
5188                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5189                 req.qp_num_qp1_entries =
5190                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5191                 req.qp_num_l2_entries =
5192                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5193                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5194                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5195                                       &req.qpc_pg_size_qpc_lvl,
5196                                       &req.qpc_page_dir);
5197         }
5198
5199         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5200                 ctx_pg = &ctx->srq_mem;
5201                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5202                 req.srq_num_l2_entries =
5203                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5204                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5205                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5206                                       &req.srq_pg_size_srq_lvl,
5207                                       &req.srq_page_dir);
5208         }
5209
5210         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5211                 ctx_pg = &ctx->cq_mem;
5212                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5213                 req.cq_num_l2_entries =
5214                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5215                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5216                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5217                                       &req.cq_pg_size_cq_lvl,
5218                                       &req.cq_page_dir);
5219         }
5220
5221         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5222                 ctx_pg = &ctx->vnic_mem;
5223                 req.vnic_num_vnic_entries =
5224                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5225                 req.vnic_num_ring_table_entries =
5226                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5227                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5228                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5229                                       &req.vnic_pg_size_vnic_lvl,
5230                                       &req.vnic_page_dir);
5231         }
5232
5233         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5234                 ctx_pg = &ctx->stat_mem;
5235                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5236                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5237                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5238                                       &req.stat_pg_size_stat_lvl,
5239                                       &req.stat_page_dir);
5240         }
5241
5242         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5243         num_entries = &req.tqm_sp_num_entries;
5244         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5245         pg_dir = &req.tqm_sp_page_dir;
5246         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5247         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5248                 if (!(enables & ena))
5249                         continue;
5250
5251                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5252
5253                 ctx_pg = ctx->tqm_mem[i];
5254                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5255                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5256         }
5257
5258         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5259                 /* DPDK does not need to configure MRAV and TIM type.
5260                  * So we are skipping over MRAV and TIM. Skip to configure
5261                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5262                  */
5263                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5264                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5265                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5266                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5267                                       &req.tqm_ring8_page_dir);
5268         }
5269
5270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5271         HWRM_CHECK_RESULT();
5272         HWRM_UNLOCK();
5273
5274         return rc;
5275 }
5276
5277 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5278 {
5279         struct hwrm_port_qstats_ext_input req = {0};
5280         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5281         struct bnxt_pf_info *pf = bp->pf;
5282         int rc;
5283
5284         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5285               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5286                 return 0;
5287
5288         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5289
5290         req.port_id = rte_cpu_to_le_16(pf->port_id);
5291         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5292                 req.tx_stat_host_addr =
5293                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5294                 req.tx_stat_size =
5295                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5296         }
5297         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5298                 req.rx_stat_host_addr =
5299                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5300                 req.rx_stat_size =
5301                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5302         }
5303         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5304
5305         if (rc) {
5306                 bp->fw_rx_port_stats_ext_size = 0;
5307                 bp->fw_tx_port_stats_ext_size = 0;
5308         } else {
5309                 bp->fw_rx_port_stats_ext_size =
5310                         rte_le_to_cpu_16(resp->rx_stat_size);
5311                 bp->fw_tx_port_stats_ext_size =
5312                         rte_le_to_cpu_16(resp->tx_stat_size);
5313         }
5314
5315         HWRM_CHECK_RESULT();
5316         HWRM_UNLOCK();
5317
5318         return rc;
5319 }
5320
5321 int
5322 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5323 {
5324         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5325         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5326                 bp->hwrm_cmd_resp_addr;
5327         int rc = 0;
5328
5329         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5330         req.tunnel_type = type;
5331         req.dest_fid = bp->fw_fid;
5332         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5333         HWRM_CHECK_RESULT();
5334
5335         HWRM_UNLOCK();
5336
5337         return rc;
5338 }
5339
5340 int
5341 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5342 {
5343         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5344         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5345                 bp->hwrm_cmd_resp_addr;
5346         int rc = 0;
5347
5348         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5349         req.tunnel_type = type;
5350         req.dest_fid = bp->fw_fid;
5351         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5352         HWRM_CHECK_RESULT();
5353
5354         HWRM_UNLOCK();
5355
5356         return rc;
5357 }
5358
5359 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5360 {
5361         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5362         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5363                 bp->hwrm_cmd_resp_addr;
5364         int rc = 0;
5365
5366         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5367         req.src_fid = bp->fw_fid;
5368         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5369         HWRM_CHECK_RESULT();
5370
5371         if (type)
5372                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5373
5374         HWRM_UNLOCK();
5375
5376         return rc;
5377 }
5378
5379 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5380                                    uint16_t *dst_fid)
5381 {
5382         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5383         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5384                 bp->hwrm_cmd_resp_addr;
5385         int rc = 0;
5386
5387         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5388         req.src_fid = bp->fw_fid;
5389         req.tunnel_type = tun_type;
5390         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5391         HWRM_CHECK_RESULT();
5392
5393         if (dst_fid)
5394                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5395
5396         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5397
5398         HWRM_UNLOCK();
5399
5400         return rc;
5401 }
5402
5403 int bnxt_hwrm_set_mac(struct bnxt *bp)
5404 {
5405         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5406         struct hwrm_func_vf_cfg_input req = {0};
5407         int rc = 0;
5408
5409         if (!BNXT_VF(bp))
5410                 return 0;
5411
5412         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5413
5414         req.enables =
5415                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5416         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5417
5418         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5419
5420         HWRM_CHECK_RESULT();
5421
5422         HWRM_UNLOCK();
5423
5424         return rc;
5425 }
5426
5427 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5428 {
5429         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5430         struct hwrm_func_drv_if_change_input req = {0};
5431         uint32_t flags;
5432         int rc;
5433
5434         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5435                 return 0;
5436
5437         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5438          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5439          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5440          */
5441         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5442                 return 0;
5443
5444         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5445
5446         if (up)
5447                 req.flags =
5448                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5449
5450         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5451
5452         HWRM_CHECK_RESULT();
5453         flags = rte_le_to_cpu_32(resp->flags);
5454         HWRM_UNLOCK();
5455
5456         if (!up)
5457                 return 0;
5458
5459         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5460                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5461                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5462         }
5463
5464         return 0;
5465 }
5466
5467 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5468 {
5469         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5470         struct bnxt_error_recovery_info *info = bp->recovery_info;
5471         struct hwrm_error_recovery_qcfg_input req = {0};
5472         uint32_t flags = 0;
5473         unsigned int i;
5474         int rc;
5475
5476         /* Older FW does not have error recovery support */
5477         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5478                 return 0;
5479
5480         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5481
5482         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5483
5484         HWRM_CHECK_RESULT();
5485
5486         flags = rte_le_to_cpu_32(resp->flags);
5487         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5488                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5489         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5490                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5491
5492         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5493             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5494                 rc = -EINVAL;
5495                 goto err;
5496         }
5497
5498         /* FW returned values are in units of 100msec */
5499         info->driver_polling_freq =
5500                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5501         info->master_func_wait_period =
5502                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5503         info->normal_func_wait_period =
5504                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5505         info->master_func_wait_period_after_reset =
5506                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5507         info->max_bailout_time_after_reset =
5508                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5509         info->status_regs[BNXT_FW_STATUS_REG] =
5510                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5511         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5512                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5513         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5514                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5515         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5516                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5517         info->reg_array_cnt =
5518                 rte_le_to_cpu_32(resp->reg_array_cnt);
5519
5520         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5521                 rc = -EINVAL;
5522                 goto err;
5523         }
5524
5525         for (i = 0; i < info->reg_array_cnt; i++) {
5526                 info->reset_reg[i] =
5527                         rte_le_to_cpu_32(resp->reset_reg[i]);
5528                 info->reset_reg_val[i] =
5529                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5530                 info->delay_after_reset[i] =
5531                         resp->delay_after_reset[i];
5532         }
5533 err:
5534         HWRM_UNLOCK();
5535
5536         /* Map the FW status registers */
5537         if (!rc)
5538                 rc = bnxt_map_fw_health_status_regs(bp);
5539
5540         if (rc) {
5541                 rte_free(bp->recovery_info);
5542                 bp->recovery_info = NULL;
5543         }
5544         return rc;
5545 }
5546
5547 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5548 {
5549         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5550         struct hwrm_fw_reset_input req = {0};
5551         int rc;
5552
5553         if (!BNXT_PF(bp))
5554                 return -EOPNOTSUPP;
5555
5556         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5557
5558         req.embedded_proc_type =
5559                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5560         req.selfrst_status =
5561                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5562         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5563
5564         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5565                                     BNXT_USE_KONG(bp));
5566
5567         HWRM_CHECK_RESULT();
5568         HWRM_UNLOCK();
5569
5570         return rc;
5571 }
5572
5573 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5574 {
5575         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5576         struct hwrm_port_ts_query_input req = {0};
5577         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5578         uint32_t flags = 0;
5579         int rc;
5580
5581         if (!ptp)
5582                 return 0;
5583
5584         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5585
5586         switch (path) {
5587         case BNXT_PTP_FLAGS_PATH_TX:
5588                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5589                 break;
5590         case BNXT_PTP_FLAGS_PATH_RX:
5591                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5592                 break;
5593         case BNXT_PTP_FLAGS_CURRENT_TIME:
5594                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5595                 break;
5596         }
5597
5598         req.flags = rte_cpu_to_le_32(flags);
5599         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5600
5601         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5602
5603         HWRM_CHECK_RESULT();
5604
5605         if (timestamp) {
5606                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5607                 *timestamp |=
5608                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5609         }
5610         HWRM_UNLOCK();
5611
5612         return rc;
5613 }
5614
5615 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5616 {
5617         int rc = 0;
5618
5619         struct hwrm_cfa_counter_qcaps_input req = {0};
5620         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5621
5622         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5623                 PMD_DRV_LOG(DEBUG,
5624                             "Not a PF or trusted VF. Command not supported\n");
5625                 return 0;
5626         }
5627
5628         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5629         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5630         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5631
5632         HWRM_CHECK_RESULT();
5633         if (max_fc)
5634                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5635         HWRM_UNLOCK();
5636
5637         return 0;
5638 }
5639
5640 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5641 {
5642         int rc = 0;
5643         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5644         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5645
5646         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5647                 PMD_DRV_LOG(DEBUG,
5648                             "Not a PF or trusted VF. Command not supported\n");
5649                 return 0;
5650         }
5651
5652         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5653
5654         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5655         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5656         req.page_dir = rte_cpu_to_le_64(dma_addr);
5657
5658         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5659
5660         HWRM_CHECK_RESULT();
5661         if (ctx_id) {
5662                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5663                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5664         }
5665         HWRM_UNLOCK();
5666
5667         return 0;
5668 }
5669
5670 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5671 {
5672         int rc = 0;
5673         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5674         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5675
5676         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5677                 PMD_DRV_LOG(DEBUG,
5678                             "Not a PF or trusted VF. Command not supported\n");
5679                 return 0;
5680         }
5681
5682         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5683
5684         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5685
5686         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5687
5688         HWRM_CHECK_RESULT();
5689         HWRM_UNLOCK();
5690
5691         return rc;
5692 }
5693
5694 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5695                               uint16_t cntr, uint16_t ctx_id,
5696                               uint32_t num_entries, bool enable)
5697 {
5698         struct hwrm_cfa_counter_cfg_input req = {0};
5699         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5700         uint16_t flags = 0;
5701         int rc;
5702
5703         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5704                 PMD_DRV_LOG(DEBUG,
5705                             "Not a PF or trusted VF. Command not supported\n");
5706                 return 0;
5707         }
5708
5709         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5710
5711         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5712         req.counter_type = rte_cpu_to_le_16(cntr);
5713         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5714                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5715         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5716         if (dir == BNXT_DIR_RX)
5717                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5718         else if (dir == BNXT_DIR_TX)
5719                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5720         req.flags = rte_cpu_to_le_16(flags);
5721         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5722         req.num_entries = rte_cpu_to_le_32(num_entries);
5723
5724         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5725         HWRM_CHECK_RESULT();
5726         HWRM_UNLOCK();
5727
5728         return 0;
5729 }
5730
5731 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5732                                  enum bnxt_flow_dir dir,
5733                                  uint16_t cntr,
5734                                  uint16_t num_entries)
5735 {
5736         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5737         struct hwrm_cfa_counter_qstats_input req = {0};
5738         uint16_t flow_ctx_id = 0;
5739         uint16_t flags = 0;
5740         int rc = 0;
5741
5742         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5743                 PMD_DRV_LOG(DEBUG,
5744                             "Not a PF or trusted VF. Command not supported\n");
5745                 return 0;
5746         }
5747
5748         if (dir == BNXT_DIR_RX) {
5749                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5750                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5751         } else if (dir == BNXT_DIR_TX) {
5752                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5753                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5754         }
5755
5756         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5757         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5758         req.counter_type = rte_cpu_to_le_16(cntr);
5759         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5760         req.num_entries = rte_cpu_to_le_16(num_entries);
5761         req.flags = rte_cpu_to_le_16(flags);
5762         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5763
5764         HWRM_CHECK_RESULT();
5765         HWRM_UNLOCK();
5766
5767         return 0;
5768 }
5769
5770 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5771                                 uint16_t *first_vf_id)
5772 {
5773         int rc = 0;
5774         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5775         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5776
5777         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5778
5779         req.fid = rte_cpu_to_le_16(fid);
5780
5781         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5782
5783         HWRM_CHECK_RESULT();
5784
5785         if (first_vf_id)
5786                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5787
5788         HWRM_UNLOCK();
5789
5790         return rc;
5791 }
5792
5793 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5794 {
5795         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5796         struct hwrm_cfa_pair_alloc_input req = {0};
5797         int rc;
5798
5799         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5800                 PMD_DRV_LOG(DEBUG,
5801                             "Not a PF or trusted VF. Command not supported\n");
5802                 return 0;
5803         }
5804
5805         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5806         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5807         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5808                  bp->eth_dev->data->name, rep_bp->vf_id);
5809
5810         req.pf_b_id = rep_bp->parent_pf_idx;
5811         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5812                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5813         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5814         req.host_b_id = 1; /* TBD - Confirm if this is OK */
5815
5816         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5817                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5818         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5819                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5820         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5821                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5822         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5823                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5824
5825         req.q_ab = rep_bp->rep_q_r2f;
5826         req.q_ba = rep_bp->rep_q_f2r;
5827         req.fc_ab = rep_bp->rep_fc_r2f;
5828         req.fc_ba = rep_bp->rep_fc_f2r;
5829
5830         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5831         HWRM_CHECK_RESULT();
5832
5833         HWRM_UNLOCK();
5834         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5835                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5836         return rc;
5837 }
5838
5839 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5840 {
5841         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5842         struct hwrm_cfa_pair_free_input req = {0};
5843         int rc;
5844
5845         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5846                 PMD_DRV_LOG(DEBUG,
5847                             "Not a PF or trusted VF. Command not supported\n");
5848                 return 0;
5849         }
5850
5851         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5852         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5853                  bp->eth_dev->data->name, rep_bp->vf_id);
5854         req.pf_b_id = rep_bp->parent_pf_idx;
5855         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5856         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5857                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5858         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5859         HWRM_CHECK_RESULT();
5860         HWRM_UNLOCK();
5861         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
5862                     rep_bp->vf_id);
5863         return rc;
5864 }
5865
5866 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5867 {
5868         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5869                                         bp->hwrm_cmd_resp_addr;
5870         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5871         uint32_t flags = 0;
5872         int rc = 0;
5873
5874         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5875                 return 0;
5876
5877         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5878                 PMD_DRV_LOG(DEBUG,
5879                             "Not a PF or trusted VF. Command not supported\n");
5880                 return 0;
5881         }
5882
5883         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
5884         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5885
5886         HWRM_CHECK_RESULT();
5887         flags = rte_le_to_cpu_32(resp->flags);
5888         HWRM_UNLOCK();
5889
5890         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
5891                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
5892         else
5893                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
5894
5895         return rc;
5896 }
5897
5898 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
5899                             uint32_t echo_req_data2)
5900 {
5901         struct hwrm_func_echo_response_input req = {0};
5902         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
5903         int rc;
5904
5905         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
5906         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
5907         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
5908
5909         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5910
5911         HWRM_CHECK_RESULT();
5912         HWRM_UNLOCK();
5913
5914         return rc;
5915 }