1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
30 #define HWRM_VERSION_1_10_2_13 0x10a020d
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(int) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages == 0)
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
78 static struct bnxt_cp_ring_info*
79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
81 struct bnxt_cp_ring_info *cp_ring = NULL;
85 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
86 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
88 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
89 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
91 if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
92 rte_cpu_to_le_16(rid)) {
97 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
98 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
99 struct bnxt_tx_queue *txq = bp->tx_queues[i];
101 if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
102 rte_cpu_to_le_16(rid)) {
113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
114 * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
115 * before timeout, we force the done bit for the cleanup to proceed.
116 * Also if cpr is null, do nothing.. The HWRM command is not for a
117 * Tx/Rx/AGG ring cleanup.
120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
121 bool tx, bool rx, bool timeout)
127 done = bnxt_flush_tx_cmp(cpr);
130 done = bnxt_flush_rx_cmp(cpr);
133 PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
136 /* We are about to timeout and still haven't seen the
137 * HWRM done for the Ring free. Force the cleanup.
139 if (!done && timeout) {
141 PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
145 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
146 * Otherwise the cpr would have been valid. So do nothing.
155 * HWRM Functions (sent to HWRM)
156 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
157 * HWRM command times out, or a negative error code if the HWRM
158 * command was failed by the FW.
161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
162 uint32_t msg_len, bool use_kong_mb)
165 struct input *req = msg;
166 struct output *resp = bp->hwrm_cmd_resp_addr;
167 uint32_t *data = msg;
170 uint16_t max_req_len = bp->max_req_len;
171 struct hwrm_short_input short_input = { 0 };
172 uint16_t bar_offset = use_kong_mb ?
173 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
174 uint16_t mb_trigger_offset = use_kong_mb ?
175 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
176 struct bnxt_cp_ring_info *cpr = NULL;
181 /* Do not send HWRM commands to firmware in error state */
182 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
185 timeout = bp->hwrm_cmd_timeout;
187 /* Update the message length for backing store config for new FW. */
188 if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
189 rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
190 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
192 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
193 msg_len > bp->max_req_len) {
194 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
196 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
197 memcpy(short_cmd_req, req, msg_len);
199 short_input.req_type = rte_cpu_to_le_16(req->req_type);
200 short_input.signature = rte_cpu_to_le_16(
201 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
202 short_input.size = rte_cpu_to_le_16(msg_len);
203 short_input.req_addr =
204 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
206 data = (uint32_t *)&short_input;
207 msg_len = sizeof(short_input);
209 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
212 /* Write request msg to hwrm channel */
213 for (i = 0; i < msg_len; i += 4) {
214 bar = (uint8_t *)bp->bar0 + bar_offset + i;
215 rte_write32(*data, bar);
219 /* Zero the rest of the request space */
220 for (; i < max_req_len; i += 4) {
221 bar = (uint8_t *)bp->bar0 + bar_offset + i;
225 /* Ring channel doorbell */
226 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
229 * Make sure the channel doorbell ring command complete before
230 * reading the response to avoid getting stale or invalid
235 /* Check ring flush is done.
236 * This is valid only for Tx and Rx rings (including AGG rings).
237 * The Tx and Rx rings should be freed once the HW confirms all
238 * the internal buffers and BDs associated with the rings are
239 * consumed and the corresponding DMA is handled.
241 if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
242 /* Check if the TxCQ matches. If that fails check if RxCQ
243 * matches. And if neither match, is_rx = false, is_tx = false.
245 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
246 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
248 /* Not a TxCQ. Check if the RxCQ matches. */
250 bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
251 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
259 /* Poll for the valid bit */
260 for (i = 0; i < timeout; i++) {
263 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
265 /* Sanity check on the resp->resp_len */
267 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
268 /* Last byte of resp contains the valid key */
269 valid = (uint8_t *)resp + resp->resp_len - 1;
270 if (*valid == HWRM_RESP_VALID_KEY && done)
277 /* Suppress VER_GET timeout messages during reset recovery */
278 if (bp->flags & BNXT_FLAG_FW_RESET &&
279 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
283 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
284 req->req_type, req->seq_id);
291 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
292 * spinlock, and does initial processing.
294 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
295 * releases the spinlock only if it returns. If the regular int return codes
296 * are not used by the function, HWRM_CHECK_RESULT() should not be used
297 * directly, rather it should be copied and modified to suit the function.
299 * HWRM_UNLOCK() must be called after all response processing is completed.
301 #define HWRM_PREP(req, type, kong) do { \
302 rte_spinlock_lock(&bp->hwrm_lock); \
303 if (bp->hwrm_cmd_resp_addr == NULL) { \
304 rte_spinlock_unlock(&bp->hwrm_lock); \
307 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
308 (req)->req_type = rte_cpu_to_le_16(type); \
309 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
310 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
311 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
312 (req)->target_id = rte_cpu_to_le_16(0xffff); \
313 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
316 #define HWRM_CHECK_RESULT_SILENT() do {\
318 rte_spinlock_unlock(&bp->hwrm_lock); \
321 if (resp->error_code) { \
322 rc = rte_le_to_cpu_16(resp->error_code); \
323 rte_spinlock_unlock(&bp->hwrm_lock); \
328 #define HWRM_CHECK_RESULT() do {\
330 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
331 rte_spinlock_unlock(&bp->hwrm_lock); \
332 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
334 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
336 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
338 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
340 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
346 if (resp->error_code) { \
347 rc = rte_le_to_cpu_16(resp->error_code); \
348 if (resp->resp_len >= 16) { \
349 struct hwrm_err_output *tmp_hwrm_err_op = \
352 "error %d:%d:%08x:%04x\n", \
353 rc, tmp_hwrm_err_op->cmd_err, \
355 tmp_hwrm_err_op->opaque_0), \
357 tmp_hwrm_err_op->opaque_1)); \
359 PMD_DRV_LOG(ERR, "error %d\n", rc); \
361 rte_spinlock_unlock(&bp->hwrm_lock); \
362 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
364 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
366 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
368 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
370 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
378 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
389 bool mailbox = BNXT_USE_CHIMP_MB;
390 struct input *req = msg;
391 struct output *resp = bp->hwrm_cmd_resp_addr;
394 mailbox = BNXT_USE_KONG(bp);
396 HWRM_PREP(req, msg_type, mailbox);
398 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
403 memcpy(resp_msg, resp, resp_len);
410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
414 uint32_t *tf_response_code,
418 uint32_t response_len)
421 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
422 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
423 bool mailbox = BNXT_USE_CHIMP_MB;
425 if (msg_len > sizeof(req.tf_req))
429 mailbox = BNXT_USE_KONG(bp);
431 HWRM_PREP(&req, HWRM_TF, mailbox);
432 /* Build request using the user supplied request payload.
433 * TLV request size is checked at build time against HWRM
434 * request max size, thus no checking required.
436 req.tf_type = tf_type;
437 req.tf_subtype = tf_subtype;
438 memcpy(req.tf_req, msg, msg_len);
440 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
443 /* Copy the resp to user provided response buffer */
444 if (response != NULL)
445 /* Post process response data. We need to copy only
446 * the 'payload' as the HWRM data structure really is
447 * HWRM header + msg header + payload and the TFLIB
448 * only provided a payload place holder.
450 if (response_len != 0) {
456 /* Extract the internal tflib response code */
457 *tf_response_code = resp->tf_resp_code;
463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
466 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
467 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
469 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
470 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
473 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
482 struct bnxt_vnic_info *vnic,
484 struct bnxt_vlan_table_entry *vlan_table)
487 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
488 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
491 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
494 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
495 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
497 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
498 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
499 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
500 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
502 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
503 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
505 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
506 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
507 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
508 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
509 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
510 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
513 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
514 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
515 req.vlan_tag_tbl_addr =
516 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
517 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
519 req.mask = rte_cpu_to_le_32(mask);
521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
531 struct bnxt_vlan_antispoof_table_entry *vlan_table)
534 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
535 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
536 bp->hwrm_cmd_resp_addr;
539 * Older HWRM versions did not support this command, and the set_rx_mask
540 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
541 * removed from set_rx_mask call, and this command was added.
543 * This command is also present from 1.7.8.11 and higher,
546 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
547 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
548 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
553 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
554 req.fid = rte_cpu_to_le_16(fid);
556 req.vlan_tag_mask_tbl_addr =
557 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
558 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
569 struct bnxt_filter_info *filter)
572 struct bnxt_filter_info *l2_filter = filter;
573 struct bnxt_vnic_info *vnic = NULL;
574 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
575 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
577 if (filter->fw_l2_filter_id == UINT64_MAX)
580 if (filter->matching_l2_fltr_ptr)
581 l2_filter = filter->matching_l2_fltr_ptr;
583 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
584 filter, l2_filter, l2_filter->l2_ref_cnt);
586 if (l2_filter->l2_ref_cnt == 0)
589 if (l2_filter->l2_ref_cnt > 0)
590 l2_filter->l2_ref_cnt--;
592 if (l2_filter->l2_ref_cnt > 0)
595 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
597 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
599 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
604 filter->fw_l2_filter_id = UINT64_MAX;
605 if (l2_filter->l2_ref_cnt == 0) {
606 vnic = l2_filter->vnic;
608 STAILQ_REMOVE(&vnic->filter, l2_filter,
609 bnxt_filter_info, next);
610 bnxt_free_filter(bp, l2_filter);
617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
619 struct bnxt_filter_info *filter)
622 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
623 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
624 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
625 const struct rte_eth_vmdq_rx_conf *conf =
626 &dev_conf->rx_adv_conf.vmdq_rx_conf;
627 uint32_t enables = 0;
628 uint16_t j = dst_id - 1;
630 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
631 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
632 conf->pool_map[j].pools & (1UL << j)) {
634 "Add vlan %u to vmdq pool %u\n",
635 conf->pool_map[j].vlan_id, j);
637 filter->l2_ivlan = conf->pool_map[j].vlan_id;
639 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
640 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
643 if (filter->fw_l2_filter_id != UINT64_MAX)
644 bnxt_hwrm_clear_l2_filter(bp, filter);
646 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
648 /* PMD does not support XDP and RoCE */
649 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
650 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
651 req.flags = rte_cpu_to_le_32(filter->flags);
653 enables = filter->enables |
654 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
655 req.dst_id = rte_cpu_to_le_16(dst_id);
658 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
659 memcpy(req.l2_addr, filter->l2_addr,
662 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
663 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
666 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
667 req.l2_ovlan = filter->l2_ovlan;
669 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
670 req.l2_ivlan = filter->l2_ivlan;
672 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
673 req.l2_ovlan_mask = filter->l2_ovlan_mask;
675 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
676 req.l2_ivlan_mask = filter->l2_ivlan_mask;
677 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
678 req.src_id = rte_cpu_to_le_32(filter->src_id);
679 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
680 req.src_type = filter->src_type;
681 if (filter->pri_hint) {
682 req.pri_hint = filter->pri_hint;
683 req.l2_filter_id_hint =
684 rte_cpu_to_le_64(filter->l2_filter_id_hint);
687 req.enables = rte_cpu_to_le_32(enables);
689 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
693 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
694 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
697 filter->l2_ref_cnt++;
702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
704 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
705 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
712 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
715 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
718 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
719 if (ptp->tx_tstamp_en)
720 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
723 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
724 req.flags = rte_cpu_to_le_32(flags);
725 req.enables = rte_cpu_to_le_32
726 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
727 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
729 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
738 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
739 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
740 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
745 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
747 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
749 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
753 if (!BNXT_CHIP_P5(bp) &&
754 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
757 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
758 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
760 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
764 if (!BNXT_CHIP_P5(bp)) {
765 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
766 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
767 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
768 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
769 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
770 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
771 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
772 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
773 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
774 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
775 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
776 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
777 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
778 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
779 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
780 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
781 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
782 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
791 void bnxt_free_vf_info(struct bnxt *bp)
798 if (bp->pf->vf_info == NULL)
801 for (i = 0; i < bp->pf->max_vfs; i++) {
802 rte_free(bp->pf->vf_info[i].vlan_table);
803 bp->pf->vf_info[i].vlan_table = NULL;
804 rte_free(bp->pf->vf_info[i].vlan_as_table);
805 bp->pf->vf_info[i].vlan_as_table = NULL;
807 rte_free(bp->pf->vf_info);
808 bp->pf->vf_info = NULL;
811 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
813 struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
817 bnxt_free_vf_info(bp);
819 vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
820 if (vf_info == NULL) {
821 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
825 bp->pf->max_vfs = max_vfs;
826 for (i = 0; i < max_vfs; i++) {
827 vf_info[i].fid = bp->pf->first_vf_id + i;
828 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
829 getpagesize(), getpagesize());
830 if (vf_info[i].vlan_table == NULL) {
831 PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
834 rte_mem_lock_page(vf_info[i].vlan_table);
836 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
837 getpagesize(), getpagesize());
838 if (vf_info[i].vlan_as_table == NULL) {
839 PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
842 rte_mem_lock_page(vf_info[i].vlan_as_table);
844 STAILQ_INIT(&vf_info[i].filter);
847 bp->pf->vf_info = vf_info;
851 bnxt_free_vf_info(bp);
855 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
858 struct hwrm_func_qcaps_input req = {.req_type = 0 };
859 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
860 uint16_t new_max_vfs;
863 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
865 req.fid = rte_cpu_to_le_16(0xffff);
867 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
871 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
872 flags = rte_le_to_cpu_32(resp->flags);
874 bp->pf->port_id = resp->port_id;
875 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
876 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
877 new_max_vfs = bp->pdev->max_vfs;
878 if (new_max_vfs != bp->pf->max_vfs) {
879 rc = bnxt_alloc_vf_info(bp, new_max_vfs);
885 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
886 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
887 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
888 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
890 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
892 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
893 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
894 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
895 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
896 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
897 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
898 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
899 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
900 bp->max_l2_ctx += bp->max_rx_em_flows;
901 /* TODO: For now, do not support VMDq/RFS on VFs. */
906 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
910 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
911 bp->max_l2_ctx, bp->max_vnics);
912 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
914 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
915 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
916 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
917 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
919 bnxt_hwrm_ptp_qcfg(bp);
923 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
924 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
926 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
927 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
928 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
931 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
932 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
934 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
935 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
937 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
938 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
946 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
950 rc = __bnxt_hwrm_func_qcaps(bp);
954 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
955 rc = bnxt_alloc_ctx_mem(bp);
960 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
961 * But the error can be ignored. Return success.
963 rc = bnxt_hwrm_func_resc_qcaps(bp);
965 bp->flags |= BNXT_FLAG_NEW_RM;
971 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
972 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
976 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
977 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
979 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
981 req.target_id = rte_cpu_to_le_16(0xffff);
983 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
987 flags = rte_le_to_cpu_32(resp->flags);
989 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
990 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
991 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
994 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
995 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
997 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
998 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1000 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1007 int bnxt_hwrm_func_reset(struct bnxt *bp)
1010 struct hwrm_func_reset_input req = {.req_type = 0 };
1011 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1013 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1015 req.enables = rte_cpu_to_le_32(0);
1017 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1019 HWRM_CHECK_RESULT();
1025 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1029 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1030 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1032 if (bp->flags & BNXT_FLAG_REGISTERED)
1035 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1036 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1037 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1038 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1040 /* PFs and trusted VFs should indicate the support of the
1041 * Master capability on non Stingray platform
1043 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1044 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1046 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1047 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1048 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1049 req.ver_maj = RTE_VER_YEAR;
1050 req.ver_min = RTE_VER_MONTH;
1051 req.ver_upd = RTE_VER_MINOR;
1054 req.enables |= rte_cpu_to_le_32(
1055 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1056 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1057 RTE_MIN(sizeof(req.vf_req_fwd),
1058 sizeof(bp->pf->vf_req_fwd)));
1061 req.flags = rte_cpu_to_le_32(flags);
1063 req.async_event_fwd[0] |=
1064 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1065 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1066 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1067 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1068 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1069 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1070 req.async_event_fwd[0] |=
1071 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1072 req.async_event_fwd[1] |=
1073 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1074 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1076 req.async_event_fwd[1] |=
1077 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1079 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1080 req.async_event_fwd[1] |=
1081 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1083 req.async_event_fwd[2] |=
1084 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
1086 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1088 HWRM_CHECK_RESULT();
1090 flags = rte_le_to_cpu_32(resp->flags);
1091 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1092 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1096 bp->flags |= BNXT_FLAG_REGISTERED;
1101 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1103 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1106 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1109 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1114 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1115 struct hwrm_func_vf_cfg_input req = {0};
1117 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1119 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1120 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1121 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1122 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1123 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1125 if (BNXT_HAS_RING_GRPS(bp)) {
1126 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1127 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1130 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1131 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1132 AGG_RING_MULTIPLIER);
1133 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1134 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1136 BNXT_NUM_ASYNC_CPR(bp));
1137 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1138 if (bp->vf_resv_strategy ==
1139 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1140 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1141 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1142 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1143 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1144 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1145 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1146 } else if (bp->vf_resv_strategy ==
1147 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1148 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1149 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1153 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1154 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1155 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1156 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1157 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1158 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1160 if (test && BNXT_HAS_RING_GRPS(bp))
1161 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1163 req.flags = rte_cpu_to_le_32(flags);
1164 req.enables |= rte_cpu_to_le_32(enables);
1166 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1169 HWRM_CHECK_RESULT_SILENT();
1171 HWRM_CHECK_RESULT();
1177 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1180 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1181 struct hwrm_func_resource_qcaps_input req = {0};
1183 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1184 req.fid = rte_cpu_to_le_16(0xffff);
1186 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1188 HWRM_CHECK_RESULT_SILENT();
1190 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1191 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1192 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1193 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1194 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1195 /* func_resource_qcaps does not return max_rx_em_flows.
1196 * So use the value provided by func_qcaps.
1198 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1199 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1200 bp->max_l2_ctx += bp->max_rx_em_flows;
1201 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1202 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1203 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1204 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1205 if (bp->vf_resv_strategy >
1206 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1207 bp->vf_resv_strategy =
1208 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1214 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1217 struct hwrm_ver_get_input req = {.req_type = 0 };
1218 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1219 uint32_t fw_version;
1220 uint16_t max_resp_len;
1221 char type[RTE_MEMZONE_NAMESIZE];
1222 uint32_t dev_caps_cfg;
1224 bp->max_req_len = HWRM_MAX_REQ_LEN;
1225 bp->hwrm_cmd_timeout = timeout;
1226 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1228 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1229 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1230 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1232 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1234 if (bp->flags & BNXT_FLAG_FW_RESET)
1235 HWRM_CHECK_RESULT_SILENT();
1237 HWRM_CHECK_RESULT();
1239 if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1244 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1245 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1246 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1247 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1248 resp->hwrm_fw_rsvd_8b);
1249 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1250 (resp->hwrm_fw_min_8b << 16) |
1251 (resp->hwrm_fw_bld_8b << 8) |
1252 resp->hwrm_fw_rsvd_8b;
1253 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1254 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1256 fw_version = resp->hwrm_intf_maj_8b << 16;
1257 fw_version |= resp->hwrm_intf_min_8b << 8;
1258 fw_version |= resp->hwrm_intf_upd_8b;
1259 bp->hwrm_spec_code = fw_version;
1261 /* def_req_timeout value is in milliseconds */
1262 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1263 /* convert timeout to usec */
1264 bp->hwrm_cmd_timeout *= 1000;
1265 if (!bp->hwrm_cmd_timeout)
1266 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1268 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1269 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1274 if (bp->max_req_len > resp->max_req_win_len) {
1275 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1280 bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1282 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1283 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1284 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1285 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1287 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1288 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1290 RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1291 bp->max_resp_len = max_resp_len;
1294 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1296 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1297 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1298 bp->flags |= BNXT_FLAG_SHORT_CMD;
1301 if (((dev_caps_cfg &
1302 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1304 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1305 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1306 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1307 bp->pdev->addr.domain, bp->pdev->addr.bus,
1308 bp->pdev->addr.devid, bp->pdev->addr.function);
1310 rte_free(bp->hwrm_short_cmd_req_addr);
1312 bp->hwrm_short_cmd_req_addr =
1313 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1314 if (bp->hwrm_short_cmd_req_addr == NULL) {
1318 bp->hwrm_short_cmd_req_dma_addr =
1319 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1320 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1321 rte_free(bp->hwrm_short_cmd_req_addr);
1323 "Unable to map buffer to physical memory.\n");
1329 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1330 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1331 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1334 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1335 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1337 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1338 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1339 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1343 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1344 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1345 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1353 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1356 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1357 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1359 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1362 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1365 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1367 HWRM_CHECK_RESULT();
1370 PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1371 bp->eth_dev->data->port_id);
1376 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1379 struct hwrm_port_phy_cfg_input req = {0};
1380 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1381 uint32_t enables = 0;
1383 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1385 if (conf->link_up) {
1386 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1387 if (bp->link_info->auto_mode && conf->link_speed) {
1388 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1389 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1392 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1394 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1395 * any auto mode, even "none".
1397 if (!conf->link_speed) {
1398 /* No speeds specified. Enable AutoNeg - all speeds */
1399 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1401 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1403 if (bp->link_info->link_signal_mode) {
1405 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1406 req.force_pam4_link_speed =
1407 rte_cpu_to_le_16(conf->link_speed);
1409 req.force_link_speed =
1410 rte_cpu_to_le_16(conf->link_speed);
1413 /* AutoNeg - Advertise speeds specified. */
1414 if (conf->auto_link_speed_mask &&
1415 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1417 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1418 req.auto_link_speed_mask =
1419 conf->auto_link_speed_mask;
1420 if (conf->auto_pam4_link_speeds) {
1422 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1423 req.auto_link_pam4_speed_mask =
1424 conf->auto_pam4_link_speeds;
1427 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1430 if (conf->auto_link_speed &&
1431 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1433 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1435 req.auto_duplex = conf->duplex;
1436 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1437 req.auto_pause = conf->auto_pause;
1438 req.force_pause = conf->force_pause;
1439 /* Set force_pause if there is no auto or if there is a force */
1440 if (req.auto_pause && !req.force_pause)
1441 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1443 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1445 req.enables = rte_cpu_to_le_32(enables);
1448 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1449 PMD_DRV_LOG(INFO, "Force Link Down\n");
1452 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1454 HWRM_CHECK_RESULT();
1460 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1461 struct bnxt_link_info *link_info)
1464 struct hwrm_port_phy_qcfg_input req = {0};
1465 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1467 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1469 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1471 HWRM_CHECK_RESULT();
1473 link_info->phy_link_status = resp->link;
1474 link_info->link_up =
1475 (link_info->phy_link_status ==
1476 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1477 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1478 link_info->duplex = resp->duplex_cfg;
1479 link_info->pause = resp->pause;
1480 link_info->auto_pause = resp->auto_pause;
1481 link_info->force_pause = resp->force_pause;
1482 link_info->auto_mode = resp->auto_mode;
1483 link_info->phy_type = resp->phy_type;
1484 link_info->media_type = resp->media_type;
1486 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1487 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1488 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1489 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1490 link_info->phy_ver[0] = resp->phy_maj;
1491 link_info->phy_ver[1] = resp->phy_min;
1492 link_info->phy_ver[2] = resp->phy_bld;
1493 link_info->link_signal_mode =
1494 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1495 link_info->force_pam4_link_speed =
1496 rte_le_to_cpu_16(resp->force_pam4_link_speed);
1497 link_info->support_pam4_speeds =
1498 rte_le_to_cpu_16(resp->support_pam4_speeds);
1499 link_info->auto_pam4_link_speeds =
1500 rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1503 PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1504 link_info->link_speed, link_info->auto_mode,
1505 link_info->auto_link_speed, link_info->auto_link_speed_mask,
1506 link_info->support_speeds, link_info->force_link_speed);
1507 PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1508 link_info->link_signal_mode,
1509 link_info->auto_pam4_link_speeds,
1510 link_info->support_pam4_speeds,
1511 link_info->force_pam4_link_speed);
1515 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1518 struct hwrm_port_phy_qcaps_input req = {0};
1519 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1520 struct bnxt_link_info *link_info = bp->link_info;
1522 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1525 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1527 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1529 HWRM_CHECK_RESULT_SILENT();
1531 bp->port_cnt = resp->port_cnt;
1532 if (resp->supported_speeds_auto_mode)
1533 link_info->support_auto_speeds =
1534 rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1535 if (resp->supported_pam4_speeds_auto_mode)
1536 link_info->support_pam4_auto_speeds =
1537 rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1544 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1548 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1549 if (bp->tx_cos_queue[i].profile ==
1550 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1551 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1558 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1562 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1563 if (bp->tx_cos_queue[i].profile !=
1564 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1565 bp->tx_cos_queue[i].id !=
1566 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1567 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1573 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1576 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1577 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1578 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1582 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1584 req.flags = rte_cpu_to_le_32(dir);
1585 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1586 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1587 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1589 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1590 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1592 HWRM_CHECK_RESULT();
1594 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1595 GET_TX_QUEUE_INFO(0);
1596 GET_TX_QUEUE_INFO(1);
1597 GET_TX_QUEUE_INFO(2);
1598 GET_TX_QUEUE_INFO(3);
1599 GET_TX_QUEUE_INFO(4);
1600 GET_TX_QUEUE_INFO(5);
1601 GET_TX_QUEUE_INFO(6);
1602 GET_TX_QUEUE_INFO(7);
1604 GET_RX_QUEUE_INFO(0);
1605 GET_RX_QUEUE_INFO(1);
1606 GET_RX_QUEUE_INFO(2);
1607 GET_RX_QUEUE_INFO(3);
1608 GET_RX_QUEUE_INFO(4);
1609 GET_RX_QUEUE_INFO(5);
1610 GET_RX_QUEUE_INFO(6);
1611 GET_RX_QUEUE_INFO(7);
1616 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1619 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1620 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1624 /* iterate and find the COSq profile to use for Tx */
1625 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1626 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1627 if (bp->tx_cos_queue[i].id != 0xff)
1628 bp->tx_cosq_id[j++] =
1629 bp->tx_cos_queue[i].id;
1632 /* When CoS classification is disabled, for normal NIC
1633 * operations, ideally we should look to use LOSSY.
1634 * If not found, fallback to the first valid profile
1636 if (!bnxt_find_lossy_profile(bp))
1637 bnxt_find_first_valid_profile(bp);
1642 bp->max_tc = resp->max_configurable_queues;
1643 bp->max_lltc = resp->max_configurable_lossless_queues;
1644 if (bp->max_tc > BNXT_MAX_QUEUE)
1645 bp->max_tc = BNXT_MAX_QUEUE;
1646 bp->max_q = bp->max_tc;
1648 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1649 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1657 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1658 struct bnxt_ring *ring,
1659 uint32_t ring_type, uint32_t map_index,
1660 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1661 uint16_t tx_cosq_id)
1664 uint32_t enables = 0;
1665 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1666 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1667 struct rte_mempool *mb_pool;
1668 uint16_t rx_buf_size;
1670 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1672 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1673 req.fbo = rte_cpu_to_le_32(0);
1674 /* Association of ring index with doorbell index */
1675 req.logical_id = rte_cpu_to_le_16(map_index);
1676 req.length = rte_cpu_to_le_32(ring->ring_size);
1678 switch (ring_type) {
1679 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1680 req.ring_type = ring_type;
1681 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1682 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1683 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1684 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1686 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1688 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1689 req.ring_type = ring_type;
1690 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1691 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1692 if (BNXT_CHIP_P5(bp)) {
1693 mb_pool = bp->rx_queues[0]->mb_pool;
1694 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1695 RTE_PKTMBUF_HEADROOM;
1696 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1697 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1699 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1701 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1703 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1705 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1706 req.ring_type = ring_type;
1707 if (BNXT_HAS_NQ(bp)) {
1708 /* Association of cp ring with nq */
1709 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1711 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1713 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1715 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1716 req.ring_type = ring_type;
1717 req.page_size = BNXT_PAGE_SHFT;
1718 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1720 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1721 req.ring_type = ring_type;
1722 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1724 mb_pool = bp->rx_queues[0]->mb_pool;
1725 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1726 RTE_PKTMBUF_HEADROOM;
1727 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1728 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1730 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1731 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1732 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1733 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1736 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1741 req.enables = rte_cpu_to_le_32(enables);
1743 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1745 if (rc || resp->error_code) {
1746 if (rc == 0 && resp->error_code)
1747 rc = rte_le_to_cpu_16(resp->error_code);
1748 switch (ring_type) {
1749 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1751 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1754 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1756 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1759 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1761 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1765 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1767 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1770 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1772 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1776 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1782 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1787 int bnxt_hwrm_ring_free(struct bnxt *bp,
1788 struct bnxt_ring *ring, uint32_t ring_type,
1789 uint16_t cp_ring_id)
1792 struct hwrm_ring_free_input req = {.req_type = 0 };
1793 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1795 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1797 req.ring_type = ring_type;
1798 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1799 req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1801 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1803 if (rc || resp->error_code) {
1804 if (rc == 0 && resp->error_code)
1805 rc = rte_le_to_cpu_16(resp->error_code);
1808 switch (ring_type) {
1809 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1810 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1813 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1814 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1817 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1818 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1821 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1823 "hwrm_ring_free nq failed. rc:%d\n", rc);
1825 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1827 "hwrm_ring_free agg failed. rc:%d\n", rc);
1830 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1838 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1841 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1842 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1844 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1846 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1847 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1848 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1849 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1853 HWRM_CHECK_RESULT();
1855 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1862 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1865 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1866 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1868 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1870 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1872 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1874 HWRM_CHECK_RESULT();
1877 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1881 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1884 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1885 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1887 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1890 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1892 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1894 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1896 HWRM_CHECK_RESULT();
1902 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1905 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1906 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1908 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1910 req.update_period_ms = rte_cpu_to_le_32(0);
1912 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1914 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1916 HWRM_CHECK_RESULT();
1918 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1925 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1928 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1929 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1931 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1933 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1935 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1937 HWRM_CHECK_RESULT();
1943 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1946 struct hwrm_vnic_alloc_input req = { 0 };
1947 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1949 if (!BNXT_HAS_RING_GRPS(bp))
1950 goto skip_ring_grps;
1952 /* map ring groups to this vnic */
1953 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1954 vnic->start_grp_id, vnic->end_grp_id);
1955 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1956 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1958 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1959 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1960 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1961 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1964 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1965 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1967 if (vnic->func_default)
1969 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1970 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1972 HWRM_CHECK_RESULT();
1974 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1976 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1980 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1981 struct bnxt_vnic_info *vnic,
1982 struct bnxt_plcmodes_cfg *pmode)
1985 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1986 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1988 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1990 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1992 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1994 HWRM_CHECK_RESULT();
1996 pmode->flags = rte_le_to_cpu_32(resp->flags);
1997 /* dflt_vnic bit doesn't exist in the _cfg command */
1998 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1999 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2000 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2001 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2008 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2009 struct bnxt_vnic_info *vnic,
2010 struct bnxt_plcmodes_cfg *pmode)
2013 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2014 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2016 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2017 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2021 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2023 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2024 req.flags = rte_cpu_to_le_32(pmode->flags);
2025 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2026 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2027 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2028 req.enables = rte_cpu_to_le_32(
2029 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2030 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2031 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2034 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2036 HWRM_CHECK_RESULT();
2042 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2045 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2046 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2047 struct bnxt_plcmodes_cfg pmodes = { 0 };
2048 uint32_t ctx_enable_flag = 0;
2049 uint32_t enables = 0;
2051 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2052 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2056 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2060 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2062 if (BNXT_CHIP_P5(bp)) {
2063 int dflt_rxq = vnic->start_grp_id;
2064 struct bnxt_rx_ring_info *rxr;
2065 struct bnxt_cp_ring_info *cpr;
2066 struct bnxt_rx_queue *rxq;
2070 * The first active receive ring is used as the VNIC
2071 * default receive ring. If there are no active receive
2072 * rings (all corresponding receive queues are stopped),
2073 * the first receive ring is used.
2075 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2076 rxq = bp->eth_dev->data->rx_queues[i];
2077 if (rxq->rx_started) {
2083 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2087 req.default_rx_ring_id =
2088 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2089 req.default_cmpl_ring_id =
2090 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2091 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2092 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2093 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2094 enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2095 req.rx_csum_v2_mode =
2096 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2101 /* Only RSS support for now TBD: COS & LB */
2102 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2103 if (vnic->lb_rule != 0xffff)
2104 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2105 if (vnic->cos_rule != 0xffff)
2106 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2107 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2108 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2109 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2111 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2112 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2113 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2116 enables |= ctx_enable_flag;
2117 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2118 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2119 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2120 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2123 req.enables = rte_cpu_to_le_32(enables);
2124 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2125 req.mru = rte_cpu_to_le_16(vnic->mru);
2126 /* Configure default VNIC only once. */
2127 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2129 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2130 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2132 if (vnic->vlan_strip)
2134 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2137 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2138 if (vnic->rss_dflt_cr)
2139 req.flags |= rte_cpu_to_le_32(
2140 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2142 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2144 HWRM_CHECK_RESULT();
2147 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2152 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2156 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2157 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2159 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2160 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2163 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2166 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2167 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2168 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2170 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2172 HWRM_CHECK_RESULT();
2174 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2175 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2176 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2177 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2178 vnic->mru = rte_le_to_cpu_16(resp->mru);
2179 vnic->func_default = rte_le_to_cpu_32(
2180 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2181 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2182 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2183 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2184 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2185 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2186 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2193 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2194 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2198 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2199 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2200 bp->hwrm_cmd_resp_addr;
2202 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2204 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2205 HWRM_CHECK_RESULT();
2207 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2208 if (!BNXT_HAS_RING_GRPS(bp))
2209 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2210 else if (ctx_idx == 0)
2211 vnic->rss_rule = ctx_id;
2219 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2220 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2223 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2224 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2225 bp->hwrm_cmd_resp_addr;
2227 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2228 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2231 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2233 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2235 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2237 HWRM_CHECK_RESULT();
2243 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2247 if (BNXT_CHIP_P5(bp)) {
2250 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2251 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2253 vnic->fw_grp_ids[j]);
2254 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2256 vnic->num_lb_ctxts = 0;
2258 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2259 vnic->rss_rule = INVALID_HW_RING_ID;
2265 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2268 struct hwrm_vnic_free_input req = {.req_type = 0 };
2269 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2271 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2272 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2276 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2278 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2280 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2282 HWRM_CHECK_RESULT();
2285 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2286 /* Configure default VNIC again if necessary. */
2287 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2288 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2294 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2298 int nr_ctxs = vnic->num_lb_ctxts;
2299 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2300 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2302 for (i = 0; i < nr_ctxs; i++) {
2303 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2305 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2306 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2307 req.hash_mode_flags = vnic->hash_mode;
2309 req.hash_key_tbl_addr =
2310 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2312 req.ring_grp_tbl_addr =
2313 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2314 i * HW_HASH_INDEX_SIZE);
2315 req.ring_table_pair_index = i;
2316 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2321 HWRM_CHECK_RESULT();
2328 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2329 struct bnxt_vnic_info *vnic)
2332 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2333 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2335 if (!vnic->rss_table)
2338 if (BNXT_CHIP_P5(bp))
2339 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2341 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2343 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2344 req.hash_mode_flags = vnic->hash_mode;
2346 req.ring_grp_tbl_addr =
2347 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2348 req.hash_key_tbl_addr =
2349 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2350 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2351 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2353 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2355 HWRM_CHECK_RESULT();
2361 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2362 struct bnxt_vnic_info *vnic)
2365 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2366 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2369 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2370 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2374 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2376 req.flags = rte_cpu_to_le_32(
2377 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2379 req.enables = rte_cpu_to_le_32(
2380 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2382 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2383 size -= RTE_PKTMBUF_HEADROOM;
2384 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2386 req.jumbo_thresh = rte_cpu_to_le_16(size);
2387 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2389 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2391 HWRM_CHECK_RESULT();
2397 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2398 struct bnxt_vnic_info *vnic, bool enable)
2401 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2402 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2404 if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2406 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2410 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2411 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2415 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2418 req.enables = rte_cpu_to_le_32(
2419 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2420 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2421 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2422 req.flags = rte_cpu_to_le_32(
2423 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2424 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2425 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2426 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2427 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2428 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2429 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2430 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2431 req.min_agg_len = rte_cpu_to_le_32(512);
2433 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2435 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2437 HWRM_CHECK_RESULT();
2443 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2445 struct hwrm_func_cfg_input req = {0};
2446 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2449 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2450 req.enables = rte_cpu_to_le_32(
2451 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2452 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2453 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2455 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2457 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2458 HWRM_CHECK_RESULT();
2461 bp->pf->vf_info[vf].random_mac = false;
2466 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2470 struct hwrm_func_qstats_input req = {.req_type = 0};
2471 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2473 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2475 req.fid = rte_cpu_to_le_16(fid);
2477 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2479 HWRM_CHECK_RESULT();
2482 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2489 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2490 struct rte_eth_stats *stats,
2491 struct hwrm_func_qstats_output *func_qstats)
2494 struct hwrm_func_qstats_input req = {.req_type = 0};
2495 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2497 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2499 req.fid = rte_cpu_to_le_16(fid);
2501 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2503 HWRM_CHECK_RESULT();
2505 memcpy(func_qstats, resp,
2506 sizeof(struct hwrm_func_qstats_output));
2511 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2512 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2513 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2514 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2515 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2516 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2518 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2519 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2520 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2521 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2522 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2523 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2525 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2526 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2527 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2535 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2538 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2539 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2541 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2543 req.fid = rte_cpu_to_le_16(fid);
2545 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2547 HWRM_CHECK_RESULT();
2553 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2558 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2559 struct bnxt_tx_queue *txq;
2560 struct bnxt_rx_queue *rxq;
2561 struct bnxt_cp_ring_info *cpr;
2563 if (i >= bp->rx_cp_nr_rings) {
2564 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2567 rxq = bp->rx_queues[i];
2571 rc = bnxt_hwrm_stat_clear(bp, cpr);
2579 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2583 struct bnxt_cp_ring_info *cpr;
2585 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2587 if (i >= bp->rx_cp_nr_rings) {
2588 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2590 cpr = bp->rx_queues[i]->cp_ring;
2591 if (BNXT_HAS_RING_GRPS(bp))
2592 bp->grp_info[i].fw_stats_ctx = -1;
2594 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2595 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2596 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2604 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2609 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2610 struct bnxt_tx_queue *txq;
2611 struct bnxt_rx_queue *rxq;
2612 struct bnxt_cp_ring_info *cpr;
2614 if (i >= bp->rx_cp_nr_rings) {
2615 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2618 rxq = bp->rx_queues[i];
2622 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2631 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2636 if (!BNXT_HAS_RING_GRPS(bp))
2639 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2641 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2644 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2652 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2654 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2656 bnxt_hwrm_ring_free(bp, cp_ring,
2657 HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2658 INVALID_HW_RING_ID);
2659 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2660 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2661 sizeof(*cpr->cp_desc_ring));
2662 cpr->cp_raw_cons = 0;
2666 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2668 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2670 bnxt_hwrm_ring_free(bp, cp_ring,
2671 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2672 INVALID_HW_RING_ID);
2673 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2674 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2675 sizeof(*cpr->cp_desc_ring));
2676 cpr->cp_raw_cons = 0;
2680 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2682 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2683 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2684 struct bnxt_ring *ring = rxr->rx_ring_struct;
2685 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2687 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2688 bnxt_hwrm_ring_free(bp, ring,
2689 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2690 cpr->cp_ring_struct->fw_ring_id);
2691 ring->fw_ring_id = INVALID_HW_RING_ID;
2692 if (BNXT_HAS_RING_GRPS(bp))
2693 bp->grp_info[queue_index].rx_fw_ring_id =
2696 ring = rxr->ag_ring_struct;
2697 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2698 bnxt_hwrm_ring_free(bp, ring,
2700 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2701 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2702 cpr->cp_ring_struct->fw_ring_id);
2703 if (BNXT_HAS_RING_GRPS(bp))
2704 bp->grp_info[queue_index].ag_fw_ring_id =
2707 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2708 bnxt_free_cp_ring(bp, cpr);
2710 if (BNXT_HAS_RING_GRPS(bp))
2711 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2715 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2719 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2720 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2721 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2722 struct bnxt_ring *ring = txr->tx_ring_struct;
2723 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2725 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2726 bnxt_hwrm_ring_free(bp, ring,
2727 HWRM_RING_FREE_INPUT_RING_TYPE_TX,
2728 cpr->cp_ring_struct->fw_ring_id);
2729 ring->fw_ring_id = INVALID_HW_RING_ID;
2730 memset(txr->tx_desc_ring, 0,
2731 txr->tx_ring_struct->ring_size *
2732 sizeof(*txr->tx_desc_ring));
2733 memset(txr->tx_buf_ring, 0,
2734 txr->tx_ring_struct->ring_size *
2735 sizeof(*txr->tx_buf_ring));
2736 txr->tx_raw_prod = 0;
2737 txr->tx_raw_cons = 0;
2739 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2740 bnxt_free_cp_ring(bp, cpr);
2741 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2745 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2746 bnxt_free_hwrm_rx_ring(bp, i);
2751 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2756 if (!BNXT_HAS_RING_GRPS(bp))
2759 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2760 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2768 * HWRM utility functions
2771 void bnxt_free_hwrm_resources(struct bnxt *bp)
2773 /* Release memzone */
2774 rte_free(bp->hwrm_cmd_resp_addr);
2775 rte_free(bp->hwrm_short_cmd_req_addr);
2776 bp->hwrm_cmd_resp_addr = NULL;
2777 bp->hwrm_short_cmd_req_addr = NULL;
2778 bp->hwrm_cmd_resp_dma_addr = 0;
2779 bp->hwrm_short_cmd_req_dma_addr = 0;
2782 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2784 struct rte_pci_device *pdev = bp->pdev;
2785 char type[RTE_MEMZONE_NAMESIZE];
2787 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2788 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2789 bp->max_resp_len = BNXT_PAGE_SIZE;
2790 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2791 if (bp->hwrm_cmd_resp_addr == NULL)
2793 bp->hwrm_cmd_resp_dma_addr =
2794 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2795 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2797 "unable to map response address to physical memory\n");
2800 rte_spinlock_init(&bp->hwrm_lock);
2806 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2810 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2811 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2814 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2815 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2820 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2825 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2827 struct bnxt_filter_info *filter;
2830 STAILQ_FOREACH(filter, &vnic->filter, next) {
2831 rc = bnxt_clear_one_vnic_filter(bp, filter);
2832 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2833 bnxt_free_filter(bp, filter);
2839 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2841 struct bnxt_filter_info *filter;
2842 struct rte_flow *flow;
2845 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2846 flow = STAILQ_FIRST(&vnic->flow_list);
2847 filter = flow->filter;
2848 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2849 rc = bnxt_clear_one_vnic_filter(bp, filter);
2851 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2857 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2859 struct bnxt_filter_info *filter;
2862 STAILQ_FOREACH(filter, &vnic->filter, next) {
2863 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2864 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2866 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2867 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2870 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2879 bnxt_free_tunnel_ports(struct bnxt *bp)
2881 if (bp->vxlan_port_cnt)
2882 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2883 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2885 if (bp->geneve_port_cnt)
2886 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2887 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2890 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2894 if (bp->vnic_info == NULL)
2898 * Cleanup VNICs in reverse order, to make sure the L2 filter
2899 * from vnic0 is last to be cleaned up.
2901 for (i = bp->max_vnics - 1; i >= 0; i--) {
2902 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2904 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2907 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2909 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2911 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2913 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2915 bnxt_hwrm_vnic_free(bp, vnic);
2917 rte_free(vnic->fw_grp_ids);
2919 /* Ring resources */
2920 bnxt_free_all_hwrm_rings(bp);
2921 bnxt_free_all_hwrm_ring_grps(bp);
2922 bnxt_free_all_hwrm_stat_ctxs(bp);
2923 bnxt_free_tunnel_ports(bp);
2926 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2928 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2930 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2931 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2933 switch (conf_link_speed) {
2934 case ETH_LINK_SPEED_10M_HD:
2935 case ETH_LINK_SPEED_100M_HD:
2937 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2939 return hw_link_duplex;
2942 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2947 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2950 uint16_t eth_link_speed = 0;
2952 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2953 return ETH_LINK_SPEED_AUTONEG;
2955 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2956 case ETH_LINK_SPEED_100M:
2957 case ETH_LINK_SPEED_100M_HD:
2960 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2962 case ETH_LINK_SPEED_1G:
2964 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2966 case ETH_LINK_SPEED_2_5G:
2968 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2970 case ETH_LINK_SPEED_10G:
2972 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2974 case ETH_LINK_SPEED_20G:
2976 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2978 case ETH_LINK_SPEED_25G:
2980 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2982 case ETH_LINK_SPEED_40G:
2984 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2986 case ETH_LINK_SPEED_50G:
2987 eth_link_speed = pam4_link ?
2988 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
2989 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2991 case ETH_LINK_SPEED_100G:
2992 eth_link_speed = pam4_link ?
2993 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
2994 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2996 case ETH_LINK_SPEED_200G:
2998 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3002 "Unsupported link speed %d; default to AUTO\n",
3006 return eth_link_speed;
3009 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3010 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3011 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3012 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3013 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3015 static int bnxt_validate_link_speed(struct bnxt *bp)
3017 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3018 uint16_t port_id = bp->eth_dev->data->port_id;
3019 uint32_t link_speed_capa;
3022 if (link_speed == ETH_LINK_SPEED_AUTONEG)
3025 link_speed_capa = bnxt_get_speed_capabilities(bp);
3027 if (link_speed & ETH_LINK_SPEED_FIXED) {
3028 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3030 if (one_speed & (one_speed - 1)) {
3032 "Invalid advertised speeds (%u) for port %u\n",
3033 link_speed, port_id);
3036 if ((one_speed & link_speed_capa) != one_speed) {
3038 "Unsupported advertised speed (%u) for port %u\n",
3039 link_speed, port_id);
3043 if (!(link_speed & link_speed_capa)) {
3045 "Unsupported advertised speeds (%u) for port %u\n",
3046 link_speed, port_id);
3054 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3058 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3059 if (bp->link_info->support_speeds)
3060 return bp->link_info->support_speeds;
3061 link_speed = BNXT_SUPPORTED_SPEEDS;
3064 if (link_speed & ETH_LINK_SPEED_100M)
3065 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3066 if (link_speed & ETH_LINK_SPEED_100M_HD)
3067 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3068 if (link_speed & ETH_LINK_SPEED_1G)
3069 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3070 if (link_speed & ETH_LINK_SPEED_2_5G)
3071 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3072 if (link_speed & ETH_LINK_SPEED_10G)
3073 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3074 if (link_speed & ETH_LINK_SPEED_20G)
3075 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3076 if (link_speed & ETH_LINK_SPEED_25G)
3077 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3078 if (link_speed & ETH_LINK_SPEED_40G)
3079 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3080 if (link_speed & ETH_LINK_SPEED_50G)
3081 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3082 if (link_speed & ETH_LINK_SPEED_100G)
3083 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3084 if (link_speed & ETH_LINK_SPEED_200G)
3085 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3089 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3091 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3093 switch (hw_link_speed) {
3094 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3095 eth_link_speed = ETH_SPEED_NUM_100M;
3097 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3098 eth_link_speed = ETH_SPEED_NUM_1G;
3100 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3101 eth_link_speed = ETH_SPEED_NUM_2_5G;
3103 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3104 eth_link_speed = ETH_SPEED_NUM_10G;
3106 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3107 eth_link_speed = ETH_SPEED_NUM_20G;
3109 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3110 eth_link_speed = ETH_SPEED_NUM_25G;
3112 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3113 eth_link_speed = ETH_SPEED_NUM_40G;
3115 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3116 eth_link_speed = ETH_SPEED_NUM_50G;
3118 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3119 eth_link_speed = ETH_SPEED_NUM_100G;
3121 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3122 eth_link_speed = ETH_SPEED_NUM_200G;
3124 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3126 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3130 return eth_link_speed;
3133 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3135 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3137 switch (hw_link_duplex) {
3138 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3139 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3141 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3143 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3144 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3147 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3151 return eth_link_duplex;
3154 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3157 struct bnxt_link_info *link_info = bp->link_info;
3159 rc = bnxt_hwrm_port_phy_qcaps(bp);
3161 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3163 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3165 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3169 if (link_info->link_speed)
3171 bnxt_parse_hw_link_speed(link_info->link_speed);
3173 link->link_speed = ETH_SPEED_NUM_NONE;
3174 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3175 link->link_status = link_info->link_up;
3176 link->link_autoneg = link_info->auto_mode ==
3177 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3178 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3183 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3186 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3187 struct bnxt_link_info link_req;
3188 uint16_t speed, autoneg;
3190 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3193 rc = bnxt_validate_link_speed(bp);
3197 memset(&link_req, 0, sizeof(link_req));
3198 link_req.link_up = link_up;
3202 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3203 if (BNXT_CHIP_P5(bp) &&
3204 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3205 /* 40G is not supported as part of media auto detect.
3206 * The speed should be forced and autoneg disabled
3207 * to configure 40G speed.
3209 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3213 /* No auto speeds and no auto_pam4_link. Disable autoneg */
3214 if (bp->link_info->auto_link_speed == 0 &&
3215 bp->link_info->link_signal_mode &&
3216 bp->link_info->auto_pam4_link_speeds == 0)
3219 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3220 bp->link_info->link_signal_mode);
3221 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3222 /* Autoneg can be done only when the FW allows.
3223 * When user configures fixed speed of 40G and later changes to
3224 * any other speed, auto_link_speed/force_link_speed is still set
3225 * to 40G until link comes up at new speed.
3228 !(!BNXT_CHIP_P5(bp) &&
3229 (bp->link_info->auto_link_speed ||
3230 bp->link_info->force_link_speed))) {
3231 link_req.phy_flags |=
3232 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3233 link_req.auto_link_speed_mask =
3234 bnxt_parse_eth_link_speed_mask(bp,
3235 dev_conf->link_speeds);
3237 if (bp->link_info->phy_type ==
3238 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3239 bp->link_info->phy_type ==
3240 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3241 bp->link_info->media_type ==
3242 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3243 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3247 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3248 /* If user wants a particular speed try that first. */
3250 link_req.link_speed = speed;
3251 else if (bp->link_info->force_pam4_link_speed)
3252 link_req.link_speed =
3253 bp->link_info->force_pam4_link_speed;
3254 else if (bp->link_info->auto_pam4_link_speeds)
3255 link_req.link_speed =
3256 bp->link_info->auto_pam4_link_speeds;
3257 else if (bp->link_info->support_pam4_speeds)
3258 link_req.link_speed =
3259 bp->link_info->support_pam4_speeds;
3260 else if (bp->link_info->force_link_speed)
3261 link_req.link_speed = bp->link_info->force_link_speed;
3263 link_req.link_speed = bp->link_info->auto_link_speed;
3264 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3265 * zero. Use the auto_link_speed.
3267 if (bp->link_info->auto_link_speed != 0 &&
3268 bp->link_info->auto_pam4_link_speeds == 0)
3269 link_req.link_speed = bp->link_info->auto_link_speed;
3271 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3272 link_req.auto_pause = bp->link_info->auto_pause;
3273 link_req.force_pause = bp->link_info->force_pause;
3276 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3279 "Set link config failed with rc %d\n", rc);
3287 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3289 struct hwrm_func_qcfg_input req = {0};
3290 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3293 bp->func_svif = BNXT_SVIF_INVALID;
3296 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3297 req.fid = rte_cpu_to_le_16(0xffff);
3299 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3301 HWRM_CHECK_RESULT();
3303 /* Hard Coded.. 0xfff VLAN ID mask */
3304 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3306 svif_info = rte_le_to_cpu_16(resp->svif_info);
3307 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3308 bp->func_svif = svif_info &
3309 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3311 flags = rte_le_to_cpu_16(resp->flags);
3312 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3313 bp->flags |= BNXT_FLAG_MULTI_HOST;
3316 !BNXT_VF_IS_TRUSTED(bp) &&
3317 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3318 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3319 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3320 } else if (BNXT_VF(bp) &&
3321 BNXT_VF_IS_TRUSTED(bp) &&
3322 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3323 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3324 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3328 *mtu = rte_le_to_cpu_16(resp->mtu);
3330 switch (resp->port_partition_type) {
3331 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3332 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3333 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3335 bp->flags |= BNXT_FLAG_NPAR_PF;
3338 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3342 bp->legacy_db_size =
3343 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3350 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3352 struct hwrm_func_qcfg_input req = {0};
3353 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3356 if (!BNXT_VF_IS_TRUSTED(bp))
3362 bp->parent->fid = BNXT_PF_FID_INVALID;
3364 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3366 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3368 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3370 HWRM_CHECK_RESULT_SILENT();
3372 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3373 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3374 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3375 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3377 /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3378 if (bp->parent->vnic == 0) {
3379 PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
3380 /* Use hard-coded values appropriate for current Wh+ fw. */
3381 if (bp->parent->fid == 2)
3382 bp->parent->vnic = 0x100;
3384 bp->parent->vnic = 1;
3392 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3393 uint16_t *vnic_id, uint16_t *svif)
3395 struct hwrm_func_qcfg_input req = {0};
3396 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3400 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3401 req.fid = rte_cpu_to_le_16(fid);
3403 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3405 HWRM_CHECK_RESULT();
3408 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3410 svif_info = rte_le_to_cpu_16(resp->svif_info);
3411 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3412 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3419 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3421 struct hwrm_port_mac_qcfg_input req = {0};
3422 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3423 uint16_t port_svif_info;
3426 bp->port_svif = BNXT_SVIF_INVALID;
3428 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3431 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3433 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3435 HWRM_CHECK_RESULT_SILENT();
3437 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3438 if (port_svif_info &
3439 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3440 bp->port_svif = port_svif_info &
3441 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3448 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3449 struct bnxt_pf_resource_info *pf_resc)
3451 struct hwrm_func_cfg_input req = {0};
3452 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3456 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3457 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3458 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3459 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3460 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3461 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3462 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3463 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3464 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3466 if (BNXT_HAS_RING_GRPS(bp)) {
3467 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3468 req.num_hw_ring_grps =
3469 rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3470 } else if (BNXT_HAS_NQ(bp)) {
3471 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3472 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3475 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3476 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3477 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3478 req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3479 req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3480 req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3481 req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3482 req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3483 req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3484 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3485 req.fid = rte_cpu_to_le_16(0xffff);
3486 req.enables = rte_cpu_to_le_32(enables);
3488 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3490 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3492 HWRM_CHECK_RESULT();
3498 /* min values are the guaranteed resources and max values are subject
3499 * to availability. The strategy for now is to keep both min & max
3503 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3504 struct hwrm_func_vf_resource_cfg_input *req,
3507 req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3509 req->min_rsscos_ctx = req->max_rsscos_ctx;
3510 req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3511 req->min_stat_ctx = req->max_stat_ctx;
3512 req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3514 req->min_cmpl_rings = req->max_cmpl_rings;
3515 req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3516 req->min_tx_rings = req->max_tx_rings;
3517 req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3518 req->min_rx_rings = req->max_rx_rings;
3519 req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3520 req->min_l2_ctxs = req->max_l2_ctxs;
3521 /* TODO: For now, do not support VMDq/RFS on VFs. */
3522 req->max_vnics = rte_cpu_to_le_16(1);
3523 req->min_vnics = req->max_vnics;
3524 req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3526 req->min_hw_ring_grps = req->max_hw_ring_grps;
3528 rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3532 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3533 struct hwrm_func_cfg_input *req,
3536 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3537 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3538 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3539 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3540 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3541 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3542 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3543 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3544 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3545 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3547 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3548 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3550 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3551 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3553 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3554 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3556 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3557 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3558 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3559 /* TODO: For now, do not support VMDq/RFS on VFs. */
3560 req->num_vnics = rte_cpu_to_le_16(1);
3561 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3565 /* Update the port wide resource values based on how many resources
3566 * got allocated to the VF.
3568 static int bnxt_update_max_resources(struct bnxt *bp,
3571 struct hwrm_func_qcfg_input req = {0};
3572 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3575 /* Get the actual allocated values now */
3576 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3577 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3578 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3579 HWRM_CHECK_RESULT();
3581 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3582 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3583 bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3584 bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3585 bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3586 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3587 bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3594 /* Update the PF resource values based on how many resources
3595 * got allocated to it.
3597 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3599 struct hwrm_func_qcfg_input req = {0};
3600 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3603 /* Get the actual allocated values now */
3604 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3605 req.fid = rte_cpu_to_le_16(0xffff);
3606 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3607 HWRM_CHECK_RESULT();
3609 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3610 bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3611 bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3612 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3613 bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3614 bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3615 bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3616 bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3623 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3625 struct hwrm_func_qcfg_input req = {0};
3626 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3629 /* Check for zero MAC address */
3630 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3631 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3632 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3633 HWRM_CHECK_RESULT();
3634 rc = rte_le_to_cpu_16(resp->vlan);
3641 static int bnxt_query_pf_resources(struct bnxt *bp,
3642 struct bnxt_pf_resource_info *pf_resc)
3644 struct hwrm_func_qcfg_input req = {0};
3645 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3648 /* And copy the allocated numbers into the pf struct */
3649 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3650 req.fid = rte_cpu_to_le_16(0xffff);
3651 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3652 HWRM_CHECK_RESULT();
3654 pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3655 pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3656 pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3657 pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3658 pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3659 pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3660 pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3661 bp->pf->evb_mode = resp->evb_mode;
3669 bnxt_calculate_pf_resources(struct bnxt *bp,
3670 struct bnxt_pf_resource_info *pf_resc,
3674 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3675 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3676 pf_resc->num_cp_rings = bp->max_cp_rings;
3677 pf_resc->num_tx_rings = bp->max_tx_rings;
3678 pf_resc->num_rx_rings = bp->max_rx_rings;
3679 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3680 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3685 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3686 bp->max_rsscos_ctx % (num_vfs + 1);
3687 pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3688 bp->max_stat_ctx % (num_vfs + 1);
3689 pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3690 bp->max_cp_rings % (num_vfs + 1);
3691 pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3692 bp->max_tx_rings % (num_vfs + 1);
3693 pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3694 bp->max_rx_rings % (num_vfs + 1);
3695 pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3696 bp->max_l2_ctx % (num_vfs + 1);
3697 pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3698 bp->max_ring_grps % (num_vfs + 1);
3701 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3703 struct bnxt_pf_resource_info pf_resc = { 0 };
3707 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3711 rc = bnxt_hwrm_func_qcaps(bp);
3715 bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3717 bp->pf->func_cfg_flags &=
3718 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3719 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3720 bp->pf->func_cfg_flags |=
3721 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3723 rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3727 rc = bnxt_update_max_resources_pf_only(bp);
3733 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3735 size_t req_buf_sz, sz;
3738 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3739 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3740 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3741 if (bp->pf->vf_req_buf == NULL) {
3745 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3746 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3748 for (i = 0; i < num_vfs; i++)
3749 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3750 (i * HWRM_MAX_REQ_LEN);
3752 rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3754 rte_free(bp->pf->vf_req_buf);
3760 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3762 struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3763 struct hwrm_func_vf_resource_cfg_input req = {0};
3766 bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3767 bp->pf->active_vfs = 0;
3768 for (i = 0; i < num_vfs; i++) {
3769 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3770 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3771 rc = bnxt_hwrm_send_message(bp,
3775 if (rc || resp->error_code) {
3777 "Failed to initialize VF %d\n", i);
3779 "Not all VFs available. (%d, %d)\n",
3780 rc, resp->error_code);
3783 /* If the first VF configuration itself fails,
3784 * unregister the vf_fwd_request buffer.
3787 bnxt_hwrm_func_buf_unrgtr(bp);
3792 /* Update the max resource values based on the resource values
3793 * allocated to the VF.
3795 bnxt_update_max_resources(bp, i);
3796 bp->pf->active_vfs++;
3797 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3804 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3806 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3807 struct hwrm_func_cfg_input req = {0};
3810 bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3812 bp->pf->active_vfs = 0;
3813 for (i = 0; i < num_vfs; i++) {
3814 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3815 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3816 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3817 rc = bnxt_hwrm_send_message(bp,
3822 /* Clear enable flag for next pass */
3823 req.enables &= ~rte_cpu_to_le_32(
3824 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3826 if (rc || resp->error_code) {
3828 "Failed to initialize VF %d\n", i);
3830 "Not all VFs available. (%d, %d)\n",
3831 rc, resp->error_code);
3834 /* If the first VF configuration itself fails,
3835 * unregister the vf_fwd_request buffer.
3838 bnxt_hwrm_func_buf_unrgtr(bp);
3844 /* Update the max resource values based on the resource values
3845 * allocated to the VF.
3847 bnxt_update_max_resources(bp, i);
3848 bp->pf->active_vfs++;
3849 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3856 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3858 if (bp->flags & BNXT_FLAG_NEW_RM)
3859 bnxt_process_vf_resc_config_new(bp, num_vfs);
3861 bnxt_process_vf_resc_config_old(bp, num_vfs);
3865 bnxt_update_pf_resources(struct bnxt *bp,
3866 struct bnxt_pf_resource_info *pf_resc)
3868 bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3869 bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3870 bp->max_cp_rings = pf_resc->num_cp_rings;
3871 bp->max_tx_rings = pf_resc->num_tx_rings;
3872 bp->max_rx_rings = pf_resc->num_rx_rings;
3873 bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3877 bnxt_configure_pf_resources(struct bnxt *bp,
3878 struct bnxt_pf_resource_info *pf_resc)
3881 * We're using STD_TX_RING_MODE here which will limit the TX
3882 * rings. This will allow QoS to function properly. Not setting this
3883 * will cause PF rings to break bandwidth settings.
3885 bp->pf->func_cfg_flags &=
3886 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3887 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3888 bp->pf->func_cfg_flags |=
3889 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3890 return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3893 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3895 struct bnxt_pf_resource_info pf_resc = { 0 };
3899 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3903 rc = bnxt_hwrm_func_qcaps(bp);
3907 bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3909 rc = bnxt_configure_pf_resources(bp, &pf_resc);
3913 rc = bnxt_query_pf_resources(bp, &pf_resc);
3918 * Now, create and register a buffer to hold forwarded VF requests
3920 rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3924 bnxt_configure_vf_resources(bp, num_vfs);
3926 bnxt_update_pf_resources(bp, &pf_resc);
3931 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3933 struct hwrm_func_cfg_input req = {0};
3934 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3937 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3939 req.fid = rte_cpu_to_le_16(0xffff);
3940 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3941 req.evb_mode = bp->pf->evb_mode;
3943 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3944 HWRM_CHECK_RESULT();
3950 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3951 uint8_t tunnel_type)
3953 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3954 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3957 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3958 req.tunnel_type = tunnel_type;
3959 req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3960 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3961 HWRM_CHECK_RESULT();
3963 switch (tunnel_type) {
3964 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3965 bp->vxlan_fw_dst_port_id =
3966 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3967 bp->vxlan_port = port;
3969 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3970 bp->geneve_fw_dst_port_id =
3971 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3972 bp->geneve_port = port;
3983 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3984 uint8_t tunnel_type)
3986 struct hwrm_tunnel_dst_port_free_input req = {0};
3987 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3990 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3992 req.tunnel_type = tunnel_type;
3993 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3994 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3996 HWRM_CHECK_RESULT();
4000 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4002 bp->vxlan_port_cnt = 0;
4006 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4007 bp->geneve_port = 0;
4008 bp->geneve_port_cnt = 0;
4014 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4017 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4018 struct hwrm_func_cfg_input req = {0};
4021 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4023 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4024 req.flags = rte_cpu_to_le_32(flags);
4025 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4027 HWRM_CHECK_RESULT();
4033 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4035 uint32_t *flag = flagp;
4037 vnic->flags = *flag;
4040 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4042 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4045 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4047 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4048 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4051 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4053 req.req_buf_num_pages = rte_cpu_to_le_16(1);
4054 req.req_buf_page_size =
4055 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4056 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4057 req.req_buf_page_addr0 =
4058 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4059 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4061 "unable to map buffer address to physical memory\n");
4066 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4068 HWRM_CHECK_RESULT();
4074 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4077 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4078 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4080 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4083 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4085 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4087 HWRM_CHECK_RESULT();
4093 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4095 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4096 struct hwrm_func_cfg_input req = {0};
4099 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4101 req.fid = rte_cpu_to_le_16(0xffff);
4102 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4103 req.enables = rte_cpu_to_le_32(
4104 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4105 req.async_event_cr = rte_cpu_to_le_16(
4106 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4107 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4109 HWRM_CHECK_RESULT();
4115 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4117 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4118 struct hwrm_func_vf_cfg_input req = {0};
4121 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4123 req.enables = rte_cpu_to_le_32(
4124 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4125 req.async_event_cr = rte_cpu_to_le_16(
4126 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4127 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4129 HWRM_CHECK_RESULT();
4135 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4137 struct hwrm_func_cfg_input req = {0};
4138 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4139 uint16_t dflt_vlan, fid;
4140 uint32_t func_cfg_flags;
4143 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4146 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4147 fid = bp->pf->vf_info[vf].fid;
4148 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4150 fid = rte_cpu_to_le_16(0xffff);
4151 func_cfg_flags = bp->pf->func_cfg_flags;
4152 dflt_vlan = bp->vlan;
4155 req.flags = rte_cpu_to_le_32(func_cfg_flags);
4156 req.fid = rte_cpu_to_le_16(fid);
4157 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4158 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4160 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4162 HWRM_CHECK_RESULT();
4168 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4169 uint16_t max_bw, uint16_t enables)
4171 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4172 struct hwrm_func_cfg_input req = {0};
4175 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4177 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4178 req.enables |= rte_cpu_to_le_32(enables);
4179 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4180 req.max_bw = rte_cpu_to_le_32(max_bw);
4181 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4183 HWRM_CHECK_RESULT();
4189 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4191 struct hwrm_func_cfg_input req = {0};
4192 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4195 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4197 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4198 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4199 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4200 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4202 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4204 HWRM_CHECK_RESULT();
4210 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4215 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4217 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4222 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4223 void *encaped, size_t ec_size)
4226 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4227 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4229 if (ec_size > sizeof(req.encap_request))
4232 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4234 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4235 memcpy(req.encap_request, encaped, ec_size);
4237 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4239 HWRM_CHECK_RESULT();
4245 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4246 struct rte_ether_addr *mac)
4248 struct hwrm_func_qcfg_input req = {0};
4249 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4252 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4254 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4255 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4257 HWRM_CHECK_RESULT();
4259 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4266 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4267 void *encaped, size_t ec_size)
4270 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4271 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4273 if (ec_size > sizeof(req.encap_request))
4276 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4278 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4279 memcpy(req.encap_request, encaped, ec_size);
4281 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4283 HWRM_CHECK_RESULT();
4289 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
4290 struct rte_eth_stats *stats, uint8_t rx)
4293 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4294 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4296 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4298 req.stat_ctx_id = rte_cpu_to_le_32(cid);
4300 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4302 HWRM_CHECK_RESULT();
4305 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4306 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4307 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4308 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4309 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4310 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4311 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4312 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4314 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4315 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4316 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4317 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4318 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4319 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4327 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4329 struct hwrm_port_qstats_input req = {0};
4330 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4331 struct bnxt_pf_info *pf = bp->pf;
4334 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4336 req.port_id = rte_cpu_to_le_16(pf->port_id);
4337 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4338 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4339 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4341 HWRM_CHECK_RESULT();
4347 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4349 struct hwrm_port_clr_stats_input req = {0};
4350 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4351 struct bnxt_pf_info *pf = bp->pf;
4354 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4355 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4356 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4359 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4361 req.port_id = rte_cpu_to_le_16(pf->port_id);
4362 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4364 HWRM_CHECK_RESULT();
4370 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4372 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4373 struct hwrm_port_led_qcaps_input req = {0};
4379 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4380 req.port_id = bp->pf->port_id;
4381 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4383 HWRM_CHECK_RESULT_SILENT();
4385 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4388 bp->leds->num_leds = resp->num_leds;
4389 memcpy(bp->leds, &resp->led0_id,
4390 sizeof(bp->leds[0]) * bp->leds->num_leds);
4391 for (i = 0; i < bp->leds->num_leds; i++) {
4392 struct bnxt_led_info *led = &bp->leds[i];
4394 uint16_t caps = led->led_state_caps;
4396 if (!led->led_group_id ||
4397 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4398 bp->leds->num_leds = 0;
4409 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4411 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4412 struct hwrm_port_led_cfg_input req = {0};
4413 struct bnxt_led_cfg *led_cfg;
4414 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4415 uint16_t duration = 0;
4418 if (!bp->leds->num_leds || BNXT_VF(bp))
4421 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4424 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4425 duration = rte_cpu_to_le_16(500);
4427 req.port_id = bp->pf->port_id;
4428 req.num_leds = bp->leds->num_leds;
4429 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4430 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4431 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4432 led_cfg->led_id = bp->leds[i].led_id;
4433 led_cfg->led_state = led_state;
4434 led_cfg->led_blink_on = duration;
4435 led_cfg->led_blink_off = duration;
4436 led_cfg->led_group_id = bp->leds[i].led_group_id;
4439 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4441 HWRM_CHECK_RESULT();
4447 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4451 struct hwrm_nvm_get_dir_info_input req = {0};
4452 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4454 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4456 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4458 HWRM_CHECK_RESULT();
4460 *entries = rte_le_to_cpu_32(resp->entries);
4461 *length = rte_le_to_cpu_32(resp->entry_length);
4467 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4470 uint32_t dir_entries;
4471 uint32_t entry_length;
4474 rte_iova_t dma_handle;
4475 struct hwrm_nvm_get_dir_entries_input req = {0};
4476 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4478 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4482 *data++ = dir_entries;
4483 *data++ = entry_length;
4485 memset(data, 0xff, len);
4487 buflen = dir_entries * entry_length;
4488 buf = rte_malloc("nvm_dir", buflen, 0);
4491 dma_handle = rte_malloc_virt2iova(buf);
4492 if (dma_handle == RTE_BAD_IOVA) {
4495 "unable to map response address to physical memory\n");
4498 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4499 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4500 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4503 memcpy(data, buf, len > buflen ? buflen : len);
4506 HWRM_CHECK_RESULT();
4512 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4513 uint32_t offset, uint32_t length,
4518 rte_iova_t dma_handle;
4519 struct hwrm_nvm_read_input req = {0};
4520 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4522 buf = rte_malloc("nvm_item", length, 0);
4526 dma_handle = rte_malloc_virt2iova(buf);
4527 if (dma_handle == RTE_BAD_IOVA) {
4530 "unable to map response address to physical memory\n");
4533 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4534 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4535 req.dir_idx = rte_cpu_to_le_16(index);
4536 req.offset = rte_cpu_to_le_32(offset);
4537 req.len = rte_cpu_to_le_32(length);
4538 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4540 memcpy(data, buf, length);
4543 HWRM_CHECK_RESULT();
4549 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4552 struct hwrm_nvm_erase_dir_entry_input req = {0};
4553 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4555 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4556 req.dir_idx = rte_cpu_to_le_16(index);
4557 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4558 HWRM_CHECK_RESULT();
4565 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4566 uint16_t dir_ordinal, uint16_t dir_ext,
4567 uint16_t dir_attr, const uint8_t *data,
4571 struct hwrm_nvm_write_input req = {0};
4572 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4573 rte_iova_t dma_handle;
4576 buf = rte_malloc("nvm_write", data_len, 0);
4580 dma_handle = rte_malloc_virt2iova(buf);
4581 if (dma_handle == RTE_BAD_IOVA) {
4584 "unable to map response address to physical memory\n");
4587 memcpy(buf, data, data_len);
4589 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4591 req.dir_type = rte_cpu_to_le_16(dir_type);
4592 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4593 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4594 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4595 req.dir_data_length = rte_cpu_to_le_32(data_len);
4596 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4598 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4601 HWRM_CHECK_RESULT();
4608 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4610 uint32_t *count = cbdata;
4612 *count = *count + 1;
4615 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4616 struct bnxt_vnic_info *vnic __rte_unused)
4621 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4625 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4626 &count, bnxt_vnic_count_hwrm_stub);
4631 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4634 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4635 struct hwrm_func_vf_vnic_ids_query_output *resp =
4636 bp->hwrm_cmd_resp_addr;
4639 /* First query all VNIC ids */
4640 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4642 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4643 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4644 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4646 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4649 "unable to map VNIC ID table address to physical memory\n");
4652 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4653 HWRM_CHECK_RESULT();
4654 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4662 * This function queries the VNIC IDs for a specified VF. It then calls
4663 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4664 * Then it calls the hwrm_cb function to program this new vnic configuration.
4666 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4667 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4668 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4670 struct bnxt_vnic_info vnic;
4672 int i, num_vnic_ids;
4677 /* First query all VNIC ids */
4678 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4679 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4680 RTE_CACHE_LINE_SIZE);
4681 if (vnic_ids == NULL)
4684 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4685 rte_mem_lock_page(((char *)vnic_ids) + sz);
4687 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4689 if (num_vnic_ids < 0)
4690 return num_vnic_ids;
4692 /* Retrieve VNIC, update bd_stall then update */
4694 for (i = 0; i < num_vnic_ids; i++) {
4695 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4696 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4697 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4700 if (vnic.mru <= 4) /* Indicates unallocated */
4703 vnic_cb(&vnic, cbdata);
4705 rc = hwrm_cb(bp, &vnic);
4715 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4718 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4719 struct hwrm_func_cfg_input req = {0};
4722 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4724 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4725 req.enables |= rte_cpu_to_le_32(
4726 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4727 req.vlan_antispoof_mode = on ?
4728 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4729 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4730 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4732 HWRM_CHECK_RESULT();
4738 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4740 struct bnxt_vnic_info vnic;
4743 int num_vnic_ids, i;
4747 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4748 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4749 RTE_CACHE_LINE_SIZE);
4750 if (vnic_ids == NULL)
4753 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4754 rte_mem_lock_page(((char *)vnic_ids) + sz);
4756 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4762 * Loop through to find the default VNIC ID.
4763 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4764 * by sending the hwrm_func_qcfg command to the firmware.
4766 for (i = 0; i < num_vnic_ids; i++) {
4767 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4768 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4769 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4770 bp->pf->first_vf_id + vf);
4773 if (vnic.func_default) {
4775 return vnic.fw_vnic_id;
4778 /* Could not find a default VNIC. */
4779 PMD_DRV_LOG(ERR, "No default VNIC\n");
4785 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4787 struct bnxt_filter_info *filter)
4790 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4791 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4792 uint32_t enables = 0;
4794 if (filter->fw_em_filter_id != UINT64_MAX)
4795 bnxt_hwrm_clear_em_filter(bp, filter);
4797 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4799 req.flags = rte_cpu_to_le_32(filter->flags);
4801 enables = filter->enables |
4802 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4803 req.dst_id = rte_cpu_to_le_16(dst_id);
4805 if (filter->ip_addr_type) {
4806 req.ip_addr_type = filter->ip_addr_type;
4807 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4810 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4811 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4813 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4814 memcpy(req.src_macaddr, filter->src_macaddr,
4815 RTE_ETHER_ADDR_LEN);
4817 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4818 memcpy(req.dst_macaddr, filter->dst_macaddr,
4819 RTE_ETHER_ADDR_LEN);
4821 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4822 req.ovlan_vid = filter->l2_ovlan;
4824 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4825 req.ivlan_vid = filter->l2_ivlan;
4827 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4828 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4830 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4831 req.ip_protocol = filter->ip_protocol;
4833 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4834 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4836 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4837 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4839 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4840 req.src_port = rte_cpu_to_be_16(filter->src_port);
4842 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4843 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4845 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4846 req.mirror_vnic_id = filter->mirror_vnic_id;
4848 req.enables = rte_cpu_to_le_32(enables);
4850 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4852 HWRM_CHECK_RESULT();
4854 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4860 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4863 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4864 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4866 if (filter->fw_em_filter_id == UINT64_MAX)
4869 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4871 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4873 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4875 HWRM_CHECK_RESULT();
4878 filter->fw_em_filter_id = UINT64_MAX;
4879 filter->fw_l2_filter_id = UINT64_MAX;
4884 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4886 struct bnxt_filter_info *filter)
4889 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4890 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4891 bp->hwrm_cmd_resp_addr;
4892 uint32_t enables = 0;
4894 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4895 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4897 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4899 req.flags = rte_cpu_to_le_32(filter->flags);
4901 enables = filter->enables |
4902 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4903 req.dst_id = rte_cpu_to_le_16(dst_id);
4905 if (filter->ip_addr_type) {
4906 req.ip_addr_type = filter->ip_addr_type;
4908 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4911 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4912 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4914 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4915 memcpy(req.src_macaddr, filter->src_macaddr,
4916 RTE_ETHER_ADDR_LEN);
4918 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4919 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4921 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4922 req.ip_protocol = filter->ip_protocol;
4924 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4925 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4927 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4928 req.src_ipaddr_mask[0] =
4929 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4931 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4932 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4934 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4935 req.dst_ipaddr_mask[0] =
4936 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4938 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4939 req.src_port = rte_cpu_to_le_16(filter->src_port);
4941 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4942 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4944 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4945 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4947 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4948 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4950 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4951 req.mirror_vnic_id = filter->mirror_vnic_id;
4953 req.enables = rte_cpu_to_le_32(enables);
4955 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4957 HWRM_CHECK_RESULT();
4959 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4960 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4966 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4967 struct bnxt_filter_info *filter)
4970 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4971 struct hwrm_cfa_ntuple_filter_free_output *resp =
4972 bp->hwrm_cmd_resp_addr;
4974 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4977 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4979 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4981 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4983 HWRM_CHECK_RESULT();
4986 filter->fw_ntuple_filter_id = UINT64_MAX;
4992 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4994 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4995 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4996 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4997 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4998 uint16_t *ring_tbl = vnic->rss_table;
4999 int nr_ctxs = vnic->num_lb_ctxts;
5000 int max_rings = bp->rx_nr_rings;
5004 for (i = 0, k = 0; i < nr_ctxs; i++) {
5005 struct bnxt_rx_ring_info *rxr;
5006 struct bnxt_cp_ring_info *cpr;
5008 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5010 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5011 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5012 req.hash_mode_flags = vnic->hash_mode;
5014 req.ring_grp_tbl_addr =
5015 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5016 i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5017 2 * sizeof(*ring_tbl));
5018 req.hash_key_tbl_addr =
5019 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5021 req.ring_table_pair_index = i;
5022 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5024 for (j = 0; j < 64; j++) {
5027 /* Find next active ring. */
5028 for (cnt = 0; cnt < max_rings; cnt++) {
5029 if (rx_queue_state[k] !=
5030 RTE_ETH_QUEUE_STATE_STOPPED)
5032 if (++k == max_rings)
5036 /* Return if no rings are active. */
5037 if (cnt == max_rings) {
5042 /* Add rx/cp ring pair to RSS table. */
5043 rxr = rxqs[k]->rx_ring;
5044 cpr = rxqs[k]->cp_ring;
5046 ring_id = rxr->rx_ring_struct->fw_ring_id;
5047 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5048 ring_id = cpr->cp_ring_struct->fw_ring_id;
5049 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5051 if (++k == max_rings)
5054 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5057 HWRM_CHECK_RESULT();
5064 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5066 unsigned int rss_idx, fw_idx, i;
5068 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5071 if (!(vnic->rss_table && vnic->hash_type))
5074 if (BNXT_CHIP_P5(bp))
5075 return bnxt_vnic_rss_configure_p5(bp, vnic);
5078 * Fill the RSS hash & redirection table with
5079 * ring group ids for all VNICs
5081 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5082 rss_idx++, fw_idx++) {
5083 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5084 fw_idx %= bp->rx_cp_nr_rings;
5085 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5090 if (i == bp->rx_cp_nr_rings)
5093 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5096 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5099 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5100 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5104 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5106 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5107 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5109 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5110 req->num_cmpl_dma_aggr_during_int =
5111 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5113 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5115 /* min timer set to 1/2 of interrupt timer */
5116 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5118 /* buf timer set to 1/4 of interrupt timer */
5119 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5121 req->cmpl_aggr_dma_tmr_during_int =
5122 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5124 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5125 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5126 req->flags = rte_cpu_to_le_16(flags);
5129 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5130 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5132 struct hwrm_ring_aggint_qcaps_input req = {0};
5133 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5138 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5139 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5140 HWRM_CHECK_RESULT();
5142 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5143 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5145 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5146 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5147 agg_req->flags = rte_cpu_to_le_16(flags);
5149 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5150 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5151 agg_req->enables = rte_cpu_to_le_32(enables);
5157 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5158 struct bnxt_coal *coal, uint16_t ring_id)
5160 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5161 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5162 bp->hwrm_cmd_resp_addr;
5165 /* Set ring coalesce parameters only for 100G NICs */
5166 if (BNXT_CHIP_P5(bp)) {
5167 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5169 } else if (bnxt_stratus_device(bp)) {
5170 bnxt_hwrm_set_coal_params(coal, &req);
5176 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5178 req.ring_id = rte_cpu_to_le_16(ring_id);
5179 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5180 HWRM_CHECK_RESULT();
5185 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5186 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5188 struct hwrm_func_backing_store_qcaps_input req = {0};
5189 struct hwrm_func_backing_store_qcaps_output *resp =
5190 bp->hwrm_cmd_resp_addr;
5191 struct bnxt_ctx_pg_info *ctx_pg;
5192 struct bnxt_ctx_mem_info *ctx;
5193 int total_alloc_len;
5194 int rc, i, tqm_rings;
5196 if (!BNXT_CHIP_P5(bp) ||
5197 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5202 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5203 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5204 HWRM_CHECK_RESULT_SILENT();
5206 total_alloc_len = sizeof(*ctx);
5207 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5208 RTE_CACHE_LINE_SIZE);
5214 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5215 ctx->qp_min_qp1_entries =
5216 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5217 ctx->qp_max_l2_entries =
5218 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5219 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5220 ctx->srq_max_l2_entries =
5221 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5222 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5223 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5224 ctx->cq_max_l2_entries =
5225 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5226 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5227 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5228 ctx->vnic_max_vnic_entries =
5229 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5230 ctx->vnic_max_ring_table_entries =
5231 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5232 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5233 ctx->stat_max_entries =
5234 rte_le_to_cpu_32(resp->stat_max_entries);
5235 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5236 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5237 ctx->tqm_min_entries_per_ring =
5238 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5239 ctx->tqm_max_entries_per_ring =
5240 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5241 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5242 if (!ctx->tqm_entries_multiple)
5243 ctx->tqm_entries_multiple = 1;
5244 ctx->mrav_max_entries =
5245 rte_le_to_cpu_32(resp->mrav_max_entries);
5246 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5247 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5248 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5249 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5251 ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5252 RTE_MIN(ctx->tqm_fp_rings_count,
5253 BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5256 /* Check if the ext ring count needs to be counted.
5257 * Ext ring count is available only with new FW so we should not
5258 * look at the field on older FW.
5260 if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5261 bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5262 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5263 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5264 ctx->tqm_fp_rings_count);
5267 tqm_rings = ctx->tqm_fp_rings_count + 1;
5269 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5270 sizeof(*ctx_pg) * tqm_rings,
5271 RTE_CACHE_LINE_SIZE);
5276 for (i = 0; i < tqm_rings; i++, ctx_pg++)
5277 ctx->tqm_mem[i] = ctx_pg;
5285 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5287 struct hwrm_func_backing_store_cfg_input req = {0};
5288 struct hwrm_func_backing_store_cfg_output *resp =
5289 bp->hwrm_cmd_resp_addr;
5290 struct bnxt_ctx_mem_info *ctx = bp->ctx;
5291 struct bnxt_ctx_pg_info *ctx_pg;
5292 uint32_t *num_entries;
5301 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5302 req.enables = rte_cpu_to_le_32(enables);
5304 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5305 ctx_pg = &ctx->qp_mem;
5306 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5307 req.qp_num_qp1_entries =
5308 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5309 req.qp_num_l2_entries =
5310 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5311 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5312 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5313 &req.qpc_pg_size_qpc_lvl,
5317 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5318 ctx_pg = &ctx->srq_mem;
5319 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5320 req.srq_num_l2_entries =
5321 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5322 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5323 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5324 &req.srq_pg_size_srq_lvl,
5328 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5329 ctx_pg = &ctx->cq_mem;
5330 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5331 req.cq_num_l2_entries =
5332 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5333 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5334 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5335 &req.cq_pg_size_cq_lvl,
5339 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5340 ctx_pg = &ctx->vnic_mem;
5341 req.vnic_num_vnic_entries =
5342 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5343 req.vnic_num_ring_table_entries =
5344 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5345 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5346 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5347 &req.vnic_pg_size_vnic_lvl,
5348 &req.vnic_page_dir);
5351 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5352 ctx_pg = &ctx->stat_mem;
5353 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5354 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5355 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5356 &req.stat_pg_size_stat_lvl,
5357 &req.stat_page_dir);
5360 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5361 num_entries = &req.tqm_sp_num_entries;
5362 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5363 pg_dir = &req.tqm_sp_page_dir;
5364 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5365 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5366 if (!(enables & ena))
5369 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5371 ctx_pg = ctx->tqm_mem[i];
5372 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5373 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5376 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5377 /* DPDK does not need to configure MRAV and TIM type.
5378 * So we are skipping over MRAV and TIM. Skip to configure
5379 * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5381 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5382 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5383 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5384 &req.tqm_ring8_pg_size_tqm_ring_lvl,
5385 &req.tqm_ring8_page_dir);
5388 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5389 HWRM_CHECK_RESULT();
5395 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5397 struct hwrm_port_qstats_ext_input req = {0};
5398 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5399 struct bnxt_pf_info *pf = bp->pf;
5402 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5403 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5406 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5408 req.port_id = rte_cpu_to_le_16(pf->port_id);
5409 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5410 req.tx_stat_host_addr =
5411 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5413 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5415 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5416 req.rx_stat_host_addr =
5417 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5419 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5421 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5424 bp->fw_rx_port_stats_ext_size = 0;
5425 bp->fw_tx_port_stats_ext_size = 0;
5427 bp->fw_rx_port_stats_ext_size =
5428 rte_le_to_cpu_16(resp->rx_stat_size);
5429 bp->fw_tx_port_stats_ext_size =
5430 rte_le_to_cpu_16(resp->tx_stat_size);
5433 HWRM_CHECK_RESULT();
5440 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5442 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5443 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5444 bp->hwrm_cmd_resp_addr;
5447 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5448 req.tunnel_type = type;
5449 req.dest_fid = bp->fw_fid;
5450 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5451 HWRM_CHECK_RESULT();
5459 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5461 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5462 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5463 bp->hwrm_cmd_resp_addr;
5466 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5467 req.tunnel_type = type;
5468 req.dest_fid = bp->fw_fid;
5469 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5470 HWRM_CHECK_RESULT();
5477 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5479 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5480 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5481 bp->hwrm_cmd_resp_addr;
5484 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5485 req.src_fid = bp->fw_fid;
5486 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5487 HWRM_CHECK_RESULT();
5490 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5497 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5500 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5501 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5502 bp->hwrm_cmd_resp_addr;
5505 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5506 req.src_fid = bp->fw_fid;
5507 req.tunnel_type = tun_type;
5508 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5509 HWRM_CHECK_RESULT();
5512 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5514 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5521 int bnxt_hwrm_set_mac(struct bnxt *bp)
5523 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5524 struct hwrm_func_vf_cfg_input req = {0};
5530 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5533 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5534 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5536 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5538 HWRM_CHECK_RESULT();
5545 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5547 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5548 struct hwrm_func_drv_if_change_input req = {0};
5552 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5555 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5556 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5557 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5559 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5562 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5566 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5568 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5570 HWRM_CHECK_RESULT();
5571 flags = rte_le_to_cpu_32(resp->flags);
5577 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5578 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5579 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5585 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5587 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5588 struct bnxt_error_recovery_info *info = bp->recovery_info;
5589 struct hwrm_error_recovery_qcfg_input req = {0};
5594 /* Older FW does not have error recovery support */
5595 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5598 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5600 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5602 HWRM_CHECK_RESULT();
5604 flags = rte_le_to_cpu_32(resp->flags);
5605 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5606 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5607 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5608 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5610 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5611 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5616 /* FW returned values are in units of 100msec */
5617 info->driver_polling_freq =
5618 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5619 info->master_func_wait_period =
5620 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5621 info->normal_func_wait_period =
5622 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5623 info->master_func_wait_period_after_reset =
5624 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5625 info->max_bailout_time_after_reset =
5626 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5627 info->status_regs[BNXT_FW_STATUS_REG] =
5628 rte_le_to_cpu_32(resp->fw_health_status_reg);
5629 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5630 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5631 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5632 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5633 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5634 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5635 info->reg_array_cnt =
5636 rte_le_to_cpu_32(resp->reg_array_cnt);
5638 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5643 for (i = 0; i < info->reg_array_cnt; i++) {
5644 info->reset_reg[i] =
5645 rte_le_to_cpu_32(resp->reset_reg[i]);
5646 info->reset_reg_val[i] =
5647 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5648 info->delay_after_reset[i] =
5649 resp->delay_after_reset[i];
5654 /* Map the FW status registers */
5656 rc = bnxt_map_fw_health_status_regs(bp);
5659 rte_free(bp->recovery_info);
5660 bp->recovery_info = NULL;
5665 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5667 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5668 struct hwrm_fw_reset_input req = {0};
5674 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5676 req.embedded_proc_type =
5677 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5678 req.selfrst_status =
5679 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5680 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5682 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5685 HWRM_CHECK_RESULT();
5691 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5693 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5694 struct hwrm_port_ts_query_input req = {0};
5695 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5702 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5705 case BNXT_PTP_FLAGS_PATH_TX:
5706 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5708 case BNXT_PTP_FLAGS_PATH_RX:
5709 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5711 case BNXT_PTP_FLAGS_CURRENT_TIME:
5712 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5716 req.flags = rte_cpu_to_le_32(flags);
5717 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5719 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5721 HWRM_CHECK_RESULT();
5724 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5726 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5733 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5737 struct hwrm_cfa_counter_qcaps_input req = {0};
5738 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5740 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5742 "Not a PF or trusted VF. Command not supported\n");
5746 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5747 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5748 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5750 HWRM_CHECK_RESULT();
5752 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5758 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5761 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5762 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5764 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5766 "Not a PF or trusted VF. Command not supported\n");
5770 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5772 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5773 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5774 req.page_dir = rte_cpu_to_le_64(dma_addr);
5776 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5778 HWRM_CHECK_RESULT();
5780 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5781 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5788 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5791 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5792 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5794 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5796 "Not a PF or trusted VF. Command not supported\n");
5800 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5802 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5804 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5806 HWRM_CHECK_RESULT();
5812 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5813 uint16_t cntr, uint16_t ctx_id,
5814 uint32_t num_entries, bool enable)
5816 struct hwrm_cfa_counter_cfg_input req = {0};
5817 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5821 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5823 "Not a PF or trusted VF. Command not supported\n");
5827 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5829 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5830 req.counter_type = rte_cpu_to_le_16(cntr);
5831 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5832 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5833 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5834 if (dir == BNXT_DIR_RX)
5835 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5836 else if (dir == BNXT_DIR_TX)
5837 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5838 req.flags = rte_cpu_to_le_16(flags);
5839 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5840 req.num_entries = rte_cpu_to_le_32(num_entries);
5842 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5843 HWRM_CHECK_RESULT();
5849 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5850 enum bnxt_flow_dir dir,
5852 uint16_t num_entries)
5854 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5855 struct hwrm_cfa_counter_qstats_input req = {0};
5856 uint16_t flow_ctx_id = 0;
5860 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5862 "Not a PF or trusted VF. Command not supported\n");
5866 if (dir == BNXT_DIR_RX) {
5867 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5868 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5869 } else if (dir == BNXT_DIR_TX) {
5870 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5871 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5874 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5875 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5876 req.counter_type = rte_cpu_to_le_16(cntr);
5877 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5878 req.num_entries = rte_cpu_to_le_16(num_entries);
5879 req.flags = rte_cpu_to_le_16(flags);
5880 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5882 HWRM_CHECK_RESULT();
5888 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5889 uint16_t *first_vf_id)
5892 struct hwrm_func_qcaps_input req = {.req_type = 0 };
5893 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5895 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5897 req.fid = rte_cpu_to_le_16(fid);
5899 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5901 HWRM_CHECK_RESULT();
5904 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5911 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5913 struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5914 struct hwrm_cfa_pair_alloc_input req = {0};
5917 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5919 "Not a PF or trusted VF. Command not supported\n");
5923 HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5924 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5925 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5926 bp->eth_dev->data->name, rep_bp->vf_id);
5928 req.pf_b_id = rep_bp->parent_pf_idx;
5929 req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5930 rte_cpu_to_le_16(rep_bp->vf_id);
5931 req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5932 req.host_b_id = 1; /* TBD - Confirm if this is OK */
5934 req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5935 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5936 req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5937 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5938 req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5939 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5940 req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5941 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5943 req.q_ab = rep_bp->rep_q_r2f;
5944 req.q_ba = rep_bp->rep_q_f2r;
5945 req.fc_ab = rep_bp->rep_fc_r2f;
5946 req.fc_ba = rep_bp->rep_fc_f2r;
5948 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5949 HWRM_CHECK_RESULT();
5952 PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5953 BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5957 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5959 struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5960 struct hwrm_cfa_pair_free_input req = {0};
5963 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5965 "Not a PF or trusted VF. Command not supported\n");
5969 HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5970 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5971 bp->eth_dev->data->name, rep_bp->vf_id);
5972 req.pf_b_id = rep_bp->parent_pf_idx;
5973 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5974 req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5975 rte_cpu_to_le_16(rep_bp->vf_id);
5976 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5977 HWRM_CHECK_RESULT();
5979 PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
5984 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5986 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5987 bp->hwrm_cmd_resp_addr;
5988 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5992 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5995 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5997 "Not a PF or trusted VF. Command not supported\n");
6001 HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6002 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6004 HWRM_CHECK_RESULT();
6005 flags = rte_le_to_cpu_32(resp->flags);
6008 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6009 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6011 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6016 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6017 uint32_t echo_req_data2)
6019 struct hwrm_func_echo_response_input req = {0};
6020 struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6023 HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6024 req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6025 req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6027 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6029 HWRM_CHECK_RESULT();
6035 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6037 struct hwrm_ver_get_input req = {.req_type = 0 };
6038 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6041 bp->max_req_len = HWRM_MAX_REQ_LEN;
6042 bp->max_resp_len = BNXT_PAGE_SIZE;
6043 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6045 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6046 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6047 req.hwrm_intf_min = HWRM_VERSION_MINOR;
6048 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6050 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6052 HWRM_CHECK_RESULT_SILENT();
6054 if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)