drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (!BNXT_CHIP_P5(bp) &&
 754             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 755                 return 0;
 756
 757         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 758                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 759
 760         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 761         if (!ptp)
 762                 return -ENOMEM;
 763
 764         if (!BNXT_CHIP_P5(bp)) {
 765                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 766                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 767                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 768                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 769                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 771                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 773                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 775                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 776                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 777                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 778                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 779                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 781                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 783         }
 784
 785         ptp->bp = bp;
 786         bp->ptp_cfg = ptp;
 787
 788         return 0;
 789 }
 790
 791 void bnxt_free_vf_info(struct bnxt *bp)
 792 {
 793         int i;
 794
 795         if (bp->pf == NULL)
 796                 return;
 797
 798         if (bp->pf->vf_info == NULL)
 799                 return;
 800
 801         for (i = 0; i < bp->pf->max_vfs; i++) {
 802                 rte_free(bp->pf->vf_info[i].vlan_table);
 803                 bp->pf->vf_info[i].vlan_table = NULL;
 804                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 805                 bp->pf->vf_info[i].vlan_as_table = NULL;
 806         }
 807         rte_free(bp->pf->vf_info);
 808         bp->pf->vf_info = NULL;
 809 }
 810
 811 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 812 {
 813         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 814         int i;
 815
 816         if (vf_info)
 817                 bnxt_free_vf_info(bp);
 818
 819         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 820         if (vf_info == NULL) {
 821                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 822                 return -ENOMEM;
 823         }
 824
 825         bp->pf->max_vfs = max_vfs;
 826         for (i = 0; i < max_vfs; i++) {
 827                 vf_info[i].fid = bp->pf->first_vf_id + i;
 828                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 829                                                     getpagesize(), getpagesize());
 830                 if (vf_info[i].vlan_table == NULL) {
 831                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 832                         goto err;
 833                 }
 834                 rte_mem_lock_page(vf_info[i].vlan_table);
 835
 836                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 837                                                        getpagesize(), getpagesize());
 838                 if (vf_info[i].vlan_as_table == NULL) {
 839                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 840                         goto err;
 841                 }
 842                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 843
 844                 STAILQ_INIT(&vf_info[i].filter);
 845         }
 846
 847         bp->pf->vf_info = vf_info;
 848
 849         return 0;
 850 err:
 851         bnxt_free_vf_info(bp);
 852         return -ENOMEM;
 853 }
 854
 855 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 856 {
 857         int rc = 0;
 858         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 859         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 860         uint16_t new_max_vfs;
 861         uint32_t flags;
 862
 863         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 864
 865         req.fid = rte_cpu_to_le_16(0xffff);
 866
 867         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 868
 869         HWRM_CHECK_RESULT();
 870
 871         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 872         flags = rte_le_to_cpu_32(resp->flags);
 873         if (BNXT_PF(bp)) {
 874                 bp->pf->port_id = resp->port_id;
 875                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 876                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 877                 new_max_vfs = bp->pdev->max_vfs;
 878                 if (new_max_vfs != bp->pf->max_vfs) {
 879                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 880                         if (rc)
 881                                 goto unlock;
 882                 }
 883         }
 884
 885         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 886         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 887                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 888                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 889         } else {
 890                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 891         }
 892         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 893         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 894         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 895         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 896         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 897         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 898         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 899         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 900                 bp->max_l2_ctx += bp->max_rx_em_flows;
 901         /* TODO: For now, do not support VMDq/RFS on VFs. */
 902         if (BNXT_PF(bp)) {
 903                 if (bp->pf->max_vfs)
 904                         bp->max_vnics = 1;
 905                 else
 906                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 907         } else {
 908                 bp->max_vnics = 1;
 909         }
 910         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 911                     bp->max_l2_ctx, bp->max_vnics);
 912         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 913         if (BNXT_PF(bp)) {
 914                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 915                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 916                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 917                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 918                         HWRM_UNLOCK();
 919                         bnxt_hwrm_ptp_qcfg(bp);
 920                 }
 921         }
 922
 923         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 924                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 925
 926         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 927                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 928                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 929         }
 930
 931         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 932                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 933
 934         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 935                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 936
 937         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 938                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 939
 940 unlock:
 941         HWRM_UNLOCK();
 942
 943         return rc;
 944 }
 945
 946 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 947 {
 948         int rc;
 949
 950         rc = __bnxt_hwrm_func_qcaps(bp);
 951         if (rc == -ENOMEM)
 952                 return rc;
 953
 954         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 955                 rc = bnxt_alloc_ctx_mem(bp);
 956                 if (rc)
 957                         return rc;
 958
 959                 /* On older FW,
 960                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 961                  * But the error can be ignored. Return success.
 962                  */
 963                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 964                 if (!rc)
 965                         bp->flags |= BNXT_FLAG_NEW_RM;
 966         }
 967
 968         return 0;
 969 }
 970
 971 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 972 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 973 {
 974         int rc = 0;
 975         uint32_t flags;
 976         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 977         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 978
 979         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 980
 981         req.target_id = rte_cpu_to_le_16(0xffff);
 982
 983         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 984
 985         HWRM_CHECK_RESULT();
 986
 987         flags = rte_le_to_cpu_32(resp->flags);
 988
 989         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 990                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 991                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 992         }
 993
 994         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 995                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
 996
 997         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
 998                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
 999
1000         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1001
1002         HWRM_UNLOCK();
1003
1004         return rc;
1005 }
1006
1007 int bnxt_hwrm_func_reset(struct bnxt *bp)
1008 {
1009         int rc = 0;
1010         struct hwrm_func_reset_input req = {.req_type = 0 };
1011         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1012
1013         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1014
1015         req.enables = rte_cpu_to_le_32(0);
1016
1017         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1018
1019         HWRM_CHECK_RESULT();
1020         HWRM_UNLOCK();
1021
1022         return rc;
1023 }
1024
1025 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1026 {
1027         int rc;
1028         uint32_t flags = 0;
1029         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1030         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1031
1032         if (bp->flags & BNXT_FLAG_REGISTERED)
1033                 return 0;
1034
1035         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1036                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1037         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1038                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1039
1040         /* PFs and trusted VFs should indicate the support of the
1041          * Master capability on non Stingray platform
1042          */
1043         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1044                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1045
1046         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1047         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1048                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1049         req.ver_maj = RTE_VER_YEAR;
1050         req.ver_min = RTE_VER_MONTH;
1051         req.ver_upd = RTE_VER_MINOR;
1052
1053         if (BNXT_PF(bp)) {
1054                 req.enables |= rte_cpu_to_le_32(
1055                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1056                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1057                        RTE_MIN(sizeof(req.vf_req_fwd),
1058                                sizeof(bp->pf->vf_req_fwd)));
1059         }
1060
1061         req.flags = rte_cpu_to_le_32(flags);
1062
1063         req.async_event_fwd[0] |=
1064                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1065                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1066                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1067                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1068                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1069         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1070                 req.async_event_fwd[0] |=
1071                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1072         req.async_event_fwd[1] |=
1073                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1074                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1075         if (BNXT_PF(bp))
1076                 req.async_event_fwd[1] |=
1077                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1078
1079         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1080                 req.async_event_fwd[1] |=
1081                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1082
1083         req.async_event_fwd[2] |=
1084                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
1085
1086         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1087
1088         HWRM_CHECK_RESULT();
1089
1090         flags = rte_le_to_cpu_32(resp->flags);
1091         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1092                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1093
1094         HWRM_UNLOCK();
1095
1096         bp->flags |= BNXT_FLAG_REGISTERED;
1097
1098         return rc;
1099 }
1100
1101 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1102 {
1103         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1104                 return 0;
1105
1106         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1107 }
1108
1109 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1110 {
1111         int rc;
1112         uint32_t flags = 0;
1113         uint32_t enables;
1114         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1115         struct hwrm_func_vf_cfg_input req = {0};
1116
1117         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1118
1119         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1120                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1121                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1122                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1123                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1124
1125         if (BNXT_HAS_RING_GRPS(bp)) {
1126                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1127                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1128         }
1129
1130         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1131         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1132                                             AGG_RING_MULTIPLIER);
1133         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1134         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1135                                               bp->tx_nr_rings +
1136                                               BNXT_NUM_ASYNC_CPR(bp));
1137         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1138         if (bp->vf_resv_strategy ==
1139             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1140                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1141                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1142                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1143                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1144                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1145                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1146         } else if (bp->vf_resv_strategy ==
1147                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1148                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1149                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1150         }
1151
1152         if (test)
1153                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1154                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1155                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1156                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1157                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1158                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1159
1160         if (test && BNXT_HAS_RING_GRPS(bp))
1161                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1162
1163         req.flags = rte_cpu_to_le_32(flags);
1164         req.enables |= rte_cpu_to_le_32(enables);
1165
1166         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1167
1168         if (test)
1169                 HWRM_CHECK_RESULT_SILENT();
1170         else
1171                 HWRM_CHECK_RESULT();
1172
1173         HWRM_UNLOCK();
1174         return rc;
1175 }
1176
1177 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1178 {
1179         int rc;
1180         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1181         struct hwrm_func_resource_qcaps_input req = {0};
1182
1183         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1184         req.fid = rte_cpu_to_le_16(0xffff);
1185
1186         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1187
1188         HWRM_CHECK_RESULT_SILENT();
1189
1190         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1191         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1192         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1193         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1194         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1195         /* func_resource_qcaps does not return max_rx_em_flows.
1196          * So use the value provided by func_qcaps.
1197          */
1198         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1199         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1200                 bp->max_l2_ctx += bp->max_rx_em_flows;
1201         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1202         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1203         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1204         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1205         if (bp->vf_resv_strategy >
1206             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1207                 bp->vf_resv_strategy =
1208                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1209
1210         HWRM_UNLOCK();
1211         return rc;
1212 }
1213
1214 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1215 {
1216         int rc = 0;
1217         struct hwrm_ver_get_input req = {.req_type = 0 };
1218         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1219         uint32_t fw_version;
1220         uint16_t max_resp_len;
1221         char type[RTE_MEMZONE_NAMESIZE];
1222         uint32_t dev_caps_cfg;
1223
1224         bp->max_req_len = HWRM_MAX_REQ_LEN;
1225         bp->hwrm_cmd_timeout = timeout;
1226         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1227
1228         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1229         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1230         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1231
1232         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1233
1234         if (bp->flags & BNXT_FLAG_FW_RESET)
1235                 HWRM_CHECK_RESULT_SILENT();
1236         else
1237                 HWRM_CHECK_RESULT();
1238
1239         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1240                 rc = -EAGAIN;
1241                 goto error;
1242         }
1243
1244         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1245                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1246                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1247                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1248                 resp->hwrm_fw_rsvd_8b);
1249         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1250                      (resp->hwrm_fw_min_8b << 16) |
1251                      (resp->hwrm_fw_bld_8b << 8) |
1252                      resp->hwrm_fw_rsvd_8b;
1253         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1254                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1255
1256         fw_version = resp->hwrm_intf_maj_8b << 16;
1257         fw_version |= resp->hwrm_intf_min_8b << 8;
1258         fw_version |= resp->hwrm_intf_upd_8b;
1259         bp->hwrm_spec_code = fw_version;
1260
1261         /* def_req_timeout value is in milliseconds */
1262         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1263         /* convert timeout to usec */
1264         bp->hwrm_cmd_timeout *= 1000;
1265         if (!bp->hwrm_cmd_timeout)
1266                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1267
1268         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1269                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1270                 rc = -EINVAL;
1271                 goto error;
1272         }
1273
1274         if (bp->max_req_len > resp->max_req_win_len) {
1275                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1276                 rc = -EINVAL;
1277                 goto error;
1278         }
1279
1280         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1281
1282         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1283         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1284         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1285                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1286
1287         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1288         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1289
1290         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1291         bp->max_resp_len = max_resp_len;
1292
1293         if ((dev_caps_cfg &
1294                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1295             (dev_caps_cfg &
1296              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1297                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1298                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1299         }
1300
1301         if (((dev_caps_cfg &
1302               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1303              (dev_caps_cfg &
1304               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1305             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1306                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1307                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1308                         bp->pdev->addr.devid, bp->pdev->addr.function);
1309
1310                 rte_free(bp->hwrm_short_cmd_req_addr);
1311
1312                 bp->hwrm_short_cmd_req_addr =
1313                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1314                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1315                         rc = -ENOMEM;
1316                         goto error;
1317                 }
1318                 bp->hwrm_short_cmd_req_dma_addr =
1319                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1320                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1321                         rte_free(bp->hwrm_short_cmd_req_addr);
1322                         PMD_DRV_LOG(ERR,
1323                                 "Unable to map buffer to physical memory.\n");
1324                         rc = -ENOMEM;
1325                         goto error;
1326                 }
1327         }
1328         if (dev_caps_cfg &
1329             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1330                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1331                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1332         }
1333         if (dev_caps_cfg &
1334             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1335                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1336         if (dev_caps_cfg &
1337             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1338                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1339                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1340         }
1341
1342         if (dev_caps_cfg &
1343             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1344                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1345                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1346         }
1347
1348 error:
1349         HWRM_UNLOCK();
1350         return rc;
1351 }
1352
1353 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1354 {
1355         int rc;
1356         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1357         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1358
1359         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1360                 return 0;
1361
1362         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1363         req.flags = flags;
1364
1365         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1366
1367         HWRM_CHECK_RESULT();
1368         HWRM_UNLOCK();
1369
1370         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1371                     bp->eth_dev->data->port_id);
1372
1373         return rc;
1374 }
1375
1376 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1377 {
1378         int rc = 0;
1379         struct hwrm_port_phy_cfg_input req = {0};
1380         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1381         uint32_t enables = 0;
1382
1383         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1384
1385         if (conf->link_up) {
1386                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1387                 if (bp->link_info->auto_mode && conf->link_speed) {
1388                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1389                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1390                 }
1391
1392                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1393                 /*
1394                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1395                  * any auto mode, even "none".
1396                  */
1397                 if (!conf->link_speed) {
1398                         /* No speeds specified. Enable AutoNeg - all speeds */
1399                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1400                         req.auto_mode =
1401                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1402                 } else {
1403                         if (bp->link_info->link_signal_mode) {
1404                                 enables |=
1405                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1406                                 req.force_pam4_link_speed =
1407                                         rte_cpu_to_le_16(conf->link_speed);
1408                         } else {
1409                                 req.force_link_speed =
1410                                         rte_cpu_to_le_16(conf->link_speed);
1411                         }
1412                 }
1413                 /* AutoNeg - Advertise speeds specified. */
1414                 if (conf->auto_link_speed_mask &&
1415                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1416                         req.auto_mode =
1417                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1418                         req.auto_link_speed_mask =
1419                                 conf->auto_link_speed_mask;
1420                         if (conf->auto_pam4_link_speeds) {
1421                                 enables |=
1422                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1423                                 req.auto_link_pam4_speed_mask =
1424                                         conf->auto_pam4_link_speeds;
1425                         } else {
1426                                 enables |=
1427                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1428                         }
1429                 }
1430                 if (conf->auto_link_speed &&
1431                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1432                         enables |=
1433                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1434
1435                 req.auto_duplex = conf->duplex;
1436                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1437                 req.auto_pause = conf->auto_pause;
1438                 req.force_pause = conf->force_pause;
1439                 /* Set force_pause if there is no auto or if there is a force */
1440                 if (req.auto_pause && !req.force_pause)
1441                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1442                 else
1443                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1444
1445                 req.enables = rte_cpu_to_le_32(enables);
1446         } else {
1447                 req.flags =
1448                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1449                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1450         }
1451
1452         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1453
1454         HWRM_CHECK_RESULT();
1455         HWRM_UNLOCK();
1456
1457         return rc;
1458 }
1459
1460 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1461                                    struct bnxt_link_info *link_info)
1462 {
1463         int rc = 0;
1464         struct hwrm_port_phy_qcfg_input req = {0};
1465         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1466
1467         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1468
1469         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1470
1471         HWRM_CHECK_RESULT();
1472
1473         link_info->phy_link_status = resp->link;
1474         link_info->link_up =
1475                 (link_info->phy_link_status ==
1476                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1477         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1478         link_info->duplex = resp->duplex_cfg;
1479         link_info->pause = resp->pause;
1480         link_info->auto_pause = resp->auto_pause;
1481         link_info->force_pause = resp->force_pause;
1482         link_info->auto_mode = resp->auto_mode;
1483         link_info->phy_type = resp->phy_type;
1484         link_info->media_type = resp->media_type;
1485
1486         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1487         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1488         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1489         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1490         link_info->phy_ver[0] = resp->phy_maj;
1491         link_info->phy_ver[1] = resp->phy_min;
1492         link_info->phy_ver[2] = resp->phy_bld;
1493         link_info->link_signal_mode =
1494                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1495         link_info->force_pam4_link_speed =
1496                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1497         link_info->support_pam4_speeds =
1498                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1499         link_info->auto_pam4_link_speeds =
1500                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1501         HWRM_UNLOCK();
1502
1503         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1504                     link_info->link_speed, link_info->auto_mode,
1505                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1506                     link_info->support_speeds, link_info->force_link_speed);
1507         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1508                     link_info->link_signal_mode,
1509                     link_info->auto_pam4_link_speeds,
1510                     link_info->support_pam4_speeds,
1511                     link_info->force_pam4_link_speed);
1512         return rc;
1513 }
1514
1515 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1516 {
1517         int rc = 0;
1518         struct hwrm_port_phy_qcaps_input req = {0};
1519         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1520         struct bnxt_link_info *link_info = bp->link_info;
1521
1522         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1523                 return 0;
1524
1525         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1526
1527         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1528
1529         HWRM_CHECK_RESULT_SILENT();
1530
1531         bp->port_cnt = resp->port_cnt;
1532         if (resp->supported_speeds_auto_mode)
1533                 link_info->support_auto_speeds =
1534                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1535         if (resp->supported_pam4_speeds_auto_mode)
1536                 link_info->support_pam4_auto_speeds =
1537                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1538
1539         HWRM_UNLOCK();
1540
1541         return 0;
1542 }
1543
1544 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1545 {
1546         int i = 0;
1547
1548         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1549                 if (bp->tx_cos_queue[i].profile ==
1550                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1551                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1552                         return true;
1553                 }
1554         }
1555         return false;
1556 }
1557
1558 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1559 {
1560         int i = 0;
1561
1562         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1563                 if (bp->tx_cos_queue[i].profile !=
1564                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1565                     bp->tx_cos_queue[i].id !=
1566                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1567                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1568                         break;
1569                 }
1570         }
1571 }
1572
1573 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1574 {
1575         int rc = 0;
1576         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1577         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1578         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1579         int i;
1580
1581 get_rx_info:
1582         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1583
1584         req.flags = rte_cpu_to_le_32(dir);
1585         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1586         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1587             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1588                 req.drv_qmap_cap =
1589                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1590         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1591
1592         HWRM_CHECK_RESULT();
1593
1594         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1595                 GET_TX_QUEUE_INFO(0);
1596                 GET_TX_QUEUE_INFO(1);
1597                 GET_TX_QUEUE_INFO(2);
1598                 GET_TX_QUEUE_INFO(3);
1599                 GET_TX_QUEUE_INFO(4);
1600                 GET_TX_QUEUE_INFO(5);
1601                 GET_TX_QUEUE_INFO(6);
1602                 GET_TX_QUEUE_INFO(7);
1603         } else  {
1604                 GET_RX_QUEUE_INFO(0);
1605                 GET_RX_QUEUE_INFO(1);
1606                 GET_RX_QUEUE_INFO(2);
1607                 GET_RX_QUEUE_INFO(3);
1608                 GET_RX_QUEUE_INFO(4);
1609                 GET_RX_QUEUE_INFO(5);
1610                 GET_RX_QUEUE_INFO(6);
1611                 GET_RX_QUEUE_INFO(7);
1612         }
1613
1614         HWRM_UNLOCK();
1615
1616         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1617                 goto done;
1618
1619         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1620                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1621         } else {
1622                 int j;
1623
1624                 /* iterate and find the COSq profile to use for Tx */
1625                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1626                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1627                                 if (bp->tx_cos_queue[i].id != 0xff)
1628                                         bp->tx_cosq_id[j++] =
1629                                                 bp->tx_cos_queue[i].id;
1630                         }
1631                 } else {
1632                         /* When CoS classification is disabled, for normal NIC
1633                          * operations, ideally we should look to use LOSSY.
1634                          * If not found, fallback to the first valid profile
1635                          */
1636                         if (!bnxt_find_lossy_profile(bp))
1637                                 bnxt_find_first_valid_profile(bp);
1638
1639                 }
1640         }
1641
1642         bp->max_tc = resp->max_configurable_queues;
1643         bp->max_lltc = resp->max_configurable_lossless_queues;
1644         if (bp->max_tc > BNXT_MAX_QUEUE)
1645                 bp->max_tc = BNXT_MAX_QUEUE;
1646         bp->max_q = bp->max_tc;
1647
1648         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1649                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1650                 goto get_rx_info;
1651         }
1652
1653 done:
1654         return rc;
1655 }
1656
1657 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1658                          struct bnxt_ring *ring,
1659                          uint32_t ring_type, uint32_t map_index,
1660                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1661                          uint16_t tx_cosq_id)
1662 {
1663         int rc = 0;
1664         uint32_t enables = 0;
1665         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1666         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1667         struct rte_mempool *mb_pool;
1668         uint16_t rx_buf_size;
1669
1670         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1671
1672         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1673         req.fbo = rte_cpu_to_le_32(0);
1674         /* Association of ring index with doorbell index */
1675         req.logical_id = rte_cpu_to_le_16(map_index);
1676         req.length = rte_cpu_to_le_32(ring->ring_size);
1677
1678         switch (ring_type) {
1679         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1680                 req.ring_type = ring_type;
1681                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1682                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1683                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1684                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1685                         enables |=
1686                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1687                 break;
1688         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1689                 req.ring_type = ring_type;
1690                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1691                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1692                 if (BNXT_CHIP_P5(bp)) {
1693                         mb_pool = bp->rx_queues[0]->mb_pool;
1694                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1695                                       RTE_PKTMBUF_HEADROOM;
1696                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1697                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1698                         enables |=
1699                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1700                 }
1701                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1702                         enables |=
1703                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1704                 break;
1705         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1706                 req.ring_type = ring_type;
1707                 if (BNXT_HAS_NQ(bp)) {
1708                         /* Association of cp ring with nq */
1709                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1710                         enables |=
1711                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1712                 }
1713                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1714                 break;
1715         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1716                 req.ring_type = ring_type;
1717                 req.page_size = BNXT_PAGE_SHFT;
1718                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1719                 break;
1720         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1721                 req.ring_type = ring_type;
1722                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1723
1724                 mb_pool = bp->rx_queues[0]->mb_pool;
1725                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1726                               RTE_PKTMBUF_HEADROOM;
1727                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1728                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1729
1730                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1731                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1732                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1733                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1734                 break;
1735         default:
1736                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1737                         ring_type);
1738                 HWRM_UNLOCK();
1739                 return -EINVAL;
1740         }
1741         req.enables = rte_cpu_to_le_32(enables);
1742
1743         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1744
1745         if (rc || resp->error_code) {
1746                 if (rc == 0 && resp->error_code)
1747                         rc = rte_le_to_cpu_16(resp->error_code);
1748                 switch (ring_type) {
1749                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1750                         PMD_DRV_LOG(ERR,
1751                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1752                         HWRM_UNLOCK();
1753                         return rc;
1754                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1755                         PMD_DRV_LOG(ERR,
1756                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1757                         HWRM_UNLOCK();
1758                         return rc;
1759                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1760                         PMD_DRV_LOG(ERR,
1761                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1762                                     rc);
1763                         HWRM_UNLOCK();
1764                         return rc;
1765                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1766                         PMD_DRV_LOG(ERR,
1767                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1768                         HWRM_UNLOCK();
1769                         return rc;
1770                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1771                         PMD_DRV_LOG(ERR,
1772                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1773                         HWRM_UNLOCK();
1774                         return rc;
1775                 default:
1776                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1777                         HWRM_UNLOCK();
1778                         return rc;
1779                 }
1780         }
1781
1782         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1783         HWRM_UNLOCK();
1784         return rc;
1785 }
1786
1787 int bnxt_hwrm_ring_free(struct bnxt *bp,
1788                         struct bnxt_ring *ring, uint32_t ring_type,
1789                         uint16_t cp_ring_id)
1790 {
1791         int rc;
1792         struct hwrm_ring_free_input req = {.req_type = 0 };
1793         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1794
1795         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1796
1797         req.ring_type = ring_type;
1798         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1799         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1800
1801         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1802
1803         if (rc || resp->error_code) {
1804                 if (rc == 0 && resp->error_code)
1805                         rc = rte_le_to_cpu_16(resp->error_code);
1806                 HWRM_UNLOCK();
1807
1808                 switch (ring_type) {
1809                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1810                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1811                                 rc);
1812                         return rc;
1813                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1814                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1815                                 rc);
1816                         return rc;
1817                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1818                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1819                                 rc);
1820                         return rc;
1821                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1822                         PMD_DRV_LOG(ERR,
1823                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1824                         return rc;
1825                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1826                         PMD_DRV_LOG(ERR,
1827                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1828                         return rc;
1829                 default:
1830                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1831                         return rc;
1832                 }
1833         }
1834         HWRM_UNLOCK();
1835         return 0;
1836 }
1837
1838 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1839 {
1840         int rc = 0;
1841         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1842         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1843
1844         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1845
1846         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1847         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1848         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1849         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1850
1851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1852
1853         HWRM_CHECK_RESULT();
1854
1855         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1856
1857         HWRM_UNLOCK();
1858
1859         return rc;
1860 }
1861
1862 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1863 {
1864         int rc;
1865         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1866         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1867
1868         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1869
1870         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1871
1872         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1873
1874         HWRM_CHECK_RESULT();
1875         HWRM_UNLOCK();
1876
1877         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1878         return rc;
1879 }
1880
1881 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1882 {
1883         int rc = 0;
1884         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1885         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1886
1887         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1888                 return rc;
1889
1890         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1891
1892         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1893
1894         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1895
1896         HWRM_CHECK_RESULT();
1897         HWRM_UNLOCK();
1898
1899         return rc;
1900 }
1901
1902 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1903 {
1904         int rc;
1905         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1906         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1907
1908         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1909
1910         req.update_period_ms = rte_cpu_to_le_32(0);
1911
1912         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1913
1914         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1915
1916         HWRM_CHECK_RESULT();
1917
1918         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1919
1920         HWRM_UNLOCK();
1921
1922         return rc;
1923 }
1924
1925 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1926 {
1927         int rc;
1928         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1929         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1930
1931         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1932
1933         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1934
1935         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1936
1937         HWRM_CHECK_RESULT();
1938         HWRM_UNLOCK();
1939
1940         return rc;
1941 }
1942
1943 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1944 {
1945         int rc = 0, i, j;
1946         struct hwrm_vnic_alloc_input req = { 0 };
1947         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1948
1949         if (!BNXT_HAS_RING_GRPS(bp))
1950                 goto skip_ring_grps;
1951
1952         /* map ring groups to this vnic */
1953         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1954                 vnic->start_grp_id, vnic->end_grp_id);
1955         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1956                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1957
1958         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1959         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1960         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1961         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1962
1963 skip_ring_grps:
1964         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1965         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1966
1967         if (vnic->func_default)
1968                 req.flags =
1969                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1970         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1971
1972         HWRM_CHECK_RESULT();
1973
1974         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1975         HWRM_UNLOCK();
1976         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1977         return rc;
1978 }
1979
1980 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1981                                         struct bnxt_vnic_info *vnic,
1982                                         struct bnxt_plcmodes_cfg *pmode)
1983 {
1984         int rc = 0;
1985         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1986         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1987
1988         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1989
1990         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1991
1992         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1993
1994         HWRM_CHECK_RESULT();
1995
1996         pmode->flags = rte_le_to_cpu_32(resp->flags);
1997         /* dflt_vnic bit doesn't exist in the _cfg command */
1998         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1999         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2000         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2001         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2002
2003         HWRM_UNLOCK();
2004
2005         return rc;
2006 }
2007
2008 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2009                                        struct bnxt_vnic_info *vnic,
2010                                        struct bnxt_plcmodes_cfg *pmode)
2011 {
2012         int rc = 0;
2013         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2014         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2015
2016         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2017                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2018                 return rc;
2019         }
2020
2021         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2022
2023         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2024         req.flags = rte_cpu_to_le_32(pmode->flags);
2025         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2026         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2027         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2028         req.enables = rte_cpu_to_le_32(
2029             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2030             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2031             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2032         );
2033
2034         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2035
2036         HWRM_CHECK_RESULT();
2037         HWRM_UNLOCK();
2038
2039         return rc;
2040 }
2041
2042 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2043 {
2044         int rc = 0;
2045         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2046         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2047         struct bnxt_plcmodes_cfg pmodes = { 0 };
2048         uint32_t ctx_enable_flag = 0;
2049         uint32_t enables = 0;
2050
2051         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2052                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2053                 return rc;
2054         }
2055
2056         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2057         if (rc)
2058                 return rc;
2059
2060         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2061
2062         if (BNXT_CHIP_P5(bp)) {
2063                 int dflt_rxq = vnic->start_grp_id;
2064                 struct bnxt_rx_ring_info *rxr;
2065                 struct bnxt_cp_ring_info *cpr;
2066                 struct bnxt_rx_queue *rxq;
2067                 int i;
2068
2069                 /*
2070                  * The first active receive ring is used as the VNIC
2071                  * default receive ring. If there are no active receive
2072                  * rings (all corresponding receive queues are stopped),
2073                  * the first receive ring is used.
2074                  */
2075                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2076                         rxq = bp->eth_dev->data->rx_queues[i];
2077                         if (rxq->rx_started) {
2078                                 dflt_rxq = i;
2079                                 break;
2080                         }
2081                 }
2082
2083                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2084                 rxr = rxq->rx_ring;
2085                 cpr = rxq->cp_ring;
2086
2087                 req.default_rx_ring_id =
2088                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2089                 req.default_cmpl_ring_id =
2090                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2091                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2092                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2093                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2094                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2095                         req.rx_csum_v2_mode =
2096                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2097                 }
2098                 goto config_mru;
2099         }
2100
2101         /* Only RSS support for now TBD: COS & LB */
2102         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2103         if (vnic->lb_rule != 0xffff)
2104                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2105         if (vnic->cos_rule != 0xffff)
2106                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2107         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2108                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2109                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2110         }
2111         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2112                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2113                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2114         }
2115
2116         enables |= ctx_enable_flag;
2117         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2118         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2119         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2120         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2121
2122 config_mru:
2123         req.enables = rte_cpu_to_le_32(enables);
2124         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2125         req.mru = rte_cpu_to_le_16(vnic->mru);
2126         /* Configure default VNIC only once. */
2127         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2128                 req.flags |=
2129                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2130                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2131         }
2132         if (vnic->vlan_strip)
2133                 req.flags |=
2134                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2135         if (vnic->bd_stall)
2136                 req.flags |=
2137                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2138         if (vnic->rss_dflt_cr)
2139                 req.flags |= rte_cpu_to_le_32(
2140                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2141
2142         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2143
2144         HWRM_CHECK_RESULT();
2145         HWRM_UNLOCK();
2146
2147         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2148
2149         return rc;
2150 }
2151
2152 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2153                 int16_t fw_vf_id)
2154 {
2155         int rc = 0;
2156         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2157         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2158
2159         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2160                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2161                 return rc;
2162         }
2163         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2164
2165         req.enables =
2166                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2167         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2168         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2169
2170         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2171
2172         HWRM_CHECK_RESULT();
2173
2174         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2175         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2176         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2177         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2178         vnic->mru = rte_le_to_cpu_16(resp->mru);
2179         vnic->func_default = rte_le_to_cpu_32(
2180                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2181         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2182                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2183         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2184                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2185         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2186                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2187
2188         HWRM_UNLOCK();
2189
2190         return rc;
2191 }
2192
2193 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2194                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2195 {
2196         int rc = 0;
2197         uint16_t ctx_id;
2198         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2199         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2200                                                 bp->hwrm_cmd_resp_addr;
2201
2202         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2203
2204         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2205         HWRM_CHECK_RESULT();
2206
2207         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2208         if (!BNXT_HAS_RING_GRPS(bp))
2209                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2210         else if (ctx_idx == 0)
2211                 vnic->rss_rule = ctx_id;
2212
2213         HWRM_UNLOCK();
2214
2215         return rc;
2216 }
2217
2218 static
2219 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2220                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2221 {
2222         int rc = 0;
2223         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2224         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2225                                                 bp->hwrm_cmd_resp_addr;
2226
2227         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2228                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2229                 return rc;
2230         }
2231         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2232
2233         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2234
2235         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2236
2237         HWRM_CHECK_RESULT();
2238         HWRM_UNLOCK();
2239
2240         return rc;
2241 }
2242
2243 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2244 {
2245         int rc = 0;
2246
2247         if (BNXT_CHIP_P5(bp)) {
2248                 int j;
2249
2250                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2251                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2252                                                       vnic,
2253                                                       vnic->fw_grp_ids[j]);
2254                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2255                 }
2256                 vnic->num_lb_ctxts = 0;
2257         } else {
2258                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2259                 vnic->rss_rule = INVALID_HW_RING_ID;
2260         }
2261
2262         return rc;
2263 }
2264
2265 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2266 {
2267         int rc = 0;
2268         struct hwrm_vnic_free_input req = {.req_type = 0 };
2269         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2270
2271         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2272                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2273                 return rc;
2274         }
2275
2276         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2277
2278         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2279
2280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2281
2282         HWRM_CHECK_RESULT();
2283         HWRM_UNLOCK();
2284
2285         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2286         /* Configure default VNIC again if necessary. */
2287         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2288                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2289
2290         return rc;
2291 }
2292
2293 static int
2294 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2295 {
2296         int i;
2297         int rc = 0;
2298         int nr_ctxs = vnic->num_lb_ctxts;
2299         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2300         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2301
2302         for (i = 0; i < nr_ctxs; i++) {
2303                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2304
2305                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2306                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2307                 req.hash_mode_flags = vnic->hash_mode;
2308
2309                 req.hash_key_tbl_addr =
2310                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2311
2312                 req.ring_grp_tbl_addr =
2313                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2314                                          i * HW_HASH_INDEX_SIZE);
2315                 req.ring_table_pair_index = i;
2316                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2317
2318                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2319                                             BNXT_USE_CHIMP_MB);
2320
2321                 HWRM_CHECK_RESULT();
2322                 HWRM_UNLOCK();
2323         }
2324
2325         return rc;
2326 }
2327
2328 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2329                            struct bnxt_vnic_info *vnic)
2330 {
2331         int rc = 0;
2332         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2333         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2334
2335         if (!vnic->rss_table)
2336                 return 0;
2337
2338         if (BNXT_CHIP_P5(bp))
2339                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2340
2341         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2342
2343         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2344         req.hash_mode_flags = vnic->hash_mode;
2345
2346         req.ring_grp_tbl_addr =
2347             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2348         req.hash_key_tbl_addr =
2349             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2350         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2351         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2352
2353         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2354
2355         HWRM_CHECK_RESULT();
2356         HWRM_UNLOCK();
2357
2358         return rc;
2359 }
2360
2361 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2362                         struct bnxt_vnic_info *vnic)
2363 {
2364         int rc = 0;
2365         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2366         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2367         uint16_t size;
2368
2369         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2370                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2371                 return rc;
2372         }
2373
2374         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2375
2376         req.flags = rte_cpu_to_le_32(
2377                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2378
2379         req.enables = rte_cpu_to_le_32(
2380                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2381
2382         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2383         size -= RTE_PKTMBUF_HEADROOM;
2384         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2385
2386         req.jumbo_thresh = rte_cpu_to_le_16(size);
2387         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2388
2389         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2390
2391         HWRM_CHECK_RESULT();
2392         HWRM_UNLOCK();
2393
2394         return rc;
2395 }
2396
2397 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2398                         struct bnxt_vnic_info *vnic, bool enable)
2399 {
2400         int rc = 0;
2401         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2402         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2403
2404         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2405                 if (enable)
2406                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2407                 return -ENOTSUP;
2408         }
2409
2410         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2411                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2412                 return 0;
2413         }
2414
2415         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2416
2417         if (enable) {
2418                 req.enables = rte_cpu_to_le_32(
2419                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2420                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2421                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2422                 req.flags = rte_cpu_to_le_32(
2423                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2424                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2425                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2426                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2427                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2428                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2429                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2430                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2431                 req.min_agg_len = rte_cpu_to_le_32(512);
2432         }
2433         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2434
2435         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2436
2437         HWRM_CHECK_RESULT();
2438         HWRM_UNLOCK();
2439
2440         return rc;
2441 }
2442
2443 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2444 {
2445         struct hwrm_func_cfg_input req = {0};
2446         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2447         int rc;
2448
2449         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2450         req.enables = rte_cpu_to_le_32(
2451                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2452         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2453         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2454
2455         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2456
2457         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2458         HWRM_CHECK_RESULT();
2459         HWRM_UNLOCK();
2460
2461         bp->pf->vf_info[vf].random_mac = false;
2462
2463         return rc;
2464 }
2465
2466 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2467                                   uint64_t *dropped)
2468 {
2469         int rc = 0;
2470         struct hwrm_func_qstats_input req = {.req_type = 0};
2471         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2472
2473         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2474
2475         req.fid = rte_cpu_to_le_16(fid);
2476
2477         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2478
2479         HWRM_CHECK_RESULT();
2480
2481         if (dropped)
2482                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2483
2484         HWRM_UNLOCK();
2485
2486         return rc;
2487 }
2488
2489 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2490                           struct rte_eth_stats *stats,
2491                           struct hwrm_func_qstats_output *func_qstats)
2492 {
2493         int rc = 0;
2494         struct hwrm_func_qstats_input req = {.req_type = 0};
2495         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2496
2497         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2498
2499         req.fid = rte_cpu_to_le_16(fid);
2500
2501         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2502
2503         HWRM_CHECK_RESULT();
2504         if (func_qstats)
2505                 memcpy(func_qstats, resp,
2506                        sizeof(struct hwrm_func_qstats_output));
2507
2508         if (!stats)
2509                 goto exit;
2510
2511         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2512         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2513         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2514         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2515         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2516         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2517
2518         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2519         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2520         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2521         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2522         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2523         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2524
2525         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2526         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2527         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2528
2529 exit:
2530         HWRM_UNLOCK();
2531
2532         return rc;
2533 }
2534
2535 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2536 {
2537         int rc = 0;
2538         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2539         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2540
2541         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2542
2543         req.fid = rte_cpu_to_le_16(fid);
2544
2545         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2546
2547         HWRM_CHECK_RESULT();
2548         HWRM_UNLOCK();
2549
2550         return rc;
2551 }
2552
2553 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2554 {
2555         unsigned int i;
2556         int rc = 0;
2557
2558         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2559                 struct bnxt_tx_queue *txq;
2560                 struct bnxt_rx_queue *rxq;
2561                 struct bnxt_cp_ring_info *cpr;
2562
2563                 if (i >= bp->rx_cp_nr_rings) {
2564                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2565                         cpr = txq->cp_ring;
2566                 } else {
2567                         rxq = bp->rx_queues[i];
2568                         cpr = rxq->cp_ring;
2569                 }
2570
2571                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2572                 if (rc)
2573                         return rc;
2574         }
2575         return 0;
2576 }
2577
2578 static int
2579 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2580 {
2581         int rc;
2582         unsigned int i;
2583         struct bnxt_cp_ring_info *cpr;
2584
2585         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2586
2587                 if (i >= bp->rx_cp_nr_rings) {
2588                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2589                 } else {
2590                         cpr = bp->rx_queues[i]->cp_ring;
2591                         if (BNXT_HAS_RING_GRPS(bp))
2592                                 bp->grp_info[i].fw_stats_ctx = -1;
2593                 }
2594                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2595                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2596                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2597                         if (rc)
2598                                 return rc;
2599                 }
2600         }
2601         return 0;
2602 }
2603
2604 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2605 {
2606         unsigned int i;
2607         int rc = 0;
2608
2609         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2610                 struct bnxt_tx_queue *txq;
2611                 struct bnxt_rx_queue *rxq;
2612                 struct bnxt_cp_ring_info *cpr;
2613
2614                 if (i >= bp->rx_cp_nr_rings) {
2615                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2616                         cpr = txq->cp_ring;
2617                 } else {
2618                         rxq = bp->rx_queues[i];
2619                         cpr = rxq->cp_ring;
2620                 }
2621
2622                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2623
2624                 if (rc)
2625                         return rc;
2626         }
2627         return rc;
2628 }
2629
2630 static int
2631 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2632 {
2633         uint16_t idx;
2634         uint32_t rc = 0;
2635
2636         if (!BNXT_HAS_RING_GRPS(bp))
2637                 return 0;
2638
2639         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2640
2641                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2642                         continue;
2643
2644                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2645
2646                 if (rc)
2647                         return rc;
2648         }
2649         return rc;
2650 }
2651
2652 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2653 {
2654         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2655
2656         bnxt_hwrm_ring_free(bp, cp_ring,
2657                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2658                             INVALID_HW_RING_ID);
2659         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2660         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2661                                      sizeof(*cpr->cp_desc_ring));
2662         cpr->cp_raw_cons = 0;
2663         cpr->valid = 0;
2664 }
2665
2666 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2667 {
2668         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2669
2670         bnxt_hwrm_ring_free(bp, cp_ring,
2671                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2672                         INVALID_HW_RING_ID);
2673         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2674         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2675                         sizeof(*cpr->cp_desc_ring));
2676         cpr->cp_raw_cons = 0;
2677         cpr->valid = 0;
2678 }
2679
2680 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2681 {
2682         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2683         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2684         struct bnxt_ring *ring = rxr->rx_ring_struct;
2685         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2686
2687         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2688                 bnxt_hwrm_ring_free(bp, ring,
2689                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2690                                     cpr->cp_ring_struct->fw_ring_id);
2691                 ring->fw_ring_id = INVALID_HW_RING_ID;
2692                 if (BNXT_HAS_RING_GRPS(bp))
2693                         bp->grp_info[queue_index].rx_fw_ring_id =
2694                                                         INVALID_HW_RING_ID;
2695         }
2696         ring = rxr->ag_ring_struct;
2697         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2698                 bnxt_hwrm_ring_free(bp, ring,
2699                                     BNXT_CHIP_P5(bp) ?
2700                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2701                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2702                                     cpr->cp_ring_struct->fw_ring_id);
2703                 if (BNXT_HAS_RING_GRPS(bp))
2704                         bp->grp_info[queue_index].ag_fw_ring_id =
2705                                                         INVALID_HW_RING_ID;
2706         }
2707         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2708                 bnxt_free_cp_ring(bp, cpr);
2709
2710         if (BNXT_HAS_RING_GRPS(bp))
2711                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2712 }
2713
2714 static int
2715 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2716 {
2717         unsigned int i;
2718
2719         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2720                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2721                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2722                 struct bnxt_ring *ring = txr->tx_ring_struct;
2723                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2724
2725                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2726                         bnxt_hwrm_ring_free(bp, ring,
2727                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX,
2728                                         cpr->cp_ring_struct->fw_ring_id);
2729                         ring->fw_ring_id = INVALID_HW_RING_ID;
2730                         memset(txr->tx_desc_ring, 0,
2731                                         txr->tx_ring_struct->ring_size *
2732                                         sizeof(*txr->tx_desc_ring));
2733                         memset(txr->tx_buf_ring, 0,
2734                                         txr->tx_ring_struct->ring_size *
2735                                         sizeof(*txr->tx_buf_ring));
2736                         txr->tx_raw_prod = 0;
2737                         txr->tx_raw_cons = 0;
2738                 }
2739                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2740                         bnxt_free_cp_ring(bp, cpr);
2741                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2742                 }
2743         }
2744
2745         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2746                 bnxt_free_hwrm_rx_ring(bp, i);
2747
2748         return 0;
2749 }
2750
2751 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2752 {
2753         uint16_t i;
2754         uint32_t rc = 0;
2755
2756         if (!BNXT_HAS_RING_GRPS(bp))
2757                 return 0;
2758
2759         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2760                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2761                 if (rc)
2762                         return rc;
2763         }
2764         return rc;
2765 }
2766
2767 /*
2768  * HWRM utility functions
2769  */
2770
2771 void bnxt_free_hwrm_resources(struct bnxt *bp)
2772 {
2773         /* Release memzone */
2774         rte_free(bp->hwrm_cmd_resp_addr);
2775         rte_free(bp->hwrm_short_cmd_req_addr);
2776         bp->hwrm_cmd_resp_addr = NULL;
2777         bp->hwrm_short_cmd_req_addr = NULL;
2778         bp->hwrm_cmd_resp_dma_addr = 0;
2779         bp->hwrm_short_cmd_req_dma_addr = 0;
2780 }
2781
2782 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2783 {
2784         struct rte_pci_device *pdev = bp->pdev;
2785         char type[RTE_MEMZONE_NAMESIZE];
2786
2787         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2788                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2789         bp->max_resp_len = BNXT_PAGE_SIZE;
2790         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2791         if (bp->hwrm_cmd_resp_addr == NULL)
2792                 return -ENOMEM;
2793         bp->hwrm_cmd_resp_dma_addr =
2794                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2795         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2796                 PMD_DRV_LOG(ERR,
2797                         "unable to map response address to physical memory\n");
2798                 return -ENOMEM;
2799         }
2800         rte_spinlock_init(&bp->hwrm_lock);
2801
2802         return 0;
2803 }
2804
2805 int
2806 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2807 {
2808         int rc = 0;
2809
2810         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2811                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2812                 if (rc)
2813                         return rc;
2814         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2815                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2816                 if (rc)
2817                         return rc;
2818         }
2819
2820         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2821         return rc;
2822 }
2823
2824 static int
2825 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2826 {
2827         struct bnxt_filter_info *filter;
2828         int rc = 0;
2829
2830         STAILQ_FOREACH(filter, &vnic->filter, next) {
2831                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2832                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2833                 bnxt_free_filter(bp, filter);
2834         }
2835         return rc;
2836 }
2837
2838 static int
2839 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2840 {
2841         struct bnxt_filter_info *filter;
2842         struct rte_flow *flow;
2843         int rc = 0;
2844
2845         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2846                 flow = STAILQ_FIRST(&vnic->flow_list);
2847                 filter = flow->filter;
2848                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2849                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2850
2851                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2852                 rte_free(flow);
2853         }
2854         return rc;
2855 }
2856
2857 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2858 {
2859         struct bnxt_filter_info *filter;
2860         int rc = 0;
2861
2862         STAILQ_FOREACH(filter, &vnic->filter, next) {
2863                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2864                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2865                                                      filter);
2866                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2867                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2868                                                          filter);
2869                 else
2870                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2871                                                      filter);
2872                 if (rc)
2873                         break;
2874         }
2875         return rc;
2876 }
2877
2878 static void
2879 bnxt_free_tunnel_ports(struct bnxt *bp)
2880 {
2881         if (bp->vxlan_port_cnt)
2882                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2883                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2884
2885         if (bp->geneve_port_cnt)
2886                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2887                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2888 }
2889
2890 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2891 {
2892         int i;
2893
2894         if (bp->vnic_info == NULL)
2895                 return;
2896
2897         /*
2898          * Cleanup VNICs in reverse order, to make sure the L2 filter
2899          * from vnic0 is last to be cleaned up.
2900          */
2901         for (i = bp->max_vnics - 1; i >= 0; i--) {
2902                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2903
2904                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2905                         continue;
2906
2907                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2908
2909                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2910
2911                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2912
2913                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2914
2915                 bnxt_hwrm_vnic_free(bp, vnic);
2916
2917                 rte_free(vnic->fw_grp_ids);
2918         }
2919         /* Ring resources */
2920         bnxt_free_all_hwrm_rings(bp);
2921         bnxt_free_all_hwrm_ring_grps(bp);
2922         bnxt_free_all_hwrm_stat_ctxs(bp);
2923         bnxt_free_tunnel_ports(bp);
2924 }
2925
2926 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2927 {
2928         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2929
2930         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2931                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2932
2933         switch (conf_link_speed) {
2934         case ETH_LINK_SPEED_10M_HD:
2935         case ETH_LINK_SPEED_100M_HD:
2936                 /* FALLTHROUGH */
2937                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2938         }
2939         return hw_link_duplex;
2940 }
2941
2942 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2943 {
2944         return !conf_link;
2945 }
2946
2947 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2948                                           uint16_t pam4_link)
2949 {
2950         uint16_t eth_link_speed = 0;
2951
2952         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2953                 return ETH_LINK_SPEED_AUTONEG;
2954
2955         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2956         case ETH_LINK_SPEED_100M:
2957         case ETH_LINK_SPEED_100M_HD:
2958                 /* FALLTHROUGH */
2959                 eth_link_speed =
2960                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2961                 break;
2962         case ETH_LINK_SPEED_1G:
2963                 eth_link_speed =
2964                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2965                 break;
2966         case ETH_LINK_SPEED_2_5G:
2967                 eth_link_speed =
2968                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2969                 break;
2970         case ETH_LINK_SPEED_10G:
2971                 eth_link_speed =
2972                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2973                 break;
2974         case ETH_LINK_SPEED_20G:
2975                 eth_link_speed =
2976                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2977                 break;
2978         case ETH_LINK_SPEED_25G:
2979                 eth_link_speed =
2980                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2981                 break;
2982         case ETH_LINK_SPEED_40G:
2983                 eth_link_speed =
2984                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2985                 break;
2986         case ETH_LINK_SPEED_50G:
2987                 eth_link_speed = pam4_link ?
2988                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
2989                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2990                 break;
2991         case ETH_LINK_SPEED_100G:
2992                 eth_link_speed = pam4_link ?
2993                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
2994                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2995                 break;
2996         case ETH_LINK_SPEED_200G:
2997                 eth_link_speed =
2998                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2999                 break;
3000         default:
3001                 PMD_DRV_LOG(ERR,
3002                         "Unsupported link speed %d; default to AUTO\n",
3003                         conf_link_speed);
3004                 break;
3005         }
3006         return eth_link_speed;
3007 }
3008
3009 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3010                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3011                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3012                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3013                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3014
3015 static int bnxt_validate_link_speed(struct bnxt *bp)
3016 {
3017         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3018         uint16_t port_id = bp->eth_dev->data->port_id;
3019         uint32_t link_speed_capa;
3020         uint32_t one_speed;
3021
3022         if (link_speed == ETH_LINK_SPEED_AUTONEG)
3023                 return 0;
3024
3025         link_speed_capa = bnxt_get_speed_capabilities(bp);
3026
3027         if (link_speed & ETH_LINK_SPEED_FIXED) {
3028                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3029
3030                 if (one_speed & (one_speed - 1)) {
3031                         PMD_DRV_LOG(ERR,
3032                                 "Invalid advertised speeds (%u) for port %u\n",
3033                                 link_speed, port_id);
3034                         return -EINVAL;
3035                 }
3036                 if ((one_speed & link_speed_capa) != one_speed) {
3037                         PMD_DRV_LOG(ERR,
3038                                 "Unsupported advertised speed (%u) for port %u\n",
3039                                 link_speed, port_id);
3040                         return -EINVAL;
3041                 }
3042         } else {
3043                 if (!(link_speed & link_speed_capa)) {
3044                         PMD_DRV_LOG(ERR,
3045                                 "Unsupported advertised speeds (%u) for port %u\n",
3046                                 link_speed, port_id);
3047                         return -EINVAL;
3048                 }
3049         }
3050         return 0;
3051 }
3052
3053 static uint16_t
3054 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3055 {
3056         uint16_t ret = 0;
3057
3058         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3059                 if (bp->link_info->support_speeds)
3060                         return bp->link_info->support_speeds;
3061                 link_speed = BNXT_SUPPORTED_SPEEDS;
3062         }
3063
3064         if (link_speed & ETH_LINK_SPEED_100M)
3065                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3066         if (link_speed & ETH_LINK_SPEED_100M_HD)
3067                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3068         if (link_speed & ETH_LINK_SPEED_1G)
3069                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3070         if (link_speed & ETH_LINK_SPEED_2_5G)
3071                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3072         if (link_speed & ETH_LINK_SPEED_10G)
3073                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3074         if (link_speed & ETH_LINK_SPEED_20G)
3075                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3076         if (link_speed & ETH_LINK_SPEED_25G)
3077                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3078         if (link_speed & ETH_LINK_SPEED_40G)
3079                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3080         if (link_speed & ETH_LINK_SPEED_50G)
3081                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3082         if (link_speed & ETH_LINK_SPEED_100G)
3083                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3084         if (link_speed & ETH_LINK_SPEED_200G)
3085                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3086         return ret;
3087 }
3088
3089 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3090 {
3091         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3092
3093         switch (hw_link_speed) {
3094         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3095                 eth_link_speed = ETH_SPEED_NUM_100M;
3096                 break;
3097         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3098                 eth_link_speed = ETH_SPEED_NUM_1G;
3099                 break;
3100         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3101                 eth_link_speed = ETH_SPEED_NUM_2_5G;
3102                 break;
3103         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3104                 eth_link_speed = ETH_SPEED_NUM_10G;
3105                 break;
3106         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3107                 eth_link_speed = ETH_SPEED_NUM_20G;
3108                 break;
3109         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3110                 eth_link_speed = ETH_SPEED_NUM_25G;
3111                 break;
3112         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3113                 eth_link_speed = ETH_SPEED_NUM_40G;
3114                 break;
3115         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3116                 eth_link_speed = ETH_SPEED_NUM_50G;
3117                 break;
3118         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3119                 eth_link_speed = ETH_SPEED_NUM_100G;
3120                 break;
3121         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3122                 eth_link_speed = ETH_SPEED_NUM_200G;
3123                 break;
3124         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3125         default:
3126                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3127                         hw_link_speed);
3128                 break;
3129         }
3130         return eth_link_speed;
3131 }
3132
3133 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3134 {
3135         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3136
3137         switch (hw_link_duplex) {
3138         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3139         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3140                 /* FALLTHROUGH */
3141                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3142                 break;
3143         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3144                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3145                 break;
3146         default:
3147                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3148                         hw_link_duplex);
3149                 break;
3150         }
3151         return eth_link_duplex;
3152 }
3153
3154 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3155 {
3156         int rc = 0;
3157         struct bnxt_link_info *link_info = bp->link_info;
3158
3159         rc = bnxt_hwrm_port_phy_qcaps(bp);
3160         if (rc)
3161                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3162
3163         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3164         if (rc) {
3165                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3166                 goto exit;
3167         }
3168
3169         if (link_info->link_speed)
3170                 link->link_speed =
3171                         bnxt_parse_hw_link_speed(link_info->link_speed);
3172         else
3173                 link->link_speed = ETH_SPEED_NUM_NONE;
3174         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3175         link->link_status = link_info->link_up;
3176         link->link_autoneg = link_info->auto_mode ==
3177                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3178                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3179 exit:
3180         return rc;
3181 }
3182
3183 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3184 {
3185         int rc = 0;
3186         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3187         struct bnxt_link_info link_req;
3188         uint16_t speed, autoneg;
3189
3190         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3191                 return 0;
3192
3193         rc = bnxt_validate_link_speed(bp);
3194         if (rc)
3195                 goto error;
3196
3197         memset(&link_req, 0, sizeof(link_req));
3198         link_req.link_up = link_up;
3199         if (!link_up)
3200                 goto port_phy_cfg;
3201
3202         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3203         if (BNXT_CHIP_P5(bp) &&
3204             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3205                 /* 40G is not supported as part of media auto detect.
3206                  * The speed should be forced and autoneg disabled
3207                  * to configure 40G speed.
3208                  */
3209                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3210                 autoneg = 0;
3211         }
3212
3213         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3214         if (bp->link_info->auto_link_speed == 0 &&
3215             bp->link_info->link_signal_mode &&
3216             bp->link_info->auto_pam4_link_speeds == 0)
3217                 autoneg = 0;
3218
3219         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3220                                           bp->link_info->link_signal_mode);
3221         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3222         /* Autoneg can be done only when the FW allows.
3223          * When user configures fixed speed of 40G and later changes to
3224          * any other speed, auto_link_speed/force_link_speed is still set
3225          * to 40G until link comes up at new speed.
3226          */
3227         if (autoneg == 1 &&
3228             !(!BNXT_CHIP_P5(bp) &&
3229               (bp->link_info->auto_link_speed ||
3230                bp->link_info->force_link_speed))) {
3231                 link_req.phy_flags |=
3232                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3233                 link_req.auto_link_speed_mask =
3234                         bnxt_parse_eth_link_speed_mask(bp,
3235                                                        dev_conf->link_speeds);
3236         } else {
3237                 if (bp->link_info->phy_type ==
3238                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3239                     bp->link_info->phy_type ==
3240                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3241                     bp->link_info->media_type ==
3242                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3243                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3244                         return -EINVAL;
3245                 }
3246
3247                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3248                 /* If user wants a particular speed try that first. */
3249                 if (speed)
3250                         link_req.link_speed = speed;
3251                 else if (bp->link_info->force_pam4_link_speed)
3252                         link_req.link_speed =
3253                                 bp->link_info->force_pam4_link_speed;
3254                 else if (bp->link_info->auto_pam4_link_speeds)
3255                         link_req.link_speed =
3256                                 bp->link_info->auto_pam4_link_speeds;
3257                 else if (bp->link_info->support_pam4_speeds)
3258                         link_req.link_speed =
3259                                 bp->link_info->support_pam4_speeds;
3260                 else if (bp->link_info->force_link_speed)
3261                         link_req.link_speed = bp->link_info->force_link_speed;
3262                 else
3263                         link_req.link_speed = bp->link_info->auto_link_speed;
3264                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3265                  * zero. Use the auto_link_speed.
3266                  */
3267                 if (bp->link_info->auto_link_speed != 0 &&
3268                     bp->link_info->auto_pam4_link_speeds == 0)
3269                         link_req.link_speed = bp->link_info->auto_link_speed;
3270         }
3271         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3272         link_req.auto_pause = bp->link_info->auto_pause;
3273         link_req.force_pause = bp->link_info->force_pause;
3274
3275 port_phy_cfg:
3276         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3277         if (rc) {
3278                 PMD_DRV_LOG(ERR,
3279                         "Set link config failed with rc %d\n", rc);
3280         }
3281
3282 error:
3283         return rc;
3284 }
3285
3286 /* JIRA 22088 */
3287 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3288 {
3289         struct hwrm_func_qcfg_input req = {0};
3290         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3291         uint16_t flags;
3292         int rc = 0;
3293         bp->func_svif = BNXT_SVIF_INVALID;
3294         uint16_t svif_info;
3295
3296         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3297         req.fid = rte_cpu_to_le_16(0xffff);
3298
3299         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3300
3301         HWRM_CHECK_RESULT();
3302
3303         /* Hard Coded.. 0xfff VLAN ID mask */
3304         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3305
3306         svif_info = rte_le_to_cpu_16(resp->svif_info);
3307         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3308                 bp->func_svif = svif_info &
3309                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3310
3311         flags = rte_le_to_cpu_16(resp->flags);
3312         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3313                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3314
3315         if (BNXT_VF(bp) &&
3316             !BNXT_VF_IS_TRUSTED(bp) &&
3317             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3318                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3319                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3320         } else if (BNXT_VF(bp) &&
3321                    BNXT_VF_IS_TRUSTED(bp) &&
3322                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3323                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3324                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3325         }
3326
3327         if (mtu)
3328                 *mtu = rte_le_to_cpu_16(resp->mtu);
3329
3330         switch (resp->port_partition_type) {
3331         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3332         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3333         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3334                 /* FALLTHROUGH */
3335                 bp->flags |= BNXT_FLAG_NPAR_PF;
3336                 break;
3337         default:
3338                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3339                 break;
3340         }
3341
3342         bp->legacy_db_size =
3343                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3344
3345         HWRM_UNLOCK();
3346
3347         return rc;
3348 }
3349
3350 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3351 {
3352         struct hwrm_func_qcfg_input req = {0};
3353         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3354         int rc;
3355
3356         if (!BNXT_VF_IS_TRUSTED(bp))
3357                 return 0;
3358
3359         if (!bp->parent)
3360                 return -EINVAL;
3361
3362         bp->parent->fid = BNXT_PF_FID_INVALID;
3363
3364         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3365
3366         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3367
3368         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3369
3370         HWRM_CHECK_RESULT_SILENT();
3371
3372         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3373         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3374         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3375         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3376
3377         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3378         if (bp->parent->vnic == 0) {
3379                 PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
3380                 /* Use hard-coded values appropriate for current Wh+ fw. */
3381                 if (bp->parent->fid == 2)
3382                         bp->parent->vnic = 0x100;
3383                 else
3384                         bp->parent->vnic = 1;
3385         }
3386
3387         HWRM_UNLOCK();
3388
3389         return 0;
3390 }
3391
3392 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3393                                  uint16_t *vnic_id, uint16_t *svif)
3394 {
3395         struct hwrm_func_qcfg_input req = {0};
3396         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3397         uint16_t svif_info;
3398         int rc = 0;
3399
3400         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3401         req.fid = rte_cpu_to_le_16(fid);
3402
3403         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3404
3405         HWRM_CHECK_RESULT();
3406
3407         if (vnic_id)
3408                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3409
3410         svif_info = rte_le_to_cpu_16(resp->svif_info);
3411         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3412                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3413
3414         HWRM_UNLOCK();
3415
3416         return rc;
3417 }
3418
3419 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3420 {
3421         struct hwrm_port_mac_qcfg_input req = {0};
3422         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3423         uint16_t port_svif_info;
3424         int rc;
3425
3426         bp->port_svif = BNXT_SVIF_INVALID;
3427
3428         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3429                 return 0;
3430
3431         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3432
3433         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3434
3435         HWRM_CHECK_RESULT_SILENT();
3436
3437         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3438         if (port_svif_info &
3439             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3440                 bp->port_svif = port_svif_info &
3441                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3442
3443         HWRM_UNLOCK();
3444
3445         return 0;
3446 }
3447
3448 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3449                                  struct bnxt_pf_resource_info *pf_resc)
3450 {
3451         struct hwrm_func_cfg_input req = {0};
3452         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3453         uint32_t enables;
3454         int rc;
3455
3456         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3457                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3458                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3459                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3460                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3461                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3462                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3463                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3464                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3465
3466         if (BNXT_HAS_RING_GRPS(bp)) {
3467                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3468                 req.num_hw_ring_grps =
3469                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3470         } else if (BNXT_HAS_NQ(bp)) {
3471                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3472                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3473         }
3474
3475         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3476         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3477         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3478         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3479         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3480         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3481         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3482         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3483         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3484         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3485         req.fid = rte_cpu_to_le_16(0xffff);
3486         req.enables = rte_cpu_to_le_32(enables);
3487
3488         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3489
3490         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3491
3492         HWRM_CHECK_RESULT();
3493         HWRM_UNLOCK();
3494
3495         return rc;
3496 }
3497
3498 /* min values are the guaranteed resources and max values are subject
3499  * to availability. The strategy for now is to keep both min & max
3500  * values the same.
3501  */
3502 static void
3503 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3504                               struct hwrm_func_vf_resource_cfg_input *req,
3505                               int num_vfs)
3506 {
3507         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3508                                                (num_vfs + 1));
3509         req->min_rsscos_ctx = req->max_rsscos_ctx;
3510         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3511         req->min_stat_ctx = req->max_stat_ctx;
3512         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3513                                                (num_vfs + 1));
3514         req->min_cmpl_rings = req->max_cmpl_rings;
3515         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3516         req->min_tx_rings = req->max_tx_rings;
3517         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3518         req->min_rx_rings = req->max_rx_rings;
3519         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3520         req->min_l2_ctxs = req->max_l2_ctxs;
3521         /* TODO: For now, do not support VMDq/RFS on VFs. */
3522         req->max_vnics = rte_cpu_to_le_16(1);
3523         req->min_vnics = req->max_vnics;
3524         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3525                                                  (num_vfs + 1));
3526         req->min_hw_ring_grps = req->max_hw_ring_grps;
3527         req->flags =
3528          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3529 }
3530
3531 static void
3532 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3533                               struct hwrm_func_cfg_input *req,
3534                               int num_vfs)
3535 {
3536         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3537                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3538                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3539                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3540                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3541                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3542                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3543                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3544                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3545                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3546
3547         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3548                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3549                                     BNXT_NUM_VLANS);
3550         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3551         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3552                                                 (num_vfs + 1));
3553         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3554         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3555                                                (num_vfs + 1));
3556         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3557         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3558         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3559         /* TODO: For now, do not support VMDq/RFS on VFs. */
3560         req->num_vnics = rte_cpu_to_le_16(1);
3561         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3562                                                  (num_vfs + 1));
3563 }
3564
3565 /* Update the port wide resource values based on how many resources
3566  * got allocated to the VF.
3567  */
3568 static int bnxt_update_max_resources(struct bnxt *bp,
3569                                      int vf)
3570 {
3571         struct hwrm_func_qcfg_input req = {0};
3572         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3573         int rc;
3574
3575         /* Get the actual allocated values now */
3576         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3577         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3578         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3579         HWRM_CHECK_RESULT();
3580
3581         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3582         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3583         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3584         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3585         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3586         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3587         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3588
3589         HWRM_UNLOCK();
3590
3591         return 0;
3592 }
3593
3594 /* Update the PF resource values based on how many resources
3595  * got allocated to it.
3596  */
3597 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3598 {
3599         struct hwrm_func_qcfg_input req = {0};
3600         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3601         int rc;
3602
3603         /* Get the actual allocated values now */
3604         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3605         req.fid = rte_cpu_to_le_16(0xffff);
3606         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3607         HWRM_CHECK_RESULT();
3608
3609         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3610         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3611         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3612         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3613         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3614         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3615         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3616         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3617
3618         HWRM_UNLOCK();
3619
3620         return 0;
3621 }
3622
3623 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3624 {
3625         struct hwrm_func_qcfg_input req = {0};
3626         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3627         int rc;
3628
3629         /* Check for zero MAC address */
3630         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3631         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3632         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3633         HWRM_CHECK_RESULT();
3634         rc = rte_le_to_cpu_16(resp->vlan);
3635
3636         HWRM_UNLOCK();
3637
3638         return rc;
3639 }
3640
3641 static int bnxt_query_pf_resources(struct bnxt *bp,
3642                                    struct bnxt_pf_resource_info *pf_resc)
3643 {
3644         struct hwrm_func_qcfg_input req = {0};
3645         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3646         int rc;
3647
3648         /* And copy the allocated numbers into the pf struct */
3649         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3650         req.fid = rte_cpu_to_le_16(0xffff);
3651         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3652         HWRM_CHECK_RESULT();
3653
3654         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3655         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3656         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3657         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3658         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3659         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3660         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3661         bp->pf->evb_mode = resp->evb_mode;
3662
3663         HWRM_UNLOCK();
3664
3665         return rc;
3666 }
3667
3668 static void
3669 bnxt_calculate_pf_resources(struct bnxt *bp,
3670                             struct bnxt_pf_resource_info *pf_resc,
3671                             int num_vfs)
3672 {
3673         if (!num_vfs) {
3674                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3675                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3676                 pf_resc->num_cp_rings = bp->max_cp_rings;
3677                 pf_resc->num_tx_rings = bp->max_tx_rings;
3678                 pf_resc->num_rx_rings = bp->max_rx_rings;
3679                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3680                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3681
3682                 return;
3683         }
3684
3685         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3686                                    bp->max_rsscos_ctx % (num_vfs + 1);
3687         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3688                                  bp->max_stat_ctx % (num_vfs + 1);
3689         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3690                                 bp->max_cp_rings % (num_vfs + 1);
3691         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3692                                 bp->max_tx_rings % (num_vfs + 1);
3693         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3694                                 bp->max_rx_rings % (num_vfs + 1);
3695         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3696                                bp->max_l2_ctx % (num_vfs + 1);
3697         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3698                                     bp->max_ring_grps % (num_vfs + 1);
3699 }
3700
3701 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3702 {
3703         struct bnxt_pf_resource_info pf_resc = { 0 };
3704         int rc;
3705
3706         if (!BNXT_PF(bp)) {
3707                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3708                 return -EINVAL;
3709         }
3710
3711         rc = bnxt_hwrm_func_qcaps(bp);
3712         if (rc)
3713                 return rc;
3714
3715         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3716
3717         bp->pf->func_cfg_flags &=
3718                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3719                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3720         bp->pf->func_cfg_flags |=
3721                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3722
3723         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3724         if (rc)
3725                 return rc;
3726
3727         rc = bnxt_update_max_resources_pf_only(bp);
3728
3729         return rc;
3730 }
3731
3732 static int
3733 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3734 {
3735         size_t req_buf_sz, sz;
3736         int i, rc;
3737
3738         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3739         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3740                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3741         if (bp->pf->vf_req_buf == NULL) {
3742                 return -ENOMEM;
3743         }
3744
3745         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3746                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3747
3748         for (i = 0; i < num_vfs; i++)
3749                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3750                                              (i * HWRM_MAX_REQ_LEN);
3751
3752         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3753         if (rc)
3754                 rte_free(bp->pf->vf_req_buf);
3755
3756         return rc;
3757 }
3758
3759 static int
3760 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3761 {
3762         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3763         struct hwrm_func_vf_resource_cfg_input req = {0};
3764         int i, rc = 0;
3765
3766         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3767         bp->pf->active_vfs = 0;
3768         for (i = 0; i < num_vfs; i++) {
3769                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3770                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3771                 rc = bnxt_hwrm_send_message(bp,
3772                                             &req,
3773                                             sizeof(req),
3774                                             BNXT_USE_CHIMP_MB);
3775                 if (rc || resp->error_code) {
3776                         PMD_DRV_LOG(ERR,
3777                                 "Failed to initialize VF %d\n", i);
3778                         PMD_DRV_LOG(ERR,
3779                                 "Not all VFs available. (%d, %d)\n",
3780                                 rc, resp->error_code);
3781                         HWRM_UNLOCK();
3782
3783                         /* If the first VF configuration itself fails,
3784                          * unregister the vf_fwd_request buffer.
3785                          */
3786                         if (i == 0)
3787                                 bnxt_hwrm_func_buf_unrgtr(bp);
3788                         break;
3789                 }
3790                 HWRM_UNLOCK();
3791
3792                 /* Update the max resource values based on the resource values
3793                  * allocated to the VF.
3794                  */
3795                 bnxt_update_max_resources(bp, i);
3796                 bp->pf->active_vfs++;
3797                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3798         }
3799
3800         return 0;
3801 }
3802
3803 static int
3804 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3805 {
3806         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3807         struct hwrm_func_cfg_input req = {0};
3808         int i, rc;
3809
3810         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3811
3812         bp->pf->active_vfs = 0;
3813         for (i = 0; i < num_vfs; i++) {
3814                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3815                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3816                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3817                 rc = bnxt_hwrm_send_message(bp,
3818                                             &req,
3819                                             sizeof(req),
3820                                             BNXT_USE_CHIMP_MB);
3821
3822                 /* Clear enable flag for next pass */
3823                 req.enables &= ~rte_cpu_to_le_32(
3824                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3825
3826                 if (rc || resp->error_code) {
3827                         PMD_DRV_LOG(ERR,
3828                                 "Failed to initialize VF %d\n", i);
3829                         PMD_DRV_LOG(ERR,
3830                                 "Not all VFs available. (%d, %d)\n",
3831                                 rc, resp->error_code);
3832                         HWRM_UNLOCK();
3833
3834                         /* If the first VF configuration itself fails,
3835                          * unregister the vf_fwd_request buffer.
3836                          */
3837                         if (i == 0)
3838                                 bnxt_hwrm_func_buf_unrgtr(bp);
3839                         break;
3840                 }
3841
3842                 HWRM_UNLOCK();
3843
3844                 /* Update the max resource values based on the resource values
3845                  * allocated to the VF.
3846                  */
3847                 bnxt_update_max_resources(bp, i);
3848                 bp->pf->active_vfs++;
3849                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3850         }
3851
3852         return 0;
3853 }
3854
3855 static void
3856 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3857 {
3858         if (bp->flags & BNXT_FLAG_NEW_RM)
3859                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3860         else
3861                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3862 }
3863
3864 static void
3865 bnxt_update_pf_resources(struct bnxt *bp,
3866                          struct bnxt_pf_resource_info *pf_resc)
3867 {
3868         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3869         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3870         bp->max_cp_rings = pf_resc->num_cp_rings;
3871         bp->max_tx_rings = pf_resc->num_tx_rings;
3872         bp->max_rx_rings = pf_resc->num_rx_rings;
3873         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3874 }
3875
3876 static int32_t
3877 bnxt_configure_pf_resources(struct bnxt *bp,
3878                             struct bnxt_pf_resource_info *pf_resc)
3879 {
3880         /*
3881          * We're using STD_TX_RING_MODE here which will limit the TX
3882          * rings. This will allow QoS to function properly. Not setting this
3883          * will cause PF rings to break bandwidth settings.
3884          */
3885         bp->pf->func_cfg_flags &=
3886                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3887                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3888         bp->pf->func_cfg_flags |=
3889                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3890         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3891 }
3892
3893 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3894 {
3895         struct bnxt_pf_resource_info pf_resc = { 0 };
3896         int rc;
3897
3898         if (!BNXT_PF(bp)) {
3899                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3900                 return -EINVAL;
3901         }
3902
3903         rc = bnxt_hwrm_func_qcaps(bp);
3904         if (rc)
3905                 return rc;
3906
3907         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3908
3909         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3910         if (rc)
3911                 return rc;
3912
3913         rc = bnxt_query_pf_resources(bp, &pf_resc);
3914         if (rc)
3915                 return rc;
3916
3917         /*
3918          * Now, create and register a buffer to hold forwarded VF requests
3919          */
3920         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3921         if (rc)
3922                 return rc;
3923
3924         bnxt_configure_vf_resources(bp, num_vfs);
3925
3926         bnxt_update_pf_resources(bp, &pf_resc);
3927
3928         return 0;
3929 }
3930
3931 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3932 {
3933         struct hwrm_func_cfg_input req = {0};
3934         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3935         int rc;
3936
3937         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3938
3939         req.fid = rte_cpu_to_le_16(0xffff);
3940         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3941         req.evb_mode = bp->pf->evb_mode;
3942
3943         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3944         HWRM_CHECK_RESULT();
3945         HWRM_UNLOCK();
3946
3947         return rc;
3948 }
3949
3950 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3951                                 uint8_t tunnel_type)
3952 {
3953         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3954         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3955         int rc = 0;
3956
3957         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3958         req.tunnel_type = tunnel_type;
3959         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3960         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3961         HWRM_CHECK_RESULT();
3962
3963         switch (tunnel_type) {
3964         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3965                 bp->vxlan_fw_dst_port_id =
3966                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3967                 bp->vxlan_port = port;
3968                 break;
3969         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3970                 bp->geneve_fw_dst_port_id =
3971                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3972                 bp->geneve_port = port;
3973                 break;
3974         default:
3975                 break;
3976         }
3977
3978         HWRM_UNLOCK();
3979
3980         return rc;
3981 }
3982
3983 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3984                                 uint8_t tunnel_type)
3985 {
3986         struct hwrm_tunnel_dst_port_free_input req = {0};
3987         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3988         int rc = 0;
3989
3990         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3991
3992         req.tunnel_type = tunnel_type;
3993         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3994         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3995
3996         HWRM_CHECK_RESULT();
3997         HWRM_UNLOCK();
3998
3999         if (tunnel_type ==
4000             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4001                 bp->vxlan_port = 0;
4002                 bp->vxlan_port_cnt = 0;
4003         }
4004
4005         if (tunnel_type ==
4006             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4007                 bp->geneve_port = 0;
4008                 bp->geneve_port_cnt = 0;
4009         }
4010
4011         return rc;
4012 }
4013
4014 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4015                                         uint32_t flags)
4016 {
4017         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4018         struct hwrm_func_cfg_input req = {0};
4019         int rc;
4020
4021         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4022
4023         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4024         req.flags = rte_cpu_to_le_32(flags);
4025         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4026
4027         HWRM_CHECK_RESULT();
4028         HWRM_UNLOCK();
4029
4030         return rc;
4031 }
4032
4033 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4034 {
4035         uint32_t *flag = flagp;
4036
4037         vnic->flags = *flag;
4038 }
4039
4040 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4041 {
4042         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4043 }
4044
4045 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4046 {
4047         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4048         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4049         int rc;
4050
4051         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4052
4053         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4054         req.req_buf_page_size =
4055                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4056         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4057         req.req_buf_page_addr0 =
4058                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4059         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4060                 PMD_DRV_LOG(ERR,
4061                         "unable to map buffer address to physical memory\n");
4062                 HWRM_UNLOCK();
4063                 return -ENOMEM;
4064         }
4065
4066         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4067
4068         HWRM_CHECK_RESULT();
4069         HWRM_UNLOCK();
4070
4071         return rc;
4072 }
4073
4074 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4075 {
4076         int rc = 0;
4077         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4078         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4079
4080         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4081                 return 0;
4082
4083         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4084
4085         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4086
4087         HWRM_CHECK_RESULT();
4088         HWRM_UNLOCK();
4089
4090         return rc;
4091 }
4092
4093 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4094 {
4095         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4096         struct hwrm_func_cfg_input req = {0};
4097         int rc;
4098
4099         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4100
4101         req.fid = rte_cpu_to_le_16(0xffff);
4102         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4103         req.enables = rte_cpu_to_le_32(
4104                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4105         req.async_event_cr = rte_cpu_to_le_16(
4106                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4107         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4108
4109         HWRM_CHECK_RESULT();
4110         HWRM_UNLOCK();
4111
4112         return rc;
4113 }
4114
4115 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4116 {
4117         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4118         struct hwrm_func_vf_cfg_input req = {0};
4119         int rc;
4120
4121         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4122
4123         req.enables = rte_cpu_to_le_32(
4124                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4125         req.async_event_cr = rte_cpu_to_le_16(
4126                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4127         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4128
4129         HWRM_CHECK_RESULT();
4130         HWRM_UNLOCK();
4131
4132         return rc;
4133 }
4134
4135 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4136 {
4137         struct hwrm_func_cfg_input req = {0};
4138         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4139         uint16_t dflt_vlan, fid;
4140         uint32_t func_cfg_flags;
4141         int rc = 0;
4142
4143         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4144
4145         if (is_vf) {
4146                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4147                 fid = bp->pf->vf_info[vf].fid;
4148                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4149         } else {
4150                 fid = rte_cpu_to_le_16(0xffff);
4151                 func_cfg_flags = bp->pf->func_cfg_flags;
4152                 dflt_vlan = bp->vlan;
4153         }
4154
4155         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4156         req.fid = rte_cpu_to_le_16(fid);
4157         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4158         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4159
4160         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4161
4162         HWRM_CHECK_RESULT();
4163         HWRM_UNLOCK();
4164
4165         return rc;
4166 }
4167
4168 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4169                         uint16_t max_bw, uint16_t enables)
4170 {
4171         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4172         struct hwrm_func_cfg_input req = {0};
4173         int rc;
4174
4175         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4176
4177         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4178         req.enables |= rte_cpu_to_le_32(enables);
4179         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4180         req.max_bw = rte_cpu_to_le_32(max_bw);
4181         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4182
4183         HWRM_CHECK_RESULT();
4184         HWRM_UNLOCK();
4185
4186         return rc;
4187 }
4188
4189 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4190 {
4191         struct hwrm_func_cfg_input req = {0};
4192         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4193         int rc = 0;
4194
4195         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4196
4197         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4198         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4199         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4200         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4201
4202         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4203
4204         HWRM_CHECK_RESULT();
4205         HWRM_UNLOCK();
4206
4207         return rc;
4208 }
4209
4210 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4211 {
4212         int rc;
4213
4214         if (BNXT_PF(bp))
4215                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4216         else
4217                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4218
4219         return rc;
4220 }
4221
4222 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4223                               void *encaped, size_t ec_size)
4224 {
4225         int rc = 0;
4226         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4227         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4228
4229         if (ec_size > sizeof(req.encap_request))
4230                 return -1;
4231
4232         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4233
4234         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4235         memcpy(req.encap_request, encaped, ec_size);
4236
4237         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4238
4239         HWRM_CHECK_RESULT();
4240         HWRM_UNLOCK();
4241
4242         return rc;
4243 }
4244
4245 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4246                                        struct rte_ether_addr *mac)
4247 {
4248         struct hwrm_func_qcfg_input req = {0};
4249         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4250         int rc;
4251
4252         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4253
4254         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4255         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4256
4257         HWRM_CHECK_RESULT();
4258
4259         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4260
4261         HWRM_UNLOCK();
4262
4263         return rc;
4264 }
4265
4266 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4267                             void *encaped, size_t ec_size)
4268 {
4269         int rc = 0;
4270         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4271         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4272
4273         if (ec_size > sizeof(req.encap_request))
4274                 return -1;
4275
4276         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4277
4278         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4279         memcpy(req.encap_request, encaped, ec_size);
4280
4281         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4282
4283         HWRM_CHECK_RESULT();
4284         HWRM_UNLOCK();
4285
4286         return rc;
4287 }
4288
4289 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
4290                          struct rte_eth_stats *stats, uint8_t rx)
4291 {
4292         int rc = 0;
4293         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4294         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4295
4296         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4297
4298         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4299
4300         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4301
4302         HWRM_CHECK_RESULT();
4303
4304         if (rx) {
4305                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4306                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4307                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4308                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4309                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4310                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4311                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4312                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4313         } else {
4314                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4315                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4316                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4317                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4318                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4319                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4320         }
4321
4322         HWRM_UNLOCK();
4323
4324         return rc;
4325 }
4326
4327 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4328 {
4329         struct hwrm_port_qstats_input req = {0};
4330         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4331         struct bnxt_pf_info *pf = bp->pf;
4332         int rc;
4333
4334         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4335
4336         req.port_id = rte_cpu_to_le_16(pf->port_id);
4337         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4338         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4340
4341         HWRM_CHECK_RESULT();
4342         HWRM_UNLOCK();
4343
4344         return rc;
4345 }
4346
4347 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4348 {
4349         struct hwrm_port_clr_stats_input req = {0};
4350         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4351         struct bnxt_pf_info *pf = bp->pf;
4352         int rc;
4353
4354         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4355         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4356             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4357                 return 0;
4358
4359         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4360
4361         req.port_id = rte_cpu_to_le_16(pf->port_id);
4362         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4363
4364         HWRM_CHECK_RESULT();
4365         HWRM_UNLOCK();
4366
4367         return rc;
4368 }
4369
4370 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4371 {
4372         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4373         struct hwrm_port_led_qcaps_input req = {0};
4374         int rc;
4375
4376         if (BNXT_VF(bp))
4377                 return 0;
4378
4379         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4380         req.port_id = bp->pf->port_id;
4381         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4382
4383         HWRM_CHECK_RESULT_SILENT();
4384
4385         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4386                 unsigned int i;
4387
4388                 bp->leds->num_leds = resp->num_leds;
4389                 memcpy(bp->leds, &resp->led0_id,
4390                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4391                 for (i = 0; i < bp->leds->num_leds; i++) {
4392                         struct bnxt_led_info *led = &bp->leds[i];
4393
4394                         uint16_t caps = led->led_state_caps;
4395
4396                         if (!led->led_group_id ||
4397                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4398                                 bp->leds->num_leds = 0;
4399                                 break;
4400                         }
4401                 }
4402         }
4403
4404         HWRM_UNLOCK();
4405
4406         return rc;
4407 }
4408
4409 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4410 {
4411         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4412         struct hwrm_port_led_cfg_input req = {0};
4413         struct bnxt_led_cfg *led_cfg;
4414         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4415         uint16_t duration = 0;
4416         int rc, i;
4417
4418         if (!bp->leds->num_leds || BNXT_VF(bp))
4419                 return -EOPNOTSUPP;
4420
4421         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4422
4423         if (led_on) {
4424                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4425                 duration = rte_cpu_to_le_16(500);
4426         }
4427         req.port_id = bp->pf->port_id;
4428         req.num_leds = bp->leds->num_leds;
4429         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4430         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4431                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4432                 led_cfg->led_id = bp->leds[i].led_id;
4433                 led_cfg->led_state = led_state;
4434                 led_cfg->led_blink_on = duration;
4435                 led_cfg->led_blink_off = duration;
4436                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4437         }
4438
4439         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4440
4441         HWRM_CHECK_RESULT();
4442         HWRM_UNLOCK();
4443
4444         return rc;
4445 }
4446
4447 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4448                                uint32_t *length)
4449 {
4450         int rc;
4451         struct hwrm_nvm_get_dir_info_input req = {0};
4452         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4453
4454         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4455
4456         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4457
4458         HWRM_CHECK_RESULT();
4459
4460         *entries = rte_le_to_cpu_32(resp->entries);
4461         *length = rte_le_to_cpu_32(resp->entry_length);
4462
4463         HWRM_UNLOCK();
4464         return rc;
4465 }
4466
4467 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4468 {
4469         int rc;
4470         uint32_t dir_entries;
4471         uint32_t entry_length;
4472         uint8_t *buf;
4473         size_t buflen;
4474         rte_iova_t dma_handle;
4475         struct hwrm_nvm_get_dir_entries_input req = {0};
4476         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4477
4478         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4479         if (rc != 0)
4480                 return rc;
4481
4482         *data++ = dir_entries;
4483         *data++ = entry_length;
4484         len -= 2;
4485         memset(data, 0xff, len);
4486
4487         buflen = dir_entries * entry_length;
4488         buf = rte_malloc("nvm_dir", buflen, 0);
4489         if (buf == NULL)
4490                 return -ENOMEM;
4491         dma_handle = rte_malloc_virt2iova(buf);
4492         if (dma_handle == RTE_BAD_IOVA) {
4493                 rte_free(buf);
4494                 PMD_DRV_LOG(ERR,
4495                         "unable to map response address to physical memory\n");
4496                 return -ENOMEM;
4497         }
4498         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4499         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4500         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4501
4502         if (rc == 0)
4503                 memcpy(data, buf, len > buflen ? buflen : len);
4504
4505         rte_free(buf);
4506         HWRM_CHECK_RESULT();
4507         HWRM_UNLOCK();
4508
4509         return rc;
4510 }
4511
4512 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4513                              uint32_t offset, uint32_t length,
4514                              uint8_t *data)
4515 {
4516         int rc;
4517         uint8_t *buf;
4518         rte_iova_t dma_handle;
4519         struct hwrm_nvm_read_input req = {0};
4520         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4521
4522         buf = rte_malloc("nvm_item", length, 0);
4523         if (!buf)
4524                 return -ENOMEM;
4525
4526         dma_handle = rte_malloc_virt2iova(buf);
4527         if (dma_handle == RTE_BAD_IOVA) {
4528                 rte_free(buf);
4529                 PMD_DRV_LOG(ERR,
4530                         "unable to map response address to physical memory\n");
4531                 return -ENOMEM;
4532         }
4533         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4534         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4535         req.dir_idx = rte_cpu_to_le_16(index);
4536         req.offset = rte_cpu_to_le_32(offset);
4537         req.len = rte_cpu_to_le_32(length);
4538         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4539         if (rc == 0)
4540                 memcpy(data, buf, length);
4541
4542         rte_free(buf);
4543         HWRM_CHECK_RESULT();
4544         HWRM_UNLOCK();
4545
4546         return rc;
4547 }
4548
4549 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4550 {
4551         int rc;
4552         struct hwrm_nvm_erase_dir_entry_input req = {0};
4553         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4554
4555         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4556         req.dir_idx = rte_cpu_to_le_16(index);
4557         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4558         HWRM_CHECK_RESULT();
4559         HWRM_UNLOCK();
4560
4561         return rc;
4562 }
4563
4564
4565 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4566                           uint16_t dir_ordinal, uint16_t dir_ext,
4567                           uint16_t dir_attr, const uint8_t *data,
4568                           size_t data_len)
4569 {
4570         int rc;
4571         struct hwrm_nvm_write_input req = {0};
4572         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4573         rte_iova_t dma_handle;
4574         uint8_t *buf;
4575
4576         buf = rte_malloc("nvm_write", data_len, 0);
4577         if (!buf)
4578                 return -ENOMEM;
4579
4580         dma_handle = rte_malloc_virt2iova(buf);
4581         if (dma_handle == RTE_BAD_IOVA) {
4582                 rte_free(buf);
4583                 PMD_DRV_LOG(ERR,
4584                         "unable to map response address to physical memory\n");
4585                 return -ENOMEM;
4586         }
4587         memcpy(buf, data, data_len);
4588
4589         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4590
4591         req.dir_type = rte_cpu_to_le_16(dir_type);
4592         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4593         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4594         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4595         req.dir_data_length = rte_cpu_to_le_32(data_len);
4596         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4597
4598         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4599
4600         rte_free(buf);
4601         HWRM_CHECK_RESULT();
4602         HWRM_UNLOCK();
4603
4604         return rc;
4605 }
4606
4607 static void
4608 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4609 {
4610         uint32_t *count = cbdata;
4611
4612         *count = *count + 1;
4613 }
4614
4615 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4616                                      struct bnxt_vnic_info *vnic __rte_unused)
4617 {
4618         return 0;
4619 }
4620
4621 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4622 {
4623         uint32_t count = 0;
4624
4625         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4626             &count, bnxt_vnic_count_hwrm_stub);
4627
4628         return count;
4629 }
4630
4631 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4632                                         uint16_t *vnic_ids)
4633 {
4634         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4635         struct hwrm_func_vf_vnic_ids_query_output *resp =
4636                                                 bp->hwrm_cmd_resp_addr;
4637         int rc;
4638
4639         /* First query all VNIC ids */
4640         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4641
4642         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4643         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4644         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4645
4646         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4647                 HWRM_UNLOCK();
4648                 PMD_DRV_LOG(ERR,
4649                 "unable to map VNIC ID table address to physical memory\n");
4650                 return -ENOMEM;
4651         }
4652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4653         HWRM_CHECK_RESULT();
4654         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4655
4656         HWRM_UNLOCK();
4657
4658         return rc;
4659 }
4660
4661 /*
4662  * This function queries the VNIC IDs  for a specified VF. It then calls
4663  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4664  * Then it calls the hwrm_cb function to program this new vnic configuration.
4665  */
4666 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4667         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4668         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4669 {
4670         struct bnxt_vnic_info vnic;
4671         int rc = 0;
4672         int i, num_vnic_ids;
4673         uint16_t *vnic_ids;
4674         size_t vnic_id_sz;
4675         size_t sz;
4676
4677         /* First query all VNIC ids */
4678         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4679         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4680                         RTE_CACHE_LINE_SIZE);
4681         if (vnic_ids == NULL)
4682                 return -ENOMEM;
4683
4684         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4685                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4686
4687         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4688
4689         if (num_vnic_ids < 0)
4690                 return num_vnic_ids;
4691
4692         /* Retrieve VNIC, update bd_stall then update */
4693
4694         for (i = 0; i < num_vnic_ids; i++) {
4695                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4696                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4697                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4698                 if (rc)
4699                         break;
4700                 if (vnic.mru <= 4)      /* Indicates unallocated */
4701                         continue;
4702
4703                 vnic_cb(&vnic, cbdata);
4704
4705                 rc = hwrm_cb(bp, &vnic);
4706                 if (rc)
4707                         break;
4708         }
4709
4710         rte_free(vnic_ids);
4711
4712         return rc;
4713 }
4714
4715 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4716                                               bool on)
4717 {
4718         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4719         struct hwrm_func_cfg_input req = {0};
4720         int rc;
4721
4722         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4723
4724         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4725         req.enables |= rte_cpu_to_le_32(
4726                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4727         req.vlan_antispoof_mode = on ?
4728                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4729                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4730         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4731
4732         HWRM_CHECK_RESULT();
4733         HWRM_UNLOCK();
4734
4735         return rc;
4736 }
4737
4738 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4739 {
4740         struct bnxt_vnic_info vnic;
4741         uint16_t *vnic_ids;
4742         size_t vnic_id_sz;
4743         int num_vnic_ids, i;
4744         size_t sz;
4745         int rc;
4746
4747         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4748         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4749                         RTE_CACHE_LINE_SIZE);
4750         if (vnic_ids == NULL)
4751                 return -ENOMEM;
4752
4753         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4754                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4755
4756         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4757         if (rc <= 0)
4758                 goto exit;
4759         num_vnic_ids = rc;
4760
4761         /*
4762          * Loop through to find the default VNIC ID.
4763          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4764          * by sending the hwrm_func_qcfg command to the firmware.
4765          */
4766         for (i = 0; i < num_vnic_ids; i++) {
4767                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4768                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4769                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4770                                         bp->pf->first_vf_id + vf);
4771                 if (rc)
4772                         goto exit;
4773                 if (vnic.func_default) {
4774                         rte_free(vnic_ids);
4775                         return vnic.fw_vnic_id;
4776                 }
4777         }
4778         /* Could not find a default VNIC. */
4779         PMD_DRV_LOG(ERR, "No default VNIC\n");
4780 exit:
4781         rte_free(vnic_ids);
4782         return rc;
4783 }
4784
4785 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4786                          uint16_t dst_id,
4787                          struct bnxt_filter_info *filter)
4788 {
4789         int rc = 0;
4790         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4791         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4792         uint32_t enables = 0;
4793
4794         if (filter->fw_em_filter_id != UINT64_MAX)
4795                 bnxt_hwrm_clear_em_filter(bp, filter);
4796
4797         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4798
4799         req.flags = rte_cpu_to_le_32(filter->flags);
4800
4801         enables = filter->enables |
4802               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4803         req.dst_id = rte_cpu_to_le_16(dst_id);
4804
4805         if (filter->ip_addr_type) {
4806                 req.ip_addr_type = filter->ip_addr_type;
4807                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4808         }
4809         if (enables &
4810             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4811                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4812         if (enables &
4813             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4814                 memcpy(req.src_macaddr, filter->src_macaddr,
4815                        RTE_ETHER_ADDR_LEN);
4816         if (enables &
4817             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4818                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4819                        RTE_ETHER_ADDR_LEN);
4820         if (enables &
4821             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4822                 req.ovlan_vid = filter->l2_ovlan;
4823         if (enables &
4824             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4825                 req.ivlan_vid = filter->l2_ivlan;
4826         if (enables &
4827             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4828                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4829         if (enables &
4830             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4831                 req.ip_protocol = filter->ip_protocol;
4832         if (enables &
4833             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4834                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4835         if (enables &
4836             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4837                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4838         if (enables &
4839             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4840                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4841         if (enables &
4842             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4843                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4844         if (enables &
4845             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4846                 req.mirror_vnic_id = filter->mirror_vnic_id;
4847
4848         req.enables = rte_cpu_to_le_32(enables);
4849
4850         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4851
4852         HWRM_CHECK_RESULT();
4853
4854         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4855         HWRM_UNLOCK();
4856
4857         return rc;
4858 }
4859
4860 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4861 {
4862         int rc = 0;
4863         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4864         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4865
4866         if (filter->fw_em_filter_id == UINT64_MAX)
4867                 return 0;
4868
4869         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4870
4871         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4872
4873         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4874
4875         HWRM_CHECK_RESULT();
4876         HWRM_UNLOCK();
4877
4878         filter->fw_em_filter_id = UINT64_MAX;
4879         filter->fw_l2_filter_id = UINT64_MAX;
4880
4881         return 0;
4882 }
4883
4884 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4885                          uint16_t dst_id,
4886                          struct bnxt_filter_info *filter)
4887 {
4888         int rc = 0;
4889         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4890         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4891                                                 bp->hwrm_cmd_resp_addr;
4892         uint32_t enables = 0;
4893
4894         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4895                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4896
4897         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4898
4899         req.flags = rte_cpu_to_le_32(filter->flags);
4900
4901         enables = filter->enables |
4902               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4903         req.dst_id = rte_cpu_to_le_16(dst_id);
4904
4905         if (filter->ip_addr_type) {
4906                 req.ip_addr_type = filter->ip_addr_type;
4907                 enables |=
4908                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4909         }
4910         if (enables &
4911             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4912                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4913         if (enables &
4914             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4915                 memcpy(req.src_macaddr, filter->src_macaddr,
4916                        RTE_ETHER_ADDR_LEN);
4917         if (enables &
4918             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4919                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4920         if (enables &
4921             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4922                 req.ip_protocol = filter->ip_protocol;
4923         if (enables &
4924             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4925                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4926         if (enables &
4927             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4928                 req.src_ipaddr_mask[0] =
4929                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4930         if (enables &
4931             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4932                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4933         if (enables &
4934             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4935                 req.dst_ipaddr_mask[0] =
4936                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4937         if (enables &
4938             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4939                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4940         if (enables &
4941             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4942                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4943         if (enables &
4944             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4945                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4946         if (enables &
4947             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4948                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4949         if (enables &
4950             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4951                 req.mirror_vnic_id = filter->mirror_vnic_id;
4952
4953         req.enables = rte_cpu_to_le_32(enables);
4954
4955         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4956
4957         HWRM_CHECK_RESULT();
4958
4959         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4960         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4961         HWRM_UNLOCK();
4962
4963         return rc;
4964 }
4965
4966 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4967                                 struct bnxt_filter_info *filter)
4968 {
4969         int rc = 0;
4970         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4971         struct hwrm_cfa_ntuple_filter_free_output *resp =
4972                                                 bp->hwrm_cmd_resp_addr;
4973
4974         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4975                 return 0;
4976
4977         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4978
4979         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4980
4981         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4982
4983         HWRM_CHECK_RESULT();
4984         HWRM_UNLOCK();
4985
4986         filter->fw_ntuple_filter_id = UINT64_MAX;
4987
4988         return 0;
4989 }
4990
4991 static int
4992 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4993 {
4994         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4995         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4996         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4997         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4998         uint16_t *ring_tbl = vnic->rss_table;
4999         int nr_ctxs = vnic->num_lb_ctxts;
5000         int max_rings = bp->rx_nr_rings;
5001         int i, j, k, cnt;
5002         int rc = 0;
5003
5004         for (i = 0, k = 0; i < nr_ctxs; i++) {
5005                 struct bnxt_rx_ring_info *rxr;
5006                 struct bnxt_cp_ring_info *cpr;
5007
5008                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5009
5010                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5011                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5012                 req.hash_mode_flags = vnic->hash_mode;
5013
5014                 req.ring_grp_tbl_addr =
5015                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5016                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5017                                      2 * sizeof(*ring_tbl));
5018                 req.hash_key_tbl_addr =
5019                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5020
5021                 req.ring_table_pair_index = i;
5022                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5023
5024                 for (j = 0; j < 64; j++) {
5025                         uint16_t ring_id;
5026
5027                         /* Find next active ring. */
5028                         for (cnt = 0; cnt < max_rings; cnt++) {
5029                                 if (rx_queue_state[k] !=
5030                                                 RTE_ETH_QUEUE_STATE_STOPPED)
5031                                         break;
5032                                 if (++k == max_rings)
5033                                         k = 0;
5034                         }
5035
5036                         /* Return if no rings are active. */
5037                         if (cnt == max_rings) {
5038                                 HWRM_UNLOCK();
5039                                 return 0;
5040                         }
5041
5042                         /* Add rx/cp ring pair to RSS table. */
5043                         rxr = rxqs[k]->rx_ring;
5044                         cpr = rxqs[k]->cp_ring;
5045
5046                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5047                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5048                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5049                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5050
5051                         if (++k == max_rings)
5052                                 k = 0;
5053                 }
5054                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5055                                             BNXT_USE_CHIMP_MB);
5056
5057                 HWRM_CHECK_RESULT();
5058                 HWRM_UNLOCK();
5059         }
5060
5061         return rc;
5062 }
5063
5064 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5065 {
5066         unsigned int rss_idx, fw_idx, i;
5067
5068         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5069                 return 0;
5070
5071         if (!(vnic->rss_table && vnic->hash_type))
5072                 return 0;
5073
5074         if (BNXT_CHIP_P5(bp))
5075                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5076
5077         /*
5078          * Fill the RSS hash & redirection table with
5079          * ring group ids for all VNICs
5080          */
5081         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5082              rss_idx++, fw_idx++) {
5083                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5084                         fw_idx %= bp->rx_cp_nr_rings;
5085                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5086                                 break;
5087                         fw_idx++;
5088                 }
5089
5090                 if (i == bp->rx_cp_nr_rings)
5091                         return 0;
5092
5093                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5094         }
5095
5096         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5097 }
5098
5099 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5100         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5101 {
5102         uint16_t flags;
5103
5104         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5105
5106         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5107         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5108
5109         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5110         req->num_cmpl_dma_aggr_during_int =
5111                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5112
5113         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5114
5115         /* min timer set to 1/2 of interrupt timer */
5116         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5117
5118         /* buf timer set to 1/4 of interrupt timer */
5119         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5120
5121         req->cmpl_aggr_dma_tmr_during_int =
5122                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5123
5124         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5125                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5126         req->flags = rte_cpu_to_le_16(flags);
5127 }
5128
5129 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5130                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5131 {
5132         struct hwrm_ring_aggint_qcaps_input req = {0};
5133         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5134         uint32_t enables;
5135         uint16_t flags;
5136         int rc;
5137
5138         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5139         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5140         HWRM_CHECK_RESULT();
5141
5142         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5143         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5144
5145         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5146                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5147         agg_req->flags = rte_cpu_to_le_16(flags);
5148         enables =
5149          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5150          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5151         agg_req->enables = rte_cpu_to_le_32(enables);
5152
5153         HWRM_UNLOCK();
5154         return rc;
5155 }
5156
5157 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5158                         struct bnxt_coal *coal, uint16_t ring_id)
5159 {
5160         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5161         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5162                                                 bp->hwrm_cmd_resp_addr;
5163         int rc;
5164
5165         /* Set ring coalesce parameters only for 100G NICs */
5166         if (BNXT_CHIP_P5(bp)) {
5167                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5168                         return -1;
5169         } else if (bnxt_stratus_device(bp)) {
5170                 bnxt_hwrm_set_coal_params(coal, &req);
5171         } else {
5172                 return 0;
5173         }
5174
5175         HWRM_PREP(&req,
5176                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5177                   BNXT_USE_CHIMP_MB);
5178         req.ring_id = rte_cpu_to_le_16(ring_id);
5179         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5180         HWRM_CHECK_RESULT();
5181         HWRM_UNLOCK();
5182         return 0;
5183 }
5184
5185 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5186 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5187 {
5188         struct hwrm_func_backing_store_qcaps_input req = {0};
5189         struct hwrm_func_backing_store_qcaps_output *resp =
5190                 bp->hwrm_cmd_resp_addr;
5191         struct bnxt_ctx_pg_info *ctx_pg;
5192         struct bnxt_ctx_mem_info *ctx;
5193         int total_alloc_len;
5194         int rc, i, tqm_rings;
5195
5196         if (!BNXT_CHIP_P5(bp) ||
5197             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5198             BNXT_VF(bp) ||
5199             bp->ctx)
5200                 return 0;
5201
5202         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5203         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5204         HWRM_CHECK_RESULT_SILENT();
5205
5206         total_alloc_len = sizeof(*ctx);
5207         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5208                           RTE_CACHE_LINE_SIZE);
5209         if (!ctx) {
5210                 rc = -ENOMEM;
5211                 goto ctx_err;
5212         }
5213
5214         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5215         ctx->qp_min_qp1_entries =
5216                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5217         ctx->qp_max_l2_entries =
5218                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5219         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5220         ctx->srq_max_l2_entries =
5221                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5222         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5223         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5224         ctx->cq_max_l2_entries =
5225                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5226         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5227         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5228         ctx->vnic_max_vnic_entries =
5229                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5230         ctx->vnic_max_ring_table_entries =
5231                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5232         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5233         ctx->stat_max_entries =
5234                 rte_le_to_cpu_32(resp->stat_max_entries);
5235         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5236         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5237         ctx->tqm_min_entries_per_ring =
5238                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5239         ctx->tqm_max_entries_per_ring =
5240                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5241         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5242         if (!ctx->tqm_entries_multiple)
5243                 ctx->tqm_entries_multiple = 1;
5244         ctx->mrav_max_entries =
5245                 rte_le_to_cpu_32(resp->mrav_max_entries);
5246         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5247         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5248         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5249         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5250
5251         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5252                                   RTE_MIN(ctx->tqm_fp_rings_count,
5253                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5254                                   bp->max_q;
5255
5256         /* Check if the ext ring count needs to be counted.
5257          * Ext ring count is available only with new FW so we should not
5258          * look at the field on older FW.
5259          */
5260         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5261             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5262                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5263                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5264                                                   ctx->tqm_fp_rings_count);
5265         }
5266
5267         tqm_rings = ctx->tqm_fp_rings_count + 1;
5268
5269         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5270                             sizeof(*ctx_pg) * tqm_rings,
5271                             RTE_CACHE_LINE_SIZE);
5272         if (!ctx_pg) {
5273                 rc = -ENOMEM;
5274                 goto ctx_err;
5275         }
5276         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5277                 ctx->tqm_mem[i] = ctx_pg;
5278
5279         bp->ctx = ctx;
5280 ctx_err:
5281         HWRM_UNLOCK();
5282         return rc;
5283 }
5284
5285 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5286 {
5287         struct hwrm_func_backing_store_cfg_input req = {0};
5288         struct hwrm_func_backing_store_cfg_output *resp =
5289                 bp->hwrm_cmd_resp_addr;
5290         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5291         struct bnxt_ctx_pg_info *ctx_pg;
5292         uint32_t *num_entries;
5293         uint64_t *pg_dir;
5294         uint8_t *pg_attr;
5295         uint32_t ena;
5296         int i, rc;
5297
5298         if (!ctx)
5299                 return 0;
5300
5301         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5302         req.enables = rte_cpu_to_le_32(enables);
5303
5304         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5305                 ctx_pg = &ctx->qp_mem;
5306                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5307                 req.qp_num_qp1_entries =
5308                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5309                 req.qp_num_l2_entries =
5310                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5311                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5312                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5313                                       &req.qpc_pg_size_qpc_lvl,
5314                                       &req.qpc_page_dir);
5315         }
5316
5317         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5318                 ctx_pg = &ctx->srq_mem;
5319                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5320                 req.srq_num_l2_entries =
5321                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5322                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5323                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5324                                       &req.srq_pg_size_srq_lvl,
5325                                       &req.srq_page_dir);
5326         }
5327
5328         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5329                 ctx_pg = &ctx->cq_mem;
5330                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5331                 req.cq_num_l2_entries =
5332                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5333                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5334                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5335                                       &req.cq_pg_size_cq_lvl,
5336                                       &req.cq_page_dir);
5337         }
5338
5339         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5340                 ctx_pg = &ctx->vnic_mem;
5341                 req.vnic_num_vnic_entries =
5342                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5343                 req.vnic_num_ring_table_entries =
5344                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5345                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5346                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5347                                       &req.vnic_pg_size_vnic_lvl,
5348                                       &req.vnic_page_dir);
5349         }
5350
5351         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5352                 ctx_pg = &ctx->stat_mem;
5353                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5354                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5355                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5356                                       &req.stat_pg_size_stat_lvl,
5357                                       &req.stat_page_dir);
5358         }
5359
5360         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5361         num_entries = &req.tqm_sp_num_entries;
5362         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5363         pg_dir = &req.tqm_sp_page_dir;
5364         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5365         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5366                 if (!(enables & ena))
5367                         continue;
5368
5369                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5370
5371                 ctx_pg = ctx->tqm_mem[i];
5372                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5373                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5374         }
5375
5376         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5377                 /* DPDK does not need to configure MRAV and TIM type.
5378                  * So we are skipping over MRAV and TIM. Skip to configure
5379                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5380                  */
5381                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5382                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5383                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5384                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5385                                       &req.tqm_ring8_page_dir);
5386         }
5387
5388         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5389         HWRM_CHECK_RESULT();
5390         HWRM_UNLOCK();
5391
5392         return rc;
5393 }
5394
5395 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5396 {
5397         struct hwrm_port_qstats_ext_input req = {0};
5398         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5399         struct bnxt_pf_info *pf = bp->pf;
5400         int rc;
5401
5402         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5403               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5404                 return 0;
5405
5406         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5407
5408         req.port_id = rte_cpu_to_le_16(pf->port_id);
5409         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5410                 req.tx_stat_host_addr =
5411                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5412                 req.tx_stat_size =
5413                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5414         }
5415         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5416                 req.rx_stat_host_addr =
5417                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5418                 req.rx_stat_size =
5419                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5420         }
5421         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5422
5423         if (rc) {
5424                 bp->fw_rx_port_stats_ext_size = 0;
5425                 bp->fw_tx_port_stats_ext_size = 0;
5426         } else {
5427                 bp->fw_rx_port_stats_ext_size =
5428                         rte_le_to_cpu_16(resp->rx_stat_size);
5429                 bp->fw_tx_port_stats_ext_size =
5430                         rte_le_to_cpu_16(resp->tx_stat_size);
5431         }
5432
5433         HWRM_CHECK_RESULT();
5434         HWRM_UNLOCK();
5435
5436         return rc;
5437 }
5438
5439 int
5440 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5441 {
5442         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5443         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5444                 bp->hwrm_cmd_resp_addr;
5445         int rc = 0;
5446
5447         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5448         req.tunnel_type = type;
5449         req.dest_fid = bp->fw_fid;
5450         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5451         HWRM_CHECK_RESULT();
5452
5453         HWRM_UNLOCK();
5454
5455         return rc;
5456 }
5457
5458 int
5459 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5460 {
5461         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5462         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5463                 bp->hwrm_cmd_resp_addr;
5464         int rc = 0;
5465
5466         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5467         req.tunnel_type = type;
5468         req.dest_fid = bp->fw_fid;
5469         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5470         HWRM_CHECK_RESULT();
5471
5472         HWRM_UNLOCK();
5473
5474         return rc;
5475 }
5476
5477 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5478 {
5479         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5480         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5481                 bp->hwrm_cmd_resp_addr;
5482         int rc = 0;
5483
5484         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5485         req.src_fid = bp->fw_fid;
5486         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5487         HWRM_CHECK_RESULT();
5488
5489         if (type)
5490                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5491
5492         HWRM_UNLOCK();
5493
5494         return rc;
5495 }
5496
5497 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5498                                    uint16_t *dst_fid)
5499 {
5500         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5501         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5502                 bp->hwrm_cmd_resp_addr;
5503         int rc = 0;
5504
5505         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5506         req.src_fid = bp->fw_fid;
5507         req.tunnel_type = tun_type;
5508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5509         HWRM_CHECK_RESULT();
5510
5511         if (dst_fid)
5512                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5513
5514         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5515
5516         HWRM_UNLOCK();
5517
5518         return rc;
5519 }
5520
5521 int bnxt_hwrm_set_mac(struct bnxt *bp)
5522 {
5523         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5524         struct hwrm_func_vf_cfg_input req = {0};
5525         int rc = 0;
5526
5527         if (!BNXT_VF(bp))
5528                 return 0;
5529
5530         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5531
5532         req.enables =
5533                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5534         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5535
5536         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5537
5538         HWRM_CHECK_RESULT();
5539
5540         HWRM_UNLOCK();
5541
5542         return rc;
5543 }
5544
5545 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5546 {
5547         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5548         struct hwrm_func_drv_if_change_input req = {0};
5549         uint32_t flags;
5550         int rc;
5551
5552         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5553                 return 0;
5554
5555         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5556          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5557          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5558          */
5559         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5560                 return 0;
5561
5562         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5563
5564         if (up)
5565                 req.flags =
5566                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5567
5568         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5569
5570         HWRM_CHECK_RESULT();
5571         flags = rte_le_to_cpu_32(resp->flags);
5572         HWRM_UNLOCK();
5573
5574         if (!up)
5575                 return 0;
5576
5577         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5578                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5579                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5580         }
5581
5582         return 0;
5583 }
5584
5585 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5586 {
5587         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5588         struct bnxt_error_recovery_info *info = bp->recovery_info;
5589         struct hwrm_error_recovery_qcfg_input req = {0};
5590         uint32_t flags = 0;
5591         unsigned int i;
5592         int rc;
5593
5594         /* Older FW does not have error recovery support */
5595         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5596                 return 0;
5597
5598         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5599
5600         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5601
5602         HWRM_CHECK_RESULT();
5603
5604         flags = rte_le_to_cpu_32(resp->flags);
5605         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5606                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5607         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5608                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5609
5610         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5611             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5612                 rc = -EINVAL;
5613                 goto err;
5614         }
5615
5616         /* FW returned values are in units of 100msec */
5617         info->driver_polling_freq =
5618                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5619         info->master_func_wait_period =
5620                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5621         info->normal_func_wait_period =
5622                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5623         info->master_func_wait_period_after_reset =
5624                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5625         info->max_bailout_time_after_reset =
5626                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5627         info->status_regs[BNXT_FW_STATUS_REG] =
5628                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5629         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5630                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5631         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5632                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5633         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5634                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5635         info->reg_array_cnt =
5636                 rte_le_to_cpu_32(resp->reg_array_cnt);
5637
5638         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5639                 rc = -EINVAL;
5640                 goto err;
5641         }
5642
5643         for (i = 0; i < info->reg_array_cnt; i++) {
5644                 info->reset_reg[i] =
5645                         rte_le_to_cpu_32(resp->reset_reg[i]);
5646                 info->reset_reg_val[i] =
5647                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5648                 info->delay_after_reset[i] =
5649                         resp->delay_after_reset[i];
5650         }
5651 err:
5652         HWRM_UNLOCK();
5653
5654         /* Map the FW status registers */
5655         if (!rc)
5656                 rc = bnxt_map_fw_health_status_regs(bp);
5657
5658         if (rc) {
5659                 rte_free(bp->recovery_info);
5660                 bp->recovery_info = NULL;
5661         }
5662         return rc;
5663 }
5664
5665 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5666 {
5667         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5668         struct hwrm_fw_reset_input req = {0};
5669         int rc;
5670
5671         if (!BNXT_PF(bp))
5672                 return -EOPNOTSUPP;
5673
5674         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5675
5676         req.embedded_proc_type =
5677                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5678         req.selfrst_status =
5679                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5680         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5681
5682         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5683                                     BNXT_USE_KONG(bp));
5684
5685         HWRM_CHECK_RESULT();
5686         HWRM_UNLOCK();
5687
5688         return rc;
5689 }
5690
5691 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5692 {
5693         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5694         struct hwrm_port_ts_query_input req = {0};
5695         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5696         uint32_t flags = 0;
5697         int rc;
5698
5699         if (!ptp)
5700                 return 0;
5701
5702         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5703
5704         switch (path) {
5705         case BNXT_PTP_FLAGS_PATH_TX:
5706                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5707                 break;
5708         case BNXT_PTP_FLAGS_PATH_RX:
5709                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5710                 break;
5711         case BNXT_PTP_FLAGS_CURRENT_TIME:
5712                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5713                 break;
5714         }
5715
5716         req.flags = rte_cpu_to_le_32(flags);
5717         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5718
5719         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5720
5721         HWRM_CHECK_RESULT();
5722
5723         if (timestamp) {
5724                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5725                 *timestamp |=
5726                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5727         }
5728         HWRM_UNLOCK();
5729
5730         return rc;
5731 }
5732
5733 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5734 {
5735         int rc = 0;
5736
5737         struct hwrm_cfa_counter_qcaps_input req = {0};
5738         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5739
5740         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5741                 PMD_DRV_LOG(DEBUG,
5742                             "Not a PF or trusted VF. Command not supported\n");
5743                 return 0;
5744         }
5745
5746         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5747         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5748         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5749
5750         HWRM_CHECK_RESULT();
5751         if (max_fc)
5752                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5753         HWRM_UNLOCK();
5754
5755         return 0;
5756 }
5757
5758 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5759 {
5760         int rc = 0;
5761         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5762         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5763
5764         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5765                 PMD_DRV_LOG(DEBUG,
5766                             "Not a PF or trusted VF. Command not supported\n");
5767                 return 0;
5768         }
5769
5770         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5771
5772         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5773         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5774         req.page_dir = rte_cpu_to_le_64(dma_addr);
5775
5776         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5777
5778         HWRM_CHECK_RESULT();
5779         if (ctx_id) {
5780                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5781                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5782         }
5783         HWRM_UNLOCK();
5784
5785         return 0;
5786 }
5787
5788 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5789 {
5790         int rc = 0;
5791         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5792         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5793
5794         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5795                 PMD_DRV_LOG(DEBUG,
5796                             "Not a PF or trusted VF. Command not supported\n");
5797                 return 0;
5798         }
5799
5800         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5801
5802         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5803
5804         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5805
5806         HWRM_CHECK_RESULT();
5807         HWRM_UNLOCK();
5808
5809         return rc;
5810 }
5811
5812 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5813                               uint16_t cntr, uint16_t ctx_id,
5814                               uint32_t num_entries, bool enable)
5815 {
5816         struct hwrm_cfa_counter_cfg_input req = {0};
5817         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5818         uint16_t flags = 0;
5819         int rc;
5820
5821         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5822                 PMD_DRV_LOG(DEBUG,
5823                             "Not a PF or trusted VF. Command not supported\n");
5824                 return 0;
5825         }
5826
5827         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5828
5829         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5830         req.counter_type = rte_cpu_to_le_16(cntr);
5831         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5832                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5833         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5834         if (dir == BNXT_DIR_RX)
5835                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5836         else if (dir == BNXT_DIR_TX)
5837                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5838         req.flags = rte_cpu_to_le_16(flags);
5839         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5840         req.num_entries = rte_cpu_to_le_32(num_entries);
5841
5842         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5843         HWRM_CHECK_RESULT();
5844         HWRM_UNLOCK();
5845
5846         return 0;
5847 }
5848
5849 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5850                                  enum bnxt_flow_dir dir,
5851                                  uint16_t cntr,
5852                                  uint16_t num_entries)
5853 {
5854         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5855         struct hwrm_cfa_counter_qstats_input req = {0};
5856         uint16_t flow_ctx_id = 0;
5857         uint16_t flags = 0;
5858         int rc = 0;
5859
5860         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5861                 PMD_DRV_LOG(DEBUG,
5862                             "Not a PF or trusted VF. Command not supported\n");
5863                 return 0;
5864         }
5865
5866         if (dir == BNXT_DIR_RX) {
5867                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5868                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5869         } else if (dir == BNXT_DIR_TX) {
5870                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5871                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5872         }
5873
5874         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5875         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5876         req.counter_type = rte_cpu_to_le_16(cntr);
5877         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5878         req.num_entries = rte_cpu_to_le_16(num_entries);
5879         req.flags = rte_cpu_to_le_16(flags);
5880         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5881
5882         HWRM_CHECK_RESULT();
5883         HWRM_UNLOCK();
5884
5885         return 0;
5886 }
5887
5888 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5889                                 uint16_t *first_vf_id)
5890 {
5891         int rc = 0;
5892         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5893         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5894
5895         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5896
5897         req.fid = rte_cpu_to_le_16(fid);
5898
5899         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5900
5901         HWRM_CHECK_RESULT();
5902
5903         if (first_vf_id)
5904                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5905
5906         HWRM_UNLOCK();
5907
5908         return rc;
5909 }
5910
5911 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5912 {
5913         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5914         struct hwrm_cfa_pair_alloc_input req = {0};
5915         int rc;
5916
5917         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5918                 PMD_DRV_LOG(DEBUG,
5919                             "Not a PF or trusted VF. Command not supported\n");
5920                 return 0;
5921         }
5922
5923         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5924         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5925         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5926                  bp->eth_dev->data->name, rep_bp->vf_id);
5927
5928         req.pf_b_id = rep_bp->parent_pf_idx;
5929         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5930                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5931         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5932         req.host_b_id = 1; /* TBD - Confirm if this is OK */
5933
5934         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5935                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5936         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5937                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5938         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5939                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5940         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5941                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5942
5943         req.q_ab = rep_bp->rep_q_r2f;
5944         req.q_ba = rep_bp->rep_q_f2r;
5945         req.fc_ab = rep_bp->rep_fc_r2f;
5946         req.fc_ba = rep_bp->rep_fc_f2r;
5947
5948         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5949         HWRM_CHECK_RESULT();
5950
5951         HWRM_UNLOCK();
5952         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5953                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5954         return rc;
5955 }
5956
5957 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5958 {
5959         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5960         struct hwrm_cfa_pair_free_input req = {0};
5961         int rc;
5962
5963         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5964                 PMD_DRV_LOG(DEBUG,
5965                             "Not a PF or trusted VF. Command not supported\n");
5966                 return 0;
5967         }
5968
5969         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5970         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5971                  bp->eth_dev->data->name, rep_bp->vf_id);
5972         req.pf_b_id = rep_bp->parent_pf_idx;
5973         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5974         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5975                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5976         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5977         HWRM_CHECK_RESULT();
5978         HWRM_UNLOCK();
5979         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
5980                     rep_bp->vf_id);
5981         return rc;
5982 }
5983
5984 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5985 {
5986         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5987                                         bp->hwrm_cmd_resp_addr;
5988         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5989         uint32_t flags = 0;
5990         int rc = 0;
5991
5992         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5993                 return 0;
5994
5995         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5996                 PMD_DRV_LOG(DEBUG,
5997                             "Not a PF or trusted VF. Command not supported\n");
5998                 return 0;
5999         }
6000
6001         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6002         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6003
6004         HWRM_CHECK_RESULT();
6005         flags = rte_le_to_cpu_32(resp->flags);
6006         HWRM_UNLOCK();
6007
6008         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6009                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6010         else
6011                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6012
6013         return rc;
6014 }
6015
6016 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6017                             uint32_t echo_req_data2)
6018 {
6019         struct hwrm_func_echo_response_input req = {0};
6020         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6021         int rc;
6022
6023         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6024         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6025         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6026
6027         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6028
6029         HWRM_CHECK_RESULT();
6030         HWRM_UNLOCK();
6031
6032         return rc;
6033 }
6034
6035 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6036 {
6037         struct hwrm_ver_get_input req = {.req_type = 0 };
6038         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6039         int rc = 0;
6040
6041         bp->max_req_len = HWRM_MAX_REQ_LEN;
6042         bp->max_resp_len = BNXT_PAGE_SIZE;
6043         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6044
6045         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6046         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6047         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6048         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6049
6050         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6051
6052         HWRM_CHECK_RESULT_SILENT();
6053
6054         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6055                 rc = -EAGAIN;
6056
6057         HWRM_UNLOCK();
6058
6059         return rc;
6060 }