1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SPEC_CODE_1_8_3 0x10803
31 #define HWRM_VERSION_1_9_1 0x10901
32 #define HWRM_VERSION_1_9_2 0x10903
34 struct bnxt_plcmodes_cfg {
36 uint16_t jumbo_thresh;
38 uint16_t hds_threshold;
41 static int page_getenum(size_t size)
57 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
58 return sizeof(void *) * 8 - 1;
61 static int page_roundup(size_t size)
63 return 1 << page_getenum(size);
66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
79 * HWRM Functions (sent to HWRM)
80 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
81 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
82 * command was failed by the ChiMP.
85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
86 uint32_t msg_len, bool use_kong_mb)
89 struct input *req = msg;
90 struct output *resp = bp->hwrm_cmd_resp_addr;
94 uint16_t max_req_len = bp->max_req_len;
95 struct hwrm_short_input short_input = { 0 };
96 uint16_t bar_offset = use_kong_mb ?
97 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
98 uint16_t mb_trigger_offset = use_kong_mb ?
99 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
101 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
102 msg_len > bp->max_req_len) {
103 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
105 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
106 memcpy(short_cmd_req, req, msg_len);
108 short_input.req_type = rte_cpu_to_le_16(req->req_type);
109 short_input.signature = rte_cpu_to_le_16(
110 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
111 short_input.size = rte_cpu_to_le_16(msg_len);
112 short_input.req_addr =
113 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
115 data = (uint32_t *)&short_input;
116 msg_len = sizeof(short_input);
118 /* Sync memory write before updating doorbell */
121 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
124 /* Write request msg to hwrm channel */
125 for (i = 0; i < msg_len; i += 4) {
126 bar = (uint8_t *)bp->bar0 + bar_offset + i;
127 rte_write32(*data, bar);
131 /* Zero the rest of the request space */
132 for (; i < max_req_len; i += 4) {
133 bar = (uint8_t *)bp->bar0 + bar_offset + i;
137 /* Ring channel doorbell */
138 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
141 /* Poll for the valid bit */
142 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
143 /* Sanity check on the resp->resp_len */
145 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
146 /* Last byte of resp contains the valid key */
147 valid = (uint8_t *)resp + resp->resp_len - 1;
148 if (*valid == HWRM_RESP_VALID_KEY)
154 if (i >= HWRM_CMD_TIMEOUT) {
155 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
166 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
167 * spinlock, and does initial processing.
169 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
170 * releases the spinlock only if it returns. If the regular int return codes
171 * are not used by the function, HWRM_CHECK_RESULT() should not be used
172 * directly, rather it should be copied and modified to suit the function.
174 * HWRM_UNLOCK() must be called after all response processing is completed.
176 #define HWRM_PREP(req, type, kong) do { \
177 rte_spinlock_lock(&bp->hwrm_lock); \
178 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
179 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
180 req.cmpl_ring = rte_cpu_to_le_16(-1); \
181 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
182 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
183 req.target_id = rte_cpu_to_le_16(0xffff); \
184 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
187 #define HWRM_CHECK_RESULT_SILENT() do {\
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 if (resp->error_code) { \
193 rc = rte_le_to_cpu_16(resp->error_code); \
194 rte_spinlock_unlock(&bp->hwrm_lock); \
199 #define HWRM_CHECK_RESULT() do {\
201 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
202 rte_spinlock_unlock(&bp->hwrm_lock); \
203 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 if (resp->resp_len >= 16) { \
212 struct hwrm_err_output *tmp_hwrm_err_op = \
215 "error %d:%d:%08x:%04x\n", \
216 rc, tmp_hwrm_err_op->cmd_err, \
218 tmp_hwrm_err_op->opaque_0), \
220 tmp_hwrm_err_op->opaque_1)); \
222 PMD_DRV_LOG(ERR, "error %d\n", rc); \
224 rte_spinlock_unlock(&bp->hwrm_lock); \
225 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
233 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
238 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
239 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
241 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
242 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
254 struct bnxt_vnic_info *vnic,
256 struct bnxt_vlan_table_entry *vlan_table)
259 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
260 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
263 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
269 /* FIXME add multicast flag, when multicast adding options is supported
272 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
273 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
274 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
275 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
276 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
277 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
278 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
279 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
280 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
281 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
282 if (vnic->mc_addr_cnt) {
283 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
284 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
285 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
288 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
290 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
291 rte_mem_virt2iova(vlan_table));
292 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
294 req.mask = rte_cpu_to_le_32(mask);
296 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
306 struct bnxt_vlan_antispoof_table_entry *vlan_table)
309 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
310 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
311 bp->hwrm_cmd_resp_addr;
314 * Older HWRM versions did not support this command, and the set_rx_mask
315 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
316 * removed from set_rx_mask call, and this command was added.
318 * This command is also present from 1.7.8.11 and higher,
321 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
322 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
323 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
328 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
329 req.fid = rte_cpu_to_le_16(fid);
331 req.vlan_tag_mask_tbl_addr =
332 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
333 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
344 struct bnxt_filter_info *filter)
347 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
348 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
350 if (filter->fw_l2_filter_id == UINT64_MAX)
353 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
355 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
362 filter->fw_l2_filter_id = UINT64_MAX;
367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
369 struct bnxt_filter_info *filter)
372 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
374 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
375 const struct rte_eth_vmdq_rx_conf *conf =
376 &dev_conf->rx_adv_conf.vmdq_rx_conf;
377 uint32_t enables = 0;
378 uint16_t j = dst_id - 1;
380 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
381 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
382 conf->pool_map[j].pools & (1UL << j)) {
384 "Add vlan %u to vmdq pool %u\n",
385 conf->pool_map[j].vlan_id, j);
387 filter->l2_ivlan = conf->pool_map[j].vlan_id;
389 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
393 if (filter->fw_l2_filter_id != UINT64_MAX)
394 bnxt_hwrm_clear_l2_filter(bp, filter);
396 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
398 req.flags = rte_cpu_to_le_32(filter->flags);
400 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
402 enables = filter->enables |
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
404 req.dst_id = rte_cpu_to_le_16(dst_id);
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
408 memcpy(req.l2_addr, filter->l2_addr,
411 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
412 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
415 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
416 req.l2_ovlan = filter->l2_ovlan;
418 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
419 req.l2_ivlan = filter->l2_ivlan;
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
422 req.l2_ovlan_mask = filter->l2_ovlan_mask;
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
425 req.l2_ivlan_mask = filter->l2_ivlan_mask;
426 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
427 req.src_id = rte_cpu_to_le_32(filter->src_id);
428 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
429 req.src_type = filter->src_type;
431 req.enables = rte_cpu_to_le_32(enables);
433 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
437 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
445 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
446 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
453 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
456 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
459 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
460 if (ptp->tx_tstamp_en)
461 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
464 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
465 req.flags = rte_cpu_to_le_32(flags);
466 req.enables = rte_cpu_to_le_32
467 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
468 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
470 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
479 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
480 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
481 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
483 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
487 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
489 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
495 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
498 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
502 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
503 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
504 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
505 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
506 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
507 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
508 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
509 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
510 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
511 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
512 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
513 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
514 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
515 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
516 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
517 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
518 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
519 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
530 struct hwrm_func_qcaps_input req = {.req_type = 0 };
531 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
532 uint16_t new_max_vfs;
536 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
538 req.fid = rte_cpu_to_le_16(0xffff);
540 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
544 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
545 flags = rte_le_to_cpu_32(resp->flags);
547 bp->pf.port_id = resp->port_id;
548 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
549 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
550 new_max_vfs = bp->pdev->max_vfs;
551 if (new_max_vfs != bp->pf.max_vfs) {
553 rte_free(bp->pf.vf_info);
554 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
555 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
556 bp->pf.max_vfs = new_max_vfs;
557 for (i = 0; i < new_max_vfs; i++) {
558 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
559 bp->pf.vf_info[i].vlan_table =
560 rte_zmalloc("VF VLAN table",
563 if (bp->pf.vf_info[i].vlan_table == NULL)
565 "Fail to alloc VLAN table for VF %d\n",
569 bp->pf.vf_info[i].vlan_table);
570 bp->pf.vf_info[i].vlan_as_table =
571 rte_zmalloc("VF VLAN AS table",
574 if (bp->pf.vf_info[i].vlan_as_table == NULL)
576 "Alloc VLAN AS table for VF %d fail\n",
580 bp->pf.vf_info[i].vlan_as_table);
581 STAILQ_INIT(&bp->pf.vf_info[i].filter);
586 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
587 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
588 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
589 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
590 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
591 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
592 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
593 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
595 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
596 /* TODO: For now, do not support VMDq/RFS on VFs. */
601 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
605 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
607 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
608 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
609 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
610 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
612 bnxt_hwrm_ptp_qcfg(bp);
616 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
617 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
624 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
628 rc = __bnxt_hwrm_func_qcaps(bp);
629 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
630 rc = bnxt_alloc_ctx_mem(bp);
634 rc = bnxt_hwrm_func_resc_qcaps(bp);
636 bp->flags |= BNXT_FLAG_NEW_RM;
642 int bnxt_hwrm_func_reset(struct bnxt *bp)
645 struct hwrm_func_reset_input req = {.req_type = 0 };
646 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
648 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
650 req.enables = rte_cpu_to_le_32(0);
652 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
660 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
663 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
664 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
666 if (bp->flags & BNXT_FLAG_REGISTERED)
669 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
670 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
671 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
672 req.ver_maj = RTE_VER_YEAR;
673 req.ver_min = RTE_VER_MONTH;
674 req.ver_upd = RTE_VER_MINOR;
677 req.enables |= rte_cpu_to_le_32(
678 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
679 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
680 RTE_MIN(sizeof(req.vf_req_fwd),
681 sizeof(bp->pf.vf_req_fwd)));
684 * PF can sniff HWRM API issued by VF. This can be set up by
685 * linux driver and inherited by the DPDK PF driver. Clear
686 * this HWRM sniffer list in FW because DPDK PF driver does
690 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
693 req.async_event_fwd[0] |=
694 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
695 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
696 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
697 req.async_event_fwd[1] |=
698 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
699 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
701 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
706 bp->flags |= BNXT_FLAG_REGISTERED;
711 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
713 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
716 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
719 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
724 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
725 struct hwrm_func_vf_cfg_input req = {0};
727 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
729 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
730 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
731 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
732 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
733 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
735 if (BNXT_HAS_RING_GRPS(bp)) {
736 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
737 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
740 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
741 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
742 AGG_RING_MULTIPLIER);
743 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
744 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
746 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
747 if (bp->vf_resv_strategy ==
748 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
749 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
750 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
751 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
752 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
753 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
754 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
758 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
759 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
760 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
761 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
762 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
763 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
765 if (test && BNXT_HAS_RING_GRPS(bp))
766 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
768 req.flags = rte_cpu_to_le_32(flags);
769 req.enables |= rte_cpu_to_le_32(enables);
771 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
774 HWRM_CHECK_RESULT_SILENT();
782 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
785 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
786 struct hwrm_func_resource_qcaps_input req = {0};
788 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
789 req.fid = rte_cpu_to_le_16(0xffff);
791 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
796 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
797 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
798 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
799 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
800 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
801 /* func_resource_qcaps does not return max_rx_em_flows.
802 * So use the value provided by func_qcaps.
805 rte_le_to_cpu_16(resp->max_l2_ctxs) +
807 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
808 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
810 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
811 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
812 if (bp->vf_resv_strategy >
813 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
814 bp->vf_resv_strategy =
815 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
821 int bnxt_hwrm_ver_get(struct bnxt *bp)
824 struct hwrm_ver_get_input req = {.req_type = 0 };
825 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
827 uint16_t max_resp_len;
828 char type[RTE_MEMZONE_NAMESIZE];
829 uint32_t dev_caps_cfg;
831 bp->max_req_len = HWRM_MAX_REQ_LEN;
832 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
834 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
835 req.hwrm_intf_min = HWRM_VERSION_MINOR;
836 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
838 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
842 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
843 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
844 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
845 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
846 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
847 (resp->hwrm_fw_min_8b << 16) |
848 (resp->hwrm_fw_bld_8b << 8) |
849 resp->hwrm_fw_rsvd_8b;
850 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
851 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
853 fw_version = resp->hwrm_intf_maj_8b << 16;
854 fw_version |= resp->hwrm_intf_min_8b << 8;
855 fw_version |= resp->hwrm_intf_upd_8b;
856 bp->hwrm_spec_code = fw_version;
858 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
859 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
864 if (bp->max_req_len > resp->max_req_win_len) {
865 PMD_DRV_LOG(ERR, "Unsupported request length\n");
868 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
869 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
870 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
871 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
873 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
874 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
876 if (bp->max_resp_len != max_resp_len) {
877 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
878 bp->pdev->addr.domain, bp->pdev->addr.bus,
879 bp->pdev->addr.devid, bp->pdev->addr.function);
881 rte_free(bp->hwrm_cmd_resp_addr);
883 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
884 if (bp->hwrm_cmd_resp_addr == NULL) {
888 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
889 bp->hwrm_cmd_resp_dma_addr =
890 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
891 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
893 "Unable to map response buffer to physical memory.\n");
897 bp->max_resp_len = max_resp_len;
901 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
903 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
904 PMD_DRV_LOG(DEBUG, "Short command supported\n");
905 bp->flags |= BNXT_FLAG_SHORT_CMD;
909 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
911 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
912 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
913 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
914 bp->pdev->addr.domain, bp->pdev->addr.bus,
915 bp->pdev->addr.devid, bp->pdev->addr.function);
917 rte_free(bp->hwrm_short_cmd_req_addr);
919 bp->hwrm_short_cmd_req_addr =
920 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
921 if (bp->hwrm_short_cmd_req_addr == NULL) {
925 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
926 bp->hwrm_short_cmd_req_dma_addr =
927 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
928 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
929 rte_free(bp->hwrm_short_cmd_req_addr);
931 "Unable to map buffer to physical memory.\n");
937 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
938 bp->flags |= BNXT_FLAG_KONG_MB_EN;
939 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
942 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
943 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
950 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
953 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
954 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
956 if (!(bp->flags & BNXT_FLAG_REGISTERED))
959 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
962 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
967 bp->flags &= ~BNXT_FLAG_REGISTERED;
972 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
975 struct hwrm_port_phy_cfg_input req = {0};
976 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
977 uint32_t enables = 0;
979 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
982 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
983 if (bp->link_info.auto_mode && conf->link_speed) {
984 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
985 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
988 req.flags = rte_cpu_to_le_32(conf->phy_flags);
989 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
990 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
992 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
993 * any auto mode, even "none".
995 if (!conf->link_speed) {
996 /* No speeds specified. Enable AutoNeg - all speeds */
998 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1000 /* AutoNeg - Advertise speeds specified. */
1001 if (conf->auto_link_speed_mask &&
1002 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1004 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1005 req.auto_link_speed_mask =
1006 conf->auto_link_speed_mask;
1008 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1011 req.auto_duplex = conf->duplex;
1012 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1013 req.auto_pause = conf->auto_pause;
1014 req.force_pause = conf->force_pause;
1015 /* Set force_pause if there is no auto or if there is a force */
1016 if (req.auto_pause && !req.force_pause)
1017 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1019 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1021 req.enables = rte_cpu_to_le_32(enables);
1024 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1025 PMD_DRV_LOG(INFO, "Force Link Down\n");
1028 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1030 HWRM_CHECK_RESULT();
1036 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1037 struct bnxt_link_info *link_info)
1040 struct hwrm_port_phy_qcfg_input req = {0};
1041 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1043 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1045 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1047 HWRM_CHECK_RESULT();
1049 link_info->phy_link_status = resp->link;
1050 link_info->link_up =
1051 (link_info->phy_link_status ==
1052 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1053 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1054 link_info->duplex = resp->duplex_cfg;
1055 link_info->pause = resp->pause;
1056 link_info->auto_pause = resp->auto_pause;
1057 link_info->force_pause = resp->force_pause;
1058 link_info->auto_mode = resp->auto_mode;
1059 link_info->phy_type = resp->phy_type;
1060 link_info->media_type = resp->media_type;
1062 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1063 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1064 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1065 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1066 link_info->phy_ver[0] = resp->phy_maj;
1067 link_info->phy_ver[1] = resp->phy_min;
1068 link_info->phy_ver[2] = resp->phy_bld;
1072 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1073 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1074 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1075 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1076 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1077 link_info->auto_link_speed_mask);
1078 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1079 link_info->force_link_speed);
1084 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1087 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1088 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1091 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1093 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1094 /* HWRM Version >= 1.9.1 */
1095 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1097 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1098 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1100 HWRM_CHECK_RESULT();
1102 #define GET_QUEUE_INFO(x) \
1103 bp->cos_queue[x].id = resp->queue_id##x; \
1104 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1117 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1118 bp->tx_cosq_id = bp->cos_queue[0].id;
1120 /* iterate and find the COSq profile to use for Tx */
1121 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1122 if (bp->cos_queue[i].profile ==
1123 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1124 bp->tx_cosq_id = bp->cos_queue[i].id;
1130 bp->max_tc = resp->max_configurable_queues;
1131 bp->max_lltc = resp->max_configurable_lossless_queues;
1132 if (bp->max_tc > BNXT_MAX_QUEUE)
1133 bp->max_tc = BNXT_MAX_QUEUE;
1134 bp->max_q = bp->max_tc;
1136 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1141 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1142 struct bnxt_ring *ring,
1143 uint32_t ring_type, uint32_t map_index,
1144 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1147 uint32_t enables = 0;
1148 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1149 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1150 struct rte_mempool *mb_pool;
1151 uint16_t rx_buf_size;
1153 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1155 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1156 req.fbo = rte_cpu_to_le_32(0);
1157 /* Association of ring index with doorbell index */
1158 req.logical_id = rte_cpu_to_le_16(map_index);
1159 req.length = rte_cpu_to_le_32(ring->ring_size);
1161 switch (ring_type) {
1162 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1163 req.ring_type = ring_type;
1164 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1165 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1166 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1167 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1169 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1171 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1172 req.ring_type = ring_type;
1173 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1174 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1175 if (BNXT_CHIP_THOR(bp)) {
1176 mb_pool = bp->rx_queues[0]->mb_pool;
1177 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1178 RTE_PKTMBUF_HEADROOM;
1179 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1181 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1183 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1185 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1187 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1188 req.ring_type = ring_type;
1189 if (BNXT_HAS_NQ(bp)) {
1190 /* Association of cp ring with nq */
1191 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1193 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1195 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1197 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1198 req.ring_type = ring_type;
1199 req.page_size = BNXT_PAGE_SHFT;
1200 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1202 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1203 req.ring_type = ring_type;
1204 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1206 mb_pool = bp->rx_queues[0]->mb_pool;
1207 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1208 RTE_PKTMBUF_HEADROOM;
1209 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1211 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1212 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1213 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1214 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1217 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1222 req.enables = rte_cpu_to_le_32(enables);
1224 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1226 if (rc || resp->error_code) {
1227 if (rc == 0 && resp->error_code)
1228 rc = rte_le_to_cpu_16(resp->error_code);
1229 switch (ring_type) {
1230 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1232 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1235 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1237 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1240 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1242 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1246 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1248 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1251 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1253 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1257 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1263 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1268 int bnxt_hwrm_ring_free(struct bnxt *bp,
1269 struct bnxt_ring *ring, uint32_t ring_type)
1272 struct hwrm_ring_free_input req = {.req_type = 0 };
1273 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1275 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1277 req.ring_type = ring_type;
1278 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1280 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1282 if (rc || resp->error_code) {
1283 if (rc == 0 && resp->error_code)
1284 rc = rte_le_to_cpu_16(resp->error_code);
1287 switch (ring_type) {
1288 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1289 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1292 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1293 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1296 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1297 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1300 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1302 "hwrm_ring_free nq failed. rc:%d\n", rc);
1304 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1306 "hwrm_ring_free agg failed. rc:%d\n", rc);
1309 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1317 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1320 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1321 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1323 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1325 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1326 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1327 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1328 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1330 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1332 HWRM_CHECK_RESULT();
1334 bp->grp_info[idx].fw_grp_id =
1335 rte_le_to_cpu_16(resp->ring_group_id);
1342 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1345 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1346 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1348 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1350 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1352 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1354 HWRM_CHECK_RESULT();
1357 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1361 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1364 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1365 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1367 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1370 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1372 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1374 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1376 HWRM_CHECK_RESULT();
1382 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1383 unsigned int idx __rte_unused)
1386 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1387 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1389 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1391 req.update_period_ms = rte_cpu_to_le_32(0);
1393 req.stats_dma_addr =
1394 rte_cpu_to_le_64(cpr->hw_stats_map);
1396 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1398 HWRM_CHECK_RESULT();
1400 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1407 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1408 unsigned int idx __rte_unused)
1411 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1412 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1414 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1416 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1418 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1420 HWRM_CHECK_RESULT();
1426 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1429 struct hwrm_vnic_alloc_input req = { 0 };
1430 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1432 if (!BNXT_HAS_RING_GRPS(bp))
1433 goto skip_ring_grps;
1435 /* map ring groups to this vnic */
1436 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1437 vnic->start_grp_id, vnic->end_grp_id);
1438 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1439 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1441 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1442 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1443 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1444 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1447 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1448 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1449 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1451 if (vnic->func_default)
1453 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1454 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1456 HWRM_CHECK_RESULT();
1458 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1460 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1464 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1465 struct bnxt_vnic_info *vnic,
1466 struct bnxt_plcmodes_cfg *pmode)
1469 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1470 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1472 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1474 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1476 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1478 HWRM_CHECK_RESULT();
1480 pmode->flags = rte_le_to_cpu_32(resp->flags);
1481 /* dflt_vnic bit doesn't exist in the _cfg command */
1482 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1483 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1484 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1485 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1492 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1493 struct bnxt_vnic_info *vnic,
1494 struct bnxt_plcmodes_cfg *pmode)
1497 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1498 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1500 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1501 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1505 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1507 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1508 req.flags = rte_cpu_to_le_32(pmode->flags);
1509 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1510 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1511 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1512 req.enables = rte_cpu_to_le_32(
1513 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1514 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1515 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1518 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1520 HWRM_CHECK_RESULT();
1526 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1529 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1530 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1531 struct bnxt_plcmodes_cfg pmodes = { 0 };
1532 uint32_t ctx_enable_flag = 0;
1533 uint32_t enables = 0;
1535 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1536 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1540 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1544 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1546 if (BNXT_CHIP_THOR(bp)) {
1547 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1548 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1549 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1551 req.default_rx_ring_id =
1552 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1553 req.default_cmpl_ring_id =
1554 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1555 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1556 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1560 /* Only RSS support for now TBD: COS & LB */
1561 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1562 if (vnic->lb_rule != 0xffff)
1563 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1564 if (vnic->cos_rule != 0xffff)
1565 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1566 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1567 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1568 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1570 enables |= ctx_enable_flag;
1571 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1572 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1573 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1574 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1577 req.enables = rte_cpu_to_le_32(enables);
1578 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1579 req.mru = rte_cpu_to_le_16(vnic->mru);
1580 /* Configure default VNIC only once. */
1581 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1583 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1584 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1586 if (vnic->vlan_strip)
1588 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1591 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1592 if (vnic->roce_dual)
1593 req.flags |= rte_cpu_to_le_32(
1594 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1595 if (vnic->roce_only)
1596 req.flags |= rte_cpu_to_le_32(
1597 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1598 if (vnic->rss_dflt_cr)
1599 req.flags |= rte_cpu_to_le_32(
1600 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1602 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1604 HWRM_CHECK_RESULT();
1607 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1612 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1616 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1617 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1619 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1620 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1623 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1626 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1627 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1628 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1630 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1632 HWRM_CHECK_RESULT();
1634 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1635 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1636 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1637 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1638 vnic->mru = rte_le_to_cpu_16(resp->mru);
1639 vnic->func_default = rte_le_to_cpu_32(
1640 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1641 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1642 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1643 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1644 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1645 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1646 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1647 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1648 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1649 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1650 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1657 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1658 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1662 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1663 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1664 bp->hwrm_cmd_resp_addr;
1666 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1668 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1669 HWRM_CHECK_RESULT();
1671 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1672 if (!BNXT_HAS_RING_GRPS(bp))
1673 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1674 else if (ctx_idx == 0)
1675 vnic->rss_rule = ctx_id;
1682 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1683 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1686 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1687 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1688 bp->hwrm_cmd_resp_addr;
1690 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1691 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1694 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1696 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1698 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1700 HWRM_CHECK_RESULT();
1706 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1709 struct hwrm_vnic_free_input req = {.req_type = 0 };
1710 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1712 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1713 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1717 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1719 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1721 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1723 HWRM_CHECK_RESULT();
1726 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1727 /* Configure default VNIC again if necessary. */
1728 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1729 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1735 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1739 int nr_ctxs = bp->max_ring_grps;
1740 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1741 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1743 if (!(vnic->rss_table && vnic->hash_type))
1746 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1748 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1749 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1750 req.hash_mode_flags = vnic->hash_mode;
1752 req.hash_key_tbl_addr =
1753 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1755 for (i = 0; i < nr_ctxs; i++) {
1756 req.ring_grp_tbl_addr =
1757 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1758 i * HW_HASH_INDEX_SIZE);
1759 req.ring_table_pair_index = i;
1760 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1762 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1765 HWRM_CHECK_RESULT();
1775 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1776 struct bnxt_vnic_info *vnic)
1779 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1780 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1782 if (BNXT_CHIP_THOR(bp))
1783 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1785 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1787 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1788 req.hash_mode_flags = vnic->hash_mode;
1790 req.ring_grp_tbl_addr =
1791 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1792 req.hash_key_tbl_addr =
1793 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1794 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1795 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1797 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1799 HWRM_CHECK_RESULT();
1805 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1806 struct bnxt_vnic_info *vnic)
1809 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1810 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1813 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1814 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1818 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1820 req.flags = rte_cpu_to_le_32(
1821 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1823 req.enables = rte_cpu_to_le_32(
1824 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1826 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1827 size -= RTE_PKTMBUF_HEADROOM;
1829 req.jumbo_thresh = rte_cpu_to_le_16(size);
1830 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1832 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1834 HWRM_CHECK_RESULT();
1840 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1841 struct bnxt_vnic_info *vnic, bool enable)
1844 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1845 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1847 if (BNXT_CHIP_THOR(bp))
1850 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1853 req.enables = rte_cpu_to_le_32(
1854 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1855 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1856 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1857 req.flags = rte_cpu_to_le_32(
1858 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1859 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1860 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1861 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1862 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1863 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1864 req.max_agg_segs = rte_cpu_to_le_16(5);
1866 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1867 req.min_agg_len = rte_cpu_to_le_32(512);
1869 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1871 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1873 HWRM_CHECK_RESULT();
1879 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1881 struct hwrm_func_cfg_input req = {0};
1882 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1885 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1886 req.enables = rte_cpu_to_le_32(
1887 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1888 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1889 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1891 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1893 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1894 HWRM_CHECK_RESULT();
1897 bp->pf.vf_info[vf].random_mac = false;
1902 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1906 struct hwrm_func_qstats_input req = {.req_type = 0};
1907 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1909 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1911 req.fid = rte_cpu_to_le_16(fid);
1913 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1915 HWRM_CHECK_RESULT();
1918 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1925 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1926 struct rte_eth_stats *stats)
1929 struct hwrm_func_qstats_input req = {.req_type = 0};
1930 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1932 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1934 req.fid = rte_cpu_to_le_16(fid);
1936 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1938 HWRM_CHECK_RESULT();
1940 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1941 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1942 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1943 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1944 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1945 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1947 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1948 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1949 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1950 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1951 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1952 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1954 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1955 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1956 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1963 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1966 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1967 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1969 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1971 req.fid = rte_cpu_to_le_16(fid);
1973 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1975 HWRM_CHECK_RESULT();
1982 * HWRM utility functions
1985 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1990 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1991 struct bnxt_tx_queue *txq;
1992 struct bnxt_rx_queue *rxq;
1993 struct bnxt_cp_ring_info *cpr;
1995 if (i >= bp->rx_cp_nr_rings) {
1996 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1999 rxq = bp->rx_queues[i];
2003 rc = bnxt_hwrm_stat_clear(bp, cpr);
2010 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2014 struct bnxt_cp_ring_info *cpr;
2016 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2018 if (i >= bp->rx_cp_nr_rings) {
2019 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2021 cpr = bp->rx_queues[i]->cp_ring;
2022 if (BNXT_HAS_RING_GRPS(bp))
2023 bp->grp_info[i].fw_stats_ctx = -1;
2025 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2026 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2027 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2035 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2040 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2041 struct bnxt_tx_queue *txq;
2042 struct bnxt_rx_queue *rxq;
2043 struct bnxt_cp_ring_info *cpr;
2045 if (i >= bp->rx_cp_nr_rings) {
2046 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2049 rxq = bp->rx_queues[i];
2053 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2061 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2066 if (!BNXT_HAS_RING_GRPS(bp))
2069 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2071 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2074 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2082 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2084 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2086 bnxt_hwrm_ring_free(bp, cp_ring,
2087 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2088 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2089 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2090 sizeof(*cpr->cp_desc_ring));
2091 cpr->cp_raw_cons = 0;
2094 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2096 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2098 bnxt_hwrm_ring_free(bp, cp_ring,
2099 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2100 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2101 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2102 sizeof(*cpr->cp_desc_ring));
2103 cpr->cp_raw_cons = 0;
2107 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2109 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2110 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2111 struct bnxt_ring *ring = rxr->rx_ring_struct;
2112 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2114 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2115 bnxt_hwrm_ring_free(bp, ring,
2116 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2117 ring->fw_ring_id = INVALID_HW_RING_ID;
2118 if (BNXT_HAS_RING_GRPS(bp))
2119 bp->grp_info[queue_index].rx_fw_ring_id =
2121 memset(rxr->rx_desc_ring, 0,
2122 rxr->rx_ring_struct->ring_size *
2123 sizeof(*rxr->rx_desc_ring));
2124 memset(rxr->rx_buf_ring, 0,
2125 rxr->rx_ring_struct->ring_size *
2126 sizeof(*rxr->rx_buf_ring));
2129 ring = rxr->ag_ring_struct;
2130 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2131 bnxt_hwrm_ring_free(bp, ring,
2132 BNXT_CHIP_THOR(bp) ?
2133 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2134 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2135 ring->fw_ring_id = INVALID_HW_RING_ID;
2136 memset(rxr->ag_buf_ring, 0,
2137 rxr->ag_ring_struct->ring_size *
2138 sizeof(*rxr->ag_buf_ring));
2140 if (BNXT_HAS_RING_GRPS(bp))
2141 bp->grp_info[queue_index].ag_fw_ring_id =
2144 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2145 bnxt_free_cp_ring(bp, cpr);
2147 bnxt_free_nq_ring(bp, rxq->nq_ring);
2150 if (BNXT_HAS_RING_GRPS(bp))
2151 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2154 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2158 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2159 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2160 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2161 struct bnxt_ring *ring = txr->tx_ring_struct;
2162 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2164 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2165 bnxt_hwrm_ring_free(bp, ring,
2166 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2167 ring->fw_ring_id = INVALID_HW_RING_ID;
2168 memset(txr->tx_desc_ring, 0,
2169 txr->tx_ring_struct->ring_size *
2170 sizeof(*txr->tx_desc_ring));
2171 memset(txr->tx_buf_ring, 0,
2172 txr->tx_ring_struct->ring_size *
2173 sizeof(*txr->tx_buf_ring));
2177 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2178 bnxt_free_cp_ring(bp, cpr);
2179 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2181 bnxt_free_nq_ring(bp, txq->nq_ring);
2185 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2186 bnxt_free_hwrm_rx_ring(bp, i);
2191 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2196 if (!BNXT_HAS_RING_GRPS(bp))
2199 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2200 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2207 void bnxt_free_hwrm_resources(struct bnxt *bp)
2209 /* Release memzone */
2210 rte_free(bp->hwrm_cmd_resp_addr);
2211 rte_free(bp->hwrm_short_cmd_req_addr);
2212 bp->hwrm_cmd_resp_addr = NULL;
2213 bp->hwrm_short_cmd_req_addr = NULL;
2214 bp->hwrm_cmd_resp_dma_addr = 0;
2215 bp->hwrm_short_cmd_req_dma_addr = 0;
2218 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2220 struct rte_pci_device *pdev = bp->pdev;
2221 char type[RTE_MEMZONE_NAMESIZE];
2223 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2224 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2225 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2226 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2227 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2228 if (bp->hwrm_cmd_resp_addr == NULL)
2230 bp->hwrm_cmd_resp_dma_addr =
2231 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2232 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2234 "unable to map response address to physical memory\n");
2237 rte_spinlock_init(&bp->hwrm_lock);
2242 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2244 struct bnxt_filter_info *filter;
2247 STAILQ_FOREACH(filter, &vnic->filter, next) {
2248 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2249 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2250 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2251 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2253 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2254 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2262 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2264 struct bnxt_filter_info *filter;
2265 struct rte_flow *flow;
2268 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2269 filter = flow->filter;
2270 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2271 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2272 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2273 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2274 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2276 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2278 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2286 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2288 struct bnxt_filter_info *filter;
2291 STAILQ_FOREACH(filter, &vnic->filter, next) {
2292 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2293 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2295 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2296 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2299 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2307 void bnxt_free_tunnel_ports(struct bnxt *bp)
2309 if (bp->vxlan_port_cnt)
2310 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2311 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2313 if (bp->geneve_port_cnt)
2314 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2315 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2316 bp->geneve_port = 0;
2319 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2323 if (bp->vnic_info == NULL)
2327 * Cleanup VNICs in reverse order, to make sure the L2 filter
2328 * from vnic0 is last to be cleaned up.
2330 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2331 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2333 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2334 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2338 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2340 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2342 if (BNXT_CHIP_THOR(bp)) {
2343 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2344 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2345 vnic->fw_grp_ids[j]);
2346 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2348 vnic->num_lb_ctxts = 0;
2350 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2351 vnic->rss_rule = INVALID_HW_RING_ID;
2354 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2356 bnxt_hwrm_vnic_free(bp, vnic);
2358 rte_free(vnic->fw_grp_ids);
2360 /* Ring resources */
2361 bnxt_free_all_hwrm_rings(bp);
2362 bnxt_free_all_hwrm_ring_grps(bp);
2363 bnxt_free_all_hwrm_stat_ctxs(bp);
2364 bnxt_free_tunnel_ports(bp);
2367 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2369 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2371 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2372 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2374 switch (conf_link_speed) {
2375 case ETH_LINK_SPEED_10M_HD:
2376 case ETH_LINK_SPEED_100M_HD:
2378 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2380 return hw_link_duplex;
2383 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2385 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2388 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2390 uint16_t eth_link_speed = 0;
2392 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2393 return ETH_LINK_SPEED_AUTONEG;
2395 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2396 case ETH_LINK_SPEED_100M:
2397 case ETH_LINK_SPEED_100M_HD:
2400 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2402 case ETH_LINK_SPEED_1G:
2404 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2406 case ETH_LINK_SPEED_2_5G:
2408 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2410 case ETH_LINK_SPEED_10G:
2412 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2414 case ETH_LINK_SPEED_20G:
2416 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2418 case ETH_LINK_SPEED_25G:
2420 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2422 case ETH_LINK_SPEED_40G:
2424 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2426 case ETH_LINK_SPEED_50G:
2428 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2430 case ETH_LINK_SPEED_100G:
2432 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2436 "Unsupported link speed %d; default to AUTO\n",
2440 return eth_link_speed;
2443 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2444 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2445 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2446 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2448 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2452 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2455 if (link_speed & ETH_LINK_SPEED_FIXED) {
2456 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2458 if (one_speed & (one_speed - 1)) {
2460 "Invalid advertised speeds (%u) for port %u\n",
2461 link_speed, port_id);
2464 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2466 "Unsupported advertised speed (%u) for port %u\n",
2467 link_speed, port_id);
2471 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2473 "Unsupported advertised speeds (%u) for port %u\n",
2474 link_speed, port_id);
2482 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2486 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2487 if (bp->link_info.support_speeds)
2488 return bp->link_info.support_speeds;
2489 link_speed = BNXT_SUPPORTED_SPEEDS;
2492 if (link_speed & ETH_LINK_SPEED_100M)
2493 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2494 if (link_speed & ETH_LINK_SPEED_100M_HD)
2495 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2496 if (link_speed & ETH_LINK_SPEED_1G)
2497 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2498 if (link_speed & ETH_LINK_SPEED_2_5G)
2499 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2500 if (link_speed & ETH_LINK_SPEED_10G)
2501 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2502 if (link_speed & ETH_LINK_SPEED_20G)
2503 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2504 if (link_speed & ETH_LINK_SPEED_25G)
2505 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2506 if (link_speed & ETH_LINK_SPEED_40G)
2507 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2508 if (link_speed & ETH_LINK_SPEED_50G)
2509 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2510 if (link_speed & ETH_LINK_SPEED_100G)
2511 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2515 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2517 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2519 switch (hw_link_speed) {
2520 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2521 eth_link_speed = ETH_SPEED_NUM_100M;
2523 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2524 eth_link_speed = ETH_SPEED_NUM_1G;
2526 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2527 eth_link_speed = ETH_SPEED_NUM_2_5G;
2529 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2530 eth_link_speed = ETH_SPEED_NUM_10G;
2532 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2533 eth_link_speed = ETH_SPEED_NUM_20G;
2535 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2536 eth_link_speed = ETH_SPEED_NUM_25G;
2538 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2539 eth_link_speed = ETH_SPEED_NUM_40G;
2541 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2542 eth_link_speed = ETH_SPEED_NUM_50G;
2544 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2545 eth_link_speed = ETH_SPEED_NUM_100G;
2547 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2549 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2553 return eth_link_speed;
2556 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2558 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2560 switch (hw_link_duplex) {
2561 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2562 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2564 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2566 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2567 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2570 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2574 return eth_link_duplex;
2577 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2580 struct bnxt_link_info *link_info = &bp->link_info;
2582 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2585 "Get link config failed with rc %d\n", rc);
2588 if (link_info->link_speed)
2590 bnxt_parse_hw_link_speed(link_info->link_speed);
2592 link->link_speed = ETH_SPEED_NUM_NONE;
2593 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2594 link->link_status = link_info->link_up;
2595 link->link_autoneg = link_info->auto_mode ==
2596 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2597 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2602 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2605 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2606 struct bnxt_link_info link_req;
2607 uint16_t speed, autoneg;
2609 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2612 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2613 bp->eth_dev->data->port_id);
2617 memset(&link_req, 0, sizeof(link_req));
2618 link_req.link_up = link_up;
2622 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2623 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2624 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2625 /* Autoneg can be done only when the FW allows */
2626 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2627 bp->link_info.force_link_speed)) {
2628 link_req.phy_flags |=
2629 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2630 link_req.auto_link_speed_mask =
2631 bnxt_parse_eth_link_speed_mask(bp,
2632 dev_conf->link_speeds);
2634 if (bp->link_info.phy_type ==
2635 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2636 bp->link_info.phy_type ==
2637 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2638 bp->link_info.media_type ==
2639 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2640 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2644 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2645 /* If user wants a particular speed try that first. */
2647 link_req.link_speed = speed;
2648 else if (bp->link_info.force_link_speed)
2649 link_req.link_speed = bp->link_info.force_link_speed;
2651 link_req.link_speed = bp->link_info.auto_link_speed;
2653 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2654 link_req.auto_pause = bp->link_info.auto_pause;
2655 link_req.force_pause = bp->link_info.force_pause;
2658 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2661 "Set link config failed with rc %d\n", rc);
2669 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2671 struct hwrm_func_qcfg_input req = {0};
2672 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2676 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2677 req.fid = rte_cpu_to_le_16(0xffff);
2679 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2681 HWRM_CHECK_RESULT();
2683 /* Hard Coded.. 0xfff VLAN ID mask */
2684 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2685 flags = rte_le_to_cpu_16(resp->flags);
2686 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2687 bp->flags |= BNXT_FLAG_MULTI_HOST;
2689 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2690 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2691 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2697 switch (resp->port_partition_type) {
2698 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2699 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2700 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2702 bp->port_partition_type = resp->port_partition_type;
2705 bp->port_partition_type = 0;
2714 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2715 struct hwrm_func_qcaps_output *qcaps)
2717 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2718 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2719 sizeof(qcaps->mac_address));
2720 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2721 qcaps->max_rx_rings = fcfg->num_rx_rings;
2722 qcaps->max_tx_rings = fcfg->num_tx_rings;
2723 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2724 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2726 qcaps->first_vf_id = 0;
2727 qcaps->max_vnics = fcfg->num_vnics;
2728 qcaps->max_decap_records = 0;
2729 qcaps->max_encap_records = 0;
2730 qcaps->max_tx_wm_flows = 0;
2731 qcaps->max_tx_em_flows = 0;
2732 qcaps->max_rx_wm_flows = 0;
2733 qcaps->max_rx_em_flows = 0;
2734 qcaps->max_flow_id = 0;
2735 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2736 qcaps->max_sp_tx_rings = 0;
2737 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2740 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2742 struct hwrm_func_cfg_input req = {0};
2743 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2747 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2748 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2749 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2750 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2751 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2752 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2753 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2754 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2755 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2757 if (BNXT_HAS_RING_GRPS(bp)) {
2758 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2759 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2760 } else if (BNXT_HAS_NQ(bp)) {
2761 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2762 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2765 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2766 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2767 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2768 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2770 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2771 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2772 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2773 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2774 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2775 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2776 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2777 req.fid = rte_cpu_to_le_16(0xffff);
2778 req.enables = rte_cpu_to_le_32(enables);
2780 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2782 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2784 HWRM_CHECK_RESULT();
2790 static void populate_vf_func_cfg_req(struct bnxt *bp,
2791 struct hwrm_func_cfg_input *req,
2794 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2795 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2796 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2797 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2798 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2799 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2800 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2801 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2802 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2803 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2805 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2806 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2808 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2809 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2811 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2813 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2814 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2816 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2817 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2818 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2819 /* TODO: For now, do not support VMDq/RFS on VFs. */
2820 req->num_vnics = rte_cpu_to_le_16(1);
2821 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2825 static void add_random_mac_if_needed(struct bnxt *bp,
2826 struct hwrm_func_cfg_input *cfg_req,
2829 struct rte_ether_addr mac;
2831 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2834 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2836 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2837 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2838 bp->pf.vf_info[vf].random_mac = true;
2840 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2841 RTE_ETHER_ADDR_LEN);
2845 static void reserve_resources_from_vf(struct bnxt *bp,
2846 struct hwrm_func_cfg_input *cfg_req,
2849 struct hwrm_func_qcaps_input req = {0};
2850 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2853 /* Get the actual allocated values now */
2854 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2855 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2856 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2859 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2860 copy_func_cfg_to_qcaps(cfg_req, resp);
2861 } else if (resp->error_code) {
2862 rc = rte_le_to_cpu_16(resp->error_code);
2863 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2864 copy_func_cfg_to_qcaps(cfg_req, resp);
2867 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2868 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2869 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2870 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2871 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2872 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2874 * TODO: While not supporting VMDq with VFs, max_vnics is always
2875 * forced to 1 in this case
2877 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2878 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2883 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2885 struct hwrm_func_qcfg_input req = {0};
2886 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2889 /* Check for zero MAC address */
2890 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2891 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2892 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2894 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2896 } else if (resp->error_code) {
2897 rc = rte_le_to_cpu_16(resp->error_code);
2898 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2901 rc = rte_le_to_cpu_16(resp->vlan);
2908 static int update_pf_resource_max(struct bnxt *bp)
2910 struct hwrm_func_qcfg_input req = {0};
2911 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2914 /* And copy the allocated numbers into the pf struct */
2915 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2916 req.fid = rte_cpu_to_le_16(0xffff);
2917 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2918 HWRM_CHECK_RESULT();
2920 /* Only TX ring value reflects actual allocation? TODO */
2921 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2922 bp->pf.evb_mode = resp->evb_mode;
2929 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2934 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2938 rc = bnxt_hwrm_func_qcaps(bp);
2942 bp->pf.func_cfg_flags &=
2943 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2944 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2945 bp->pf.func_cfg_flags |=
2946 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2947 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2948 rc = __bnxt_hwrm_func_qcaps(bp);
2952 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2954 struct hwrm_func_cfg_input req = {0};
2955 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2962 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2966 rc = bnxt_hwrm_func_qcaps(bp);
2971 bp->pf.active_vfs = num_vfs;
2974 * First, configure the PF to only use one TX ring. This ensures that
2975 * there are enough rings for all VFs.
2977 * If we don't do this, when we call func_alloc() later, we will lock
2978 * extra rings to the PF that won't be available during func_cfg() of
2981 * This has been fixed with firmware versions above 20.6.54
2983 bp->pf.func_cfg_flags &=
2984 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2985 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2986 bp->pf.func_cfg_flags |=
2987 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2988 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2993 * Now, create and register a buffer to hold forwarded VF requests
2995 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2996 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2997 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2998 if (bp->pf.vf_req_buf == NULL) {
3002 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3003 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3004 for (i = 0; i < num_vfs; i++)
3005 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3006 (i * HWRM_MAX_REQ_LEN);
3008 rc = bnxt_hwrm_func_buf_rgtr(bp);
3012 populate_vf_func_cfg_req(bp, &req, num_vfs);
3014 bp->pf.active_vfs = 0;
3015 for (i = 0; i < num_vfs; i++) {
3016 add_random_mac_if_needed(bp, &req, i);
3018 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3019 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3020 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3021 rc = bnxt_hwrm_send_message(bp,
3026 /* Clear enable flag for next pass */
3027 req.enables &= ~rte_cpu_to_le_32(
3028 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3030 if (rc || resp->error_code) {
3032 "Failed to initizlie VF %d\n", i);
3034 "Not all VFs available. (%d, %d)\n",
3035 rc, resp->error_code);
3042 reserve_resources_from_vf(bp, &req, i);
3043 bp->pf.active_vfs++;
3044 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3048 * Now configure the PF to use "the rest" of the resources
3049 * We're using STD_TX_RING_MODE here though which will limit the TX
3050 * rings. This will allow QoS to function properly. Not setting this
3051 * will cause PF rings to break bandwidth settings.
3053 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3057 rc = update_pf_resource_max(bp);
3064 bnxt_hwrm_func_buf_unrgtr(bp);
3068 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3070 struct hwrm_func_cfg_input req = {0};
3071 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3074 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3076 req.fid = rte_cpu_to_le_16(0xffff);
3077 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3078 req.evb_mode = bp->pf.evb_mode;
3080 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3081 HWRM_CHECK_RESULT();
3087 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3088 uint8_t tunnel_type)
3090 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3091 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3094 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3095 req.tunnel_type = tunnel_type;
3096 req.tunnel_dst_port_val = port;
3097 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3098 HWRM_CHECK_RESULT();
3100 switch (tunnel_type) {
3101 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3102 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3103 bp->vxlan_port = port;
3105 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3106 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3107 bp->geneve_port = port;
3118 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3119 uint8_t tunnel_type)
3121 struct hwrm_tunnel_dst_port_free_input req = {0};
3122 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3125 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3127 req.tunnel_type = tunnel_type;
3128 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3129 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3131 HWRM_CHECK_RESULT();
3137 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3140 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3141 struct hwrm_func_cfg_input req = {0};
3144 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3146 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3147 req.flags = rte_cpu_to_le_32(flags);
3148 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3150 HWRM_CHECK_RESULT();
3156 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3158 uint32_t *flag = flagp;
3160 vnic->flags = *flag;
3163 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3165 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3168 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3171 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3172 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3174 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3176 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3177 req.req_buf_page_size = rte_cpu_to_le_16(
3178 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3179 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3180 req.req_buf_page_addr0 =
3181 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3182 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3184 "unable to map buffer address to physical memory\n");
3188 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3190 HWRM_CHECK_RESULT();
3196 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3199 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3200 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3202 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3204 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3206 HWRM_CHECK_RESULT();
3212 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3214 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3215 struct hwrm_func_cfg_input req = {0};
3218 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3220 req.fid = rte_cpu_to_le_16(0xffff);
3221 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3222 req.enables = rte_cpu_to_le_32(
3223 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3224 req.async_event_cr = rte_cpu_to_le_16(
3225 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3226 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3228 HWRM_CHECK_RESULT();
3234 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3236 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3237 struct hwrm_func_vf_cfg_input req = {0};
3240 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3242 req.enables = rte_cpu_to_le_32(
3243 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3244 req.async_event_cr = rte_cpu_to_le_16(
3245 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3246 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3248 HWRM_CHECK_RESULT();
3254 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3256 struct hwrm_func_cfg_input req = {0};
3257 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3258 uint16_t dflt_vlan, fid;
3259 uint32_t func_cfg_flags;
3262 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3265 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3266 fid = bp->pf.vf_info[vf].fid;
3267 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3269 fid = rte_cpu_to_le_16(0xffff);
3270 func_cfg_flags = bp->pf.func_cfg_flags;
3271 dflt_vlan = bp->vlan;
3274 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3275 req.fid = rte_cpu_to_le_16(fid);
3276 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3277 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3279 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3281 HWRM_CHECK_RESULT();
3287 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3288 uint16_t max_bw, uint16_t enables)
3290 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3291 struct hwrm_func_cfg_input req = {0};
3294 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3296 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3297 req.enables |= rte_cpu_to_le_32(enables);
3298 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3299 req.max_bw = rte_cpu_to_le_32(max_bw);
3300 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3302 HWRM_CHECK_RESULT();
3308 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3310 struct hwrm_func_cfg_input req = {0};
3311 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3314 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3316 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3317 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3318 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3319 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3321 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3323 HWRM_CHECK_RESULT();
3329 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3334 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3336 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3341 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3342 void *encaped, size_t ec_size)
3345 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3346 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3348 if (ec_size > sizeof(req.encap_request))
3351 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3353 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3354 memcpy(req.encap_request, encaped, ec_size);
3356 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3358 HWRM_CHECK_RESULT();
3364 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3365 struct rte_ether_addr *mac)
3367 struct hwrm_func_qcfg_input req = {0};
3368 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3371 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3373 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3374 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3376 HWRM_CHECK_RESULT();
3378 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3385 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3386 void *encaped, size_t ec_size)
3389 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3390 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3392 if (ec_size > sizeof(req.encap_request))
3395 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3397 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3398 memcpy(req.encap_request, encaped, ec_size);
3400 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3402 HWRM_CHECK_RESULT();
3408 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3409 struct rte_eth_stats *stats, uint8_t rx)
3412 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3413 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3415 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3417 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3419 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3421 HWRM_CHECK_RESULT();
3424 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3425 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3426 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3427 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3428 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3429 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3430 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3431 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3433 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3434 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3435 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3436 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3437 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3438 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3447 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3449 struct hwrm_port_qstats_input req = {0};
3450 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3451 struct bnxt_pf_info *pf = &bp->pf;
3454 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3456 req.port_id = rte_cpu_to_le_16(pf->port_id);
3457 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3458 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3459 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3461 HWRM_CHECK_RESULT();
3467 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3469 struct hwrm_port_clr_stats_input req = {0};
3470 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3471 struct bnxt_pf_info *pf = &bp->pf;
3474 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3475 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3476 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3479 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3481 req.port_id = rte_cpu_to_le_16(pf->port_id);
3482 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3484 HWRM_CHECK_RESULT();
3490 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3492 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3493 struct hwrm_port_led_qcaps_input req = {0};
3499 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3500 req.port_id = bp->pf.port_id;
3501 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3503 HWRM_CHECK_RESULT();
3505 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3508 bp->num_leds = resp->num_leds;
3509 memcpy(bp->leds, &resp->led0_id,
3510 sizeof(bp->leds[0]) * bp->num_leds);
3511 for (i = 0; i < bp->num_leds; i++) {
3512 struct bnxt_led_info *led = &bp->leds[i];
3514 uint16_t caps = led->led_state_caps;
3516 if (!led->led_group_id ||
3517 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3529 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3531 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3532 struct hwrm_port_led_cfg_input req = {0};
3533 struct bnxt_led_cfg *led_cfg;
3534 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3535 uint16_t duration = 0;
3538 if (!bp->num_leds || BNXT_VF(bp))
3541 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3544 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3545 duration = rte_cpu_to_le_16(500);
3547 req.port_id = bp->pf.port_id;
3548 req.num_leds = bp->num_leds;
3549 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3550 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3551 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3552 led_cfg->led_id = bp->leds[i].led_id;
3553 led_cfg->led_state = led_state;
3554 led_cfg->led_blink_on = duration;
3555 led_cfg->led_blink_off = duration;
3556 led_cfg->led_group_id = bp->leds[i].led_group_id;
3559 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3561 HWRM_CHECK_RESULT();
3567 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3571 struct hwrm_nvm_get_dir_info_input req = {0};
3572 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3574 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3576 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3578 HWRM_CHECK_RESULT();
3582 *entries = rte_le_to_cpu_32(resp->entries);
3583 *length = rte_le_to_cpu_32(resp->entry_length);
3588 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3591 uint32_t dir_entries;
3592 uint32_t entry_length;
3595 rte_iova_t dma_handle;
3596 struct hwrm_nvm_get_dir_entries_input req = {0};
3597 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3599 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3603 *data++ = dir_entries;
3604 *data++ = entry_length;
3606 memset(data, 0xff, len);
3608 buflen = dir_entries * entry_length;
3609 buf = rte_malloc("nvm_dir", buflen, 0);
3610 rte_mem_lock_page(buf);
3613 dma_handle = rte_mem_virt2iova(buf);
3614 if (dma_handle == RTE_BAD_IOVA) {
3616 "unable to map response address to physical memory\n");
3619 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3620 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3621 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3624 memcpy(data, buf, len > buflen ? buflen : len);
3627 HWRM_CHECK_RESULT();
3633 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3634 uint32_t offset, uint32_t length,
3639 rte_iova_t dma_handle;
3640 struct hwrm_nvm_read_input req = {0};
3641 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3643 buf = rte_malloc("nvm_item", length, 0);
3644 rte_mem_lock_page(buf);
3648 dma_handle = rte_mem_virt2iova(buf);
3649 if (dma_handle == RTE_BAD_IOVA) {
3651 "unable to map response address to physical memory\n");
3654 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3655 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3656 req.dir_idx = rte_cpu_to_le_16(index);
3657 req.offset = rte_cpu_to_le_32(offset);
3658 req.len = rte_cpu_to_le_32(length);
3659 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3661 memcpy(data, buf, length);
3664 HWRM_CHECK_RESULT();
3670 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3673 struct hwrm_nvm_erase_dir_entry_input req = {0};
3674 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3676 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3677 req.dir_idx = rte_cpu_to_le_16(index);
3678 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3679 HWRM_CHECK_RESULT();
3686 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3687 uint16_t dir_ordinal, uint16_t dir_ext,
3688 uint16_t dir_attr, const uint8_t *data,
3692 struct hwrm_nvm_write_input req = {0};
3693 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3694 rte_iova_t dma_handle;
3697 buf = rte_malloc("nvm_write", data_len, 0);
3698 rte_mem_lock_page(buf);
3702 dma_handle = rte_mem_virt2iova(buf);
3703 if (dma_handle == RTE_BAD_IOVA) {
3705 "unable to map response address to physical memory\n");
3708 memcpy(buf, data, data_len);
3710 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3712 req.dir_type = rte_cpu_to_le_16(dir_type);
3713 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3714 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3715 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3716 req.dir_data_length = rte_cpu_to_le_32(data_len);
3717 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3719 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3722 HWRM_CHECK_RESULT();
3729 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3731 uint32_t *count = cbdata;
3733 *count = *count + 1;
3736 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3737 struct bnxt_vnic_info *vnic __rte_unused)
3742 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3746 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3747 &count, bnxt_vnic_count_hwrm_stub);
3752 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3755 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3756 struct hwrm_func_vf_vnic_ids_query_output *resp =
3757 bp->hwrm_cmd_resp_addr;
3760 /* First query all VNIC ids */
3761 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3763 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3764 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3765 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3767 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3770 "unable to map VNIC ID table address to physical memory\n");
3773 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3776 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3778 } else if (resp->error_code) {
3779 rc = rte_le_to_cpu_16(resp->error_code);
3781 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3784 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3792 * This function queries the VNIC IDs for a specified VF. It then calls
3793 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3794 * Then it calls the hwrm_cb function to program this new vnic configuration.
3796 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3797 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3798 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3800 struct bnxt_vnic_info vnic;
3802 int i, num_vnic_ids;
3807 /* First query all VNIC ids */
3808 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3809 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3810 RTE_CACHE_LINE_SIZE);
3811 if (vnic_ids == NULL) {
3815 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3816 rte_mem_lock_page(((char *)vnic_ids) + sz);
3818 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3820 if (num_vnic_ids < 0)
3821 return num_vnic_ids;
3823 /* Retrieve VNIC, update bd_stall then update */
3825 for (i = 0; i < num_vnic_ids; i++) {
3826 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3827 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3828 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3831 if (vnic.mru <= 4) /* Indicates unallocated */
3834 vnic_cb(&vnic, cbdata);
3836 rc = hwrm_cb(bp, &vnic);
3846 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3849 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3850 struct hwrm_func_cfg_input req = {0};
3853 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3855 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3856 req.enables |= rte_cpu_to_le_32(
3857 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3858 req.vlan_antispoof_mode = on ?
3859 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3860 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3861 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3863 HWRM_CHECK_RESULT();
3869 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3871 struct bnxt_vnic_info vnic;
3874 int num_vnic_ids, i;
3878 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3879 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3880 RTE_CACHE_LINE_SIZE);
3881 if (vnic_ids == NULL) {
3886 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3887 rte_mem_lock_page(((char *)vnic_ids) + sz);
3889 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3895 * Loop through to find the default VNIC ID.
3896 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3897 * by sending the hwrm_func_qcfg command to the firmware.
3899 for (i = 0; i < num_vnic_ids; i++) {
3900 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3901 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3902 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3903 bp->pf.first_vf_id + vf);
3906 if (vnic.func_default) {
3908 return vnic.fw_vnic_id;
3911 /* Could not find a default VNIC. */
3912 PMD_DRV_LOG(ERR, "No default VNIC\n");
3918 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3920 struct bnxt_filter_info *filter)
3923 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3924 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3925 uint32_t enables = 0;
3927 if (filter->fw_em_filter_id != UINT64_MAX)
3928 bnxt_hwrm_clear_em_filter(bp, filter);
3930 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3932 req.flags = rte_cpu_to_le_32(filter->flags);
3934 enables = filter->enables |
3935 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3936 req.dst_id = rte_cpu_to_le_16(dst_id);
3938 if (filter->ip_addr_type) {
3939 req.ip_addr_type = filter->ip_addr_type;
3940 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3943 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3944 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3946 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3947 memcpy(req.src_macaddr, filter->src_macaddr,
3948 RTE_ETHER_ADDR_LEN);
3950 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3951 memcpy(req.dst_macaddr, filter->dst_macaddr,
3952 RTE_ETHER_ADDR_LEN);
3954 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3955 req.ovlan_vid = filter->l2_ovlan;
3957 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3958 req.ivlan_vid = filter->l2_ivlan;
3960 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3961 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3963 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3964 req.ip_protocol = filter->ip_protocol;
3966 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3967 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3969 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3970 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3972 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3973 req.src_port = rte_cpu_to_be_16(filter->src_port);
3975 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3976 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3978 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3979 req.mirror_vnic_id = filter->mirror_vnic_id;
3981 req.enables = rte_cpu_to_le_32(enables);
3983 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3985 HWRM_CHECK_RESULT();
3987 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3993 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3996 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3997 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3999 if (filter->fw_em_filter_id == UINT64_MAX)
4002 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4003 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4005 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4007 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4009 HWRM_CHECK_RESULT();
4012 filter->fw_em_filter_id = UINT64_MAX;
4013 filter->fw_l2_filter_id = UINT64_MAX;
4018 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4020 struct bnxt_filter_info *filter)
4023 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4024 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4025 bp->hwrm_cmd_resp_addr;
4026 uint32_t enables = 0;
4028 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4029 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4031 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4033 req.flags = rte_cpu_to_le_32(filter->flags);
4035 enables = filter->enables |
4036 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4037 req.dst_id = rte_cpu_to_le_16(dst_id);
4040 if (filter->ip_addr_type) {
4041 req.ip_addr_type = filter->ip_addr_type;
4043 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4046 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4047 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4049 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4050 memcpy(req.src_macaddr, filter->src_macaddr,
4051 RTE_ETHER_ADDR_LEN);
4053 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4054 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4055 //RTE_ETHER_ADDR_LEN);
4057 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4058 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4060 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4061 req.ip_protocol = filter->ip_protocol;
4063 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4064 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4066 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4067 req.src_ipaddr_mask[0] =
4068 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4070 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4071 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4073 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4074 req.dst_ipaddr_mask[0] =
4075 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4077 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4078 req.src_port = rte_cpu_to_le_16(filter->src_port);
4080 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4081 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4083 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4084 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4086 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4087 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4089 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4090 req.mirror_vnic_id = filter->mirror_vnic_id;
4092 req.enables = rte_cpu_to_le_32(enables);
4094 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4096 HWRM_CHECK_RESULT();
4098 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4104 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4105 struct bnxt_filter_info *filter)
4108 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4109 struct hwrm_cfa_ntuple_filter_free_output *resp =
4110 bp->hwrm_cmd_resp_addr;
4112 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4115 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4117 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4119 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4121 HWRM_CHECK_RESULT();
4124 filter->fw_ntuple_filter_id = UINT64_MAX;
4130 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4132 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4133 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4134 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4135 int nr_ctxs = bp->max_ring_grps;
4136 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4137 uint16_t *ring_tbl = vnic->rss_table;
4138 int max_rings = bp->rx_nr_rings;
4142 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4144 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4145 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4146 req.hash_mode_flags = vnic->hash_mode;
4148 req.ring_grp_tbl_addr =
4149 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4150 req.hash_key_tbl_addr =
4151 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4153 for (i = 0, k = 0; i < nr_ctxs; i++) {
4154 struct bnxt_rx_ring_info *rxr;
4155 struct bnxt_cp_ring_info *cpr;
4157 req.ring_table_pair_index = i;
4158 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4160 for (j = 0; j < 64; j++) {
4163 /* Find next active ring. */
4164 for (cnt = 0; cnt < max_rings; cnt++) {
4165 if (rx_queue_state[k] !=
4166 RTE_ETH_QUEUE_STATE_STOPPED)
4168 if (++k == max_rings)
4172 /* Return if no rings are active. */
4173 if (cnt == max_rings)
4176 /* Add rx/cp ring pair to RSS table. */
4177 rxr = rxqs[k]->rx_ring;
4178 cpr = rxqs[k]->cp_ring;
4180 ring_id = rxr->rx_ring_struct->fw_ring_id;
4181 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4182 ring_id = cpr->cp_ring_struct->fw_ring_id;
4183 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4185 if (++k == max_rings)
4188 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4191 HWRM_CHECK_RESULT();
4201 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4203 unsigned int rss_idx, fw_idx, i;
4205 if (!(vnic->rss_table && vnic->hash_type))
4208 if (BNXT_CHIP_THOR(bp))
4209 return bnxt_vnic_rss_configure_thor(bp, vnic);
4212 * Fill the RSS hash & redirection table with
4213 * ring group ids for all VNICs
4215 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4216 rss_idx++, fw_idx++) {
4217 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4218 fw_idx %= bp->rx_cp_nr_rings;
4219 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4223 if (i == bp->rx_cp_nr_rings)
4225 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4227 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4230 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4231 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4235 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4237 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4238 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4240 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4241 req->num_cmpl_dma_aggr_during_int =
4242 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4244 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4246 /* min timer set to 1/2 of interrupt timer */
4247 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4249 /* buf timer set to 1/4 of interrupt timer */
4250 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4252 req->cmpl_aggr_dma_tmr_during_int =
4253 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4255 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4256 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4257 req->flags = rte_cpu_to_le_16(flags);
4260 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4261 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4263 struct hwrm_ring_aggint_qcaps_input req = {0};
4264 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4269 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4270 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4274 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4275 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4277 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4278 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4279 agg_req->flags = rte_cpu_to_le_16(flags);
4281 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4282 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4283 agg_req->enables = rte_cpu_to_le_32(enables);
4286 HWRM_CHECK_RESULT();
4291 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4292 struct bnxt_coal *coal, uint16_t ring_id)
4294 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4295 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4296 bp->hwrm_cmd_resp_addr;
4299 /* Set ring coalesce parameters only for 100G NICs */
4300 if (BNXT_CHIP_THOR(bp)) {
4301 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4303 } else if (bnxt_stratus_device(bp)) {
4304 bnxt_hwrm_set_coal_params(coal, &req);
4309 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4310 req.ring_id = rte_cpu_to_le_16(ring_id);
4311 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4312 HWRM_CHECK_RESULT();
4317 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4318 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4320 struct hwrm_func_backing_store_qcaps_input req = {0};
4321 struct hwrm_func_backing_store_qcaps_output *resp =
4322 bp->hwrm_cmd_resp_addr;
4325 if (!BNXT_CHIP_THOR(bp) ||
4326 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4331 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4332 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4333 HWRM_CHECK_RESULT_SILENT();
4336 struct bnxt_ctx_pg_info *ctx_pg;
4337 struct bnxt_ctx_mem_info *ctx;
4338 int total_alloc_len;
4341 total_alloc_len = sizeof(*ctx);
4342 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4343 RTE_CACHE_LINE_SIZE);
4348 memset(ctx, 0, total_alloc_len);
4350 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4351 sizeof(*ctx_pg) * BNXT_MAX_Q,
4352 RTE_CACHE_LINE_SIZE);
4357 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4358 ctx->tqm_mem[i] = ctx_pg;
4361 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4362 ctx->qp_min_qp1_entries =
4363 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4364 ctx->qp_max_l2_entries =
4365 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4366 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4367 ctx->srq_max_l2_entries =
4368 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4369 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4370 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4371 ctx->cq_max_l2_entries =
4372 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4373 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4374 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4375 ctx->vnic_max_vnic_entries =
4376 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4377 ctx->vnic_max_ring_table_entries =
4378 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4379 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4380 ctx->stat_max_entries =
4381 rte_le_to_cpu_32(resp->stat_max_entries);
4382 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4383 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4384 ctx->tqm_min_entries_per_ring =
4385 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4386 ctx->tqm_max_entries_per_ring =
4387 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4388 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4389 if (!ctx->tqm_entries_multiple)
4390 ctx->tqm_entries_multiple = 1;
4391 ctx->mrav_max_entries =
4392 rte_le_to_cpu_32(resp->mrav_max_entries);
4393 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4394 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4395 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4404 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4406 struct hwrm_func_backing_store_cfg_input req = {0};
4407 struct hwrm_func_backing_store_cfg_output *resp =
4408 bp->hwrm_cmd_resp_addr;
4409 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4410 struct bnxt_ctx_pg_info *ctx_pg;
4411 uint32_t *num_entries;
4420 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4421 req.enables = rte_cpu_to_le_32(enables);
4423 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4424 ctx_pg = &ctx->qp_mem;
4425 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4426 req.qp_num_qp1_entries =
4427 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4428 req.qp_num_l2_entries =
4429 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4430 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4431 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4432 &req.qpc_pg_size_qpc_lvl,
4436 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4437 ctx_pg = &ctx->srq_mem;
4438 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4439 req.srq_num_l2_entries =
4440 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4441 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4442 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4443 &req.srq_pg_size_srq_lvl,
4447 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4448 ctx_pg = &ctx->cq_mem;
4449 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4450 req.cq_num_l2_entries =
4451 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4452 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4453 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4454 &req.cq_pg_size_cq_lvl,
4458 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4459 ctx_pg = &ctx->vnic_mem;
4460 req.vnic_num_vnic_entries =
4461 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4462 req.vnic_num_ring_table_entries =
4463 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4464 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4465 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4466 &req.vnic_pg_size_vnic_lvl,
4467 &req.vnic_page_dir);
4470 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4471 ctx_pg = &ctx->stat_mem;
4472 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4473 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4474 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4475 &req.stat_pg_size_stat_lvl,
4476 &req.stat_page_dir);
4479 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4480 num_entries = &req.tqm_sp_num_entries;
4481 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4482 pg_dir = &req.tqm_sp_page_dir;
4483 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4484 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4485 if (!(enables & ena))
4488 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4490 ctx_pg = ctx->tqm_mem[i];
4491 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4492 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4495 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4496 HWRM_CHECK_RESULT();
4503 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4505 struct hwrm_port_qstats_ext_input req = {0};
4506 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4507 struct bnxt_pf_info *pf = &bp->pf;
4510 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4511 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4514 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4516 req.port_id = rte_cpu_to_le_16(pf->port_id);
4517 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4518 req.tx_stat_host_addr =
4519 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4521 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4523 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4524 req.rx_stat_host_addr =
4525 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4527 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4529 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4532 bp->fw_rx_port_stats_ext_size = 0;
4533 bp->fw_tx_port_stats_ext_size = 0;
4535 bp->fw_rx_port_stats_ext_size =
4536 rte_le_to_cpu_16(resp->rx_stat_size);
4537 bp->fw_tx_port_stats_ext_size =
4538 rte_le_to_cpu_16(resp->tx_stat_size);
4541 HWRM_CHECK_RESULT();
4548 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4550 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4551 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4552 bp->hwrm_cmd_resp_addr;
4555 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_KONG(bp));
4556 req.tunnel_type = type;
4557 req.dest_fid = bp->fw_fid;
4558 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4559 HWRM_CHECK_RESULT();
4567 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4569 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4570 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4571 bp->hwrm_cmd_resp_addr;
4574 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_KONG(bp));
4575 req.tunnel_type = type;
4576 req.dest_fid = bp->fw_fid;
4577 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4578 HWRM_CHECK_RESULT();
4585 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4587 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4588 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4589 bp->hwrm_cmd_resp_addr;
4592 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_KONG(bp));
4593 req.src_fid = bp->fw_fid;
4594 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4595 HWRM_CHECK_RESULT();
4598 *type = resp->tunnel_mask;
4605 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4608 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4609 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4610 bp->hwrm_cmd_resp_addr;
4613 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_KONG(bp));
4614 req.src_fid = bp->fw_fid;
4615 req.tunnel_type = tun_type;
4616 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4617 HWRM_CHECK_RESULT();
4620 *dst_fid = resp->dest_fid;
4622 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4629 int bnxt_hwrm_set_mac(struct bnxt *bp)
4631 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4632 struct hwrm_func_vf_cfg_input req = {0};
4638 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4641 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4642 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4644 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4646 HWRM_CHECK_RESULT();
4648 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);