1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
30 #define HWRM_VERSION_1_10_2_13 0x10a020d
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(int) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages == 0)
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
78 static struct bnxt_cp_ring_info*
79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
81 struct bnxt_cp_ring_info *cp_ring = NULL;
85 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
86 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
88 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
89 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
91 if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
92 rte_cpu_to_le_16(rid)) {
97 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
98 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
99 struct bnxt_tx_queue *txq = bp->tx_queues[i];
101 if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
102 rte_cpu_to_le_16(rid)) {
113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
114 * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
115 * before timeout, we force the done bit for the cleanup to proceed.
116 * Also if cpr is null, do nothing.. The HWRM command is not for a
117 * Tx/Rx/AGG ring cleanup.
120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
121 bool tx, bool rx, bool timeout)
127 done = bnxt_flush_tx_cmp(cpr);
130 done = bnxt_flush_rx_cmp(cpr);
133 PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
136 /* We are about to timeout and still haven't seen the
137 * HWRM done for the Ring free. Force the cleanup.
139 if (!done && timeout) {
141 PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
145 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
146 * Otherwise the cpr would have been valid. So do nothing.
155 * HWRM Functions (sent to HWRM)
156 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
157 * HWRM command times out, or a negative error code if the HWRM
158 * command was failed by the FW.
161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
162 uint32_t msg_len, bool use_kong_mb)
165 struct input *req = msg;
166 struct output *resp = bp->hwrm_cmd_resp_addr;
167 uint32_t *data = msg;
170 uint16_t max_req_len = bp->max_req_len;
171 struct hwrm_short_input short_input = { 0 };
172 uint16_t bar_offset = use_kong_mb ?
173 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
174 uint16_t mb_trigger_offset = use_kong_mb ?
175 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
176 struct bnxt_cp_ring_info *cpr = NULL;
181 /* Do not send HWRM commands to firmware in error state */
182 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
185 timeout = bp->hwrm_cmd_timeout;
187 /* Update the message length for backing store config for new FW. */
188 if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
189 rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
190 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
192 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
193 msg_len > bp->max_req_len) {
194 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
196 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
197 memcpy(short_cmd_req, req, msg_len);
199 short_input.req_type = rte_cpu_to_le_16(req->req_type);
200 short_input.signature = rte_cpu_to_le_16(
201 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
202 short_input.size = rte_cpu_to_le_16(msg_len);
203 short_input.req_addr =
204 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
206 data = (uint32_t *)&short_input;
207 msg_len = sizeof(short_input);
209 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
212 /* Write request msg to hwrm channel */
213 for (i = 0; i < msg_len; i += 4) {
214 bar = (uint8_t *)bp->bar0 + bar_offset + i;
215 rte_write32(*data, bar);
219 /* Zero the rest of the request space */
220 for (; i < max_req_len; i += 4) {
221 bar = (uint8_t *)bp->bar0 + bar_offset + i;
225 /* Ring channel doorbell */
226 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
229 * Make sure the channel doorbell ring command complete before
230 * reading the response to avoid getting stale or invalid
235 /* Check ring flush is done.
236 * This is valid only for Tx and Rx rings (including AGG rings).
237 * The Tx and Rx rings should be freed once the HW confirms all
238 * the internal buffers and BDs associated with the rings are
239 * consumed and the corresponding DMA is handled.
241 if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
242 /* Check if the TxCQ matches. If that fails check if RxCQ
243 * matches. And if neither match, is_rx = false, is_tx = false.
245 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
246 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
248 /* Not a TxCQ. Check if the RxCQ matches. */
250 bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
251 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
259 /* Poll for the valid bit */
260 for (i = 0; i < timeout; i++) {
263 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
265 /* Sanity check on the resp->resp_len */
267 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
268 /* Last byte of resp contains the valid key */
269 valid = (uint8_t *)resp + resp->resp_len - 1;
270 if (*valid == HWRM_RESP_VALID_KEY && done)
277 /* Suppress VER_GET timeout messages during reset recovery */
278 if (bp->flags & BNXT_FLAG_FW_RESET &&
279 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
283 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
284 req->req_type, req->seq_id);
291 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
292 * spinlock, and does initial processing.
294 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
295 * releases the spinlock only if it returns. If the regular int return codes
296 * are not used by the function, HWRM_CHECK_RESULT() should not be used
297 * directly, rather it should be copied and modified to suit the function.
299 * HWRM_UNLOCK() must be called after all response processing is completed.
301 #define HWRM_PREP(req, type, kong) do { \
302 rte_spinlock_lock(&bp->hwrm_lock); \
303 if (bp->hwrm_cmd_resp_addr == NULL) { \
304 rte_spinlock_unlock(&bp->hwrm_lock); \
307 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
308 (req)->req_type = rte_cpu_to_le_16(type); \
309 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
310 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
311 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
312 (req)->target_id = rte_cpu_to_le_16(0xffff); \
313 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
316 #define HWRM_CHECK_RESULT_SILENT() do {\
318 rte_spinlock_unlock(&bp->hwrm_lock); \
321 if (resp->error_code) { \
322 rc = rte_le_to_cpu_16(resp->error_code); \
323 rte_spinlock_unlock(&bp->hwrm_lock); \
328 #define HWRM_CHECK_RESULT() do {\
330 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
331 rte_spinlock_unlock(&bp->hwrm_lock); \
332 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
334 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
336 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
338 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
340 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
346 if (resp->error_code) { \
347 rc = rte_le_to_cpu_16(resp->error_code); \
348 if (resp->resp_len >= 16) { \
349 struct hwrm_err_output *tmp_hwrm_err_op = \
352 "error %d:%d:%08x:%04x\n", \
353 rc, tmp_hwrm_err_op->cmd_err, \
355 tmp_hwrm_err_op->opaque_0), \
357 tmp_hwrm_err_op->opaque_1)); \
359 PMD_DRV_LOG(ERR, "error %d\n", rc); \
361 rte_spinlock_unlock(&bp->hwrm_lock); \
362 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
364 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
366 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
368 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
370 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
378 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
389 bool mailbox = BNXT_USE_CHIMP_MB;
390 struct input *req = msg;
391 struct output *resp = bp->hwrm_cmd_resp_addr;
394 mailbox = BNXT_USE_KONG(bp);
396 HWRM_PREP(req, msg_type, mailbox);
398 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
403 memcpy(resp_msg, resp, resp_len);
410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
414 uint32_t *tf_response_code,
418 uint32_t response_len)
421 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
422 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
423 bool mailbox = BNXT_USE_CHIMP_MB;
425 if (msg_len > sizeof(req.tf_req))
429 mailbox = BNXT_USE_KONG(bp);
431 HWRM_PREP(&req, HWRM_TF, mailbox);
432 /* Build request using the user supplied request payload.
433 * TLV request size is checked at build time against HWRM
434 * request max size, thus no checking required.
436 req.tf_type = tf_type;
437 req.tf_subtype = tf_subtype;
438 memcpy(req.tf_req, msg, msg_len);
440 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
443 /* Copy the resp to user provided response buffer */
444 if (response != NULL)
445 /* Post process response data. We need to copy only
446 * the 'payload' as the HWRM data structure really is
447 * HWRM header + msg header + payload and the TFLIB
448 * only provided a payload place holder.
450 if (response_len != 0) {
456 /* Extract the internal tflib response code */
457 *tf_response_code = resp->tf_resp_code;
463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
466 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
467 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
469 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
470 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
473 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
482 struct bnxt_vnic_info *vnic,
484 struct bnxt_vlan_table_entry *vlan_table)
487 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
488 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
491 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
494 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
495 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
497 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
498 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
499 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
500 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
502 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
503 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
505 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
506 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
507 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
508 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
509 req.num_mc_entries = rte_cpu_to_le_32(bp->nb_mc_addr);
510 req.mc_tbl_addr = rte_cpu_to_le_64(bp->mc_list_dma_addr);
513 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
514 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
515 req.vlan_tag_tbl_addr =
516 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
517 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
519 req.mask = rte_cpu_to_le_32(mask);
521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
531 struct bnxt_vlan_antispoof_table_entry *vlan_table)
534 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
535 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
536 bp->hwrm_cmd_resp_addr;
539 * Older HWRM versions did not support this command, and the set_rx_mask
540 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
541 * removed from set_rx_mask call, and this command was added.
543 * This command is also present from 1.7.8.11 and higher,
546 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
547 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
548 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
553 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
554 req.fid = rte_cpu_to_le_16(fid);
556 req.vlan_tag_mask_tbl_addr =
557 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
558 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
569 struct bnxt_filter_info *filter)
572 struct bnxt_filter_info *l2_filter = filter;
573 struct bnxt_vnic_info *vnic = NULL;
574 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
575 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
577 if (filter->fw_l2_filter_id == UINT64_MAX)
580 if (filter->matching_l2_fltr_ptr)
581 l2_filter = filter->matching_l2_fltr_ptr;
583 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
584 filter, l2_filter, l2_filter->l2_ref_cnt);
586 if (l2_filter->l2_ref_cnt == 0)
589 if (l2_filter->l2_ref_cnt > 0)
590 l2_filter->l2_ref_cnt--;
592 if (l2_filter->l2_ref_cnt > 0)
595 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
597 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
599 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
604 filter->fw_l2_filter_id = UINT64_MAX;
605 if (l2_filter->l2_ref_cnt == 0) {
606 vnic = l2_filter->vnic;
608 STAILQ_REMOVE(&vnic->filter, l2_filter,
609 bnxt_filter_info, next);
610 bnxt_free_filter(bp, l2_filter);
617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
619 struct bnxt_filter_info *filter)
622 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
623 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
624 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
625 const struct rte_eth_vmdq_rx_conf *conf =
626 &dev_conf->rx_adv_conf.vmdq_rx_conf;
627 uint32_t enables = 0;
628 uint16_t j = dst_id - 1;
630 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
631 if ((dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) &&
632 conf->pool_map[j].pools & (1UL << j)) {
634 "Add vlan %u to vmdq pool %u\n",
635 conf->pool_map[j].vlan_id, j);
637 filter->l2_ivlan = conf->pool_map[j].vlan_id;
639 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
640 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
643 if (filter->fw_l2_filter_id != UINT64_MAX)
644 bnxt_hwrm_clear_l2_filter(bp, filter);
646 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
648 /* PMD does not support XDP and RoCE */
649 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
650 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
651 req.flags = rte_cpu_to_le_32(filter->flags);
653 enables = filter->enables |
654 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
655 req.dst_id = rte_cpu_to_le_16(dst_id);
658 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
659 memcpy(req.l2_addr, filter->l2_addr,
662 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
663 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
666 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
667 req.l2_ovlan = filter->l2_ovlan;
669 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
670 req.l2_ivlan = filter->l2_ivlan;
672 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
673 req.l2_ovlan_mask = filter->l2_ovlan_mask;
675 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
676 req.l2_ivlan_mask = filter->l2_ivlan_mask;
677 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
678 req.src_id = rte_cpu_to_le_32(filter->src_id);
679 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
680 req.src_type = filter->src_type;
681 if (filter->pri_hint) {
682 req.pri_hint = filter->pri_hint;
683 req.l2_filter_id_hint =
684 rte_cpu_to_le_64(filter->l2_filter_id_hint);
687 req.enables = rte_cpu_to_le_32(enables);
689 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
693 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
694 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
697 filter->l2_ref_cnt++;
702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
704 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
705 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
712 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
715 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
718 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
719 if (ptp->tx_tstamp_en)
720 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
723 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
724 req.flags = rte_cpu_to_le_32(flags);
725 req.enables = rte_cpu_to_le_32
726 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
727 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
729 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
738 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
739 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
740 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
745 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
747 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
749 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
753 if (BNXT_CHIP_P5(bp)) {
754 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
757 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
761 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
762 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
764 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
768 if (!BNXT_CHIP_P5(bp)) {
769 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
770 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
771 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
772 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
773 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
774 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
775 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
776 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
777 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
778 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
779 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
780 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
781 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
782 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
783 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
784 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
785 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
786 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
795 void bnxt_free_vf_info(struct bnxt *bp)
802 if (bp->pf->vf_info == NULL)
805 for (i = 0; i < bp->pf->max_vfs; i++) {
806 rte_free(bp->pf->vf_info[i].vlan_table);
807 bp->pf->vf_info[i].vlan_table = NULL;
808 rte_free(bp->pf->vf_info[i].vlan_as_table);
809 bp->pf->vf_info[i].vlan_as_table = NULL;
811 rte_free(bp->pf->vf_info);
812 bp->pf->vf_info = NULL;
815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
817 struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
821 bnxt_free_vf_info(bp);
823 vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
824 if (vf_info == NULL) {
825 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
829 bp->pf->max_vfs = max_vfs;
830 for (i = 0; i < max_vfs; i++) {
831 vf_info[i].fid = bp->pf->first_vf_id + i;
832 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
833 getpagesize(), getpagesize());
834 if (vf_info[i].vlan_table == NULL) {
835 PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
838 rte_mem_lock_page(vf_info[i].vlan_table);
840 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
841 getpagesize(), getpagesize());
842 if (vf_info[i].vlan_as_table == NULL) {
843 PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
846 rte_mem_lock_page(vf_info[i].vlan_as_table);
848 STAILQ_INIT(&vf_info[i].filter);
851 bp->pf->vf_info = vf_info;
855 bnxt_free_vf_info(bp);
859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
862 struct hwrm_func_qcaps_input req = {.req_type = 0 };
863 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
864 uint16_t new_max_vfs;
867 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
869 req.fid = rte_cpu_to_le_16(0xffff);
871 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
875 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
876 flags = rte_le_to_cpu_32(resp->flags);
878 bp->pf->port_id = resp->port_id;
879 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
880 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
881 new_max_vfs = bp->pdev->max_vfs;
882 if (new_max_vfs != bp->pf->max_vfs) {
883 rc = bnxt_alloc_vf_info(bp, new_max_vfs);
889 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
890 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
891 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
892 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
894 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
896 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
897 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
898 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
899 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
900 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
901 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
902 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
903 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
904 bp->max_l2_ctx += bp->max_rx_em_flows;
905 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
906 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
907 bp->max_l2_ctx, bp->max_vnics);
908 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
909 bp->max_mcast_addr = rte_le_to_cpu_32(resp->max_mcast_filters);
912 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
913 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
914 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
915 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
917 bnxt_hwrm_ptp_qcfg(bp);
921 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
922 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
924 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
925 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
926 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
929 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
930 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
932 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
933 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
935 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
936 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
938 if (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) {
939 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
940 PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n");
943 bp->tunnel_disable_flag = rte_le_to_cpu_16(resp->tunnel_disable_flag);
944 if (bp->tunnel_disable_flag)
945 PMD_DRV_LOG(DEBUG, "Tunnel parsing capability is disabled, flags : %#x\n",
946 bp->tunnel_disable_flag);
953 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
957 rc = __bnxt_hwrm_func_qcaps(bp);
961 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
962 rc = bnxt_alloc_ctx_mem(bp);
967 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
968 * But the error can be ignored. Return success.
970 rc = bnxt_hwrm_func_resc_qcaps(bp);
972 bp->flags |= BNXT_FLAG_NEW_RM;
978 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
979 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
983 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
984 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
986 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
988 req.target_id = rte_cpu_to_le_16(0xffff);
990 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
994 flags = rte_le_to_cpu_32(resp->flags);
996 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
997 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
998 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
1001 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
1002 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1004 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1005 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1007 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP) {
1008 bp->vnic_cap_flags |= BNXT_VNIC_CAP_VLAN_RX_STRIP;
1009 PMD_DRV_LOG(DEBUG, "Rx VLAN strip capability enabled\n");
1012 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1019 int bnxt_hwrm_func_reset(struct bnxt *bp)
1022 struct hwrm_func_reset_input req = {.req_type = 0 };
1023 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1025 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1027 req.enables = rte_cpu_to_le_32(0);
1029 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1031 HWRM_CHECK_RESULT();
1037 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1041 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1042 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1044 if (bp->flags & BNXT_FLAG_REGISTERED)
1047 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1048 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1049 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1050 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1052 /* PFs and trusted VFs should indicate the support of the
1053 * Master capability on non Stingray platform
1055 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1056 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1058 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1059 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1060 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1061 req.ver_maj_8b = RTE_VER_YEAR;
1062 req.ver_min_8b = RTE_VER_MONTH;
1063 req.ver_upd_8b = RTE_VER_MINOR;
1066 req.enables |= rte_cpu_to_le_32(
1067 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1068 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1069 RTE_MIN(sizeof(req.vf_req_fwd),
1070 sizeof(bp->pf->vf_req_fwd)));
1073 req.flags = rte_cpu_to_le_32(flags);
1075 req.async_event_fwd[0] |=
1076 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1077 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1078 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1079 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1080 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1081 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1082 req.async_event_fwd[0] |=
1083 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1084 req.async_event_fwd[1] |=
1085 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1086 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1088 req.async_event_fwd[1] |=
1089 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1091 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1092 req.async_event_fwd[1] |=
1093 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1095 req.async_event_fwd[2] |=
1096 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST |
1097 ASYNC_CMPL_EVENT_ID_ERROR_REPORT);
1099 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1101 HWRM_CHECK_RESULT();
1103 flags = rte_le_to_cpu_32(resp->flags);
1104 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1105 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1109 bp->flags |= BNXT_FLAG_REGISTERED;
1114 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1116 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1119 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1122 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1127 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1128 struct hwrm_func_vf_cfg_input req = {0};
1130 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1132 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1133 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1134 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1135 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1136 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1138 if (BNXT_HAS_RING_GRPS(bp)) {
1139 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1140 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1143 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1144 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1145 AGG_RING_MULTIPLIER);
1146 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1147 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1149 BNXT_NUM_ASYNC_CPR(bp));
1150 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1151 if (bp->vf_resv_strategy ==
1152 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1153 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1154 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1155 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1156 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1157 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1158 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1159 } else if (bp->vf_resv_strategy ==
1160 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1161 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1162 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1166 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1167 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1168 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1169 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1170 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1171 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1173 if (test && BNXT_HAS_RING_GRPS(bp))
1174 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1176 req.flags = rte_cpu_to_le_32(flags);
1177 req.enables |= rte_cpu_to_le_32(enables);
1179 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1182 HWRM_CHECK_RESULT_SILENT();
1184 HWRM_CHECK_RESULT();
1190 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1193 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1194 struct hwrm_func_resource_qcaps_input req = {0};
1196 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1197 req.fid = rte_cpu_to_le_16(0xffff);
1199 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1201 HWRM_CHECK_RESULT_SILENT();
1203 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1204 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1205 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1206 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1207 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1208 /* func_resource_qcaps does not return max_rx_em_flows.
1209 * So use the value provided by func_qcaps.
1211 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1212 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1213 bp->max_l2_ctx += bp->max_rx_em_flows;
1214 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1215 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1216 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1217 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1218 if (bp->vf_resv_strategy >
1219 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1220 bp->vf_resv_strategy =
1221 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1227 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1230 struct hwrm_ver_get_input req = {.req_type = 0 };
1231 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1232 uint32_t fw_version;
1233 uint16_t max_resp_len;
1234 char type[RTE_MEMZONE_NAMESIZE];
1235 uint32_t dev_caps_cfg;
1237 bp->max_req_len = HWRM_MAX_REQ_LEN;
1238 bp->hwrm_cmd_timeout = timeout;
1239 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1241 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1242 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1243 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1247 if (bp->flags & BNXT_FLAG_FW_RESET)
1248 HWRM_CHECK_RESULT_SILENT();
1250 HWRM_CHECK_RESULT();
1252 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1253 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1254 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1255 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1256 resp->hwrm_fw_rsvd_8b);
1257 bp->fw_ver = ((uint32_t)resp->hwrm_fw_maj_8b << 24) |
1258 ((uint32_t)resp->hwrm_fw_min_8b << 16) |
1259 ((uint32_t)resp->hwrm_fw_bld_8b << 8) |
1260 resp->hwrm_fw_rsvd_8b;
1261 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1262 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1264 fw_version = resp->hwrm_intf_maj_8b << 16;
1265 fw_version |= resp->hwrm_intf_min_8b << 8;
1266 fw_version |= resp->hwrm_intf_upd_8b;
1267 bp->hwrm_spec_code = fw_version;
1269 /* def_req_timeout value is in milliseconds */
1270 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1271 /* convert timeout to usec */
1272 bp->hwrm_cmd_timeout *= 1000;
1273 if (!bp->hwrm_cmd_timeout)
1274 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1276 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1277 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1282 if (bp->max_req_len > resp->max_req_win_len) {
1283 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1288 bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1290 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1291 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1292 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1293 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1295 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1296 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1298 RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1299 bp->max_resp_len = max_resp_len;
1302 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1304 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1305 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1306 bp->flags |= BNXT_FLAG_SHORT_CMD;
1309 if (((dev_caps_cfg &
1310 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1312 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1313 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1314 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1315 bp->pdev->addr.domain, bp->pdev->addr.bus,
1316 bp->pdev->addr.devid, bp->pdev->addr.function);
1318 rte_free(bp->hwrm_short_cmd_req_addr);
1320 bp->hwrm_short_cmd_req_addr =
1321 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1322 if (bp->hwrm_short_cmd_req_addr == NULL) {
1326 bp->hwrm_short_cmd_req_dma_addr =
1327 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1328 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1329 rte_free(bp->hwrm_short_cmd_req_addr);
1331 "Unable to map buffer to physical memory.\n");
1337 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1338 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1339 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1342 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1343 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1345 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1346 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1347 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1351 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1352 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1353 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1357 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
1358 PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
1359 bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
1367 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp)
1370 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1371 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1373 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1376 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1378 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1380 HWRM_CHECK_RESULT();
1383 PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1384 bp->eth_dev->data->port_id);
1389 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1392 struct hwrm_port_phy_cfg_input req = {0};
1393 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1394 uint32_t enables = 0;
1396 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1398 if (conf->link_up) {
1399 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1400 if (bp->link_info->auto_mode && conf->link_speed) {
1401 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1402 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1405 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1407 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1408 * any auto mode, even "none".
1410 if (!conf->link_speed) {
1411 /* No speeds specified. Enable AutoNeg - all speeds */
1412 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1414 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1416 if (bp->link_info->link_signal_mode) {
1418 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1419 req.force_pam4_link_speed =
1420 rte_cpu_to_le_16(conf->link_speed);
1422 req.force_link_speed =
1423 rte_cpu_to_le_16(conf->link_speed);
1426 /* AutoNeg - Advertise speeds specified. */
1427 if ((conf->auto_link_speed_mask || conf->auto_pam4_link_speed_mask) &&
1428 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1430 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1431 if (conf->auto_pam4_link_speed_mask) {
1433 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1434 req.auto_link_pam4_speed_mask =
1435 rte_cpu_to_le_16(conf->auto_pam4_link_speed_mask);
1437 if (conf->auto_link_speed_mask) {
1439 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1440 req.auto_link_speed_mask =
1441 rte_cpu_to_le_16(conf->auto_link_speed_mask);
1444 if (conf->auto_link_speed &&
1445 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1447 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1449 req.auto_duplex = conf->duplex;
1450 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1451 req.auto_pause = conf->auto_pause;
1452 req.force_pause = conf->force_pause;
1453 /* Set force_pause if there is no auto or if there is a force */
1454 if (req.auto_pause && !req.force_pause)
1455 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1457 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1459 req.enables = rte_cpu_to_le_32(enables);
1462 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1463 PMD_DRV_LOG(INFO, "Force Link Down\n");
1466 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1468 HWRM_CHECK_RESULT();
1474 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1475 struct bnxt_link_info *link_info)
1478 struct hwrm_port_phy_qcfg_input req = {0};
1479 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1481 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1483 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1485 HWRM_CHECK_RESULT();
1487 link_info->phy_link_status = resp->link;
1488 link_info->link_up =
1489 (link_info->phy_link_status ==
1490 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1491 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1492 link_info->duplex = resp->duplex_cfg;
1493 link_info->pause = resp->pause;
1494 link_info->auto_pause = resp->auto_pause;
1495 link_info->force_pause = resp->force_pause;
1496 link_info->auto_mode = resp->auto_mode;
1497 link_info->phy_type = resp->phy_type;
1498 link_info->media_type = resp->media_type;
1500 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1501 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1502 link_info->auto_link_speed_mask = rte_le_to_cpu_16(resp->auto_link_speed_mask);
1503 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1504 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1505 link_info->phy_ver[0] = resp->phy_maj;
1506 link_info->phy_ver[1] = resp->phy_min;
1507 link_info->phy_ver[2] = resp->phy_bld;
1508 link_info->link_signal_mode =
1509 resp->active_fec_signal_mode & HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK;
1510 link_info->force_pam4_link_speed =
1511 rte_le_to_cpu_16(resp->force_pam4_link_speed);
1512 link_info->support_pam4_speeds =
1513 rte_le_to_cpu_16(resp->support_pam4_speeds);
1514 link_info->auto_pam4_link_speed_mask =
1515 rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1516 link_info->module_status = resp->module_status;
1519 PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1520 link_info->link_speed, link_info->auto_mode,
1521 link_info->auto_link_speed, link_info->auto_link_speed_mask,
1522 link_info->support_speeds, link_info->force_link_speed);
1523 PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1524 link_info->link_signal_mode,
1525 link_info->auto_pam4_link_speed_mask,
1526 link_info->support_pam4_speeds,
1527 link_info->force_pam4_link_speed);
1531 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1534 struct hwrm_port_phy_qcaps_input req = {0};
1535 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1536 struct bnxt_link_info *link_info = bp->link_info;
1538 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1541 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1543 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1545 HWRM_CHECK_RESULT_SILENT();
1547 bp->port_cnt = resp->port_cnt;
1548 if (resp->supported_speeds_auto_mode)
1549 link_info->support_auto_speeds =
1550 rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1551 if (resp->supported_pam4_speeds_auto_mode)
1552 link_info->support_pam4_auto_speeds =
1553 rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1557 /* Older firmware does not have supported_auto_speeds, so assume
1558 * that all supported speeds can be autonegotiated.
1560 if (link_info->auto_link_speed_mask && !link_info->support_auto_speeds)
1561 link_info->support_auto_speeds = link_info->support_speeds;
1566 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1570 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1571 if (bp->tx_cos_queue[i].profile ==
1572 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1573 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1580 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1584 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1585 if (bp->tx_cos_queue[i].profile !=
1586 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1587 bp->tx_cos_queue[i].id !=
1588 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1589 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1595 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1598 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1599 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1600 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1604 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1606 req.flags = rte_cpu_to_le_32(dir);
1607 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1608 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1609 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1611 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1612 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1614 HWRM_CHECK_RESULT();
1616 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1617 GET_TX_QUEUE_INFO(0);
1618 GET_TX_QUEUE_INFO(1);
1619 GET_TX_QUEUE_INFO(2);
1620 GET_TX_QUEUE_INFO(3);
1621 GET_TX_QUEUE_INFO(4);
1622 GET_TX_QUEUE_INFO(5);
1623 GET_TX_QUEUE_INFO(6);
1624 GET_TX_QUEUE_INFO(7);
1626 GET_RX_QUEUE_INFO(0);
1627 GET_RX_QUEUE_INFO(1);
1628 GET_RX_QUEUE_INFO(2);
1629 GET_RX_QUEUE_INFO(3);
1630 GET_RX_QUEUE_INFO(4);
1631 GET_RX_QUEUE_INFO(5);
1632 GET_RX_QUEUE_INFO(6);
1633 GET_RX_QUEUE_INFO(7);
1638 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1641 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1642 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1646 /* iterate and find the COSq profile to use for Tx */
1647 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1648 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1649 if (bp->tx_cos_queue[i].id != 0xff)
1650 bp->tx_cosq_id[j++] =
1651 bp->tx_cos_queue[i].id;
1654 /* When CoS classification is disabled, for normal NIC
1655 * operations, ideally we should look to use LOSSY.
1656 * If not found, fallback to the first valid profile
1658 if (!bnxt_find_lossy_profile(bp))
1659 bnxt_find_first_valid_profile(bp);
1664 bp->max_tc = resp->max_configurable_queues;
1665 bp->max_lltc = resp->max_configurable_lossless_queues;
1666 if (bp->max_tc > BNXT_MAX_QUEUE)
1667 bp->max_tc = BNXT_MAX_QUEUE;
1668 bp->max_q = bp->max_tc;
1670 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1671 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1679 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1680 struct bnxt_ring *ring,
1681 uint32_t ring_type, uint32_t map_index,
1682 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1683 uint16_t tx_cosq_id)
1686 uint32_t enables = 0;
1687 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1688 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1689 struct rte_mempool *mb_pool;
1690 uint16_t rx_buf_size;
1692 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1694 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1695 req.fbo = rte_cpu_to_le_32(0);
1696 /* Association of ring index with doorbell index */
1697 req.logical_id = rte_cpu_to_le_16(map_index);
1698 req.length = rte_cpu_to_le_32(ring->ring_size);
1700 switch (ring_type) {
1701 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1702 req.ring_type = ring_type;
1703 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1704 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1705 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1706 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1708 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1710 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1711 req.ring_type = ring_type;
1712 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1713 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1714 if (BNXT_CHIP_P5(bp)) {
1715 mb_pool = bp->rx_queues[0]->mb_pool;
1716 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1717 RTE_PKTMBUF_HEADROOM;
1718 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1719 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1721 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1723 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1725 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1727 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1728 req.ring_type = ring_type;
1729 if (BNXT_HAS_NQ(bp)) {
1730 /* Association of cp ring with nq */
1731 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1733 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1735 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1737 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1738 req.ring_type = ring_type;
1739 req.page_size = BNXT_PAGE_SHFT;
1740 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1742 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1743 req.ring_type = ring_type;
1744 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1746 mb_pool = bp->rx_queues[0]->mb_pool;
1747 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1748 RTE_PKTMBUF_HEADROOM;
1749 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1750 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1752 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1753 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1754 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1755 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1758 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1763 req.enables = rte_cpu_to_le_32(enables);
1765 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1767 if (rc || resp->error_code) {
1768 if (rc == 0 && resp->error_code)
1769 rc = rte_le_to_cpu_16(resp->error_code);
1770 switch (ring_type) {
1771 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1773 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1776 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1778 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1781 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1783 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1787 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1789 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1792 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1794 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1798 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1804 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1809 int bnxt_hwrm_ring_free(struct bnxt *bp,
1810 struct bnxt_ring *ring, uint32_t ring_type,
1811 uint16_t cp_ring_id)
1814 struct hwrm_ring_free_input req = {.req_type = 0 };
1815 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1817 if (ring->fw_ring_id == INVALID_HW_RING_ID)
1820 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1822 req.ring_type = ring_type;
1823 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1824 req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1826 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1827 ring->fw_ring_id = INVALID_HW_RING_ID;
1829 if (rc || resp->error_code) {
1830 if (rc == 0 && resp->error_code)
1831 rc = rte_le_to_cpu_16(resp->error_code);
1834 switch (ring_type) {
1835 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1836 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1839 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1840 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1843 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1844 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1847 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1849 "hwrm_ring_free nq failed. rc:%d\n", rc);
1851 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1853 "hwrm_ring_free agg failed. rc:%d\n", rc);
1856 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1864 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1867 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1868 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1870 /* Don't attempt to re-create the ring group if it is already created */
1871 if (bp->grp_info[idx].fw_grp_id != INVALID_HW_RING_ID)
1874 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1876 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1877 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1878 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1879 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1881 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1883 HWRM_CHECK_RESULT();
1885 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1892 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1895 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1896 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1898 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1901 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1903 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1905 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1907 HWRM_CHECK_RESULT();
1910 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1914 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1917 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1918 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1920 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1923 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1925 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1927 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1929 HWRM_CHECK_RESULT();
1935 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1938 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1939 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1941 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE)
1944 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1946 req.update_period_ms = rte_cpu_to_le_32(0);
1948 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1950 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1952 HWRM_CHECK_RESULT();
1954 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1961 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1964 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1965 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1967 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1970 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1972 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1974 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1976 HWRM_CHECK_RESULT();
1979 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1984 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1987 struct hwrm_vnic_alloc_input req = { 0 };
1988 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1990 if (!BNXT_HAS_RING_GRPS(bp))
1991 goto skip_ring_grps;
1993 /* map ring groups to this vnic */
1994 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1995 vnic->start_grp_id, vnic->end_grp_id);
1996 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1997 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1999 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
2000 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
2001 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
2002 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
2005 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
2006 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
2008 if (vnic->func_default)
2010 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
2011 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2013 HWRM_CHECK_RESULT();
2015 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
2017 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2021 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
2022 struct bnxt_vnic_info *vnic,
2023 struct bnxt_plcmodes_cfg *pmode)
2026 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2027 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2029 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2031 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2033 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2035 HWRM_CHECK_RESULT();
2037 pmode->flags = rte_le_to_cpu_32(resp->flags);
2038 /* dflt_vnic bit doesn't exist in the _cfg command */
2039 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2040 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2041 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2042 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2049 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2050 struct bnxt_vnic_info *vnic,
2051 struct bnxt_plcmodes_cfg *pmode)
2054 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2055 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2057 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2058 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2062 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2064 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2065 req.flags = rte_cpu_to_le_32(pmode->flags);
2066 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2067 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2068 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2069 req.enables = rte_cpu_to_le_32(
2070 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2071 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2072 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2075 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2077 HWRM_CHECK_RESULT();
2083 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2086 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2087 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2088 struct bnxt_plcmodes_cfg pmodes = { 0 };
2089 uint32_t ctx_enable_flag = 0;
2090 uint32_t enables = 0;
2092 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2093 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2097 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2101 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2103 if (BNXT_CHIP_P5(bp)) {
2104 int dflt_rxq = vnic->start_grp_id;
2105 struct bnxt_rx_ring_info *rxr;
2106 struct bnxt_cp_ring_info *cpr;
2107 struct bnxt_rx_queue *rxq;
2111 * The first active receive ring is used as the VNIC
2112 * default receive ring. If there are no active receive
2113 * rings (all corresponding receive queues are stopped),
2114 * the first receive ring is used.
2116 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2117 rxq = bp->eth_dev->data->rx_queues[i];
2118 if (rxq->rx_started) {
2124 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2128 req.default_rx_ring_id =
2129 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2130 req.default_cmpl_ring_id =
2131 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2132 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2133 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2134 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2135 enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2136 req.rx_csum_v2_mode =
2137 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2142 /* Only RSS support for now TBD: COS & LB */
2143 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2144 if (vnic->lb_rule != 0xffff)
2145 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2146 if (vnic->cos_rule != 0xffff)
2147 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2148 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2149 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2150 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2152 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2153 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2154 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2157 enables |= ctx_enable_flag;
2158 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2159 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2160 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2161 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2164 req.enables = rte_cpu_to_le_32(enables);
2165 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2166 req.mru = rte_cpu_to_le_16(vnic->mru);
2167 /* Configure default VNIC only once. */
2168 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2170 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2171 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2173 if (vnic->vlan_strip)
2175 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2178 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2179 if (vnic->rss_dflt_cr)
2180 req.flags |= rte_cpu_to_le_32(
2181 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2183 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2185 HWRM_CHECK_RESULT();
2188 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2193 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2197 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2198 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2200 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2201 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2204 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2207 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2208 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2209 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2211 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2213 HWRM_CHECK_RESULT();
2215 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2216 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2217 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2218 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2219 vnic->mru = rte_le_to_cpu_16(resp->mru);
2220 vnic->func_default = rte_le_to_cpu_32(
2221 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2222 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2223 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2224 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2225 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2226 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2227 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2234 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2235 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2239 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2240 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2241 bp->hwrm_cmd_resp_addr;
2243 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2246 HWRM_CHECK_RESULT();
2248 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2249 if (!BNXT_HAS_RING_GRPS(bp))
2250 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2251 else if (ctx_idx == 0)
2252 vnic->rss_rule = ctx_id;
2260 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2261 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2264 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2265 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2266 bp->hwrm_cmd_resp_addr;
2268 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2269 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2272 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2274 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2276 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2278 HWRM_CHECK_RESULT();
2284 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2288 if (BNXT_CHIP_P5(bp)) {
2291 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2292 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2294 vnic->fw_grp_ids[j]);
2295 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2297 vnic->num_lb_ctxts = 0;
2299 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2300 vnic->rss_rule = INVALID_HW_RING_ID;
2306 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2309 struct hwrm_vnic_free_input req = {.req_type = 0 };
2310 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2312 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2313 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2317 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2319 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2321 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2323 HWRM_CHECK_RESULT();
2326 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2327 /* Configure default VNIC again if necessary. */
2328 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2329 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2335 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2339 int nr_ctxs = vnic->num_lb_ctxts;
2340 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2341 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2343 for (i = 0; i < nr_ctxs; i++) {
2344 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2346 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2347 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2348 req.hash_mode_flags = vnic->hash_mode;
2350 req.hash_key_tbl_addr =
2351 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2353 req.ring_grp_tbl_addr =
2354 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2355 i * HW_HASH_INDEX_SIZE);
2356 req.ring_table_pair_index = i;
2357 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2359 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2362 HWRM_CHECK_RESULT();
2369 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2370 struct bnxt_vnic_info *vnic)
2373 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2374 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2376 if (!vnic->rss_table)
2379 if (BNXT_CHIP_P5(bp))
2380 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2382 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2384 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2385 req.hash_mode_flags = vnic->hash_mode;
2387 req.ring_grp_tbl_addr =
2388 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2389 req.hash_key_tbl_addr =
2390 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2391 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2392 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2394 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2396 HWRM_CHECK_RESULT();
2402 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2403 struct bnxt_vnic_info *vnic)
2406 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2407 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2410 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2411 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2415 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2417 req.flags = rte_cpu_to_le_32(
2418 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2420 req.enables = rte_cpu_to_le_32(
2421 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2423 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2424 size -= RTE_PKTMBUF_HEADROOM;
2425 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2427 req.jumbo_thresh = rte_cpu_to_le_16(size);
2428 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2430 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2432 HWRM_CHECK_RESULT();
2438 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2439 struct bnxt_vnic_info *vnic, bool enable)
2442 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2443 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2445 if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2447 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2451 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2452 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2456 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2459 req.enables = rte_cpu_to_le_32(
2460 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2461 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2462 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2463 req.flags = rte_cpu_to_le_32(
2464 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2465 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2466 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2467 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2468 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2469 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2470 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2471 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2472 req.min_agg_len = rte_cpu_to_le_32(512);
2474 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2476 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2478 HWRM_CHECK_RESULT();
2484 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2486 struct hwrm_func_cfg_input req = {0};
2487 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2490 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2491 req.enables = rte_cpu_to_le_32(
2492 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2493 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2494 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2496 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2498 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2499 HWRM_CHECK_RESULT();
2502 bp->pf->vf_info[vf].random_mac = false;
2507 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2511 struct hwrm_func_qstats_input req = {.req_type = 0};
2512 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2514 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2516 req.fid = rte_cpu_to_le_16(fid);
2518 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2520 HWRM_CHECK_RESULT();
2523 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2530 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2531 struct rte_eth_stats *stats,
2532 struct hwrm_func_qstats_output *func_qstats)
2535 struct hwrm_func_qstats_input req = {.req_type = 0};
2536 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2538 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2540 req.fid = rte_cpu_to_le_16(fid);
2542 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2544 HWRM_CHECK_RESULT();
2546 memcpy(func_qstats, resp,
2547 sizeof(struct hwrm_func_qstats_output));
2552 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2553 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2554 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2555 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2556 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2557 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2559 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2560 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2561 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2562 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2563 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2564 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2566 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2567 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2568 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2576 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2579 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2580 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2582 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2584 req.fid = rte_cpu_to_le_16(fid);
2586 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2588 HWRM_CHECK_RESULT();
2594 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2599 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2600 struct bnxt_tx_queue *txq;
2601 struct bnxt_rx_queue *rxq;
2602 struct bnxt_cp_ring_info *cpr;
2604 if (i >= bp->rx_cp_nr_rings) {
2605 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2608 rxq = bp->rx_queues[i];
2612 rc = bnxt_hwrm_stat_clear(bp, cpr);
2620 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2624 struct bnxt_cp_ring_info *cpr;
2626 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2628 cpr = bp->rx_queues[i]->cp_ring;
2629 if (BNXT_HAS_RING_GRPS(bp))
2630 bp->grp_info[i].fw_stats_ctx = -1;
2633 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2638 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2639 cpr = bp->tx_queues[i]->cp_ring;
2642 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2651 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2656 if (!BNXT_HAS_RING_GRPS(bp))
2659 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2661 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2664 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2672 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2674 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2676 bnxt_hwrm_ring_free(bp, cp_ring,
2677 HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2678 INVALID_HW_RING_ID);
2679 memset(cpr->cp_desc_ring, 0,
2680 cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2681 cpr->cp_raw_cons = 0;
2684 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2686 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2688 bnxt_hwrm_ring_free(bp, cp_ring,
2689 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2690 INVALID_HW_RING_ID);
2691 memset(cpr->cp_desc_ring, 0,
2692 cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2693 cpr->cp_raw_cons = 0;
2696 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2698 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2699 struct bnxt_rx_ring_info *rxr = rxq ? rxq->rx_ring : NULL;
2700 struct bnxt_ring *ring = rxr ? rxr->rx_ring_struct : NULL;
2701 struct bnxt_cp_ring_info *cpr = rxq ? rxq->cp_ring : NULL;
2703 if (BNXT_HAS_RING_GRPS(bp))
2704 bnxt_hwrm_ring_grp_free(bp, queue_index);
2706 if (ring != NULL && cpr != NULL)
2707 bnxt_hwrm_ring_free(bp, ring,
2708 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2709 cpr->cp_ring_struct->fw_ring_id);
2710 if (BNXT_HAS_RING_GRPS(bp))
2711 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2713 /* Check agg ring struct explicitly.
2714 * bnxt_need_agg_ring() returns the current state of offload flags,
2715 * but we may have to deal with agg ring struct before the offload
2716 * flags are updated.
2718 if (!bnxt_need_agg_ring(bp->eth_dev) ||
2719 (rxr && rxr->ag_ring_struct == NULL))
2722 ring = rxr ? rxr->ag_ring_struct : NULL;
2723 if (ring != NULL && cpr != NULL) {
2724 bnxt_hwrm_ring_free(bp, ring,
2726 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2727 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2728 cpr->cp_ring_struct->fw_ring_id);
2730 if (BNXT_HAS_RING_GRPS(bp))
2731 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2735 bnxt_hwrm_stat_ctx_free(bp, cpr);
2736 bnxt_free_cp_ring(bp, cpr);
2739 if (BNXT_HAS_RING_GRPS(bp))
2740 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2743 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2746 struct hwrm_ring_reset_input req = {.req_type = 0 };
2747 struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2749 HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2751 req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2752 req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2753 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2755 HWRM_CHECK_RESULT();
2763 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2767 for (i = 0; i < bp->tx_cp_nr_rings; i++)
2768 bnxt_free_hwrm_tx_ring(bp, i);
2770 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2771 bnxt_free_hwrm_rx_ring(bp, i);
2776 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2781 if (!BNXT_HAS_RING_GRPS(bp))
2784 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2785 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2793 * HWRM utility functions
2796 void bnxt_free_hwrm_resources(struct bnxt *bp)
2798 /* Release memzone */
2799 rte_free(bp->hwrm_cmd_resp_addr);
2800 rte_free(bp->hwrm_short_cmd_req_addr);
2801 bp->hwrm_cmd_resp_addr = NULL;
2802 bp->hwrm_short_cmd_req_addr = NULL;
2803 bp->hwrm_cmd_resp_dma_addr = 0;
2804 bp->hwrm_short_cmd_req_dma_addr = 0;
2807 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2809 struct rte_pci_device *pdev = bp->pdev;
2810 char type[RTE_MEMZONE_NAMESIZE];
2812 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2813 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2814 bp->max_resp_len = BNXT_PAGE_SIZE;
2815 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2816 if (bp->hwrm_cmd_resp_addr == NULL)
2818 bp->hwrm_cmd_resp_dma_addr =
2819 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2820 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2822 "unable to map response address to physical memory\n");
2825 rte_spinlock_init(&bp->hwrm_lock);
2831 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2835 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2836 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2839 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2840 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2845 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2850 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2852 struct bnxt_filter_info *filter;
2855 STAILQ_FOREACH(filter, &vnic->filter, next) {
2856 rc = bnxt_clear_one_vnic_filter(bp, filter);
2857 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2858 bnxt_free_filter(bp, filter);
2864 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2866 struct bnxt_filter_info *filter;
2867 struct rte_flow *flow;
2870 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2871 flow = STAILQ_FIRST(&vnic->flow_list);
2872 filter = flow->filter;
2873 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2874 rc = bnxt_clear_one_vnic_filter(bp, filter);
2876 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2882 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2884 struct bnxt_filter_info *filter;
2887 STAILQ_FOREACH(filter, &vnic->filter, next) {
2888 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2889 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2891 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2892 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2895 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2904 bnxt_free_tunnel_ports(struct bnxt *bp)
2906 if (bp->vxlan_port_cnt)
2907 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2908 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2910 if (bp->geneve_port_cnt)
2911 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2912 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2915 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2919 if (bp->vnic_info == NULL)
2923 * Cleanup VNICs in reverse order, to make sure the L2 filter
2924 * from vnic0 is last to be cleaned up.
2926 for (i = bp->max_vnics - 1; i >= 0; i--) {
2927 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2929 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2932 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2934 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2936 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2938 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2940 bnxt_hwrm_vnic_free(bp, vnic);
2942 rte_free(vnic->fw_grp_ids);
2944 /* Ring resources */
2945 bnxt_free_all_hwrm_rings(bp);
2946 bnxt_free_all_hwrm_ring_grps(bp);
2947 bnxt_free_all_hwrm_stat_ctxs(bp);
2948 bnxt_free_tunnel_ports(bp);
2951 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2953 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2955 if ((conf_link_speed & RTE_ETH_LINK_SPEED_FIXED) == RTE_ETH_LINK_SPEED_AUTONEG)
2956 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2958 switch (conf_link_speed) {
2959 case RTE_ETH_LINK_SPEED_10M_HD:
2960 case RTE_ETH_LINK_SPEED_100M_HD:
2962 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2964 return hw_link_duplex;
2967 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2972 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2975 uint16_t eth_link_speed = 0;
2977 if (conf_link_speed == RTE_ETH_LINK_SPEED_AUTONEG)
2978 return RTE_ETH_LINK_SPEED_AUTONEG;
2980 switch (conf_link_speed & ~RTE_ETH_LINK_SPEED_FIXED) {
2981 case RTE_ETH_LINK_SPEED_100M:
2982 case RTE_ETH_LINK_SPEED_100M_HD:
2985 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2987 case RTE_ETH_LINK_SPEED_1G:
2989 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2991 case RTE_ETH_LINK_SPEED_2_5G:
2993 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2995 case RTE_ETH_LINK_SPEED_10G:
2997 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2999 case RTE_ETH_LINK_SPEED_20G:
3001 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3003 case RTE_ETH_LINK_SPEED_25G:
3005 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3007 case RTE_ETH_LINK_SPEED_40G:
3009 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3011 case RTE_ETH_LINK_SPEED_50G:
3012 eth_link_speed = pam4_link ?
3013 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3014 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3016 case RTE_ETH_LINK_SPEED_100G:
3017 eth_link_speed = pam4_link ?
3018 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3019 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3021 case RTE_ETH_LINK_SPEED_200G:
3023 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3027 "Unsupported link speed %d; default to AUTO\n",
3031 return eth_link_speed;
3034 #define BNXT_SUPPORTED_SPEEDS (RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_100M_HD | \
3035 RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_2_5G | \
3036 RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_20G | RTE_ETH_LINK_SPEED_25G | \
3037 RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_50G | \
3038 RTE_ETH_LINK_SPEED_100G | RTE_ETH_LINK_SPEED_200G)
3040 static int bnxt_validate_link_speed(struct bnxt *bp)
3042 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3043 uint16_t port_id = bp->eth_dev->data->port_id;
3044 uint32_t link_speed_capa;
3047 if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG)
3050 link_speed_capa = bnxt_get_speed_capabilities(bp);
3052 if (link_speed & RTE_ETH_LINK_SPEED_FIXED) {
3053 one_speed = link_speed & ~RTE_ETH_LINK_SPEED_FIXED;
3055 if (one_speed & (one_speed - 1)) {
3057 "Invalid advertised speeds (%u) for port %u\n",
3058 link_speed, port_id);
3061 if ((one_speed & link_speed_capa) != one_speed) {
3063 "Unsupported advertised speed (%u) for port %u\n",
3064 link_speed, port_id);
3068 if (!(link_speed & link_speed_capa)) {
3070 "Unsupported advertised speeds (%u) for port %u\n",
3071 link_speed, port_id);
3079 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3083 if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG) {
3084 if (bp->link_info->support_speeds)
3085 return bp->link_info->support_speeds;
3086 link_speed = BNXT_SUPPORTED_SPEEDS;
3089 if (link_speed & RTE_ETH_LINK_SPEED_100M)
3090 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3091 if (link_speed & RTE_ETH_LINK_SPEED_100M_HD)
3092 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3093 if (link_speed & RTE_ETH_LINK_SPEED_1G)
3094 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3095 if (link_speed & RTE_ETH_LINK_SPEED_2_5G)
3096 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3097 if (link_speed & RTE_ETH_LINK_SPEED_10G)
3098 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3099 if (link_speed & RTE_ETH_LINK_SPEED_20G)
3100 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3101 if (link_speed & RTE_ETH_LINK_SPEED_25G)
3102 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3103 if (link_speed & RTE_ETH_LINK_SPEED_40G)
3104 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3105 if (link_speed & RTE_ETH_LINK_SPEED_50G)
3106 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3107 if (link_speed & RTE_ETH_LINK_SPEED_100G)
3108 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3109 if (link_speed & RTE_ETH_LINK_SPEED_200G)
3110 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3114 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3116 uint32_t eth_link_speed = RTE_ETH_SPEED_NUM_NONE;
3118 switch (hw_link_speed) {
3119 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3120 eth_link_speed = RTE_ETH_SPEED_NUM_100M;
3122 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3123 eth_link_speed = RTE_ETH_SPEED_NUM_1G;
3125 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3126 eth_link_speed = RTE_ETH_SPEED_NUM_2_5G;
3128 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3129 eth_link_speed = RTE_ETH_SPEED_NUM_10G;
3131 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3132 eth_link_speed = RTE_ETH_SPEED_NUM_20G;
3134 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3135 eth_link_speed = RTE_ETH_SPEED_NUM_25G;
3137 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3138 eth_link_speed = RTE_ETH_SPEED_NUM_40G;
3140 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3141 eth_link_speed = RTE_ETH_SPEED_NUM_50G;
3143 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3144 eth_link_speed = RTE_ETH_SPEED_NUM_100G;
3146 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3147 eth_link_speed = RTE_ETH_SPEED_NUM_200G;
3149 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3151 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3155 return eth_link_speed;
3158 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3160 uint16_t eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3162 switch (hw_link_duplex) {
3163 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3164 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3166 eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3168 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3169 eth_link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
3172 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3176 return eth_link_duplex;
3179 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3182 struct bnxt_link_info *link_info = bp->link_info;
3184 rc = bnxt_hwrm_port_phy_qcaps(bp);
3186 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3188 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3190 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3194 if (link_info->link_speed)
3196 bnxt_parse_hw_link_speed(link_info->link_speed);
3198 link->link_speed = RTE_ETH_SPEED_NUM_NONE;
3199 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3200 link->link_status = link_info->link_up;
3201 link->link_autoneg = link_info->auto_mode ==
3202 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3203 RTE_ETH_LINK_FIXED : RTE_ETH_LINK_AUTONEG;
3208 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3211 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3212 struct bnxt_link_info link_req;
3213 uint16_t speed, autoneg;
3215 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3218 rc = bnxt_validate_link_speed(bp);
3222 memset(&link_req, 0, sizeof(link_req));
3223 link_req.link_up = link_up;
3227 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3228 if (BNXT_CHIP_P5(bp) &&
3229 dev_conf->link_speeds == RTE_ETH_LINK_SPEED_40G) {
3230 /* 40G is not supported as part of media auto detect.
3231 * The speed should be forced and autoneg disabled
3232 * to configure 40G speed.
3234 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3238 /* No auto speeds and no auto_pam4_link. Disable autoneg */
3239 if (bp->link_info->auto_link_speed == 0 &&
3240 bp->link_info->link_signal_mode &&
3241 bp->link_info->auto_pam4_link_speed_mask == 0)
3244 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3245 bp->link_info->link_signal_mode);
3246 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3247 /* Autoneg can be done only when the FW allows. */
3249 (bp->link_info->support_auto_speeds || bp->link_info->support_pam4_auto_speeds)) {
3250 link_req.phy_flags |=
3251 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3252 link_req.auto_link_speed_mask =
3253 bnxt_parse_eth_link_speed_mask(bp,
3254 dev_conf->link_speeds);
3255 link_req.auto_pam4_link_speed_mask =
3256 bp->link_info->auto_pam4_link_speed_mask;
3258 if (bp->link_info->phy_type ==
3259 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3260 bp->link_info->phy_type ==
3261 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3262 bp->link_info->media_type ==
3263 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3264 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3268 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3269 /* If user wants a particular speed try that first. */
3271 link_req.link_speed = speed;
3272 else if (bp->link_info->force_pam4_link_speed)
3273 link_req.link_speed =
3274 bp->link_info->force_pam4_link_speed;
3275 else if (bp->link_info->auto_pam4_link_speed_mask)
3276 link_req.link_speed =
3277 bp->link_info->auto_pam4_link_speed_mask;
3278 else if (bp->link_info->support_pam4_speeds)
3279 link_req.link_speed =
3280 bp->link_info->support_pam4_speeds;
3281 else if (bp->link_info->force_link_speed)
3282 link_req.link_speed = bp->link_info->force_link_speed;
3284 link_req.link_speed = bp->link_info->auto_link_speed;
3285 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3286 * zero. Use the auto_link_speed.
3288 if (bp->link_info->auto_link_speed != 0 &&
3289 bp->link_info->auto_pam4_link_speed_mask == 0)
3290 link_req.link_speed = bp->link_info->auto_link_speed;
3292 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3293 link_req.auto_pause = bp->link_info->auto_pause;
3294 link_req.force_pause = bp->link_info->force_pause;
3297 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3300 "Set link config failed with rc %d\n", rc);
3307 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3309 struct hwrm_func_qcfg_input req = {0};
3310 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3313 bp->func_svif = BNXT_SVIF_INVALID;
3316 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3317 req.fid = rte_cpu_to_le_16(0xffff);
3319 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3321 HWRM_CHECK_RESULT();
3323 bp->vlan = rte_le_to_cpu_16(resp->vlan) & RTE_ETH_VLAN_ID_MAX;
3325 svif_info = rte_le_to_cpu_16(resp->svif_info);
3326 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3327 bp->func_svif = svif_info &
3328 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3330 flags = rte_le_to_cpu_16(resp->flags);
3331 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3332 bp->flags |= BNXT_FLAG_MULTI_HOST;
3335 !BNXT_VF_IS_TRUSTED(bp) &&
3336 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3337 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3338 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3339 } else if (BNXT_VF(bp) &&
3340 BNXT_VF_IS_TRUSTED(bp) &&
3341 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3342 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3343 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3347 *mtu = rte_le_to_cpu_16(resp->admin_mtu);
3349 switch (resp->port_partition_type) {
3350 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3351 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3352 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3354 bp->flags |= BNXT_FLAG_NPAR_PF;
3357 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3361 bp->legacy_db_size =
3362 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3369 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3371 struct hwrm_func_qcfg_input req = {0};
3372 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3376 if (!BNXT_VF_IS_TRUSTED(bp))
3382 bp->parent->fid = BNXT_PF_FID_INVALID;
3384 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3386 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3388 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3390 HWRM_CHECK_RESULT_SILENT();
3392 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3393 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3394 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3395 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3397 flags = rte_le_to_cpu_16(resp->flags);
3398 /* check for the multi-root support */
3399 if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) {
3400 bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN;
3401 PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n");
3409 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3410 uint16_t *vnic_id, uint16_t *svif)
3412 struct hwrm_func_qcfg_input req = {0};
3413 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3417 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3418 req.fid = rte_cpu_to_le_16(fid);
3420 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3422 HWRM_CHECK_RESULT();
3425 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3427 svif_info = rte_le_to_cpu_16(resp->svif_info);
3428 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3429 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3436 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3438 struct hwrm_port_mac_qcfg_input req = {0};
3439 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3440 uint16_t port_svif_info;
3443 bp->port_svif = BNXT_SVIF_INVALID;
3445 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3448 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3450 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3452 HWRM_CHECK_RESULT_SILENT();
3454 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3455 if (port_svif_info &
3456 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3457 bp->port_svif = port_svif_info &
3458 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3465 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3466 struct bnxt_pf_resource_info *pf_resc)
3468 struct hwrm_func_cfg_input req = {0};
3469 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3473 enables = HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3474 HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU |
3475 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3476 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3477 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3478 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3479 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3480 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3481 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3482 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3484 if (BNXT_HAS_RING_GRPS(bp)) {
3485 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3486 req.num_hw_ring_grps =
3487 rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3488 } else if (BNXT_HAS_NQ(bp)) {
3489 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3490 req.num_msix = rte_cpu_to_le_16(pf_resc->num_nq_rings);
3493 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3494 req.admin_mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3495 req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
3496 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3497 req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3498 req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3499 req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3500 req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3501 req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3502 req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3503 req.num_vnics = rte_cpu_to_le_16(pf_resc->num_vnics);
3504 req.fid = rte_cpu_to_le_16(0xffff);
3505 req.enables = rte_cpu_to_le_32(enables);
3507 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3509 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3511 HWRM_CHECK_RESULT();
3517 /* min values are the guaranteed resources and max values are subject
3518 * to availability. The strategy for now is to keep both min & max
3522 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3523 struct hwrm_func_vf_resource_cfg_input *req,
3526 req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3528 req->min_rsscos_ctx = req->max_rsscos_ctx;
3529 req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3530 req->min_stat_ctx = req->max_stat_ctx;
3531 req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3533 req->min_cmpl_rings = req->max_cmpl_rings;
3534 req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3535 req->min_tx_rings = req->max_tx_rings;
3536 req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3537 req->min_rx_rings = req->max_rx_rings;
3538 req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3539 req->min_l2_ctxs = req->max_l2_ctxs;
3540 req->max_vnics = rte_cpu_to_le_16(bp->max_vnics / (num_vfs + 1));
3541 req->min_vnics = req->max_vnics;
3542 req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3544 req->min_hw_ring_grps = req->max_hw_ring_grps;
3545 req->max_msix = rte_cpu_to_le_16(bp->max_nq_rings / (num_vfs + 1));
3549 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3550 struct hwrm_func_cfg_input *req,
3553 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3554 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3555 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3556 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3557 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3558 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3559 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3560 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3561 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3562 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3564 req->admin_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3565 RTE_ETHER_CRC_LEN + RTE_VLAN_HLEN *
3567 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3568 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3570 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3571 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3573 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3574 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3575 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3576 /* TODO: For now, do not support VMDq/RFS on VFs. */
3577 req->num_vnics = rte_cpu_to_le_16(1);
3578 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3582 /* Update the port wide resource values based on how many resources
3583 * got allocated to the VF.
3585 static int bnxt_update_max_resources(struct bnxt *bp,
3588 struct hwrm_func_qcfg_input req = {0};
3589 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3592 /* Get the actual allocated values now */
3593 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3594 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3595 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3596 HWRM_CHECK_RESULT();
3598 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3599 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3600 bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3601 bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3602 bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3603 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3604 bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3605 bp->max_nq_rings -= rte_le_to_cpu_16(resp->alloc_msix);
3606 bp->max_vnics -= rte_le_to_cpu_16(resp->alloc_vnics);
3613 /* Update the PF resource values based on how many resources
3614 * got allocated to it.
3616 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3618 struct hwrm_func_qcfg_input req = {0};
3619 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3622 /* Get the actual allocated values now */
3623 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3624 req.fid = rte_cpu_to_le_16(0xffff);
3625 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3626 HWRM_CHECK_RESULT();
3628 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3629 bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3630 bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3631 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3632 bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3633 bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3634 bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3635 bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3642 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3644 struct hwrm_func_qcfg_input req = {0};
3645 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3648 /* Check for zero MAC address */
3649 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3650 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3651 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3652 HWRM_CHECK_RESULT();
3653 rc = rte_le_to_cpu_16(resp->vlan);
3660 static int bnxt_query_pf_resources(struct bnxt *bp,
3661 struct bnxt_pf_resource_info *pf_resc)
3663 struct hwrm_func_qcfg_input req = {0};
3664 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3667 /* And copy the allocated numbers into the pf struct */
3668 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3669 req.fid = rte_cpu_to_le_16(0xffff);
3670 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3671 HWRM_CHECK_RESULT();
3673 pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3674 pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3675 pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3676 pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3677 pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3678 pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3679 pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3680 pf_resc->num_nq_rings = rte_le_to_cpu_32(resp->alloc_msix);
3681 pf_resc->num_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3682 bp->pf->evb_mode = resp->evb_mode;
3690 bnxt_calculate_pf_resources(struct bnxt *bp,
3691 struct bnxt_pf_resource_info *pf_resc,
3695 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3696 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3697 pf_resc->num_cp_rings = bp->max_cp_rings;
3698 pf_resc->num_tx_rings = bp->max_tx_rings;
3699 pf_resc->num_rx_rings = bp->max_rx_rings;
3700 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3701 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3702 pf_resc->num_nq_rings = bp->max_nq_rings;
3703 pf_resc->num_vnics = bp->max_vnics;
3708 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3709 bp->max_rsscos_ctx % (num_vfs + 1);
3710 pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3711 bp->max_stat_ctx % (num_vfs + 1);
3712 pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3713 bp->max_cp_rings % (num_vfs + 1);
3714 pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3715 bp->max_tx_rings % (num_vfs + 1);
3716 pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3717 bp->max_rx_rings % (num_vfs + 1);
3718 pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3719 bp->max_l2_ctx % (num_vfs + 1);
3720 pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3721 bp->max_ring_grps % (num_vfs + 1);
3722 pf_resc->num_nq_rings = bp->max_nq_rings / (num_vfs + 1) +
3723 bp->max_nq_rings % (num_vfs + 1);
3724 pf_resc->num_vnics = bp->max_vnics / (num_vfs + 1) +
3725 bp->max_vnics % (num_vfs + 1);
3728 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3730 struct bnxt_pf_resource_info pf_resc = { 0 };
3734 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3738 rc = bnxt_hwrm_func_qcaps(bp);
3742 bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3744 bp->pf->func_cfg_flags &=
3745 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3746 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3747 bp->pf->func_cfg_flags |=
3748 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3750 rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3754 rc = bnxt_update_max_resources_pf_only(bp);
3760 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3762 size_t req_buf_sz, sz;
3765 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3766 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3767 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3768 if (bp->pf->vf_req_buf == NULL) {
3772 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3773 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3775 for (i = 0; i < num_vfs; i++)
3776 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3777 (i * HWRM_MAX_REQ_LEN);
3779 rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3781 rte_free(bp->pf->vf_req_buf);
3787 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3789 struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3790 struct hwrm_func_vf_resource_cfg_input req = {0};
3793 bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3794 bp->pf->active_vfs = 0;
3795 for (i = 0; i < num_vfs; i++) {
3796 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3797 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3798 rc = bnxt_hwrm_send_message(bp,
3802 if (rc || resp->error_code) {
3804 "Failed to initialize VF %d\n", i);
3806 "Not all VFs available. (%d, %d)\n",
3807 rc, resp->error_code);
3810 /* If the first VF configuration itself fails,
3811 * unregister the vf_fwd_request buffer.
3814 bnxt_hwrm_func_buf_unrgtr(bp);
3819 /* Update the max resource values based on the resource values
3820 * allocated to the VF.
3822 bnxt_update_max_resources(bp, i);
3823 bp->pf->active_vfs++;
3824 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3831 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3833 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3834 struct hwrm_func_cfg_input req = {0};
3837 bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3839 bp->pf->active_vfs = 0;
3840 for (i = 0; i < num_vfs; i++) {
3841 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3842 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3843 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3844 rc = bnxt_hwrm_send_message(bp,
3849 /* Clear enable flag for next pass */
3850 req.enables &= ~rte_cpu_to_le_32(
3851 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3853 if (rc || resp->error_code) {
3855 "Failed to initialize VF %d\n", i);
3857 "Not all VFs available. (%d, %d)\n",
3858 rc, resp->error_code);
3861 /* If the first VF configuration itself fails,
3862 * unregister the vf_fwd_request buffer.
3865 bnxt_hwrm_func_buf_unrgtr(bp);
3871 /* Update the max resource values based on the resource values
3872 * allocated to the VF.
3874 bnxt_update_max_resources(bp, i);
3875 bp->pf->active_vfs++;
3876 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3883 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3885 if (bp->flags & BNXT_FLAG_NEW_RM)
3886 bnxt_process_vf_resc_config_new(bp, num_vfs);
3888 bnxt_process_vf_resc_config_old(bp, num_vfs);
3892 bnxt_update_pf_resources(struct bnxt *bp,
3893 struct bnxt_pf_resource_info *pf_resc)
3895 bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3896 bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3897 bp->max_cp_rings = pf_resc->num_cp_rings;
3898 bp->max_tx_rings = pf_resc->num_tx_rings;
3899 bp->max_rx_rings = pf_resc->num_rx_rings;
3900 bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3901 bp->max_nq_rings = pf_resc->num_nq_rings;
3902 bp->max_vnics = pf_resc->num_vnics;
3906 bnxt_configure_pf_resources(struct bnxt *bp,
3907 struct bnxt_pf_resource_info *pf_resc)
3910 * We're using STD_TX_RING_MODE here which will limit the TX
3911 * rings. This will allow QoS to function properly. Not setting this
3912 * will cause PF rings to break bandwidth settings.
3914 bp->pf->func_cfg_flags &=
3915 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3916 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3917 bp->pf->func_cfg_flags |=
3918 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3919 return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3922 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3924 struct bnxt_pf_resource_info pf_resc = { 0 };
3928 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3932 rc = bnxt_hwrm_func_qcaps(bp);
3936 bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3938 rc = bnxt_configure_pf_resources(bp, &pf_resc);
3942 rc = bnxt_query_pf_resources(bp, &pf_resc);
3947 * Now, create and register a buffer to hold forwarded VF requests
3949 rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3953 bnxt_configure_vf_resources(bp, num_vfs);
3955 bnxt_update_pf_resources(bp, &pf_resc);
3960 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3962 struct hwrm_func_cfg_input req = {0};
3963 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3966 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3968 req.fid = rte_cpu_to_le_16(0xffff);
3969 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3970 req.evb_mode = bp->pf->evb_mode;
3972 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3973 HWRM_CHECK_RESULT();
3979 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3980 uint8_t tunnel_type)
3982 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3983 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3986 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3987 req.tunnel_type = tunnel_type;
3988 req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3989 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3990 HWRM_CHECK_RESULT();
3992 switch (tunnel_type) {
3993 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3994 bp->vxlan_fw_dst_port_id =
3995 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3996 bp->vxlan_port = port;
3998 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3999 bp->geneve_fw_dst_port_id =
4000 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
4001 bp->geneve_port = port;
4012 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4013 uint8_t tunnel_type)
4015 struct hwrm_tunnel_dst_port_free_input req = {0};
4016 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4019 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4021 req.tunnel_type = tunnel_type;
4022 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4023 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4025 HWRM_CHECK_RESULT();
4029 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4031 bp->vxlan_port_cnt = 0;
4035 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4036 bp->geneve_port = 0;
4037 bp->geneve_port_cnt = 0;
4043 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4046 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4047 struct hwrm_func_cfg_input req = {0};
4050 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4052 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4053 req.flags = rte_cpu_to_le_32(flags);
4054 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4056 HWRM_CHECK_RESULT();
4062 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4064 uint32_t *flag = flagp;
4066 vnic->flags = *flag;
4069 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4071 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4074 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4076 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4077 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4080 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4082 req.req_buf_num_pages = rte_cpu_to_le_16(1);
4083 req.req_buf_page_size =
4084 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4085 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4086 req.req_buf_page_addr0 =
4087 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4088 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4090 "unable to map buffer address to physical memory\n");
4095 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4097 HWRM_CHECK_RESULT();
4103 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4106 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4107 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4109 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4112 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4114 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4116 HWRM_CHECK_RESULT();
4122 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4124 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4125 struct hwrm_func_cfg_input req = {0};
4128 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4130 req.fid = rte_cpu_to_le_16(0xffff);
4131 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4132 req.enables = rte_cpu_to_le_32(
4133 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4134 req.async_event_cr = rte_cpu_to_le_16(
4135 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4136 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4138 HWRM_CHECK_RESULT();
4144 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4146 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4147 struct hwrm_func_vf_cfg_input req = {0};
4150 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4152 req.enables = rte_cpu_to_le_32(
4153 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4154 req.async_event_cr = rte_cpu_to_le_16(
4155 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4156 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4158 HWRM_CHECK_RESULT();
4164 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4166 struct hwrm_func_cfg_input req = {0};
4167 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4168 uint16_t dflt_vlan, fid;
4169 uint32_t func_cfg_flags;
4172 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4175 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4176 fid = bp->pf->vf_info[vf].fid;
4177 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4179 fid = rte_cpu_to_le_16(0xffff);
4180 func_cfg_flags = bp->pf->func_cfg_flags;
4181 dflt_vlan = bp->vlan;
4184 req.flags = rte_cpu_to_le_32(func_cfg_flags);
4185 req.fid = rte_cpu_to_le_16(fid);
4186 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4187 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4189 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4191 HWRM_CHECK_RESULT();
4197 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4198 uint16_t max_bw, uint16_t enables)
4200 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4201 struct hwrm_func_cfg_input req = {0};
4204 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4206 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4207 req.enables |= rte_cpu_to_le_32(enables);
4208 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4209 req.max_bw = rte_cpu_to_le_32(max_bw);
4210 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4212 HWRM_CHECK_RESULT();
4218 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4220 struct hwrm_func_cfg_input req = {0};
4221 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4224 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4226 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4227 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4228 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4229 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4231 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4233 HWRM_CHECK_RESULT();
4239 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4244 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4246 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4251 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4252 void *encaped, size_t ec_size)
4255 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4256 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4258 if (ec_size > sizeof(req.encap_request))
4261 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4263 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4264 memcpy(req.encap_request, encaped, ec_size);
4266 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4268 HWRM_CHECK_RESULT();
4274 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4275 struct rte_ether_addr *mac)
4277 struct hwrm_func_qcfg_input req = {0};
4278 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4281 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4283 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4284 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4286 HWRM_CHECK_RESULT();
4288 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4295 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4296 void *encaped, size_t ec_size)
4299 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4300 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4302 if (ec_size > sizeof(req.encap_request))
4305 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4307 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4308 memcpy(req.encap_request, encaped, ec_size);
4310 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4312 HWRM_CHECK_RESULT();
4318 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4320 /* One of the HW stat values that make up this counter was zero as
4321 * returned by HW in this iteration, so use the previous
4322 * iteration's counter value
4324 if (*prev_cntr && *cntr == 0)
4330 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4331 struct bnxt_ring_stats *ring_stats, bool rx)
4334 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4335 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4337 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4339 req.stat_ctx_id = rte_cpu_to_le_32(cid);
4341 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4343 HWRM_CHECK_RESULT();
4346 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4348 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4349 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4350 &prev_stats->rx_ucast_pkts);
4352 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4353 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4354 &prev_stats->rx_mcast_pkts);
4356 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4357 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4358 &prev_stats->rx_bcast_pkts);
4360 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4361 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4362 &prev_stats->rx_ucast_bytes);
4364 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4365 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4366 &prev_stats->rx_mcast_bytes);
4368 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4369 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4370 &prev_stats->rx_bcast_bytes);
4372 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4373 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4374 &prev_stats->rx_discard_pkts);
4376 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4377 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4378 &prev_stats->rx_error_pkts);
4380 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4381 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4382 &prev_stats->rx_agg_pkts);
4384 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4385 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4386 &prev_stats->rx_agg_bytes);
4388 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4389 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4390 &prev_stats->rx_agg_events);
4392 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4393 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4394 &prev_stats->rx_agg_aborts);
4396 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4398 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4399 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4400 &prev_stats->tx_ucast_pkts);
4402 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4403 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4404 &prev_stats->tx_mcast_pkts);
4406 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4407 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4408 &prev_stats->tx_bcast_pkts);
4410 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4411 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4412 &prev_stats->tx_ucast_bytes);
4414 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4415 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4416 &prev_stats->tx_mcast_bytes);
4418 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4419 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4420 &prev_stats->tx_bcast_bytes);
4422 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4423 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4424 &prev_stats->tx_discard_pkts);
4432 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4434 struct hwrm_port_qstats_input req = {0};
4435 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4436 struct bnxt_pf_info *pf = bp->pf;
4439 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4441 req.port_id = rte_cpu_to_le_16(pf->port_id);
4442 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4443 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4444 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4446 HWRM_CHECK_RESULT();
4452 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4454 struct hwrm_port_clr_stats_input req = {0};
4455 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4456 struct bnxt_pf_info *pf = bp->pf;
4459 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4460 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4461 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4464 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4466 req.port_id = rte_cpu_to_le_16(pf->port_id);
4467 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4469 HWRM_CHECK_RESULT();
4475 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4477 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4478 struct hwrm_port_led_qcaps_input req = {0};
4484 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4485 req.port_id = bp->pf->port_id;
4486 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4488 HWRM_CHECK_RESULT_SILENT();
4490 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4493 bp->leds->num_leds = resp->num_leds;
4494 memcpy(bp->leds, &resp->led0_id,
4495 sizeof(bp->leds[0]) * bp->leds->num_leds);
4496 for (i = 0; i < bp->leds->num_leds; i++) {
4497 struct bnxt_led_info *led = &bp->leds[i];
4499 uint16_t caps = led->led_state_caps;
4501 if (!led->led_group_id ||
4502 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4503 bp->leds->num_leds = 0;
4514 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4516 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4517 struct hwrm_port_led_cfg_input req = {0};
4518 struct bnxt_led_cfg *led_cfg;
4519 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4520 uint16_t duration = 0;
4523 if (!bp->leds->num_leds || BNXT_VF(bp))
4526 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4529 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4530 duration = rte_cpu_to_le_16(500);
4532 req.port_id = bp->pf->port_id;
4533 req.num_leds = bp->leds->num_leds;
4534 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4535 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4536 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4537 led_cfg->led_id = bp->leds[i].led_id;
4538 led_cfg->led_state = led_state;
4539 led_cfg->led_blink_on = duration;
4540 led_cfg->led_blink_off = duration;
4541 led_cfg->led_group_id = bp->leds[i].led_group_id;
4544 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4546 HWRM_CHECK_RESULT();
4552 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4556 struct hwrm_nvm_get_dir_info_input req = {0};
4557 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4559 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4561 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4563 HWRM_CHECK_RESULT();
4565 *entries = rte_le_to_cpu_32(resp->entries);
4566 *length = rte_le_to_cpu_32(resp->entry_length);
4572 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4575 uint32_t dir_entries;
4576 uint32_t entry_length;
4579 rte_iova_t dma_handle;
4580 struct hwrm_nvm_get_dir_entries_input req = {0};
4581 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4583 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4587 *data++ = dir_entries;
4588 *data++ = entry_length;
4590 memset(data, 0xff, len);
4592 buflen = dir_entries * entry_length;
4593 buf = rte_malloc("nvm_dir", buflen, 0);
4596 dma_handle = rte_malloc_virt2iova(buf);
4597 if (dma_handle == RTE_BAD_IOVA) {
4600 "unable to map response address to physical memory\n");
4603 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4604 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4605 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4608 memcpy(data, buf, len > buflen ? buflen : len);
4611 HWRM_CHECK_RESULT();
4617 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4618 uint32_t offset, uint32_t length,
4623 rte_iova_t dma_handle;
4624 struct hwrm_nvm_read_input req = {0};
4625 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4627 buf = rte_malloc("nvm_item", length, 0);
4631 dma_handle = rte_malloc_virt2iova(buf);
4632 if (dma_handle == RTE_BAD_IOVA) {
4635 "unable to map response address to physical memory\n");
4638 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4639 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4640 req.dir_idx = rte_cpu_to_le_16(index);
4641 req.offset = rte_cpu_to_le_32(offset);
4642 req.len = rte_cpu_to_le_32(length);
4643 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4645 memcpy(data, buf, length);
4648 HWRM_CHECK_RESULT();
4654 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4657 struct hwrm_nvm_erase_dir_entry_input req = {0};
4658 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4660 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4661 req.dir_idx = rte_cpu_to_le_16(index);
4662 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4663 HWRM_CHECK_RESULT();
4669 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4670 uint16_t dir_ordinal, uint16_t dir_ext,
4671 uint16_t dir_attr, const uint8_t *data,
4675 struct hwrm_nvm_write_input req = {0};
4676 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4677 rte_iova_t dma_handle;
4680 buf = rte_malloc("nvm_write", data_len, 0);
4684 dma_handle = rte_malloc_virt2iova(buf);
4685 if (dma_handle == RTE_BAD_IOVA) {
4688 "unable to map response address to physical memory\n");
4691 memcpy(buf, data, data_len);
4693 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4695 req.dir_type = rte_cpu_to_le_16(dir_type);
4696 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4697 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4698 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4699 req.dir_data_length = rte_cpu_to_le_32(data_len);
4700 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4702 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4705 HWRM_CHECK_RESULT();
4712 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4714 uint32_t *count = cbdata;
4716 *count = *count + 1;
4719 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4720 struct bnxt_vnic_info *vnic __rte_unused)
4725 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4729 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4730 &count, bnxt_vnic_count_hwrm_stub);
4735 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4738 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4739 struct hwrm_func_vf_vnic_ids_query_output *resp =
4740 bp->hwrm_cmd_resp_addr;
4743 /* First query all VNIC ids */
4744 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4746 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4747 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4748 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4750 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4753 "unable to map VNIC ID table address to physical memory\n");
4756 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4757 HWRM_CHECK_RESULT();
4758 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4766 * This function queries the VNIC IDs for a specified VF. It then calls
4767 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4768 * Then it calls the hwrm_cb function to program this new vnic configuration.
4770 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4771 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4772 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4774 struct bnxt_vnic_info vnic;
4776 int i, num_vnic_ids;
4781 /* First query all VNIC ids */
4782 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4783 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4784 RTE_CACHE_LINE_SIZE);
4785 if (vnic_ids == NULL)
4788 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4789 rte_mem_lock_page(((char *)vnic_ids) + sz);
4791 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4793 if (num_vnic_ids < 0)
4794 return num_vnic_ids;
4796 /* Retrieve VNIC, update bd_stall then update */
4798 for (i = 0; i < num_vnic_ids; i++) {
4799 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4800 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4801 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4804 if (vnic.mru <= 4) /* Indicates unallocated */
4807 vnic_cb(&vnic, cbdata);
4809 rc = hwrm_cb(bp, &vnic);
4819 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4822 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4823 struct hwrm_func_cfg_input req = {0};
4826 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4828 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4829 req.enables |= rte_cpu_to_le_32(
4830 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4831 req.vlan_antispoof_mode = on ?
4832 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4833 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4834 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4836 HWRM_CHECK_RESULT();
4842 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4844 struct bnxt_vnic_info vnic;
4847 int num_vnic_ids, i;
4851 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4852 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4853 RTE_CACHE_LINE_SIZE);
4854 if (vnic_ids == NULL)
4857 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4858 rte_mem_lock_page(((char *)vnic_ids) + sz);
4860 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4866 * Loop through to find the default VNIC ID.
4867 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4868 * by sending the hwrm_func_qcfg command to the firmware.
4870 for (i = 0; i < num_vnic_ids; i++) {
4871 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4872 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4873 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4874 bp->pf->first_vf_id + vf);
4877 if (vnic.func_default) {
4879 return vnic.fw_vnic_id;
4882 /* Could not find a default VNIC. */
4883 PMD_DRV_LOG(ERR, "No default VNIC\n");
4889 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4891 struct bnxt_filter_info *filter)
4894 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4895 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4896 uint32_t enables = 0;
4898 if (filter->fw_em_filter_id != UINT64_MAX)
4899 bnxt_hwrm_clear_em_filter(bp, filter);
4901 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4903 req.flags = rte_cpu_to_le_32(filter->flags);
4905 enables = filter->enables |
4906 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4907 req.dst_id = rte_cpu_to_le_16(dst_id);
4909 if (filter->ip_addr_type) {
4910 req.ip_addr_type = filter->ip_addr_type;
4911 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4914 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4915 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4917 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4918 memcpy(req.src_macaddr, filter->src_macaddr,
4919 RTE_ETHER_ADDR_LEN);
4921 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4922 memcpy(req.dst_macaddr, filter->dst_macaddr,
4923 RTE_ETHER_ADDR_LEN);
4925 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4926 req.ovlan_vid = filter->l2_ovlan;
4928 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4929 req.ivlan_vid = filter->l2_ivlan;
4931 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4932 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4934 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4935 req.ip_protocol = filter->ip_protocol;
4937 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4938 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4940 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4941 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4943 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4944 req.src_port = rte_cpu_to_be_16(filter->src_port);
4946 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4947 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4949 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4950 req.mirror_vnic_id = filter->mirror_vnic_id;
4952 req.enables = rte_cpu_to_le_32(enables);
4954 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4956 HWRM_CHECK_RESULT();
4958 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4964 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4967 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4968 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4970 if (filter->fw_em_filter_id == UINT64_MAX)
4973 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4975 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4977 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4979 HWRM_CHECK_RESULT();
4982 filter->fw_em_filter_id = UINT64_MAX;
4983 filter->fw_l2_filter_id = UINT64_MAX;
4988 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4990 struct bnxt_filter_info *filter)
4993 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4994 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4995 bp->hwrm_cmd_resp_addr;
4996 uint32_t enables = 0;
4998 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4999 bnxt_hwrm_clear_ntuple_filter(bp, filter);
5001 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
5003 req.flags = rte_cpu_to_le_32(filter->flags);
5005 enables = filter->enables |
5006 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
5007 req.dst_id = rte_cpu_to_le_16(dst_id);
5009 if (filter->ip_addr_type) {
5010 req.ip_addr_type = filter->ip_addr_type;
5012 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
5015 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5016 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5018 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5019 memcpy(req.src_macaddr, filter->src_macaddr,
5020 RTE_ETHER_ADDR_LEN);
5022 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5023 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5025 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5026 req.ip_protocol = filter->ip_protocol;
5028 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5029 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5031 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5032 req.src_ipaddr_mask[0] =
5033 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5035 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5036 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5038 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5039 req.dst_ipaddr_mask[0] =
5040 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5042 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5043 req.src_port = rte_cpu_to_le_16(filter->src_port);
5045 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5046 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5048 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5049 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5051 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5052 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5054 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5055 req.mirror_vnic_id = filter->mirror_vnic_id;
5057 req.enables = rte_cpu_to_le_32(enables);
5059 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5061 HWRM_CHECK_RESULT();
5063 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5064 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5070 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5071 struct bnxt_filter_info *filter)
5074 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5075 struct hwrm_cfa_ntuple_filter_free_output *resp =
5076 bp->hwrm_cmd_resp_addr;
5078 if (filter->fw_ntuple_filter_id == UINT64_MAX)
5081 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5083 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5085 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5087 HWRM_CHECK_RESULT();
5090 filter->fw_ntuple_filter_id = UINT64_MAX;
5096 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5098 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5099 uint8_t *rxq_state = bp->eth_dev->data->rx_queue_state;
5100 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5101 struct bnxt_rx_queue **rxqs = bp->rx_queues;
5102 uint16_t *ring_tbl = vnic->rss_table;
5103 int nr_ctxs = vnic->num_lb_ctxts;
5104 int max_rings = bp->rx_nr_rings;
5108 for (i = 0, k = 0; i < nr_ctxs; i++) {
5109 struct bnxt_rx_ring_info *rxr;
5110 struct bnxt_cp_ring_info *cpr;
5112 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5114 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5115 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5116 req.hash_mode_flags = vnic->hash_mode;
5118 req.ring_grp_tbl_addr =
5119 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5120 i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5121 2 * sizeof(*ring_tbl));
5122 req.hash_key_tbl_addr =
5123 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5125 req.ring_table_pair_index = i;
5126 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5128 for (j = 0; j < 64; j++) {
5131 /* Find next active ring. */
5132 for (cnt = 0; cnt < max_rings; cnt++) {
5133 if (rxq_state[k] != RTE_ETH_QUEUE_STATE_STOPPED)
5135 if (++k == max_rings)
5139 /* Return if no rings are active. */
5140 if (cnt == max_rings) {
5145 /* Add rx/cp ring pair to RSS table. */
5146 rxr = rxqs[k]->rx_ring;
5147 cpr = rxqs[k]->cp_ring;
5149 ring_id = rxr->rx_ring_struct->fw_ring_id;
5150 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5151 ring_id = cpr->cp_ring_struct->fw_ring_id;
5152 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5154 if (++k == max_rings)
5157 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5160 HWRM_CHECK_RESULT();
5167 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5169 unsigned int rss_idx, fw_idx, i;
5171 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5174 if (!(vnic->rss_table && vnic->hash_type))
5177 if (BNXT_CHIP_P5(bp))
5178 return bnxt_vnic_rss_configure_p5(bp, vnic);
5181 * Fill the RSS hash & redirection table with
5182 * ring group ids for all VNICs
5184 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5185 rss_idx++, fw_idx++) {
5186 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5187 fw_idx %= bp->rx_cp_nr_rings;
5188 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5193 if (i == bp->rx_cp_nr_rings)
5196 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5199 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5202 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5203 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5207 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5209 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5210 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5212 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5213 req->num_cmpl_dma_aggr_during_int =
5214 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5216 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5218 /* min timer set to 1/2 of interrupt timer */
5219 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5221 /* buf timer set to 1/4 of interrupt timer */
5222 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5224 req->cmpl_aggr_dma_tmr_during_int =
5225 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5227 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5228 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5229 req->flags = rte_cpu_to_le_16(flags);
5232 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5233 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5235 struct hwrm_ring_aggint_qcaps_input req = {0};
5236 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5241 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5242 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5243 HWRM_CHECK_RESULT();
5245 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5246 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5248 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5249 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5250 agg_req->flags = rte_cpu_to_le_16(flags);
5252 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5253 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5254 agg_req->enables = rte_cpu_to_le_32(enables);
5260 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5261 struct bnxt_coal *coal, uint16_t ring_id)
5263 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5264 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5265 bp->hwrm_cmd_resp_addr;
5268 /* Set ring coalesce parameters only for 100G NICs */
5269 if (BNXT_CHIP_P5(bp)) {
5270 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5272 } else if (bnxt_stratus_device(bp)) {
5273 bnxt_hwrm_set_coal_params(coal, &req);
5279 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5281 req.ring_id = rte_cpu_to_le_16(ring_id);
5282 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5283 HWRM_CHECK_RESULT();
5288 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5289 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5291 struct hwrm_func_backing_store_qcaps_input req = {0};
5292 struct hwrm_func_backing_store_qcaps_output *resp =
5293 bp->hwrm_cmd_resp_addr;
5294 struct bnxt_ctx_pg_info *ctx_pg;
5295 struct bnxt_ctx_mem_info *ctx;
5296 int total_alloc_len;
5297 int rc, i, tqm_rings;
5299 if (!BNXT_CHIP_P5(bp) ||
5300 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5305 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5306 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5307 HWRM_CHECK_RESULT_SILENT();
5309 total_alloc_len = sizeof(*ctx);
5310 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5311 RTE_CACHE_LINE_SIZE);
5317 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5318 ctx->qp_min_qp1_entries =
5319 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5320 ctx->qp_max_l2_entries =
5321 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5322 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5323 ctx->srq_max_l2_entries =
5324 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5325 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5326 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5327 ctx->cq_max_l2_entries =
5328 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5329 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5330 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5331 ctx->vnic_max_vnic_entries =
5332 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5333 ctx->vnic_max_ring_table_entries =
5334 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5335 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5336 ctx->stat_max_entries =
5337 rte_le_to_cpu_32(resp->stat_max_entries);
5338 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5339 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5340 ctx->tqm_min_entries_per_ring =
5341 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5342 ctx->tqm_max_entries_per_ring =
5343 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5344 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5345 if (!ctx->tqm_entries_multiple)
5346 ctx->tqm_entries_multiple = 1;
5347 ctx->mrav_max_entries =
5348 rte_le_to_cpu_32(resp->mrav_max_entries);
5349 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5350 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5351 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5352 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5354 ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5355 RTE_MIN(ctx->tqm_fp_rings_count,
5356 BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5359 /* Check if the ext ring count needs to be counted.
5360 * Ext ring count is available only with new FW so we should not
5361 * look at the field on older FW.
5363 if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5364 bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5365 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5366 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5367 ctx->tqm_fp_rings_count);
5370 tqm_rings = ctx->tqm_fp_rings_count + 1;
5372 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5373 sizeof(*ctx_pg) * tqm_rings,
5374 RTE_CACHE_LINE_SIZE);
5379 for (i = 0; i < tqm_rings; i++, ctx_pg++)
5380 ctx->tqm_mem[i] = ctx_pg;
5388 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5390 struct hwrm_func_backing_store_cfg_input req = {0};
5391 struct hwrm_func_backing_store_cfg_output *resp =
5392 bp->hwrm_cmd_resp_addr;
5393 struct bnxt_ctx_mem_info *ctx = bp->ctx;
5394 struct bnxt_ctx_pg_info *ctx_pg;
5395 uint32_t *num_entries;
5404 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5405 req.enables = rte_cpu_to_le_32(enables);
5407 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5408 ctx_pg = &ctx->qp_mem;
5409 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5410 req.qp_num_qp1_entries =
5411 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5412 req.qp_num_l2_entries =
5413 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5414 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5415 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5416 &req.qpc_pg_size_qpc_lvl,
5420 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5421 ctx_pg = &ctx->srq_mem;
5422 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5423 req.srq_num_l2_entries =
5424 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5425 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5426 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5427 &req.srq_pg_size_srq_lvl,
5431 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5432 ctx_pg = &ctx->cq_mem;
5433 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5434 req.cq_num_l2_entries =
5435 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5436 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5437 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5438 &req.cq_pg_size_cq_lvl,
5442 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5443 ctx_pg = &ctx->vnic_mem;
5444 req.vnic_num_vnic_entries =
5445 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5446 req.vnic_num_ring_table_entries =
5447 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5448 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5449 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5450 &req.vnic_pg_size_vnic_lvl,
5451 &req.vnic_page_dir);
5454 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5455 ctx_pg = &ctx->stat_mem;
5456 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5457 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5458 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5459 &req.stat_pg_size_stat_lvl,
5460 &req.stat_page_dir);
5463 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5464 num_entries = &req.tqm_sp_num_entries;
5465 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5466 pg_dir = &req.tqm_sp_page_dir;
5467 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5468 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5469 if (!(enables & ena))
5472 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5474 ctx_pg = ctx->tqm_mem[i];
5475 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5476 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5479 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5480 /* DPDK does not need to configure MRAV and TIM type.
5481 * So we are skipping over MRAV and TIM. Skip to configure
5482 * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5484 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5485 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5486 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5487 &req.tqm_ring8_pg_size_tqm_ring_lvl,
5488 &req.tqm_ring8_page_dir);
5491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5492 HWRM_CHECK_RESULT();
5498 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5500 struct hwrm_port_qstats_ext_input req = {0};
5501 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5502 struct bnxt_pf_info *pf = bp->pf;
5505 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5506 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5509 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5511 req.port_id = rte_cpu_to_le_16(pf->port_id);
5512 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5513 req.tx_stat_host_addr =
5514 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5516 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5518 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5519 req.rx_stat_host_addr =
5520 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5522 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5524 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5527 bp->fw_rx_port_stats_ext_size = 0;
5528 bp->fw_tx_port_stats_ext_size = 0;
5530 bp->fw_rx_port_stats_ext_size =
5531 rte_le_to_cpu_16(resp->rx_stat_size);
5532 bp->fw_tx_port_stats_ext_size =
5533 rte_le_to_cpu_16(resp->tx_stat_size);
5536 HWRM_CHECK_RESULT();
5543 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5545 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5546 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5547 bp->hwrm_cmd_resp_addr;
5550 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5551 req.tunnel_type = type;
5552 req.dest_fid = bp->fw_fid;
5553 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5554 HWRM_CHECK_RESULT();
5562 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5564 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5565 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5566 bp->hwrm_cmd_resp_addr;
5569 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5570 req.tunnel_type = type;
5571 req.dest_fid = bp->fw_fid;
5572 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5573 HWRM_CHECK_RESULT();
5580 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5582 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5583 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5584 bp->hwrm_cmd_resp_addr;
5587 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5588 req.src_fid = bp->fw_fid;
5589 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5590 HWRM_CHECK_RESULT();
5593 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5600 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5603 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5604 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5605 bp->hwrm_cmd_resp_addr;
5608 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5609 req.src_fid = bp->fw_fid;
5610 req.tunnel_type = tun_type;
5611 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5612 HWRM_CHECK_RESULT();
5615 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5617 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5624 int bnxt_hwrm_set_mac(struct bnxt *bp)
5626 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5627 struct hwrm_func_vf_cfg_input req = {0};
5633 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5636 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5637 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5639 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5641 HWRM_CHECK_RESULT();
5648 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5650 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5651 struct hwrm_func_drv_if_change_input req = {0};
5655 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5658 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5659 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5660 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5662 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5665 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5669 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5671 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5673 HWRM_CHECK_RESULT();
5674 flags = rte_le_to_cpu_32(resp->flags);
5680 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5681 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5682 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5688 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5690 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5691 struct bnxt_error_recovery_info *info = bp->recovery_info;
5692 struct hwrm_error_recovery_qcfg_input req = {0};
5697 /* Older FW does not have error recovery support */
5698 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5701 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5703 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5705 HWRM_CHECK_RESULT();
5707 flags = rte_le_to_cpu_32(resp->flags);
5708 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5709 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5710 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5711 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5713 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5714 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5719 /* FW returned values are in units of 100msec */
5720 info->driver_polling_freq =
5721 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5722 info->primary_func_wait_period =
5723 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5724 info->normal_func_wait_period =
5725 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5726 info->primary_func_wait_period_after_reset =
5727 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5728 info->max_bailout_time_after_reset =
5729 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5730 info->status_regs[BNXT_FW_STATUS_REG] =
5731 rte_le_to_cpu_32(resp->fw_health_status_reg);
5732 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5733 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5734 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5735 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5736 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5737 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5738 info->reg_array_cnt =
5739 rte_le_to_cpu_32(resp->reg_array_cnt);
5741 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5746 for (i = 0; i < info->reg_array_cnt; i++) {
5747 info->reset_reg[i] =
5748 rte_le_to_cpu_32(resp->reset_reg[i]);
5749 info->reset_reg_val[i] =
5750 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5751 info->delay_after_reset[i] =
5752 resp->delay_after_reset[i];
5757 /* Map the FW status registers */
5759 rc = bnxt_map_fw_health_status_regs(bp);
5762 rte_free(bp->recovery_info);
5763 bp->recovery_info = NULL;
5768 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5770 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5771 struct hwrm_fw_reset_input req = {0};
5777 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5779 req.embedded_proc_type =
5780 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5781 req.selfrst_status =
5782 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5783 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5785 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5788 HWRM_CHECK_RESULT();
5794 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5796 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5797 struct hwrm_port_ts_query_input req = {0};
5798 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5805 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5808 case BNXT_PTP_FLAGS_PATH_TX:
5809 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5811 case BNXT_PTP_FLAGS_PATH_RX:
5812 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5814 case BNXT_PTP_FLAGS_CURRENT_TIME:
5815 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5819 req.flags = rte_cpu_to_le_32(flags);
5820 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5822 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5824 HWRM_CHECK_RESULT();
5827 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5829 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5836 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5840 struct hwrm_cfa_counter_qcaps_input req = {0};
5841 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5843 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5845 "Not a PF or trusted VF. Command not supported\n");
5849 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5850 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5853 HWRM_CHECK_RESULT();
5855 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5861 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5864 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5865 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5867 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5869 "Not a PF or trusted VF. Command not supported\n");
5873 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5875 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5876 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5877 req.page_dir = rte_cpu_to_le_64(dma_addr);
5879 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5881 HWRM_CHECK_RESULT();
5883 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5884 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5891 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5894 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5895 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5897 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5899 "Not a PF or trusted VF. Command not supported\n");
5903 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5905 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5907 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5909 HWRM_CHECK_RESULT();
5915 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5916 uint16_t cntr, uint16_t ctx_id,
5917 uint32_t num_entries, bool enable)
5919 struct hwrm_cfa_counter_cfg_input req = {0};
5920 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5924 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5926 "Not a PF or trusted VF. Command not supported\n");
5930 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5932 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5933 req.counter_type = rte_cpu_to_le_16(cntr);
5934 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5935 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5936 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5937 if (dir == BNXT_DIR_RX)
5938 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5939 else if (dir == BNXT_DIR_TX)
5940 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5941 req.flags = rte_cpu_to_le_16(flags);
5942 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5943 req.num_entries = rte_cpu_to_le_32(num_entries);
5945 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5946 HWRM_CHECK_RESULT();
5952 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5953 enum bnxt_flow_dir dir,
5955 uint16_t num_entries)
5957 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5958 struct hwrm_cfa_counter_qstats_input req = {0};
5959 uint16_t flow_ctx_id = 0;
5963 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5965 "Not a PF or trusted VF. Command not supported\n");
5969 if (dir == BNXT_DIR_RX) {
5970 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5971 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5972 } else if (dir == BNXT_DIR_TX) {
5973 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5974 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5977 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5978 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5979 req.counter_type = rte_cpu_to_le_16(cntr);
5980 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5981 req.num_entries = rte_cpu_to_le_16(num_entries);
5982 req.flags = rte_cpu_to_le_16(flags);
5983 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5985 HWRM_CHECK_RESULT();
5991 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5992 uint16_t *first_vf_id)
5995 struct hwrm_func_qcaps_input req = {.req_type = 0 };
5996 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5998 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
6000 req.fid = rte_cpu_to_le_16(fid);
6002 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6004 HWRM_CHECK_RESULT();
6007 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
6014 int bnxt_hwrm_cfa_pair_exists(struct bnxt *bp, struct bnxt_representor *rep_bp)
6016 struct hwrm_cfa_pair_info_output *resp = bp->hwrm_cmd_resp_addr;
6017 struct hwrm_cfa_pair_info_input req = {0};
6020 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6022 "Not a PF or trusted VF. Command not supported\n");
6026 HWRM_PREP(&req, HWRM_CFA_PAIR_INFO, BNXT_USE_CHIMP_MB);
6027 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6028 bp->eth_dev->data->name, rep_bp->vf_id);
6030 rte_cpu_to_le_32(HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE);
6032 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6033 HWRM_CHECK_RESULT();
6034 if (rc == HWRM_ERR_CODE_SUCCESS && strlen(resp->pair_name)) {
6042 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6044 struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6045 struct hwrm_cfa_pair_alloc_input req = {0};
6048 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6050 "Not a PF or trusted VF. Command not supported\n");
6054 HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6055 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6056 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6057 bp->eth_dev->data->name, rep_bp->vf_id);
6059 req.pf_b_id = rep_bp->parent_pf_idx;
6060 req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6061 rte_cpu_to_le_16(rep_bp->vf_id);
6062 req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6063 req.host_b_id = 1; /* TBD - Confirm if this is OK */
6065 req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6066 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6067 req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6068 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6069 req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6070 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6071 req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6072 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6074 req.q_ab = rep_bp->rep_q_r2f;
6075 req.q_ba = rep_bp->rep_q_f2r;
6076 req.fc_ab = rep_bp->rep_fc_r2f;
6077 req.fc_ba = rep_bp->rep_fc_f2r;
6079 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6080 HWRM_CHECK_RESULT();
6083 PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6084 BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6088 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6090 struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6091 struct hwrm_cfa_pair_free_input req = {0};
6094 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6096 "Not a PF or trusted VF. Command not supported\n");
6100 HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6101 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6102 bp->eth_dev->data->name, rep_bp->vf_id);
6103 req.pf_b_id = rep_bp->parent_pf_idx;
6104 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6105 req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6106 rte_cpu_to_le_16(rep_bp->vf_id);
6107 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6108 HWRM_CHECK_RESULT();
6110 PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6115 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6116 uint32_t echo_req_data2)
6118 struct hwrm_func_echo_response_input req = {0};
6119 struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6122 HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6123 req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6124 req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6126 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6128 HWRM_CHECK_RESULT();
6134 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6136 struct hwrm_ver_get_input req = {.req_type = 0 };
6137 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6140 bp->max_req_len = HWRM_MAX_REQ_LEN;
6141 bp->max_resp_len = BNXT_PAGE_SIZE;
6142 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6144 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6145 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6146 req.hwrm_intf_min = HWRM_VERSION_MINOR;
6147 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6149 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6151 HWRM_CHECK_RESULT_SILENT();
6157 int bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt *bp, uint16_t i2c_addr,
6158 uint16_t page_number, uint16_t start_addr,
6159 uint16_t data_length, uint8_t *buf)
6161 struct hwrm_port_phy_i2c_read_output *resp = bp->hwrm_cmd_resp_addr;
6162 struct hwrm_port_phy_i2c_read_input req = {0};
6163 uint32_t enables = HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET;
6164 int rc, byte_offset = 0;
6169 HWRM_PREP(&req, HWRM_PORT_PHY_I2C_READ, BNXT_USE_CHIMP_MB);
6170 req.i2c_slave_addr = i2c_addr;
6171 req.page_number = rte_cpu_to_le_16(page_number);
6172 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
6174 xfer_size = RTE_MIN(data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
6175 req.page_offset = rte_cpu_to_le_16(start_addr + byte_offset);
6176 req.data_length = xfer_size;
6177 req.enables = rte_cpu_to_le_32(start_addr + byte_offset ? enables : 0);
6178 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6179 HWRM_CHECK_RESULT();
6181 memcpy(buf + byte_offset, resp->data, xfer_size);
6183 data_length -= xfer_size;
6184 byte_offset += xfer_size;
6187 } while (data_length > 0);
6192 void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index)
6194 struct bnxt_tx_queue *txq = bp->tx_queues[queue_index];
6195 struct bnxt_tx_ring_info *txr = txq->tx_ring;
6196 struct bnxt_ring *ring = txr->tx_ring_struct;
6197 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
6199 bnxt_hwrm_ring_free(bp, ring,
6200 HWRM_RING_FREE_INPUT_RING_TYPE_TX,
6201 cpr->cp_ring_struct->fw_ring_id);
6202 txr->tx_raw_prod = 0;
6203 txr->tx_raw_cons = 0;
6204 memset(txr->tx_desc_ring, 0,
6205 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_desc_ring));
6206 memset(txr->tx_buf_ring, 0,
6207 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_buf_ring));
6209 bnxt_hwrm_stat_ctx_free(bp, cpr);
6211 bnxt_free_cp_ring(bp, cpr);
6214 int bnxt_hwrm_config_host_mtu(struct bnxt *bp)
6216 struct hwrm_func_cfg_input req = {0};
6217 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
6223 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
6225 req.fid = rte_cpu_to_le_16(0xffff);
6226 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU);
6227 req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
6229 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6230 HWRM_CHECK_RESULT();
6237 bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
6239 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
6240 struct hwrm_vnic_rss_cfg_input req = {0};
6241 int nr_ctxs = vnic->num_lb_ctxts;
6244 for (i = 0; i < nr_ctxs; i++) {
6245 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
6247 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
6248 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
6250 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6252 HWRM_CHECK_RESULT();