drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(bp->nb_mc_addr);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(bp->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (BNXT_CHIP_P5(bp)) {
 754                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
 755                         return 0;
 756         } else {
 757                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 758                         return 0;
 759         }
 760
 761         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 762                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 763
 764         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 765         if (!ptp)
 766                 return -ENOMEM;
 767
 768         if (!BNXT_CHIP_P5(bp)) {
 769                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 771                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 773                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 775                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 776                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 777                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 778                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 779                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 781                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 783                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 784                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 785                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 786                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 787         }
 788
 789         ptp->bp = bp;
 790         bp->ptp_cfg = ptp;
 791
 792         return 0;
 793 }
 794
 795 void bnxt_free_vf_info(struct bnxt *bp)
 796 {
 797         int i;
 798
 799         if (bp->pf == NULL)
 800                 return;
 801
 802         if (bp->pf->vf_info == NULL)
 803                 return;
 804
 805         for (i = 0; i < bp->pf->max_vfs; i++) {
 806                 rte_free(bp->pf->vf_info[i].vlan_table);
 807                 bp->pf->vf_info[i].vlan_table = NULL;
 808                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 809                 bp->pf->vf_info[i].vlan_as_table = NULL;
 810         }
 811         rte_free(bp->pf->vf_info);
 812         bp->pf->vf_info = NULL;
 813 }
 814
 815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 816 {
 817         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 818         int i;
 819
 820         if (vf_info)
 821                 bnxt_free_vf_info(bp);
 822
 823         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 824         if (vf_info == NULL) {
 825                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 826                 return -ENOMEM;
 827         }
 828
 829         bp->pf->max_vfs = max_vfs;
 830         for (i = 0; i < max_vfs; i++) {
 831                 vf_info[i].fid = bp->pf->first_vf_id + i;
 832                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 833                                                     getpagesize(), getpagesize());
 834                 if (vf_info[i].vlan_table == NULL) {
 835                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 836                         goto err;
 837                 }
 838                 rte_mem_lock_page(vf_info[i].vlan_table);
 839
 840                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 841                                                        getpagesize(), getpagesize());
 842                 if (vf_info[i].vlan_as_table == NULL) {
 843                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 844                         goto err;
 845                 }
 846                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 847
 848                 STAILQ_INIT(&vf_info[i].filter);
 849         }
 850
 851         bp->pf->vf_info = vf_info;
 852
 853         return 0;
 854 err:
 855         bnxt_free_vf_info(bp);
 856         return -ENOMEM;
 857 }
 858
 859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 860 {
 861         int rc = 0;
 862         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 863         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 864         uint16_t new_max_vfs;
 865         uint32_t flags;
 866
 867         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 868
 869         req.fid = rte_cpu_to_le_16(0xffff);
 870
 871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 872
 873         HWRM_CHECK_RESULT();
 874
 875         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 876         flags = rte_le_to_cpu_32(resp->flags);
 877         if (BNXT_PF(bp)) {
 878                 bp->pf->port_id = resp->port_id;
 879                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 880                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 881                 new_max_vfs = bp->pdev->max_vfs;
 882                 if (new_max_vfs != bp->pf->max_vfs) {
 883                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 884                         if (rc)
 885                                 goto unlock;
 886                 }
 887         }
 888
 889         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 890         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 891                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 892                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 893         } else {
 894                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 895         }
 896         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 897         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 898         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 899         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 900         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 901         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 902         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 903         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 904                 bp->max_l2_ctx += bp->max_rx_em_flows;
 905         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 906         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 907                     bp->max_l2_ctx, bp->max_vnics);
 908         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 909         bp->max_mcast_addr = rte_le_to_cpu_32(resp->max_mcast_filters);
 910
 911         if (BNXT_PF(bp)) {
 912                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 913                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 914                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 915                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 916                         HWRM_UNLOCK();
 917                         bnxt_hwrm_ptp_qcfg(bp);
 918                 }
 919         }
 920
 921         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 922                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 923
 924         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 925                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 926                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 927         }
 928
 929         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 930                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 931
 932         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 933                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 934
 935         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 936                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 937
 938         if (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) {
 939                 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
 940                 PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n");
 941         }
 942
 943         bp->tunnel_disable_flag = rte_le_to_cpu_16(resp->tunnel_disable_flag);
 944         if (bp->tunnel_disable_flag)
 945                 PMD_DRV_LOG(DEBUG, "Tunnel parsing capability is disabled, flags : %#x\n",
 946                             bp->tunnel_disable_flag);
 947 unlock:
 948         HWRM_UNLOCK();
 949
 950         return rc;
 951 }
 952
 953 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 954 {
 955         int rc;
 956
 957         rc = __bnxt_hwrm_func_qcaps(bp);
 958         if (rc == -ENOMEM)
 959                 return rc;
 960
 961         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 962                 rc = bnxt_alloc_ctx_mem(bp);
 963                 if (rc)
 964                         return rc;
 965
 966                 /* On older FW,
 967                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 968                  * But the error can be ignored. Return success.
 969                  */
 970                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 971                 if (!rc)
 972                         bp->flags |= BNXT_FLAG_NEW_RM;
 973         }
 974
 975         return 0;
 976 }
 977
 978 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 979 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 980 {
 981         int rc = 0;
 982         uint32_t flags;
 983         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 984         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 985
 986         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 987
 988         req.target_id = rte_cpu_to_le_16(0xffff);
 989
 990         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 991
 992         HWRM_CHECK_RESULT();
 993
 994         flags = rte_le_to_cpu_32(resp->flags);
 995
 996         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 997                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 998                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 999         }
1000
1001         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
1002                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1003
1004         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1005                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1006
1007         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP) {
1008                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_VLAN_RX_STRIP;
1009                 PMD_DRV_LOG(DEBUG, "Rx VLAN strip capability enabled\n");
1010         }
1011
1012         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1013
1014         HWRM_UNLOCK();
1015
1016         return rc;
1017 }
1018
1019 int bnxt_hwrm_func_reset(struct bnxt *bp)
1020 {
1021         int rc = 0;
1022         struct hwrm_func_reset_input req = {.req_type = 0 };
1023         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1024
1025         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1026
1027         req.enables = rte_cpu_to_le_32(0);
1028
1029         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1030
1031         HWRM_CHECK_RESULT();
1032         HWRM_UNLOCK();
1033
1034         return rc;
1035 }
1036
1037 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1038 {
1039         int rc;
1040         uint32_t flags = 0;
1041         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1042         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1043
1044         if (bp->flags & BNXT_FLAG_REGISTERED)
1045                 return 0;
1046
1047         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1048                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1049         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1050                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1051
1052         /* PFs and trusted VFs should indicate the support of the
1053          * Master capability on non Stingray platform
1054          */
1055         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1056                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1057
1058         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1059         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1060                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1061         req.ver_maj_8b = RTE_VER_YEAR;
1062         req.ver_min_8b = RTE_VER_MONTH;
1063         req.ver_upd_8b = RTE_VER_MINOR;
1064
1065         if (BNXT_PF(bp)) {
1066                 req.enables |= rte_cpu_to_le_32(
1067                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1068                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1069                        RTE_MIN(sizeof(req.vf_req_fwd),
1070                                sizeof(bp->pf->vf_req_fwd)));
1071         }
1072
1073         req.flags = rte_cpu_to_le_32(flags);
1074
1075         req.async_event_fwd[0] |=
1076                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1077                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1078                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1079                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1080                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1081         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1082                 req.async_event_fwd[0] |=
1083                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1084         req.async_event_fwd[1] |=
1085                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1086                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1087         if (BNXT_PF(bp))
1088                 req.async_event_fwd[1] |=
1089                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1090
1091         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1092                 req.async_event_fwd[1] |=
1093                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1094
1095         req.async_event_fwd[2] |=
1096                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST |
1097                                  ASYNC_CMPL_EVENT_ID_ERROR_REPORT);
1098
1099         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1100
1101         HWRM_CHECK_RESULT();
1102
1103         flags = rte_le_to_cpu_32(resp->flags);
1104         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1105                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1106
1107         HWRM_UNLOCK();
1108
1109         bp->flags |= BNXT_FLAG_REGISTERED;
1110
1111         return rc;
1112 }
1113
1114 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1115 {
1116         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1117                 return 0;
1118
1119         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1120 }
1121
1122 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1123 {
1124         int rc;
1125         uint32_t flags = 0;
1126         uint32_t enables;
1127         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1128         struct hwrm_func_vf_cfg_input req = {0};
1129
1130         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1131
1132         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1133                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1134                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1135                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1136                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1137
1138         if (BNXT_HAS_RING_GRPS(bp)) {
1139                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1140                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1141         }
1142
1143         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1144         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1145                                             AGG_RING_MULTIPLIER);
1146         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1147         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1148                                               bp->tx_nr_rings +
1149                                               BNXT_NUM_ASYNC_CPR(bp));
1150         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1151         if (bp->vf_resv_strategy ==
1152             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1153                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1154                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1155                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1156                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1157                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1158                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1159         } else if (bp->vf_resv_strategy ==
1160                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1161                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1162                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1163         }
1164
1165         if (test)
1166                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1167                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1168                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1169                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1170                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1171                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1172
1173         if (test && BNXT_HAS_RING_GRPS(bp))
1174                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1175
1176         req.flags = rte_cpu_to_le_32(flags);
1177         req.enables |= rte_cpu_to_le_32(enables);
1178
1179         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1180
1181         if (test)
1182                 HWRM_CHECK_RESULT_SILENT();
1183         else
1184                 HWRM_CHECK_RESULT();
1185
1186         HWRM_UNLOCK();
1187         return rc;
1188 }
1189
1190 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1191 {
1192         int rc;
1193         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1194         struct hwrm_func_resource_qcaps_input req = {0};
1195
1196         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1197         req.fid = rte_cpu_to_le_16(0xffff);
1198
1199         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1200
1201         HWRM_CHECK_RESULT_SILENT();
1202
1203         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1204         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1205         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1206         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1207         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1208         /* func_resource_qcaps does not return max_rx_em_flows.
1209          * So use the value provided by func_qcaps.
1210          */
1211         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1212         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1213                 bp->max_l2_ctx += bp->max_rx_em_flows;
1214         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1215         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1216         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1217         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1218         if (bp->vf_resv_strategy >
1219             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1220                 bp->vf_resv_strategy =
1221                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1222
1223         HWRM_UNLOCK();
1224         return rc;
1225 }
1226
1227 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1228 {
1229         int rc = 0;
1230         struct hwrm_ver_get_input req = {.req_type = 0 };
1231         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1232         uint32_t fw_version;
1233         uint16_t max_resp_len;
1234         char type[RTE_MEMZONE_NAMESIZE];
1235         uint32_t dev_caps_cfg;
1236
1237         bp->max_req_len = HWRM_MAX_REQ_LEN;
1238         bp->hwrm_cmd_timeout = timeout;
1239         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1240
1241         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1242         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1243         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1244
1245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1246
1247         if (bp->flags & BNXT_FLAG_FW_RESET)
1248                 HWRM_CHECK_RESULT_SILENT();
1249         else
1250                 HWRM_CHECK_RESULT();
1251
1252         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1253                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1254                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1255                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1256                 resp->hwrm_fw_rsvd_8b);
1257         bp->fw_ver = ((uint32_t)resp->hwrm_fw_maj_8b << 24) |
1258                      ((uint32_t)resp->hwrm_fw_min_8b << 16) |
1259                      ((uint32_t)resp->hwrm_fw_bld_8b << 8) |
1260                      resp->hwrm_fw_rsvd_8b;
1261         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1262                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1263
1264         fw_version = resp->hwrm_intf_maj_8b << 16;
1265         fw_version |= resp->hwrm_intf_min_8b << 8;
1266         fw_version |= resp->hwrm_intf_upd_8b;
1267         bp->hwrm_spec_code = fw_version;
1268
1269         /* def_req_timeout value is in milliseconds */
1270         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1271         /* convert timeout to usec */
1272         bp->hwrm_cmd_timeout *= 1000;
1273         if (!bp->hwrm_cmd_timeout)
1274                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1275
1276         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1277                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1278                 rc = -EINVAL;
1279                 goto error;
1280         }
1281
1282         if (bp->max_req_len > resp->max_req_win_len) {
1283                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1284                 rc = -EINVAL;
1285                 goto error;
1286         }
1287
1288         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1289
1290         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1291         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1292         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1293                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1294
1295         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1296         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1297
1298         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1299         bp->max_resp_len = max_resp_len;
1300
1301         if ((dev_caps_cfg &
1302                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1303             (dev_caps_cfg &
1304              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1305                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1306                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1307         }
1308
1309         if (((dev_caps_cfg &
1310               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1311              (dev_caps_cfg &
1312               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1313             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1314                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1315                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1316                         bp->pdev->addr.devid, bp->pdev->addr.function);
1317
1318                 rte_free(bp->hwrm_short_cmd_req_addr);
1319
1320                 bp->hwrm_short_cmd_req_addr =
1321                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1322                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1323                         rc = -ENOMEM;
1324                         goto error;
1325                 }
1326                 bp->hwrm_short_cmd_req_dma_addr =
1327                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1328                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1329                         rte_free(bp->hwrm_short_cmd_req_addr);
1330                         PMD_DRV_LOG(ERR,
1331                                 "Unable to map buffer to physical memory.\n");
1332                         rc = -ENOMEM;
1333                         goto error;
1334                 }
1335         }
1336         if (dev_caps_cfg &
1337             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1338                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1339                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1340         }
1341         if (dev_caps_cfg &
1342             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1343                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1344         if (dev_caps_cfg &
1345             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1346                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1347                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1348         }
1349
1350         if (dev_caps_cfg &
1351             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1352                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1353                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1354         }
1355
1356         if (dev_caps_cfg &
1357             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
1358                 PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
1359                 bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
1360         }
1361
1362 error:
1363         HWRM_UNLOCK();
1364         return rc;
1365 }
1366
1367 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp)
1368 {
1369         int rc;
1370         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1371         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1372
1373         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1374                 return 0;
1375
1376         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1377
1378         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1379
1380         HWRM_CHECK_RESULT();
1381         HWRM_UNLOCK();
1382
1383         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1384                     bp->eth_dev->data->port_id);
1385
1386         return rc;
1387 }
1388
1389 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1390 {
1391         int rc = 0;
1392         struct hwrm_port_phy_cfg_input req = {0};
1393         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1394         uint32_t enables = 0;
1395
1396         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1397
1398         if (conf->link_up) {
1399                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1400                 if (bp->link_info->auto_mode && conf->link_speed) {
1401                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1402                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1403                 }
1404
1405                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1406                 /*
1407                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1408                  * any auto mode, even "none".
1409                  */
1410                 if (!conf->link_speed) {
1411                         /* No speeds specified. Enable AutoNeg - all speeds */
1412                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1413                         req.auto_mode =
1414                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1415                 } else {
1416                         if (bp->link_info->link_signal_mode) {
1417                                 enables |=
1418                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1419                                 req.force_pam4_link_speed =
1420                                         rte_cpu_to_le_16(conf->link_speed);
1421                         } else {
1422                                 req.force_link_speed =
1423                                         rte_cpu_to_le_16(conf->link_speed);
1424                         }
1425                 }
1426                 /* AutoNeg - Advertise speeds specified. */
1427                 if ((conf->auto_link_speed_mask || conf->auto_pam4_link_speed_mask) &&
1428                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1429                         req.auto_mode =
1430                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1431                         if (conf->auto_pam4_link_speed_mask) {
1432                                 enables |=
1433                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1434                                 req.auto_link_pam4_speed_mask =
1435                                 rte_cpu_to_le_16(conf->auto_pam4_link_speed_mask);
1436                         }
1437                         if (conf->auto_link_speed_mask) {
1438                                 enables |=
1439                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1440                                 req.auto_link_speed_mask =
1441                                 rte_cpu_to_le_16(conf->auto_link_speed_mask);
1442                         }
1443                 }
1444                 if (conf->auto_link_speed &&
1445                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1446                         enables |=
1447                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1448
1449                 req.auto_duplex = conf->duplex;
1450                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1451                 req.auto_pause = conf->auto_pause;
1452                 req.force_pause = conf->force_pause;
1453                 /* Set force_pause if there is no auto or if there is a force */
1454                 if (req.auto_pause && !req.force_pause)
1455                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1456                 else
1457                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1458
1459                 req.enables = rte_cpu_to_le_32(enables);
1460         } else {
1461                 req.flags =
1462                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1463                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1464         }
1465
1466         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1467
1468         HWRM_CHECK_RESULT();
1469         HWRM_UNLOCK();
1470
1471         return rc;
1472 }
1473
1474 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1475                                    struct bnxt_link_info *link_info)
1476 {
1477         int rc = 0;
1478         struct hwrm_port_phy_qcfg_input req = {0};
1479         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1480
1481         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1482
1483         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1484
1485         HWRM_CHECK_RESULT();
1486
1487         link_info->phy_link_status = resp->link;
1488         link_info->link_up =
1489                 (link_info->phy_link_status ==
1490                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1491         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1492         link_info->duplex = resp->duplex_cfg;
1493         link_info->pause = resp->pause;
1494         link_info->auto_pause = resp->auto_pause;
1495         link_info->force_pause = resp->force_pause;
1496         link_info->auto_mode = resp->auto_mode;
1497         link_info->phy_type = resp->phy_type;
1498         link_info->media_type = resp->media_type;
1499
1500         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1501         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1502         link_info->auto_link_speed_mask = rte_le_to_cpu_16(resp->auto_link_speed_mask);
1503         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1504         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1505         link_info->phy_ver[0] = resp->phy_maj;
1506         link_info->phy_ver[1] = resp->phy_min;
1507         link_info->phy_ver[2] = resp->phy_bld;
1508         link_info->link_signal_mode =
1509                 resp->active_fec_signal_mode & HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK;
1510         link_info->force_pam4_link_speed =
1511                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1512         link_info->support_pam4_speeds =
1513                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1514         link_info->auto_pam4_link_speed_mask =
1515                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1516         link_info->module_status = resp->module_status;
1517         HWRM_UNLOCK();
1518
1519         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1520                     link_info->link_speed, link_info->auto_mode,
1521                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1522                     link_info->support_speeds, link_info->force_link_speed);
1523         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1524                     link_info->link_signal_mode,
1525                     link_info->auto_pam4_link_speed_mask,
1526                     link_info->support_pam4_speeds,
1527                     link_info->force_pam4_link_speed);
1528         return rc;
1529 }
1530
1531 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1532 {
1533         int rc = 0;
1534         struct hwrm_port_phy_qcaps_input req = {0};
1535         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1536         struct bnxt_link_info *link_info = bp->link_info;
1537
1538         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1539                 return 0;
1540
1541         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1542
1543         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1544
1545         HWRM_CHECK_RESULT_SILENT();
1546
1547         bp->port_cnt = resp->port_cnt;
1548         if (resp->supported_speeds_auto_mode)
1549                 link_info->support_auto_speeds =
1550                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1551         if (resp->supported_pam4_speeds_auto_mode)
1552                 link_info->support_pam4_auto_speeds =
1553                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1554
1555         HWRM_UNLOCK();
1556
1557         /* Older firmware does not have supported_auto_speeds, so assume
1558          * that all supported speeds can be autonegotiated.
1559          */
1560         if (link_info->auto_link_speed_mask && !link_info->support_auto_speeds)
1561                 link_info->support_auto_speeds = link_info->support_speeds;
1562
1563         return 0;
1564 }
1565
1566 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1567 {
1568         int i = 0;
1569
1570         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1571                 if (bp->tx_cos_queue[i].profile ==
1572                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1573                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1574                         return true;
1575                 }
1576         }
1577         return false;
1578 }
1579
1580 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1581 {
1582         int i = 0;
1583
1584         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1585                 if (bp->tx_cos_queue[i].profile !=
1586                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1587                     bp->tx_cos_queue[i].id !=
1588                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1589                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1590                         break;
1591                 }
1592         }
1593 }
1594
1595 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1596 {
1597         int rc = 0;
1598         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1599         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1600         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1601         int i;
1602
1603 get_rx_info:
1604         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1605
1606         req.flags = rte_cpu_to_le_32(dir);
1607         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1608         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1609             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1610                 req.drv_qmap_cap =
1611                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1612         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1613
1614         HWRM_CHECK_RESULT();
1615
1616         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1617                 GET_TX_QUEUE_INFO(0);
1618                 GET_TX_QUEUE_INFO(1);
1619                 GET_TX_QUEUE_INFO(2);
1620                 GET_TX_QUEUE_INFO(3);
1621                 GET_TX_QUEUE_INFO(4);
1622                 GET_TX_QUEUE_INFO(5);
1623                 GET_TX_QUEUE_INFO(6);
1624                 GET_TX_QUEUE_INFO(7);
1625         } else  {
1626                 GET_RX_QUEUE_INFO(0);
1627                 GET_RX_QUEUE_INFO(1);
1628                 GET_RX_QUEUE_INFO(2);
1629                 GET_RX_QUEUE_INFO(3);
1630                 GET_RX_QUEUE_INFO(4);
1631                 GET_RX_QUEUE_INFO(5);
1632                 GET_RX_QUEUE_INFO(6);
1633                 GET_RX_QUEUE_INFO(7);
1634         }
1635
1636         HWRM_UNLOCK();
1637
1638         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1639                 goto done;
1640
1641         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1642                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1643         } else {
1644                 int j;
1645
1646                 /* iterate and find the COSq profile to use for Tx */
1647                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1648                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1649                                 if (bp->tx_cos_queue[i].id != 0xff)
1650                                         bp->tx_cosq_id[j++] =
1651                                                 bp->tx_cos_queue[i].id;
1652                         }
1653                 } else {
1654                         /* When CoS classification is disabled, for normal NIC
1655                          * operations, ideally we should look to use LOSSY.
1656                          * If not found, fallback to the first valid profile
1657                          */
1658                         if (!bnxt_find_lossy_profile(bp))
1659                                 bnxt_find_first_valid_profile(bp);
1660
1661                 }
1662         }
1663
1664         bp->max_tc = resp->max_configurable_queues;
1665         bp->max_lltc = resp->max_configurable_lossless_queues;
1666         if (bp->max_tc > BNXT_MAX_QUEUE)
1667                 bp->max_tc = BNXT_MAX_QUEUE;
1668         bp->max_q = bp->max_tc;
1669
1670         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1671                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1672                 goto get_rx_info;
1673         }
1674
1675 done:
1676         return rc;
1677 }
1678
1679 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1680                          struct bnxt_ring *ring,
1681                          uint32_t ring_type, uint32_t map_index,
1682                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1683                          uint16_t tx_cosq_id)
1684 {
1685         int rc = 0;
1686         uint32_t enables = 0;
1687         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1688         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1689         struct rte_mempool *mb_pool;
1690         uint16_t rx_buf_size;
1691
1692         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1693
1694         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1695         req.fbo = rte_cpu_to_le_32(0);
1696         /* Association of ring index with doorbell index */
1697         req.logical_id = rte_cpu_to_le_16(map_index);
1698         req.length = rte_cpu_to_le_32(ring->ring_size);
1699
1700         switch (ring_type) {
1701         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1702                 req.ring_type = ring_type;
1703                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1704                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1705                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1706                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1707                         enables |=
1708                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1709                 break;
1710         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1711                 req.ring_type = ring_type;
1712                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1713                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1714                 if (BNXT_CHIP_P5(bp)) {
1715                         mb_pool = bp->rx_queues[0]->mb_pool;
1716                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1717                                       RTE_PKTMBUF_HEADROOM;
1718                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1719                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1720                         enables |=
1721                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1722                 }
1723                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1724                         enables |=
1725                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1726                 break;
1727         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1728                 req.ring_type = ring_type;
1729                 if (BNXT_HAS_NQ(bp)) {
1730                         /* Association of cp ring with nq */
1731                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1732                         enables |=
1733                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1734                 }
1735                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1736                 break;
1737         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1738                 req.ring_type = ring_type;
1739                 req.page_size = BNXT_PAGE_SHFT;
1740                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1741                 break;
1742         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1743                 req.ring_type = ring_type;
1744                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1745
1746                 mb_pool = bp->rx_queues[0]->mb_pool;
1747                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1748                               RTE_PKTMBUF_HEADROOM;
1749                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1750                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1751
1752                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1753                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1754                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1755                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1756                 break;
1757         default:
1758                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1759                         ring_type);
1760                 HWRM_UNLOCK();
1761                 return -EINVAL;
1762         }
1763         req.enables = rte_cpu_to_le_32(enables);
1764
1765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1766
1767         if (rc || resp->error_code) {
1768                 if (rc == 0 && resp->error_code)
1769                         rc = rte_le_to_cpu_16(resp->error_code);
1770                 switch (ring_type) {
1771                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1772                         PMD_DRV_LOG(ERR,
1773                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1774                         HWRM_UNLOCK();
1775                         return rc;
1776                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1777                         PMD_DRV_LOG(ERR,
1778                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1779                         HWRM_UNLOCK();
1780                         return rc;
1781                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1782                         PMD_DRV_LOG(ERR,
1783                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1784                                     rc);
1785                         HWRM_UNLOCK();
1786                         return rc;
1787                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1788                         PMD_DRV_LOG(ERR,
1789                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1790                         HWRM_UNLOCK();
1791                         return rc;
1792                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1793                         PMD_DRV_LOG(ERR,
1794                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1795                         HWRM_UNLOCK();
1796                         return rc;
1797                 default:
1798                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1799                         HWRM_UNLOCK();
1800                         return rc;
1801                 }
1802         }
1803
1804         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1805         HWRM_UNLOCK();
1806         return rc;
1807 }
1808
1809 int bnxt_hwrm_ring_free(struct bnxt *bp,
1810                         struct bnxt_ring *ring, uint32_t ring_type,
1811                         uint16_t cp_ring_id)
1812 {
1813         int rc;
1814         struct hwrm_ring_free_input req = {.req_type = 0 };
1815         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1816
1817         if (ring->fw_ring_id == INVALID_HW_RING_ID)
1818                 return -EINVAL;
1819
1820         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1821
1822         req.ring_type = ring_type;
1823         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1824         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1825
1826         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1827         ring->fw_ring_id = INVALID_HW_RING_ID;
1828
1829         if (rc || resp->error_code) {
1830                 if (rc == 0 && resp->error_code)
1831                         rc = rte_le_to_cpu_16(resp->error_code);
1832                 HWRM_UNLOCK();
1833
1834                 switch (ring_type) {
1835                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1836                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1837                                 rc);
1838                         return rc;
1839                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1840                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1841                                 rc);
1842                         return rc;
1843                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1844                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1845                                 rc);
1846                         return rc;
1847                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1848                         PMD_DRV_LOG(ERR,
1849                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1850                         return rc;
1851                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1852                         PMD_DRV_LOG(ERR,
1853                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1854                         return rc;
1855                 default:
1856                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1857                         return rc;
1858                 }
1859         }
1860         HWRM_UNLOCK();
1861         return 0;
1862 }
1863
1864 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1865 {
1866         int rc = 0;
1867         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1868         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1869
1870         /* Don't attempt to re-create the ring group if it is already created */
1871         if (bp->grp_info[idx].fw_grp_id != INVALID_HW_RING_ID)
1872                 return 0;
1873
1874         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1875
1876         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1877         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1878         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1879         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1880
1881         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1882
1883         HWRM_CHECK_RESULT();
1884
1885         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1886
1887         HWRM_UNLOCK();
1888
1889         return rc;
1890 }
1891
1892 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1893 {
1894         int rc;
1895         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1896         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1897
1898         if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1899                 return 0;
1900
1901         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1902
1903         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1904
1905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1906
1907         HWRM_CHECK_RESULT();
1908         HWRM_UNLOCK();
1909
1910         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1911         return rc;
1912 }
1913
1914 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1915 {
1916         int rc = 0;
1917         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1918         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1919
1920         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1921                 return rc;
1922
1923         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1924
1925         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1926
1927         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1928
1929         HWRM_CHECK_RESULT();
1930         HWRM_UNLOCK();
1931
1932         return rc;
1933 }
1934
1935 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1936 {
1937         int rc;
1938         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1939         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1940
1941         if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE)
1942                 return 0;
1943
1944         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1945
1946         req.update_period_ms = rte_cpu_to_le_32(0);
1947
1948         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1949
1950         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1951
1952         HWRM_CHECK_RESULT();
1953
1954         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1955
1956         HWRM_UNLOCK();
1957
1958         return rc;
1959 }
1960
1961 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1962 {
1963         int rc;
1964         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1965         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1966
1967         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1968                 return 0;
1969
1970         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1971
1972         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1973
1974         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1975
1976         HWRM_CHECK_RESULT();
1977         HWRM_UNLOCK();
1978
1979         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1980
1981         return rc;
1982 }
1983
1984 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1985 {
1986         int rc = 0, i, j;
1987         struct hwrm_vnic_alloc_input req = { 0 };
1988         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1989
1990         if (!BNXT_HAS_RING_GRPS(bp))
1991                 goto skip_ring_grps;
1992
1993         /* map ring groups to this vnic */
1994         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1995                 vnic->start_grp_id, vnic->end_grp_id);
1996         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1997                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1998
1999         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
2000         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
2001         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
2002         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
2003
2004 skip_ring_grps:
2005         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
2006         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
2007
2008         if (vnic->func_default)
2009                 req.flags =
2010                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
2011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2012
2013         HWRM_CHECK_RESULT();
2014
2015         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
2016         HWRM_UNLOCK();
2017         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2018         return rc;
2019 }
2020
2021 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
2022                                         struct bnxt_vnic_info *vnic,
2023                                         struct bnxt_plcmodes_cfg *pmode)
2024 {
2025         int rc = 0;
2026         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2027         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2028
2029         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2030
2031         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2032
2033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2034
2035         HWRM_CHECK_RESULT();
2036
2037         pmode->flags = rte_le_to_cpu_32(resp->flags);
2038         /* dflt_vnic bit doesn't exist in the _cfg command */
2039         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2040         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2041         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2042         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2043
2044         HWRM_UNLOCK();
2045
2046         return rc;
2047 }
2048
2049 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2050                                        struct bnxt_vnic_info *vnic,
2051                                        struct bnxt_plcmodes_cfg *pmode)
2052 {
2053         int rc = 0;
2054         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2055         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2056
2057         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2058                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2059                 return rc;
2060         }
2061
2062         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2063
2064         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2065         req.flags = rte_cpu_to_le_32(pmode->flags);
2066         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2067         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2068         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2069         req.enables = rte_cpu_to_le_32(
2070             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2071             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2072             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2073         );
2074
2075         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2076
2077         HWRM_CHECK_RESULT();
2078         HWRM_UNLOCK();
2079
2080         return rc;
2081 }
2082
2083 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2084 {
2085         int rc = 0;
2086         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2087         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2088         struct bnxt_plcmodes_cfg pmodes = { 0 };
2089         uint32_t ctx_enable_flag = 0;
2090         uint32_t enables = 0;
2091
2092         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2093                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2094                 return rc;
2095         }
2096
2097         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2098         if (rc)
2099                 return rc;
2100
2101         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2102
2103         if (BNXT_CHIP_P5(bp)) {
2104                 int dflt_rxq = vnic->start_grp_id;
2105                 struct bnxt_rx_ring_info *rxr;
2106                 struct bnxt_cp_ring_info *cpr;
2107                 struct bnxt_rx_queue *rxq;
2108                 int i;
2109
2110                 /*
2111                  * The first active receive ring is used as the VNIC
2112                  * default receive ring. If there are no active receive
2113                  * rings (all corresponding receive queues are stopped),
2114                  * the first receive ring is used.
2115                  */
2116                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2117                         rxq = bp->eth_dev->data->rx_queues[i];
2118                         if (rxq->rx_started) {
2119                                 dflt_rxq = i;
2120                                 break;
2121                         }
2122                 }
2123
2124                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2125                 rxr = rxq->rx_ring;
2126                 cpr = rxq->cp_ring;
2127
2128                 req.default_rx_ring_id =
2129                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2130                 req.default_cmpl_ring_id =
2131                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2132                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2133                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2134                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2135                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2136                         req.rx_csum_v2_mode =
2137                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2138                 }
2139                 goto config_mru;
2140         }
2141
2142         /* Only RSS support for now TBD: COS & LB */
2143         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2144         if (vnic->lb_rule != 0xffff)
2145                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2146         if (vnic->cos_rule != 0xffff)
2147                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2148         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2149                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2150                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2151         }
2152         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2153                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2154                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2155         }
2156
2157         enables |= ctx_enable_flag;
2158         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2159         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2160         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2161         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2162
2163 config_mru:
2164         req.enables = rte_cpu_to_le_32(enables);
2165         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2166         req.mru = rte_cpu_to_le_16(vnic->mru);
2167         /* Configure default VNIC only once. */
2168         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2169                 req.flags |=
2170                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2171                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2172         }
2173         if (vnic->vlan_strip)
2174                 req.flags |=
2175                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2176         if (vnic->bd_stall)
2177                 req.flags |=
2178                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2179         if (vnic->rss_dflt_cr)
2180                 req.flags |= rte_cpu_to_le_32(
2181                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2182
2183         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2184
2185         HWRM_CHECK_RESULT();
2186         HWRM_UNLOCK();
2187
2188         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2189
2190         return rc;
2191 }
2192
2193 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2194                 int16_t fw_vf_id)
2195 {
2196         int rc = 0;
2197         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2198         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2199
2200         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2201                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2202                 return rc;
2203         }
2204         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2205
2206         req.enables =
2207                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2208         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2209         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2210
2211         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2212
2213         HWRM_CHECK_RESULT();
2214
2215         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2216         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2217         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2218         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2219         vnic->mru = rte_le_to_cpu_16(resp->mru);
2220         vnic->func_default = rte_le_to_cpu_32(
2221                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2222         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2223                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2224         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2225                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2226         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2227                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2228
2229         HWRM_UNLOCK();
2230
2231         return rc;
2232 }
2233
2234 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2235                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2236 {
2237         int rc = 0;
2238         uint16_t ctx_id;
2239         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2240         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2241                                                 bp->hwrm_cmd_resp_addr;
2242
2243         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2244
2245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2246         HWRM_CHECK_RESULT();
2247
2248         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2249         if (!BNXT_HAS_RING_GRPS(bp))
2250                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2251         else if (ctx_idx == 0)
2252                 vnic->rss_rule = ctx_id;
2253
2254         HWRM_UNLOCK();
2255
2256         return rc;
2257 }
2258
2259 static
2260 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2261                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2262 {
2263         int rc = 0;
2264         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2265         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2266                                                 bp->hwrm_cmd_resp_addr;
2267
2268         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2269                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2270                 return rc;
2271         }
2272         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2273
2274         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2275
2276         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2277
2278         HWRM_CHECK_RESULT();
2279         HWRM_UNLOCK();
2280
2281         return rc;
2282 }
2283
2284 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2285 {
2286         int rc = 0;
2287
2288         if (BNXT_CHIP_P5(bp)) {
2289                 int j;
2290
2291                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2292                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2293                                                       vnic,
2294                                                       vnic->fw_grp_ids[j]);
2295                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2296                 }
2297                 vnic->num_lb_ctxts = 0;
2298         } else {
2299                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2300                 vnic->rss_rule = INVALID_HW_RING_ID;
2301         }
2302
2303         return rc;
2304 }
2305
2306 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2307 {
2308         int rc = 0;
2309         struct hwrm_vnic_free_input req = {.req_type = 0 };
2310         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2311
2312         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2313                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2314                 return rc;
2315         }
2316
2317         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2318
2319         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2320
2321         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2322
2323         HWRM_CHECK_RESULT();
2324         HWRM_UNLOCK();
2325
2326         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2327         /* Configure default VNIC again if necessary. */
2328         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2329                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2330
2331         return rc;
2332 }
2333
2334 static int
2335 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2336 {
2337         int i;
2338         int rc = 0;
2339         int nr_ctxs = vnic->num_lb_ctxts;
2340         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2341         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2342
2343         for (i = 0; i < nr_ctxs; i++) {
2344                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2345
2346                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2347                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2348                 req.hash_mode_flags = vnic->hash_mode;
2349
2350                 req.hash_key_tbl_addr =
2351                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2352
2353                 req.ring_grp_tbl_addr =
2354                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2355                                          i * HW_HASH_INDEX_SIZE);
2356                 req.ring_table_pair_index = i;
2357                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2358
2359                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2360                                             BNXT_USE_CHIMP_MB);
2361
2362                 HWRM_CHECK_RESULT();
2363                 HWRM_UNLOCK();
2364         }
2365
2366         return rc;
2367 }
2368
2369 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2370                            struct bnxt_vnic_info *vnic)
2371 {
2372         int rc = 0;
2373         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2374         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2375
2376         if (!vnic->rss_table)
2377                 return 0;
2378
2379         if (BNXT_CHIP_P5(bp))
2380                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2381
2382         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2383
2384         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2385         req.hash_mode_flags = vnic->hash_mode;
2386
2387         req.ring_grp_tbl_addr =
2388             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2389         req.hash_key_tbl_addr =
2390             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2391         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2392         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2393
2394         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2395
2396         HWRM_CHECK_RESULT();
2397         HWRM_UNLOCK();
2398
2399         return rc;
2400 }
2401
2402 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2403                         struct bnxt_vnic_info *vnic)
2404 {
2405         int rc = 0;
2406         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2407         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2408         uint16_t size;
2409
2410         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2411                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2412                 return rc;
2413         }
2414
2415         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2416
2417         req.flags = rte_cpu_to_le_32(
2418                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2419
2420         req.enables = rte_cpu_to_le_32(
2421                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2422
2423         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2424         size -= RTE_PKTMBUF_HEADROOM;
2425         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2426
2427         req.jumbo_thresh = rte_cpu_to_le_16(size);
2428         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2429
2430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2431
2432         HWRM_CHECK_RESULT();
2433         HWRM_UNLOCK();
2434
2435         return rc;
2436 }
2437
2438 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2439                         struct bnxt_vnic_info *vnic, bool enable)
2440 {
2441         int rc = 0;
2442         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2443         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2444
2445         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2446                 if (enable)
2447                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2448                 return -ENOTSUP;
2449         }
2450
2451         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2452                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2453                 return 0;
2454         }
2455
2456         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2457
2458         if (enable) {
2459                 req.enables = rte_cpu_to_le_32(
2460                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2461                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2462                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2463                 req.flags = rte_cpu_to_le_32(
2464                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2465                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2466                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2467                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2468                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2469                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2470                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2471                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2472                 req.min_agg_len = rte_cpu_to_le_32(512);
2473         }
2474         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2475
2476         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2477
2478         HWRM_CHECK_RESULT();
2479         HWRM_UNLOCK();
2480
2481         return rc;
2482 }
2483
2484 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2485 {
2486         struct hwrm_func_cfg_input req = {0};
2487         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2488         int rc;
2489
2490         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2491         req.enables = rte_cpu_to_le_32(
2492                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2493         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2494         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2495
2496         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2497
2498         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2499         HWRM_CHECK_RESULT();
2500         HWRM_UNLOCK();
2501
2502         bp->pf->vf_info[vf].random_mac = false;
2503
2504         return rc;
2505 }
2506
2507 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2508                                   uint64_t *dropped)
2509 {
2510         int rc = 0;
2511         struct hwrm_func_qstats_input req = {.req_type = 0};
2512         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2513
2514         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2515
2516         req.fid = rte_cpu_to_le_16(fid);
2517
2518         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2519
2520         HWRM_CHECK_RESULT();
2521
2522         if (dropped)
2523                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2524
2525         HWRM_UNLOCK();
2526
2527         return rc;
2528 }
2529
2530 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2531                           struct rte_eth_stats *stats,
2532                           struct hwrm_func_qstats_output *func_qstats)
2533 {
2534         int rc = 0;
2535         struct hwrm_func_qstats_input req = {.req_type = 0};
2536         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2537
2538         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2539
2540         req.fid = rte_cpu_to_le_16(fid);
2541
2542         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2543
2544         HWRM_CHECK_RESULT();
2545         if (func_qstats)
2546                 memcpy(func_qstats, resp,
2547                        sizeof(struct hwrm_func_qstats_output));
2548
2549         if (!stats)
2550                 goto exit;
2551
2552         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2553         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2554         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2555         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2556         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2557         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2558
2559         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2560         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2561         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2562         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2563         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2564         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2565
2566         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2567         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2568         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2569
2570 exit:
2571         HWRM_UNLOCK();
2572
2573         return rc;
2574 }
2575
2576 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2577 {
2578         int rc = 0;
2579         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2580         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2581
2582         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2583
2584         req.fid = rte_cpu_to_le_16(fid);
2585
2586         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2587
2588         HWRM_CHECK_RESULT();
2589         HWRM_UNLOCK();
2590
2591         return rc;
2592 }
2593
2594 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2595 {
2596         unsigned int i;
2597         int rc = 0;
2598
2599         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2600                 struct bnxt_tx_queue *txq;
2601                 struct bnxt_rx_queue *rxq;
2602                 struct bnxt_cp_ring_info *cpr;
2603
2604                 if (i >= bp->rx_cp_nr_rings) {
2605                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2606                         cpr = txq->cp_ring;
2607                 } else {
2608                         rxq = bp->rx_queues[i];
2609                         cpr = rxq->cp_ring;
2610                 }
2611
2612                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2613                 if (rc)
2614                         return rc;
2615         }
2616         return 0;
2617 }
2618
2619 static int
2620 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2621 {
2622         int rc;
2623         unsigned int i;
2624         struct bnxt_cp_ring_info *cpr;
2625
2626         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2627
2628                 cpr = bp->rx_queues[i]->cp_ring;
2629                 if (BNXT_HAS_RING_GRPS(bp))
2630                         bp->grp_info[i].fw_stats_ctx = -1;
2631                 if (cpr == NULL)
2632                         continue;
2633                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2634                 if (rc)
2635                         return rc;
2636         }
2637
2638         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2639                 cpr = bp->tx_queues[i]->cp_ring;
2640                 if (cpr == NULL)
2641                         continue;
2642                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2643                 if (rc)
2644                         return rc;
2645         }
2646
2647         return 0;
2648 }
2649
2650 static int
2651 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2652 {
2653         uint16_t idx;
2654         uint32_t rc = 0;
2655
2656         if (!BNXT_HAS_RING_GRPS(bp))
2657                 return 0;
2658
2659         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2660
2661                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2662                         continue;
2663
2664                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2665
2666                 if (rc)
2667                         return rc;
2668         }
2669         return rc;
2670 }
2671
2672 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2673 {
2674         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2675
2676         bnxt_hwrm_ring_free(bp, cp_ring,
2677                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2678                             INVALID_HW_RING_ID);
2679         memset(cpr->cp_desc_ring, 0,
2680                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2681         cpr->cp_raw_cons = 0;
2682 }
2683
2684 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2685 {
2686         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2687
2688         bnxt_hwrm_ring_free(bp, cp_ring,
2689                             HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2690                             INVALID_HW_RING_ID);
2691         memset(cpr->cp_desc_ring, 0,
2692                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2693         cpr->cp_raw_cons = 0;
2694 }
2695
2696 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2697 {
2698         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2699         struct bnxt_rx_ring_info *rxr = rxq ? rxq->rx_ring : NULL;
2700         struct bnxt_ring *ring = rxr ? rxr->rx_ring_struct : NULL;
2701         struct bnxt_cp_ring_info *cpr = rxq ? rxq->cp_ring : NULL;
2702
2703         if (BNXT_HAS_RING_GRPS(bp))
2704                 bnxt_hwrm_ring_grp_free(bp, queue_index);
2705
2706         if (ring != NULL && cpr != NULL)
2707                 bnxt_hwrm_ring_free(bp, ring,
2708                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2709                                     cpr->cp_ring_struct->fw_ring_id);
2710         if (BNXT_HAS_RING_GRPS(bp))
2711                 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2712
2713         /* Check agg ring struct explicitly.
2714          * bnxt_need_agg_ring() returns the current state of offload flags,
2715          * but we may have to deal with agg ring struct before the offload
2716          * flags are updated.
2717          */
2718         if (!bnxt_need_agg_ring(bp->eth_dev) ||
2719             (rxr && rxr->ag_ring_struct == NULL))
2720                 goto no_agg;
2721
2722         ring = rxr ? rxr->ag_ring_struct : NULL;
2723         if (ring != NULL && cpr != NULL) {
2724                 bnxt_hwrm_ring_free(bp, ring,
2725                                     BNXT_CHIP_P5(bp) ?
2726                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2727                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2728                                     cpr->cp_ring_struct->fw_ring_id);
2729         }
2730         if (BNXT_HAS_RING_GRPS(bp))
2731                 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2732
2733 no_agg:
2734         if (cpr != NULL) {
2735                 bnxt_hwrm_stat_ctx_free(bp, cpr);
2736                 bnxt_free_cp_ring(bp, cpr);
2737         }
2738
2739         if (BNXT_HAS_RING_GRPS(bp))
2740                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2741 }
2742
2743 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2744 {
2745         int rc;
2746         struct hwrm_ring_reset_input req = {.req_type = 0 };
2747         struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2748
2749         HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2750
2751         req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2752         req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2753         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2754
2755         HWRM_CHECK_RESULT();
2756
2757         HWRM_UNLOCK();
2758
2759         return rc;
2760 }
2761
2762 static int
2763 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2764 {
2765         unsigned int i;
2766
2767         for (i = 0; i < bp->tx_cp_nr_rings; i++)
2768                 bnxt_free_hwrm_tx_ring(bp, i);
2769
2770         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2771                 bnxt_free_hwrm_rx_ring(bp, i);
2772
2773         return 0;
2774 }
2775
2776 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2777 {
2778         uint16_t i;
2779         uint32_t rc = 0;
2780
2781         if (!BNXT_HAS_RING_GRPS(bp))
2782                 return 0;
2783
2784         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2785                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2786                 if (rc)
2787                         return rc;
2788         }
2789         return rc;
2790 }
2791
2792 /*
2793  * HWRM utility functions
2794  */
2795
2796 void bnxt_free_hwrm_resources(struct bnxt *bp)
2797 {
2798         /* Release memzone */
2799         rte_free(bp->hwrm_cmd_resp_addr);
2800         rte_free(bp->hwrm_short_cmd_req_addr);
2801         bp->hwrm_cmd_resp_addr = NULL;
2802         bp->hwrm_short_cmd_req_addr = NULL;
2803         bp->hwrm_cmd_resp_dma_addr = 0;
2804         bp->hwrm_short_cmd_req_dma_addr = 0;
2805 }
2806
2807 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2808 {
2809         struct rte_pci_device *pdev = bp->pdev;
2810         char type[RTE_MEMZONE_NAMESIZE];
2811
2812         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2813                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2814         bp->max_resp_len = BNXT_PAGE_SIZE;
2815         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2816         if (bp->hwrm_cmd_resp_addr == NULL)
2817                 return -ENOMEM;
2818         bp->hwrm_cmd_resp_dma_addr =
2819                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2820         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2821                 PMD_DRV_LOG(ERR,
2822                         "unable to map response address to physical memory\n");
2823                 return -ENOMEM;
2824         }
2825         rte_spinlock_init(&bp->hwrm_lock);
2826
2827         return 0;
2828 }
2829
2830 int
2831 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2832 {
2833         int rc = 0;
2834
2835         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2836                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2837                 if (rc)
2838                         return rc;
2839         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2840                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2841                 if (rc)
2842                         return rc;
2843         }
2844
2845         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2846         return rc;
2847 }
2848
2849 static int
2850 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2851 {
2852         struct bnxt_filter_info *filter;
2853         int rc = 0;
2854
2855         STAILQ_FOREACH(filter, &vnic->filter, next) {
2856                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2857                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2858                 bnxt_free_filter(bp, filter);
2859         }
2860         return rc;
2861 }
2862
2863 static int
2864 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2865 {
2866         struct bnxt_filter_info *filter;
2867         struct rte_flow *flow;
2868         int rc = 0;
2869
2870         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2871                 flow = STAILQ_FIRST(&vnic->flow_list);
2872                 filter = flow->filter;
2873                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2874                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2875
2876                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2877                 rte_free(flow);
2878         }
2879         return rc;
2880 }
2881
2882 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2883 {
2884         struct bnxt_filter_info *filter;
2885         int rc = 0;
2886
2887         STAILQ_FOREACH(filter, &vnic->filter, next) {
2888                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2889                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2890                                                      filter);
2891                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2892                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2893                                                          filter);
2894                 else
2895                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2896                                                      filter);
2897                 if (rc)
2898                         break;
2899         }
2900         return rc;
2901 }
2902
2903 static void
2904 bnxt_free_tunnel_ports(struct bnxt *bp)
2905 {
2906         if (bp->vxlan_port_cnt)
2907                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2908                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2909
2910         if (bp->geneve_port_cnt)
2911                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2912                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2913 }
2914
2915 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2916 {
2917         int i;
2918
2919         if (bp->vnic_info == NULL)
2920                 return;
2921
2922         /*
2923          * Cleanup VNICs in reverse order, to make sure the L2 filter
2924          * from vnic0 is last to be cleaned up.
2925          */
2926         for (i = bp->max_vnics - 1; i >= 0; i--) {
2927                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2928
2929                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2930                         continue;
2931
2932                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2933
2934                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2935
2936                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2937
2938                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2939
2940                 bnxt_hwrm_vnic_free(bp, vnic);
2941
2942                 rte_free(vnic->fw_grp_ids);
2943         }
2944         /* Ring resources */
2945         bnxt_free_all_hwrm_rings(bp);
2946         bnxt_free_all_hwrm_ring_grps(bp);
2947         bnxt_free_all_hwrm_stat_ctxs(bp);
2948         bnxt_free_tunnel_ports(bp);
2949 }
2950
2951 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2952 {
2953         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2954
2955         if ((conf_link_speed & RTE_ETH_LINK_SPEED_FIXED) == RTE_ETH_LINK_SPEED_AUTONEG)
2956                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2957
2958         switch (conf_link_speed) {
2959         case RTE_ETH_LINK_SPEED_10M_HD:
2960         case RTE_ETH_LINK_SPEED_100M_HD:
2961                 /* FALLTHROUGH */
2962                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2963         }
2964         return hw_link_duplex;
2965 }
2966
2967 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2968 {
2969         return !conf_link;
2970 }
2971
2972 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2973                                           uint16_t pam4_link)
2974 {
2975         uint16_t eth_link_speed = 0;
2976
2977         if (conf_link_speed == RTE_ETH_LINK_SPEED_AUTONEG)
2978                 return RTE_ETH_LINK_SPEED_AUTONEG;
2979
2980         switch (conf_link_speed & ~RTE_ETH_LINK_SPEED_FIXED) {
2981         case RTE_ETH_LINK_SPEED_100M:
2982         case RTE_ETH_LINK_SPEED_100M_HD:
2983                 /* FALLTHROUGH */
2984                 eth_link_speed =
2985                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2986                 break;
2987         case RTE_ETH_LINK_SPEED_1G:
2988                 eth_link_speed =
2989                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2990                 break;
2991         case RTE_ETH_LINK_SPEED_2_5G:
2992                 eth_link_speed =
2993                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2994                 break;
2995         case RTE_ETH_LINK_SPEED_10G:
2996                 eth_link_speed =
2997                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2998                 break;
2999         case RTE_ETH_LINK_SPEED_20G:
3000                 eth_link_speed =
3001                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3002                 break;
3003         case RTE_ETH_LINK_SPEED_25G:
3004                 eth_link_speed =
3005                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3006                 break;
3007         case RTE_ETH_LINK_SPEED_40G:
3008                 eth_link_speed =
3009                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3010                 break;
3011         case RTE_ETH_LINK_SPEED_50G:
3012                 eth_link_speed = pam4_link ?
3013                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3014                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3015                 break;
3016         case RTE_ETH_LINK_SPEED_100G:
3017                 eth_link_speed = pam4_link ?
3018                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3019                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3020                 break;
3021         case RTE_ETH_LINK_SPEED_200G:
3022                 eth_link_speed =
3023                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3024                 break;
3025         default:
3026                 PMD_DRV_LOG(ERR,
3027                         "Unsupported link speed %d; default to AUTO\n",
3028                         conf_link_speed);
3029                 break;
3030         }
3031         return eth_link_speed;
3032 }
3033
3034 #define BNXT_SUPPORTED_SPEEDS (RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_100M_HD | \
3035                 RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_2_5G | \
3036                 RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_20G | RTE_ETH_LINK_SPEED_25G | \
3037                 RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_50G | \
3038                 RTE_ETH_LINK_SPEED_100G | RTE_ETH_LINK_SPEED_200G)
3039
3040 static int bnxt_validate_link_speed(struct bnxt *bp)
3041 {
3042         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3043         uint16_t port_id = bp->eth_dev->data->port_id;
3044         uint32_t link_speed_capa;
3045         uint32_t one_speed;
3046
3047         if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG)
3048                 return 0;
3049
3050         link_speed_capa = bnxt_get_speed_capabilities(bp);
3051
3052         if (link_speed & RTE_ETH_LINK_SPEED_FIXED) {
3053                 one_speed = link_speed & ~RTE_ETH_LINK_SPEED_FIXED;
3054
3055                 if (one_speed & (one_speed - 1)) {
3056                         PMD_DRV_LOG(ERR,
3057                                 "Invalid advertised speeds (%u) for port %u\n",
3058                                 link_speed, port_id);
3059                         return -EINVAL;
3060                 }
3061                 if ((one_speed & link_speed_capa) != one_speed) {
3062                         PMD_DRV_LOG(ERR,
3063                                 "Unsupported advertised speed (%u) for port %u\n",
3064                                 link_speed, port_id);
3065                         return -EINVAL;
3066                 }
3067         } else {
3068                 if (!(link_speed & link_speed_capa)) {
3069                         PMD_DRV_LOG(ERR,
3070                                 "Unsupported advertised speeds (%u) for port %u\n",
3071                                 link_speed, port_id);
3072                         return -EINVAL;
3073                 }
3074         }
3075         return 0;
3076 }
3077
3078 static uint16_t
3079 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3080 {
3081         uint16_t ret = 0;
3082
3083         if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG) {
3084                 if (bp->link_info->support_speeds)
3085                         return bp->link_info->support_speeds;
3086                 link_speed = BNXT_SUPPORTED_SPEEDS;
3087         }
3088
3089         if (link_speed & RTE_ETH_LINK_SPEED_100M)
3090                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3091         if (link_speed & RTE_ETH_LINK_SPEED_100M_HD)
3092                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3093         if (link_speed & RTE_ETH_LINK_SPEED_1G)
3094                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3095         if (link_speed & RTE_ETH_LINK_SPEED_2_5G)
3096                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3097         if (link_speed & RTE_ETH_LINK_SPEED_10G)
3098                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3099         if (link_speed & RTE_ETH_LINK_SPEED_20G)
3100                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3101         if (link_speed & RTE_ETH_LINK_SPEED_25G)
3102                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3103         if (link_speed & RTE_ETH_LINK_SPEED_40G)
3104                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3105         if (link_speed & RTE_ETH_LINK_SPEED_50G)
3106                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3107         if (link_speed & RTE_ETH_LINK_SPEED_100G)
3108                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3109         if (link_speed & RTE_ETH_LINK_SPEED_200G)
3110                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3111         return ret;
3112 }
3113
3114 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3115 {
3116         uint32_t eth_link_speed = RTE_ETH_SPEED_NUM_NONE;
3117
3118         switch (hw_link_speed) {
3119         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3120                 eth_link_speed = RTE_ETH_SPEED_NUM_100M;
3121                 break;
3122         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3123                 eth_link_speed = RTE_ETH_SPEED_NUM_1G;
3124                 break;
3125         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3126                 eth_link_speed = RTE_ETH_SPEED_NUM_2_5G;
3127                 break;
3128         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3129                 eth_link_speed = RTE_ETH_SPEED_NUM_10G;
3130                 break;
3131         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3132                 eth_link_speed = RTE_ETH_SPEED_NUM_20G;
3133                 break;
3134         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3135                 eth_link_speed = RTE_ETH_SPEED_NUM_25G;
3136                 break;
3137         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3138                 eth_link_speed = RTE_ETH_SPEED_NUM_40G;
3139                 break;
3140         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3141                 eth_link_speed = RTE_ETH_SPEED_NUM_50G;
3142                 break;
3143         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3144                 eth_link_speed = RTE_ETH_SPEED_NUM_100G;
3145                 break;
3146         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3147                 eth_link_speed = RTE_ETH_SPEED_NUM_200G;
3148                 break;
3149         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3150         default:
3151                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3152                         hw_link_speed);
3153                 break;
3154         }
3155         return eth_link_speed;
3156 }
3157
3158 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3159 {
3160         uint16_t eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3161
3162         switch (hw_link_duplex) {
3163         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3164         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3165                 /* FALLTHROUGH */
3166                 eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3167                 break;
3168         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3169                 eth_link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
3170                 break;
3171         default:
3172                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3173                         hw_link_duplex);
3174                 break;
3175         }
3176         return eth_link_duplex;
3177 }
3178
3179 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3180 {
3181         int rc = 0;
3182         struct bnxt_link_info *link_info = bp->link_info;
3183
3184         rc = bnxt_hwrm_port_phy_qcaps(bp);
3185         if (rc)
3186                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3187
3188         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3189         if (rc) {
3190                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3191                 goto exit;
3192         }
3193
3194         if (link_info->link_speed)
3195                 link->link_speed =
3196                         bnxt_parse_hw_link_speed(link_info->link_speed);
3197         else
3198                 link->link_speed = RTE_ETH_SPEED_NUM_NONE;
3199         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3200         link->link_status = link_info->link_up;
3201         link->link_autoneg = link_info->auto_mode ==
3202                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3203                 RTE_ETH_LINK_FIXED : RTE_ETH_LINK_AUTONEG;
3204 exit:
3205         return rc;
3206 }
3207
3208 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3209 {
3210         int rc = 0;
3211         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3212         struct bnxt_link_info link_req;
3213         uint16_t speed, autoneg;
3214
3215         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3216                 return 0;
3217
3218         rc = bnxt_validate_link_speed(bp);
3219         if (rc)
3220                 goto error;
3221
3222         memset(&link_req, 0, sizeof(link_req));
3223         link_req.link_up = link_up;
3224         if (!link_up)
3225                 goto port_phy_cfg;
3226
3227         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3228         if (BNXT_CHIP_P5(bp) &&
3229             dev_conf->link_speeds == RTE_ETH_LINK_SPEED_40G) {
3230                 /* 40G is not supported as part of media auto detect.
3231                  * The speed should be forced and autoneg disabled
3232                  * to configure 40G speed.
3233                  */
3234                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3235                 autoneg = 0;
3236         }
3237
3238         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3239         if (bp->link_info->auto_link_speed == 0 &&
3240             bp->link_info->link_signal_mode &&
3241             bp->link_info->auto_pam4_link_speed_mask == 0)
3242                 autoneg = 0;
3243
3244         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3245                                           bp->link_info->link_signal_mode);
3246         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3247         /* Autoneg can be done only when the FW allows. */
3248         if (autoneg == 1 &&
3249             (bp->link_info->support_auto_speeds || bp->link_info->support_pam4_auto_speeds)) {
3250                 link_req.phy_flags |=
3251                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3252                 link_req.auto_link_speed_mask =
3253                         bnxt_parse_eth_link_speed_mask(bp,
3254                                                        dev_conf->link_speeds);
3255                 link_req.auto_pam4_link_speed_mask =
3256                         bp->link_info->auto_pam4_link_speed_mask;
3257         } else {
3258                 if (bp->link_info->phy_type ==
3259                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3260                     bp->link_info->phy_type ==
3261                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3262                     bp->link_info->media_type ==
3263                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3264                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3265                         return -EINVAL;
3266                 }
3267
3268                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3269                 /* If user wants a particular speed try that first. */
3270                 if (speed)
3271                         link_req.link_speed = speed;
3272                 else if (bp->link_info->force_pam4_link_speed)
3273                         link_req.link_speed =
3274                                 bp->link_info->force_pam4_link_speed;
3275                 else if (bp->link_info->auto_pam4_link_speed_mask)
3276                         link_req.link_speed =
3277                                 bp->link_info->auto_pam4_link_speed_mask;
3278                 else if (bp->link_info->support_pam4_speeds)
3279                         link_req.link_speed =
3280                                 bp->link_info->support_pam4_speeds;
3281                 else if (bp->link_info->force_link_speed)
3282                         link_req.link_speed = bp->link_info->force_link_speed;
3283                 else
3284                         link_req.link_speed = bp->link_info->auto_link_speed;
3285                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3286                  * zero. Use the auto_link_speed.
3287                  */
3288                 if (bp->link_info->auto_link_speed != 0 &&
3289                     bp->link_info->auto_pam4_link_speed_mask == 0)
3290                         link_req.link_speed = bp->link_info->auto_link_speed;
3291         }
3292         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3293         link_req.auto_pause = bp->link_info->auto_pause;
3294         link_req.force_pause = bp->link_info->force_pause;
3295
3296 port_phy_cfg:
3297         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3298         if (rc) {
3299                 PMD_DRV_LOG(ERR,
3300                         "Set link config failed with rc %d\n", rc);
3301         }
3302
3303 error:
3304         return rc;
3305 }
3306
3307 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3308 {
3309         struct hwrm_func_qcfg_input req = {0};
3310         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3311         uint16_t flags;
3312         int rc = 0;
3313         bp->func_svif = BNXT_SVIF_INVALID;
3314         uint16_t svif_info;
3315
3316         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3317         req.fid = rte_cpu_to_le_16(0xffff);
3318
3319         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3320
3321         HWRM_CHECK_RESULT();
3322
3323         bp->vlan = rte_le_to_cpu_16(resp->vlan) & RTE_ETH_VLAN_ID_MAX;
3324
3325         svif_info = rte_le_to_cpu_16(resp->svif_info);
3326         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3327                 bp->func_svif = svif_info &
3328                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3329
3330         flags = rte_le_to_cpu_16(resp->flags);
3331         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3332                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3333
3334         if (BNXT_VF(bp) &&
3335             !BNXT_VF_IS_TRUSTED(bp) &&
3336             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3337                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3338                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3339         } else if (BNXT_VF(bp) &&
3340                    BNXT_VF_IS_TRUSTED(bp) &&
3341                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3342                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3343                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3344         }
3345
3346         if (mtu)
3347                 *mtu = rte_le_to_cpu_16(resp->admin_mtu);
3348
3349         switch (resp->port_partition_type) {
3350         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3351         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3352         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3353                 /* FALLTHROUGH */
3354                 bp->flags |= BNXT_FLAG_NPAR_PF;
3355                 break;
3356         default:
3357                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3358                 break;
3359         }
3360
3361         bp->legacy_db_size =
3362                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3363
3364         HWRM_UNLOCK();
3365
3366         return rc;
3367 }
3368
3369 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3370 {
3371         struct hwrm_func_qcfg_input req = {0};
3372         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3373         uint16_t flags;
3374         int rc;
3375
3376         if (!BNXT_VF_IS_TRUSTED(bp))
3377                 return 0;
3378
3379         if (!bp->parent)
3380                 return -EINVAL;
3381
3382         bp->parent->fid = BNXT_PF_FID_INVALID;
3383
3384         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3385
3386         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3387
3388         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3389
3390         HWRM_CHECK_RESULT_SILENT();
3391
3392         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3393         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3394         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3395         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3396
3397         flags = rte_le_to_cpu_16(resp->flags);
3398         /* check for the multi-root support */
3399         if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) {
3400                 bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN;
3401                 PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n");
3402         }
3403
3404         HWRM_UNLOCK();
3405
3406         return 0;
3407 }
3408
3409 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3410                                  uint16_t *vnic_id, uint16_t *svif)
3411 {
3412         struct hwrm_func_qcfg_input req = {0};
3413         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3414         uint16_t svif_info;
3415         int rc = 0;
3416
3417         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3418         req.fid = rte_cpu_to_le_16(fid);
3419
3420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3421
3422         HWRM_CHECK_RESULT();
3423
3424         if (vnic_id)
3425                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3426
3427         svif_info = rte_le_to_cpu_16(resp->svif_info);
3428         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3429                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3430
3431         HWRM_UNLOCK();
3432
3433         return rc;
3434 }
3435
3436 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3437 {
3438         struct hwrm_port_mac_qcfg_input req = {0};
3439         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3440         uint16_t port_svif_info;
3441         int rc;
3442
3443         bp->port_svif = BNXT_SVIF_INVALID;
3444
3445         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3446                 return 0;
3447
3448         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3449
3450         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3451
3452         HWRM_CHECK_RESULT_SILENT();
3453
3454         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3455         if (port_svif_info &
3456             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3457                 bp->port_svif = port_svif_info &
3458                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3459
3460         HWRM_UNLOCK();
3461
3462         return 0;
3463 }
3464
3465 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3466                                  struct bnxt_pf_resource_info *pf_resc)
3467 {
3468         struct hwrm_func_cfg_input req = {0};
3469         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3470         uint32_t enables;
3471         int rc;
3472
3473         enables = HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3474                   HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU |
3475                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3476                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3477                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3478                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3479                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3480                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3481                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3482                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3483
3484         if (BNXT_HAS_RING_GRPS(bp)) {
3485                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3486                 req.num_hw_ring_grps =
3487                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3488         } else if (BNXT_HAS_NQ(bp)) {
3489                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3490                 req.num_msix = rte_cpu_to_le_16(pf_resc->num_nq_rings);
3491         }
3492
3493         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3494         req.admin_mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3495         req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
3496         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3497         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3498         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3499         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3500         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3501         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3502         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3503         req.num_vnics = rte_cpu_to_le_16(pf_resc->num_vnics);
3504         req.fid = rte_cpu_to_le_16(0xffff);
3505         req.enables = rte_cpu_to_le_32(enables);
3506
3507         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3508
3509         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3510
3511         HWRM_CHECK_RESULT();
3512         HWRM_UNLOCK();
3513
3514         return rc;
3515 }
3516
3517 /* min values are the guaranteed resources and max values are subject
3518  * to availability. The strategy for now is to keep both min & max
3519  * values the same.
3520  */
3521 static void
3522 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3523                               struct hwrm_func_vf_resource_cfg_input *req,
3524                               int num_vfs)
3525 {
3526         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3527                                                (num_vfs + 1));
3528         req->min_rsscos_ctx = req->max_rsscos_ctx;
3529         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3530         req->min_stat_ctx = req->max_stat_ctx;
3531         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3532                                                (num_vfs + 1));
3533         req->min_cmpl_rings = req->max_cmpl_rings;
3534         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3535         req->min_tx_rings = req->max_tx_rings;
3536         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3537         req->min_rx_rings = req->max_rx_rings;
3538         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3539         req->min_l2_ctxs = req->max_l2_ctxs;
3540         req->max_vnics = rte_cpu_to_le_16(bp->max_vnics / (num_vfs + 1));
3541         req->min_vnics = req->max_vnics;
3542         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3543                                                  (num_vfs + 1));
3544         req->min_hw_ring_grps = req->max_hw_ring_grps;
3545         req->max_msix = rte_cpu_to_le_16(bp->max_nq_rings / (num_vfs + 1));
3546 }
3547
3548 static void
3549 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3550                               struct hwrm_func_cfg_input *req,
3551                               int num_vfs)
3552 {
3553         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3554                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3555                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3556                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3557                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3558                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3559                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3560                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3561                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3562                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3563
3564         req->admin_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3565                                           RTE_ETHER_CRC_LEN + RTE_VLAN_HLEN *
3566                                           BNXT_NUM_VLANS);
3567         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3568         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3569                                                 (num_vfs + 1));
3570         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3571         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3572                                                (num_vfs + 1));
3573         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3574         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3575         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3576         /* TODO: For now, do not support VMDq/RFS on VFs. */
3577         req->num_vnics = rte_cpu_to_le_16(1);
3578         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3579                                                  (num_vfs + 1));
3580 }
3581
3582 /* Update the port wide resource values based on how many resources
3583  * got allocated to the VF.
3584  */
3585 static int bnxt_update_max_resources(struct bnxt *bp,
3586                                      int vf)
3587 {
3588         struct hwrm_func_qcfg_input req = {0};
3589         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3590         int rc;
3591
3592         /* Get the actual allocated values now */
3593         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3594         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3595         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3596         HWRM_CHECK_RESULT();
3597
3598         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3599         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3600         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3601         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3602         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3603         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3604         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3605         bp->max_nq_rings -= rte_le_to_cpu_16(resp->alloc_msix);
3606         bp->max_vnics -= rte_le_to_cpu_16(resp->alloc_vnics);
3607
3608         HWRM_UNLOCK();
3609
3610         return 0;
3611 }
3612
3613 /* Update the PF resource values based on how many resources
3614  * got allocated to it.
3615  */
3616 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3617 {
3618         struct hwrm_func_qcfg_input req = {0};
3619         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3620         int rc;
3621
3622         /* Get the actual allocated values now */
3623         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3624         req.fid = rte_cpu_to_le_16(0xffff);
3625         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3626         HWRM_CHECK_RESULT();
3627
3628         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3629         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3630         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3631         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3632         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3633         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3634         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3635         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3636
3637         HWRM_UNLOCK();
3638
3639         return 0;
3640 }
3641
3642 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3643 {
3644         struct hwrm_func_qcfg_input req = {0};
3645         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3646         int rc;
3647
3648         /* Check for zero MAC address */
3649         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3650         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3651         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3652         HWRM_CHECK_RESULT();
3653         rc = rte_le_to_cpu_16(resp->vlan);
3654
3655         HWRM_UNLOCK();
3656
3657         return rc;
3658 }
3659
3660 static int bnxt_query_pf_resources(struct bnxt *bp,
3661                                    struct bnxt_pf_resource_info *pf_resc)
3662 {
3663         struct hwrm_func_qcfg_input req = {0};
3664         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3665         int rc;
3666
3667         /* And copy the allocated numbers into the pf struct */
3668         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3669         req.fid = rte_cpu_to_le_16(0xffff);
3670         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3671         HWRM_CHECK_RESULT();
3672
3673         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3674         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3675         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3676         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3677         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3678         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3679         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3680         pf_resc->num_nq_rings = rte_le_to_cpu_32(resp->alloc_msix);
3681         pf_resc->num_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3682         bp->pf->evb_mode = resp->evb_mode;
3683
3684         HWRM_UNLOCK();
3685
3686         return rc;
3687 }
3688
3689 static void
3690 bnxt_calculate_pf_resources(struct bnxt *bp,
3691                             struct bnxt_pf_resource_info *pf_resc,
3692                             int num_vfs)
3693 {
3694         if (!num_vfs) {
3695                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3696                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3697                 pf_resc->num_cp_rings = bp->max_cp_rings;
3698                 pf_resc->num_tx_rings = bp->max_tx_rings;
3699                 pf_resc->num_rx_rings = bp->max_rx_rings;
3700                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3701                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3702                 pf_resc->num_nq_rings = bp->max_nq_rings;
3703                 pf_resc->num_vnics = bp->max_vnics;
3704
3705                 return;
3706         }
3707
3708         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3709                                    bp->max_rsscos_ctx % (num_vfs + 1);
3710         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3711                                  bp->max_stat_ctx % (num_vfs + 1);
3712         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3713                                 bp->max_cp_rings % (num_vfs + 1);
3714         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3715                                 bp->max_tx_rings % (num_vfs + 1);
3716         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3717                                 bp->max_rx_rings % (num_vfs + 1);
3718         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3719                                bp->max_l2_ctx % (num_vfs + 1);
3720         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3721                                     bp->max_ring_grps % (num_vfs + 1);
3722         pf_resc->num_nq_rings = bp->max_nq_rings / (num_vfs + 1) +
3723                                 bp->max_nq_rings % (num_vfs + 1);
3724         pf_resc->num_vnics = bp->max_vnics / (num_vfs + 1) +
3725                                 bp->max_vnics % (num_vfs + 1);
3726 }
3727
3728 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3729 {
3730         struct bnxt_pf_resource_info pf_resc = { 0 };
3731         int rc;
3732
3733         if (!BNXT_PF(bp)) {
3734                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3735                 return -EINVAL;
3736         }
3737
3738         rc = bnxt_hwrm_func_qcaps(bp);
3739         if (rc)
3740                 return rc;
3741
3742         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3743
3744         bp->pf->func_cfg_flags &=
3745                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3746                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3747         bp->pf->func_cfg_flags |=
3748                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3749
3750         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3751         if (rc)
3752                 return rc;
3753
3754         rc = bnxt_update_max_resources_pf_only(bp);
3755
3756         return rc;
3757 }
3758
3759 static int
3760 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3761 {
3762         size_t req_buf_sz, sz;
3763         int i, rc;
3764
3765         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3766         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3767                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3768         if (bp->pf->vf_req_buf == NULL) {
3769                 return -ENOMEM;
3770         }
3771
3772         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3773                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3774
3775         for (i = 0; i < num_vfs; i++)
3776                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3777                                              (i * HWRM_MAX_REQ_LEN);
3778
3779         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3780         if (rc)
3781                 rte_free(bp->pf->vf_req_buf);
3782
3783         return rc;
3784 }
3785
3786 static int
3787 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3788 {
3789         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3790         struct hwrm_func_vf_resource_cfg_input req = {0};
3791         int i, rc = 0;
3792
3793         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3794         bp->pf->active_vfs = 0;
3795         for (i = 0; i < num_vfs; i++) {
3796                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3797                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3798                 rc = bnxt_hwrm_send_message(bp,
3799                                             &req,
3800                                             sizeof(req),
3801                                             BNXT_USE_CHIMP_MB);
3802                 if (rc || resp->error_code) {
3803                         PMD_DRV_LOG(ERR,
3804                                 "Failed to initialize VF %d\n", i);
3805                         PMD_DRV_LOG(ERR,
3806                                 "Not all VFs available. (%d, %d)\n",
3807                                 rc, resp->error_code);
3808                         HWRM_UNLOCK();
3809
3810                         /* If the first VF configuration itself fails,
3811                          * unregister the vf_fwd_request buffer.
3812                          */
3813                         if (i == 0)
3814                                 bnxt_hwrm_func_buf_unrgtr(bp);
3815                         break;
3816                 }
3817                 HWRM_UNLOCK();
3818
3819                 /* Update the max resource values based on the resource values
3820                  * allocated to the VF.
3821                  */
3822                 bnxt_update_max_resources(bp, i);
3823                 bp->pf->active_vfs++;
3824                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3825         }
3826
3827         return 0;
3828 }
3829
3830 static int
3831 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3832 {
3833         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3834         struct hwrm_func_cfg_input req = {0};
3835         int i, rc;
3836
3837         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3838
3839         bp->pf->active_vfs = 0;
3840         for (i = 0; i < num_vfs; i++) {
3841                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3842                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3843                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3844                 rc = bnxt_hwrm_send_message(bp,
3845                                             &req,
3846                                             sizeof(req),
3847                                             BNXT_USE_CHIMP_MB);
3848
3849                 /* Clear enable flag for next pass */
3850                 req.enables &= ~rte_cpu_to_le_32(
3851                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3852
3853                 if (rc || resp->error_code) {
3854                         PMD_DRV_LOG(ERR,
3855                                 "Failed to initialize VF %d\n", i);
3856                         PMD_DRV_LOG(ERR,
3857                                 "Not all VFs available. (%d, %d)\n",
3858                                 rc, resp->error_code);
3859                         HWRM_UNLOCK();
3860
3861                         /* If the first VF configuration itself fails,
3862                          * unregister the vf_fwd_request buffer.
3863                          */
3864                         if (i == 0)
3865                                 bnxt_hwrm_func_buf_unrgtr(bp);
3866                         break;
3867                 }
3868
3869                 HWRM_UNLOCK();
3870
3871                 /* Update the max resource values based on the resource values
3872                  * allocated to the VF.
3873                  */
3874                 bnxt_update_max_resources(bp, i);
3875                 bp->pf->active_vfs++;
3876                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3877         }
3878
3879         return 0;
3880 }
3881
3882 static void
3883 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3884 {
3885         if (bp->flags & BNXT_FLAG_NEW_RM)
3886                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3887         else
3888                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3889 }
3890
3891 static void
3892 bnxt_update_pf_resources(struct bnxt *bp,
3893                          struct bnxt_pf_resource_info *pf_resc)
3894 {
3895         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3896         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3897         bp->max_cp_rings = pf_resc->num_cp_rings;
3898         bp->max_tx_rings = pf_resc->num_tx_rings;
3899         bp->max_rx_rings = pf_resc->num_rx_rings;
3900         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3901         bp->max_nq_rings = pf_resc->num_nq_rings;
3902         bp->max_vnics = pf_resc->num_vnics;
3903 }
3904
3905 static int32_t
3906 bnxt_configure_pf_resources(struct bnxt *bp,
3907                             struct bnxt_pf_resource_info *pf_resc)
3908 {
3909         /*
3910          * We're using STD_TX_RING_MODE here which will limit the TX
3911          * rings. This will allow QoS to function properly. Not setting this
3912          * will cause PF rings to break bandwidth settings.
3913          */
3914         bp->pf->func_cfg_flags &=
3915                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3916                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3917         bp->pf->func_cfg_flags |=
3918                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3919         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3920 }
3921
3922 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3923 {
3924         struct bnxt_pf_resource_info pf_resc = { 0 };
3925         int rc;
3926
3927         if (!BNXT_PF(bp)) {
3928                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3929                 return -EINVAL;
3930         }
3931
3932         rc = bnxt_hwrm_func_qcaps(bp);
3933         if (rc)
3934                 return rc;
3935
3936         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3937
3938         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3939         if (rc)
3940                 return rc;
3941
3942         rc = bnxt_query_pf_resources(bp, &pf_resc);
3943         if (rc)
3944                 return rc;
3945
3946         /*
3947          * Now, create and register a buffer to hold forwarded VF requests
3948          */
3949         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3950         if (rc)
3951                 return rc;
3952
3953         bnxt_configure_vf_resources(bp, num_vfs);
3954
3955         bnxt_update_pf_resources(bp, &pf_resc);
3956
3957         return 0;
3958 }
3959
3960 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3961 {
3962         struct hwrm_func_cfg_input req = {0};
3963         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3964         int rc;
3965
3966         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3967
3968         req.fid = rte_cpu_to_le_16(0xffff);
3969         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3970         req.evb_mode = bp->pf->evb_mode;
3971
3972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3973         HWRM_CHECK_RESULT();
3974         HWRM_UNLOCK();
3975
3976         return rc;
3977 }
3978
3979 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3980                                 uint8_t tunnel_type)
3981 {
3982         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3983         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3984         int rc = 0;
3985
3986         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3987         req.tunnel_type = tunnel_type;
3988         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3989         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3990         HWRM_CHECK_RESULT();
3991
3992         switch (tunnel_type) {
3993         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3994                 bp->vxlan_fw_dst_port_id =
3995                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3996                 bp->vxlan_port = port;
3997                 break;
3998         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3999                 bp->geneve_fw_dst_port_id =
4000                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
4001                 bp->geneve_port = port;
4002                 break;
4003         default:
4004                 break;
4005         }
4006
4007         HWRM_UNLOCK();
4008
4009         return rc;
4010 }
4011
4012 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4013                                 uint8_t tunnel_type)
4014 {
4015         struct hwrm_tunnel_dst_port_free_input req = {0};
4016         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4017         int rc = 0;
4018
4019         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4020
4021         req.tunnel_type = tunnel_type;
4022         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4023         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4024
4025         HWRM_CHECK_RESULT();
4026         HWRM_UNLOCK();
4027
4028         if (tunnel_type ==
4029             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4030                 bp->vxlan_port = 0;
4031                 bp->vxlan_port_cnt = 0;
4032         }
4033
4034         if (tunnel_type ==
4035             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4036                 bp->geneve_port = 0;
4037                 bp->geneve_port_cnt = 0;
4038         }
4039
4040         return rc;
4041 }
4042
4043 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4044                                         uint32_t flags)
4045 {
4046         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4047         struct hwrm_func_cfg_input req = {0};
4048         int rc;
4049
4050         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4051
4052         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4053         req.flags = rte_cpu_to_le_32(flags);
4054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4055
4056         HWRM_CHECK_RESULT();
4057         HWRM_UNLOCK();
4058
4059         return rc;
4060 }
4061
4062 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4063 {
4064         uint32_t *flag = flagp;
4065
4066         vnic->flags = *flag;
4067 }
4068
4069 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4070 {
4071         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4072 }
4073
4074 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4075 {
4076         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4077         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4078         int rc;
4079
4080         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4081
4082         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4083         req.req_buf_page_size =
4084                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4085         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4086         req.req_buf_page_addr0 =
4087                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4088         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4089                 PMD_DRV_LOG(ERR,
4090                         "unable to map buffer address to physical memory\n");
4091                 HWRM_UNLOCK();
4092                 return -ENOMEM;
4093         }
4094
4095         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4096
4097         HWRM_CHECK_RESULT();
4098         HWRM_UNLOCK();
4099
4100         return rc;
4101 }
4102
4103 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4104 {
4105         int rc = 0;
4106         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4107         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4108
4109         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4110                 return 0;
4111
4112         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4113
4114         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4115
4116         HWRM_CHECK_RESULT();
4117         HWRM_UNLOCK();
4118
4119         return rc;
4120 }
4121
4122 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4123 {
4124         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4125         struct hwrm_func_cfg_input req = {0};
4126         int rc;
4127
4128         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4129
4130         req.fid = rte_cpu_to_le_16(0xffff);
4131         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4132         req.enables = rte_cpu_to_le_32(
4133                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4134         req.async_event_cr = rte_cpu_to_le_16(
4135                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4136         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4137
4138         HWRM_CHECK_RESULT();
4139         HWRM_UNLOCK();
4140
4141         return rc;
4142 }
4143
4144 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4145 {
4146         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4147         struct hwrm_func_vf_cfg_input req = {0};
4148         int rc;
4149
4150         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4151
4152         req.enables = rte_cpu_to_le_32(
4153                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4154         req.async_event_cr = rte_cpu_to_le_16(
4155                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4157
4158         HWRM_CHECK_RESULT();
4159         HWRM_UNLOCK();
4160
4161         return rc;
4162 }
4163
4164 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4165 {
4166         struct hwrm_func_cfg_input req = {0};
4167         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4168         uint16_t dflt_vlan, fid;
4169         uint32_t func_cfg_flags;
4170         int rc = 0;
4171
4172         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4173
4174         if (is_vf) {
4175                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4176                 fid = bp->pf->vf_info[vf].fid;
4177                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4178         } else {
4179                 fid = rte_cpu_to_le_16(0xffff);
4180                 func_cfg_flags = bp->pf->func_cfg_flags;
4181                 dflt_vlan = bp->vlan;
4182         }
4183
4184         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4185         req.fid = rte_cpu_to_le_16(fid);
4186         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4187         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4188
4189         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4190
4191         HWRM_CHECK_RESULT();
4192         HWRM_UNLOCK();
4193
4194         return rc;
4195 }
4196
4197 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4198                         uint16_t max_bw, uint16_t enables)
4199 {
4200         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4201         struct hwrm_func_cfg_input req = {0};
4202         int rc;
4203
4204         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4205
4206         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4207         req.enables |= rte_cpu_to_le_32(enables);
4208         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4209         req.max_bw = rte_cpu_to_le_32(max_bw);
4210         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4211
4212         HWRM_CHECK_RESULT();
4213         HWRM_UNLOCK();
4214
4215         return rc;
4216 }
4217
4218 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4219 {
4220         struct hwrm_func_cfg_input req = {0};
4221         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4222         int rc = 0;
4223
4224         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4225
4226         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4227         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4228         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4229         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4230
4231         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4232
4233         HWRM_CHECK_RESULT();
4234         HWRM_UNLOCK();
4235
4236         return rc;
4237 }
4238
4239 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4240 {
4241         int rc;
4242
4243         if (BNXT_PF(bp))
4244                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4245         else
4246                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4247
4248         return rc;
4249 }
4250
4251 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4252                               void *encaped, size_t ec_size)
4253 {
4254         int rc = 0;
4255         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4256         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4257
4258         if (ec_size > sizeof(req.encap_request))
4259                 return -1;
4260
4261         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4262
4263         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4264         memcpy(req.encap_request, encaped, ec_size);
4265
4266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4267
4268         HWRM_CHECK_RESULT();
4269         HWRM_UNLOCK();
4270
4271         return rc;
4272 }
4273
4274 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4275                                        struct rte_ether_addr *mac)
4276 {
4277         struct hwrm_func_qcfg_input req = {0};
4278         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4279         int rc;
4280
4281         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4282
4283         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4284         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4285
4286         HWRM_CHECK_RESULT();
4287
4288         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4289
4290         HWRM_UNLOCK();
4291
4292         return rc;
4293 }
4294
4295 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4296                             void *encaped, size_t ec_size)
4297 {
4298         int rc = 0;
4299         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4300         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4301
4302         if (ec_size > sizeof(req.encap_request))
4303                 return -1;
4304
4305         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4306
4307         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4308         memcpy(req.encap_request, encaped, ec_size);
4309
4310         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4311
4312         HWRM_CHECK_RESULT();
4313         HWRM_UNLOCK();
4314
4315         return rc;
4316 }
4317
4318 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4319 {
4320         /* One of the HW stat values that make up this counter was zero as
4321          * returned by HW in this iteration, so use the previous
4322          * iteration's counter value
4323          */
4324         if (*prev_cntr && *cntr == 0)
4325                 *cntr = *prev_cntr;
4326         else
4327                 *prev_cntr = *cntr;
4328 }
4329
4330 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4331                          struct bnxt_ring_stats *ring_stats, bool rx)
4332 {
4333         int rc = 0;
4334         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4335         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4336
4337         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4338
4339         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4340
4341         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4342
4343         HWRM_CHECK_RESULT();
4344
4345         if (rx) {
4346                 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4347
4348                 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4349                 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4350                                       &prev_stats->rx_ucast_pkts);
4351
4352                 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4353                 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4354                                       &prev_stats->rx_mcast_pkts);
4355
4356                 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4357                 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4358                                       &prev_stats->rx_bcast_pkts);
4359
4360                 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4361                 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4362                                       &prev_stats->rx_ucast_bytes);
4363
4364                 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4365                 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4366                                       &prev_stats->rx_mcast_bytes);
4367
4368                 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4369                 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4370                                       &prev_stats->rx_bcast_bytes);
4371
4372                 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4373                 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4374                                       &prev_stats->rx_discard_pkts);
4375
4376                 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4377                 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4378                                       &prev_stats->rx_error_pkts);
4379
4380                 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4381                 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4382                                       &prev_stats->rx_agg_pkts);
4383
4384                 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4385                 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4386                                       &prev_stats->rx_agg_bytes);
4387
4388                 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4389                 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4390                                       &prev_stats->rx_agg_events);
4391
4392                 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4393                 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4394                                       &prev_stats->rx_agg_aborts);
4395         } else {
4396                 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4397
4398                 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4399                 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4400                                       &prev_stats->tx_ucast_pkts);
4401
4402                 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4403                 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4404                                       &prev_stats->tx_mcast_pkts);
4405
4406                 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4407                 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4408                                       &prev_stats->tx_bcast_pkts);
4409
4410                 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4411                 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4412                                       &prev_stats->tx_ucast_bytes);
4413
4414                 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4415                 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4416                                       &prev_stats->tx_mcast_bytes);
4417
4418                 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4419                 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4420                                       &prev_stats->tx_bcast_bytes);
4421
4422                 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4423                 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4424                                       &prev_stats->tx_discard_pkts);
4425         }
4426
4427         HWRM_UNLOCK();
4428
4429         return rc;
4430 }
4431
4432 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4433 {
4434         struct hwrm_port_qstats_input req = {0};
4435         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4436         struct bnxt_pf_info *pf = bp->pf;
4437         int rc;
4438
4439         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4440
4441         req.port_id = rte_cpu_to_le_16(pf->port_id);
4442         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4443         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4444         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4445
4446         HWRM_CHECK_RESULT();
4447         HWRM_UNLOCK();
4448
4449         return rc;
4450 }
4451
4452 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4453 {
4454         struct hwrm_port_clr_stats_input req = {0};
4455         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4456         struct bnxt_pf_info *pf = bp->pf;
4457         int rc;
4458
4459         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4460         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4461             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4462                 return 0;
4463
4464         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4465
4466         req.port_id = rte_cpu_to_le_16(pf->port_id);
4467         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4468
4469         HWRM_CHECK_RESULT();
4470         HWRM_UNLOCK();
4471
4472         return rc;
4473 }
4474
4475 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4476 {
4477         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4478         struct hwrm_port_led_qcaps_input req = {0};
4479         int rc;
4480
4481         if (BNXT_VF(bp))
4482                 return 0;
4483
4484         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4485         req.port_id = bp->pf->port_id;
4486         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4487
4488         HWRM_CHECK_RESULT_SILENT();
4489
4490         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4491                 unsigned int i;
4492
4493                 bp->leds->num_leds = resp->num_leds;
4494                 memcpy(bp->leds, &resp->led0_id,
4495                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4496                 for (i = 0; i < bp->leds->num_leds; i++) {
4497                         struct bnxt_led_info *led = &bp->leds[i];
4498
4499                         uint16_t caps = led->led_state_caps;
4500
4501                         if (!led->led_group_id ||
4502                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4503                                 bp->leds->num_leds = 0;
4504                                 break;
4505                         }
4506                 }
4507         }
4508
4509         HWRM_UNLOCK();
4510
4511         return rc;
4512 }
4513
4514 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4515 {
4516         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4517         struct hwrm_port_led_cfg_input req = {0};
4518         struct bnxt_led_cfg *led_cfg;
4519         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4520         uint16_t duration = 0;
4521         int rc, i;
4522
4523         if (!bp->leds->num_leds || BNXT_VF(bp))
4524                 return -EOPNOTSUPP;
4525
4526         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4527
4528         if (led_on) {
4529                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4530                 duration = rte_cpu_to_le_16(500);
4531         }
4532         req.port_id = bp->pf->port_id;
4533         req.num_leds = bp->leds->num_leds;
4534         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4535         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4536                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4537                 led_cfg->led_id = bp->leds[i].led_id;
4538                 led_cfg->led_state = led_state;
4539                 led_cfg->led_blink_on = duration;
4540                 led_cfg->led_blink_off = duration;
4541                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4542         }
4543
4544         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4545
4546         HWRM_CHECK_RESULT();
4547         HWRM_UNLOCK();
4548
4549         return rc;
4550 }
4551
4552 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4553                                uint32_t *length)
4554 {
4555         int rc;
4556         struct hwrm_nvm_get_dir_info_input req = {0};
4557         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4558
4559         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4560
4561         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4562
4563         HWRM_CHECK_RESULT();
4564
4565         *entries = rte_le_to_cpu_32(resp->entries);
4566         *length = rte_le_to_cpu_32(resp->entry_length);
4567
4568         HWRM_UNLOCK();
4569         return rc;
4570 }
4571
4572 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4573 {
4574         int rc;
4575         uint32_t dir_entries;
4576         uint32_t entry_length;
4577         uint8_t *buf;
4578         size_t buflen;
4579         rte_iova_t dma_handle;
4580         struct hwrm_nvm_get_dir_entries_input req = {0};
4581         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4582
4583         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4584         if (rc != 0)
4585                 return rc;
4586
4587         *data++ = dir_entries;
4588         *data++ = entry_length;
4589         len -= 2;
4590         memset(data, 0xff, len);
4591
4592         buflen = dir_entries * entry_length;
4593         buf = rte_malloc("nvm_dir", buflen, 0);
4594         if (buf == NULL)
4595                 return -ENOMEM;
4596         dma_handle = rte_malloc_virt2iova(buf);
4597         if (dma_handle == RTE_BAD_IOVA) {
4598                 rte_free(buf);
4599                 PMD_DRV_LOG(ERR,
4600                         "unable to map response address to physical memory\n");
4601                 return -ENOMEM;
4602         }
4603         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4604         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4605         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4606
4607         if (rc == 0)
4608                 memcpy(data, buf, len > buflen ? buflen : len);
4609
4610         rte_free(buf);
4611         HWRM_CHECK_RESULT();
4612         HWRM_UNLOCK();
4613
4614         return rc;
4615 }
4616
4617 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4618                              uint32_t offset, uint32_t length,
4619                              uint8_t *data)
4620 {
4621         int rc;
4622         uint8_t *buf;
4623         rte_iova_t dma_handle;
4624         struct hwrm_nvm_read_input req = {0};
4625         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4626
4627         buf = rte_malloc("nvm_item", length, 0);
4628         if (!buf)
4629                 return -ENOMEM;
4630
4631         dma_handle = rte_malloc_virt2iova(buf);
4632         if (dma_handle == RTE_BAD_IOVA) {
4633                 rte_free(buf);
4634                 PMD_DRV_LOG(ERR,
4635                         "unable to map response address to physical memory\n");
4636                 return -ENOMEM;
4637         }
4638         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4639         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4640         req.dir_idx = rte_cpu_to_le_16(index);
4641         req.offset = rte_cpu_to_le_32(offset);
4642         req.len = rte_cpu_to_le_32(length);
4643         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4644         if (rc == 0)
4645                 memcpy(data, buf, length);
4646
4647         rte_free(buf);
4648         HWRM_CHECK_RESULT();
4649         HWRM_UNLOCK();
4650
4651         return rc;
4652 }
4653
4654 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4655 {
4656         int rc;
4657         struct hwrm_nvm_erase_dir_entry_input req = {0};
4658         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4659
4660         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4661         req.dir_idx = rte_cpu_to_le_16(index);
4662         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4663         HWRM_CHECK_RESULT();
4664         HWRM_UNLOCK();
4665
4666         return rc;
4667 }
4668
4669 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4670                           uint16_t dir_ordinal, uint16_t dir_ext,
4671                           uint16_t dir_attr, const uint8_t *data,
4672                           size_t data_len)
4673 {
4674         int rc;
4675         struct hwrm_nvm_write_input req = {0};
4676         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4677         rte_iova_t dma_handle;
4678         uint8_t *buf;
4679
4680         buf = rte_malloc("nvm_write", data_len, 0);
4681         if (!buf)
4682                 return -ENOMEM;
4683
4684         dma_handle = rte_malloc_virt2iova(buf);
4685         if (dma_handle == RTE_BAD_IOVA) {
4686                 rte_free(buf);
4687                 PMD_DRV_LOG(ERR,
4688                         "unable to map response address to physical memory\n");
4689                 return -ENOMEM;
4690         }
4691         memcpy(buf, data, data_len);
4692
4693         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4694
4695         req.dir_type = rte_cpu_to_le_16(dir_type);
4696         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4697         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4698         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4699         req.dir_data_length = rte_cpu_to_le_32(data_len);
4700         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4701
4702         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4703
4704         rte_free(buf);
4705         HWRM_CHECK_RESULT();
4706         HWRM_UNLOCK();
4707
4708         return rc;
4709 }
4710
4711 static void
4712 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4713 {
4714         uint32_t *count = cbdata;
4715
4716         *count = *count + 1;
4717 }
4718
4719 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4720                                      struct bnxt_vnic_info *vnic __rte_unused)
4721 {
4722         return 0;
4723 }
4724
4725 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4726 {
4727         uint32_t count = 0;
4728
4729         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4730             &count, bnxt_vnic_count_hwrm_stub);
4731
4732         return count;
4733 }
4734
4735 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4736                                         uint16_t *vnic_ids)
4737 {
4738         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4739         struct hwrm_func_vf_vnic_ids_query_output *resp =
4740                                                 bp->hwrm_cmd_resp_addr;
4741         int rc;
4742
4743         /* First query all VNIC ids */
4744         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4745
4746         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4747         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4748         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4749
4750         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4751                 HWRM_UNLOCK();
4752                 PMD_DRV_LOG(ERR,
4753                 "unable to map VNIC ID table address to physical memory\n");
4754                 return -ENOMEM;
4755         }
4756         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4757         HWRM_CHECK_RESULT();
4758         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4759
4760         HWRM_UNLOCK();
4761
4762         return rc;
4763 }
4764
4765 /*
4766  * This function queries the VNIC IDs  for a specified VF. It then calls
4767  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4768  * Then it calls the hwrm_cb function to program this new vnic configuration.
4769  */
4770 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4771         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4772         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4773 {
4774         struct bnxt_vnic_info vnic;
4775         int rc = 0;
4776         int i, num_vnic_ids;
4777         uint16_t *vnic_ids;
4778         size_t vnic_id_sz;
4779         size_t sz;
4780
4781         /* First query all VNIC ids */
4782         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4783         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4784                         RTE_CACHE_LINE_SIZE);
4785         if (vnic_ids == NULL)
4786                 return -ENOMEM;
4787
4788         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4789                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4790
4791         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4792
4793         if (num_vnic_ids < 0)
4794                 return num_vnic_ids;
4795
4796         /* Retrieve VNIC, update bd_stall then update */
4797
4798         for (i = 0; i < num_vnic_ids; i++) {
4799                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4800                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4801                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4802                 if (rc)
4803                         break;
4804                 if (vnic.mru <= 4)      /* Indicates unallocated */
4805                         continue;
4806
4807                 vnic_cb(&vnic, cbdata);
4808
4809                 rc = hwrm_cb(bp, &vnic);
4810                 if (rc)
4811                         break;
4812         }
4813
4814         rte_free(vnic_ids);
4815
4816         return rc;
4817 }
4818
4819 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4820                                               bool on)
4821 {
4822         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4823         struct hwrm_func_cfg_input req = {0};
4824         int rc;
4825
4826         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4827
4828         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4829         req.enables |= rte_cpu_to_le_32(
4830                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4831         req.vlan_antispoof_mode = on ?
4832                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4833                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4834         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4835
4836         HWRM_CHECK_RESULT();
4837         HWRM_UNLOCK();
4838
4839         return rc;
4840 }
4841
4842 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4843 {
4844         struct bnxt_vnic_info vnic;
4845         uint16_t *vnic_ids;
4846         size_t vnic_id_sz;
4847         int num_vnic_ids, i;
4848         size_t sz;
4849         int rc;
4850
4851         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4852         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4853                         RTE_CACHE_LINE_SIZE);
4854         if (vnic_ids == NULL)
4855                 return -ENOMEM;
4856
4857         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4858                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4859
4860         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4861         if (rc <= 0)
4862                 goto exit;
4863         num_vnic_ids = rc;
4864
4865         /*
4866          * Loop through to find the default VNIC ID.
4867          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4868          * by sending the hwrm_func_qcfg command to the firmware.
4869          */
4870         for (i = 0; i < num_vnic_ids; i++) {
4871                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4872                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4873                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4874                                         bp->pf->first_vf_id + vf);
4875                 if (rc)
4876                         goto exit;
4877                 if (vnic.func_default) {
4878                         rte_free(vnic_ids);
4879                         return vnic.fw_vnic_id;
4880                 }
4881         }
4882         /* Could not find a default VNIC. */
4883         PMD_DRV_LOG(ERR, "No default VNIC\n");
4884 exit:
4885         rte_free(vnic_ids);
4886         return rc;
4887 }
4888
4889 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4890                          uint16_t dst_id,
4891                          struct bnxt_filter_info *filter)
4892 {
4893         int rc = 0;
4894         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4895         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4896         uint32_t enables = 0;
4897
4898         if (filter->fw_em_filter_id != UINT64_MAX)
4899                 bnxt_hwrm_clear_em_filter(bp, filter);
4900
4901         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4902
4903         req.flags = rte_cpu_to_le_32(filter->flags);
4904
4905         enables = filter->enables |
4906               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4907         req.dst_id = rte_cpu_to_le_16(dst_id);
4908
4909         if (filter->ip_addr_type) {
4910                 req.ip_addr_type = filter->ip_addr_type;
4911                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4912         }
4913         if (enables &
4914             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4915                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4916         if (enables &
4917             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4918                 memcpy(req.src_macaddr, filter->src_macaddr,
4919                        RTE_ETHER_ADDR_LEN);
4920         if (enables &
4921             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4922                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4923                        RTE_ETHER_ADDR_LEN);
4924         if (enables &
4925             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4926                 req.ovlan_vid = filter->l2_ovlan;
4927         if (enables &
4928             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4929                 req.ivlan_vid = filter->l2_ivlan;
4930         if (enables &
4931             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4932                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4933         if (enables &
4934             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4935                 req.ip_protocol = filter->ip_protocol;
4936         if (enables &
4937             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4938                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4939         if (enables &
4940             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4941                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4942         if (enables &
4943             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4944                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4945         if (enables &
4946             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4947                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4948         if (enables &
4949             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4950                 req.mirror_vnic_id = filter->mirror_vnic_id;
4951
4952         req.enables = rte_cpu_to_le_32(enables);
4953
4954         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4955
4956         HWRM_CHECK_RESULT();
4957
4958         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4959         HWRM_UNLOCK();
4960
4961         return rc;
4962 }
4963
4964 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4965 {
4966         int rc = 0;
4967         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4968         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4969
4970         if (filter->fw_em_filter_id == UINT64_MAX)
4971                 return 0;
4972
4973         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4974
4975         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4976
4977         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4978
4979         HWRM_CHECK_RESULT();
4980         HWRM_UNLOCK();
4981
4982         filter->fw_em_filter_id = UINT64_MAX;
4983         filter->fw_l2_filter_id = UINT64_MAX;
4984
4985         return 0;
4986 }
4987
4988 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4989                          uint16_t dst_id,
4990                          struct bnxt_filter_info *filter)
4991 {
4992         int rc = 0;
4993         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4994         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4995                                                 bp->hwrm_cmd_resp_addr;
4996         uint32_t enables = 0;
4997
4998         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4999                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
5000
5001         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
5002
5003         req.flags = rte_cpu_to_le_32(filter->flags);
5004
5005         enables = filter->enables |
5006               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
5007         req.dst_id = rte_cpu_to_le_16(dst_id);
5008
5009         if (filter->ip_addr_type) {
5010                 req.ip_addr_type = filter->ip_addr_type;
5011                 enables |=
5012                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
5013         }
5014         if (enables &
5015             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5016                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5017         if (enables &
5018             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5019                 memcpy(req.src_macaddr, filter->src_macaddr,
5020                        RTE_ETHER_ADDR_LEN);
5021         if (enables &
5022             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5023                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5024         if (enables &
5025             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5026                 req.ip_protocol = filter->ip_protocol;
5027         if (enables &
5028             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5029                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5030         if (enables &
5031             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5032                 req.src_ipaddr_mask[0] =
5033                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5034         if (enables &
5035             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5036                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5037         if (enables &
5038             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5039                 req.dst_ipaddr_mask[0] =
5040                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5041         if (enables &
5042             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5043                 req.src_port = rte_cpu_to_le_16(filter->src_port);
5044         if (enables &
5045             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5046                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5047         if (enables &
5048             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5049                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5050         if (enables &
5051             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5052                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5053         if (enables &
5054             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5055                 req.mirror_vnic_id = filter->mirror_vnic_id;
5056
5057         req.enables = rte_cpu_to_le_32(enables);
5058
5059         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5060
5061         HWRM_CHECK_RESULT();
5062
5063         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5064         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5065         HWRM_UNLOCK();
5066
5067         return rc;
5068 }
5069
5070 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5071                                 struct bnxt_filter_info *filter)
5072 {
5073         int rc = 0;
5074         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5075         struct hwrm_cfa_ntuple_filter_free_output *resp =
5076                                                 bp->hwrm_cmd_resp_addr;
5077
5078         if (filter->fw_ntuple_filter_id == UINT64_MAX)
5079                 return 0;
5080
5081         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5082
5083         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5084
5085         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5086
5087         HWRM_CHECK_RESULT();
5088         HWRM_UNLOCK();
5089
5090         filter->fw_ntuple_filter_id = UINT64_MAX;
5091
5092         return 0;
5093 }
5094
5095 static int
5096 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5097 {
5098         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5099         uint8_t *rxq_state = bp->eth_dev->data->rx_queue_state;
5100         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5101         struct bnxt_rx_queue **rxqs = bp->rx_queues;
5102         uint16_t *ring_tbl = vnic->rss_table;
5103         int nr_ctxs = vnic->num_lb_ctxts;
5104         int max_rings = bp->rx_nr_rings;
5105         int i, j, k, cnt;
5106         int rc = 0;
5107
5108         for (i = 0, k = 0; i < nr_ctxs; i++) {
5109                 struct bnxt_rx_ring_info *rxr;
5110                 struct bnxt_cp_ring_info *cpr;
5111
5112                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5113
5114                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5115                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5116                 req.hash_mode_flags = vnic->hash_mode;
5117
5118                 req.ring_grp_tbl_addr =
5119                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5120                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5121                                      2 * sizeof(*ring_tbl));
5122                 req.hash_key_tbl_addr =
5123                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5124
5125                 req.ring_table_pair_index = i;
5126                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5127
5128                 for (j = 0; j < 64; j++) {
5129                         uint16_t ring_id;
5130
5131                         /* Find next active ring. */
5132                         for (cnt = 0; cnt < max_rings; cnt++) {
5133                                 if (rxq_state[k] != RTE_ETH_QUEUE_STATE_STOPPED)
5134                                         break;
5135                                 if (++k == max_rings)
5136                                         k = 0;
5137                         }
5138
5139                         /* Return if no rings are active. */
5140                         if (cnt == max_rings) {
5141                                 HWRM_UNLOCK();
5142                                 return 0;
5143                         }
5144
5145                         /* Add rx/cp ring pair to RSS table. */
5146                         rxr = rxqs[k]->rx_ring;
5147                         cpr = rxqs[k]->cp_ring;
5148
5149                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5150                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5151                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5152                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5153
5154                         if (++k == max_rings)
5155                                 k = 0;
5156                 }
5157                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5158                                             BNXT_USE_CHIMP_MB);
5159
5160                 HWRM_CHECK_RESULT();
5161                 HWRM_UNLOCK();
5162         }
5163
5164         return rc;
5165 }
5166
5167 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5168 {
5169         unsigned int rss_idx, fw_idx, i;
5170
5171         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5172                 return 0;
5173
5174         if (!(vnic->rss_table && vnic->hash_type))
5175                 return 0;
5176
5177         if (BNXT_CHIP_P5(bp))
5178                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5179
5180         /*
5181          * Fill the RSS hash & redirection table with
5182          * ring group ids for all VNICs
5183          */
5184         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5185              rss_idx++, fw_idx++) {
5186                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5187                         fw_idx %= bp->rx_cp_nr_rings;
5188                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5189                                 break;
5190                         fw_idx++;
5191                 }
5192
5193                 if (i == bp->rx_cp_nr_rings)
5194                         return 0;
5195
5196                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5197         }
5198
5199         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5200 }
5201
5202 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5203         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5204 {
5205         uint16_t flags;
5206
5207         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5208
5209         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5210         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5211
5212         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5213         req->num_cmpl_dma_aggr_during_int =
5214                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5215
5216         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5217
5218         /* min timer set to 1/2 of interrupt timer */
5219         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5220
5221         /* buf timer set to 1/4 of interrupt timer */
5222         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5223
5224         req->cmpl_aggr_dma_tmr_during_int =
5225                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5226
5227         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5228                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5229         req->flags = rte_cpu_to_le_16(flags);
5230 }
5231
5232 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5233                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5234 {
5235         struct hwrm_ring_aggint_qcaps_input req = {0};
5236         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5237         uint32_t enables;
5238         uint16_t flags;
5239         int rc;
5240
5241         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5242         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5243         HWRM_CHECK_RESULT();
5244
5245         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5246         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5247
5248         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5249                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5250         agg_req->flags = rte_cpu_to_le_16(flags);
5251         enables =
5252          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5253          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5254         agg_req->enables = rte_cpu_to_le_32(enables);
5255
5256         HWRM_UNLOCK();
5257         return rc;
5258 }
5259
5260 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5261                         struct bnxt_coal *coal, uint16_t ring_id)
5262 {
5263         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5264         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5265                                                 bp->hwrm_cmd_resp_addr;
5266         int rc;
5267
5268         /* Set ring coalesce parameters only for 100G NICs */
5269         if (BNXT_CHIP_P5(bp)) {
5270                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5271                         return -1;
5272         } else if (bnxt_stratus_device(bp)) {
5273                 bnxt_hwrm_set_coal_params(coal, &req);
5274         } else {
5275                 return 0;
5276         }
5277
5278         HWRM_PREP(&req,
5279                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5280                   BNXT_USE_CHIMP_MB);
5281         req.ring_id = rte_cpu_to_le_16(ring_id);
5282         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5283         HWRM_CHECK_RESULT();
5284         HWRM_UNLOCK();
5285         return 0;
5286 }
5287
5288 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5289 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5290 {
5291         struct hwrm_func_backing_store_qcaps_input req = {0};
5292         struct hwrm_func_backing_store_qcaps_output *resp =
5293                 bp->hwrm_cmd_resp_addr;
5294         struct bnxt_ctx_pg_info *ctx_pg;
5295         struct bnxt_ctx_mem_info *ctx;
5296         int total_alloc_len;
5297         int rc, i, tqm_rings;
5298
5299         if (!BNXT_CHIP_P5(bp) ||
5300             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5301             BNXT_VF(bp) ||
5302             bp->ctx)
5303                 return 0;
5304
5305         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5306         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5307         HWRM_CHECK_RESULT_SILENT();
5308
5309         total_alloc_len = sizeof(*ctx);
5310         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5311                           RTE_CACHE_LINE_SIZE);
5312         if (!ctx) {
5313                 rc = -ENOMEM;
5314                 goto ctx_err;
5315         }
5316
5317         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5318         ctx->qp_min_qp1_entries =
5319                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5320         ctx->qp_max_l2_entries =
5321                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5322         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5323         ctx->srq_max_l2_entries =
5324                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5325         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5326         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5327         ctx->cq_max_l2_entries =
5328                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5329         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5330         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5331         ctx->vnic_max_vnic_entries =
5332                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5333         ctx->vnic_max_ring_table_entries =
5334                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5335         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5336         ctx->stat_max_entries =
5337                 rte_le_to_cpu_32(resp->stat_max_entries);
5338         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5339         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5340         ctx->tqm_min_entries_per_ring =
5341                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5342         ctx->tqm_max_entries_per_ring =
5343                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5344         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5345         if (!ctx->tqm_entries_multiple)
5346                 ctx->tqm_entries_multiple = 1;
5347         ctx->mrav_max_entries =
5348                 rte_le_to_cpu_32(resp->mrav_max_entries);
5349         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5350         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5351         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5352         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5353
5354         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5355                                   RTE_MIN(ctx->tqm_fp_rings_count,
5356                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5357                                   bp->max_q;
5358
5359         /* Check if the ext ring count needs to be counted.
5360          * Ext ring count is available only with new FW so we should not
5361          * look at the field on older FW.
5362          */
5363         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5364             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5365                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5366                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5367                                                   ctx->tqm_fp_rings_count);
5368         }
5369
5370         tqm_rings = ctx->tqm_fp_rings_count + 1;
5371
5372         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5373                             sizeof(*ctx_pg) * tqm_rings,
5374                             RTE_CACHE_LINE_SIZE);
5375         if (!ctx_pg) {
5376                 rc = -ENOMEM;
5377                 goto ctx_err;
5378         }
5379         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5380                 ctx->tqm_mem[i] = ctx_pg;
5381
5382         bp->ctx = ctx;
5383 ctx_err:
5384         HWRM_UNLOCK();
5385         return rc;
5386 }
5387
5388 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5389 {
5390         struct hwrm_func_backing_store_cfg_input req = {0};
5391         struct hwrm_func_backing_store_cfg_output *resp =
5392                 bp->hwrm_cmd_resp_addr;
5393         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5394         struct bnxt_ctx_pg_info *ctx_pg;
5395         uint32_t *num_entries;
5396         uint64_t *pg_dir;
5397         uint8_t *pg_attr;
5398         uint32_t ena;
5399         int i, rc;
5400
5401         if (!ctx)
5402                 return 0;
5403
5404         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5405         req.enables = rte_cpu_to_le_32(enables);
5406
5407         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5408                 ctx_pg = &ctx->qp_mem;
5409                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5410                 req.qp_num_qp1_entries =
5411                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5412                 req.qp_num_l2_entries =
5413                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5414                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5415                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5416                                       &req.qpc_pg_size_qpc_lvl,
5417                                       &req.qpc_page_dir);
5418         }
5419
5420         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5421                 ctx_pg = &ctx->srq_mem;
5422                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5423                 req.srq_num_l2_entries =
5424                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5425                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5426                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5427                                       &req.srq_pg_size_srq_lvl,
5428                                       &req.srq_page_dir);
5429         }
5430
5431         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5432                 ctx_pg = &ctx->cq_mem;
5433                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5434                 req.cq_num_l2_entries =
5435                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5436                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5437                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5438                                       &req.cq_pg_size_cq_lvl,
5439                                       &req.cq_page_dir);
5440         }
5441
5442         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5443                 ctx_pg = &ctx->vnic_mem;
5444                 req.vnic_num_vnic_entries =
5445                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5446                 req.vnic_num_ring_table_entries =
5447                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5448                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5449                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5450                                       &req.vnic_pg_size_vnic_lvl,
5451                                       &req.vnic_page_dir);
5452         }
5453
5454         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5455                 ctx_pg = &ctx->stat_mem;
5456                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5457                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5458                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5459                                       &req.stat_pg_size_stat_lvl,
5460                                       &req.stat_page_dir);
5461         }
5462
5463         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5464         num_entries = &req.tqm_sp_num_entries;
5465         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5466         pg_dir = &req.tqm_sp_page_dir;
5467         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5468         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5469                 if (!(enables & ena))
5470                         continue;
5471
5472                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5473
5474                 ctx_pg = ctx->tqm_mem[i];
5475                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5476                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5477         }
5478
5479         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5480                 /* DPDK does not need to configure MRAV and TIM type.
5481                  * So we are skipping over MRAV and TIM. Skip to configure
5482                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5483                  */
5484                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5485                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5486                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5487                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5488                                       &req.tqm_ring8_page_dir);
5489         }
5490
5491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5492         HWRM_CHECK_RESULT();
5493         HWRM_UNLOCK();
5494
5495         return rc;
5496 }
5497
5498 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5499 {
5500         struct hwrm_port_qstats_ext_input req = {0};
5501         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5502         struct bnxt_pf_info *pf = bp->pf;
5503         int rc;
5504
5505         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5506               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5507                 return 0;
5508
5509         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5510
5511         req.port_id = rte_cpu_to_le_16(pf->port_id);
5512         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5513                 req.tx_stat_host_addr =
5514                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5515                 req.tx_stat_size =
5516                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5517         }
5518         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5519                 req.rx_stat_host_addr =
5520                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5521                 req.rx_stat_size =
5522                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5523         }
5524         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5525
5526         if (rc) {
5527                 bp->fw_rx_port_stats_ext_size = 0;
5528                 bp->fw_tx_port_stats_ext_size = 0;
5529         } else {
5530                 bp->fw_rx_port_stats_ext_size =
5531                         rte_le_to_cpu_16(resp->rx_stat_size);
5532                 bp->fw_tx_port_stats_ext_size =
5533                         rte_le_to_cpu_16(resp->tx_stat_size);
5534         }
5535
5536         HWRM_CHECK_RESULT();
5537         HWRM_UNLOCK();
5538
5539         return rc;
5540 }
5541
5542 int
5543 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5544 {
5545         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5546         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5547                 bp->hwrm_cmd_resp_addr;
5548         int rc = 0;
5549
5550         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5551         req.tunnel_type = type;
5552         req.dest_fid = bp->fw_fid;
5553         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5554         HWRM_CHECK_RESULT();
5555
5556         HWRM_UNLOCK();
5557
5558         return rc;
5559 }
5560
5561 int
5562 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5563 {
5564         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5565         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5566                 bp->hwrm_cmd_resp_addr;
5567         int rc = 0;
5568
5569         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5570         req.tunnel_type = type;
5571         req.dest_fid = bp->fw_fid;
5572         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5573         HWRM_CHECK_RESULT();
5574
5575         HWRM_UNLOCK();
5576
5577         return rc;
5578 }
5579
5580 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5581 {
5582         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5583         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5584                 bp->hwrm_cmd_resp_addr;
5585         int rc = 0;
5586
5587         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5588         req.src_fid = bp->fw_fid;
5589         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5590         HWRM_CHECK_RESULT();
5591
5592         if (type)
5593                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5594
5595         HWRM_UNLOCK();
5596
5597         return rc;
5598 }
5599
5600 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5601                                    uint16_t *dst_fid)
5602 {
5603         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5604         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5605                 bp->hwrm_cmd_resp_addr;
5606         int rc = 0;
5607
5608         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5609         req.src_fid = bp->fw_fid;
5610         req.tunnel_type = tun_type;
5611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5612         HWRM_CHECK_RESULT();
5613
5614         if (dst_fid)
5615                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5616
5617         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5618
5619         HWRM_UNLOCK();
5620
5621         return rc;
5622 }
5623
5624 int bnxt_hwrm_set_mac(struct bnxt *bp)
5625 {
5626         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5627         struct hwrm_func_vf_cfg_input req = {0};
5628         int rc = 0;
5629
5630         if (!BNXT_VF(bp))
5631                 return 0;
5632
5633         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5634
5635         req.enables =
5636                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5637         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5638
5639         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5640
5641         HWRM_CHECK_RESULT();
5642
5643         HWRM_UNLOCK();
5644
5645         return rc;
5646 }
5647
5648 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5649 {
5650         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5651         struct hwrm_func_drv_if_change_input req = {0};
5652         uint32_t flags;
5653         int rc;
5654
5655         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5656                 return 0;
5657
5658         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5659          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5660          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5661          */
5662         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5663                 return 0;
5664
5665         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5666
5667         if (up)
5668                 req.flags =
5669                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5670
5671         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5672
5673         HWRM_CHECK_RESULT();
5674         flags = rte_le_to_cpu_32(resp->flags);
5675         HWRM_UNLOCK();
5676
5677         if (!up)
5678                 return 0;
5679
5680         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5681                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5682                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5683         }
5684
5685         return 0;
5686 }
5687
5688 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5689 {
5690         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5691         struct bnxt_error_recovery_info *info = bp->recovery_info;
5692         struct hwrm_error_recovery_qcfg_input req = {0};
5693         uint32_t flags = 0;
5694         unsigned int i;
5695         int rc;
5696
5697         /* Older FW does not have error recovery support */
5698         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5699                 return 0;
5700
5701         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5702
5703         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5704
5705         HWRM_CHECK_RESULT();
5706
5707         flags = rte_le_to_cpu_32(resp->flags);
5708         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5709                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5710         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5711                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5712
5713         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5714             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5715                 rc = -EINVAL;
5716                 goto err;
5717         }
5718
5719         /* FW returned values are in units of 100msec */
5720         info->driver_polling_freq =
5721                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5722         info->primary_func_wait_period =
5723                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5724         info->normal_func_wait_period =
5725                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5726         info->primary_func_wait_period_after_reset =
5727                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5728         info->max_bailout_time_after_reset =
5729                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5730         info->status_regs[BNXT_FW_STATUS_REG] =
5731                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5732         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5733                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5734         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5735                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5736         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5737                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5738         info->reg_array_cnt =
5739                 rte_le_to_cpu_32(resp->reg_array_cnt);
5740
5741         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5742                 rc = -EINVAL;
5743                 goto err;
5744         }
5745
5746         for (i = 0; i < info->reg_array_cnt; i++) {
5747                 info->reset_reg[i] =
5748                         rte_le_to_cpu_32(resp->reset_reg[i]);
5749                 info->reset_reg_val[i] =
5750                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5751                 info->delay_after_reset[i] =
5752                         resp->delay_after_reset[i];
5753         }
5754 err:
5755         HWRM_UNLOCK();
5756
5757         /* Map the FW status registers */
5758         if (!rc)
5759                 rc = bnxt_map_fw_health_status_regs(bp);
5760
5761         if (rc) {
5762                 rte_free(bp->recovery_info);
5763                 bp->recovery_info = NULL;
5764         }
5765         return rc;
5766 }
5767
5768 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5769 {
5770         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5771         struct hwrm_fw_reset_input req = {0};
5772         int rc;
5773
5774         if (!BNXT_PF(bp))
5775                 return -EOPNOTSUPP;
5776
5777         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5778
5779         req.embedded_proc_type =
5780                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5781         req.selfrst_status =
5782                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5783         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5784
5785         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5786                                     BNXT_USE_KONG(bp));
5787
5788         HWRM_CHECK_RESULT();
5789         HWRM_UNLOCK();
5790
5791         return rc;
5792 }
5793
5794 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5795 {
5796         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5797         struct hwrm_port_ts_query_input req = {0};
5798         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5799         uint32_t flags = 0;
5800         int rc;
5801
5802         if (!ptp)
5803                 return 0;
5804
5805         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5806
5807         switch (path) {
5808         case BNXT_PTP_FLAGS_PATH_TX:
5809                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5810                 break;
5811         case BNXT_PTP_FLAGS_PATH_RX:
5812                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5813                 break;
5814         case BNXT_PTP_FLAGS_CURRENT_TIME:
5815                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5816                 break;
5817         }
5818
5819         req.flags = rte_cpu_to_le_32(flags);
5820         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5821
5822         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5823
5824         HWRM_CHECK_RESULT();
5825
5826         if (timestamp) {
5827                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5828                 *timestamp |=
5829                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5830         }
5831         HWRM_UNLOCK();
5832
5833         return rc;
5834 }
5835
5836 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5837 {
5838         int rc = 0;
5839
5840         struct hwrm_cfa_counter_qcaps_input req = {0};
5841         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5842
5843         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5844                 PMD_DRV_LOG(DEBUG,
5845                             "Not a PF or trusted VF. Command not supported\n");
5846                 return 0;
5847         }
5848
5849         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5850         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5852
5853         HWRM_CHECK_RESULT();
5854         if (max_fc)
5855                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5856         HWRM_UNLOCK();
5857
5858         return 0;
5859 }
5860
5861 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5862 {
5863         int rc = 0;
5864         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5865         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5866
5867         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5868                 PMD_DRV_LOG(DEBUG,
5869                             "Not a PF or trusted VF. Command not supported\n");
5870                 return 0;
5871         }
5872
5873         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5874
5875         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5876         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5877         req.page_dir = rte_cpu_to_le_64(dma_addr);
5878
5879         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5880
5881         HWRM_CHECK_RESULT();
5882         if (ctx_id) {
5883                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5884                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5885         }
5886         HWRM_UNLOCK();
5887
5888         return 0;
5889 }
5890
5891 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5892 {
5893         int rc = 0;
5894         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5895         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5896
5897         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5898                 PMD_DRV_LOG(DEBUG,
5899                             "Not a PF or trusted VF. Command not supported\n");
5900                 return 0;
5901         }
5902
5903         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5904
5905         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5906
5907         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5908
5909         HWRM_CHECK_RESULT();
5910         HWRM_UNLOCK();
5911
5912         return rc;
5913 }
5914
5915 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5916                               uint16_t cntr, uint16_t ctx_id,
5917                               uint32_t num_entries, bool enable)
5918 {
5919         struct hwrm_cfa_counter_cfg_input req = {0};
5920         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5921         uint16_t flags = 0;
5922         int rc;
5923
5924         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5925                 PMD_DRV_LOG(DEBUG,
5926                             "Not a PF or trusted VF. Command not supported\n");
5927                 return 0;
5928         }
5929
5930         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5931
5932         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5933         req.counter_type = rte_cpu_to_le_16(cntr);
5934         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5935                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5936         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5937         if (dir == BNXT_DIR_RX)
5938                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5939         else if (dir == BNXT_DIR_TX)
5940                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5941         req.flags = rte_cpu_to_le_16(flags);
5942         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5943         req.num_entries = rte_cpu_to_le_32(num_entries);
5944
5945         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5946         HWRM_CHECK_RESULT();
5947         HWRM_UNLOCK();
5948
5949         return 0;
5950 }
5951
5952 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5953                                  enum bnxt_flow_dir dir,
5954                                  uint16_t cntr,
5955                                  uint16_t num_entries)
5956 {
5957         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5958         struct hwrm_cfa_counter_qstats_input req = {0};
5959         uint16_t flow_ctx_id = 0;
5960         uint16_t flags = 0;
5961         int rc = 0;
5962
5963         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5964                 PMD_DRV_LOG(DEBUG,
5965                             "Not a PF or trusted VF. Command not supported\n");
5966                 return 0;
5967         }
5968
5969         if (dir == BNXT_DIR_RX) {
5970                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5971                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5972         } else if (dir == BNXT_DIR_TX) {
5973                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5974                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5975         }
5976
5977         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5978         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5979         req.counter_type = rte_cpu_to_le_16(cntr);
5980         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5981         req.num_entries = rte_cpu_to_le_16(num_entries);
5982         req.flags = rte_cpu_to_le_16(flags);
5983         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5984
5985         HWRM_CHECK_RESULT();
5986         HWRM_UNLOCK();
5987
5988         return 0;
5989 }
5990
5991 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5992                                 uint16_t *first_vf_id)
5993 {
5994         int rc = 0;
5995         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5996         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5997
5998         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5999
6000         req.fid = rte_cpu_to_le_16(fid);
6001
6002         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6003
6004         HWRM_CHECK_RESULT();
6005
6006         if (first_vf_id)
6007                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
6008
6009         HWRM_UNLOCK();
6010
6011         return rc;
6012 }
6013
6014 int bnxt_hwrm_cfa_pair_exists(struct bnxt *bp, struct bnxt_representor *rep_bp)
6015 {
6016         struct hwrm_cfa_pair_info_output *resp = bp->hwrm_cmd_resp_addr;
6017         struct hwrm_cfa_pair_info_input req = {0};
6018         int rc = 0;
6019
6020         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6021                 PMD_DRV_LOG(DEBUG,
6022                             "Not a PF or trusted VF. Command not supported\n");
6023                 return 0;
6024         }
6025
6026         HWRM_PREP(&req, HWRM_CFA_PAIR_INFO, BNXT_USE_CHIMP_MB);
6027         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6028                  bp->eth_dev->data->name, rep_bp->vf_id);
6029         req.flags =
6030                 rte_cpu_to_le_32(HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE);
6031
6032         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6033         HWRM_CHECK_RESULT();
6034         if (rc == HWRM_ERR_CODE_SUCCESS && strlen(resp->pair_name)) {
6035                 HWRM_UNLOCK();
6036                 return !rc;
6037         }
6038         HWRM_UNLOCK();
6039         return rc;
6040 }
6041
6042 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6043 {
6044         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6045         struct hwrm_cfa_pair_alloc_input req = {0};
6046         int rc;
6047
6048         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6049                 PMD_DRV_LOG(DEBUG,
6050                             "Not a PF or trusted VF. Command not supported\n");
6051                 return 0;
6052         }
6053
6054         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6055         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6056         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6057                  bp->eth_dev->data->name, rep_bp->vf_id);
6058
6059         req.pf_b_id = rep_bp->parent_pf_idx;
6060         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6061                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6062         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6063         req.host_b_id = 1; /* TBD - Confirm if this is OK */
6064
6065         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6066                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6067         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6068                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6069         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6070                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6071         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6072                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6073
6074         req.q_ab = rep_bp->rep_q_r2f;
6075         req.q_ba = rep_bp->rep_q_f2r;
6076         req.fc_ab = rep_bp->rep_fc_r2f;
6077         req.fc_ba = rep_bp->rep_fc_f2r;
6078
6079         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6080         HWRM_CHECK_RESULT();
6081
6082         HWRM_UNLOCK();
6083         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6084                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6085         return rc;
6086 }
6087
6088 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6089 {
6090         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6091         struct hwrm_cfa_pair_free_input req = {0};
6092         int rc;
6093
6094         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6095                 PMD_DRV_LOG(DEBUG,
6096                             "Not a PF or trusted VF. Command not supported\n");
6097                 return 0;
6098         }
6099
6100         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6101         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6102                  bp->eth_dev->data->name, rep_bp->vf_id);
6103         req.pf_b_id = rep_bp->parent_pf_idx;
6104         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6105         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6106                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6107         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6108         HWRM_CHECK_RESULT();
6109         HWRM_UNLOCK();
6110         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6111                     rep_bp->vf_id);
6112         return rc;
6113 }
6114
6115 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6116                             uint32_t echo_req_data2)
6117 {
6118         struct hwrm_func_echo_response_input req = {0};
6119         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6120         int rc;
6121
6122         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6123         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6124         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6125
6126         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6127
6128         HWRM_CHECK_RESULT();
6129         HWRM_UNLOCK();
6130
6131         return rc;
6132 }
6133
6134 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6135 {
6136         struct hwrm_ver_get_input req = {.req_type = 0 };
6137         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6138         int rc = 0;
6139
6140         bp->max_req_len = HWRM_MAX_REQ_LEN;
6141         bp->max_resp_len = BNXT_PAGE_SIZE;
6142         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6143
6144         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6145         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6146         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6147         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6148
6149         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6150
6151         HWRM_CHECK_RESULT_SILENT();
6152         HWRM_UNLOCK();
6153
6154         return rc;
6155 }
6156
6157 int bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt *bp, uint16_t i2c_addr,
6158                                           uint16_t page_number, uint16_t start_addr,
6159                                           uint16_t data_length, uint8_t *buf)
6160 {
6161         struct hwrm_port_phy_i2c_read_output *resp = bp->hwrm_cmd_resp_addr;
6162         struct hwrm_port_phy_i2c_read_input req = {0};
6163         uint32_t enables = HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET;
6164         int rc, byte_offset = 0;
6165
6166         do {
6167                 uint16_t xfer_size;
6168
6169                 HWRM_PREP(&req, HWRM_PORT_PHY_I2C_READ, BNXT_USE_CHIMP_MB);
6170                 req.i2c_slave_addr = i2c_addr;
6171                 req.page_number = rte_cpu_to_le_16(page_number);
6172                 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
6173
6174                 xfer_size = RTE_MIN(data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
6175                 req.page_offset = rte_cpu_to_le_16(start_addr + byte_offset);
6176                 req.data_length = xfer_size;
6177                 req.enables = rte_cpu_to_le_32(start_addr + byte_offset ? enables : 0);
6178                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6179                 HWRM_CHECK_RESULT();
6180
6181                 memcpy(buf + byte_offset, resp->data, xfer_size);
6182
6183                 data_length -= xfer_size;
6184                 byte_offset += xfer_size;
6185
6186                 HWRM_UNLOCK();
6187         } while (data_length > 0);
6188
6189         return rc;
6190 }
6191
6192 void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index)
6193 {
6194         struct bnxt_tx_queue *txq = bp->tx_queues[queue_index];
6195         struct bnxt_tx_ring_info *txr = txq->tx_ring;
6196         struct bnxt_ring *ring = txr->tx_ring_struct;
6197         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
6198
6199         bnxt_hwrm_ring_free(bp, ring,
6200                             HWRM_RING_FREE_INPUT_RING_TYPE_TX,
6201                             cpr->cp_ring_struct->fw_ring_id);
6202         txr->tx_raw_prod = 0;
6203         txr->tx_raw_cons = 0;
6204         memset(txr->tx_desc_ring, 0,
6205                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_desc_ring));
6206         memset(txr->tx_buf_ring, 0,
6207                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_buf_ring));
6208
6209         bnxt_hwrm_stat_ctx_free(bp, cpr);
6210
6211         bnxt_free_cp_ring(bp, cpr);
6212 }
6213
6214 int bnxt_hwrm_config_host_mtu(struct bnxt *bp)
6215 {
6216         struct hwrm_func_cfg_input req = {0};
6217         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
6218         int rc;
6219
6220         if (!BNXT_PF(bp))
6221                 return 0;
6222
6223         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
6224
6225         req.fid = rte_cpu_to_le_16(0xffff);
6226         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU);
6227         req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
6228
6229         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6230         HWRM_CHECK_RESULT();
6231         HWRM_UNLOCK();
6232
6233         return rc;
6234 }
6235
6236 int
6237 bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
6238 {
6239         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
6240         struct hwrm_vnic_rss_cfg_input req = {0};
6241         int nr_ctxs = vnic->num_lb_ctxts;
6242         int i, rc = 0;
6243
6244         for (i = 0; i < nr_ctxs; i++) {
6245                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
6246
6247                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
6248                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
6249
6250                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6251
6252                 HWRM_CHECK_RESULT();
6253                 HWRM_UNLOCK();
6254         }
6255
6256         return rc;
6257 }