1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
16 #include "bnxt_filter.h"
17 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_vnic.h"
24 #include "hsi_struct_def_dpdk.h"
28 #define HWRM_CMD_TIMEOUT 6000000
29 #define HWRM_SHORT_CMD_TIMEOUT 50000
30 #define HWRM_SPEC_CODE_1_8_3 0x10803
31 #define HWRM_VERSION_1_9_1 0x10901
32 #define HWRM_VERSION_1_9_2 0x10903
34 struct bnxt_plcmodes_cfg {
36 uint16_t jumbo_thresh;
38 uint16_t hds_threshold;
41 static int page_getenum(size_t size)
57 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
58 return sizeof(void *) * 8 - 1;
61 static int page_roundup(size_t size)
63 return 1 << page_getenum(size);
66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
79 * HWRM Functions (sent to HWRM)
80 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
81 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
82 * command was failed by the ChiMP.
85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
86 uint32_t msg_len, bool use_kong_mb)
89 struct input *req = msg;
90 struct output *resp = bp->hwrm_cmd_resp_addr;
94 uint16_t max_req_len = bp->max_req_len;
95 struct hwrm_short_input short_input = { 0 };
96 uint16_t bar_offset = use_kong_mb ?
97 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
98 uint16_t mb_trigger_offset = use_kong_mb ?
99 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
102 /* Do not send HWRM commands to firmware in error state */
103 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
106 /* For VER_GET command, set timeout as 50ms */
107 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
108 timeout = HWRM_SHORT_CMD_TIMEOUT;
110 timeout = HWRM_CMD_TIMEOUT;
112 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
113 msg_len > bp->max_req_len) {
114 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
116 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
117 memcpy(short_cmd_req, req, msg_len);
119 short_input.req_type = rte_cpu_to_le_16(req->req_type);
120 short_input.signature = rte_cpu_to_le_16(
121 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
122 short_input.size = rte_cpu_to_le_16(msg_len);
123 short_input.req_addr =
124 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
126 data = (uint32_t *)&short_input;
127 msg_len = sizeof(short_input);
129 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
132 /* Write request msg to hwrm channel */
133 for (i = 0; i < msg_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + bar_offset + i;
135 rte_write32(*data, bar);
139 /* Zero the rest of the request space */
140 for (; i < max_req_len; i += 4) {
141 bar = (uint8_t *)bp->bar0 + bar_offset + i;
145 /* Ring channel doorbell */
146 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
149 * Make sure the channel doorbell ring command complete before
150 * reading the response to avoid getting stale or invalid
155 /* Poll for the valid bit */
156 for (i = 0; i < timeout; i++) {
157 /* Sanity check on the resp->resp_len */
159 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
160 /* Last byte of resp contains the valid key */
161 valid = (uint8_t *)resp + resp->resp_len - 1;
162 if (*valid == HWRM_RESP_VALID_KEY)
169 /* Suppress VER_GET timeout messages during reset recovery */
170 if (bp->flags & BNXT_FLAG_FW_RESET &&
171 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
174 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
182 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
183 * spinlock, and does initial processing.
185 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
186 * releases the spinlock only if it returns. If the regular int return codes
187 * are not used by the function, HWRM_CHECK_RESULT() should not be used
188 * directly, rather it should be copied and modified to suit the function.
190 * HWRM_UNLOCK() must be called after all response processing is completed.
192 #define HWRM_PREP(req, type, kong) do { \
193 rte_spinlock_lock(&bp->hwrm_lock); \
194 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
195 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
196 req.cmpl_ring = rte_cpu_to_le_16(-1); \
197 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
198 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
199 req.target_id = rte_cpu_to_le_16(0xffff); \
200 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
203 #define HWRM_CHECK_RESULT_SILENT() do {\
205 rte_spinlock_unlock(&bp->hwrm_lock); \
208 if (resp->error_code) { \
209 rc = rte_le_to_cpu_16(resp->error_code); \
210 rte_spinlock_unlock(&bp->hwrm_lock); \
215 #define HWRM_CHECK_RESULT() do {\
217 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
218 rte_spinlock_unlock(&bp->hwrm_lock); \
219 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
221 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
223 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
225 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
231 if (resp->error_code) { \
232 rc = rte_le_to_cpu_16(resp->error_code); \
233 if (resp->resp_len >= 16) { \
234 struct hwrm_err_output *tmp_hwrm_err_op = \
237 "error %d:%d:%08x:%04x\n", \
238 rc, tmp_hwrm_err_op->cmd_err, \
240 tmp_hwrm_err_op->opaque_0), \
242 tmp_hwrm_err_op->opaque_1)); \
244 PMD_DRV_LOG(ERR, "error %d\n", rc); \
246 rte_spinlock_unlock(&bp->hwrm_lock); \
247 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
249 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
251 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
253 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
261 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
263 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
266 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
267 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
269 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
270 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
273 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
281 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
282 struct bnxt_vnic_info *vnic,
284 struct bnxt_vlan_table_entry *vlan_table)
287 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
288 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
291 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
294 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
295 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
297 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
298 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
299 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
300 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
302 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
303 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
305 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
306 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
307 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
308 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
309 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
310 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
313 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
314 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
315 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
316 rte_mem_virt2iova(vlan_table));
317 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
319 req.mask = rte_cpu_to_le_32(mask);
321 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
329 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
331 struct bnxt_vlan_antispoof_table_entry *vlan_table)
334 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
335 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
336 bp->hwrm_cmd_resp_addr;
339 * Older HWRM versions did not support this command, and the set_rx_mask
340 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
341 * removed from set_rx_mask call, and this command was added.
343 * This command is also present from 1.7.8.11 and higher,
346 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
347 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
348 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
353 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
354 req.fid = rte_cpu_to_le_16(fid);
356 req.vlan_tag_mask_tbl_addr =
357 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
358 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
360 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
368 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
369 struct bnxt_filter_info *filter)
372 struct bnxt_filter_info *l2_filter = filter;
373 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
374 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
376 if (filter->fw_l2_filter_id == UINT64_MAX)
379 if (filter->matching_l2_fltr_ptr)
380 l2_filter = filter->matching_l2_fltr_ptr;
382 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
383 filter, l2_filter, l2_filter->l2_ref_cnt);
385 if (l2_filter->l2_ref_cnt > 0)
386 l2_filter->l2_ref_cnt--;
388 if (l2_filter->l2_ref_cnt > 0)
391 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
393 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
395 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
400 filter->fw_l2_filter_id = UINT64_MAX;
405 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
407 struct bnxt_filter_info *filter)
410 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
411 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
412 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
413 const struct rte_eth_vmdq_rx_conf *conf =
414 &dev_conf->rx_adv_conf.vmdq_rx_conf;
415 uint32_t enables = 0;
416 uint16_t j = dst_id - 1;
418 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
419 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
420 conf->pool_map[j].pools & (1UL << j)) {
422 "Add vlan %u to vmdq pool %u\n",
423 conf->pool_map[j].vlan_id, j);
425 filter->l2_ivlan = conf->pool_map[j].vlan_id;
427 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
428 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
431 if (filter->fw_l2_filter_id != UINT64_MAX)
432 bnxt_hwrm_clear_l2_filter(bp, filter);
434 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
436 req.flags = rte_cpu_to_le_32(filter->flags);
438 enables = filter->enables |
439 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
440 req.dst_id = rte_cpu_to_le_16(dst_id);
443 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
444 memcpy(req.l2_addr, filter->l2_addr,
447 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
448 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
451 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
452 req.l2_ovlan = filter->l2_ovlan;
454 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
455 req.l2_ivlan = filter->l2_ivlan;
457 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
458 req.l2_ovlan_mask = filter->l2_ovlan_mask;
460 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
461 req.l2_ivlan_mask = filter->l2_ivlan_mask;
462 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
463 req.src_id = rte_cpu_to_le_32(filter->src_id);
464 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
465 req.src_type = filter->src_type;
466 if (filter->pri_hint) {
467 req.pri_hint = filter->pri_hint;
468 req.l2_filter_id_hint =
469 rte_cpu_to_le_64(filter->l2_filter_id_hint);
472 req.enables = rte_cpu_to_le_32(enables);
474 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
478 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
484 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
486 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
487 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
494 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
497 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
500 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
501 if (ptp->tx_tstamp_en)
502 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
505 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
506 req.flags = rte_cpu_to_le_32(flags);
507 req.enables = rte_cpu_to_le_32
508 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
509 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
511 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
517 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
520 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
521 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
522 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
524 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
528 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
530 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
532 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
536 if (!BNXT_CHIP_THOR(bp) &&
537 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
540 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
541 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
543 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
547 if (!BNXT_CHIP_THOR(bp)) {
548 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
549 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
550 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
551 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
552 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
553 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
554 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
555 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
556 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
557 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
558 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
559 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
560 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
561 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
562 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
563 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
564 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
565 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
574 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
577 struct hwrm_func_qcaps_input req = {.req_type = 0 };
578 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
579 uint16_t new_max_vfs;
583 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
585 req.fid = rte_cpu_to_le_16(0xffff);
587 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
591 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
592 flags = rte_le_to_cpu_32(resp->flags);
594 bp->pf.port_id = resp->port_id;
595 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
596 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
597 new_max_vfs = bp->pdev->max_vfs;
598 if (new_max_vfs != bp->pf.max_vfs) {
600 rte_free(bp->pf.vf_info);
601 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
602 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
603 bp->pf.max_vfs = new_max_vfs;
604 for (i = 0; i < new_max_vfs; i++) {
605 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
606 bp->pf.vf_info[i].vlan_table =
607 rte_zmalloc("VF VLAN table",
610 if (bp->pf.vf_info[i].vlan_table == NULL)
612 "Fail to alloc VLAN table for VF %d\n",
616 bp->pf.vf_info[i].vlan_table);
617 bp->pf.vf_info[i].vlan_as_table =
618 rte_zmalloc("VF VLAN AS table",
621 if (bp->pf.vf_info[i].vlan_as_table == NULL)
623 "Alloc VLAN AS table for VF %d fail\n",
627 bp->pf.vf_info[i].vlan_as_table);
628 STAILQ_INIT(&bp->pf.vf_info[i].filter);
633 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
634 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
635 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
636 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
637 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
638 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
639 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
640 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
641 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
642 if (!BNXT_CHIP_THOR(bp))
643 bp->max_l2_ctx += bp->max_rx_em_flows;
644 /* TODO: For now, do not support VMDq/RFS on VFs. */
649 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
653 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
655 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
656 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
657 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
658 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
660 bnxt_hwrm_ptp_qcfg(bp);
664 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
665 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
667 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
668 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
669 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
671 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
674 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
675 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
677 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
684 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
688 rc = __bnxt_hwrm_func_qcaps(bp);
689 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
690 rc = bnxt_alloc_ctx_mem(bp);
694 rc = bnxt_hwrm_func_resc_qcaps(bp);
696 bp->flags |= BNXT_FLAG_NEW_RM;
702 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
703 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
706 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
707 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
709 HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
711 req.target_id = rte_cpu_to_le_16(0xffff);
713 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
717 if (rte_le_to_cpu_32(resp->flags) &
718 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
719 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
720 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
723 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
730 int bnxt_hwrm_func_reset(struct bnxt *bp)
733 struct hwrm_func_reset_input req = {.req_type = 0 };
734 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
736 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
738 req.enables = rte_cpu_to_le_32(0);
740 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
748 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
752 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
753 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
755 if (bp->flags & BNXT_FLAG_REGISTERED)
758 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
759 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
760 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
762 /* PFs and trusted VFs should indicate the support of the
763 * Master capability on non Stingray platform
765 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
766 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
768 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
769 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
770 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
771 req.ver_maj = RTE_VER_YEAR;
772 req.ver_min = RTE_VER_MONTH;
773 req.ver_upd = RTE_VER_MINOR;
776 req.enables |= rte_cpu_to_le_32(
777 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
778 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
779 RTE_MIN(sizeof(req.vf_req_fwd),
780 sizeof(bp->pf.vf_req_fwd)));
783 * PF can sniff HWRM API issued by VF. This can be set up by
784 * linux driver and inherited by the DPDK PF driver. Clear
785 * this HWRM sniffer list in FW because DPDK PF driver does
788 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
791 req.flags = rte_cpu_to_le_32(flags);
793 req.async_event_fwd[0] |=
794 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
795 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
796 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
797 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
798 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
799 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
800 req.async_event_fwd[0] |=
801 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
802 req.async_event_fwd[1] |=
803 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
804 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
806 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
810 flags = rte_le_to_cpu_32(resp->flags);
811 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
812 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
816 bp->flags |= BNXT_FLAG_REGISTERED;
821 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
823 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
826 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
829 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
834 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
835 struct hwrm_func_vf_cfg_input req = {0};
837 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
839 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
840 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
841 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
842 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
843 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
845 if (BNXT_HAS_RING_GRPS(bp)) {
846 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
847 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
850 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
851 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
852 AGG_RING_MULTIPLIER);
853 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
854 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
856 BNXT_NUM_ASYNC_CPR(bp));
857 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
858 if (bp->vf_resv_strategy ==
859 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
860 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
861 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
862 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
863 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
864 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
865 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
869 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
870 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
871 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
872 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
873 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
874 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
876 if (test && BNXT_HAS_RING_GRPS(bp))
877 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
879 req.flags = rte_cpu_to_le_32(flags);
880 req.enables |= rte_cpu_to_le_32(enables);
882 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
885 HWRM_CHECK_RESULT_SILENT();
893 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
896 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
897 struct hwrm_func_resource_qcaps_input req = {0};
899 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
900 req.fid = rte_cpu_to_le_16(0xffff);
902 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
907 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
908 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
909 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
910 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
911 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
912 /* func_resource_qcaps does not return max_rx_em_flows.
913 * So use the value provided by func_qcaps.
915 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
916 if (!BNXT_CHIP_THOR(bp))
917 bp->max_l2_ctx += bp->max_rx_em_flows;
918 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
919 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
921 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
922 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
923 if (bp->vf_resv_strategy >
924 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
925 bp->vf_resv_strategy =
926 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
932 int bnxt_hwrm_ver_get(struct bnxt *bp)
935 struct hwrm_ver_get_input req = {.req_type = 0 };
936 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
938 uint16_t max_resp_len;
939 char type[RTE_MEMZONE_NAMESIZE];
940 uint32_t dev_caps_cfg;
942 bp->max_req_len = HWRM_MAX_REQ_LEN;
943 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
945 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
946 req.hwrm_intf_min = HWRM_VERSION_MINOR;
947 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
949 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
951 if (bp->flags & BNXT_FLAG_FW_RESET)
952 HWRM_CHECK_RESULT_SILENT();
956 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
957 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
958 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
959 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
960 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
961 (resp->hwrm_fw_min_8b << 16) |
962 (resp->hwrm_fw_bld_8b << 8) |
963 resp->hwrm_fw_rsvd_8b;
964 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
965 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
967 fw_version = resp->hwrm_intf_maj_8b << 16;
968 fw_version |= resp->hwrm_intf_min_8b << 8;
969 fw_version |= resp->hwrm_intf_upd_8b;
970 bp->hwrm_spec_code = fw_version;
972 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
973 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
978 if (bp->max_req_len > resp->max_req_win_len) {
979 PMD_DRV_LOG(ERR, "Unsupported request length\n");
982 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
983 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
984 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
985 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
987 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
988 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
990 if (bp->max_resp_len != max_resp_len) {
991 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
992 bp->pdev->addr.domain, bp->pdev->addr.bus,
993 bp->pdev->addr.devid, bp->pdev->addr.function);
995 rte_free(bp->hwrm_cmd_resp_addr);
997 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
998 if (bp->hwrm_cmd_resp_addr == NULL) {
1002 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1003 bp->hwrm_cmd_resp_dma_addr =
1004 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1005 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1007 "Unable to map response buffer to physical memory.\n");
1011 bp->max_resp_len = max_resp_len;
1015 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1017 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1018 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1019 bp->flags |= BNXT_FLAG_SHORT_CMD;
1022 if (((dev_caps_cfg &
1023 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1025 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1026 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1027 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1028 bp->pdev->addr.domain, bp->pdev->addr.bus,
1029 bp->pdev->addr.devid, bp->pdev->addr.function);
1031 rte_free(bp->hwrm_short_cmd_req_addr);
1033 bp->hwrm_short_cmd_req_addr =
1034 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1035 if (bp->hwrm_short_cmd_req_addr == NULL) {
1039 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1040 bp->hwrm_short_cmd_req_dma_addr =
1041 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1042 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1043 rte_free(bp->hwrm_short_cmd_req_addr);
1045 "Unable to map buffer to physical memory.\n");
1051 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1052 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1053 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1056 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1057 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1059 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1060 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1061 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1069 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1072 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1073 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1075 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1078 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1081 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1083 HWRM_CHECK_RESULT();
1089 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1092 struct hwrm_port_phy_cfg_input req = {0};
1093 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1094 uint32_t enables = 0;
1096 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1098 if (conf->link_up) {
1099 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1100 if (bp->link_info.auto_mode && conf->link_speed) {
1101 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1102 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1105 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1106 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1107 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1109 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1110 * any auto mode, even "none".
1112 if (!conf->link_speed) {
1113 /* No speeds specified. Enable AutoNeg - all speeds */
1115 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1117 /* AutoNeg - Advertise speeds specified. */
1118 if (conf->auto_link_speed_mask &&
1119 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1121 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1122 req.auto_link_speed_mask =
1123 conf->auto_link_speed_mask;
1125 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1128 req.auto_duplex = conf->duplex;
1129 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1130 req.auto_pause = conf->auto_pause;
1131 req.force_pause = conf->force_pause;
1132 /* Set force_pause if there is no auto or if there is a force */
1133 if (req.auto_pause && !req.force_pause)
1134 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1136 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1138 req.enables = rte_cpu_to_le_32(enables);
1141 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1142 PMD_DRV_LOG(INFO, "Force Link Down\n");
1145 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1147 HWRM_CHECK_RESULT();
1153 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1154 struct bnxt_link_info *link_info)
1157 struct hwrm_port_phy_qcfg_input req = {0};
1158 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1160 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1162 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1164 HWRM_CHECK_RESULT();
1166 link_info->phy_link_status = resp->link;
1167 link_info->link_up =
1168 (link_info->phy_link_status ==
1169 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1170 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1171 link_info->duplex = resp->duplex_cfg;
1172 link_info->pause = resp->pause;
1173 link_info->auto_pause = resp->auto_pause;
1174 link_info->force_pause = resp->force_pause;
1175 link_info->auto_mode = resp->auto_mode;
1176 link_info->phy_type = resp->phy_type;
1177 link_info->media_type = resp->media_type;
1179 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1180 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1181 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1182 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1183 link_info->phy_ver[0] = resp->phy_maj;
1184 link_info->phy_ver[1] = resp->phy_min;
1185 link_info->phy_ver[2] = resp->phy_bld;
1189 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1190 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1191 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1192 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1193 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1194 link_info->auto_link_speed_mask);
1195 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1196 link_info->force_link_speed);
1201 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1204 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1205 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1206 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1210 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1212 req.flags = rte_cpu_to_le_32(dir);
1213 /* HWRM Version >= 1.9.1 */
1214 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1216 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1217 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1219 HWRM_CHECK_RESULT();
1221 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1222 GET_TX_QUEUE_INFO(0);
1223 GET_TX_QUEUE_INFO(1);
1224 GET_TX_QUEUE_INFO(2);
1225 GET_TX_QUEUE_INFO(3);
1226 GET_TX_QUEUE_INFO(4);
1227 GET_TX_QUEUE_INFO(5);
1228 GET_TX_QUEUE_INFO(6);
1229 GET_TX_QUEUE_INFO(7);
1231 GET_RX_QUEUE_INFO(0);
1232 GET_RX_QUEUE_INFO(1);
1233 GET_RX_QUEUE_INFO(2);
1234 GET_RX_QUEUE_INFO(3);
1235 GET_RX_QUEUE_INFO(4);
1236 GET_RX_QUEUE_INFO(5);
1237 GET_RX_QUEUE_INFO(6);
1238 GET_RX_QUEUE_INFO(7);
1243 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1246 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1247 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1251 /* iterate and find the COSq profile to use for Tx */
1252 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1253 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1254 if (bp->tx_cos_queue[i].id != 0xff)
1255 bp->tx_cosq_id[j++] =
1256 bp->tx_cos_queue[i].id;
1259 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1260 if (bp->tx_cos_queue[i].profile ==
1261 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1263 bp->tx_cos_queue[i].id;
1270 bp->max_tc = resp->max_configurable_queues;
1271 bp->max_lltc = resp->max_configurable_lossless_queues;
1272 if (bp->max_tc > BNXT_MAX_QUEUE)
1273 bp->max_tc = BNXT_MAX_QUEUE;
1274 bp->max_q = bp->max_tc;
1276 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1277 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1285 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1286 struct bnxt_ring *ring,
1287 uint32_t ring_type, uint32_t map_index,
1288 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1289 uint16_t tx_cosq_id)
1292 uint32_t enables = 0;
1293 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1294 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1295 struct rte_mempool *mb_pool;
1296 uint16_t rx_buf_size;
1298 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1300 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1301 req.fbo = rte_cpu_to_le_32(0);
1302 /* Association of ring index with doorbell index */
1303 req.logical_id = rte_cpu_to_le_16(map_index);
1304 req.length = rte_cpu_to_le_32(ring->ring_size);
1306 switch (ring_type) {
1307 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1308 req.ring_type = ring_type;
1309 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1310 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1311 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1312 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1314 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1316 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1317 req.ring_type = ring_type;
1318 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1319 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1320 if (BNXT_CHIP_THOR(bp)) {
1321 mb_pool = bp->rx_queues[0]->mb_pool;
1322 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1323 RTE_PKTMBUF_HEADROOM;
1324 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1325 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1327 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1329 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1331 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1333 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1334 req.ring_type = ring_type;
1335 if (BNXT_HAS_NQ(bp)) {
1336 /* Association of cp ring with nq */
1337 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1339 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1341 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1343 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1344 req.ring_type = ring_type;
1345 req.page_size = BNXT_PAGE_SHFT;
1346 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1348 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1349 req.ring_type = ring_type;
1350 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1352 mb_pool = bp->rx_queues[0]->mb_pool;
1353 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1354 RTE_PKTMBUF_HEADROOM;
1355 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1356 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1358 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1359 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1360 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1361 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1364 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1369 req.enables = rte_cpu_to_le_32(enables);
1371 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1373 if (rc || resp->error_code) {
1374 if (rc == 0 && resp->error_code)
1375 rc = rte_le_to_cpu_16(resp->error_code);
1376 switch (ring_type) {
1377 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1379 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1382 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1384 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1387 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1389 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1393 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1395 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1398 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1400 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1404 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1410 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1415 int bnxt_hwrm_ring_free(struct bnxt *bp,
1416 struct bnxt_ring *ring, uint32_t ring_type)
1419 struct hwrm_ring_free_input req = {.req_type = 0 };
1420 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1422 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1424 req.ring_type = ring_type;
1425 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1427 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1429 if (rc || resp->error_code) {
1430 if (rc == 0 && resp->error_code)
1431 rc = rte_le_to_cpu_16(resp->error_code);
1434 switch (ring_type) {
1435 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1436 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1439 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1440 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1443 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1444 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1447 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1449 "hwrm_ring_free nq failed. rc:%d\n", rc);
1451 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1453 "hwrm_ring_free agg failed. rc:%d\n", rc);
1456 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1464 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1467 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1468 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1470 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1472 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1473 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1474 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1475 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1477 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1479 HWRM_CHECK_RESULT();
1481 bp->grp_info[idx].fw_grp_id =
1482 rte_le_to_cpu_16(resp->ring_group_id);
1489 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1492 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1493 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1495 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1497 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1499 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1501 HWRM_CHECK_RESULT();
1504 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1508 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1511 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1512 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1514 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1517 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1519 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1523 HWRM_CHECK_RESULT();
1529 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1530 unsigned int idx __rte_unused)
1533 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1534 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1536 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1538 req.update_period_ms = rte_cpu_to_le_32(0);
1540 req.stats_dma_addr =
1541 rte_cpu_to_le_64(cpr->hw_stats_map);
1543 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1545 HWRM_CHECK_RESULT();
1547 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1554 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1555 unsigned int idx __rte_unused)
1558 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1559 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1561 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1563 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1565 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1567 HWRM_CHECK_RESULT();
1573 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1576 struct hwrm_vnic_alloc_input req = { 0 };
1577 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1579 if (!BNXT_HAS_RING_GRPS(bp))
1580 goto skip_ring_grps;
1582 /* map ring groups to this vnic */
1583 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1584 vnic->start_grp_id, vnic->end_grp_id);
1585 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1586 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1588 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1589 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1590 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1591 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1594 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1595 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1596 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1598 if (vnic->func_default)
1600 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1601 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1603 HWRM_CHECK_RESULT();
1605 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1607 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1611 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1612 struct bnxt_vnic_info *vnic,
1613 struct bnxt_plcmodes_cfg *pmode)
1616 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1617 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1619 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1621 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1623 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1625 HWRM_CHECK_RESULT();
1627 pmode->flags = rte_le_to_cpu_32(resp->flags);
1628 /* dflt_vnic bit doesn't exist in the _cfg command */
1629 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1630 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1631 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1632 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1639 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1640 struct bnxt_vnic_info *vnic,
1641 struct bnxt_plcmodes_cfg *pmode)
1644 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1645 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1647 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1648 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1652 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1654 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1655 req.flags = rte_cpu_to_le_32(pmode->flags);
1656 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1657 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1658 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1659 req.enables = rte_cpu_to_le_32(
1660 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1661 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1662 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1665 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1667 HWRM_CHECK_RESULT();
1673 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1676 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1677 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1678 struct bnxt_plcmodes_cfg pmodes = { 0 };
1679 uint32_t ctx_enable_flag = 0;
1680 uint32_t enables = 0;
1682 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1683 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1687 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1691 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1693 if (BNXT_CHIP_THOR(bp)) {
1694 struct bnxt_rx_queue *rxq =
1695 bp->eth_dev->data->rx_queues[vnic->start_grp_id];
1696 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1697 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1699 req.default_rx_ring_id =
1700 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1701 req.default_cmpl_ring_id =
1702 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1703 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1704 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1708 /* Only RSS support for now TBD: COS & LB */
1709 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1710 if (vnic->lb_rule != 0xffff)
1711 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1712 if (vnic->cos_rule != 0xffff)
1713 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1714 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1715 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1716 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1718 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1719 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1720 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1723 enables |= ctx_enable_flag;
1724 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1725 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1726 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1727 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1730 req.enables = rte_cpu_to_le_32(enables);
1731 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1732 req.mru = rte_cpu_to_le_16(vnic->mru);
1733 /* Configure default VNIC only once. */
1734 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1736 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1737 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1739 if (vnic->vlan_strip)
1741 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1744 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1745 if (vnic->roce_dual)
1746 req.flags |= rte_cpu_to_le_32(
1747 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1748 if (vnic->roce_only)
1749 req.flags |= rte_cpu_to_le_32(
1750 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1751 if (vnic->rss_dflt_cr)
1752 req.flags |= rte_cpu_to_le_32(
1753 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1755 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1757 HWRM_CHECK_RESULT();
1760 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1765 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1769 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1770 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1772 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1773 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1776 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1779 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1780 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1781 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1783 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1785 HWRM_CHECK_RESULT();
1787 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1788 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1789 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1790 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1791 vnic->mru = rte_le_to_cpu_16(resp->mru);
1792 vnic->func_default = rte_le_to_cpu_32(
1793 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1794 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1795 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1796 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1797 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1798 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1799 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1800 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1801 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1802 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1803 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1810 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1811 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1815 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1816 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1817 bp->hwrm_cmd_resp_addr;
1819 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1821 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1822 HWRM_CHECK_RESULT();
1824 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1825 if (!BNXT_HAS_RING_GRPS(bp))
1826 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1827 else if (ctx_idx == 0)
1828 vnic->rss_rule = ctx_id;
1836 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1837 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1840 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1841 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1842 bp->hwrm_cmd_resp_addr;
1844 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1845 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1848 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1850 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1852 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1854 HWRM_CHECK_RESULT();
1860 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1864 if (BNXT_CHIP_THOR(bp)) {
1867 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1868 rc = _bnxt_hwrm_vnic_ctx_free(bp,
1870 vnic->fw_grp_ids[j]);
1871 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1873 vnic->num_lb_ctxts = 0;
1875 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1876 vnic->rss_rule = INVALID_HW_RING_ID;
1882 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1885 struct hwrm_vnic_free_input req = {.req_type = 0 };
1886 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1888 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1889 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1893 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1895 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1897 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1899 HWRM_CHECK_RESULT();
1902 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1903 /* Configure default VNIC again if necessary. */
1904 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1905 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1911 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1915 int nr_ctxs = vnic->num_lb_ctxts;
1916 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1917 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1919 for (i = 0; i < nr_ctxs; i++) {
1920 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1922 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1923 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1924 req.hash_mode_flags = vnic->hash_mode;
1926 req.hash_key_tbl_addr =
1927 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1929 req.ring_grp_tbl_addr =
1930 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1931 i * HW_HASH_INDEX_SIZE);
1932 req.ring_table_pair_index = i;
1933 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1935 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1938 HWRM_CHECK_RESULT();
1945 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1946 struct bnxt_vnic_info *vnic)
1949 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1950 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1952 if (!vnic->rss_table)
1955 if (BNXT_CHIP_THOR(bp))
1956 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1958 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1960 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1961 req.hash_mode_flags = vnic->hash_mode;
1963 req.ring_grp_tbl_addr =
1964 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1965 req.hash_key_tbl_addr =
1966 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1967 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1968 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1970 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1972 HWRM_CHECK_RESULT();
1978 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1979 struct bnxt_vnic_info *vnic)
1982 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1983 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1986 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1987 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1991 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1993 req.flags = rte_cpu_to_le_32(
1994 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1996 req.enables = rte_cpu_to_le_32(
1997 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1999 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2000 size -= RTE_PKTMBUF_HEADROOM;
2001 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2003 req.jumbo_thresh = rte_cpu_to_le_16(size);
2004 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2006 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2008 HWRM_CHECK_RESULT();
2014 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2015 struct bnxt_vnic_info *vnic, bool enable)
2018 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2019 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2021 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2023 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2027 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2028 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2032 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2035 req.enables = rte_cpu_to_le_32(
2036 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2037 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2038 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2039 req.flags = rte_cpu_to_le_32(
2040 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2041 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2042 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2043 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2044 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2045 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2046 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2047 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2048 req.min_agg_len = rte_cpu_to_le_32(512);
2050 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2052 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2054 HWRM_CHECK_RESULT();
2060 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2062 struct hwrm_func_cfg_input req = {0};
2063 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2066 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2067 req.enables = rte_cpu_to_le_32(
2068 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2069 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2070 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2072 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2074 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2075 HWRM_CHECK_RESULT();
2078 bp->pf.vf_info[vf].random_mac = false;
2083 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2087 struct hwrm_func_qstats_input req = {.req_type = 0};
2088 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2090 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2092 req.fid = rte_cpu_to_le_16(fid);
2094 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2096 HWRM_CHECK_RESULT();
2099 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2106 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2107 struct rte_eth_stats *stats)
2110 struct hwrm_func_qstats_input req = {.req_type = 0};
2111 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2113 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2115 req.fid = rte_cpu_to_le_16(fid);
2117 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2119 HWRM_CHECK_RESULT();
2121 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2122 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2123 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2124 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2125 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2126 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2128 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2129 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2130 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2131 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2132 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2133 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2135 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2136 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2137 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2144 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2147 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2148 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2150 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2152 req.fid = rte_cpu_to_le_16(fid);
2154 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2156 HWRM_CHECK_RESULT();
2163 * HWRM utility functions
2166 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2171 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2172 struct bnxt_tx_queue *txq;
2173 struct bnxt_rx_queue *rxq;
2174 struct bnxt_cp_ring_info *cpr;
2176 if (i >= bp->rx_cp_nr_rings) {
2177 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2180 rxq = bp->rx_queues[i];
2184 rc = bnxt_hwrm_stat_clear(bp, cpr);
2191 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2195 struct bnxt_cp_ring_info *cpr;
2197 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2199 if (i >= bp->rx_cp_nr_rings) {
2200 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2202 cpr = bp->rx_queues[i]->cp_ring;
2203 if (BNXT_HAS_RING_GRPS(bp))
2204 bp->grp_info[i].fw_stats_ctx = -1;
2206 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2207 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2208 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2216 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2221 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2222 struct bnxt_tx_queue *txq;
2223 struct bnxt_rx_queue *rxq;
2224 struct bnxt_cp_ring_info *cpr;
2226 if (i >= bp->rx_cp_nr_rings) {
2227 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2230 rxq = bp->rx_queues[i];
2234 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2242 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2247 if (!BNXT_HAS_RING_GRPS(bp))
2250 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2252 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2255 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2263 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2265 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2267 bnxt_hwrm_ring_free(bp, cp_ring,
2268 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2269 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2270 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2271 sizeof(*cpr->cp_desc_ring));
2272 cpr->cp_raw_cons = 0;
2276 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2278 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2280 bnxt_hwrm_ring_free(bp, cp_ring,
2281 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2282 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2283 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2284 sizeof(*cpr->cp_desc_ring));
2285 cpr->cp_raw_cons = 0;
2289 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2291 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2292 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2293 struct bnxt_ring *ring = rxr->rx_ring_struct;
2294 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2296 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2297 bnxt_hwrm_ring_free(bp, ring,
2298 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2299 ring->fw_ring_id = INVALID_HW_RING_ID;
2300 if (BNXT_HAS_RING_GRPS(bp))
2301 bp->grp_info[queue_index].rx_fw_ring_id =
2303 memset(rxr->rx_desc_ring, 0,
2304 rxr->rx_ring_struct->ring_size *
2305 sizeof(*rxr->rx_desc_ring));
2306 memset(rxr->rx_buf_ring, 0,
2307 rxr->rx_ring_struct->ring_size *
2308 sizeof(*rxr->rx_buf_ring));
2311 ring = rxr->ag_ring_struct;
2312 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2313 bnxt_hwrm_ring_free(bp, ring,
2314 BNXT_CHIP_THOR(bp) ?
2315 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2316 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2317 ring->fw_ring_id = INVALID_HW_RING_ID;
2318 memset(rxr->ag_buf_ring, 0,
2319 rxr->ag_ring_struct->ring_size *
2320 sizeof(*rxr->ag_buf_ring));
2322 if (BNXT_HAS_RING_GRPS(bp))
2323 bp->grp_info[queue_index].ag_fw_ring_id =
2326 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2327 bnxt_free_cp_ring(bp, cpr);
2329 if (BNXT_HAS_RING_GRPS(bp))
2330 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2333 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2337 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2338 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2339 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2340 struct bnxt_ring *ring = txr->tx_ring_struct;
2341 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2343 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2344 bnxt_hwrm_ring_free(bp, ring,
2345 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2346 ring->fw_ring_id = INVALID_HW_RING_ID;
2347 memset(txr->tx_desc_ring, 0,
2348 txr->tx_ring_struct->ring_size *
2349 sizeof(*txr->tx_desc_ring));
2350 memset(txr->tx_buf_ring, 0,
2351 txr->tx_ring_struct->ring_size *
2352 sizeof(*txr->tx_buf_ring));
2356 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2357 bnxt_free_cp_ring(bp, cpr);
2358 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2362 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2363 bnxt_free_hwrm_rx_ring(bp, i);
2368 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2373 if (!BNXT_HAS_RING_GRPS(bp))
2376 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2377 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2384 void bnxt_free_hwrm_resources(struct bnxt *bp)
2386 /* Release memzone */
2387 rte_free(bp->hwrm_cmd_resp_addr);
2388 rte_free(bp->hwrm_short_cmd_req_addr);
2389 bp->hwrm_cmd_resp_addr = NULL;
2390 bp->hwrm_short_cmd_req_addr = NULL;
2391 bp->hwrm_cmd_resp_dma_addr = 0;
2392 bp->hwrm_short_cmd_req_dma_addr = 0;
2395 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2397 struct rte_pci_device *pdev = bp->pdev;
2398 char type[RTE_MEMZONE_NAMESIZE];
2400 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2401 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2402 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2403 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2404 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2405 if (bp->hwrm_cmd_resp_addr == NULL)
2407 bp->hwrm_cmd_resp_dma_addr =
2408 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2409 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2411 "unable to map response address to physical memory\n");
2414 rte_spinlock_init(&bp->hwrm_lock);
2419 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2421 struct bnxt_filter_info *filter;
2424 STAILQ_FOREACH(filter, &vnic->filter, next) {
2425 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2426 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2427 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2428 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2430 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2431 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2432 bnxt_free_filter(bp, filter);
2440 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2442 struct bnxt_filter_info *filter;
2443 struct rte_flow *flow;
2446 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2447 flow = STAILQ_FIRST(&vnic->flow_list);
2448 filter = flow->filter;
2449 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2450 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2451 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2452 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2453 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2455 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2457 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2465 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2467 struct bnxt_filter_info *filter;
2470 STAILQ_FOREACH(filter, &vnic->filter, next) {
2471 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2472 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2474 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2475 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2478 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2489 void bnxt_free_tunnel_ports(struct bnxt *bp)
2491 if (bp->vxlan_port_cnt)
2492 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2493 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2495 if (bp->geneve_port_cnt)
2496 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2497 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2498 bp->geneve_port = 0;
2501 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2505 if (bp->vnic_info == NULL)
2509 * Cleanup VNICs in reverse order, to make sure the L2 filter
2510 * from vnic0 is last to be cleaned up.
2512 for (i = bp->max_vnics - 1; i >= 0; i--) {
2513 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2515 // If the VNIC ID is invalid we are not currently using the VNIC
2516 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2519 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2521 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2523 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2525 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2527 bnxt_hwrm_vnic_free(bp, vnic);
2529 rte_free(vnic->fw_grp_ids);
2531 /* Ring resources */
2532 bnxt_free_all_hwrm_rings(bp);
2533 bnxt_free_all_hwrm_ring_grps(bp);
2534 bnxt_free_all_hwrm_stat_ctxs(bp);
2535 bnxt_free_tunnel_ports(bp);
2538 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2540 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2542 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2543 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2545 switch (conf_link_speed) {
2546 case ETH_LINK_SPEED_10M_HD:
2547 case ETH_LINK_SPEED_100M_HD:
2549 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2551 return hw_link_duplex;
2554 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2556 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2559 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2561 uint16_t eth_link_speed = 0;
2563 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2564 return ETH_LINK_SPEED_AUTONEG;
2566 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2567 case ETH_LINK_SPEED_100M:
2568 case ETH_LINK_SPEED_100M_HD:
2571 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2573 case ETH_LINK_SPEED_1G:
2575 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2577 case ETH_LINK_SPEED_2_5G:
2579 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2581 case ETH_LINK_SPEED_10G:
2583 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2585 case ETH_LINK_SPEED_20G:
2587 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2589 case ETH_LINK_SPEED_25G:
2591 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2593 case ETH_LINK_SPEED_40G:
2595 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2597 case ETH_LINK_SPEED_50G:
2599 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2601 case ETH_LINK_SPEED_100G:
2603 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2607 "Unsupported link speed %d; default to AUTO\n",
2611 return eth_link_speed;
2614 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2615 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2616 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2617 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2619 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2623 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2626 if (link_speed & ETH_LINK_SPEED_FIXED) {
2627 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2629 if (one_speed & (one_speed - 1)) {
2631 "Invalid advertised speeds (%u) for port %u\n",
2632 link_speed, port_id);
2635 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2637 "Unsupported advertised speed (%u) for port %u\n",
2638 link_speed, port_id);
2642 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2644 "Unsupported advertised speeds (%u) for port %u\n",
2645 link_speed, port_id);
2653 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2657 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2658 if (bp->link_info.support_speeds)
2659 return bp->link_info.support_speeds;
2660 link_speed = BNXT_SUPPORTED_SPEEDS;
2663 if (link_speed & ETH_LINK_SPEED_100M)
2664 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2665 if (link_speed & ETH_LINK_SPEED_100M_HD)
2666 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2667 if (link_speed & ETH_LINK_SPEED_1G)
2668 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2669 if (link_speed & ETH_LINK_SPEED_2_5G)
2670 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2671 if (link_speed & ETH_LINK_SPEED_10G)
2672 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2673 if (link_speed & ETH_LINK_SPEED_20G)
2674 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2675 if (link_speed & ETH_LINK_SPEED_25G)
2676 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2677 if (link_speed & ETH_LINK_SPEED_40G)
2678 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2679 if (link_speed & ETH_LINK_SPEED_50G)
2680 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2681 if (link_speed & ETH_LINK_SPEED_100G)
2682 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2686 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2688 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2690 switch (hw_link_speed) {
2691 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2692 eth_link_speed = ETH_SPEED_NUM_100M;
2694 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2695 eth_link_speed = ETH_SPEED_NUM_1G;
2697 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2698 eth_link_speed = ETH_SPEED_NUM_2_5G;
2700 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2701 eth_link_speed = ETH_SPEED_NUM_10G;
2703 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2704 eth_link_speed = ETH_SPEED_NUM_20G;
2706 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2707 eth_link_speed = ETH_SPEED_NUM_25G;
2709 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2710 eth_link_speed = ETH_SPEED_NUM_40G;
2712 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2713 eth_link_speed = ETH_SPEED_NUM_50G;
2715 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2716 eth_link_speed = ETH_SPEED_NUM_100G;
2718 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2720 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2724 return eth_link_speed;
2727 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2729 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2731 switch (hw_link_duplex) {
2732 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2733 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2735 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2737 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2738 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2741 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2745 return eth_link_duplex;
2748 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2751 struct bnxt_link_info *link_info = &bp->link_info;
2753 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2756 "Get link config failed with rc %d\n", rc);
2759 if (link_info->link_speed)
2761 bnxt_parse_hw_link_speed(link_info->link_speed);
2763 link->link_speed = ETH_SPEED_NUM_NONE;
2764 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2765 link->link_status = link_info->link_up;
2766 link->link_autoneg = link_info->auto_mode ==
2767 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2768 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2773 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2776 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2777 struct bnxt_link_info link_req;
2778 uint16_t speed, autoneg;
2780 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2783 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2784 bp->eth_dev->data->port_id);
2788 memset(&link_req, 0, sizeof(link_req));
2789 link_req.link_up = link_up;
2793 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2794 if (BNXT_CHIP_THOR(bp) &&
2795 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2796 /* 40G is not supported as part of media auto detect.
2797 * The speed should be forced and autoneg disabled
2798 * to configure 40G speed.
2800 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2804 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2805 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2806 /* Autoneg can be done only when the FW allows.
2807 * When user configures fixed speed of 40G and later changes to
2808 * any other speed, auto_link_speed/force_link_speed is still set
2809 * to 40G until link comes up at new speed.
2812 !(!BNXT_CHIP_THOR(bp) &&
2813 (bp->link_info.auto_link_speed ||
2814 bp->link_info.force_link_speed))) {
2815 link_req.phy_flags |=
2816 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2817 link_req.auto_link_speed_mask =
2818 bnxt_parse_eth_link_speed_mask(bp,
2819 dev_conf->link_speeds);
2821 if (bp->link_info.phy_type ==
2822 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2823 bp->link_info.phy_type ==
2824 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2825 bp->link_info.media_type ==
2826 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2827 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2831 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2832 /* If user wants a particular speed try that first. */
2834 link_req.link_speed = speed;
2835 else if (bp->link_info.force_link_speed)
2836 link_req.link_speed = bp->link_info.force_link_speed;
2838 link_req.link_speed = bp->link_info.auto_link_speed;
2840 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2841 link_req.auto_pause = bp->link_info.auto_pause;
2842 link_req.force_pause = bp->link_info.force_pause;
2845 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2848 "Set link config failed with rc %d\n", rc);
2856 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2858 struct hwrm_func_qcfg_input req = {0};
2859 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2863 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2864 req.fid = rte_cpu_to_le_16(0xffff);
2866 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2868 HWRM_CHECK_RESULT();
2870 /* Hard Coded.. 0xfff VLAN ID mask */
2871 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2872 flags = rte_le_to_cpu_16(resp->flags);
2873 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2874 bp->flags |= BNXT_FLAG_MULTI_HOST;
2877 !BNXT_VF_IS_TRUSTED(bp) &&
2878 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2879 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2880 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2881 } else if (BNXT_VF(bp) &&
2882 BNXT_VF_IS_TRUSTED(bp) &&
2883 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2884 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2885 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2891 switch (resp->port_partition_type) {
2892 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2893 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2894 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2896 bp->port_partition_type = resp->port_partition_type;
2899 bp->port_partition_type = 0;
2908 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2909 struct hwrm_func_qcaps_output *qcaps)
2911 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2912 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2913 sizeof(qcaps->mac_address));
2914 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2915 qcaps->max_rx_rings = fcfg->num_rx_rings;
2916 qcaps->max_tx_rings = fcfg->num_tx_rings;
2917 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2918 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2920 qcaps->first_vf_id = 0;
2921 qcaps->max_vnics = fcfg->num_vnics;
2922 qcaps->max_decap_records = 0;
2923 qcaps->max_encap_records = 0;
2924 qcaps->max_tx_wm_flows = 0;
2925 qcaps->max_tx_em_flows = 0;
2926 qcaps->max_rx_wm_flows = 0;
2927 qcaps->max_rx_em_flows = 0;
2928 qcaps->max_flow_id = 0;
2929 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2930 qcaps->max_sp_tx_rings = 0;
2931 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2934 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2936 struct hwrm_func_cfg_input req = {0};
2937 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2941 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2942 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2943 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2944 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2945 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2946 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2947 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2948 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2949 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2951 if (BNXT_HAS_RING_GRPS(bp)) {
2952 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2953 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2954 } else if (BNXT_HAS_NQ(bp)) {
2955 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2956 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2959 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2960 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2961 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2962 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2964 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2965 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2966 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2967 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2968 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2969 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2970 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2971 req.fid = rte_cpu_to_le_16(0xffff);
2972 req.enables = rte_cpu_to_le_32(enables);
2974 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2976 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2978 HWRM_CHECK_RESULT();
2984 static void populate_vf_func_cfg_req(struct bnxt *bp,
2985 struct hwrm_func_cfg_input *req,
2988 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2989 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2990 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2991 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2992 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2993 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2994 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2995 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2996 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2997 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2999 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3000 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3002 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3003 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3005 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3007 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3008 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3010 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3011 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3012 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3013 /* TODO: For now, do not support VMDq/RFS on VFs. */
3014 req->num_vnics = rte_cpu_to_le_16(1);
3015 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3019 static void add_random_mac_if_needed(struct bnxt *bp,
3020 struct hwrm_func_cfg_input *cfg_req,
3023 struct rte_ether_addr mac;
3025 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3028 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3030 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3031 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3032 bp->pf.vf_info[vf].random_mac = true;
3034 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3035 RTE_ETHER_ADDR_LEN);
3039 static void reserve_resources_from_vf(struct bnxt *bp,
3040 struct hwrm_func_cfg_input *cfg_req,
3043 struct hwrm_func_qcaps_input req = {0};
3044 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3047 /* Get the actual allocated values now */
3048 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3049 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3050 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3053 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3054 copy_func_cfg_to_qcaps(cfg_req, resp);
3055 } else if (resp->error_code) {
3056 rc = rte_le_to_cpu_16(resp->error_code);
3057 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3058 copy_func_cfg_to_qcaps(cfg_req, resp);
3061 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3062 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3063 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3064 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3065 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3066 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3068 * TODO: While not supporting VMDq with VFs, max_vnics is always
3069 * forced to 1 in this case
3071 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3072 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3077 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3079 struct hwrm_func_qcfg_input req = {0};
3080 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3083 /* Check for zero MAC address */
3084 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3085 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3086 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3087 HWRM_CHECK_RESULT();
3088 rc = rte_le_to_cpu_16(resp->vlan);
3095 static int update_pf_resource_max(struct bnxt *bp)
3097 struct hwrm_func_qcfg_input req = {0};
3098 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3101 /* And copy the allocated numbers into the pf struct */
3102 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3103 req.fid = rte_cpu_to_le_16(0xffff);
3104 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3105 HWRM_CHECK_RESULT();
3107 /* Only TX ring value reflects actual allocation? TODO */
3108 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3109 bp->pf.evb_mode = resp->evb_mode;
3116 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3121 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3125 rc = bnxt_hwrm_func_qcaps(bp);
3129 bp->pf.func_cfg_flags &=
3130 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3131 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3132 bp->pf.func_cfg_flags |=
3133 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3134 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3135 rc = __bnxt_hwrm_func_qcaps(bp);
3139 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3141 struct hwrm_func_cfg_input req = {0};
3142 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3149 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3153 rc = bnxt_hwrm_func_qcaps(bp);
3158 bp->pf.active_vfs = num_vfs;
3161 * First, configure the PF to only use one TX ring. This ensures that
3162 * there are enough rings for all VFs.
3164 * If we don't do this, when we call func_alloc() later, we will lock
3165 * extra rings to the PF that won't be available during func_cfg() of
3168 * This has been fixed with firmware versions above 20.6.54
3170 bp->pf.func_cfg_flags &=
3171 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3172 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3173 bp->pf.func_cfg_flags |=
3174 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3175 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3180 * Now, create and register a buffer to hold forwarded VF requests
3182 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3183 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3184 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3185 if (bp->pf.vf_req_buf == NULL) {
3189 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3190 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3191 for (i = 0; i < num_vfs; i++)
3192 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3193 (i * HWRM_MAX_REQ_LEN);
3195 rc = bnxt_hwrm_func_buf_rgtr(bp);
3199 populate_vf_func_cfg_req(bp, &req, num_vfs);
3201 bp->pf.active_vfs = 0;
3202 for (i = 0; i < num_vfs; i++) {
3203 add_random_mac_if_needed(bp, &req, i);
3205 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3206 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3207 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3208 rc = bnxt_hwrm_send_message(bp,
3213 /* Clear enable flag for next pass */
3214 req.enables &= ~rte_cpu_to_le_32(
3215 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3217 if (rc || resp->error_code) {
3219 "Failed to initizlie VF %d\n", i);
3221 "Not all VFs available. (%d, %d)\n",
3222 rc, resp->error_code);
3229 reserve_resources_from_vf(bp, &req, i);
3230 bp->pf.active_vfs++;
3231 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3235 * Now configure the PF to use "the rest" of the resources
3236 * We're using STD_TX_RING_MODE here though which will limit the TX
3237 * rings. This will allow QoS to function properly. Not setting this
3238 * will cause PF rings to break bandwidth settings.
3240 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3244 rc = update_pf_resource_max(bp);
3251 bnxt_hwrm_func_buf_unrgtr(bp);
3255 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3257 struct hwrm_func_cfg_input req = {0};
3258 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3261 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3263 req.fid = rte_cpu_to_le_16(0xffff);
3264 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3265 req.evb_mode = bp->pf.evb_mode;
3267 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3268 HWRM_CHECK_RESULT();
3274 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3275 uint8_t tunnel_type)
3277 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3278 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3281 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3282 req.tunnel_type = tunnel_type;
3283 req.tunnel_dst_port_val = port;
3284 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3285 HWRM_CHECK_RESULT();
3287 switch (tunnel_type) {
3288 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3289 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3290 bp->vxlan_port = port;
3292 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3293 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3294 bp->geneve_port = port;
3305 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3306 uint8_t tunnel_type)
3308 struct hwrm_tunnel_dst_port_free_input req = {0};
3309 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3312 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3314 req.tunnel_type = tunnel_type;
3315 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3316 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3318 HWRM_CHECK_RESULT();
3324 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3327 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3328 struct hwrm_func_cfg_input req = {0};
3331 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3333 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3334 req.flags = rte_cpu_to_le_32(flags);
3335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3337 HWRM_CHECK_RESULT();
3343 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3345 uint32_t *flag = flagp;
3347 vnic->flags = *flag;
3350 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3352 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3355 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3358 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3359 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3361 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3363 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3364 req.req_buf_page_size = rte_cpu_to_le_16(
3365 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3366 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3367 req.req_buf_page_addr0 =
3368 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3369 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3371 "unable to map buffer address to physical memory\n");
3375 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3377 HWRM_CHECK_RESULT();
3383 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3386 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3387 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3389 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3392 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3394 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3396 HWRM_CHECK_RESULT();
3402 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3404 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3405 struct hwrm_func_cfg_input req = {0};
3408 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3410 req.fid = rte_cpu_to_le_16(0xffff);
3411 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3412 req.enables = rte_cpu_to_le_32(
3413 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3414 req.async_event_cr = rte_cpu_to_le_16(
3415 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3416 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3418 HWRM_CHECK_RESULT();
3424 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3426 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3427 struct hwrm_func_vf_cfg_input req = {0};
3430 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3432 req.enables = rte_cpu_to_le_32(
3433 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3434 req.async_event_cr = rte_cpu_to_le_16(
3435 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3436 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3438 HWRM_CHECK_RESULT();
3444 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3446 struct hwrm_func_cfg_input req = {0};
3447 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3448 uint16_t dflt_vlan, fid;
3449 uint32_t func_cfg_flags;
3452 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3455 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3456 fid = bp->pf.vf_info[vf].fid;
3457 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3459 fid = rte_cpu_to_le_16(0xffff);
3460 func_cfg_flags = bp->pf.func_cfg_flags;
3461 dflt_vlan = bp->vlan;
3464 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3465 req.fid = rte_cpu_to_le_16(fid);
3466 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3467 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3469 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3471 HWRM_CHECK_RESULT();
3477 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3478 uint16_t max_bw, uint16_t enables)
3480 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3481 struct hwrm_func_cfg_input req = {0};
3484 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3486 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3487 req.enables |= rte_cpu_to_le_32(enables);
3488 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3489 req.max_bw = rte_cpu_to_le_32(max_bw);
3490 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3492 HWRM_CHECK_RESULT();
3498 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3500 struct hwrm_func_cfg_input req = {0};
3501 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3504 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3506 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3507 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3508 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3509 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3511 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3513 HWRM_CHECK_RESULT();
3519 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3524 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3526 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3531 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3532 void *encaped, size_t ec_size)
3535 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3536 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3538 if (ec_size > sizeof(req.encap_request))
3541 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3543 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3544 memcpy(req.encap_request, encaped, ec_size);
3546 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3548 HWRM_CHECK_RESULT();
3554 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3555 struct rte_ether_addr *mac)
3557 struct hwrm_func_qcfg_input req = {0};
3558 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3561 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3563 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3564 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3566 HWRM_CHECK_RESULT();
3568 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3575 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3576 void *encaped, size_t ec_size)
3579 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3580 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3582 if (ec_size > sizeof(req.encap_request))
3585 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3587 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3588 memcpy(req.encap_request, encaped, ec_size);
3590 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3592 HWRM_CHECK_RESULT();
3598 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3599 struct rte_eth_stats *stats, uint8_t rx)
3602 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3603 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3605 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3607 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3609 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3611 HWRM_CHECK_RESULT();
3614 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3615 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3616 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3617 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3618 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3619 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3620 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3621 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3623 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3624 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3625 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3626 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3627 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3628 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3637 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3639 struct hwrm_port_qstats_input req = {0};
3640 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3641 struct bnxt_pf_info *pf = &bp->pf;
3644 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3646 req.port_id = rte_cpu_to_le_16(pf->port_id);
3647 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3648 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3649 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3651 HWRM_CHECK_RESULT();
3657 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3659 struct hwrm_port_clr_stats_input req = {0};
3660 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3661 struct bnxt_pf_info *pf = &bp->pf;
3664 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3665 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3666 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3669 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3671 req.port_id = rte_cpu_to_le_16(pf->port_id);
3672 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3674 HWRM_CHECK_RESULT();
3680 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3682 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3683 struct hwrm_port_led_qcaps_input req = {0};
3689 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3690 req.port_id = bp->pf.port_id;
3691 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3693 HWRM_CHECK_RESULT();
3695 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3698 bp->num_leds = resp->num_leds;
3699 memcpy(bp->leds, &resp->led0_id,
3700 sizeof(bp->leds[0]) * bp->num_leds);
3701 for (i = 0; i < bp->num_leds; i++) {
3702 struct bnxt_led_info *led = &bp->leds[i];
3704 uint16_t caps = led->led_state_caps;
3706 if (!led->led_group_id ||
3707 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3719 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3721 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3722 struct hwrm_port_led_cfg_input req = {0};
3723 struct bnxt_led_cfg *led_cfg;
3724 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3725 uint16_t duration = 0;
3728 if (!bp->num_leds || BNXT_VF(bp))
3731 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3734 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3735 duration = rte_cpu_to_le_16(500);
3737 req.port_id = bp->pf.port_id;
3738 req.num_leds = bp->num_leds;
3739 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3740 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3741 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3742 led_cfg->led_id = bp->leds[i].led_id;
3743 led_cfg->led_state = led_state;
3744 led_cfg->led_blink_on = duration;
3745 led_cfg->led_blink_off = duration;
3746 led_cfg->led_group_id = bp->leds[i].led_group_id;
3749 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3751 HWRM_CHECK_RESULT();
3757 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3761 struct hwrm_nvm_get_dir_info_input req = {0};
3762 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3764 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3766 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3768 HWRM_CHECK_RESULT();
3770 *entries = rte_le_to_cpu_32(resp->entries);
3771 *length = rte_le_to_cpu_32(resp->entry_length);
3777 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3780 uint32_t dir_entries;
3781 uint32_t entry_length;
3784 rte_iova_t dma_handle;
3785 struct hwrm_nvm_get_dir_entries_input req = {0};
3786 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3788 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3792 *data++ = dir_entries;
3793 *data++ = entry_length;
3795 memset(data, 0xff, len);
3797 buflen = dir_entries * entry_length;
3798 buf = rte_malloc("nvm_dir", buflen, 0);
3799 rte_mem_lock_page(buf);
3802 dma_handle = rte_mem_virt2iova(buf);
3803 if (dma_handle == RTE_BAD_IOVA) {
3805 "unable to map response address to physical memory\n");
3808 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3809 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3810 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3813 memcpy(data, buf, len > buflen ? buflen : len);
3816 HWRM_CHECK_RESULT();
3822 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3823 uint32_t offset, uint32_t length,
3828 rte_iova_t dma_handle;
3829 struct hwrm_nvm_read_input req = {0};
3830 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3832 buf = rte_malloc("nvm_item", length, 0);
3833 rte_mem_lock_page(buf);
3837 dma_handle = rte_mem_virt2iova(buf);
3838 if (dma_handle == RTE_BAD_IOVA) {
3840 "unable to map response address to physical memory\n");
3843 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3844 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3845 req.dir_idx = rte_cpu_to_le_16(index);
3846 req.offset = rte_cpu_to_le_32(offset);
3847 req.len = rte_cpu_to_le_32(length);
3848 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3850 memcpy(data, buf, length);
3853 HWRM_CHECK_RESULT();
3859 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3862 struct hwrm_nvm_erase_dir_entry_input req = {0};
3863 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3865 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3866 req.dir_idx = rte_cpu_to_le_16(index);
3867 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3868 HWRM_CHECK_RESULT();
3875 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3876 uint16_t dir_ordinal, uint16_t dir_ext,
3877 uint16_t dir_attr, const uint8_t *data,
3881 struct hwrm_nvm_write_input req = {0};
3882 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3883 rte_iova_t dma_handle;
3886 buf = rte_malloc("nvm_write", data_len, 0);
3887 rte_mem_lock_page(buf);
3891 dma_handle = rte_mem_virt2iova(buf);
3892 if (dma_handle == RTE_BAD_IOVA) {
3894 "unable to map response address to physical memory\n");
3897 memcpy(buf, data, data_len);
3899 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3901 req.dir_type = rte_cpu_to_le_16(dir_type);
3902 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3903 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3904 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3905 req.dir_data_length = rte_cpu_to_le_32(data_len);
3906 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3908 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3911 HWRM_CHECK_RESULT();
3918 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3920 uint32_t *count = cbdata;
3922 *count = *count + 1;
3925 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3926 struct bnxt_vnic_info *vnic __rte_unused)
3931 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3935 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3936 &count, bnxt_vnic_count_hwrm_stub);
3941 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3944 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3945 struct hwrm_func_vf_vnic_ids_query_output *resp =
3946 bp->hwrm_cmd_resp_addr;
3949 /* First query all VNIC ids */
3950 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3952 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3953 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3954 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3956 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3959 "unable to map VNIC ID table address to physical memory\n");
3962 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3963 HWRM_CHECK_RESULT();
3964 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3972 * This function queries the VNIC IDs for a specified VF. It then calls
3973 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3974 * Then it calls the hwrm_cb function to program this new vnic configuration.
3976 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3977 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3978 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3980 struct bnxt_vnic_info vnic;
3982 int i, num_vnic_ids;
3987 /* First query all VNIC ids */
3988 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3989 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3990 RTE_CACHE_LINE_SIZE);
3991 if (vnic_ids == NULL)
3994 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3995 rte_mem_lock_page(((char *)vnic_ids) + sz);
3997 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3999 if (num_vnic_ids < 0)
4000 return num_vnic_ids;
4002 /* Retrieve VNIC, update bd_stall then update */
4004 for (i = 0; i < num_vnic_ids; i++) {
4005 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4006 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4007 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4010 if (vnic.mru <= 4) /* Indicates unallocated */
4013 vnic_cb(&vnic, cbdata);
4015 rc = hwrm_cb(bp, &vnic);
4025 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4028 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4029 struct hwrm_func_cfg_input req = {0};
4032 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4034 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4035 req.enables |= rte_cpu_to_le_32(
4036 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4037 req.vlan_antispoof_mode = on ?
4038 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4039 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4040 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4042 HWRM_CHECK_RESULT();
4048 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4050 struct bnxt_vnic_info vnic;
4053 int num_vnic_ids, i;
4057 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4058 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4059 RTE_CACHE_LINE_SIZE);
4060 if (vnic_ids == NULL)
4063 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4064 rte_mem_lock_page(((char *)vnic_ids) + sz);
4066 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4072 * Loop through to find the default VNIC ID.
4073 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4074 * by sending the hwrm_func_qcfg command to the firmware.
4076 for (i = 0; i < num_vnic_ids; i++) {
4077 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4078 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4079 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4080 bp->pf.first_vf_id + vf);
4083 if (vnic.func_default) {
4085 return vnic.fw_vnic_id;
4088 /* Could not find a default VNIC. */
4089 PMD_DRV_LOG(ERR, "No default VNIC\n");
4095 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4097 struct bnxt_filter_info *filter)
4100 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4101 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4102 uint32_t enables = 0;
4104 if (filter->fw_em_filter_id != UINT64_MAX)
4105 bnxt_hwrm_clear_em_filter(bp, filter);
4107 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4109 req.flags = rte_cpu_to_le_32(filter->flags);
4111 enables = filter->enables |
4112 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4113 req.dst_id = rte_cpu_to_le_16(dst_id);
4115 if (filter->ip_addr_type) {
4116 req.ip_addr_type = filter->ip_addr_type;
4117 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4120 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4121 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4123 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4124 memcpy(req.src_macaddr, filter->src_macaddr,
4125 RTE_ETHER_ADDR_LEN);
4127 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4128 memcpy(req.dst_macaddr, filter->dst_macaddr,
4129 RTE_ETHER_ADDR_LEN);
4131 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4132 req.ovlan_vid = filter->l2_ovlan;
4134 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4135 req.ivlan_vid = filter->l2_ivlan;
4137 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4138 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4140 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4141 req.ip_protocol = filter->ip_protocol;
4143 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4144 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4146 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4147 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4149 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4150 req.src_port = rte_cpu_to_be_16(filter->src_port);
4152 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4153 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4155 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4156 req.mirror_vnic_id = filter->mirror_vnic_id;
4158 req.enables = rte_cpu_to_le_32(enables);
4160 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4162 HWRM_CHECK_RESULT();
4164 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4170 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4173 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4174 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4176 if (filter->fw_em_filter_id == UINT64_MAX)
4179 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4180 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4182 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4184 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4186 HWRM_CHECK_RESULT();
4189 filter->fw_em_filter_id = UINT64_MAX;
4190 filter->fw_l2_filter_id = UINT64_MAX;
4195 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4197 struct bnxt_filter_info *filter)
4200 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4201 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4202 bp->hwrm_cmd_resp_addr;
4203 uint32_t enables = 0;
4205 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4206 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4208 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4210 req.flags = rte_cpu_to_le_32(filter->flags);
4212 enables = filter->enables |
4213 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4214 req.dst_id = rte_cpu_to_le_16(dst_id);
4217 if (filter->ip_addr_type) {
4218 req.ip_addr_type = filter->ip_addr_type;
4220 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4223 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4224 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4226 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4227 memcpy(req.src_macaddr, filter->src_macaddr,
4228 RTE_ETHER_ADDR_LEN);
4230 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4231 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4232 //RTE_ETHER_ADDR_LEN);
4234 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4235 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4237 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4238 req.ip_protocol = filter->ip_protocol;
4240 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4241 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4243 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4244 req.src_ipaddr_mask[0] =
4245 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4247 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4248 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4250 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4251 req.dst_ipaddr_mask[0] =
4252 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4254 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4255 req.src_port = rte_cpu_to_le_16(filter->src_port);
4257 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4258 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4260 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4261 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4263 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4264 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4266 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4267 req.mirror_vnic_id = filter->mirror_vnic_id;
4269 req.enables = rte_cpu_to_le_32(enables);
4271 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4273 HWRM_CHECK_RESULT();
4275 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4281 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4282 struct bnxt_filter_info *filter)
4285 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4286 struct hwrm_cfa_ntuple_filter_free_output *resp =
4287 bp->hwrm_cmd_resp_addr;
4289 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4292 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4294 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4296 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4298 HWRM_CHECK_RESULT();
4301 filter->fw_ntuple_filter_id = UINT64_MAX;
4307 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4309 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4310 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4311 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4312 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4313 uint16_t *ring_tbl = vnic->rss_table;
4314 int nr_ctxs = vnic->num_lb_ctxts;
4315 int max_rings = bp->rx_nr_rings;
4319 for (i = 0, k = 0; i < nr_ctxs; i++) {
4320 struct bnxt_rx_ring_info *rxr;
4321 struct bnxt_cp_ring_info *cpr;
4323 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4325 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4326 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4327 req.hash_mode_flags = vnic->hash_mode;
4329 req.ring_grp_tbl_addr =
4330 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4331 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4332 2 * sizeof(*ring_tbl));
4333 req.hash_key_tbl_addr =
4334 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4336 req.ring_table_pair_index = i;
4337 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4339 for (j = 0; j < 64; j++) {
4342 /* Find next active ring. */
4343 for (cnt = 0; cnt < max_rings; cnt++) {
4344 if (rx_queue_state[k] !=
4345 RTE_ETH_QUEUE_STATE_STOPPED)
4347 if (++k == max_rings)
4351 /* Return if no rings are active. */
4352 if (cnt == max_rings)
4355 /* Add rx/cp ring pair to RSS table. */
4356 rxr = rxqs[k]->rx_ring;
4357 cpr = rxqs[k]->cp_ring;
4359 ring_id = rxr->rx_ring_struct->fw_ring_id;
4360 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4361 ring_id = cpr->cp_ring_struct->fw_ring_id;
4362 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4364 if (++k == max_rings)
4367 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4370 HWRM_CHECK_RESULT();
4377 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4379 unsigned int rss_idx, fw_idx, i;
4381 if (!(vnic->rss_table && vnic->hash_type))
4384 if (BNXT_CHIP_THOR(bp))
4385 return bnxt_vnic_rss_configure_thor(bp, vnic);
4387 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4390 if (vnic->rss_table && vnic->hash_type) {
4392 * Fill the RSS hash & redirection table with
4393 * ring group ids for all VNICs
4395 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4396 rss_idx++, fw_idx++) {
4397 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4398 fw_idx %= bp->rx_cp_nr_rings;
4399 if (vnic->fw_grp_ids[fw_idx] !=
4404 if (i == bp->rx_cp_nr_rings)
4406 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4408 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4414 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4415 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4419 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4421 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4422 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4424 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4425 req->num_cmpl_dma_aggr_during_int =
4426 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4428 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4430 /* min timer set to 1/2 of interrupt timer */
4431 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4433 /* buf timer set to 1/4 of interrupt timer */
4434 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4436 req->cmpl_aggr_dma_tmr_during_int =
4437 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4439 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4440 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4441 req->flags = rte_cpu_to_le_16(flags);
4444 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4445 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4447 struct hwrm_ring_aggint_qcaps_input req = {0};
4448 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4453 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4454 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4455 HWRM_CHECK_RESULT();
4457 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4458 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4460 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4461 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4462 agg_req->flags = rte_cpu_to_le_16(flags);
4464 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4465 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4466 agg_req->enables = rte_cpu_to_le_32(enables);
4472 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4473 struct bnxt_coal *coal, uint16_t ring_id)
4475 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4476 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4477 bp->hwrm_cmd_resp_addr;
4480 /* Set ring coalesce parameters only for 100G NICs */
4481 if (BNXT_CHIP_THOR(bp)) {
4482 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4484 } else if (bnxt_stratus_device(bp)) {
4485 bnxt_hwrm_set_coal_params(coal, &req);
4490 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4491 req.ring_id = rte_cpu_to_le_16(ring_id);
4492 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4493 HWRM_CHECK_RESULT();
4498 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4499 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4501 struct hwrm_func_backing_store_qcaps_input req = {0};
4502 struct hwrm_func_backing_store_qcaps_output *resp =
4503 bp->hwrm_cmd_resp_addr;
4504 struct bnxt_ctx_pg_info *ctx_pg;
4505 struct bnxt_ctx_mem_info *ctx;
4506 int total_alloc_len;
4509 if (!BNXT_CHIP_THOR(bp) ||
4510 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4515 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4516 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4517 HWRM_CHECK_RESULT_SILENT();
4519 total_alloc_len = sizeof(*ctx);
4520 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4521 RTE_CACHE_LINE_SIZE);
4527 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4528 sizeof(*ctx_pg) * BNXT_MAX_Q,
4529 RTE_CACHE_LINE_SIZE);
4534 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4535 ctx->tqm_mem[i] = ctx_pg;
4538 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4539 ctx->qp_min_qp1_entries =
4540 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4541 ctx->qp_max_l2_entries =
4542 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4543 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4544 ctx->srq_max_l2_entries =
4545 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4546 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4547 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4548 ctx->cq_max_l2_entries =
4549 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4550 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4551 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4552 ctx->vnic_max_vnic_entries =
4553 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4554 ctx->vnic_max_ring_table_entries =
4555 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4556 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4557 ctx->stat_max_entries =
4558 rte_le_to_cpu_32(resp->stat_max_entries);
4559 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4560 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4561 ctx->tqm_min_entries_per_ring =
4562 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4563 ctx->tqm_max_entries_per_ring =
4564 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4565 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4566 if (!ctx->tqm_entries_multiple)
4567 ctx->tqm_entries_multiple = 1;
4568 ctx->mrav_max_entries =
4569 rte_le_to_cpu_32(resp->mrav_max_entries);
4570 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4571 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4572 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4578 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4580 struct hwrm_func_backing_store_cfg_input req = {0};
4581 struct hwrm_func_backing_store_cfg_output *resp =
4582 bp->hwrm_cmd_resp_addr;
4583 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4584 struct bnxt_ctx_pg_info *ctx_pg;
4585 uint32_t *num_entries;
4594 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4595 req.enables = rte_cpu_to_le_32(enables);
4597 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4598 ctx_pg = &ctx->qp_mem;
4599 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4600 req.qp_num_qp1_entries =
4601 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4602 req.qp_num_l2_entries =
4603 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4604 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4605 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4606 &req.qpc_pg_size_qpc_lvl,
4610 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4611 ctx_pg = &ctx->srq_mem;
4612 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4613 req.srq_num_l2_entries =
4614 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4615 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4616 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4617 &req.srq_pg_size_srq_lvl,
4621 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4622 ctx_pg = &ctx->cq_mem;
4623 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4624 req.cq_num_l2_entries =
4625 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4626 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4627 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4628 &req.cq_pg_size_cq_lvl,
4632 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4633 ctx_pg = &ctx->vnic_mem;
4634 req.vnic_num_vnic_entries =
4635 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4636 req.vnic_num_ring_table_entries =
4637 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4638 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4639 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4640 &req.vnic_pg_size_vnic_lvl,
4641 &req.vnic_page_dir);
4644 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4645 ctx_pg = &ctx->stat_mem;
4646 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4647 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4648 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4649 &req.stat_pg_size_stat_lvl,
4650 &req.stat_page_dir);
4653 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4654 num_entries = &req.tqm_sp_num_entries;
4655 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4656 pg_dir = &req.tqm_sp_page_dir;
4657 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4658 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4659 if (!(enables & ena))
4662 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4664 ctx_pg = ctx->tqm_mem[i];
4665 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4666 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4669 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4670 HWRM_CHECK_RESULT();
4676 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4678 struct hwrm_port_qstats_ext_input req = {0};
4679 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4680 struct bnxt_pf_info *pf = &bp->pf;
4683 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4684 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4687 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4689 req.port_id = rte_cpu_to_le_16(pf->port_id);
4690 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4691 req.tx_stat_host_addr =
4692 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4694 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4696 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4697 req.rx_stat_host_addr =
4698 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4700 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4702 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4705 bp->fw_rx_port_stats_ext_size = 0;
4706 bp->fw_tx_port_stats_ext_size = 0;
4708 bp->fw_rx_port_stats_ext_size =
4709 rte_le_to_cpu_16(resp->rx_stat_size);
4710 bp->fw_tx_port_stats_ext_size =
4711 rte_le_to_cpu_16(resp->tx_stat_size);
4714 HWRM_CHECK_RESULT();
4721 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4723 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4724 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4725 bp->hwrm_cmd_resp_addr;
4728 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4729 req.tunnel_type = type;
4730 req.dest_fid = bp->fw_fid;
4731 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4732 HWRM_CHECK_RESULT();
4740 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4742 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4743 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4744 bp->hwrm_cmd_resp_addr;
4747 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4748 req.tunnel_type = type;
4749 req.dest_fid = bp->fw_fid;
4750 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4751 HWRM_CHECK_RESULT();
4758 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4760 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4761 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4762 bp->hwrm_cmd_resp_addr;
4765 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4766 req.src_fid = bp->fw_fid;
4767 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4768 HWRM_CHECK_RESULT();
4771 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4778 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4781 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4782 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4783 bp->hwrm_cmd_resp_addr;
4786 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4787 req.src_fid = bp->fw_fid;
4788 req.tunnel_type = tun_type;
4789 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4790 HWRM_CHECK_RESULT();
4793 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4795 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4802 int bnxt_hwrm_set_mac(struct bnxt *bp)
4804 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4805 struct hwrm_func_vf_cfg_input req = {0};
4811 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4814 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4815 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4817 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4819 HWRM_CHECK_RESULT();
4821 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4827 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4829 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4830 struct hwrm_func_drv_if_change_input req = {0};
4834 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4837 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4838 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4839 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4841 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4844 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4848 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4850 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4852 HWRM_CHECK_RESULT();
4853 flags = rte_le_to_cpu_32(resp->flags);
4856 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4857 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4858 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4864 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4866 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4867 struct bnxt_error_recovery_info *info = bp->recovery_info;
4868 struct hwrm_error_recovery_qcfg_input req = {0};
4873 /* Older FW does not have error recovery support */
4874 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4878 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4880 bp->recovery_info = info;
4884 memset(info, 0, sizeof(*info));
4887 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4889 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4891 HWRM_CHECK_RESULT();
4893 flags = rte_le_to_cpu_32(resp->flags);
4894 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4895 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4896 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4897 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4899 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4900 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4905 /* FW returned values are in units of 100msec */
4906 info->driver_polling_freq =
4907 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4908 info->master_func_wait_period =
4909 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4910 info->normal_func_wait_period =
4911 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4912 info->master_func_wait_period_after_reset =
4913 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4914 info->max_bailout_time_after_reset =
4915 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4916 info->status_regs[BNXT_FW_STATUS_REG] =
4917 rte_le_to_cpu_32(resp->fw_health_status_reg);
4918 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4919 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4920 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4921 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4922 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4923 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4924 info->reg_array_cnt =
4925 rte_le_to_cpu_32(resp->reg_array_cnt);
4927 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4932 for (i = 0; i < info->reg_array_cnt; i++) {
4933 info->reset_reg[i] =
4934 rte_le_to_cpu_32(resp->reset_reg[i]);
4935 info->reset_reg_val[i] =
4936 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4937 info->delay_after_reset[i] =
4938 resp->delay_after_reset[i];
4943 /* Map the FW status registers */
4945 rc = bnxt_map_fw_health_status_regs(bp);
4948 rte_free(bp->recovery_info);
4949 bp->recovery_info = NULL;
4954 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4956 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4957 struct hwrm_fw_reset_input req = {0};
4963 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4965 req.embedded_proc_type =
4966 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4967 req.selfrst_status =
4968 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4969 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4971 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4974 HWRM_CHECK_RESULT();
4980 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4982 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4983 struct hwrm_port_ts_query_input req = {0};
4984 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4991 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4994 case BNXT_PTP_FLAGS_PATH_TX:
4995 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4997 case BNXT_PTP_FLAGS_PATH_RX:
4998 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5000 case BNXT_PTP_FLAGS_CURRENT_TIME:
5001 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5005 req.flags = rte_cpu_to_le_32(flags);
5006 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5008 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5010 HWRM_CHECK_RESULT();
5013 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5015 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5022 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5024 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5025 bp->hwrm_cmd_resp_addr;
5026 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5030 if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5033 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5035 "Not a PF or trusted VF. Command not supported\n");
5039 HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5040 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5042 HWRM_CHECK_RESULT();
5043 flags = rte_le_to_cpu_32(resp->flags);
5046 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5047 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5048 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");