drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR,
 168                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 169                             req->req_type, req->seq_id);
 170                 return -ETIMEDOUT;
 171         }
 172         return 0;
 173 }
 174
 175 /*
 176  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 177  * spinlock, and does initial processing.
 178  *
 179  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 180  * releases the spinlock only if it returns. If the regular int return codes
 181  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 182  * directly, rather it should be copied and modified to suit the function.
 183  *
 184  * HWRM_UNLOCK() must be called after all response processing is completed.
 185  */
 186 #define HWRM_PREP(req, type, kong) do { \
 187         rte_spinlock_lock(&bp->hwrm_lock); \
 188         if (bp->hwrm_cmd_resp_addr == NULL) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return -EACCES; \
 191         } \
 192         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 193         (req)->req_type = rte_cpu_to_le_16(type); \
 194         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 195         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 196                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 197         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 198         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 199 } while (0)
 200
 201 #define HWRM_CHECK_RESULT_SILENT() do {\
 202         if (rc) { \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 rte_spinlock_unlock(&bp->hwrm_lock); \
 209                 return rc; \
 210         } \
 211 } while (0)
 212
 213 #define HWRM_CHECK_RESULT() do {\
 214         if (rc) { \
 215                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 218                         rc = -EACCES; \
 219                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 220                         rc = -ENOSPC; \
 221                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 222                         rc = -EINVAL; \
 223                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 224                         rc = -ENOTSUP; \
 225                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 226                         rc = -EAGAIN; \
 227                 else if (rc > 0) \
 228                         rc = -EIO; \
 229                 return rc; \
 230         } \
 231         if (resp->error_code) { \
 232                 rc = rte_le_to_cpu_16(resp->error_code); \
 233                 if (resp->resp_len >= 16) { \
 234                         struct hwrm_err_output *tmp_hwrm_err_op = \
 235                                                 (void *)resp; \
 236                         PMD_DRV_LOG(ERR, \
 237                                 "error %d:%d:%08x:%04x\n", \
 238                                 rc, tmp_hwrm_err_op->cmd_err, \
 239                                 rte_le_to_cpu_32(\
 240                                         tmp_hwrm_err_op->opaque_0), \
 241                                 rte_le_to_cpu_16(\
 242                                         tmp_hwrm_err_op->opaque_1)); \
 243                 } else { \
 244                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 245                 } \
 246                 rte_spinlock_unlock(&bp->hwrm_lock); \
 247                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 248                         rc = -EACCES; \
 249                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 250                         rc = -ENOSPC; \
 251                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 252                         rc = -EINVAL; \
 253                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 254                         rc = -ENOTSUP; \
 255                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 256                         rc = -EAGAIN; \
 257                 else if (rc > 0) \
 258                         rc = -EIO; \
 259                 return rc; \
 260         } \
 261 } while (0)
 262
 263 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 264
 265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 266                                 bool use_kong_mb,
 267                                 uint16_t msg_type,
 268                                 void *msg,
 269                                 uint32_t msg_len,
 270                                 void *resp_msg,
 271                                 uint32_t resp_len)
 272 {
 273         int rc = 0;
 274         bool mailbox = BNXT_USE_CHIMP_MB;
 275         struct input *req = msg;
 276         struct output *resp = bp->hwrm_cmd_resp_addr;
 277
 278         if (use_kong_mb)
 279                 mailbox = BNXT_USE_KONG(bp);
 280
 281         HWRM_PREP(req, msg_type, mailbox);
 282
 283         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 284
 285         HWRM_CHECK_RESULT();
 286
 287         if (resp_msg)
 288                 memcpy(resp_msg, resp, resp_len);
 289
 290         HWRM_UNLOCK();
 291
 292         return rc;
 293 }
 294
 295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 296                                   bool use_kong_mb,
 297                                   uint16_t tf_type,
 298                                   uint16_t tf_subtype,
 299                                   uint32_t *tf_response_code,
 300                                   void *msg,
 301                                   uint32_t msg_len,
 302                                   void *response,
 303                                   uint32_t response_len)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 307         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 308         bool mailbox = BNXT_USE_CHIMP_MB;
 309
 310         if (msg_len > sizeof(req.tf_req))
 311                 return -ENOMEM;
 312
 313         if (use_kong_mb)
 314                 mailbox = BNXT_USE_KONG(bp);
 315
 316         HWRM_PREP(&req, HWRM_TF, mailbox);
 317         /* Build request using the user supplied request payload.
 318          * TLV request size is checked at build time against HWRM
 319          * request max size, thus no checking required.
 320          */
 321         req.tf_type = tf_type;
 322         req.tf_subtype = tf_subtype;
 323         memcpy(req.tf_req, msg, msg_len);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 326         HWRM_CHECK_RESULT();
 327
 328         /* Copy the resp to user provided response buffer */
 329         if (response != NULL)
 330                 /* Post process response data. We need to copy only
 331                  * the 'payload' as the HWRM data structure really is
 332                  * HWRM header + msg header + payload and the TFLIB
 333                  * only provided a payload place holder.
 334                  */
 335                 if (response_len != 0) {
 336                         memcpy(response,
 337                                resp->tf_resp,
 338                                response_len);
 339                 }
 340
 341         /* Extract the internal tflib response code */
 342         *tf_response_code = resp->tf_resp_code;
 343         HWRM_UNLOCK();
 344
 345         return rc;
 346 }
 347
 348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 349 {
 350         int rc = 0;
 351         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 352         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 353
 354         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 355         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 356         req.mask = 0;
 357
 358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 359
 360         HWRM_CHECK_RESULT();
 361         HWRM_UNLOCK();
 362
 363         return rc;
 364 }
 365
 366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 367                                  struct bnxt_vnic_info *vnic,
 368                                  uint16_t vlan_count,
 369                                  struct bnxt_vlan_table_entry *vlan_table)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 374         uint32_t mask = 0;
 375
 376         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 377                 return rc;
 378
 379         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 380         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 384         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 385                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 386
 387         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 389
 390         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 391                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 392         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 393                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 394                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 395                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 396         }
 397         if (vlan_table) {
 398                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 399                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 400                 req.vlan_tag_tbl_addr =
 401                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 402                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 403         }
 404         req.mask = rte_cpu_to_le_32(mask);
 405
 406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 407
 408         HWRM_CHECK_RESULT();
 409         HWRM_UNLOCK();
 410
 411         return rc;
 412 }
 413
 414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 415                         uint16_t vlan_count,
 416                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 420         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 421                                                 bp->hwrm_cmd_resp_addr;
 422
 423         /*
 424          * Older HWRM versions did not support this command, and the set_rx_mask
 425          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 426          * removed from set_rx_mask call, and this command was added.
 427          *
 428          * This command is also present from 1.7.8.11 and higher,
 429          * as well as 1.7.8.0
 430          */
 431         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 432                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 433                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 434                                         (11)))
 435                                 return 0;
 436                 }
 437         }
 438         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 439         req.fid = rte_cpu_to_le_16(fid);
 440
 441         req.vlan_tag_mask_tbl_addr =
 442                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 443         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 444
 445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 446
 447         HWRM_CHECK_RESULT();
 448         HWRM_UNLOCK();
 449
 450         return rc;
 451 }
 452
 453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 454                              struct bnxt_filter_info *filter)
 455 {
 456         int rc = 0;
 457         struct bnxt_filter_info *l2_filter = filter;
 458         struct bnxt_vnic_info *vnic = NULL;
 459         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 460         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 461
 462         if (filter->fw_l2_filter_id == UINT64_MAX)
 463                 return 0;
 464
 465         if (filter->matching_l2_fltr_ptr)
 466                 l2_filter = filter->matching_l2_fltr_ptr;
 467
 468         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 469                     filter, l2_filter, l2_filter->l2_ref_cnt);
 470
 471         if (l2_filter->l2_ref_cnt == 0)
 472                 return 0;
 473
 474         if (l2_filter->l2_ref_cnt > 0)
 475                 l2_filter->l2_ref_cnt--;
 476
 477         if (l2_filter->l2_ref_cnt > 0)
 478                 return 0;
 479
 480         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 481
 482         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 483
 484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 485
 486         HWRM_CHECK_RESULT();
 487         HWRM_UNLOCK();
 488
 489         filter->fw_l2_filter_id = UINT64_MAX;
 490         if (l2_filter->l2_ref_cnt == 0) {
 491                 vnic = l2_filter->vnic;
 492                 if (vnic) {
 493                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 494                                       bnxt_filter_info, next);
 495                         bnxt_free_filter(bp, l2_filter);
 496                 }
 497         }
 498
 499         return 0;
 500 }
 501
 502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 503                          uint16_t dst_id,
 504                          struct bnxt_filter_info *filter)
 505 {
 506         int rc = 0;
 507         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 508         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 509         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 510         const struct rte_eth_vmdq_rx_conf *conf =
 511                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 512         uint32_t enables = 0;
 513         uint16_t j = dst_id - 1;
 514
 515         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 516         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 517             conf->pool_map[j].pools & (1UL << j)) {
 518                 PMD_DRV_LOG(DEBUG,
 519                         "Add vlan %u to vmdq pool %u\n",
 520                         conf->pool_map[j].vlan_id, j);
 521
 522                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 523                 filter->enables |=
 524                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 525                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 526         }
 527
 528         if (filter->fw_l2_filter_id != UINT64_MAX)
 529                 bnxt_hwrm_clear_l2_filter(bp, filter);
 530
 531         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 532
 533         req.flags = rte_cpu_to_le_32(filter->flags);
 534
 535         enables = filter->enables |
 536               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 537         req.dst_id = rte_cpu_to_le_16(dst_id);
 538
 539         if (enables &
 540             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 541                 memcpy(req.l2_addr, filter->l2_addr,
 542                        RTE_ETHER_ADDR_LEN);
 543         if (enables &
 544             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 545                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 546                        RTE_ETHER_ADDR_LEN);
 547         if (enables &
 548             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 549                 req.l2_ovlan = filter->l2_ovlan;
 550         if (enables &
 551             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 552                 req.l2_ivlan = filter->l2_ivlan;
 553         if (enables &
 554             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 555                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 556         if (enables &
 557             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 558                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 559         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 560                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 561         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 562                 req.src_type = filter->src_type;
 563         if (filter->pri_hint) {
 564                 req.pri_hint = filter->pri_hint;
 565                 req.l2_filter_id_hint =
 566                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 567         }
 568
 569         req.enables = rte_cpu_to_le_32(enables);
 570
 571         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 572
 573         HWRM_CHECK_RESULT();
 574
 575         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 576         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 577         HWRM_UNLOCK();
 578
 579         filter->l2_ref_cnt++;
 580
 581         return rc;
 582 }
 583
 584 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 585 {
 586         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 587         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 588         uint32_t flags = 0;
 589         int rc;
 590
 591         if (!ptp)
 592                 return 0;
 593
 594         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 595
 596         if (ptp->rx_filter)
 597                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 598         else
 599                 flags |=
 600                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 601         if (ptp->tx_tstamp_en)
 602                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 603         else
 604                 flags |=
 605                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 606         req.flags = rte_cpu_to_le_32(flags);
 607         req.enables = rte_cpu_to_le_32
 608                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 609         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 610
 611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 612         HWRM_UNLOCK();
 613
 614         return rc;
 615 }
 616
 617 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 618 {
 619         int rc = 0;
 620         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 621         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 622         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 623
 624         if (ptp)
 625                 return 0;
 626
 627         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 628
 629         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 630
 631         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 632
 633         HWRM_CHECK_RESULT();
 634
 635         if (!BNXT_CHIP_THOR(bp) &&
 636             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 637                 return 0;
 638
 639         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 640                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 641
 642         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 643         if (!ptp)
 644                 return -ENOMEM;
 645
 646         if (!BNXT_CHIP_THOR(bp)) {
 647                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 648                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 649                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 650                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 651                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 652                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 653                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 654                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 655                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 656                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 657                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 658                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 659                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 660                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 661                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 662                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 663                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 664                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 665         }
 666
 667         ptp->bp = bp;
 668         bp->ptp_cfg = ptp;
 669
 670         return 0;
 671 }
 672
 673 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 674 {
 675         int rc = 0;
 676         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 677         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 678         uint16_t new_max_vfs;
 679         uint32_t flags;
 680         int i;
 681
 682         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 683
 684         req.fid = rte_cpu_to_le_16(0xffff);
 685
 686         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 687
 688         HWRM_CHECK_RESULT();
 689
 690         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 691         flags = rte_le_to_cpu_32(resp->flags);
 692         if (BNXT_PF(bp)) {
 693                 bp->pf->port_id = resp->port_id;
 694                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 695                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 696                 new_max_vfs = bp->pdev->max_vfs;
 697                 if (new_max_vfs != bp->pf->max_vfs) {
 698                         if (bp->pf->vf_info)
 699                                 rte_free(bp->pf->vf_info);
 700                         bp->pf->vf_info = rte_malloc("bnxt_vf_info",
 701                             sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
 702                         bp->pf->max_vfs = new_max_vfs;
 703                         for (i = 0; i < new_max_vfs; i++) {
 704                                 bp->pf->vf_info[i].fid =
 705                                         bp->pf->first_vf_id + i;
 706                                 bp->pf->vf_info[i].vlan_table =
 707                                         rte_zmalloc("VF VLAN table",
 708                                                     getpagesize(),
 709                                                     getpagesize());
 710                                 if (bp->pf->vf_info[i].vlan_table == NULL)
 711                                         PMD_DRV_LOG(ERR,
 712                                         "Fail to alloc VLAN table for VF %d\n",
 713                                         i);
 714                                 else
 715                                         rte_mem_lock_page(
 716                                                 bp->pf->vf_info[i].vlan_table);
 717                                 bp->pf->vf_info[i].vlan_as_table =
 718                                         rte_zmalloc("VF VLAN AS table",
 719                                                     getpagesize(),
 720                                                     getpagesize());
 721                                 if (bp->pf->vf_info[i].vlan_as_table == NULL)
 722                                         PMD_DRV_LOG(ERR,
 723                                         "Alloc VLAN AS table for VF %d fail\n",
 724                                         i);
 725                                 else
 726                                         rte_mem_lock_page(
 727                                               bp->pf->vf_info[i].vlan_as_table);
 728                                 STAILQ_INIT(&bp->pf->vf_info[i].filter);
 729                         }
 730                 }
 731         }
 732
 733         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 734         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 735         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 736         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 737         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 738         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 739         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 740         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 741         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 742         if (!BNXT_CHIP_THOR(bp))
 743                 bp->max_l2_ctx += bp->max_rx_em_flows;
 744         /* TODO: For now, do not support VMDq/RFS on VFs. */
 745         if (BNXT_PF(bp)) {
 746                 if (bp->pf->max_vfs)
 747                         bp->max_vnics = 1;
 748                 else
 749                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 750         } else {
 751                 bp->max_vnics = 1;
 752         }
 753         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 754                     bp->max_l2_ctx, bp->max_vnics);
 755         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 756         if (BNXT_PF(bp)) {
 757                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 758                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 759                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 760                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 761                         HWRM_UNLOCK();
 762                         bnxt_hwrm_ptp_qcfg(bp);
 763                 }
 764         }
 765
 766         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 767                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 768
 769         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 770                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 771                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 772         }
 773
 774         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 775                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 776
 777         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 778                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 779
 780         HWRM_UNLOCK();
 781
 782         return rc;
 783 }
 784
 785 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 786 {
 787         int rc;
 788
 789         rc = __bnxt_hwrm_func_qcaps(bp);
 790         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 791                 rc = bnxt_alloc_ctx_mem(bp);
 792                 if (rc)
 793                         return rc;
 794
 795                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 796                 if (!rc)
 797                         bp->flags |= BNXT_FLAG_NEW_RM;
 798         }
 799
 800         /* On older FW,
 801          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 802          * But the error can be ignored. Return success.
 803          */
 804
 805         return 0;
 806 }
 807
 808 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 809 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 810 {
 811         int rc = 0;
 812         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 813         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 814
 815         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 816
 817         req.target_id = rte_cpu_to_le_16(0xffff);
 818
 819         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 820
 821         HWRM_CHECK_RESULT();
 822
 823         if (rte_le_to_cpu_32(resp->flags) &
 824             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 825                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 826                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 827         }
 828
 829         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 830
 831         HWRM_UNLOCK();
 832
 833         return rc;
 834 }
 835
 836 int bnxt_hwrm_func_reset(struct bnxt *bp)
 837 {
 838         int rc = 0;
 839         struct hwrm_func_reset_input req = {.req_type = 0 };
 840         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 841
 842         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 843
 844         req.enables = rte_cpu_to_le_32(0);
 845
 846         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 847
 848         HWRM_CHECK_RESULT();
 849         HWRM_UNLOCK();
 850
 851         return rc;
 852 }
 853
 854 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 855 {
 856         int rc;
 857         uint32_t flags = 0;
 858         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 859         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 860
 861         if (bp->flags & BNXT_FLAG_REGISTERED)
 862                 return 0;
 863
 864         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 865                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 866         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 867                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 868
 869         /* PFs and trusted VFs should indicate the support of the
 870          * Master capability on non Stingray platform
 871          */
 872         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 873                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 874
 875         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 876         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 877                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 878         req.ver_maj = RTE_VER_YEAR;
 879         req.ver_min = RTE_VER_MONTH;
 880         req.ver_upd = RTE_VER_MINOR;
 881
 882         if (BNXT_PF(bp)) {
 883                 req.enables |= rte_cpu_to_le_32(
 884                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 885                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
 886                        RTE_MIN(sizeof(req.vf_req_fwd),
 887                                sizeof(bp->pf->vf_req_fwd)));
 888
 889                 /*
 890                  * PF can sniff HWRM API issued by VF. This can be set up by
 891                  * linux driver and inherited by the DPDK PF driver. Clear
 892                  * this HWRM sniffer list in FW because DPDK PF driver does
 893                  * not support this.
 894                  */
 895                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 896         }
 897
 898         req.flags = rte_cpu_to_le_32(flags);
 899
 900         req.async_event_fwd[0] |=
 901                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 902                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 903                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 904                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 905                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 906         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 907                 req.async_event_fwd[0] |=
 908                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 909         req.async_event_fwd[1] |=
 910                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 911                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 912         if (BNXT_PF(bp))
 913                 req.async_event_fwd[1] |=
 914                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 915
 916         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 917
 918         HWRM_CHECK_RESULT();
 919
 920         flags = rte_le_to_cpu_32(resp->flags);
 921         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 922                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 923
 924         HWRM_UNLOCK();
 925
 926         bp->flags |= BNXT_FLAG_REGISTERED;
 927
 928         return rc;
 929 }
 930
 931 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 932 {
 933         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 934                 return 0;
 935
 936         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 937 }
 938
 939 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 940 {
 941         int rc;
 942         uint32_t flags = 0;
 943         uint32_t enables;
 944         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 945         struct hwrm_func_vf_cfg_input req = {0};
 946
 947         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 948
 949         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 950                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 951                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 952                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 953                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 954
 955         if (BNXT_HAS_RING_GRPS(bp)) {
 956                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 957                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 958         }
 959
 960         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 961         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 962                                             AGG_RING_MULTIPLIER);
 963         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 964         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 965                                               bp->tx_nr_rings +
 966                                               BNXT_NUM_ASYNC_CPR(bp));
 967         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 968         if (bp->vf_resv_strategy ==
 969             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 970                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 971                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 972                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 973                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 974                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 975                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 976         } else if (bp->vf_resv_strategy ==
 977                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 978                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 979                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 980         }
 981
 982         if (test)
 983                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 984                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 985                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 986                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 987                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 988                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 989
 990         if (test && BNXT_HAS_RING_GRPS(bp))
 991                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 992
 993         req.flags = rte_cpu_to_le_32(flags);
 994         req.enables |= rte_cpu_to_le_32(enables);
 995
 996         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 997
 998         if (test)
 999                 HWRM_CHECK_RESULT_SILENT();
1000         else
1001                 HWRM_CHECK_RESULT();
1002
1003         HWRM_UNLOCK();
1004         return rc;
1005 }
1006
1007 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1008 {
1009         int rc;
1010         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1011         struct hwrm_func_resource_qcaps_input req = {0};
1012
1013         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1014         req.fid = rte_cpu_to_le_16(0xffff);
1015
1016         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1017
1018         HWRM_CHECK_RESULT_SILENT();
1019
1020         if (BNXT_VF(bp)) {
1021                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1022                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1023                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1024                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1025                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1026                 /* func_resource_qcaps does not return max_rx_em_flows.
1027                  * So use the value provided by func_qcaps.
1028                  */
1029                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1030                 if (!BNXT_CHIP_THOR(bp))
1031                         bp->max_l2_ctx += bp->max_rx_em_flows;
1032                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1033                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1034         }
1035         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1036         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1037         if (bp->vf_resv_strategy >
1038             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1039                 bp->vf_resv_strategy =
1040                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1041
1042         HWRM_UNLOCK();
1043         return rc;
1044 }
1045
1046 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1047 {
1048         int rc = 0;
1049         struct hwrm_ver_get_input req = {.req_type = 0 };
1050         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1051         uint32_t fw_version;
1052         uint16_t max_resp_len;
1053         char type[RTE_MEMZONE_NAMESIZE];
1054         uint32_t dev_caps_cfg;
1055
1056         bp->max_req_len = HWRM_MAX_REQ_LEN;
1057         bp->hwrm_cmd_timeout = timeout;
1058         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1059
1060         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1061         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1062         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1063
1064         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1065
1066         if (bp->flags & BNXT_FLAG_FW_RESET)
1067                 HWRM_CHECK_RESULT_SILENT();
1068         else
1069                 HWRM_CHECK_RESULT();
1070
1071         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1072                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1073                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1074                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1075         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1076                      (resp->hwrm_fw_min_8b << 16) |
1077                      (resp->hwrm_fw_bld_8b << 8) |
1078                      resp->hwrm_fw_rsvd_8b;
1079         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1080                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1081
1082         fw_version = resp->hwrm_intf_maj_8b << 16;
1083         fw_version |= resp->hwrm_intf_min_8b << 8;
1084         fw_version |= resp->hwrm_intf_upd_8b;
1085         bp->hwrm_spec_code = fw_version;
1086
1087         /* def_req_timeout value is in milliseconds */
1088         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1089         /* convert timeout to usec */
1090         bp->hwrm_cmd_timeout *= 1000;
1091         if (!bp->hwrm_cmd_timeout)
1092                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1093
1094         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1095                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1096                 rc = -EINVAL;
1097                 goto error;
1098         }
1099
1100         if (bp->max_req_len > resp->max_req_win_len) {
1101                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1102                 rc = -EINVAL;
1103         }
1104         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1105         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1106         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1107                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1108
1109         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1110         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1111
1112         if (bp->max_resp_len != max_resp_len) {
1113                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1114                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1115                         bp->pdev->addr.devid, bp->pdev->addr.function);
1116
1117                 rte_free(bp->hwrm_cmd_resp_addr);
1118
1119                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1120                 if (bp->hwrm_cmd_resp_addr == NULL) {
1121                         rc = -ENOMEM;
1122                         goto error;
1123                 }
1124                 bp->hwrm_cmd_resp_dma_addr =
1125                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1126                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1127                         PMD_DRV_LOG(ERR,
1128                         "Unable to map response buffer to physical memory.\n");
1129                         rc = -ENOMEM;
1130                         goto error;
1131                 }
1132                 bp->max_resp_len = max_resp_len;
1133         }
1134
1135         if ((dev_caps_cfg &
1136                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1137             (dev_caps_cfg &
1138              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1139                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1140                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1141         }
1142
1143         if (((dev_caps_cfg &
1144               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1145              (dev_caps_cfg &
1146               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1147             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1148                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1149                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1150                         bp->pdev->addr.devid, bp->pdev->addr.function);
1151
1152                 rte_free(bp->hwrm_short_cmd_req_addr);
1153
1154                 bp->hwrm_short_cmd_req_addr =
1155                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1156                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1157                         rc = -ENOMEM;
1158                         goto error;
1159                 }
1160                 bp->hwrm_short_cmd_req_dma_addr =
1161                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1162                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1163                         rte_free(bp->hwrm_short_cmd_req_addr);
1164                         PMD_DRV_LOG(ERR,
1165                                 "Unable to map buffer to physical memory.\n");
1166                         rc = -ENOMEM;
1167                         goto error;
1168                 }
1169         }
1170         if (dev_caps_cfg &
1171             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1172                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1173                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1174         }
1175         if (dev_caps_cfg &
1176             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1177                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1178         if (dev_caps_cfg &
1179             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1180                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1181                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1182         }
1183
1184         if (dev_caps_cfg &
1185             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1186                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1187                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1188         }
1189
1190
1191 error:
1192         HWRM_UNLOCK();
1193         return rc;
1194 }
1195
1196 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1197 {
1198         int rc;
1199         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1200         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1201
1202         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1203                 return 0;
1204
1205         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1206         req.flags = flags;
1207
1208         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1209
1210         HWRM_CHECK_RESULT();
1211         HWRM_UNLOCK();
1212
1213         return rc;
1214 }
1215
1216 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1217 {
1218         int rc = 0;
1219         struct hwrm_port_phy_cfg_input req = {0};
1220         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1221         uint32_t enables = 0;
1222
1223         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1224
1225         if (conf->link_up) {
1226                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1227                 if (bp->link_info->auto_mode && conf->link_speed) {
1228                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1229                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1230                 }
1231
1232                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1233                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1234                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1235                 /*
1236                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1237                  * any auto mode, even "none".
1238                  */
1239                 if (!conf->link_speed) {
1240                         /* No speeds specified. Enable AutoNeg - all speeds */
1241                         req.auto_mode =
1242                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1243                 }
1244                 /* AutoNeg - Advertise speeds specified. */
1245                 if (conf->auto_link_speed_mask &&
1246                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1247                         req.auto_mode =
1248                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1249                         req.auto_link_speed_mask =
1250                                 conf->auto_link_speed_mask;
1251                         enables |=
1252                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1253                 }
1254
1255                 req.auto_duplex = conf->duplex;
1256                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1257                 req.auto_pause = conf->auto_pause;
1258                 req.force_pause = conf->force_pause;
1259                 /* Set force_pause if there is no auto or if there is a force */
1260                 if (req.auto_pause && !req.force_pause)
1261                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1262                 else
1263                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1264
1265                 req.enables = rte_cpu_to_le_32(enables);
1266         } else {
1267                 req.flags =
1268                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1269                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1270         }
1271
1272         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1273
1274         HWRM_CHECK_RESULT();
1275         HWRM_UNLOCK();
1276
1277         return rc;
1278 }
1279
1280 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1281                                    struct bnxt_link_info *link_info)
1282 {
1283         int rc = 0;
1284         struct hwrm_port_phy_qcfg_input req = {0};
1285         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1286
1287         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1288
1289         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1290
1291         HWRM_CHECK_RESULT();
1292
1293         link_info->phy_link_status = resp->link;
1294         link_info->link_up =
1295                 (link_info->phy_link_status ==
1296                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1297         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1298         link_info->duplex = resp->duplex_cfg;
1299         link_info->pause = resp->pause;
1300         link_info->auto_pause = resp->auto_pause;
1301         link_info->force_pause = resp->force_pause;
1302         link_info->auto_mode = resp->auto_mode;
1303         link_info->phy_type = resp->phy_type;
1304         link_info->media_type = resp->media_type;
1305
1306         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1307         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1308         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1309         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1310         link_info->phy_ver[0] = resp->phy_maj;
1311         link_info->phy_ver[1] = resp->phy_min;
1312         link_info->phy_ver[2] = resp->phy_bld;
1313
1314         HWRM_UNLOCK();
1315
1316         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1317         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1318         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1319         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1320         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1321                     link_info->auto_link_speed_mask);
1322         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1323                     link_info->force_link_speed);
1324
1325         return rc;
1326 }
1327
1328 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1329 {
1330         int i = 0;
1331
1332         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1333                 if (bp->tx_cos_queue[i].profile ==
1334                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1335                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1336                         return true;
1337                 }
1338         }
1339         return false;
1340 }
1341
1342 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1343 {
1344         int i = 0;
1345
1346         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1347                 if (bp->tx_cos_queue[i].profile !=
1348                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1349                     bp->tx_cos_queue[i].id !=
1350                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1351                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1352                         break;
1353                 }
1354         }
1355 }
1356
1357 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1358 {
1359         int rc = 0;
1360         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1361         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1362         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1363         int i;
1364
1365 get_rx_info:
1366         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1367
1368         req.flags = rte_cpu_to_le_32(dir);
1369         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1370         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1371             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1372                 req.drv_qmap_cap =
1373                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1375
1376         HWRM_CHECK_RESULT();
1377
1378         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1379                 GET_TX_QUEUE_INFO(0);
1380                 GET_TX_QUEUE_INFO(1);
1381                 GET_TX_QUEUE_INFO(2);
1382                 GET_TX_QUEUE_INFO(3);
1383                 GET_TX_QUEUE_INFO(4);
1384                 GET_TX_QUEUE_INFO(5);
1385                 GET_TX_QUEUE_INFO(6);
1386                 GET_TX_QUEUE_INFO(7);
1387         } else  {
1388                 GET_RX_QUEUE_INFO(0);
1389                 GET_RX_QUEUE_INFO(1);
1390                 GET_RX_QUEUE_INFO(2);
1391                 GET_RX_QUEUE_INFO(3);
1392                 GET_RX_QUEUE_INFO(4);
1393                 GET_RX_QUEUE_INFO(5);
1394                 GET_RX_QUEUE_INFO(6);
1395                 GET_RX_QUEUE_INFO(7);
1396         }
1397
1398         HWRM_UNLOCK();
1399
1400         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1401                 goto done;
1402
1403         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1404                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1405         } else {
1406                 int j;
1407
1408                 /* iterate and find the COSq profile to use for Tx */
1409                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1410                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1411                                 if (bp->tx_cos_queue[i].id != 0xff)
1412                                         bp->tx_cosq_id[j++] =
1413                                                 bp->tx_cos_queue[i].id;
1414                         }
1415                 } else {
1416                         /* When CoS classification is disabled, for normal NIC
1417                          * operations, ideally we should look to use LOSSY.
1418                          * If not found, fallback to the first valid profile
1419                          */
1420                         if (!bnxt_find_lossy_profile(bp))
1421                                 bnxt_find_first_valid_profile(bp);
1422
1423                 }
1424         }
1425
1426         bp->max_tc = resp->max_configurable_queues;
1427         bp->max_lltc = resp->max_configurable_lossless_queues;
1428         if (bp->max_tc > BNXT_MAX_QUEUE)
1429                 bp->max_tc = BNXT_MAX_QUEUE;
1430         bp->max_q = bp->max_tc;
1431
1432         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1433                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1434                 goto get_rx_info;
1435         }
1436
1437 done:
1438         return rc;
1439 }
1440
1441 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1442                          struct bnxt_ring *ring,
1443                          uint32_t ring_type, uint32_t map_index,
1444                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1445                          uint16_t tx_cosq_id)
1446 {
1447         int rc = 0;
1448         uint32_t enables = 0;
1449         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1450         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1451         struct rte_mempool *mb_pool;
1452         uint16_t rx_buf_size;
1453
1454         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1455
1456         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1457         req.fbo = rte_cpu_to_le_32(0);
1458         /* Association of ring index with doorbell index */
1459         req.logical_id = rte_cpu_to_le_16(map_index);
1460         req.length = rte_cpu_to_le_32(ring->ring_size);
1461
1462         switch (ring_type) {
1463         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1464                 req.ring_type = ring_type;
1465                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1466                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1467                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1468                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1469                         enables |=
1470                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1471                 break;
1472         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1473                 req.ring_type = ring_type;
1474                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1475                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1476                 if (BNXT_CHIP_THOR(bp)) {
1477                         mb_pool = bp->rx_queues[0]->mb_pool;
1478                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1479                                       RTE_PKTMBUF_HEADROOM;
1480                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1481                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1482                         enables |=
1483                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1484                 }
1485                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1486                         enables |=
1487                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1488                 break;
1489         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1490                 req.ring_type = ring_type;
1491                 if (BNXT_HAS_NQ(bp)) {
1492                         /* Association of cp ring with nq */
1493                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1494                         enables |=
1495                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1496                 }
1497                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1498                 break;
1499         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1500                 req.ring_type = ring_type;
1501                 req.page_size = BNXT_PAGE_SHFT;
1502                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1503                 break;
1504         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1505                 req.ring_type = ring_type;
1506                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1507
1508                 mb_pool = bp->rx_queues[0]->mb_pool;
1509                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1510                               RTE_PKTMBUF_HEADROOM;
1511                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1512                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1513
1514                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1515                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1516                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1517                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1518                 break;
1519         default:
1520                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1521                         ring_type);
1522                 HWRM_UNLOCK();
1523                 return -EINVAL;
1524         }
1525         req.enables = rte_cpu_to_le_32(enables);
1526
1527         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1528
1529         if (rc || resp->error_code) {
1530                 if (rc == 0 && resp->error_code)
1531                         rc = rte_le_to_cpu_16(resp->error_code);
1532                 switch (ring_type) {
1533                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1534                         PMD_DRV_LOG(ERR,
1535                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1536                         HWRM_UNLOCK();
1537                         return rc;
1538                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1539                         PMD_DRV_LOG(ERR,
1540                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1541                         HWRM_UNLOCK();
1542                         return rc;
1543                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1544                         PMD_DRV_LOG(ERR,
1545                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1546                                     rc);
1547                         HWRM_UNLOCK();
1548                         return rc;
1549                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1550                         PMD_DRV_LOG(ERR,
1551                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1552                         HWRM_UNLOCK();
1553                         return rc;
1554                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1555                         PMD_DRV_LOG(ERR,
1556                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1557                         HWRM_UNLOCK();
1558                         return rc;
1559                 default:
1560                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1561                         HWRM_UNLOCK();
1562                         return rc;
1563                 }
1564         }
1565
1566         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1567         HWRM_UNLOCK();
1568         return rc;
1569 }
1570
1571 int bnxt_hwrm_ring_free(struct bnxt *bp,
1572                         struct bnxt_ring *ring, uint32_t ring_type)
1573 {
1574         int rc;
1575         struct hwrm_ring_free_input req = {.req_type = 0 };
1576         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1577
1578         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1579
1580         req.ring_type = ring_type;
1581         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1582
1583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1584
1585         if (rc || resp->error_code) {
1586                 if (rc == 0 && resp->error_code)
1587                         rc = rte_le_to_cpu_16(resp->error_code);
1588                 HWRM_UNLOCK();
1589
1590                 switch (ring_type) {
1591                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1592                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1593                                 rc);
1594                         return rc;
1595                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1596                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1597                                 rc);
1598                         return rc;
1599                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1600                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1601                                 rc);
1602                         return rc;
1603                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1604                         PMD_DRV_LOG(ERR,
1605                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1606                         return rc;
1607                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1608                         PMD_DRV_LOG(ERR,
1609                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1610                         return rc;
1611                 default:
1612                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1613                         return rc;
1614                 }
1615         }
1616         HWRM_UNLOCK();
1617         return 0;
1618 }
1619
1620 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1621 {
1622         int rc = 0;
1623         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1624         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1625
1626         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1627
1628         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1629         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1630         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1631         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1632
1633         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1634
1635         HWRM_CHECK_RESULT();
1636
1637         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1638
1639         HWRM_UNLOCK();
1640
1641         return rc;
1642 }
1643
1644 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1645 {
1646         int rc;
1647         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1648         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1649
1650         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1651
1652         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1653
1654         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1655
1656         HWRM_CHECK_RESULT();
1657         HWRM_UNLOCK();
1658
1659         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1660         return rc;
1661 }
1662
1663 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1664 {
1665         int rc = 0;
1666         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1667         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1668
1669         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1670                 return rc;
1671
1672         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1673
1674         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1675
1676         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1677
1678         HWRM_CHECK_RESULT();
1679         HWRM_UNLOCK();
1680
1681         return rc;
1682 }
1683
1684 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1685                                 unsigned int idx __rte_unused)
1686 {
1687         int rc;
1688         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1689         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1690
1691         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1692
1693         req.update_period_ms = rte_cpu_to_le_32(0);
1694
1695         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1696
1697         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1698
1699         HWRM_CHECK_RESULT();
1700
1701         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1702
1703         HWRM_UNLOCK();
1704
1705         return rc;
1706 }
1707
1708 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1709                                 unsigned int idx __rte_unused)
1710 {
1711         int rc;
1712         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1713         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1714
1715         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1716
1717         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1718
1719         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1720
1721         HWRM_CHECK_RESULT();
1722         HWRM_UNLOCK();
1723
1724         return rc;
1725 }
1726
1727 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1728 {
1729         int rc = 0, i, j;
1730         struct hwrm_vnic_alloc_input req = { 0 };
1731         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1732
1733         if (!BNXT_HAS_RING_GRPS(bp))
1734                 goto skip_ring_grps;
1735
1736         /* map ring groups to this vnic */
1737         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1738                 vnic->start_grp_id, vnic->end_grp_id);
1739         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1740                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1741
1742         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1743         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1744         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1745         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1746
1747 skip_ring_grps:
1748         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1749         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1750
1751         if (vnic->func_default)
1752                 req.flags =
1753                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1754         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1755
1756         HWRM_CHECK_RESULT();
1757
1758         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1759         HWRM_UNLOCK();
1760         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1761         return rc;
1762 }
1763
1764 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1765                                         struct bnxt_vnic_info *vnic,
1766                                         struct bnxt_plcmodes_cfg *pmode)
1767 {
1768         int rc = 0;
1769         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1770         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1771
1772         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1773
1774         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1775
1776         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1777
1778         HWRM_CHECK_RESULT();
1779
1780         pmode->flags = rte_le_to_cpu_32(resp->flags);
1781         /* dflt_vnic bit doesn't exist in the _cfg command */
1782         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1783         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1784         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1785         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1786
1787         HWRM_UNLOCK();
1788
1789         return rc;
1790 }
1791
1792 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1793                                        struct bnxt_vnic_info *vnic,
1794                                        struct bnxt_plcmodes_cfg *pmode)
1795 {
1796         int rc = 0;
1797         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1798         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1799
1800         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1801                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1802                 return rc;
1803         }
1804
1805         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1806
1807         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1808         req.flags = rte_cpu_to_le_32(pmode->flags);
1809         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1810         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1811         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1812         req.enables = rte_cpu_to_le_32(
1813             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1814             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1815             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1816         );
1817
1818         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1819
1820         HWRM_CHECK_RESULT();
1821         HWRM_UNLOCK();
1822
1823         return rc;
1824 }
1825
1826 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1827 {
1828         int rc = 0;
1829         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1830         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1831         struct bnxt_plcmodes_cfg pmodes = { 0 };
1832         uint32_t ctx_enable_flag = 0;
1833         uint32_t enables = 0;
1834
1835         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1836                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1837                 return rc;
1838         }
1839
1840         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1841         if (rc)
1842                 return rc;
1843
1844         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1845
1846         if (BNXT_CHIP_THOR(bp)) {
1847                 int dflt_rxq = vnic->start_grp_id;
1848                 struct bnxt_rx_ring_info *rxr;
1849                 struct bnxt_cp_ring_info *cpr;
1850                 struct bnxt_rx_queue *rxq;
1851                 int i;
1852
1853                 /*
1854                  * The first active receive ring is used as the VNIC
1855                  * default receive ring. If there are no active receive
1856                  * rings (all corresponding receive queues are stopped),
1857                  * the first receive ring is used.
1858                  */
1859                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1860                         rxq = bp->eth_dev->data->rx_queues[i];
1861                         if (rxq->rx_started) {
1862                                 dflt_rxq = i;
1863                                 break;
1864                         }
1865                 }
1866
1867                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1868                 rxr = rxq->rx_ring;
1869                 cpr = rxq->cp_ring;
1870
1871                 req.default_rx_ring_id =
1872                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1873                 req.default_cmpl_ring_id =
1874                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1875                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1876                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1877                 goto config_mru;
1878         }
1879
1880         /* Only RSS support for now TBD: COS & LB */
1881         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1882         if (vnic->lb_rule != 0xffff)
1883                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1884         if (vnic->cos_rule != 0xffff)
1885                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1886         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1887                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1888                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1889         }
1890         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1891                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1892                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1893         }
1894
1895         enables |= ctx_enable_flag;
1896         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1897         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1898         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1899         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1900
1901 config_mru:
1902         req.enables = rte_cpu_to_le_32(enables);
1903         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1904         req.mru = rte_cpu_to_le_16(vnic->mru);
1905         /* Configure default VNIC only once. */
1906         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1907                 req.flags |=
1908                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1909                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1910         }
1911         if (vnic->vlan_strip)
1912                 req.flags |=
1913                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1914         if (vnic->bd_stall)
1915                 req.flags |=
1916                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1917         if (vnic->roce_dual)
1918                 req.flags |= rte_cpu_to_le_32(
1919                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1920         if (vnic->roce_only)
1921                 req.flags |= rte_cpu_to_le_32(
1922                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1923         if (vnic->rss_dflt_cr)
1924                 req.flags |= rte_cpu_to_le_32(
1925                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1926
1927         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1928
1929         HWRM_CHECK_RESULT();
1930         HWRM_UNLOCK();
1931
1932         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1933
1934         return rc;
1935 }
1936
1937 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1938                 int16_t fw_vf_id)
1939 {
1940         int rc = 0;
1941         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1942         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1943
1944         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1945                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1946                 return rc;
1947         }
1948         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1949
1950         req.enables =
1951                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1952         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1953         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1954
1955         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1956
1957         HWRM_CHECK_RESULT();
1958
1959         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1960         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1961         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1962         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1963         vnic->mru = rte_le_to_cpu_16(resp->mru);
1964         vnic->func_default = rte_le_to_cpu_32(
1965                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1966         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1967                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1968         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1969                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1970         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1971                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1972         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1973                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1974         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1975                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1976
1977         HWRM_UNLOCK();
1978
1979         return rc;
1980 }
1981
1982 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1983                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1984 {
1985         int rc = 0;
1986         uint16_t ctx_id;
1987         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1988         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1989                                                 bp->hwrm_cmd_resp_addr;
1990
1991         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1992
1993         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1994         HWRM_CHECK_RESULT();
1995
1996         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1997         if (!BNXT_HAS_RING_GRPS(bp))
1998                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1999         else if (ctx_idx == 0)
2000                 vnic->rss_rule = ctx_id;
2001
2002         HWRM_UNLOCK();
2003
2004         return rc;
2005 }
2006
2007 static
2008 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2009                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2010 {
2011         int rc = 0;
2012         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2013         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2014                                                 bp->hwrm_cmd_resp_addr;
2015
2016         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2017                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2018                 return rc;
2019         }
2020         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2021
2022         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2023
2024         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2025
2026         HWRM_CHECK_RESULT();
2027         HWRM_UNLOCK();
2028
2029         return rc;
2030 }
2031
2032 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2033 {
2034         int rc = 0;
2035
2036         if (BNXT_CHIP_THOR(bp)) {
2037                 int j;
2038
2039                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2040                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2041                                                       vnic,
2042                                                       vnic->fw_grp_ids[j]);
2043                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2044                 }
2045                 vnic->num_lb_ctxts = 0;
2046         } else {
2047                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2048                 vnic->rss_rule = INVALID_HW_RING_ID;
2049         }
2050
2051         return rc;
2052 }
2053
2054 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2055 {
2056         int rc = 0;
2057         struct hwrm_vnic_free_input req = {.req_type = 0 };
2058         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2059
2060         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2061                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2062                 return rc;
2063         }
2064
2065         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2066
2067         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2068
2069         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2070
2071         HWRM_CHECK_RESULT();
2072         HWRM_UNLOCK();
2073
2074         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2075         /* Configure default VNIC again if necessary. */
2076         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2077                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2078
2079         return rc;
2080 }
2081
2082 static int
2083 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2084 {
2085         int i;
2086         int rc = 0;
2087         int nr_ctxs = vnic->num_lb_ctxts;
2088         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2089         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2090
2091         for (i = 0; i < nr_ctxs; i++) {
2092                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2093
2094                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2095                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2096                 req.hash_mode_flags = vnic->hash_mode;
2097
2098                 req.hash_key_tbl_addr =
2099                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2100
2101                 req.ring_grp_tbl_addr =
2102                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2103                                          i * HW_HASH_INDEX_SIZE);
2104                 req.ring_table_pair_index = i;
2105                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2106
2107                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2108                                             BNXT_USE_CHIMP_MB);
2109
2110                 HWRM_CHECK_RESULT();
2111                 HWRM_UNLOCK();
2112         }
2113
2114         return rc;
2115 }
2116
2117 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2118                            struct bnxt_vnic_info *vnic)
2119 {
2120         int rc = 0;
2121         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2122         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2123
2124         if (!vnic->rss_table)
2125                 return 0;
2126
2127         if (BNXT_CHIP_THOR(bp))
2128                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2129
2130         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2131
2132         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2133         req.hash_mode_flags = vnic->hash_mode;
2134
2135         req.ring_grp_tbl_addr =
2136             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2137         req.hash_key_tbl_addr =
2138             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2139         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2140         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2141
2142         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2143
2144         HWRM_CHECK_RESULT();
2145         HWRM_UNLOCK();
2146
2147         return rc;
2148 }
2149
2150 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2151                         struct bnxt_vnic_info *vnic)
2152 {
2153         int rc = 0;
2154         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2155         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2156         uint16_t size;
2157
2158         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2159                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2160                 return rc;
2161         }
2162
2163         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2164
2165         req.flags = rte_cpu_to_le_32(
2166                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2167
2168         req.enables = rte_cpu_to_le_32(
2169                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2170
2171         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2172         size -= RTE_PKTMBUF_HEADROOM;
2173         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2174
2175         req.jumbo_thresh = rte_cpu_to_le_16(size);
2176         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2177
2178         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2179
2180         HWRM_CHECK_RESULT();
2181         HWRM_UNLOCK();
2182
2183         return rc;
2184 }
2185
2186 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2187                         struct bnxt_vnic_info *vnic, bool enable)
2188 {
2189         int rc = 0;
2190         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2191         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2192
2193         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2194                 if (enable)
2195                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2196                 return -ENOTSUP;
2197         }
2198
2199         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2200                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2201                 return 0;
2202         }
2203
2204         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2205
2206         if (enable) {
2207                 req.enables = rte_cpu_to_le_32(
2208                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2209                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2210                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2211                 req.flags = rte_cpu_to_le_32(
2212                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2213                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2214                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2215                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2216                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2217                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2218                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2219                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2220                 req.min_agg_len = rte_cpu_to_le_32(512);
2221         }
2222         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2223
2224         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2225
2226         HWRM_CHECK_RESULT();
2227         HWRM_UNLOCK();
2228
2229         return rc;
2230 }
2231
2232 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2233 {
2234         struct hwrm_func_cfg_input req = {0};
2235         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2236         int rc;
2237
2238         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2239         req.enables = rte_cpu_to_le_32(
2240                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2241         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2242         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2243
2244         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2245
2246         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2247         HWRM_CHECK_RESULT();
2248         HWRM_UNLOCK();
2249
2250         bp->pf->vf_info[vf].random_mac = false;
2251
2252         return rc;
2253 }
2254
2255 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2256                                   uint64_t *dropped)
2257 {
2258         int rc = 0;
2259         struct hwrm_func_qstats_input req = {.req_type = 0};
2260         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2261
2262         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2263
2264         req.fid = rte_cpu_to_le_16(fid);
2265
2266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2267
2268         HWRM_CHECK_RESULT();
2269
2270         if (dropped)
2271                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2272
2273         HWRM_UNLOCK();
2274
2275         return rc;
2276 }
2277
2278 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2279                           struct rte_eth_stats *stats,
2280                           struct hwrm_func_qstats_output *func_qstats)
2281 {
2282         int rc = 0;
2283         struct hwrm_func_qstats_input req = {.req_type = 0};
2284         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2285
2286         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2287
2288         req.fid = rte_cpu_to_le_16(fid);
2289
2290         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2291
2292         HWRM_CHECK_RESULT();
2293         if (func_qstats)
2294                 memcpy(func_qstats, resp,
2295                        sizeof(struct hwrm_func_qstats_output));
2296
2297         if (!stats)
2298                 goto exit;
2299
2300         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2301         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2302         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2303         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2304         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2305         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2306
2307         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2308         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2309         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2310         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2311         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2312         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2313
2314         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2315         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2316         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2317
2318 exit:
2319         HWRM_UNLOCK();
2320
2321         return rc;
2322 }
2323
2324 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2325 {
2326         int rc = 0;
2327         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2328         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2329
2330         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2331
2332         req.fid = rte_cpu_to_le_16(fid);
2333
2334         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2335
2336         HWRM_CHECK_RESULT();
2337         HWRM_UNLOCK();
2338
2339         return rc;
2340 }
2341
2342 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2343 {
2344         unsigned int i;
2345         int rc = 0;
2346
2347         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2348                 struct bnxt_tx_queue *txq;
2349                 struct bnxt_rx_queue *rxq;
2350                 struct bnxt_cp_ring_info *cpr;
2351
2352                 if (i >= bp->rx_cp_nr_rings) {
2353                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2354                         cpr = txq->cp_ring;
2355                 } else {
2356                         rxq = bp->rx_queues[i];
2357                         cpr = rxq->cp_ring;
2358                 }
2359
2360                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2361                 if (rc)
2362                         return rc;
2363         }
2364         return 0;
2365 }
2366
2367 static int
2368 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2369 {
2370         int rc;
2371         unsigned int i;
2372         struct bnxt_cp_ring_info *cpr;
2373
2374         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2375
2376                 if (i >= bp->rx_cp_nr_rings) {
2377                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2378                 } else {
2379                         cpr = bp->rx_queues[i]->cp_ring;
2380                         if (BNXT_HAS_RING_GRPS(bp))
2381                                 bp->grp_info[i].fw_stats_ctx = -1;
2382                 }
2383                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2384                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2385                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2386                         if (rc)
2387                                 return rc;
2388                 }
2389         }
2390         return 0;
2391 }
2392
2393 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2394 {
2395         unsigned int i;
2396         int rc = 0;
2397
2398         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2399                 struct bnxt_tx_queue *txq;
2400                 struct bnxt_rx_queue *rxq;
2401                 struct bnxt_cp_ring_info *cpr;
2402
2403                 if (i >= bp->rx_cp_nr_rings) {
2404                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2405                         cpr = txq->cp_ring;
2406                 } else {
2407                         rxq = bp->rx_queues[i];
2408                         cpr = rxq->cp_ring;
2409                 }
2410
2411                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2412
2413                 if (rc)
2414                         return rc;
2415         }
2416         return rc;
2417 }
2418
2419 static int
2420 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2421 {
2422         uint16_t idx;
2423         uint32_t rc = 0;
2424
2425         if (!BNXT_HAS_RING_GRPS(bp))
2426                 return 0;
2427
2428         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2429
2430                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2431                         continue;
2432
2433                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2434
2435                 if (rc)
2436                         return rc;
2437         }
2438         return rc;
2439 }
2440
2441 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2442 {
2443         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2444
2445         bnxt_hwrm_ring_free(bp, cp_ring,
2446                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2447         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2448         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2449                                      sizeof(*cpr->cp_desc_ring));
2450         cpr->cp_raw_cons = 0;
2451         cpr->valid = 0;
2452 }
2453
2454 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2455 {
2456         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2457
2458         bnxt_hwrm_ring_free(bp, cp_ring,
2459                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2460         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2461         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2462                         sizeof(*cpr->cp_desc_ring));
2463         cpr->cp_raw_cons = 0;
2464         cpr->valid = 0;
2465 }
2466
2467 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2468 {
2469         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2470         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2471         struct bnxt_ring *ring = rxr->rx_ring_struct;
2472         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2473
2474         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2475                 bnxt_hwrm_ring_free(bp, ring,
2476                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2477                 ring->fw_ring_id = INVALID_HW_RING_ID;
2478                 if (BNXT_HAS_RING_GRPS(bp))
2479                         bp->grp_info[queue_index].rx_fw_ring_id =
2480                                                         INVALID_HW_RING_ID;
2481         }
2482         ring = rxr->ag_ring_struct;
2483         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2484                 bnxt_hwrm_ring_free(bp, ring,
2485                                     BNXT_CHIP_THOR(bp) ?
2486                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2487                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2488                 if (BNXT_HAS_RING_GRPS(bp))
2489                         bp->grp_info[queue_index].ag_fw_ring_id =
2490                                                         INVALID_HW_RING_ID;
2491         }
2492         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2493                 bnxt_free_cp_ring(bp, cpr);
2494
2495         if (BNXT_HAS_RING_GRPS(bp))
2496                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2497 }
2498
2499 static int
2500 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2501 {
2502         unsigned int i;
2503
2504         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2505                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2506                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2507                 struct bnxt_ring *ring = txr->tx_ring_struct;
2508                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2509
2510                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2511                         bnxt_hwrm_ring_free(bp, ring,
2512                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2513                         ring->fw_ring_id = INVALID_HW_RING_ID;
2514                         memset(txr->tx_desc_ring, 0,
2515                                         txr->tx_ring_struct->ring_size *
2516                                         sizeof(*txr->tx_desc_ring));
2517                         memset(txr->tx_buf_ring, 0,
2518                                         txr->tx_ring_struct->ring_size *
2519                                         sizeof(*txr->tx_buf_ring));
2520                         txr->tx_prod = 0;
2521                         txr->tx_cons = 0;
2522                 }
2523                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2524                         bnxt_free_cp_ring(bp, cpr);
2525                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2526                 }
2527         }
2528
2529         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2530                 bnxt_free_hwrm_rx_ring(bp, i);
2531
2532         return 0;
2533 }
2534
2535 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2536 {
2537         uint16_t i;
2538         uint32_t rc = 0;
2539
2540         if (!BNXT_HAS_RING_GRPS(bp))
2541                 return 0;
2542
2543         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2544                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2545                 if (rc)
2546                         return rc;
2547         }
2548         return rc;
2549 }
2550
2551 /*
2552  * HWRM utility functions
2553  */
2554
2555 void bnxt_free_hwrm_resources(struct bnxt *bp)
2556 {
2557         /* Release memzone */
2558         rte_free(bp->hwrm_cmd_resp_addr);
2559         rte_free(bp->hwrm_short_cmd_req_addr);
2560         bp->hwrm_cmd_resp_addr = NULL;
2561         bp->hwrm_short_cmd_req_addr = NULL;
2562         bp->hwrm_cmd_resp_dma_addr = 0;
2563         bp->hwrm_short_cmd_req_dma_addr = 0;
2564 }
2565
2566 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2567 {
2568         struct rte_pci_device *pdev = bp->pdev;
2569         char type[RTE_MEMZONE_NAMESIZE];
2570
2571         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2572                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2573         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2574         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2575         if (bp->hwrm_cmd_resp_addr == NULL)
2576                 return -ENOMEM;
2577         bp->hwrm_cmd_resp_dma_addr =
2578                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2579         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2580                 PMD_DRV_LOG(ERR,
2581                         "unable to map response address to physical memory\n");
2582                 return -ENOMEM;
2583         }
2584         rte_spinlock_init(&bp->hwrm_lock);
2585
2586         return 0;
2587 }
2588
2589 static int
2590 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2591 {
2592         struct bnxt_filter_info *filter;
2593         int rc = 0;
2594
2595         STAILQ_FOREACH(filter, &vnic->filter, next) {
2596                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2597                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2598                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2599                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2600                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2601                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2602                 bnxt_free_filter(bp, filter);
2603         }
2604         return rc;
2605 }
2606
2607 static int
2608 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2609 {
2610         struct bnxt_filter_info *filter;
2611         struct rte_flow *flow;
2612         int rc = 0;
2613
2614         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2615                 flow = STAILQ_FIRST(&vnic->flow_list);
2616                 filter = flow->filter;
2617                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2618                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2619                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2620                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2621                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2622                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2623
2624                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2625                 rte_free(flow);
2626         }
2627         return rc;
2628 }
2629
2630 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2631 {
2632         struct bnxt_filter_info *filter;
2633         int rc = 0;
2634
2635         STAILQ_FOREACH(filter, &vnic->filter, next) {
2636                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2637                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2638                                                      filter);
2639                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2640                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2641                                                          filter);
2642                 else
2643                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2644                                                      filter);
2645                 if (rc)
2646                         break;
2647         }
2648         return rc;
2649 }
2650
2651 static void
2652 bnxt_free_tunnel_ports(struct bnxt *bp)
2653 {
2654         if (bp->vxlan_port_cnt)
2655                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2656                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2657         bp->vxlan_port = 0;
2658         if (bp->geneve_port_cnt)
2659                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2660                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2661         bp->geneve_port = 0;
2662 }
2663
2664 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2665 {
2666         int i;
2667
2668         if (bp->vnic_info == NULL)
2669                 return;
2670
2671         /*
2672          * Cleanup VNICs in reverse order, to make sure the L2 filter
2673          * from vnic0 is last to be cleaned up.
2674          */
2675         for (i = bp->max_vnics - 1; i >= 0; i--) {
2676                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2677
2678                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2679                         continue;
2680
2681                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2682
2683                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2684
2685                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2686
2687                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2688
2689                 bnxt_hwrm_vnic_free(bp, vnic);
2690
2691                 rte_free(vnic->fw_grp_ids);
2692         }
2693         /* Ring resources */
2694         bnxt_free_all_hwrm_rings(bp);
2695         bnxt_free_all_hwrm_ring_grps(bp);
2696         bnxt_free_all_hwrm_stat_ctxs(bp);
2697         bnxt_free_tunnel_ports(bp);
2698 }
2699
2700 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2701 {
2702         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2703
2704         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2705                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2706
2707         switch (conf_link_speed) {
2708         case ETH_LINK_SPEED_10M_HD:
2709         case ETH_LINK_SPEED_100M_HD:
2710                 /* FALLTHROUGH */
2711                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2712         }
2713         return hw_link_duplex;
2714 }
2715
2716 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2717 {
2718         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2719 }
2720
2721 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2722 {
2723         uint16_t eth_link_speed = 0;
2724
2725         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2726                 return ETH_LINK_SPEED_AUTONEG;
2727
2728         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2729         case ETH_LINK_SPEED_100M:
2730         case ETH_LINK_SPEED_100M_HD:
2731                 /* FALLTHROUGH */
2732                 eth_link_speed =
2733                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2734                 break;
2735         case ETH_LINK_SPEED_1G:
2736                 eth_link_speed =
2737                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2738                 break;
2739         case ETH_LINK_SPEED_2_5G:
2740                 eth_link_speed =
2741                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2742                 break;
2743         case ETH_LINK_SPEED_10G:
2744                 eth_link_speed =
2745                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2746                 break;
2747         case ETH_LINK_SPEED_20G:
2748                 eth_link_speed =
2749                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2750                 break;
2751         case ETH_LINK_SPEED_25G:
2752                 eth_link_speed =
2753                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2754                 break;
2755         case ETH_LINK_SPEED_40G:
2756                 eth_link_speed =
2757                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2758                 break;
2759         case ETH_LINK_SPEED_50G:
2760                 eth_link_speed =
2761                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2762                 break;
2763         case ETH_LINK_SPEED_100G:
2764                 eth_link_speed =
2765                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2766                 break;
2767         case ETH_LINK_SPEED_200G:
2768                 eth_link_speed =
2769                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2770                 break;
2771         default:
2772                 PMD_DRV_LOG(ERR,
2773                         "Unsupported link speed %d; default to AUTO\n",
2774                         conf_link_speed);
2775                 break;
2776         }
2777         return eth_link_speed;
2778 }
2779
2780 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2781                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2782                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2783                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2784                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2785
2786 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2787 {
2788         uint32_t one_speed;
2789
2790         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2791                 return 0;
2792
2793         if (link_speed & ETH_LINK_SPEED_FIXED) {
2794                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2795
2796                 if (one_speed & (one_speed - 1)) {
2797                         PMD_DRV_LOG(ERR,
2798                                 "Invalid advertised speeds (%u) for port %u\n",
2799                                 link_speed, port_id);
2800                         return -EINVAL;
2801                 }
2802                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2803                         PMD_DRV_LOG(ERR,
2804                                 "Unsupported advertised speed (%u) for port %u\n",
2805                                 link_speed, port_id);
2806                         return -EINVAL;
2807                 }
2808         } else {
2809                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2810                         PMD_DRV_LOG(ERR,
2811                                 "Unsupported advertised speeds (%u) for port %u\n",
2812                                 link_speed, port_id);
2813                         return -EINVAL;
2814                 }
2815         }
2816         return 0;
2817 }
2818
2819 static uint16_t
2820 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2821 {
2822         uint16_t ret = 0;
2823
2824         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2825                 if (bp->link_info->support_speeds)
2826                         return bp->link_info->support_speeds;
2827                 link_speed = BNXT_SUPPORTED_SPEEDS;
2828         }
2829
2830         if (link_speed & ETH_LINK_SPEED_100M)
2831                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2832         if (link_speed & ETH_LINK_SPEED_100M_HD)
2833                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2834         if (link_speed & ETH_LINK_SPEED_1G)
2835                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2836         if (link_speed & ETH_LINK_SPEED_2_5G)
2837                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2838         if (link_speed & ETH_LINK_SPEED_10G)
2839                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2840         if (link_speed & ETH_LINK_SPEED_20G)
2841                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2842         if (link_speed & ETH_LINK_SPEED_25G)
2843                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2844         if (link_speed & ETH_LINK_SPEED_40G)
2845                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2846         if (link_speed & ETH_LINK_SPEED_50G)
2847                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2848         if (link_speed & ETH_LINK_SPEED_100G)
2849                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2850         if (link_speed & ETH_LINK_SPEED_200G)
2851                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2852         return ret;
2853 }
2854
2855 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2856 {
2857         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2858
2859         switch (hw_link_speed) {
2860         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2861                 eth_link_speed = ETH_SPEED_NUM_100M;
2862                 break;
2863         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2864                 eth_link_speed = ETH_SPEED_NUM_1G;
2865                 break;
2866         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2867                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2868                 break;
2869         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2870                 eth_link_speed = ETH_SPEED_NUM_10G;
2871                 break;
2872         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2873                 eth_link_speed = ETH_SPEED_NUM_20G;
2874                 break;
2875         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2876                 eth_link_speed = ETH_SPEED_NUM_25G;
2877                 break;
2878         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2879                 eth_link_speed = ETH_SPEED_NUM_40G;
2880                 break;
2881         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2882                 eth_link_speed = ETH_SPEED_NUM_50G;
2883                 break;
2884         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2885                 eth_link_speed = ETH_SPEED_NUM_100G;
2886                 break;
2887         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2888                 eth_link_speed = ETH_SPEED_NUM_200G;
2889                 break;
2890         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2891         default:
2892                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2893                         hw_link_speed);
2894                 break;
2895         }
2896         return eth_link_speed;
2897 }
2898
2899 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2900 {
2901         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2902
2903         switch (hw_link_duplex) {
2904         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2905         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2906                 /* FALLTHROUGH */
2907                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2908                 break;
2909         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2910                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2911                 break;
2912         default:
2913                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2914                         hw_link_duplex);
2915                 break;
2916         }
2917         return eth_link_duplex;
2918 }
2919
2920 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2921 {
2922         int rc = 0;
2923         struct bnxt_link_info *link_info = bp->link_info;
2924
2925         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2926         if (rc) {
2927                 PMD_DRV_LOG(ERR,
2928                         "Get link config failed with rc %d\n", rc);
2929                 goto exit;
2930         }
2931         if (link_info->link_speed)
2932                 link->link_speed =
2933                         bnxt_parse_hw_link_speed(link_info->link_speed);
2934         else
2935                 link->link_speed = ETH_SPEED_NUM_NONE;
2936         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2937         link->link_status = link_info->link_up;
2938         link->link_autoneg = link_info->auto_mode ==
2939                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2940                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2941 exit:
2942         return rc;
2943 }
2944
2945 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2946 {
2947         int rc = 0;
2948         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2949         struct bnxt_link_info link_req;
2950         uint16_t speed, autoneg;
2951
2952         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2953                 return 0;
2954
2955         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2956                         bp->eth_dev->data->port_id);
2957         if (rc)
2958                 goto error;
2959
2960         memset(&link_req, 0, sizeof(link_req));
2961         link_req.link_up = link_up;
2962         if (!link_up)
2963                 goto port_phy_cfg;
2964
2965         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2966         if (BNXT_CHIP_THOR(bp) &&
2967             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2968                 /* 40G is not supported as part of media auto detect.
2969                  * The speed should be forced and autoneg disabled
2970                  * to configure 40G speed.
2971                  */
2972                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2973                 autoneg = 0;
2974         }
2975
2976         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2977         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2978         /* Autoneg can be done only when the FW allows.
2979          * When user configures fixed speed of 40G and later changes to
2980          * any other speed, auto_link_speed/force_link_speed is still set
2981          * to 40G until link comes up at new speed.
2982          */
2983         if (autoneg == 1 &&
2984             !(!BNXT_CHIP_THOR(bp) &&
2985               (bp->link_info->auto_link_speed ||
2986                bp->link_info->force_link_speed))) {
2987                 link_req.phy_flags |=
2988                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2989                 link_req.auto_link_speed_mask =
2990                         bnxt_parse_eth_link_speed_mask(bp,
2991                                                        dev_conf->link_speeds);
2992         } else {
2993                 if (bp->link_info->phy_type ==
2994                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2995                     bp->link_info->phy_type ==
2996                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2997                     bp->link_info->media_type ==
2998                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2999                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3000                         return -EINVAL;
3001                 }
3002
3003                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3004                 /* If user wants a particular speed try that first. */
3005                 if (speed)
3006                         link_req.link_speed = speed;
3007                 else if (bp->link_info->force_link_speed)
3008                         link_req.link_speed = bp->link_info->force_link_speed;
3009                 else
3010                         link_req.link_speed = bp->link_info->auto_link_speed;
3011         }
3012         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3013         link_req.auto_pause = bp->link_info->auto_pause;
3014         link_req.force_pause = bp->link_info->force_pause;
3015
3016 port_phy_cfg:
3017         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3018         if (rc) {
3019                 PMD_DRV_LOG(ERR,
3020                         "Set link config failed with rc %d\n", rc);
3021         }
3022
3023 error:
3024         return rc;
3025 }
3026
3027 /* JIRA 22088 */
3028 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3029 {
3030         struct hwrm_func_qcfg_input req = {0};
3031         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3032         uint16_t flags;
3033         int rc = 0;
3034         bp->func_svif = BNXT_SVIF_INVALID;
3035         uint16_t svif_info;
3036
3037         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3038         req.fid = rte_cpu_to_le_16(0xffff);
3039
3040         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3041
3042         HWRM_CHECK_RESULT();
3043
3044         /* Hard Coded.. 0xfff VLAN ID mask */
3045         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3046
3047         svif_info = rte_le_to_cpu_16(resp->svif_info);
3048         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3049                 bp->func_svif = svif_info &
3050                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3051
3052         flags = rte_le_to_cpu_16(resp->flags);
3053         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3054                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3055
3056         if (BNXT_VF(bp) &&
3057             !BNXT_VF_IS_TRUSTED(bp) &&
3058             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3059                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3060                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3061         } else if (BNXT_VF(bp) &&
3062                    BNXT_VF_IS_TRUSTED(bp) &&
3063                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3064                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3065                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3066         }
3067
3068         if (mtu)
3069                 *mtu = rte_le_to_cpu_16(resp->mtu);
3070
3071         switch (resp->port_partition_type) {
3072         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3073         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3074         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3075                 /* FALLTHROUGH */
3076                 bp->flags |= BNXT_FLAG_NPAR_PF;
3077                 break;
3078         default:
3079                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3080                 break;
3081         }
3082
3083         HWRM_UNLOCK();
3084
3085         return rc;
3086 }
3087
3088 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3089 {
3090         struct hwrm_port_mac_qcfg_input req = {0};
3091         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3092         uint16_t port_svif_info;
3093         int rc;
3094
3095         bp->port_svif = BNXT_SVIF_INVALID;
3096
3097         if (!BNXT_PF(bp))
3098                 return 0;
3099
3100         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3101
3102         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3103
3104         HWRM_CHECK_RESULT();
3105
3106         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3107         if (port_svif_info &
3108             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3109                 bp->port_svif = port_svif_info &
3110                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3111
3112         HWRM_UNLOCK();
3113
3114         return 0;
3115 }
3116
3117 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3118                                    struct hwrm_func_qcaps_output *qcaps)
3119 {
3120         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3121         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3122                sizeof(qcaps->mac_address));
3123         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3124         qcaps->max_rx_rings = fcfg->num_rx_rings;
3125         qcaps->max_tx_rings = fcfg->num_tx_rings;
3126         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3127         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3128         qcaps->max_vfs = 0;
3129         qcaps->first_vf_id = 0;
3130         qcaps->max_vnics = fcfg->num_vnics;
3131         qcaps->max_decap_records = 0;
3132         qcaps->max_encap_records = 0;
3133         qcaps->max_tx_wm_flows = 0;
3134         qcaps->max_tx_em_flows = 0;
3135         qcaps->max_rx_wm_flows = 0;
3136         qcaps->max_rx_em_flows = 0;
3137         qcaps->max_flow_id = 0;
3138         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3139         qcaps->max_sp_tx_rings = 0;
3140         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3141 }
3142
3143 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3144 {
3145         struct hwrm_func_cfg_input req = {0};
3146         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3147         uint32_t enables;
3148         int rc;
3149
3150         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3151                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3152                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3153                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3154                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3155                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3156                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3157                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3158                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3159
3160         if (BNXT_HAS_RING_GRPS(bp)) {
3161                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3162                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3163         } else if (BNXT_HAS_NQ(bp)) {
3164                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3165                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3166         }
3167
3168         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3169         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3170         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3171         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3172         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3173         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3174         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3175         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3176         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3177         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3178         req.fid = rte_cpu_to_le_16(0xffff);
3179         req.enables = rte_cpu_to_le_32(enables);
3180
3181         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3182
3183         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3184
3185         HWRM_CHECK_RESULT();
3186         HWRM_UNLOCK();
3187
3188         return rc;
3189 }
3190
3191 static void populate_vf_func_cfg_req(struct bnxt *bp,
3192                                      struct hwrm_func_cfg_input *req,
3193                                      int num_vfs)
3194 {
3195         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3196                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3197                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3198                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3199                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3200                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3201                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3202                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3203                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3204                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3205
3206         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3207                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3208                                     BNXT_NUM_VLANS);
3209         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3210         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3211                                                 (num_vfs + 1));
3212         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3213         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3214                                                (num_vfs + 1));
3215         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3216         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3217         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3218         /* TODO: For now, do not support VMDq/RFS on VFs. */
3219         req->num_vnics = rte_cpu_to_le_16(1);
3220         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3221                                                  (num_vfs + 1));
3222 }
3223
3224 static void add_random_mac_if_needed(struct bnxt *bp,
3225                                      struct hwrm_func_cfg_input *cfg_req,
3226                                      int vf)
3227 {
3228         struct rte_ether_addr mac;
3229
3230         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3231                 return;
3232
3233         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3234                 cfg_req->enables |=
3235                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3236                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3237                 bp->pf->vf_info[vf].random_mac = true;
3238         } else {
3239                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3240                         RTE_ETHER_ADDR_LEN);
3241         }
3242 }
3243
3244 static int reserve_resources_from_vf(struct bnxt *bp,
3245                                      struct hwrm_func_cfg_input *cfg_req,
3246                                      int vf)
3247 {
3248         struct hwrm_func_qcaps_input req = {0};
3249         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3250         int rc;
3251
3252         /* Get the actual allocated values now */
3253         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3254         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3255         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3256
3257         if (rc) {
3258                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3259                 copy_func_cfg_to_qcaps(cfg_req, resp);
3260         } else if (resp->error_code) {
3261                 rc = rte_le_to_cpu_16(resp->error_code);
3262                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3263                 copy_func_cfg_to_qcaps(cfg_req, resp);
3264         }
3265
3266         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3267         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3268         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3269         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3270         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3271         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3272         /*
3273          * TODO: While not supporting VMDq with VFs, max_vnics is always
3274          * forced to 1 in this case
3275          */
3276         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3277         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3278
3279         HWRM_UNLOCK();
3280
3281         return 0;
3282 }
3283
3284 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3285 {
3286         struct hwrm_func_qcfg_input req = {0};
3287         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3288         int rc;
3289
3290         /* Check for zero MAC address */
3291         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3292         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3293         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3294         HWRM_CHECK_RESULT();
3295         rc = rte_le_to_cpu_16(resp->vlan);
3296
3297         HWRM_UNLOCK();
3298
3299         return rc;
3300 }
3301
3302 static int update_pf_resource_max(struct bnxt *bp)
3303 {
3304         struct hwrm_func_qcfg_input req = {0};
3305         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3306         int rc;
3307
3308         /* And copy the allocated numbers into the pf struct */
3309         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3310         req.fid = rte_cpu_to_le_16(0xffff);
3311         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3312         HWRM_CHECK_RESULT();
3313
3314         /* Only TX ring value reflects actual allocation? TODO */
3315         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3316         bp->pf->evb_mode = resp->evb_mode;
3317
3318         HWRM_UNLOCK();
3319
3320         return rc;
3321 }
3322
3323 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3324 {
3325         int rc;
3326
3327         if (!BNXT_PF(bp)) {
3328                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3329                 return -EINVAL;
3330         }
3331
3332         rc = bnxt_hwrm_func_qcaps(bp);
3333         if (rc)
3334                 return rc;
3335
3336         bp->pf->func_cfg_flags &=
3337                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3338                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3339         bp->pf->func_cfg_flags |=
3340                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3341         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3342         rc = __bnxt_hwrm_func_qcaps(bp);
3343         return rc;
3344 }
3345
3346 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3347 {
3348         struct hwrm_func_cfg_input req = {0};
3349         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3350         int i;
3351         size_t sz;
3352         int rc = 0;
3353         size_t req_buf_sz;
3354
3355         if (!BNXT_PF(bp)) {
3356                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3357                 return -EINVAL;
3358         }
3359
3360         rc = bnxt_hwrm_func_qcaps(bp);
3361
3362         if (rc)
3363                 return rc;
3364
3365         bp->pf->active_vfs = num_vfs;
3366
3367         /*
3368          * First, configure the PF to only use one TX ring.  This ensures that
3369          * there are enough rings for all VFs.
3370          *
3371          * If we don't do this, when we call func_alloc() later, we will lock
3372          * extra rings to the PF that won't be available during func_cfg() of
3373          * the VFs.
3374          *
3375          * This has been fixed with firmware versions above 20.6.54
3376          */
3377         bp->pf->func_cfg_flags &=
3378                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3379                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3380         bp->pf->func_cfg_flags |=
3381                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3382         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3383         if (rc)
3384                 return rc;
3385
3386         /*
3387          * Now, create and register a buffer to hold forwarded VF requests
3388          */
3389         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3390         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3391                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3392         if (bp->pf->vf_req_buf == NULL) {
3393                 rc = -ENOMEM;
3394                 goto error_free;
3395         }
3396         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3397                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3398         for (i = 0; i < num_vfs; i++)
3399                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3400                                         (i * HWRM_MAX_REQ_LEN);
3401
3402         rc = bnxt_hwrm_func_buf_rgtr(bp);
3403         if (rc)
3404                 goto error_free;
3405
3406         populate_vf_func_cfg_req(bp, &req, num_vfs);
3407
3408         bp->pf->active_vfs = 0;
3409         for (i = 0; i < num_vfs; i++) {
3410                 add_random_mac_if_needed(bp, &req, i);
3411
3412                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3413                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3414                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3415                 rc = bnxt_hwrm_send_message(bp,
3416                                             &req,
3417                                             sizeof(req),
3418                                             BNXT_USE_CHIMP_MB);
3419
3420                 /* Clear enable flag for next pass */
3421                 req.enables &= ~rte_cpu_to_le_32(
3422                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3423
3424                 if (rc || resp->error_code) {
3425                         PMD_DRV_LOG(ERR,
3426                                 "Failed to initizlie VF %d\n", i);
3427                         PMD_DRV_LOG(ERR,
3428                                 "Not all VFs available. (%d, %d)\n",
3429                                 rc, resp->error_code);
3430                         HWRM_UNLOCK();
3431                         break;
3432                 }
3433
3434                 HWRM_UNLOCK();
3435
3436                 reserve_resources_from_vf(bp, &req, i);
3437                 bp->pf->active_vfs++;
3438                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3439         }
3440
3441         /*
3442          * Now configure the PF to use "the rest" of the resources
3443          * We're using STD_TX_RING_MODE here though which will limit the TX
3444          * rings.  This will allow QoS to function properly.  Not setting this
3445          * will cause PF rings to break bandwidth settings.
3446          */
3447         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3448         if (rc)
3449                 goto error_free;
3450
3451         rc = update_pf_resource_max(bp);
3452         if (rc)
3453                 goto error_free;
3454
3455         return rc;
3456
3457 error_free:
3458         bnxt_hwrm_func_buf_unrgtr(bp);
3459         return rc;
3460 }
3461
3462 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3463 {
3464         struct hwrm_func_cfg_input req = {0};
3465         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3466         int rc;
3467
3468         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3469
3470         req.fid = rte_cpu_to_le_16(0xffff);
3471         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3472         req.evb_mode = bp->pf->evb_mode;
3473
3474         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3475         HWRM_CHECK_RESULT();
3476         HWRM_UNLOCK();
3477
3478         return rc;
3479 }
3480
3481 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3482                                 uint8_t tunnel_type)
3483 {
3484         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3485         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3486         int rc = 0;
3487
3488         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3489         req.tunnel_type = tunnel_type;
3490         req.tunnel_dst_port_val = port;
3491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3492         HWRM_CHECK_RESULT();
3493
3494         switch (tunnel_type) {
3495         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3496                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3497                 bp->vxlan_port = port;
3498                 break;
3499         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3500                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3501                 bp->geneve_port = port;
3502                 break;
3503         default:
3504                 break;
3505         }
3506
3507         HWRM_UNLOCK();
3508
3509         return rc;
3510 }
3511
3512 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3513                                 uint8_t tunnel_type)
3514 {
3515         struct hwrm_tunnel_dst_port_free_input req = {0};
3516         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3517         int rc = 0;
3518
3519         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3520
3521         req.tunnel_type = tunnel_type;
3522         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3523         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3524
3525         HWRM_CHECK_RESULT();
3526         HWRM_UNLOCK();
3527
3528         return rc;
3529 }
3530
3531 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3532                                         uint32_t flags)
3533 {
3534         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3535         struct hwrm_func_cfg_input req = {0};
3536         int rc;
3537
3538         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3539
3540         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3541         req.flags = rte_cpu_to_le_32(flags);
3542         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3543
3544         HWRM_CHECK_RESULT();
3545         HWRM_UNLOCK();
3546
3547         return rc;
3548 }
3549
3550 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3551 {
3552         uint32_t *flag = flagp;
3553
3554         vnic->flags = *flag;
3555 }
3556
3557 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3558 {
3559         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3560 }
3561
3562 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3563 {
3564         int rc = 0;
3565         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3566         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3567
3568         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3569
3570         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3571         req.req_buf_page_size = rte_cpu_to_le_16(
3572                          page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3573         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3574         req.req_buf_page_addr0 =
3575                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3576         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3577                 PMD_DRV_LOG(ERR,
3578                         "unable to map buffer address to physical memory\n");
3579                 return -ENOMEM;
3580         }
3581
3582         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3583
3584         HWRM_CHECK_RESULT();
3585         HWRM_UNLOCK();
3586
3587         return rc;
3588 }
3589
3590 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3591 {
3592         int rc = 0;
3593         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3594         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3595
3596         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3597                 return 0;
3598
3599         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3600
3601         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3602
3603         HWRM_CHECK_RESULT();
3604         HWRM_UNLOCK();
3605
3606         return rc;
3607 }
3608
3609 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3610 {
3611         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3612         struct hwrm_func_cfg_input req = {0};
3613         int rc;
3614
3615         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3616
3617         req.fid = rte_cpu_to_le_16(0xffff);
3618         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3619         req.enables = rte_cpu_to_le_32(
3620                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3621         req.async_event_cr = rte_cpu_to_le_16(
3622                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3623         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3624
3625         HWRM_CHECK_RESULT();
3626         HWRM_UNLOCK();
3627
3628         return rc;
3629 }
3630
3631 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3632 {
3633         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3634         struct hwrm_func_vf_cfg_input req = {0};
3635         int rc;
3636
3637         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3638
3639         req.enables = rte_cpu_to_le_32(
3640                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3641         req.async_event_cr = rte_cpu_to_le_16(
3642                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3643         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3644
3645         HWRM_CHECK_RESULT();
3646         HWRM_UNLOCK();
3647
3648         return rc;
3649 }
3650
3651 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3652 {
3653         struct hwrm_func_cfg_input req = {0};
3654         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3655         uint16_t dflt_vlan, fid;
3656         uint32_t func_cfg_flags;
3657         int rc = 0;
3658
3659         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3660
3661         if (is_vf) {
3662                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3663                 fid = bp->pf->vf_info[vf].fid;
3664                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3665         } else {
3666                 fid = rte_cpu_to_le_16(0xffff);
3667                 func_cfg_flags = bp->pf->func_cfg_flags;
3668                 dflt_vlan = bp->vlan;
3669         }
3670
3671         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3672         req.fid = rte_cpu_to_le_16(fid);
3673         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3674         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3675
3676         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3677
3678         HWRM_CHECK_RESULT();
3679         HWRM_UNLOCK();
3680
3681         return rc;
3682 }
3683
3684 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3685                         uint16_t max_bw, uint16_t enables)
3686 {
3687         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3688         struct hwrm_func_cfg_input req = {0};
3689         int rc;
3690
3691         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3692
3693         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3694         req.enables |= rte_cpu_to_le_32(enables);
3695         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3696         req.max_bw = rte_cpu_to_le_32(max_bw);
3697         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3698
3699         HWRM_CHECK_RESULT();
3700         HWRM_UNLOCK();
3701
3702         return rc;
3703 }
3704
3705 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3706 {
3707         struct hwrm_func_cfg_input req = {0};
3708         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3709         int rc = 0;
3710
3711         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3712
3713         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3714         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3715         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3716         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3717
3718         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3719
3720         HWRM_CHECK_RESULT();
3721         HWRM_UNLOCK();
3722
3723         return rc;
3724 }
3725
3726 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3727 {
3728         int rc;
3729
3730         if (BNXT_PF(bp))
3731                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3732         else
3733                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3734
3735         return rc;
3736 }
3737
3738 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3739                               void *encaped, size_t ec_size)
3740 {
3741         int rc = 0;
3742         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3743         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3744
3745         if (ec_size > sizeof(req.encap_request))
3746                 return -1;
3747
3748         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3749
3750         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3751         memcpy(req.encap_request, encaped, ec_size);
3752
3753         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3754
3755         HWRM_CHECK_RESULT();
3756         HWRM_UNLOCK();
3757
3758         return rc;
3759 }
3760
3761 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3762                                        struct rte_ether_addr *mac)
3763 {
3764         struct hwrm_func_qcfg_input req = {0};
3765         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3766         int rc;
3767
3768         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3769
3770         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3771         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3772
3773         HWRM_CHECK_RESULT();
3774
3775         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3776
3777         HWRM_UNLOCK();
3778
3779         return rc;
3780 }
3781
3782 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3783                             void *encaped, size_t ec_size)
3784 {
3785         int rc = 0;
3786         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3787         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3788
3789         if (ec_size > sizeof(req.encap_request))
3790                 return -1;
3791
3792         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3793
3794         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3795         memcpy(req.encap_request, encaped, ec_size);
3796
3797         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3798
3799         HWRM_CHECK_RESULT();
3800         HWRM_UNLOCK();
3801
3802         return rc;
3803 }
3804
3805 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3806                          struct rte_eth_stats *stats, uint8_t rx)
3807 {
3808         int rc = 0;
3809         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3810         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3811
3812         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3813
3814         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3815
3816         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3817
3818         HWRM_CHECK_RESULT();
3819
3820         if (rx) {
3821                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3822                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3823                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3824                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3825                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3826                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3827                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3828                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3829         } else {
3830                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3831                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3832                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3833                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3834                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3835                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3836         }
3837
3838         HWRM_UNLOCK();
3839
3840         return rc;
3841 }
3842
3843 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3844 {
3845         struct hwrm_port_qstats_input req = {0};
3846         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3847         struct bnxt_pf_info *pf = bp->pf;
3848         int rc;
3849
3850         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3851
3852         req.port_id = rte_cpu_to_le_16(pf->port_id);
3853         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3854         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3855         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3856
3857         HWRM_CHECK_RESULT();
3858         HWRM_UNLOCK();
3859
3860         return rc;
3861 }
3862
3863 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3864 {
3865         struct hwrm_port_clr_stats_input req = {0};
3866         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3867         struct bnxt_pf_info *pf = bp->pf;
3868         int rc;
3869
3870         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3871         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3872             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3873                 return 0;
3874
3875         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3876
3877         req.port_id = rte_cpu_to_le_16(pf->port_id);
3878         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3879
3880         HWRM_CHECK_RESULT();
3881         HWRM_UNLOCK();
3882
3883         return rc;
3884 }
3885
3886 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3887 {
3888         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3889         struct hwrm_port_led_qcaps_input req = {0};
3890         int rc;
3891
3892         if (BNXT_VF(bp))
3893                 return 0;
3894
3895         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3896         req.port_id = bp->pf->port_id;
3897         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3898
3899         HWRM_CHECK_RESULT();
3900
3901         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3902                 unsigned int i;
3903
3904                 bp->leds->num_leds = resp->num_leds;
3905                 memcpy(bp->leds, &resp->led0_id,
3906                         sizeof(bp->leds[0]) * bp->leds->num_leds);
3907                 for (i = 0; i < bp->leds->num_leds; i++) {
3908                         struct bnxt_led_info *led = &bp->leds[i];
3909
3910                         uint16_t caps = led->led_state_caps;
3911
3912                         if (!led->led_group_id ||
3913                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3914                                 bp->leds->num_leds = 0;
3915                                 break;
3916                         }
3917                 }
3918         }
3919
3920         HWRM_UNLOCK();
3921
3922         return rc;
3923 }
3924
3925 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3926 {
3927         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3928         struct hwrm_port_led_cfg_input req = {0};
3929         struct bnxt_led_cfg *led_cfg;
3930         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3931         uint16_t duration = 0;
3932         int rc, i;
3933
3934         if (!bp->leds->num_leds || BNXT_VF(bp))
3935                 return -EOPNOTSUPP;
3936
3937         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3938
3939         if (led_on) {
3940                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3941                 duration = rte_cpu_to_le_16(500);
3942         }
3943         req.port_id = bp->pf->port_id;
3944         req.num_leds = bp->leds->num_leds;
3945         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3946         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
3947                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3948                 led_cfg->led_id = bp->leds[i].led_id;
3949                 led_cfg->led_state = led_state;
3950                 led_cfg->led_blink_on = duration;
3951                 led_cfg->led_blink_off = duration;
3952                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3953         }
3954
3955         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3956
3957         HWRM_CHECK_RESULT();
3958         HWRM_UNLOCK();
3959
3960         return rc;
3961 }
3962
3963 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3964                                uint32_t *length)
3965 {
3966         int rc;
3967         struct hwrm_nvm_get_dir_info_input req = {0};
3968         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3969
3970         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3971
3972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3973
3974         HWRM_CHECK_RESULT();
3975
3976         *entries = rte_le_to_cpu_32(resp->entries);
3977         *length = rte_le_to_cpu_32(resp->entry_length);
3978
3979         HWRM_UNLOCK();
3980         return rc;
3981 }
3982
3983 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3984 {
3985         int rc;
3986         uint32_t dir_entries;
3987         uint32_t entry_length;
3988         uint8_t *buf;
3989         size_t buflen;
3990         rte_iova_t dma_handle;
3991         struct hwrm_nvm_get_dir_entries_input req = {0};
3992         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3993
3994         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3995         if (rc != 0)
3996                 return rc;
3997
3998         *data++ = dir_entries;
3999         *data++ = entry_length;
4000         len -= 2;
4001         memset(data, 0xff, len);
4002
4003         buflen = dir_entries * entry_length;
4004         buf = rte_malloc("nvm_dir", buflen, 0);
4005         if (buf == NULL)
4006                 return -ENOMEM;
4007         dma_handle = rte_malloc_virt2iova(buf);
4008         if (dma_handle == RTE_BAD_IOVA) {
4009                 PMD_DRV_LOG(ERR,
4010                         "unable to map response address to physical memory\n");
4011                 return -ENOMEM;
4012         }
4013         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4014         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4015         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4016
4017         if (rc == 0)
4018                 memcpy(data, buf, len > buflen ? buflen : len);
4019
4020         rte_free(buf);
4021         HWRM_CHECK_RESULT();
4022         HWRM_UNLOCK();
4023
4024         return rc;
4025 }
4026
4027 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4028                              uint32_t offset, uint32_t length,
4029                              uint8_t *data)
4030 {
4031         int rc;
4032         uint8_t *buf;
4033         rte_iova_t dma_handle;
4034         struct hwrm_nvm_read_input req = {0};
4035         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4036
4037         buf = rte_malloc("nvm_item", length, 0);
4038         if (!buf)
4039                 return -ENOMEM;
4040
4041         dma_handle = rte_malloc_virt2iova(buf);
4042         if (dma_handle == RTE_BAD_IOVA) {
4043                 PMD_DRV_LOG(ERR,
4044                         "unable to map response address to physical memory\n");
4045                 return -ENOMEM;
4046         }
4047         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4048         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4049         req.dir_idx = rte_cpu_to_le_16(index);
4050         req.offset = rte_cpu_to_le_32(offset);
4051         req.len = rte_cpu_to_le_32(length);
4052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4053         if (rc == 0)
4054                 memcpy(data, buf, length);
4055
4056         rte_free(buf);
4057         HWRM_CHECK_RESULT();
4058         HWRM_UNLOCK();
4059
4060         return rc;
4061 }
4062
4063 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4064 {
4065         int rc;
4066         struct hwrm_nvm_erase_dir_entry_input req = {0};
4067         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4068
4069         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4070         req.dir_idx = rte_cpu_to_le_16(index);
4071         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4072         HWRM_CHECK_RESULT();
4073         HWRM_UNLOCK();
4074
4075         return rc;
4076 }
4077
4078
4079 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4080                           uint16_t dir_ordinal, uint16_t dir_ext,
4081                           uint16_t dir_attr, const uint8_t *data,
4082                           size_t data_len)
4083 {
4084         int rc;
4085         struct hwrm_nvm_write_input req = {0};
4086         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4087         rte_iova_t dma_handle;
4088         uint8_t *buf;
4089
4090         buf = rte_malloc("nvm_write", data_len, 0);
4091         if (!buf)
4092                 return -ENOMEM;
4093
4094         dma_handle = rte_malloc_virt2iova(buf);
4095         if (dma_handle == RTE_BAD_IOVA) {
4096                 PMD_DRV_LOG(ERR,
4097                         "unable to map response address to physical memory\n");
4098                 return -ENOMEM;
4099         }
4100         memcpy(buf, data, data_len);
4101
4102         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4103
4104         req.dir_type = rte_cpu_to_le_16(dir_type);
4105         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4106         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4107         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4108         req.dir_data_length = rte_cpu_to_le_32(data_len);
4109         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4110
4111         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4112
4113         rte_free(buf);
4114         HWRM_CHECK_RESULT();
4115         HWRM_UNLOCK();
4116
4117         return rc;
4118 }
4119
4120 static void
4121 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4122 {
4123         uint32_t *count = cbdata;
4124
4125         *count = *count + 1;
4126 }
4127
4128 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4129                                      struct bnxt_vnic_info *vnic __rte_unused)
4130 {
4131         return 0;
4132 }
4133
4134 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4135 {
4136         uint32_t count = 0;
4137
4138         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4139             &count, bnxt_vnic_count_hwrm_stub);
4140
4141         return count;
4142 }
4143
4144 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4145                                         uint16_t *vnic_ids)
4146 {
4147         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4148         struct hwrm_func_vf_vnic_ids_query_output *resp =
4149                                                 bp->hwrm_cmd_resp_addr;
4150         int rc;
4151
4152         /* First query all VNIC ids */
4153         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4154
4155         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4156         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4157         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4158
4159         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4160                 HWRM_UNLOCK();
4161                 PMD_DRV_LOG(ERR,
4162                 "unable to map VNIC ID table address to physical memory\n");
4163                 return -ENOMEM;
4164         }
4165         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4166         HWRM_CHECK_RESULT();
4167         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4168
4169         HWRM_UNLOCK();
4170
4171         return rc;
4172 }
4173
4174 /*
4175  * This function queries the VNIC IDs  for a specified VF. It then calls
4176  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4177  * Then it calls the hwrm_cb function to program this new vnic configuration.
4178  */
4179 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4180         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4181         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4182 {
4183         struct bnxt_vnic_info vnic;
4184         int rc = 0;
4185         int i, num_vnic_ids;
4186         uint16_t *vnic_ids;
4187         size_t vnic_id_sz;
4188         size_t sz;
4189
4190         /* First query all VNIC ids */
4191         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4192         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4193                         RTE_CACHE_LINE_SIZE);
4194         if (vnic_ids == NULL)
4195                 return -ENOMEM;
4196
4197         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4198                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4199
4200         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4201
4202         if (num_vnic_ids < 0)
4203                 return num_vnic_ids;
4204
4205         /* Retrieve VNIC, update bd_stall then update */
4206
4207         for (i = 0; i < num_vnic_ids; i++) {
4208                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4209                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4210                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4211                 if (rc)
4212                         break;
4213                 if (vnic.mru <= 4)      /* Indicates unallocated */
4214                         continue;
4215
4216                 vnic_cb(&vnic, cbdata);
4217
4218                 rc = hwrm_cb(bp, &vnic);
4219                 if (rc)
4220                         break;
4221         }
4222
4223         rte_free(vnic_ids);
4224
4225         return rc;
4226 }
4227
4228 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4229                                               bool on)
4230 {
4231         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4232         struct hwrm_func_cfg_input req = {0};
4233         int rc;
4234
4235         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4236
4237         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4238         req.enables |= rte_cpu_to_le_32(
4239                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4240         req.vlan_antispoof_mode = on ?
4241                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4242                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4243         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4244
4245         HWRM_CHECK_RESULT();
4246         HWRM_UNLOCK();
4247
4248         return rc;
4249 }
4250
4251 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4252 {
4253         struct bnxt_vnic_info vnic;
4254         uint16_t *vnic_ids;
4255         size_t vnic_id_sz;
4256         int num_vnic_ids, i;
4257         size_t sz;
4258         int rc;
4259
4260         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4261         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4262                         RTE_CACHE_LINE_SIZE);
4263         if (vnic_ids == NULL)
4264                 return -ENOMEM;
4265
4266         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4267                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4268
4269         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4270         if (rc <= 0)
4271                 goto exit;
4272         num_vnic_ids = rc;
4273
4274         /*
4275          * Loop through to find the default VNIC ID.
4276          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4277          * by sending the hwrm_func_qcfg command to the firmware.
4278          */
4279         for (i = 0; i < num_vnic_ids; i++) {
4280                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4281                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4282                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4283                                         bp->pf->first_vf_id + vf);
4284                 if (rc)
4285                         goto exit;
4286                 if (vnic.func_default) {
4287                         rte_free(vnic_ids);
4288                         return vnic.fw_vnic_id;
4289                 }
4290         }
4291         /* Could not find a default VNIC. */
4292         PMD_DRV_LOG(ERR, "No default VNIC\n");
4293 exit:
4294         rte_free(vnic_ids);
4295         return rc;
4296 }
4297
4298 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4299                          uint16_t dst_id,
4300                          struct bnxt_filter_info *filter)
4301 {
4302         int rc = 0;
4303         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4304         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4305         uint32_t enables = 0;
4306
4307         if (filter->fw_em_filter_id != UINT64_MAX)
4308                 bnxt_hwrm_clear_em_filter(bp, filter);
4309
4310         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4311
4312         req.flags = rte_cpu_to_le_32(filter->flags);
4313
4314         enables = filter->enables |
4315               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4316         req.dst_id = rte_cpu_to_le_16(dst_id);
4317
4318         if (filter->ip_addr_type) {
4319                 req.ip_addr_type = filter->ip_addr_type;
4320                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4321         }
4322         if (enables &
4323             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4324                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4325         if (enables &
4326             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4327                 memcpy(req.src_macaddr, filter->src_macaddr,
4328                        RTE_ETHER_ADDR_LEN);
4329         if (enables &
4330             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4331                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4332                        RTE_ETHER_ADDR_LEN);
4333         if (enables &
4334             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4335                 req.ovlan_vid = filter->l2_ovlan;
4336         if (enables &
4337             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4338                 req.ivlan_vid = filter->l2_ivlan;
4339         if (enables &
4340             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4341                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4342         if (enables &
4343             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4344                 req.ip_protocol = filter->ip_protocol;
4345         if (enables &
4346             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4347                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4348         if (enables &
4349             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4350                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4351         if (enables &
4352             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4353                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4354         if (enables &
4355             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4356                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4357         if (enables &
4358             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4359                 req.mirror_vnic_id = filter->mirror_vnic_id;
4360
4361         req.enables = rte_cpu_to_le_32(enables);
4362
4363         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4364
4365         HWRM_CHECK_RESULT();
4366
4367         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4368         HWRM_UNLOCK();
4369
4370         return rc;
4371 }
4372
4373 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4374 {
4375         int rc = 0;
4376         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4377         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4378
4379         if (filter->fw_em_filter_id == UINT64_MAX)
4380                 return 0;
4381
4382         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4383
4384         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4385
4386         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4387
4388         HWRM_CHECK_RESULT();
4389         HWRM_UNLOCK();
4390
4391         filter->fw_em_filter_id = UINT64_MAX;
4392         filter->fw_l2_filter_id = UINT64_MAX;
4393
4394         return 0;
4395 }
4396
4397 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4398                          uint16_t dst_id,
4399                          struct bnxt_filter_info *filter)
4400 {
4401         int rc = 0;
4402         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4403         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4404                                                 bp->hwrm_cmd_resp_addr;
4405         uint32_t enables = 0;
4406
4407         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4408                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4409
4410         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4411
4412         req.flags = rte_cpu_to_le_32(filter->flags);
4413
4414         enables = filter->enables |
4415               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4416         req.dst_id = rte_cpu_to_le_16(dst_id);
4417
4418         if (filter->ip_addr_type) {
4419                 req.ip_addr_type = filter->ip_addr_type;
4420                 enables |=
4421                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4422         }
4423         if (enables &
4424             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4425                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4426         if (enables &
4427             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4428                 memcpy(req.src_macaddr, filter->src_macaddr,
4429                        RTE_ETHER_ADDR_LEN);
4430         if (enables &
4431             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4432                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4433         if (enables &
4434             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4435                 req.ip_protocol = filter->ip_protocol;
4436         if (enables &
4437             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4438                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4439         if (enables &
4440             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4441                 req.src_ipaddr_mask[0] =
4442                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4443         if (enables &
4444             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4445                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4446         if (enables &
4447             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4448                 req.dst_ipaddr_mask[0] =
4449                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4450         if (enables &
4451             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4452                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4453         if (enables &
4454             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4455                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4456         if (enables &
4457             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4458                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4459         if (enables &
4460             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4461                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4462         if (enables &
4463             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4464                 req.mirror_vnic_id = filter->mirror_vnic_id;
4465
4466         req.enables = rte_cpu_to_le_32(enables);
4467
4468         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4469
4470         HWRM_CHECK_RESULT();
4471
4472         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4473         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4474         HWRM_UNLOCK();
4475
4476         return rc;
4477 }
4478
4479 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4480                                 struct bnxt_filter_info *filter)
4481 {
4482         int rc = 0;
4483         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4484         struct hwrm_cfa_ntuple_filter_free_output *resp =
4485                                                 bp->hwrm_cmd_resp_addr;
4486
4487         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4488                 return 0;
4489
4490         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4491
4492         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4493
4494         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4495
4496         HWRM_CHECK_RESULT();
4497         HWRM_UNLOCK();
4498
4499         filter->fw_ntuple_filter_id = UINT64_MAX;
4500
4501         return 0;
4502 }
4503
4504 static int
4505 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4506 {
4507         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4508         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4509         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4510         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4511         uint16_t *ring_tbl = vnic->rss_table;
4512         int nr_ctxs = vnic->num_lb_ctxts;
4513         int max_rings = bp->rx_nr_rings;
4514         int i, j, k, cnt;
4515         int rc = 0;
4516
4517         for (i = 0, k = 0; i < nr_ctxs; i++) {
4518                 struct bnxt_rx_ring_info *rxr;
4519                 struct bnxt_cp_ring_info *cpr;
4520
4521                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4522
4523                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4524                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4525                 req.hash_mode_flags = vnic->hash_mode;
4526
4527                 req.ring_grp_tbl_addr =
4528                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4529                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4530                                      2 * sizeof(*ring_tbl));
4531                 req.hash_key_tbl_addr =
4532                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4533
4534                 req.ring_table_pair_index = i;
4535                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4536
4537                 for (j = 0; j < 64; j++) {
4538                         uint16_t ring_id;
4539
4540                         /* Find next active ring. */
4541                         for (cnt = 0; cnt < max_rings; cnt++) {
4542                                 if (rx_queue_state[k] !=
4543                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4544                                         break;
4545                                 if (++k == max_rings)
4546                                         k = 0;
4547                         }
4548
4549                         /* Return if no rings are active. */
4550                         if (cnt == max_rings) {
4551                                 HWRM_UNLOCK();
4552                                 return 0;
4553                         }
4554
4555                         /* Add rx/cp ring pair to RSS table. */
4556                         rxr = rxqs[k]->rx_ring;
4557                         cpr = rxqs[k]->cp_ring;
4558
4559                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4560                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4561                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4562                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4563
4564                         if (++k == max_rings)
4565                                 k = 0;
4566                 }
4567                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4568                                             BNXT_USE_CHIMP_MB);
4569
4570                 HWRM_CHECK_RESULT();
4571                 HWRM_UNLOCK();
4572         }
4573
4574         return rc;
4575 }
4576
4577 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4578 {
4579         unsigned int rss_idx, fw_idx, i;
4580
4581         if (!(vnic->rss_table && vnic->hash_type))
4582                 return 0;
4583
4584         if (BNXT_CHIP_THOR(bp))
4585                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4586
4587         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4588                 return 0;
4589
4590         if (vnic->rss_table && vnic->hash_type) {
4591                 /*
4592                  * Fill the RSS hash & redirection table with
4593                  * ring group ids for all VNICs
4594                  */
4595                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4596                         rss_idx++, fw_idx++) {
4597                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4598                                 fw_idx %= bp->rx_cp_nr_rings;
4599                                 if (vnic->fw_grp_ids[fw_idx] !=
4600                                     INVALID_HW_RING_ID)
4601                                         break;
4602                                 fw_idx++;
4603                         }
4604                         if (i == bp->rx_cp_nr_rings)
4605                                 return 0;
4606                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4607                 }
4608                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4609         }
4610
4611         return 0;
4612 }
4613
4614 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4615         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4616 {
4617         uint16_t flags;
4618
4619         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4620
4621         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4622         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4623
4624         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4625         req->num_cmpl_dma_aggr_during_int =
4626                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4627
4628         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4629
4630         /* min timer set to 1/2 of interrupt timer */
4631         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4632
4633         /* buf timer set to 1/4 of interrupt timer */
4634         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4635
4636         req->cmpl_aggr_dma_tmr_during_int =
4637                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4638
4639         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4640                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4641         req->flags = rte_cpu_to_le_16(flags);
4642 }
4643
4644 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4645                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4646 {
4647         struct hwrm_ring_aggint_qcaps_input req = {0};
4648         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4649         uint32_t enables;
4650         uint16_t flags;
4651         int rc;
4652
4653         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4654         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4655         HWRM_CHECK_RESULT();
4656
4657         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4658         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4659
4660         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4661                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4662         agg_req->flags = rte_cpu_to_le_16(flags);
4663         enables =
4664          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4665          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4666         agg_req->enables = rte_cpu_to_le_32(enables);
4667
4668         HWRM_UNLOCK();
4669         return rc;
4670 }
4671
4672 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4673                         struct bnxt_coal *coal, uint16_t ring_id)
4674 {
4675         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4676         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4677                                                 bp->hwrm_cmd_resp_addr;
4678         int rc;
4679
4680         /* Set ring coalesce parameters only for 100G NICs */
4681         if (BNXT_CHIP_THOR(bp)) {
4682                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4683                         return -1;
4684         } else if (bnxt_stratus_device(bp)) {
4685                 bnxt_hwrm_set_coal_params(coal, &req);
4686         } else {
4687                 return 0;
4688         }
4689
4690         HWRM_PREP(&req,
4691                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4692                   BNXT_USE_CHIMP_MB);
4693         req.ring_id = rte_cpu_to_le_16(ring_id);
4694         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4695         HWRM_CHECK_RESULT();
4696         HWRM_UNLOCK();
4697         return 0;
4698 }
4699
4700 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4701 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4702 {
4703         struct hwrm_func_backing_store_qcaps_input req = {0};
4704         struct hwrm_func_backing_store_qcaps_output *resp =
4705                 bp->hwrm_cmd_resp_addr;
4706         struct bnxt_ctx_pg_info *ctx_pg;
4707         struct bnxt_ctx_mem_info *ctx;
4708         int total_alloc_len;
4709         int rc, i, tqm_rings;
4710
4711         if (!BNXT_CHIP_THOR(bp) ||
4712             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4713             BNXT_VF(bp) ||
4714             bp->ctx)
4715                 return 0;
4716
4717         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4718         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4719         HWRM_CHECK_RESULT_SILENT();
4720
4721         total_alloc_len = sizeof(*ctx);
4722         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4723                           RTE_CACHE_LINE_SIZE);
4724         if (!ctx) {
4725                 rc = -ENOMEM;
4726                 goto ctx_err;
4727         }
4728
4729         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4730         ctx->qp_min_qp1_entries =
4731                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4732         ctx->qp_max_l2_entries =
4733                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4734         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4735         ctx->srq_max_l2_entries =
4736                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4737         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4738         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4739         ctx->cq_max_l2_entries =
4740                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4741         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4742         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4743         ctx->vnic_max_vnic_entries =
4744                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4745         ctx->vnic_max_ring_table_entries =
4746                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4747         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4748         ctx->stat_max_entries =
4749                 rte_le_to_cpu_32(resp->stat_max_entries);
4750         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4751         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4752         ctx->tqm_min_entries_per_ring =
4753                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4754         ctx->tqm_max_entries_per_ring =
4755                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4756         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4757         if (!ctx->tqm_entries_multiple)
4758                 ctx->tqm_entries_multiple = 1;
4759         ctx->mrav_max_entries =
4760                 rte_le_to_cpu_32(resp->mrav_max_entries);
4761         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4762         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4763         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4764         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4765
4766         if (!ctx->tqm_fp_rings_count)
4767                 ctx->tqm_fp_rings_count = bp->max_q;
4768
4769         tqm_rings = ctx->tqm_fp_rings_count + 1;
4770
4771         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4772                             sizeof(*ctx_pg) * tqm_rings,
4773                             RTE_CACHE_LINE_SIZE);
4774         if (!ctx_pg) {
4775                 rc = -ENOMEM;
4776                 goto ctx_err;
4777         }
4778         for (i = 0; i < tqm_rings; i++, ctx_pg++)
4779                 ctx->tqm_mem[i] = ctx_pg;
4780
4781         bp->ctx = ctx;
4782 ctx_err:
4783         HWRM_UNLOCK();
4784         return rc;
4785 }
4786
4787 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4788 {
4789         struct hwrm_func_backing_store_cfg_input req = {0};
4790         struct hwrm_func_backing_store_cfg_output *resp =
4791                 bp->hwrm_cmd_resp_addr;
4792         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4793         struct bnxt_ctx_pg_info *ctx_pg;
4794         uint32_t *num_entries;
4795         uint64_t *pg_dir;
4796         uint8_t *pg_attr;
4797         uint32_t ena;
4798         int i, rc;
4799
4800         if (!ctx)
4801                 return 0;
4802
4803         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4804         req.enables = rte_cpu_to_le_32(enables);
4805
4806         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4807                 ctx_pg = &ctx->qp_mem;
4808                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4809                 req.qp_num_qp1_entries =
4810                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4811                 req.qp_num_l2_entries =
4812                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4813                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4814                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4815                                       &req.qpc_pg_size_qpc_lvl,
4816                                       &req.qpc_page_dir);
4817         }
4818
4819         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4820                 ctx_pg = &ctx->srq_mem;
4821                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4822                 req.srq_num_l2_entries =
4823                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4824                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4825                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4826                                       &req.srq_pg_size_srq_lvl,
4827                                       &req.srq_page_dir);
4828         }
4829
4830         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4831                 ctx_pg = &ctx->cq_mem;
4832                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4833                 req.cq_num_l2_entries =
4834                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4835                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4836                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4837                                       &req.cq_pg_size_cq_lvl,
4838                                       &req.cq_page_dir);
4839         }
4840
4841         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4842                 ctx_pg = &ctx->vnic_mem;
4843                 req.vnic_num_vnic_entries =
4844                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4845                 req.vnic_num_ring_table_entries =
4846                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4847                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4848                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4849                                       &req.vnic_pg_size_vnic_lvl,
4850                                       &req.vnic_page_dir);
4851         }
4852
4853         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4854                 ctx_pg = &ctx->stat_mem;
4855                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4856                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4857                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4858                                       &req.stat_pg_size_stat_lvl,
4859                                       &req.stat_page_dir);
4860         }
4861
4862         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4863         num_entries = &req.tqm_sp_num_entries;
4864         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4865         pg_dir = &req.tqm_sp_page_dir;
4866         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4867         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4868                 if (!(enables & ena))
4869                         continue;
4870
4871                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4872
4873                 ctx_pg = ctx->tqm_mem[i];
4874                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4875                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4876         }
4877
4878         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4879         HWRM_CHECK_RESULT();
4880         HWRM_UNLOCK();
4881
4882         return rc;
4883 }
4884
4885 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4886 {
4887         struct hwrm_port_qstats_ext_input req = {0};
4888         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4889         struct bnxt_pf_info *pf = bp->pf;
4890         int rc;
4891
4892         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4893               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4894                 return 0;
4895
4896         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4897
4898         req.port_id = rte_cpu_to_le_16(pf->port_id);
4899         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4900                 req.tx_stat_host_addr =
4901                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4902                 req.tx_stat_size =
4903                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4904         }
4905         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4906                 req.rx_stat_host_addr =
4907                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4908                 req.rx_stat_size =
4909                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4910         }
4911         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4912
4913         if (rc) {
4914                 bp->fw_rx_port_stats_ext_size = 0;
4915                 bp->fw_tx_port_stats_ext_size = 0;
4916         } else {
4917                 bp->fw_rx_port_stats_ext_size =
4918                         rte_le_to_cpu_16(resp->rx_stat_size);
4919                 bp->fw_tx_port_stats_ext_size =
4920                         rte_le_to_cpu_16(resp->tx_stat_size);
4921         }
4922
4923         HWRM_CHECK_RESULT();
4924         HWRM_UNLOCK();
4925
4926         return rc;
4927 }
4928
4929 int
4930 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4931 {
4932         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4933         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4934                 bp->hwrm_cmd_resp_addr;
4935         int rc = 0;
4936
4937         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4938         req.tunnel_type = type;
4939         req.dest_fid = bp->fw_fid;
4940         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4941         HWRM_CHECK_RESULT();
4942
4943         HWRM_UNLOCK();
4944
4945         return rc;
4946 }
4947
4948 int
4949 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4950 {
4951         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4952         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4953                 bp->hwrm_cmd_resp_addr;
4954         int rc = 0;
4955
4956         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4957         req.tunnel_type = type;
4958         req.dest_fid = bp->fw_fid;
4959         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4960         HWRM_CHECK_RESULT();
4961
4962         HWRM_UNLOCK();
4963
4964         return rc;
4965 }
4966
4967 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4968 {
4969         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4970         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4971                 bp->hwrm_cmd_resp_addr;
4972         int rc = 0;
4973
4974         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4975         req.src_fid = bp->fw_fid;
4976         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4977         HWRM_CHECK_RESULT();
4978
4979         if (type)
4980                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4981
4982         HWRM_UNLOCK();
4983
4984         return rc;
4985 }
4986
4987 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4988                                    uint16_t *dst_fid)
4989 {
4990         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4991         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4992                 bp->hwrm_cmd_resp_addr;
4993         int rc = 0;
4994
4995         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4996         req.src_fid = bp->fw_fid;
4997         req.tunnel_type = tun_type;
4998         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4999         HWRM_CHECK_RESULT();
5000
5001         if (dst_fid)
5002                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5003
5004         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5005
5006         HWRM_UNLOCK();
5007
5008         return rc;
5009 }
5010
5011 int bnxt_hwrm_set_mac(struct bnxt *bp)
5012 {
5013         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5014         struct hwrm_func_vf_cfg_input req = {0};
5015         int rc = 0;
5016
5017         if (!BNXT_VF(bp))
5018                 return 0;
5019
5020         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5021
5022         req.enables =
5023                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5024         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5025
5026         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5027
5028         HWRM_CHECK_RESULT();
5029
5030         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5031         HWRM_UNLOCK();
5032
5033         return rc;
5034 }
5035
5036 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5037 {
5038         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5039         struct hwrm_func_drv_if_change_input req = {0};
5040         uint32_t flags;
5041         int rc;
5042
5043         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5044                 return 0;
5045
5046         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5047          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5048          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5049          */
5050         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5051                 return 0;
5052
5053         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5054
5055         if (up)
5056                 req.flags =
5057                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5058
5059         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5060
5061         HWRM_CHECK_RESULT();
5062         flags = rte_le_to_cpu_32(resp->flags);
5063         HWRM_UNLOCK();
5064
5065         if (!up)
5066                 return 0;
5067
5068         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5069                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5070                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5071         }
5072
5073         return 0;
5074 }
5075
5076 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5077 {
5078         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5079         struct bnxt_error_recovery_info *info = bp->recovery_info;
5080         struct hwrm_error_recovery_qcfg_input req = {0};
5081         uint32_t flags = 0;
5082         unsigned int i;
5083         int rc;
5084
5085         /* Older FW does not have error recovery support */
5086         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5087                 return 0;
5088
5089         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5090
5091         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5092
5093         HWRM_CHECK_RESULT();
5094
5095         flags = rte_le_to_cpu_32(resp->flags);
5096         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5097                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5098         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5099                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5100
5101         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5102             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5103                 rc = -EINVAL;
5104                 goto err;
5105         }
5106
5107         /* FW returned values are in units of 100msec */
5108         info->driver_polling_freq =
5109                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5110         info->master_func_wait_period =
5111                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5112         info->normal_func_wait_period =
5113                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5114         info->master_func_wait_period_after_reset =
5115                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5116         info->max_bailout_time_after_reset =
5117                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5118         info->status_regs[BNXT_FW_STATUS_REG] =
5119                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5120         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5121                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5122         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5123                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5124         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5125                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5126         info->reg_array_cnt =
5127                 rte_le_to_cpu_32(resp->reg_array_cnt);
5128
5129         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5130                 rc = -EINVAL;
5131                 goto err;
5132         }
5133
5134         for (i = 0; i < info->reg_array_cnt; i++) {
5135                 info->reset_reg[i] =
5136                         rte_le_to_cpu_32(resp->reset_reg[i]);
5137                 info->reset_reg_val[i] =
5138                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5139                 info->delay_after_reset[i] =
5140                         resp->delay_after_reset[i];
5141         }
5142 err:
5143         HWRM_UNLOCK();
5144
5145         /* Map the FW status registers */
5146         if (!rc)
5147                 rc = bnxt_map_fw_health_status_regs(bp);
5148
5149         if (rc) {
5150                 rte_free(bp->recovery_info);
5151                 bp->recovery_info = NULL;
5152         }
5153         return rc;
5154 }
5155
5156 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5157 {
5158         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5159         struct hwrm_fw_reset_input req = {0};
5160         int rc;
5161
5162         if (!BNXT_PF(bp))
5163                 return -EOPNOTSUPP;
5164
5165         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5166
5167         req.embedded_proc_type =
5168                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5169         req.selfrst_status =
5170                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5171         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5172
5173         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5174                                     BNXT_USE_KONG(bp));
5175
5176         HWRM_CHECK_RESULT();
5177         HWRM_UNLOCK();
5178
5179         return rc;
5180 }
5181
5182 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5183 {
5184         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5185         struct hwrm_port_ts_query_input req = {0};
5186         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5187         uint32_t flags = 0;
5188         int rc;
5189
5190         if (!ptp)
5191                 return 0;
5192
5193         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5194
5195         switch (path) {
5196         case BNXT_PTP_FLAGS_PATH_TX:
5197                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5198                 break;
5199         case BNXT_PTP_FLAGS_PATH_RX:
5200                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5201                 break;
5202         case BNXT_PTP_FLAGS_CURRENT_TIME:
5203                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5204                 break;
5205         }
5206
5207         req.flags = rte_cpu_to_le_32(flags);
5208         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5209
5210         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5211
5212         HWRM_CHECK_RESULT();
5213
5214         if (timestamp) {
5215                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5216                 *timestamp |=
5217                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5218         }
5219         HWRM_UNLOCK();
5220
5221         return rc;
5222 }
5223
5224 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5225 {
5226         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5227                                         bp->hwrm_cmd_resp_addr;
5228         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5229         uint32_t flags = 0;
5230         int rc = 0;
5231
5232         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5233                 return rc;
5234
5235         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5236                 PMD_DRV_LOG(DEBUG,
5237                             "Not a PF or trusted VF. Command not supported\n");
5238                 return 0;
5239         }
5240
5241         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5242         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5243
5244         HWRM_CHECK_RESULT();
5245         flags = rte_le_to_cpu_32(resp->flags);
5246         HWRM_UNLOCK();
5247
5248         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5249                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5250                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5251         }
5252
5253         return rc;
5254 }
5255
5256 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5257 {
5258         int rc = 0;
5259
5260         struct hwrm_cfa_counter_qcaps_input req = {0};
5261         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5262
5263         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5264                 PMD_DRV_LOG(DEBUG,
5265                             "Not a PF or trusted VF. Command not supported\n");
5266                 return 0;
5267         }
5268
5269         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5270         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5271         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5272
5273         HWRM_CHECK_RESULT();
5274         if (max_fc)
5275                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5276         HWRM_UNLOCK();
5277
5278         return 0;
5279 }
5280
5281 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5282 {
5283         int rc = 0;
5284         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5285         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5286
5287         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5288                 PMD_DRV_LOG(DEBUG,
5289                             "Not a PF or trusted VF. Command not supported\n");
5290                 return 0;
5291         }
5292
5293         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5294
5295         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5296         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5297         req.page_dir = rte_cpu_to_le_64(dma_addr);
5298
5299         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5300
5301         HWRM_CHECK_RESULT();
5302         if (ctx_id) {
5303                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5304                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5305         }
5306         HWRM_UNLOCK();
5307
5308         return 0;
5309 }
5310
5311 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5312 {
5313         int rc = 0;
5314         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5315         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5316
5317         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5318                 PMD_DRV_LOG(DEBUG,
5319                             "Not a PF or trusted VF. Command not supported\n");
5320                 return 0;
5321         }
5322
5323         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5324
5325         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5326
5327         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5328
5329         HWRM_CHECK_RESULT();
5330         HWRM_UNLOCK();
5331
5332         return rc;
5333 }
5334
5335 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5336                               uint16_t cntr, uint16_t ctx_id,
5337                               uint32_t num_entries, bool enable)
5338 {
5339         struct hwrm_cfa_counter_cfg_input req = {0};
5340         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5341         uint16_t flags = 0;
5342         int rc;
5343
5344         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5345                 PMD_DRV_LOG(DEBUG,
5346                             "Not a PF or trusted VF. Command not supported\n");
5347                 return 0;
5348         }
5349
5350         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5351
5352         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5353         req.counter_type = rte_cpu_to_le_16(cntr);
5354         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5355                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5356         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5357         if (dir == BNXT_DIR_RX)
5358                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5359         else if (dir == BNXT_DIR_TX)
5360                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5361         req.flags = rte_cpu_to_le_16(flags);
5362         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5363         req.num_entries = rte_cpu_to_le_32(num_entries);
5364
5365         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5366         HWRM_CHECK_RESULT();
5367         HWRM_UNLOCK();
5368
5369         return 0;
5370 }
5371
5372 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5373                                  enum bnxt_flow_dir dir,
5374                                  uint16_t cntr,
5375                                  uint16_t num_entries)
5376 {
5377         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5378         struct hwrm_cfa_counter_qstats_input req = {0};
5379         uint16_t flow_ctx_id = 0;
5380         uint16_t flags = 0;
5381         int rc = 0;
5382
5383         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5384                 PMD_DRV_LOG(DEBUG,
5385                             "Not a PF or trusted VF. Command not supported\n");
5386                 return 0;
5387         }
5388
5389         if (dir == BNXT_DIR_RX) {
5390                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5391                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5392         } else if (dir == BNXT_DIR_TX) {
5393                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5394                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5395         }
5396
5397         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5398         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5399         req.counter_type = rte_cpu_to_le_16(cntr);
5400         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5401         req.num_entries = rte_cpu_to_le_16(num_entries);
5402         req.flags = rte_cpu_to_le_16(flags);
5403         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5404
5405         HWRM_CHECK_RESULT();
5406         HWRM_UNLOCK();
5407
5408         return 0;
5409 }